1 /*
2 * Copyright 2019 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24 #define SWSMU_CODE_LAYER_L2
25
26 #include <linux/firmware.h>
27 #include <linux/pci.h>
28 #include <linux/i2c.h>
29 #include "amdgpu.h"
30 #include "amdgpu_dpm.h"
31 #include "amdgpu_smu.h"
32 #include "atomfirmware.h"
33 #include "amdgpu_atomfirmware.h"
34 #include "amdgpu_atombios.h"
35 #include "smu_v11_0.h"
36 #include "smu11_driver_if_sienna_cichlid.h"
37 #include "soc15_common.h"
38 #include "atom.h"
39 #include "sienna_cichlid_ppt.h"
40 #include "smu_v11_0_7_pptable.h"
41 #include "smu_v11_0_7_ppsmc.h"
42 #include "nbio/nbio_2_3_offset.h"
43 #include "nbio/nbio_2_3_sh_mask.h"
44 #include "thm/thm_11_0_2_offset.h"
45 #include "thm/thm_11_0_2_sh_mask.h"
46 #include "mp/mp_11_0_offset.h"
47 #include "mp/mp_11_0_sh_mask.h"
48
49 #include "asic_reg/mp/mp_11_0_sh_mask.h"
50 #include "amdgpu_ras.h"
51 #include "smu_cmn.h"
52
53 /*
54 * DO NOT use these for err/warn/info/debug messages.
55 * Use dev_err, dev_warn, dev_info and dev_dbg instead.
56 * They are more MGPU friendly.
57 */
58 #undef pr_err
59 #undef pr_warn
60 #undef pr_info
61 #undef pr_debug
62
63 #define FEATURE_MASK(feature) (1ULL << feature)
64 #define SMC_DPM_FEATURE ( \
65 FEATURE_MASK(FEATURE_DPM_PREFETCHER_BIT) | \
66 FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT) | \
67 FEATURE_MASK(FEATURE_DPM_UCLK_BIT) | \
68 FEATURE_MASK(FEATURE_DPM_LINK_BIT) | \
69 FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT) | \
70 FEATURE_MASK(FEATURE_DPM_FCLK_BIT) | \
71 FEATURE_MASK(FEATURE_DPM_DCEFCLK_BIT) | \
72 FEATURE_MASK(FEATURE_DPM_MP0CLK_BIT))
73
74 #define SMU_11_0_7_GFX_BUSY_THRESHOLD 15
75
76 #define GET_PPTABLE_MEMBER(field, member) \
77 do { \
78 if (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) == \
79 IP_VERSION(11, 0, 13)) \
80 (*member) = (smu->smu_table.driver_pptable + \
81 offsetof(PPTable_beige_goby_t, field)); \
82 else \
83 (*member) = (smu->smu_table.driver_pptable + \
84 offsetof(PPTable_t, field)); \
85 } while (0)
86
87 /* STB FIFO depth is in 64bit units */
88 #define SIENNA_CICHLID_STB_DEPTH_UNIT_BYTES 8
89
90 /*
91 * SMU support ECCTABLE since version 58.70.0,
92 * use this to check whether ECCTABLE feature is supported.
93 */
94 #define SUPPORT_ECCTABLE_SMU_VERSION 0x003a4600
95
get_table_size(struct smu_context * smu)96 static int get_table_size(struct smu_context *smu)
97 {
98 if (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) == IP_VERSION(11, 0, 13))
99 return sizeof(PPTable_beige_goby_t);
100 else
101 return sizeof(PPTable_t);
102 }
103
104 static struct cmn2asic_msg_mapping sienna_cichlid_message_map[SMU_MSG_MAX_COUNT] = {
105 MSG_MAP(TestMessage, PPSMC_MSG_TestMessage, 1),
106 MSG_MAP(GetSmuVersion, PPSMC_MSG_GetSmuVersion, 1),
107 MSG_MAP(GetDriverIfVersion, PPSMC_MSG_GetDriverIfVersion, 1),
108 MSG_MAP(SetAllowedFeaturesMaskLow, PPSMC_MSG_SetAllowedFeaturesMaskLow, 0),
109 MSG_MAP(SetAllowedFeaturesMaskHigh, PPSMC_MSG_SetAllowedFeaturesMaskHigh, 0),
110 MSG_MAP(EnableAllSmuFeatures, PPSMC_MSG_EnableAllSmuFeatures, 0),
111 MSG_MAP(DisableAllSmuFeatures, PPSMC_MSG_DisableAllSmuFeatures, 0),
112 MSG_MAP(EnableSmuFeaturesLow, PPSMC_MSG_EnableSmuFeaturesLow, 1),
113 MSG_MAP(EnableSmuFeaturesHigh, PPSMC_MSG_EnableSmuFeaturesHigh, 1),
114 MSG_MAP(DisableSmuFeaturesLow, PPSMC_MSG_DisableSmuFeaturesLow, 1),
115 MSG_MAP(DisableSmuFeaturesHigh, PPSMC_MSG_DisableSmuFeaturesHigh, 1),
116 MSG_MAP(GetEnabledSmuFeaturesLow, PPSMC_MSG_GetRunningSmuFeaturesLow, 1),
117 MSG_MAP(GetEnabledSmuFeaturesHigh, PPSMC_MSG_GetRunningSmuFeaturesHigh, 1),
118 MSG_MAP(SetWorkloadMask, PPSMC_MSG_SetWorkloadMask, 1),
119 MSG_MAP(SetPptLimit, PPSMC_MSG_SetPptLimit, 0),
120 MSG_MAP(SetDriverDramAddrHigh, PPSMC_MSG_SetDriverDramAddrHigh, 1),
121 MSG_MAP(SetDriverDramAddrLow, PPSMC_MSG_SetDriverDramAddrLow, 1),
122 MSG_MAP(SetToolsDramAddrHigh, PPSMC_MSG_SetToolsDramAddrHigh, 0),
123 MSG_MAP(SetToolsDramAddrLow, PPSMC_MSG_SetToolsDramAddrLow, 0),
124 MSG_MAP(TransferTableSmu2Dram, PPSMC_MSG_TransferTableSmu2Dram, 1),
125 MSG_MAP(TransferTableDram2Smu, PPSMC_MSG_TransferTableDram2Smu, 0),
126 MSG_MAP(UseDefaultPPTable, PPSMC_MSG_UseDefaultPPTable, 0),
127 MSG_MAP(RunDcBtc, PPSMC_MSG_RunDcBtc, 0),
128 MSG_MAP(EnterBaco, PPSMC_MSG_EnterBaco, 0),
129 MSG_MAP(SetSoftMinByFreq, PPSMC_MSG_SetSoftMinByFreq, 1),
130 MSG_MAP(SetSoftMaxByFreq, PPSMC_MSG_SetSoftMaxByFreq, 1),
131 MSG_MAP(SetHardMinByFreq, PPSMC_MSG_SetHardMinByFreq, 1),
132 MSG_MAP(SetHardMaxByFreq, PPSMC_MSG_SetHardMaxByFreq, 0),
133 MSG_MAP(GetMinDpmFreq, PPSMC_MSG_GetMinDpmFreq, 1),
134 MSG_MAP(GetMaxDpmFreq, PPSMC_MSG_GetMaxDpmFreq, 1),
135 MSG_MAP(GetDpmFreqByIndex, PPSMC_MSG_GetDpmFreqByIndex, 1),
136 MSG_MAP(SetGeminiMode, PPSMC_MSG_SetGeminiMode, 0),
137 MSG_MAP(SetGeminiApertureHigh, PPSMC_MSG_SetGeminiApertureHigh, 0),
138 MSG_MAP(SetGeminiApertureLow, PPSMC_MSG_SetGeminiApertureLow, 0),
139 MSG_MAP(OverridePcieParameters, PPSMC_MSG_OverridePcieParameters, 0),
140 MSG_MAP(ReenableAcDcInterrupt, PPSMC_MSG_ReenableAcDcInterrupt, 0),
141 MSG_MAP(NotifyPowerSource, PPSMC_MSG_NotifyPowerSource, 0),
142 MSG_MAP(SetUclkFastSwitch, PPSMC_MSG_SetUclkFastSwitch, 0),
143 MSG_MAP(SetVideoFps, PPSMC_MSG_SetVideoFps, 0),
144 MSG_MAP(PrepareMp1ForUnload, PPSMC_MSG_PrepareMp1ForUnload, 1),
145 MSG_MAP(AllowGfxOff, PPSMC_MSG_AllowGfxOff, 0),
146 MSG_MAP(DisallowGfxOff, PPSMC_MSG_DisallowGfxOff, 0),
147 MSG_MAP(GetPptLimit, PPSMC_MSG_GetPptLimit, 0),
148 MSG_MAP(GetDcModeMaxDpmFreq, PPSMC_MSG_GetDcModeMaxDpmFreq, 1),
149 MSG_MAP(ExitBaco, PPSMC_MSG_ExitBaco, 0),
150 MSG_MAP(PowerUpVcn, PPSMC_MSG_PowerUpVcn, 0),
151 MSG_MAP(PowerDownVcn, PPSMC_MSG_PowerDownVcn, 0),
152 MSG_MAP(PowerUpJpeg, PPSMC_MSG_PowerUpJpeg, 0),
153 MSG_MAP(PowerDownJpeg, PPSMC_MSG_PowerDownJpeg, 0),
154 MSG_MAP(BacoAudioD3PME, PPSMC_MSG_BacoAudioD3PME, 0),
155 MSG_MAP(ArmD3, PPSMC_MSG_ArmD3, 0),
156 MSG_MAP(Mode1Reset, PPSMC_MSG_Mode1Reset, 0),
157 MSG_MAP(SetMGpuFanBoostLimitRpm, PPSMC_MSG_SetMGpuFanBoostLimitRpm, 0),
158 MSG_MAP(SetGpoFeaturePMask, PPSMC_MSG_SetGpoFeaturePMask, 0),
159 MSG_MAP(DisallowGpo, PPSMC_MSG_DisallowGpo, 0),
160 MSG_MAP(Enable2ndUSB20Port, PPSMC_MSG_Enable2ndUSB20Port, 0),
161 MSG_MAP(DriverMode2Reset, PPSMC_MSG_DriverMode2Reset, 0),
162 };
163
164 static struct cmn2asic_mapping sienna_cichlid_clk_map[SMU_CLK_COUNT] = {
165 CLK_MAP(GFXCLK, PPCLK_GFXCLK),
166 CLK_MAP(SCLK, PPCLK_GFXCLK),
167 CLK_MAP(SOCCLK, PPCLK_SOCCLK),
168 CLK_MAP(FCLK, PPCLK_FCLK),
169 CLK_MAP(UCLK, PPCLK_UCLK),
170 CLK_MAP(MCLK, PPCLK_UCLK),
171 CLK_MAP(DCLK, PPCLK_DCLK_0),
172 CLK_MAP(DCLK1, PPCLK_DCLK_1),
173 CLK_MAP(VCLK, PPCLK_VCLK_0),
174 CLK_MAP(VCLK1, PPCLK_VCLK_1),
175 CLK_MAP(DCEFCLK, PPCLK_DCEFCLK),
176 CLK_MAP(DISPCLK, PPCLK_DISPCLK),
177 CLK_MAP(PIXCLK, PPCLK_PIXCLK),
178 CLK_MAP(PHYCLK, PPCLK_PHYCLK),
179 };
180
181 static struct cmn2asic_mapping sienna_cichlid_feature_mask_map[SMU_FEATURE_COUNT] = {
182 FEA_MAP(DPM_PREFETCHER),
183 FEA_MAP(DPM_GFXCLK),
184 FEA_MAP(DPM_GFX_GPO),
185 FEA_MAP(DPM_UCLK),
186 FEA_MAP(DPM_FCLK),
187 FEA_MAP(DPM_SOCCLK),
188 FEA_MAP(DPM_MP0CLK),
189 FEA_MAP(DPM_LINK),
190 FEA_MAP(DPM_DCEFCLK),
191 FEA_MAP(DPM_XGMI),
192 FEA_MAP(MEM_VDDCI_SCALING),
193 FEA_MAP(MEM_MVDD_SCALING),
194 FEA_MAP(DS_GFXCLK),
195 FEA_MAP(DS_SOCCLK),
196 FEA_MAP(DS_FCLK),
197 FEA_MAP(DS_LCLK),
198 FEA_MAP(DS_DCEFCLK),
199 FEA_MAP(DS_UCLK),
200 FEA_MAP(GFX_ULV),
201 FEA_MAP(FW_DSTATE),
202 FEA_MAP(GFXOFF),
203 FEA_MAP(BACO),
204 FEA_MAP(MM_DPM_PG),
205 FEA_MAP(RSMU_SMN_CG),
206 FEA_MAP(PPT),
207 FEA_MAP(TDC),
208 FEA_MAP(APCC_PLUS),
209 FEA_MAP(GTHR),
210 FEA_MAP(ACDC),
211 FEA_MAP(VR0HOT),
212 FEA_MAP(VR1HOT),
213 FEA_MAP(FW_CTF),
214 FEA_MAP(FAN_CONTROL),
215 FEA_MAP(THERMAL),
216 FEA_MAP(GFX_DCS),
217 FEA_MAP(RM),
218 FEA_MAP(LED_DISPLAY),
219 FEA_MAP(GFX_SS),
220 FEA_MAP(OUT_OF_BAND_MONITOR),
221 FEA_MAP(TEMP_DEPENDENT_VMIN),
222 FEA_MAP(MMHUB_PG),
223 FEA_MAP(ATHUB_PG),
224 FEA_MAP(APCC_DFLL),
225 };
226
227 static struct cmn2asic_mapping sienna_cichlid_table_map[SMU_TABLE_COUNT] = {
228 TAB_MAP(PPTABLE),
229 TAB_MAP(WATERMARKS),
230 TAB_MAP(AVFS_PSM_DEBUG),
231 TAB_MAP(AVFS_FUSE_OVERRIDE),
232 TAB_MAP(PMSTATUSLOG),
233 TAB_MAP(SMU_METRICS),
234 TAB_MAP(DRIVER_SMU_CONFIG),
235 TAB_MAP(ACTIVITY_MONITOR_COEFF),
236 TAB_MAP(OVERDRIVE),
237 TAB_MAP(I2C_COMMANDS),
238 TAB_MAP(PACE),
239 TAB_MAP(ECCINFO),
240 };
241
242 static struct cmn2asic_mapping sienna_cichlid_pwr_src_map[SMU_POWER_SOURCE_COUNT] = {
243 PWR_MAP(AC),
244 PWR_MAP(DC),
245 };
246
247 static struct cmn2asic_mapping sienna_cichlid_workload_map[PP_SMC_POWER_PROFILE_COUNT] = {
248 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT, WORKLOAD_PPLIB_DEFAULT_BIT),
249 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_FULLSCREEN3D, WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT),
250 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_POWERSAVING, WORKLOAD_PPLIB_POWER_SAVING_BIT),
251 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VIDEO, WORKLOAD_PPLIB_VIDEO_BIT),
252 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VR, WORKLOAD_PPLIB_VR_BIT),
253 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_COMPUTE, WORKLOAD_PPLIB_COMPUTE_BIT),
254 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_CUSTOM, WORKLOAD_PPLIB_CUSTOM_BIT),
255 };
256
257 static const uint8_t sienna_cichlid_throttler_map[] = {
258 [THROTTLER_TEMP_EDGE_BIT] = (SMU_THROTTLER_TEMP_EDGE_BIT),
259 [THROTTLER_TEMP_HOTSPOT_BIT] = (SMU_THROTTLER_TEMP_HOTSPOT_BIT),
260 [THROTTLER_TEMP_MEM_BIT] = (SMU_THROTTLER_TEMP_MEM_BIT),
261 [THROTTLER_TEMP_VR_GFX_BIT] = (SMU_THROTTLER_TEMP_VR_GFX_BIT),
262 [THROTTLER_TEMP_VR_MEM0_BIT] = (SMU_THROTTLER_TEMP_VR_MEM0_BIT),
263 [THROTTLER_TEMP_VR_MEM1_BIT] = (SMU_THROTTLER_TEMP_VR_MEM1_BIT),
264 [THROTTLER_TEMP_VR_SOC_BIT] = (SMU_THROTTLER_TEMP_VR_SOC_BIT),
265 [THROTTLER_TEMP_LIQUID0_BIT] = (SMU_THROTTLER_TEMP_LIQUID0_BIT),
266 [THROTTLER_TEMP_LIQUID1_BIT] = (SMU_THROTTLER_TEMP_LIQUID1_BIT),
267 [THROTTLER_TDC_GFX_BIT] = (SMU_THROTTLER_TDC_GFX_BIT),
268 [THROTTLER_TDC_SOC_BIT] = (SMU_THROTTLER_TDC_SOC_BIT),
269 [THROTTLER_PPT0_BIT] = (SMU_THROTTLER_PPT0_BIT),
270 [THROTTLER_PPT1_BIT] = (SMU_THROTTLER_PPT1_BIT),
271 [THROTTLER_PPT2_BIT] = (SMU_THROTTLER_PPT2_BIT),
272 [THROTTLER_PPT3_BIT] = (SMU_THROTTLER_PPT3_BIT),
273 [THROTTLER_FIT_BIT] = (SMU_THROTTLER_FIT_BIT),
274 [THROTTLER_PPM_BIT] = (SMU_THROTTLER_PPM_BIT),
275 [THROTTLER_APCC_BIT] = (SMU_THROTTLER_APCC_BIT),
276 };
277
278 static int
sienna_cichlid_get_allowed_feature_mask(struct smu_context * smu,uint32_t * feature_mask,uint32_t num)279 sienna_cichlid_get_allowed_feature_mask(struct smu_context *smu,
280 uint32_t *feature_mask, uint32_t num)
281 {
282 struct amdgpu_device *adev = smu->adev;
283
284 if (num > 2)
285 return -EINVAL;
286
287 memset(feature_mask, 0, sizeof(uint32_t) * num);
288
289 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_PREFETCHER_BIT)
290 | FEATURE_MASK(FEATURE_DPM_FCLK_BIT)
291 | FEATURE_MASK(FEATURE_DPM_MP0CLK_BIT)
292 | FEATURE_MASK(FEATURE_DS_SOCCLK_BIT)
293 | FEATURE_MASK(FEATURE_DS_DCEFCLK_BIT)
294 | FEATURE_MASK(FEATURE_DS_FCLK_BIT)
295 | FEATURE_MASK(FEATURE_DS_UCLK_BIT)
296 | FEATURE_MASK(FEATURE_FW_DSTATE_BIT)
297 | FEATURE_MASK(FEATURE_DF_CSTATE_BIT)
298 | FEATURE_MASK(FEATURE_RSMU_SMN_CG_BIT)
299 | FEATURE_MASK(FEATURE_GFX_SS_BIT)
300 | FEATURE_MASK(FEATURE_VR0HOT_BIT)
301 | FEATURE_MASK(FEATURE_PPT_BIT)
302 | FEATURE_MASK(FEATURE_TDC_BIT)
303 | FEATURE_MASK(FEATURE_BACO_BIT)
304 | FEATURE_MASK(FEATURE_APCC_DFLL_BIT)
305 | FEATURE_MASK(FEATURE_FW_CTF_BIT)
306 | FEATURE_MASK(FEATURE_FAN_CONTROL_BIT)
307 | FEATURE_MASK(FEATURE_THERMAL_BIT)
308 | FEATURE_MASK(FEATURE_OUT_OF_BAND_MONITOR_BIT);
309
310 if (adev->pm.pp_feature & PP_SCLK_DPM_MASK) {
311 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT);
312 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_GFX_GPO_BIT);
313 }
314
315 if ((adev->pm.pp_feature & PP_GFX_DCS_MASK) &&
316 (amdgpu_ip_version(adev, MP1_HWIP, 0) > IP_VERSION(11, 0, 7)) &&
317 !(adev->flags & AMD_IS_APU))
318 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFX_DCS_BIT);
319
320 if (adev->pm.pp_feature & PP_MCLK_DPM_MASK)
321 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_UCLK_BIT)
322 | FEATURE_MASK(FEATURE_MEM_VDDCI_SCALING_BIT)
323 | FEATURE_MASK(FEATURE_MEM_MVDD_SCALING_BIT);
324
325 if (adev->pm.pp_feature & PP_PCIE_DPM_MASK)
326 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_LINK_BIT);
327
328 if (adev->pm.pp_feature & PP_DCEFCLK_DPM_MASK)
329 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_DCEFCLK_BIT);
330
331 if (adev->pm.pp_feature & PP_SOCCLK_DPM_MASK)
332 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT);
333
334 if (adev->pm.pp_feature & PP_ULV_MASK)
335 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFX_ULV_BIT);
336
337 if (adev->pm.pp_feature & PP_SCLK_DEEP_SLEEP_MASK)
338 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DS_GFXCLK_BIT);
339
340 if (adev->pm.pp_feature & PP_GFXOFF_MASK)
341 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFXOFF_BIT);
342
343 if (smu->adev->pg_flags & AMD_PG_SUPPORT_ATHUB)
344 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_ATHUB_PG_BIT);
345
346 if (smu->adev->pg_flags & AMD_PG_SUPPORT_MMHUB)
347 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_MMHUB_PG_BIT);
348
349 if (smu->adev->pg_flags & AMD_PG_SUPPORT_VCN ||
350 smu->adev->pg_flags & AMD_PG_SUPPORT_JPEG)
351 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_MM_DPM_PG_BIT);
352
353 if (smu->dc_controlled_by_gpio)
354 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_ACDC_BIT);
355
356 if (amdgpu_device_should_use_aspm(adev))
357 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DS_LCLK_BIT);
358
359 return 0;
360 }
361
sienna_cichlid_check_bxco_support(struct smu_context * smu)362 static void sienna_cichlid_check_bxco_support(struct smu_context *smu)
363 {
364 struct smu_table_context *table_context = &smu->smu_table;
365 struct smu_11_0_7_powerplay_table *powerplay_table =
366 table_context->power_play_table;
367 struct smu_baco_context *smu_baco = &smu->smu_baco;
368 struct amdgpu_device *adev = smu->adev;
369 uint32_t val;
370
371 if (powerplay_table->platform_caps & SMU_11_0_7_PP_PLATFORM_CAP_BACO) {
372 val = RREG32_SOC15(NBIO, 0, mmRCC_BIF_STRAP0);
373 smu_baco->platform_support =
374 (val & RCC_BIF_STRAP0__STRAP_PX_CAPABLE_MASK) ? true :
375 false;
376
377 /*
378 * Disable BACO entry/exit completely on below SKUs to
379 * avoid hardware intermittent failures.
380 */
381 if (((adev->pdev->device == 0x73A1) &&
382 (adev->pdev->revision == 0x00)) ||
383 ((adev->pdev->device == 0x73BF) &&
384 (adev->pdev->revision == 0xCF)) ||
385 ((adev->pdev->device == 0x7422) &&
386 (adev->pdev->revision == 0x00)) ||
387 ((adev->pdev->device == 0x73A3) &&
388 (adev->pdev->revision == 0x00)) ||
389 ((adev->pdev->device == 0x73E3) &&
390 (adev->pdev->revision == 0x00)))
391 smu_baco->platform_support = false;
392
393 }
394 }
395
sienna_cichlid_check_fan_support(struct smu_context * smu)396 static void sienna_cichlid_check_fan_support(struct smu_context *smu)
397 {
398 struct smu_table_context *table_context = &smu->smu_table;
399 PPTable_t *pptable = table_context->driver_pptable;
400 uint64_t features = *(uint64_t *) pptable->FeaturesToRun;
401
402 /* Fan control is not possible if PPTable has it disabled */
403 smu->adev->pm.no_fan =
404 !(features & (1ULL << FEATURE_FAN_CONTROL_BIT));
405 if (smu->adev->pm.no_fan)
406 dev_info_once(smu->adev->dev,
407 "PMFW based fan control disabled");
408 }
409
sienna_cichlid_check_powerplay_table(struct smu_context * smu)410 static int sienna_cichlid_check_powerplay_table(struct smu_context *smu)
411 {
412 struct smu_table_context *table_context = &smu->smu_table;
413 struct smu_11_0_7_powerplay_table *powerplay_table =
414 table_context->power_play_table;
415
416 if (powerplay_table->platform_caps & SMU_11_0_7_PP_PLATFORM_CAP_HARDWAREDC)
417 smu->dc_controlled_by_gpio = true;
418
419 sienna_cichlid_check_bxco_support(smu);
420 sienna_cichlid_check_fan_support(smu);
421
422 table_context->thermal_controller_type =
423 powerplay_table->thermal_controller_type;
424
425 /*
426 * Instead of having its own buffer space and get overdrive_table copied,
427 * smu->od_settings just points to the actual overdrive_table
428 */
429 smu->od_settings = &powerplay_table->overdrive_table;
430
431 return 0;
432 }
433
sienna_cichlid_append_powerplay_table(struct smu_context * smu)434 static int sienna_cichlid_append_powerplay_table(struct smu_context *smu)
435 {
436 struct atom_smc_dpm_info_v4_9 *smc_dpm_table;
437 int index, ret;
438 PPTable_beige_goby_t *ppt_beige_goby;
439 PPTable_t *ppt;
440
441 if (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) == IP_VERSION(11, 0, 13))
442 ppt_beige_goby = smu->smu_table.driver_pptable;
443 else
444 ppt = smu->smu_table.driver_pptable;
445
446 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
447 smc_dpm_info);
448
449 ret = amdgpu_atombios_get_data_table(smu->adev, index, NULL, NULL, NULL,
450 (uint8_t **)&smc_dpm_table);
451 if (ret)
452 return ret;
453
454 if (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) == IP_VERSION(11, 0, 13))
455 smu_memcpy_trailing(ppt_beige_goby, I2cControllers, BoardReserved,
456 smc_dpm_table, I2cControllers);
457 else
458 smu_memcpy_trailing(ppt, I2cControllers, BoardReserved,
459 smc_dpm_table, I2cControllers);
460
461 return 0;
462 }
463
sienna_cichlid_store_powerplay_table(struct smu_context * smu)464 static int sienna_cichlid_store_powerplay_table(struct smu_context *smu)
465 {
466 struct smu_table_context *table_context = &smu->smu_table;
467 struct smu_11_0_7_powerplay_table *powerplay_table =
468 table_context->power_play_table;
469 int table_size;
470
471 table_size = get_table_size(smu);
472 memcpy(table_context->driver_pptable, &powerplay_table->smc_pptable,
473 table_size);
474
475 return 0;
476 }
477
sienna_cichlid_patch_pptable_quirk(struct smu_context * smu)478 static int sienna_cichlid_patch_pptable_quirk(struct smu_context *smu)
479 {
480 struct amdgpu_device *adev = smu->adev;
481 uint32_t *board_reserved;
482 uint16_t *freq_table_gfx;
483 uint32_t i;
484
485 /* Fix some OEM SKU specific stability issues */
486 GET_PPTABLE_MEMBER(BoardReserved, &board_reserved);
487 if ((adev->pdev->device == 0x73DF) &&
488 (adev->pdev->revision == 0XC3) &&
489 (adev->pdev->subsystem_device == 0x16C2) &&
490 (adev->pdev->subsystem_vendor == 0x1043))
491 board_reserved[0] = 1387;
492
493 GET_PPTABLE_MEMBER(FreqTableGfx, &freq_table_gfx);
494 if ((adev->pdev->device == 0x73DF) &&
495 (adev->pdev->revision == 0XC3) &&
496 ((adev->pdev->subsystem_device == 0x16C2) ||
497 (adev->pdev->subsystem_device == 0x133C)) &&
498 (adev->pdev->subsystem_vendor == 0x1043)) {
499 for (i = 0; i < NUM_GFXCLK_DPM_LEVELS; i++) {
500 if (freq_table_gfx[i] > 2500)
501 freq_table_gfx[i] = 2500;
502 }
503 }
504
505 return 0;
506 }
507
sienna_cichlid_setup_pptable(struct smu_context * smu)508 static int sienna_cichlid_setup_pptable(struct smu_context *smu)
509 {
510 int ret = 0;
511
512 ret = smu_v11_0_setup_pptable(smu);
513 if (ret)
514 return ret;
515
516 ret = sienna_cichlid_store_powerplay_table(smu);
517 if (ret)
518 return ret;
519
520 ret = sienna_cichlid_append_powerplay_table(smu);
521 if (ret)
522 return ret;
523
524 ret = sienna_cichlid_check_powerplay_table(smu);
525 if (ret)
526 return ret;
527
528 return sienna_cichlid_patch_pptable_quirk(smu);
529 }
530
sienna_cichlid_tables_init(struct smu_context * smu)531 static int sienna_cichlid_tables_init(struct smu_context *smu)
532 {
533 struct smu_table_context *smu_table = &smu->smu_table;
534 struct smu_table *tables = smu_table->tables;
535 int table_size;
536
537 table_size = get_table_size(smu);
538 SMU_TABLE_INIT(tables, SMU_TABLE_PPTABLE, table_size,
539 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
540 SMU_TABLE_INIT(tables, SMU_TABLE_WATERMARKS, sizeof(Watermarks_t),
541 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
542 SMU_TABLE_INIT(tables, SMU_TABLE_SMU_METRICS, sizeof(SmuMetricsExternal_t),
543 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
544 SMU_TABLE_INIT(tables, SMU_TABLE_I2C_COMMANDS, sizeof(SwI2cRequest_t),
545 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
546 SMU_TABLE_INIT(tables, SMU_TABLE_OVERDRIVE, sizeof(OverDriveTable_t),
547 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
548 SMU_TABLE_INIT(tables, SMU_TABLE_PMSTATUSLOG, SMU11_TOOL_SIZE,
549 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
550 SMU_TABLE_INIT(tables, SMU_TABLE_ACTIVITY_MONITOR_COEFF,
551 sizeof(DpmActivityMonitorCoeffIntExternal_t), PAGE_SIZE,
552 AMDGPU_GEM_DOMAIN_VRAM);
553 SMU_TABLE_INIT(tables, SMU_TABLE_ECCINFO, sizeof(EccInfoTable_t),
554 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
555 SMU_TABLE_INIT(tables, SMU_TABLE_DRIVER_SMU_CONFIG, sizeof(DriverSmuConfigExternal_t),
556 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
557
558 smu_table->metrics_table = kzalloc(sizeof(SmuMetricsExternal_t), GFP_KERNEL);
559 if (!smu_table->metrics_table)
560 goto err0_out;
561 smu_table->metrics_time = 0;
562
563 smu_table->gpu_metrics_table_size = sizeof(struct gpu_metrics_v1_3);
564 smu_table->gpu_metrics_table = kzalloc(smu_table->gpu_metrics_table_size, GFP_KERNEL);
565 if (!smu_table->gpu_metrics_table)
566 goto err1_out;
567
568 smu_table->watermarks_table = kzalloc(sizeof(Watermarks_t), GFP_KERNEL);
569 if (!smu_table->watermarks_table)
570 goto err2_out;
571
572 smu_table->ecc_table = kzalloc(tables[SMU_TABLE_ECCINFO].size, GFP_KERNEL);
573 if (!smu_table->ecc_table)
574 goto err3_out;
575
576 smu_table->driver_smu_config_table =
577 kzalloc(tables[SMU_TABLE_DRIVER_SMU_CONFIG].size, GFP_KERNEL);
578 if (!smu_table->driver_smu_config_table)
579 goto err4_out;
580
581 return 0;
582
583 err4_out:
584 kfree(smu_table->ecc_table);
585 err3_out:
586 kfree(smu_table->watermarks_table);
587 err2_out:
588 kfree(smu_table->gpu_metrics_table);
589 err1_out:
590 kfree(smu_table->metrics_table);
591 err0_out:
592 return -ENOMEM;
593 }
594
sienna_cichlid_get_throttler_status_locked(struct smu_context * smu,bool use_metrics_v3,bool use_metrics_v2)595 static uint32_t sienna_cichlid_get_throttler_status_locked(struct smu_context *smu,
596 bool use_metrics_v3,
597 bool use_metrics_v2)
598 {
599 struct smu_table_context *smu_table= &smu->smu_table;
600 SmuMetricsExternal_t *metrics_ext =
601 (SmuMetricsExternal_t *)(smu_table->metrics_table);
602 uint32_t throttler_status = 0;
603 int i;
604
605 if (use_metrics_v3) {
606 for (i = 0; i < THROTTLER_COUNT; i++)
607 throttler_status |=
608 (metrics_ext->SmuMetrics_V3.ThrottlingPercentage[i] ? 1U << i : 0);
609 } else if (use_metrics_v2) {
610 for (i = 0; i < THROTTLER_COUNT; i++)
611 throttler_status |=
612 (metrics_ext->SmuMetrics_V2.ThrottlingPercentage[i] ? 1U << i : 0);
613 } else {
614 throttler_status = metrics_ext->SmuMetrics.ThrottlerStatus;
615 }
616
617 return throttler_status;
618 }
619
sienna_cichlid_is_od_feature_supported(struct smu_11_0_7_overdrive_table * od_table,enum SMU_11_0_7_ODFEATURE_CAP cap)620 static bool sienna_cichlid_is_od_feature_supported(struct smu_11_0_7_overdrive_table *od_table,
621 enum SMU_11_0_7_ODFEATURE_CAP cap)
622 {
623 return od_table->cap[cap];
624 }
625
sienna_cichlid_get_power_limit(struct smu_context * smu,uint32_t * current_power_limit,uint32_t * default_power_limit,uint32_t * max_power_limit,uint32_t * min_power_limit)626 static int sienna_cichlid_get_power_limit(struct smu_context *smu,
627 uint32_t *current_power_limit,
628 uint32_t *default_power_limit,
629 uint32_t *max_power_limit,
630 uint32_t *min_power_limit)
631 {
632 struct smu_11_0_7_powerplay_table *powerplay_table =
633 (struct smu_11_0_7_powerplay_table *)smu->smu_table.power_play_table;
634 struct smu_11_0_7_overdrive_table *od_settings = smu->od_settings;
635 uint32_t power_limit, od_percent_upper = 0, od_percent_lower = 0;
636 uint16_t *table_member;
637
638 GET_PPTABLE_MEMBER(SocketPowerLimitAc, &table_member);
639
640 if (smu_v11_0_get_current_power_limit(smu, &power_limit)) {
641 power_limit =
642 table_member[PPT_THROTTLER_PPT0];
643 }
644
645 if (current_power_limit)
646 *current_power_limit = power_limit;
647 if (default_power_limit)
648 *default_power_limit = power_limit;
649
650 if (powerplay_table) {
651 if (smu->od_enabled &&
652 sienna_cichlid_is_od_feature_supported(od_settings, SMU_11_0_7_ODCAP_POWER_LIMIT)) {
653 od_percent_upper = le32_to_cpu(powerplay_table->overdrive_table.max[SMU_11_0_7_ODSETTING_POWERPERCENTAGE]);
654 od_percent_lower = le32_to_cpu(powerplay_table->overdrive_table.min[SMU_11_0_7_ODSETTING_POWERPERCENTAGE]);
655 } else if ((sienna_cichlid_is_od_feature_supported(od_settings, SMU_11_0_7_ODCAP_POWER_LIMIT))) {
656 od_percent_upper = 0;
657 od_percent_lower = le32_to_cpu(powerplay_table->overdrive_table.min[SMU_11_0_7_ODSETTING_POWERPERCENTAGE]);
658 }
659 }
660
661 dev_dbg(smu->adev->dev, "od percent upper:%d, od percent lower:%d (default power: %d)\n",
662 od_percent_upper, od_percent_lower, power_limit);
663
664 if (max_power_limit) {
665 *max_power_limit = power_limit * (100 + od_percent_upper);
666 *max_power_limit /= 100;
667 }
668
669 if (min_power_limit) {
670 *min_power_limit = power_limit * (100 - od_percent_lower);
671 *min_power_limit /= 100;
672 }
673 return 0;
674 }
675
sienna_cichlid_get_smartshift_power_percentage(struct smu_context * smu,uint32_t * apu_percent,uint32_t * dgpu_percent)676 static void sienna_cichlid_get_smartshift_power_percentage(struct smu_context *smu,
677 uint32_t *apu_percent,
678 uint32_t *dgpu_percent)
679 {
680 struct smu_table_context *smu_table = &smu->smu_table;
681 SmuMetrics_V4_t *metrics_v4 =
682 &(((SmuMetricsExternal_t *)(smu_table->metrics_table))->SmuMetrics_V4);
683 uint16_t powerRatio = 0;
684 uint16_t apu_power_limit = 0;
685 uint16_t dgpu_power_limit = 0;
686 uint32_t apu_boost = 0;
687 uint32_t dgpu_boost = 0;
688 uint32_t cur_power_limit;
689
690 if (metrics_v4->ApuSTAPMSmartShiftLimit != 0) {
691 sienna_cichlid_get_power_limit(smu, &cur_power_limit, NULL, NULL, NULL);
692 apu_power_limit = metrics_v4->ApuSTAPMLimit;
693 dgpu_power_limit = cur_power_limit;
694 powerRatio = (((apu_power_limit +
695 dgpu_power_limit) * 100) /
696 metrics_v4->ApuSTAPMSmartShiftLimit);
697 if (powerRatio > 100) {
698 apu_power_limit = (apu_power_limit * 100) /
699 powerRatio;
700 dgpu_power_limit = (dgpu_power_limit * 100) /
701 powerRatio;
702 }
703 if (metrics_v4->AverageApuSocketPower > apu_power_limit &&
704 apu_power_limit != 0) {
705 apu_boost = ((metrics_v4->AverageApuSocketPower -
706 apu_power_limit) * 100) /
707 apu_power_limit;
708 if (apu_boost > 100)
709 apu_boost = 100;
710 }
711
712 if (metrics_v4->AverageSocketPower > dgpu_power_limit &&
713 dgpu_power_limit != 0) {
714 dgpu_boost = ((metrics_v4->AverageSocketPower -
715 dgpu_power_limit) * 100) /
716 dgpu_power_limit;
717 if (dgpu_boost > 100)
718 dgpu_boost = 100;
719 }
720
721 if (dgpu_boost >= apu_boost)
722 apu_boost = 0;
723 else
724 dgpu_boost = 0;
725 }
726 *apu_percent = apu_boost;
727 *dgpu_percent = dgpu_boost;
728 }
729
sienna_cichlid_get_smu_metrics_data(struct smu_context * smu,MetricsMember_t member,uint32_t * value)730 static int sienna_cichlid_get_smu_metrics_data(struct smu_context *smu,
731 MetricsMember_t member,
732 uint32_t *value)
733 {
734 struct smu_table_context *smu_table= &smu->smu_table;
735 SmuMetrics_t *metrics =
736 &(((SmuMetricsExternal_t *)(smu_table->metrics_table))->SmuMetrics);
737 SmuMetrics_V2_t *metrics_v2 =
738 &(((SmuMetricsExternal_t *)(smu_table->metrics_table))->SmuMetrics_V2);
739 SmuMetrics_V3_t *metrics_v3 =
740 &(((SmuMetricsExternal_t *)(smu_table->metrics_table))->SmuMetrics_V3);
741 bool use_metrics_v2 = false;
742 bool use_metrics_v3 = false;
743 uint16_t average_gfx_activity;
744 int ret = 0;
745 uint32_t apu_percent = 0;
746 uint32_t dgpu_percent = 0;
747
748 switch (amdgpu_ip_version(smu->adev, MP1_HWIP, 0)) {
749 case IP_VERSION(11, 0, 7):
750 if (smu->smc_fw_version >= 0x3A4900)
751 use_metrics_v3 = true;
752 else if (smu->smc_fw_version >= 0x3A4300)
753 use_metrics_v2 = true;
754 break;
755 case IP_VERSION(11, 0, 11):
756 if (smu->smc_fw_version >= 0x412D00)
757 use_metrics_v2 = true;
758 break;
759 case IP_VERSION(11, 0, 12):
760 if (smu->smc_fw_version >= 0x3B2300)
761 use_metrics_v2 = true;
762 break;
763 case IP_VERSION(11, 0, 13):
764 if (smu->smc_fw_version >= 0x491100)
765 use_metrics_v2 = true;
766 break;
767 default:
768 break;
769 }
770
771 ret = smu_cmn_get_metrics_table(smu,
772 NULL,
773 false);
774 if (ret)
775 return ret;
776
777 switch (member) {
778 case METRICS_CURR_GFXCLK:
779 *value = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_GFXCLK] :
780 use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_GFXCLK] :
781 metrics->CurrClock[PPCLK_GFXCLK];
782 break;
783 case METRICS_CURR_SOCCLK:
784 *value = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_SOCCLK] :
785 use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_SOCCLK] :
786 metrics->CurrClock[PPCLK_SOCCLK];
787 break;
788 case METRICS_CURR_UCLK:
789 *value = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_UCLK] :
790 use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_UCLK] :
791 metrics->CurrClock[PPCLK_UCLK];
792 break;
793 case METRICS_CURR_VCLK:
794 *value = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_VCLK_0] :
795 use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_VCLK_0] :
796 metrics->CurrClock[PPCLK_VCLK_0];
797 break;
798 case METRICS_CURR_VCLK1:
799 *value = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_VCLK_1] :
800 use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_VCLK_1] :
801 metrics->CurrClock[PPCLK_VCLK_1];
802 break;
803 case METRICS_CURR_DCLK:
804 *value = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_DCLK_0] :
805 use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_DCLK_0] :
806 metrics->CurrClock[PPCLK_DCLK_0];
807 break;
808 case METRICS_CURR_DCLK1:
809 *value = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_DCLK_1] :
810 use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_DCLK_1] :
811 metrics->CurrClock[PPCLK_DCLK_1];
812 break;
813 case METRICS_CURR_DCEFCLK:
814 *value = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_DCEFCLK] :
815 use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_DCEFCLK] :
816 metrics->CurrClock[PPCLK_DCEFCLK];
817 break;
818 case METRICS_CURR_FCLK:
819 *value = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_FCLK] :
820 use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_FCLK] :
821 metrics->CurrClock[PPCLK_FCLK];
822 break;
823 case METRICS_AVERAGE_GFXCLK:
824 average_gfx_activity = use_metrics_v3 ? metrics_v3->AverageGfxActivity :
825 use_metrics_v2 ? metrics_v2->AverageGfxActivity :
826 metrics->AverageGfxActivity;
827 if (average_gfx_activity <= SMU_11_0_7_GFX_BUSY_THRESHOLD)
828 *value = use_metrics_v3 ? metrics_v3->AverageGfxclkFrequencyPostDs :
829 use_metrics_v2 ? metrics_v2->AverageGfxclkFrequencyPostDs :
830 metrics->AverageGfxclkFrequencyPostDs;
831 else
832 *value = use_metrics_v3 ? metrics_v3->AverageGfxclkFrequencyPreDs :
833 use_metrics_v2 ? metrics_v2->AverageGfxclkFrequencyPreDs :
834 metrics->AverageGfxclkFrequencyPreDs;
835 break;
836 case METRICS_AVERAGE_FCLK:
837 *value = use_metrics_v3 ? metrics_v3->AverageFclkFrequencyPostDs :
838 use_metrics_v2 ? metrics_v2->AverageFclkFrequencyPostDs :
839 metrics->AverageFclkFrequencyPostDs;
840 break;
841 case METRICS_AVERAGE_UCLK:
842 *value = use_metrics_v3 ? metrics_v3->AverageUclkFrequencyPostDs :
843 use_metrics_v2 ? metrics_v2->AverageUclkFrequencyPostDs :
844 metrics->AverageUclkFrequencyPostDs;
845 break;
846 case METRICS_AVERAGE_GFXACTIVITY:
847 *value = use_metrics_v3 ? metrics_v3->AverageGfxActivity :
848 use_metrics_v2 ? metrics_v2->AverageGfxActivity :
849 metrics->AverageGfxActivity;
850 break;
851 case METRICS_AVERAGE_MEMACTIVITY:
852 *value = use_metrics_v3 ? metrics_v3->AverageUclkActivity :
853 use_metrics_v2 ? metrics_v2->AverageUclkActivity :
854 metrics->AverageUclkActivity;
855 break;
856 case METRICS_AVERAGE_SOCKETPOWER:
857 *value = use_metrics_v3 ? metrics_v3->AverageSocketPower << 8 :
858 use_metrics_v2 ? metrics_v2->AverageSocketPower << 8 :
859 metrics->AverageSocketPower << 8;
860 break;
861 case METRICS_TEMPERATURE_EDGE:
862 *value = (use_metrics_v3 ? metrics_v3->TemperatureEdge :
863 use_metrics_v2 ? metrics_v2->TemperatureEdge :
864 metrics->TemperatureEdge) * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
865 break;
866 case METRICS_TEMPERATURE_HOTSPOT:
867 *value = (use_metrics_v3 ? metrics_v3->TemperatureHotspot :
868 use_metrics_v2 ? metrics_v2->TemperatureHotspot :
869 metrics->TemperatureHotspot) * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
870 break;
871 case METRICS_TEMPERATURE_MEM:
872 *value = (use_metrics_v3 ? metrics_v3->TemperatureMem :
873 use_metrics_v2 ? metrics_v2->TemperatureMem :
874 metrics->TemperatureMem) * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
875 break;
876 case METRICS_TEMPERATURE_VRGFX:
877 *value = (use_metrics_v3 ? metrics_v3->TemperatureVrGfx :
878 use_metrics_v2 ? metrics_v2->TemperatureVrGfx :
879 metrics->TemperatureVrGfx) * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
880 break;
881 case METRICS_TEMPERATURE_VRSOC:
882 *value = (use_metrics_v3 ? metrics_v3->TemperatureVrSoc :
883 use_metrics_v2 ? metrics_v2->TemperatureVrSoc :
884 metrics->TemperatureVrSoc) * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
885 break;
886 case METRICS_THROTTLER_STATUS:
887 *value = sienna_cichlid_get_throttler_status_locked(smu, use_metrics_v3, use_metrics_v2);
888 break;
889 case METRICS_CURR_FANSPEED:
890 *value = use_metrics_v3 ? metrics_v3->CurrFanSpeed :
891 use_metrics_v2 ? metrics_v2->CurrFanSpeed : metrics->CurrFanSpeed;
892 break;
893 case METRICS_UNIQUE_ID_UPPER32:
894 /* Only supported in 0x3A5300+, metrics_v3 requires 0x3A4900+ */
895 *value = use_metrics_v3 ? metrics_v3->PublicSerialNumUpper32 : 0;
896 break;
897 case METRICS_UNIQUE_ID_LOWER32:
898 /* Only supported in 0x3A5300+, metrics_v3 requires 0x3A4900+ */
899 *value = use_metrics_v3 ? metrics_v3->PublicSerialNumLower32 : 0;
900 break;
901 case METRICS_SS_APU_SHARE:
902 sienna_cichlid_get_smartshift_power_percentage(smu, &apu_percent, &dgpu_percent);
903 *value = apu_percent;
904 break;
905 case METRICS_SS_DGPU_SHARE:
906 sienna_cichlid_get_smartshift_power_percentage(smu, &apu_percent, &dgpu_percent);
907 *value = dgpu_percent;
908 break;
909
910 default:
911 *value = UINT_MAX;
912 break;
913 }
914
915 return ret;
916
917 }
918
sienna_cichlid_allocate_dpm_context(struct smu_context * smu)919 static int sienna_cichlid_allocate_dpm_context(struct smu_context *smu)
920 {
921 struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
922
923 smu_dpm->dpm_context = kzalloc(sizeof(struct smu_11_0_dpm_context),
924 GFP_KERNEL);
925 if (!smu_dpm->dpm_context)
926 return -ENOMEM;
927
928 smu_dpm->dpm_context_size = sizeof(struct smu_11_0_dpm_context);
929
930 return 0;
931 }
932
933 static void sienna_cichlid_stb_init(struct smu_context *smu);
934
sienna_cichlid_init_smc_tables(struct smu_context * smu)935 static int sienna_cichlid_init_smc_tables(struct smu_context *smu)
936 {
937 struct amdgpu_device *adev = smu->adev;
938 int ret = 0;
939
940 ret = sienna_cichlid_tables_init(smu);
941 if (ret)
942 return ret;
943
944 ret = sienna_cichlid_allocate_dpm_context(smu);
945 if (ret)
946 return ret;
947
948 if (!amdgpu_sriov_vf(adev))
949 sienna_cichlid_stb_init(smu);
950
951 return smu_v11_0_init_smc_tables(smu);
952 }
953
sienna_cichlid_set_default_dpm_table(struct smu_context * smu)954 static int sienna_cichlid_set_default_dpm_table(struct smu_context *smu)
955 {
956 struct smu_11_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;
957 struct smu_11_0_dpm_table *dpm_table;
958 struct amdgpu_device *adev = smu->adev;
959 int i, ret = 0;
960 DpmDescriptor_t *table_member;
961
962 /* socclk dpm table setup */
963 dpm_table = &dpm_context->dpm_tables.soc_table;
964 GET_PPTABLE_MEMBER(DpmDescriptor, &table_member);
965 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
966 ret = smu_v11_0_set_single_dpm_table(smu,
967 SMU_SOCCLK,
968 dpm_table);
969 if (ret)
970 return ret;
971 dpm_table->is_fine_grained =
972 !table_member[PPCLK_SOCCLK].SnapToDiscrete;
973 } else {
974 dpm_table->count = 1;
975 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.socclk / 100;
976 dpm_table->dpm_levels[0].enabled = true;
977 dpm_table->min = dpm_table->dpm_levels[0].value;
978 dpm_table->max = dpm_table->dpm_levels[0].value;
979 }
980
981 /* gfxclk dpm table setup */
982 dpm_table = &dpm_context->dpm_tables.gfx_table;
983 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT)) {
984 ret = smu_v11_0_set_single_dpm_table(smu,
985 SMU_GFXCLK,
986 dpm_table);
987 if (ret)
988 return ret;
989 dpm_table->is_fine_grained =
990 !table_member[PPCLK_GFXCLK].SnapToDiscrete;
991 } else {
992 dpm_table->count = 1;
993 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.gfxclk / 100;
994 dpm_table->dpm_levels[0].enabled = true;
995 dpm_table->min = dpm_table->dpm_levels[0].value;
996 dpm_table->max = dpm_table->dpm_levels[0].value;
997 }
998
999 /* uclk dpm table setup */
1000 dpm_table = &dpm_context->dpm_tables.uclk_table;
1001 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
1002 ret = smu_v11_0_set_single_dpm_table(smu,
1003 SMU_UCLK,
1004 dpm_table);
1005 if (ret)
1006 return ret;
1007 dpm_table->is_fine_grained =
1008 !table_member[PPCLK_UCLK].SnapToDiscrete;
1009 } else {
1010 dpm_table->count = 1;
1011 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.uclk / 100;
1012 dpm_table->dpm_levels[0].enabled = true;
1013 dpm_table->min = dpm_table->dpm_levels[0].value;
1014 dpm_table->max = dpm_table->dpm_levels[0].value;
1015 }
1016
1017 /* fclk dpm table setup */
1018 dpm_table = &dpm_context->dpm_tables.fclk_table;
1019 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_FCLK_BIT)) {
1020 ret = smu_v11_0_set_single_dpm_table(smu,
1021 SMU_FCLK,
1022 dpm_table);
1023 if (ret)
1024 return ret;
1025 dpm_table->is_fine_grained =
1026 !table_member[PPCLK_FCLK].SnapToDiscrete;
1027 } else {
1028 dpm_table->count = 1;
1029 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.fclk / 100;
1030 dpm_table->dpm_levels[0].enabled = true;
1031 dpm_table->min = dpm_table->dpm_levels[0].value;
1032 dpm_table->max = dpm_table->dpm_levels[0].value;
1033 }
1034
1035 /* vclk0/1 dpm table setup */
1036 for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
1037 if (adev->vcn.harvest_config & (1 << i))
1038 continue;
1039
1040 dpm_table = &dpm_context->dpm_tables.vclk_table;
1041 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) {
1042 ret = smu_v11_0_set_single_dpm_table(smu,
1043 i ? SMU_VCLK1 : SMU_VCLK,
1044 dpm_table);
1045 if (ret)
1046 return ret;
1047 dpm_table->is_fine_grained =
1048 !table_member[i ? PPCLK_VCLK_1 : PPCLK_VCLK_0].SnapToDiscrete;
1049 } else {
1050 dpm_table->count = 1;
1051 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.vclk / 100;
1052 dpm_table->dpm_levels[0].enabled = true;
1053 dpm_table->min = dpm_table->dpm_levels[0].value;
1054 dpm_table->max = dpm_table->dpm_levels[0].value;
1055 }
1056 }
1057
1058 /* dclk0/1 dpm table setup */
1059 for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
1060 if (adev->vcn.harvest_config & (1 << i))
1061 continue;
1062 dpm_table = &dpm_context->dpm_tables.dclk_table;
1063 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) {
1064 ret = smu_v11_0_set_single_dpm_table(smu,
1065 i ? SMU_DCLK1 : SMU_DCLK,
1066 dpm_table);
1067 if (ret)
1068 return ret;
1069 dpm_table->is_fine_grained =
1070 !table_member[i ? PPCLK_DCLK_1 : PPCLK_DCLK_0].SnapToDiscrete;
1071 } else {
1072 dpm_table->count = 1;
1073 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dclk / 100;
1074 dpm_table->dpm_levels[0].enabled = true;
1075 dpm_table->min = dpm_table->dpm_levels[0].value;
1076 dpm_table->max = dpm_table->dpm_levels[0].value;
1077 }
1078 }
1079
1080 /* dcefclk dpm table setup */
1081 dpm_table = &dpm_context->dpm_tables.dcef_table;
1082 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
1083 ret = smu_v11_0_set_single_dpm_table(smu,
1084 SMU_DCEFCLK,
1085 dpm_table);
1086 if (ret)
1087 return ret;
1088 dpm_table->is_fine_grained =
1089 !table_member[PPCLK_DCEFCLK].SnapToDiscrete;
1090 } else {
1091 dpm_table->count = 1;
1092 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100;
1093 dpm_table->dpm_levels[0].enabled = true;
1094 dpm_table->min = dpm_table->dpm_levels[0].value;
1095 dpm_table->max = dpm_table->dpm_levels[0].value;
1096 }
1097
1098 /* pixelclk dpm table setup */
1099 dpm_table = &dpm_context->dpm_tables.pixel_table;
1100 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
1101 ret = smu_v11_0_set_single_dpm_table(smu,
1102 SMU_PIXCLK,
1103 dpm_table);
1104 if (ret)
1105 return ret;
1106 dpm_table->is_fine_grained =
1107 !table_member[PPCLK_PIXCLK].SnapToDiscrete;
1108 } else {
1109 dpm_table->count = 1;
1110 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100;
1111 dpm_table->dpm_levels[0].enabled = true;
1112 dpm_table->min = dpm_table->dpm_levels[0].value;
1113 dpm_table->max = dpm_table->dpm_levels[0].value;
1114 }
1115
1116 /* displayclk dpm table setup */
1117 dpm_table = &dpm_context->dpm_tables.display_table;
1118 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
1119 ret = smu_v11_0_set_single_dpm_table(smu,
1120 SMU_DISPCLK,
1121 dpm_table);
1122 if (ret)
1123 return ret;
1124 dpm_table->is_fine_grained =
1125 !table_member[PPCLK_DISPCLK].SnapToDiscrete;
1126 } else {
1127 dpm_table->count = 1;
1128 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100;
1129 dpm_table->dpm_levels[0].enabled = true;
1130 dpm_table->min = dpm_table->dpm_levels[0].value;
1131 dpm_table->max = dpm_table->dpm_levels[0].value;
1132 }
1133
1134 /* phyclk dpm table setup */
1135 dpm_table = &dpm_context->dpm_tables.phy_table;
1136 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
1137 ret = smu_v11_0_set_single_dpm_table(smu,
1138 SMU_PHYCLK,
1139 dpm_table);
1140 if (ret)
1141 return ret;
1142 dpm_table->is_fine_grained =
1143 !table_member[PPCLK_PHYCLK].SnapToDiscrete;
1144 } else {
1145 dpm_table->count = 1;
1146 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100;
1147 dpm_table->dpm_levels[0].enabled = true;
1148 dpm_table->min = dpm_table->dpm_levels[0].value;
1149 dpm_table->max = dpm_table->dpm_levels[0].value;
1150 }
1151
1152 return 0;
1153 }
1154
sienna_cichlid_dpm_set_vcn_enable(struct smu_context * smu,bool enable)1155 static int sienna_cichlid_dpm_set_vcn_enable(struct smu_context *smu, bool enable)
1156 {
1157 struct amdgpu_device *adev = smu->adev;
1158 int i, ret = 0;
1159
1160 for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
1161 if (adev->vcn.harvest_config & (1 << i))
1162 continue;
1163 /* vcn dpm on is a prerequisite for vcn power gate messages */
1164 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) {
1165 ret = smu_cmn_send_smc_msg_with_param(smu, enable ?
1166 SMU_MSG_PowerUpVcn : SMU_MSG_PowerDownVcn,
1167 0x10000 * i, NULL);
1168 if (ret)
1169 return ret;
1170 }
1171 }
1172
1173 return ret;
1174 }
1175
sienna_cichlid_dpm_set_jpeg_enable(struct smu_context * smu,bool enable)1176 static int sienna_cichlid_dpm_set_jpeg_enable(struct smu_context *smu, bool enable)
1177 {
1178 int ret = 0;
1179
1180 if (enable) {
1181 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) {
1182 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerUpJpeg, 0, NULL);
1183 if (ret)
1184 return ret;
1185 }
1186 } else {
1187 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) {
1188 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerDownJpeg, 0, NULL);
1189 if (ret)
1190 return ret;
1191 }
1192 }
1193
1194 return ret;
1195 }
1196
sienna_cichlid_get_current_clk_freq_by_table(struct smu_context * smu,enum smu_clk_type clk_type,uint32_t * value)1197 static int sienna_cichlid_get_current_clk_freq_by_table(struct smu_context *smu,
1198 enum smu_clk_type clk_type,
1199 uint32_t *value)
1200 {
1201 MetricsMember_t member_type;
1202 int clk_id = 0;
1203
1204 clk_id = smu_cmn_to_asic_specific_index(smu,
1205 CMN2ASIC_MAPPING_CLK,
1206 clk_type);
1207 if (clk_id < 0)
1208 return clk_id;
1209
1210 switch (clk_id) {
1211 case PPCLK_GFXCLK:
1212 member_type = METRICS_CURR_GFXCLK;
1213 break;
1214 case PPCLK_UCLK:
1215 member_type = METRICS_CURR_UCLK;
1216 break;
1217 case PPCLK_SOCCLK:
1218 member_type = METRICS_CURR_SOCCLK;
1219 break;
1220 case PPCLK_FCLK:
1221 member_type = METRICS_CURR_FCLK;
1222 break;
1223 case PPCLK_VCLK_0:
1224 member_type = METRICS_CURR_VCLK;
1225 break;
1226 case PPCLK_VCLK_1:
1227 member_type = METRICS_CURR_VCLK1;
1228 break;
1229 case PPCLK_DCLK_0:
1230 member_type = METRICS_CURR_DCLK;
1231 break;
1232 case PPCLK_DCLK_1:
1233 member_type = METRICS_CURR_DCLK1;
1234 break;
1235 case PPCLK_DCEFCLK:
1236 member_type = METRICS_CURR_DCEFCLK;
1237 break;
1238 default:
1239 return -EINVAL;
1240 }
1241
1242 return sienna_cichlid_get_smu_metrics_data(smu,
1243 member_type,
1244 value);
1245
1246 }
1247
sienna_cichlid_is_support_fine_grained_dpm(struct smu_context * smu,enum smu_clk_type clk_type)1248 static bool sienna_cichlid_is_support_fine_grained_dpm(struct smu_context *smu, enum smu_clk_type clk_type)
1249 {
1250 DpmDescriptor_t *dpm_desc = NULL;
1251 DpmDescriptor_t *table_member;
1252 uint32_t clk_index = 0;
1253
1254 GET_PPTABLE_MEMBER(DpmDescriptor, &table_member);
1255 clk_index = smu_cmn_to_asic_specific_index(smu,
1256 CMN2ASIC_MAPPING_CLK,
1257 clk_type);
1258 dpm_desc = &table_member[clk_index];
1259
1260 /* 0 - Fine grained DPM, 1 - Discrete DPM */
1261 return dpm_desc->SnapToDiscrete == 0;
1262 }
1263
sienna_cichlid_get_od_setting_range(struct smu_11_0_7_overdrive_table * od_table,enum SMU_11_0_7_ODSETTING_ID setting,uint32_t * min,uint32_t * max)1264 static void sienna_cichlid_get_od_setting_range(struct smu_11_0_7_overdrive_table *od_table,
1265 enum SMU_11_0_7_ODSETTING_ID setting,
1266 uint32_t *min, uint32_t *max)
1267 {
1268 if (min)
1269 *min = od_table->min[setting];
1270 if (max)
1271 *max = od_table->max[setting];
1272 }
1273
sienna_cichlid_print_clk_levels(struct smu_context * smu,enum smu_clk_type clk_type,char * buf)1274 static int sienna_cichlid_print_clk_levels(struct smu_context *smu,
1275 enum smu_clk_type clk_type, char *buf)
1276 {
1277 struct amdgpu_device *adev = smu->adev;
1278 struct smu_table_context *table_context = &smu->smu_table;
1279 struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
1280 struct smu_11_0_dpm_context *dpm_context = smu_dpm->dpm_context;
1281 uint16_t *table_member;
1282
1283 struct smu_11_0_7_overdrive_table *od_settings = smu->od_settings;
1284 OverDriveTable_t *od_table =
1285 (OverDriveTable_t *)table_context->overdrive_table;
1286 int i, size = 0, ret = 0;
1287 uint32_t cur_value = 0, value = 0, count = 0;
1288 uint32_t freq_values[3] = {0};
1289 uint32_t mark_index = 0;
1290 uint32_t gen_speed, lane_width;
1291 uint32_t min_value, max_value;
1292
1293 smu_cmn_get_sysfs_buf(&buf, &size);
1294
1295 switch (clk_type) {
1296 case SMU_GFXCLK:
1297 case SMU_SCLK:
1298 case SMU_SOCCLK:
1299 case SMU_MCLK:
1300 case SMU_UCLK:
1301 case SMU_FCLK:
1302 case SMU_VCLK:
1303 case SMU_VCLK1:
1304 case SMU_DCLK:
1305 case SMU_DCLK1:
1306 case SMU_DCEFCLK:
1307 ret = sienna_cichlid_get_current_clk_freq_by_table(smu, clk_type, &cur_value);
1308 if (ret)
1309 goto print_clk_out;
1310
1311 ret = smu_v11_0_get_dpm_level_count(smu, clk_type, &count);
1312 if (ret)
1313 goto print_clk_out;
1314
1315 if (!sienna_cichlid_is_support_fine_grained_dpm(smu, clk_type)) {
1316 for (i = 0; i < count; i++) {
1317 ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, i, &value);
1318 if (ret)
1319 goto print_clk_out;
1320
1321 size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n", i, value,
1322 cur_value == value ? "*" : "");
1323 }
1324 } else {
1325 ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, 0, &freq_values[0]);
1326 if (ret)
1327 goto print_clk_out;
1328 ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, count - 1, &freq_values[2]);
1329 if (ret)
1330 goto print_clk_out;
1331
1332 freq_values[1] = cur_value;
1333 mark_index = cur_value == freq_values[0] ? 0 :
1334 cur_value == freq_values[2] ? 2 : 1;
1335
1336 count = 3;
1337 if (mark_index != 1) {
1338 count = 2;
1339 freq_values[1] = freq_values[2];
1340 }
1341
1342 for (i = 0; i < count; i++) {
1343 size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n", i, freq_values[i],
1344 cur_value == freq_values[i] ? "*" : "");
1345 }
1346
1347 }
1348 break;
1349 case SMU_PCIE:
1350 gen_speed = smu_v11_0_get_current_pcie_link_speed_level(smu);
1351 lane_width = smu_v11_0_get_current_pcie_link_width_level(smu);
1352 GET_PPTABLE_MEMBER(LclkFreq, &table_member);
1353 for (i = 0; i < NUM_LINK_LEVELS; i++)
1354 size += sysfs_emit_at(buf, size, "%d: %s %s %dMhz %s\n", i,
1355 (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 0) ? "2.5GT/s," :
1356 (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 1) ? "5.0GT/s," :
1357 (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 2) ? "8.0GT/s," :
1358 (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 3) ? "16.0GT/s," : "",
1359 (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 1) ? "x1" :
1360 (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 2) ? "x2" :
1361 (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 3) ? "x4" :
1362 (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 4) ? "x8" :
1363 (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 5) ? "x12" :
1364 (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 6) ? "x16" : "",
1365 table_member[i],
1366 (gen_speed == dpm_context->dpm_tables.pcie_table.pcie_gen[i]) &&
1367 (lane_width == dpm_context->dpm_tables.pcie_table.pcie_lane[i]) ?
1368 "*" : "");
1369 break;
1370 case SMU_OD_SCLK:
1371 if (!smu->od_enabled || !od_table || !od_settings)
1372 break;
1373
1374 if (!sienna_cichlid_is_od_feature_supported(od_settings, SMU_11_0_7_ODCAP_GFXCLK_LIMITS))
1375 break;
1376
1377 size += sysfs_emit_at(buf, size, "OD_SCLK:\n");
1378 size += sysfs_emit_at(buf, size, "0: %uMhz\n1: %uMhz\n", od_table->GfxclkFmin, od_table->GfxclkFmax);
1379 break;
1380
1381 case SMU_OD_MCLK:
1382 if (!smu->od_enabled || !od_table || !od_settings)
1383 break;
1384
1385 if (!sienna_cichlid_is_od_feature_supported(od_settings, SMU_11_0_7_ODCAP_UCLK_LIMITS))
1386 break;
1387
1388 size += sysfs_emit_at(buf, size, "OD_MCLK:\n");
1389 size += sysfs_emit_at(buf, size, "0: %uMhz\n1: %uMHz\n", od_table->UclkFmin, od_table->UclkFmax);
1390 break;
1391
1392 case SMU_OD_VDDGFX_OFFSET:
1393 if (!smu->od_enabled || !od_table || !od_settings)
1394 break;
1395
1396 /*
1397 * OD GFX Voltage Offset functionality is supported only by 58.41.0
1398 * and onwards SMU firmwares.
1399 */
1400 if ((amdgpu_ip_version(adev, MP1_HWIP, 0) ==
1401 IP_VERSION(11, 0, 7)) &&
1402 (smu->smc_fw_version < 0x003a2900))
1403 break;
1404
1405 size += sysfs_emit_at(buf, size, "OD_VDDGFX_OFFSET:\n");
1406 size += sysfs_emit_at(buf, size, "%dmV\n", od_table->VddGfxOffset);
1407 break;
1408
1409 case SMU_OD_RANGE:
1410 if (!smu->od_enabled || !od_table || !od_settings)
1411 break;
1412
1413 size += sysfs_emit_at(buf, size, "%s:\n", "OD_RANGE");
1414
1415 if (sienna_cichlid_is_od_feature_supported(od_settings, SMU_11_0_7_ODCAP_GFXCLK_LIMITS)) {
1416 sienna_cichlid_get_od_setting_range(od_settings, SMU_11_0_7_ODSETTING_GFXCLKFMIN,
1417 &min_value, NULL);
1418 sienna_cichlid_get_od_setting_range(od_settings, SMU_11_0_7_ODSETTING_GFXCLKFMAX,
1419 NULL, &max_value);
1420 size += sysfs_emit_at(buf, size, "SCLK: %7uMhz %10uMhz\n",
1421 min_value, max_value);
1422 }
1423
1424 if (sienna_cichlid_is_od_feature_supported(od_settings, SMU_11_0_7_ODCAP_UCLK_LIMITS)) {
1425 sienna_cichlid_get_od_setting_range(od_settings, SMU_11_0_7_ODSETTING_UCLKFMIN,
1426 &min_value, NULL);
1427 sienna_cichlid_get_od_setting_range(od_settings, SMU_11_0_7_ODSETTING_UCLKFMAX,
1428 NULL, &max_value);
1429 size += sysfs_emit_at(buf, size, "MCLK: %7uMhz %10uMhz\n",
1430 min_value, max_value);
1431 }
1432 break;
1433
1434 default:
1435 break;
1436 }
1437
1438 print_clk_out:
1439 return size;
1440 }
1441
sienna_cichlid_force_clk_levels(struct smu_context * smu,enum smu_clk_type clk_type,uint32_t mask)1442 static int sienna_cichlid_force_clk_levels(struct smu_context *smu,
1443 enum smu_clk_type clk_type, uint32_t mask)
1444 {
1445 int ret = 0;
1446 uint32_t soft_min_level = 0, soft_max_level = 0, min_freq = 0, max_freq = 0;
1447
1448 soft_min_level = mask ? (ffs(mask) - 1) : 0;
1449 soft_max_level = mask ? (fls(mask) - 1) : 0;
1450
1451 switch (clk_type) {
1452 case SMU_GFXCLK:
1453 case SMU_SCLK:
1454 case SMU_SOCCLK:
1455 case SMU_MCLK:
1456 case SMU_UCLK:
1457 case SMU_FCLK:
1458 /* There is only 2 levels for fine grained DPM */
1459 if (sienna_cichlid_is_support_fine_grained_dpm(smu, clk_type)) {
1460 soft_max_level = (soft_max_level >= 1 ? 1 : 0);
1461 soft_min_level = (soft_min_level >= 1 ? 1 : 0);
1462 }
1463
1464 ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, soft_min_level, &min_freq);
1465 if (ret)
1466 goto forec_level_out;
1467
1468 ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, soft_max_level, &max_freq);
1469 if (ret)
1470 goto forec_level_out;
1471
1472 ret = smu_v11_0_set_soft_freq_limited_range(smu, clk_type, min_freq, max_freq);
1473 if (ret)
1474 goto forec_level_out;
1475 break;
1476 case SMU_DCEFCLK:
1477 dev_info(smu->adev->dev,"Setting DCEFCLK min/max dpm level is not supported!\n");
1478 break;
1479 default:
1480 break;
1481 }
1482
1483 forec_level_out:
1484 return 0;
1485 }
1486
sienna_cichlid_populate_umd_state_clk(struct smu_context * smu)1487 static int sienna_cichlid_populate_umd_state_clk(struct smu_context *smu)
1488 {
1489 struct smu_11_0_dpm_context *dpm_context =
1490 smu->smu_dpm.dpm_context;
1491 struct smu_11_0_dpm_table *gfx_table =
1492 &dpm_context->dpm_tables.gfx_table;
1493 struct smu_11_0_dpm_table *mem_table =
1494 &dpm_context->dpm_tables.uclk_table;
1495 struct smu_11_0_dpm_table *soc_table =
1496 &dpm_context->dpm_tables.soc_table;
1497 struct smu_umd_pstate_table *pstate_table =
1498 &smu->pstate_table;
1499 struct amdgpu_device *adev = smu->adev;
1500
1501 pstate_table->gfxclk_pstate.min = gfx_table->min;
1502 pstate_table->gfxclk_pstate.peak = gfx_table->max;
1503
1504 pstate_table->uclk_pstate.min = mem_table->min;
1505 pstate_table->uclk_pstate.peak = mem_table->max;
1506
1507 pstate_table->socclk_pstate.min = soc_table->min;
1508 pstate_table->socclk_pstate.peak = soc_table->max;
1509
1510 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) {
1511 case IP_VERSION(11, 0, 7):
1512 case IP_VERSION(11, 0, 11):
1513 pstate_table->gfxclk_pstate.standard = SIENNA_CICHLID_UMD_PSTATE_PROFILING_GFXCLK;
1514 pstate_table->uclk_pstate.standard = SIENNA_CICHLID_UMD_PSTATE_PROFILING_MEMCLK;
1515 pstate_table->socclk_pstate.standard = SIENNA_CICHLID_UMD_PSTATE_PROFILING_SOCCLK;
1516 break;
1517 case IP_VERSION(11, 0, 12):
1518 pstate_table->gfxclk_pstate.standard = DIMGREY_CAVEFISH_UMD_PSTATE_PROFILING_GFXCLK;
1519 pstate_table->uclk_pstate.standard = DIMGREY_CAVEFISH_UMD_PSTATE_PROFILING_MEMCLK;
1520 pstate_table->socclk_pstate.standard = DIMGREY_CAVEFISH_UMD_PSTATE_PROFILING_SOCCLK;
1521 break;
1522 case IP_VERSION(11, 0, 13):
1523 pstate_table->gfxclk_pstate.standard = BEIGE_GOBY_UMD_PSTATE_PROFILING_GFXCLK;
1524 pstate_table->uclk_pstate.standard = BEIGE_GOBY_UMD_PSTATE_PROFILING_MEMCLK;
1525 pstate_table->socclk_pstate.standard = BEIGE_GOBY_UMD_PSTATE_PROFILING_SOCCLK;
1526 break;
1527 default:
1528 break;
1529 }
1530
1531 return 0;
1532 }
1533
sienna_cichlid_pre_display_config_changed(struct smu_context * smu)1534 static int sienna_cichlid_pre_display_config_changed(struct smu_context *smu)
1535 {
1536 int ret = 0;
1537 uint32_t max_freq = 0;
1538
1539 /* Sienna_Cichlid do not support to change display num currently */
1540 return 0;
1541 #if 0
1542 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_NumOfDisplays, 0, NULL);
1543 if (ret)
1544 return ret;
1545 #endif
1546
1547 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
1548 ret = smu_v11_0_get_dpm_ultimate_freq(smu, SMU_UCLK, NULL, &max_freq);
1549 if (ret)
1550 return ret;
1551 ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, 0, max_freq);
1552 if (ret)
1553 return ret;
1554 }
1555
1556 return ret;
1557 }
1558
sienna_cichlid_display_config_changed(struct smu_context * smu)1559 static int sienna_cichlid_display_config_changed(struct smu_context *smu)
1560 {
1561 int ret = 0;
1562
1563 if ((smu->watermarks_bitmap & WATERMARKS_EXIST) &&
1564 smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT) &&
1565 smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
1566 #if 0
1567 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_NumOfDisplays,
1568 smu->display_config->num_display,
1569 NULL);
1570 #endif
1571 if (ret)
1572 return ret;
1573 }
1574
1575 return ret;
1576 }
1577
sienna_cichlid_is_dpm_running(struct smu_context * smu)1578 static bool sienna_cichlid_is_dpm_running(struct smu_context *smu)
1579 {
1580 int ret = 0;
1581 uint64_t feature_enabled;
1582
1583 ret = smu_cmn_get_enabled_mask(smu, &feature_enabled);
1584 if (ret)
1585 return false;
1586
1587 return !!(feature_enabled & SMC_DPM_FEATURE);
1588 }
1589
sienna_cichlid_get_fan_speed_rpm(struct smu_context * smu,uint32_t * speed)1590 static int sienna_cichlid_get_fan_speed_rpm(struct smu_context *smu,
1591 uint32_t *speed)
1592 {
1593 if (!speed)
1594 return -EINVAL;
1595
1596 /*
1597 * For Sienna_Cichlid and later, the fan speed(rpm) reported
1598 * by pmfw is always trustable(even when the fan control feature
1599 * disabled or 0 RPM kicked in).
1600 */
1601 return sienna_cichlid_get_smu_metrics_data(smu,
1602 METRICS_CURR_FANSPEED,
1603 speed);
1604 }
1605
sienna_cichlid_get_fan_parameters(struct smu_context * smu)1606 static int sienna_cichlid_get_fan_parameters(struct smu_context *smu)
1607 {
1608 uint16_t *table_member;
1609
1610 GET_PPTABLE_MEMBER(FanMaximumRpm, &table_member);
1611 smu->fan_max_rpm = *table_member;
1612
1613 return 0;
1614 }
1615
sienna_cichlid_get_power_profile_mode(struct smu_context * smu,char * buf)1616 static int sienna_cichlid_get_power_profile_mode(struct smu_context *smu, char *buf)
1617 {
1618 DpmActivityMonitorCoeffIntExternal_t activity_monitor_external;
1619 DpmActivityMonitorCoeffInt_t *activity_monitor =
1620 &(activity_monitor_external.DpmActivityMonitorCoeffInt);
1621 uint32_t i, size = 0;
1622 int16_t workload_type = 0;
1623 static const char *title[] = {
1624 "PROFILE_INDEX(NAME)",
1625 "CLOCK_TYPE(NAME)",
1626 "FPS",
1627 "MinFreqType",
1628 "MinActiveFreqType",
1629 "MinActiveFreq",
1630 "BoosterFreqType",
1631 "BoosterFreq",
1632 "PD_Data_limit_c",
1633 "PD_Data_error_coeff",
1634 "PD_Data_error_rate_coeff"};
1635 int result = 0;
1636
1637 if (!buf)
1638 return -EINVAL;
1639
1640 size += sysfs_emit_at(buf, size, "%16s %s %s %s %s %s %s %s %s %s %s\n",
1641 title[0], title[1], title[2], title[3], title[4], title[5],
1642 title[6], title[7], title[8], title[9], title[10]);
1643
1644 for (i = 0; i <= PP_SMC_POWER_PROFILE_CUSTOM; i++) {
1645 /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */
1646 workload_type = smu_cmn_to_asic_specific_index(smu,
1647 CMN2ASIC_MAPPING_WORKLOAD,
1648 i);
1649 if (workload_type < 0)
1650 return -EINVAL;
1651
1652 result = smu_cmn_update_table(smu,
1653 SMU_TABLE_ACTIVITY_MONITOR_COEFF, workload_type,
1654 (void *)(&activity_monitor_external), false);
1655 if (result) {
1656 dev_err(smu->adev->dev, "[%s] Failed to get activity monitor!", __func__);
1657 return result;
1658 }
1659
1660 size += sysfs_emit_at(buf, size, "%2d %14s%s:\n",
1661 i, amdgpu_pp_profile_name[i], (i == smu->power_profile_mode) ? "*" : " ");
1662
1663 size += sysfs_emit_at(buf, size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
1664 " ",
1665 0,
1666 "GFXCLK",
1667 activity_monitor->Gfx_FPS,
1668 activity_monitor->Gfx_MinFreqStep,
1669 activity_monitor->Gfx_MinActiveFreqType,
1670 activity_monitor->Gfx_MinActiveFreq,
1671 activity_monitor->Gfx_BoosterFreqType,
1672 activity_monitor->Gfx_BoosterFreq,
1673 activity_monitor->Gfx_PD_Data_limit_c,
1674 activity_monitor->Gfx_PD_Data_error_coeff,
1675 activity_monitor->Gfx_PD_Data_error_rate_coeff);
1676
1677 size += sysfs_emit_at(buf, size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
1678 " ",
1679 1,
1680 "SOCCLK",
1681 activity_monitor->Fclk_FPS,
1682 activity_monitor->Fclk_MinFreqStep,
1683 activity_monitor->Fclk_MinActiveFreqType,
1684 activity_monitor->Fclk_MinActiveFreq,
1685 activity_monitor->Fclk_BoosterFreqType,
1686 activity_monitor->Fclk_BoosterFreq,
1687 activity_monitor->Fclk_PD_Data_limit_c,
1688 activity_monitor->Fclk_PD_Data_error_coeff,
1689 activity_monitor->Fclk_PD_Data_error_rate_coeff);
1690
1691 size += sysfs_emit_at(buf, size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
1692 " ",
1693 2,
1694 "MEMCLK",
1695 activity_monitor->Mem_FPS,
1696 activity_monitor->Mem_MinFreqStep,
1697 activity_monitor->Mem_MinActiveFreqType,
1698 activity_monitor->Mem_MinActiveFreq,
1699 activity_monitor->Mem_BoosterFreqType,
1700 activity_monitor->Mem_BoosterFreq,
1701 activity_monitor->Mem_PD_Data_limit_c,
1702 activity_monitor->Mem_PD_Data_error_coeff,
1703 activity_monitor->Mem_PD_Data_error_rate_coeff);
1704 }
1705
1706 return size;
1707 }
1708
1709 #define SIENNA_CICHLID_CUSTOM_PARAMS_COUNT 10
1710 #define SIENNA_CICHLID_CUSTOM_PARAMS_CLOCK_COUNT 3
1711 #define SIENNA_CICHLID_CUSTOM_PARAMS_SIZE (SIENNA_CICHLID_CUSTOM_PARAMS_CLOCK_COUNT * SIENNA_CICHLID_CUSTOM_PARAMS_COUNT * sizeof(long))
1712
sienna_cichlid_set_power_profile_mode_coeff(struct smu_context * smu,long * input)1713 static int sienna_cichlid_set_power_profile_mode_coeff(struct smu_context *smu,
1714 long *input)
1715 {
1716
1717 DpmActivityMonitorCoeffIntExternal_t activity_monitor_external;
1718 DpmActivityMonitorCoeffInt_t *activity_monitor =
1719 &(activity_monitor_external.DpmActivityMonitorCoeffInt);
1720 int ret, idx;
1721
1722 ret = smu_cmn_update_table(smu,
1723 SMU_TABLE_ACTIVITY_MONITOR_COEFF, WORKLOAD_PPLIB_CUSTOM_BIT,
1724 (void *)(&activity_monitor_external), false);
1725 if (ret) {
1726 dev_err(smu->adev->dev, "[%s] Failed to get activity monitor!", __func__);
1727 return ret;
1728 }
1729
1730 idx = 0 * SIENNA_CICHLID_CUSTOM_PARAMS_COUNT;
1731 if (input[idx]) {
1732 /* Gfxclk */
1733 activity_monitor->Gfx_FPS = input[idx + 1];
1734 activity_monitor->Gfx_MinFreqStep = input[idx + 2];
1735 activity_monitor->Gfx_MinActiveFreqType = input[idx + 3];
1736 activity_monitor->Gfx_MinActiveFreq = input[idx + 4];
1737 activity_monitor->Gfx_BoosterFreqType = input[idx + 5];
1738 activity_monitor->Gfx_BoosterFreq = input[idx + 6];
1739 activity_monitor->Gfx_PD_Data_limit_c = input[idx + 7];
1740 activity_monitor->Gfx_PD_Data_error_coeff = input[idx + 8];
1741 activity_monitor->Gfx_PD_Data_error_rate_coeff = input[idx + 9];
1742 }
1743 idx = 1 * SIENNA_CICHLID_CUSTOM_PARAMS_COUNT;
1744 if (input[idx]) {
1745 /* Socclk */
1746 activity_monitor->Fclk_FPS = input[idx + 1];
1747 activity_monitor->Fclk_MinFreqStep = input[idx + 2];
1748 activity_monitor->Fclk_MinActiveFreqType = input[idx + 3];
1749 activity_monitor->Fclk_MinActiveFreq = input[idx + 4];
1750 activity_monitor->Fclk_BoosterFreqType = input[idx + 5];
1751 activity_monitor->Fclk_BoosterFreq = input[idx + 6];
1752 activity_monitor->Fclk_PD_Data_limit_c = input[idx + 7];
1753 activity_monitor->Fclk_PD_Data_error_coeff = input[idx + 8];
1754 activity_monitor->Fclk_PD_Data_error_rate_coeff = input[idx + 9];
1755 }
1756 idx = 2 * SIENNA_CICHLID_CUSTOM_PARAMS_COUNT;
1757 if (input[idx]) {
1758 /* Memclk */
1759 activity_monitor->Mem_FPS = input[idx + 1];
1760 activity_monitor->Mem_MinFreqStep = input[idx + 2];
1761 activity_monitor->Mem_MinActiveFreqType = input[idx + 3];
1762 activity_monitor->Mem_MinActiveFreq = input[idx + 4];
1763 activity_monitor->Mem_BoosterFreqType = input[idx + 5];
1764 activity_monitor->Mem_BoosterFreq = input[idx + 6];
1765 activity_monitor->Mem_PD_Data_limit_c = input[idx + 7];
1766 activity_monitor->Mem_PD_Data_error_coeff = input[idx + 8];
1767 activity_monitor->Mem_PD_Data_error_rate_coeff = input[idx + 9];
1768 }
1769
1770 ret = smu_cmn_update_table(smu,
1771 SMU_TABLE_ACTIVITY_MONITOR_COEFF, WORKLOAD_PPLIB_CUSTOM_BIT,
1772 (void *)(&activity_monitor_external), true);
1773 if (ret) {
1774 dev_err(smu->adev->dev, "[%s] Failed to set activity monitor!", __func__);
1775 return ret;
1776 }
1777
1778 return ret;
1779 }
1780
sienna_cichlid_set_power_profile_mode(struct smu_context * smu,u32 workload_mask,long * custom_params,u32 custom_params_max_idx)1781 static int sienna_cichlid_set_power_profile_mode(struct smu_context *smu,
1782 u32 workload_mask,
1783 long *custom_params,
1784 u32 custom_params_max_idx)
1785 {
1786 u32 backend_workload_mask = 0;
1787 int ret, idx = -1, i;
1788
1789 smu_cmn_get_backend_workload_mask(smu, workload_mask,
1790 &backend_workload_mask);
1791
1792 if (workload_mask & (1 << PP_SMC_POWER_PROFILE_CUSTOM)) {
1793 if (!smu->custom_profile_params) {
1794 smu->custom_profile_params =
1795 kzalloc(SIENNA_CICHLID_CUSTOM_PARAMS_SIZE, GFP_KERNEL);
1796 if (!smu->custom_profile_params)
1797 return -ENOMEM;
1798 }
1799 if (custom_params && custom_params_max_idx) {
1800 if (custom_params_max_idx != SIENNA_CICHLID_CUSTOM_PARAMS_COUNT)
1801 return -EINVAL;
1802 if (custom_params[0] >= SIENNA_CICHLID_CUSTOM_PARAMS_CLOCK_COUNT)
1803 return -EINVAL;
1804 idx = custom_params[0] * SIENNA_CICHLID_CUSTOM_PARAMS_COUNT;
1805 smu->custom_profile_params[idx] = 1;
1806 for (i = 1; i < custom_params_max_idx; i++)
1807 smu->custom_profile_params[idx + i] = custom_params[i];
1808 }
1809 ret = sienna_cichlid_set_power_profile_mode_coeff(smu,
1810 smu->custom_profile_params);
1811 if (ret) {
1812 if (idx != -1)
1813 smu->custom_profile_params[idx] = 0;
1814 return ret;
1815 }
1816 } else if (smu->custom_profile_params) {
1817 memset(smu->custom_profile_params, 0, SIENNA_CICHLID_CUSTOM_PARAMS_SIZE);
1818 }
1819
1820 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetWorkloadMask,
1821 backend_workload_mask, NULL);
1822 if (ret) {
1823 dev_err(smu->adev->dev, "Failed to set workload mask 0x%08x\n",
1824 workload_mask);
1825 if (idx != -1)
1826 smu->custom_profile_params[idx] = 0;
1827 return ret;
1828 }
1829
1830 return ret;
1831 }
1832
sienna_cichlid_notify_smc_display_config(struct smu_context * smu)1833 static int sienna_cichlid_notify_smc_display_config(struct smu_context *smu)
1834 {
1835 struct smu_clocks min_clocks = {0};
1836 struct pp_display_clock_request clock_req;
1837 int ret = 0;
1838
1839 min_clocks.dcef_clock = smu->display_config->min_dcef_set_clk;
1840 min_clocks.dcef_clock_in_sr = smu->display_config->min_dcef_deep_sleep_set_clk;
1841 min_clocks.memory_clock = smu->display_config->min_mem_set_clock;
1842
1843 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
1844 clock_req.clock_type = amd_pp_dcef_clock;
1845 clock_req.clock_freq_in_khz = min_clocks.dcef_clock * 10;
1846
1847 ret = smu_v11_0_display_clock_voltage_request(smu, &clock_req);
1848 if (!ret) {
1849 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DS_DCEFCLK_BIT)) {
1850 ret = smu_cmn_send_smc_msg_with_param(smu,
1851 SMU_MSG_SetMinDeepSleepDcefclk,
1852 min_clocks.dcef_clock_in_sr/100,
1853 NULL);
1854 if (ret) {
1855 dev_err(smu->adev->dev, "Attempt to set divider for DCEFCLK Failed!");
1856 return ret;
1857 }
1858 }
1859 } else {
1860 dev_info(smu->adev->dev, "Attempt to set Hard Min for DCEFCLK Failed!");
1861 }
1862 }
1863
1864 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
1865 ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, min_clocks.memory_clock/100, 0);
1866 if (ret) {
1867 dev_err(smu->adev->dev, "[%s] Set hard min uclk failed!", __func__);
1868 return ret;
1869 }
1870 }
1871
1872 return 0;
1873 }
1874
sienna_cichlid_set_watermarks_table(struct smu_context * smu,struct pp_smu_wm_range_sets * clock_ranges)1875 static int sienna_cichlid_set_watermarks_table(struct smu_context *smu,
1876 struct pp_smu_wm_range_sets *clock_ranges)
1877 {
1878 Watermarks_t *table = smu->smu_table.watermarks_table;
1879 int ret = 0;
1880 int i;
1881
1882 if (clock_ranges) {
1883 if (clock_ranges->num_reader_wm_sets > NUM_WM_RANGES ||
1884 clock_ranges->num_writer_wm_sets > NUM_WM_RANGES)
1885 return -EINVAL;
1886
1887 for (i = 0; i < clock_ranges->num_reader_wm_sets; i++) {
1888 table->WatermarkRow[WM_DCEFCLK][i].MinClock =
1889 clock_ranges->reader_wm_sets[i].min_drain_clk_mhz;
1890 table->WatermarkRow[WM_DCEFCLK][i].MaxClock =
1891 clock_ranges->reader_wm_sets[i].max_drain_clk_mhz;
1892 table->WatermarkRow[WM_DCEFCLK][i].MinUclk =
1893 clock_ranges->reader_wm_sets[i].min_fill_clk_mhz;
1894 table->WatermarkRow[WM_DCEFCLK][i].MaxUclk =
1895 clock_ranges->reader_wm_sets[i].max_fill_clk_mhz;
1896
1897 table->WatermarkRow[WM_DCEFCLK][i].WmSetting =
1898 clock_ranges->reader_wm_sets[i].wm_inst;
1899 }
1900
1901 for (i = 0; i < clock_ranges->num_writer_wm_sets; i++) {
1902 table->WatermarkRow[WM_SOCCLK][i].MinClock =
1903 clock_ranges->writer_wm_sets[i].min_fill_clk_mhz;
1904 table->WatermarkRow[WM_SOCCLK][i].MaxClock =
1905 clock_ranges->writer_wm_sets[i].max_fill_clk_mhz;
1906 table->WatermarkRow[WM_SOCCLK][i].MinUclk =
1907 clock_ranges->writer_wm_sets[i].min_drain_clk_mhz;
1908 table->WatermarkRow[WM_SOCCLK][i].MaxUclk =
1909 clock_ranges->writer_wm_sets[i].max_drain_clk_mhz;
1910
1911 table->WatermarkRow[WM_SOCCLK][i].WmSetting =
1912 clock_ranges->writer_wm_sets[i].wm_inst;
1913 }
1914
1915 smu->watermarks_bitmap |= WATERMARKS_EXIST;
1916 }
1917
1918 if ((smu->watermarks_bitmap & WATERMARKS_EXIST) &&
1919 !(smu->watermarks_bitmap & WATERMARKS_LOADED)) {
1920 ret = smu_cmn_write_watermarks_table(smu);
1921 if (ret) {
1922 dev_err(smu->adev->dev, "Failed to update WMTABLE!");
1923 return ret;
1924 }
1925 smu->watermarks_bitmap |= WATERMARKS_LOADED;
1926 }
1927
1928 return 0;
1929 }
1930
sienna_cichlid_read_sensor(struct smu_context * smu,enum amd_pp_sensors sensor,void * data,uint32_t * size)1931 static int sienna_cichlid_read_sensor(struct smu_context *smu,
1932 enum amd_pp_sensors sensor,
1933 void *data, uint32_t *size)
1934 {
1935 int ret = 0;
1936 uint16_t *temp;
1937 struct amdgpu_device *adev = smu->adev;
1938
1939 if(!data || !size)
1940 return -EINVAL;
1941
1942 switch (sensor) {
1943 case AMDGPU_PP_SENSOR_MAX_FAN_RPM:
1944 GET_PPTABLE_MEMBER(FanMaximumRpm, &temp);
1945 *(uint16_t *)data = *temp;
1946 *size = 4;
1947 break;
1948 case AMDGPU_PP_SENSOR_MEM_LOAD:
1949 ret = sienna_cichlid_get_smu_metrics_data(smu,
1950 METRICS_AVERAGE_MEMACTIVITY,
1951 (uint32_t *)data);
1952 *size = 4;
1953 break;
1954 case AMDGPU_PP_SENSOR_GPU_LOAD:
1955 ret = sienna_cichlid_get_smu_metrics_data(smu,
1956 METRICS_AVERAGE_GFXACTIVITY,
1957 (uint32_t *)data);
1958 *size = 4;
1959 break;
1960 case AMDGPU_PP_SENSOR_GPU_AVG_POWER:
1961 ret = sienna_cichlid_get_smu_metrics_data(smu,
1962 METRICS_AVERAGE_SOCKETPOWER,
1963 (uint32_t *)data);
1964 *size = 4;
1965 break;
1966 case AMDGPU_PP_SENSOR_HOTSPOT_TEMP:
1967 ret = sienna_cichlid_get_smu_metrics_data(smu,
1968 METRICS_TEMPERATURE_HOTSPOT,
1969 (uint32_t *)data);
1970 *size = 4;
1971 break;
1972 case AMDGPU_PP_SENSOR_EDGE_TEMP:
1973 ret = sienna_cichlid_get_smu_metrics_data(smu,
1974 METRICS_TEMPERATURE_EDGE,
1975 (uint32_t *)data);
1976 *size = 4;
1977 break;
1978 case AMDGPU_PP_SENSOR_MEM_TEMP:
1979 ret = sienna_cichlid_get_smu_metrics_data(smu,
1980 METRICS_TEMPERATURE_MEM,
1981 (uint32_t *)data);
1982 *size = 4;
1983 break;
1984 case AMDGPU_PP_SENSOR_GFX_MCLK:
1985 ret = sienna_cichlid_get_smu_metrics_data(smu,
1986 METRICS_CURR_UCLK,
1987 (uint32_t *)data);
1988 *(uint32_t *)data *= 100;
1989 *size = 4;
1990 break;
1991 case AMDGPU_PP_SENSOR_GFX_SCLK:
1992 ret = sienna_cichlid_get_smu_metrics_data(smu,
1993 METRICS_AVERAGE_GFXCLK,
1994 (uint32_t *)data);
1995 *(uint32_t *)data *= 100;
1996 *size = 4;
1997 break;
1998 case AMDGPU_PP_SENSOR_VDDGFX:
1999 ret = smu_v11_0_get_gfx_vdd(smu, (uint32_t *)data);
2000 *size = 4;
2001 break;
2002 case AMDGPU_PP_SENSOR_SS_APU_SHARE:
2003 if (amdgpu_ip_version(adev, MP1_HWIP, 0) !=
2004 IP_VERSION(11, 0, 7)) {
2005 ret = sienna_cichlid_get_smu_metrics_data(smu,
2006 METRICS_SS_APU_SHARE, (uint32_t *)data);
2007 *size = 4;
2008 } else {
2009 ret = -EOPNOTSUPP;
2010 }
2011 break;
2012 case AMDGPU_PP_SENSOR_SS_DGPU_SHARE:
2013 if (amdgpu_ip_version(adev, MP1_HWIP, 0) !=
2014 IP_VERSION(11, 0, 7)) {
2015 ret = sienna_cichlid_get_smu_metrics_data(smu,
2016 METRICS_SS_DGPU_SHARE, (uint32_t *)data);
2017 *size = 4;
2018 } else {
2019 ret = -EOPNOTSUPP;
2020 }
2021 break;
2022 case AMDGPU_PP_SENSOR_GPU_INPUT_POWER:
2023 default:
2024 ret = -EOPNOTSUPP;
2025 break;
2026 }
2027
2028 return ret;
2029 }
2030
sienna_cichlid_get_unique_id(struct smu_context * smu)2031 static void sienna_cichlid_get_unique_id(struct smu_context *smu)
2032 {
2033 struct amdgpu_device *adev = smu->adev;
2034 uint32_t upper32 = 0, lower32 = 0;
2035
2036 /* Only supported as of version 0.58.83.0 and only on Sienna Cichlid */
2037 if (smu->smc_fw_version < 0x3A5300 ||
2038 amdgpu_ip_version(smu->adev, MP1_HWIP, 0) != IP_VERSION(11, 0, 7))
2039 return;
2040
2041 if (sienna_cichlid_get_smu_metrics_data(smu, METRICS_UNIQUE_ID_UPPER32, &upper32))
2042 goto out;
2043 if (sienna_cichlid_get_smu_metrics_data(smu, METRICS_UNIQUE_ID_LOWER32, &lower32))
2044 goto out;
2045
2046 out:
2047
2048 adev->unique_id = ((uint64_t)upper32 << 32) | lower32;
2049 }
2050
sienna_cichlid_get_uclk_dpm_states(struct smu_context * smu,uint32_t * clocks_in_khz,uint32_t * num_states)2051 static int sienna_cichlid_get_uclk_dpm_states(struct smu_context *smu, uint32_t *clocks_in_khz, uint32_t *num_states)
2052 {
2053 uint32_t num_discrete_levels = 0;
2054 uint16_t *dpm_levels = NULL;
2055 uint16_t i = 0;
2056 struct smu_table_context *table_context = &smu->smu_table;
2057 DpmDescriptor_t *table_member1;
2058 uint16_t *table_member2;
2059
2060 if (!clocks_in_khz || !num_states || !table_context->driver_pptable)
2061 return -EINVAL;
2062
2063 GET_PPTABLE_MEMBER(DpmDescriptor, &table_member1);
2064 num_discrete_levels = table_member1[PPCLK_UCLK].NumDiscreteLevels;
2065 GET_PPTABLE_MEMBER(FreqTableUclk, &table_member2);
2066 dpm_levels = table_member2;
2067
2068 if (num_discrete_levels == 0 || dpm_levels == NULL)
2069 return -EINVAL;
2070
2071 *num_states = num_discrete_levels;
2072 for (i = 0; i < num_discrete_levels; i++) {
2073 /* convert to khz */
2074 *clocks_in_khz = (*dpm_levels) * 1000;
2075 clocks_in_khz++;
2076 dpm_levels++;
2077 }
2078
2079 return 0;
2080 }
2081
sienna_cichlid_get_thermal_temperature_range(struct smu_context * smu,struct smu_temperature_range * range)2082 static int sienna_cichlid_get_thermal_temperature_range(struct smu_context *smu,
2083 struct smu_temperature_range *range)
2084 {
2085 struct smu_table_context *table_context = &smu->smu_table;
2086 struct smu_11_0_7_powerplay_table *powerplay_table =
2087 table_context->power_play_table;
2088 uint16_t *table_member;
2089 uint16_t temp_edge, temp_hotspot, temp_mem;
2090
2091 if (!range)
2092 return -EINVAL;
2093
2094 memcpy(range, &smu11_thermal_policy[0], sizeof(struct smu_temperature_range));
2095
2096 GET_PPTABLE_MEMBER(TemperatureLimit, &table_member);
2097 temp_edge = table_member[TEMP_EDGE];
2098 temp_hotspot = table_member[TEMP_HOTSPOT];
2099 temp_mem = table_member[TEMP_MEM];
2100
2101 range->max = temp_edge * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
2102 range->edge_emergency_max = (temp_edge + CTF_OFFSET_EDGE) *
2103 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
2104 range->hotspot_crit_max = temp_hotspot * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
2105 range->hotspot_emergency_max = (temp_hotspot + CTF_OFFSET_HOTSPOT) *
2106 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
2107 range->mem_crit_max = temp_mem * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
2108 range->mem_emergency_max = (temp_mem + CTF_OFFSET_MEM)*
2109 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
2110
2111 range->software_shutdown_temp = powerplay_table->software_shutdown_temp;
2112
2113 return 0;
2114 }
2115
sienna_cichlid_display_disable_memory_clock_switch(struct smu_context * smu,bool disable_memory_clock_switch)2116 static int sienna_cichlid_display_disable_memory_clock_switch(struct smu_context *smu,
2117 bool disable_memory_clock_switch)
2118 {
2119 int ret = 0;
2120 struct smu_11_0_max_sustainable_clocks *max_sustainable_clocks =
2121 (struct smu_11_0_max_sustainable_clocks *)
2122 smu->smu_table.max_sustainable_clocks;
2123 uint32_t min_memory_clock = smu->hard_min_uclk_req_from_dal;
2124 uint32_t max_memory_clock = max_sustainable_clocks->uclock;
2125
2126 if(smu->disable_uclk_switch == disable_memory_clock_switch)
2127 return 0;
2128
2129 if(disable_memory_clock_switch)
2130 ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, max_memory_clock, 0);
2131 else
2132 ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, min_memory_clock, 0);
2133
2134 if(!ret)
2135 smu->disable_uclk_switch = disable_memory_clock_switch;
2136
2137 return ret;
2138 }
2139
sienna_cichlid_update_pcie_parameters(struct smu_context * smu,uint8_t pcie_gen_cap,uint8_t pcie_width_cap)2140 static int sienna_cichlid_update_pcie_parameters(struct smu_context *smu,
2141 uint8_t pcie_gen_cap,
2142 uint8_t pcie_width_cap)
2143 {
2144 struct smu_11_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;
2145 struct smu_11_0_pcie_table *pcie_table = &dpm_context->dpm_tables.pcie_table;
2146 uint8_t *table_member1, *table_member2;
2147 uint8_t min_gen_speed, max_gen_speed;
2148 uint8_t min_lane_width, max_lane_width;
2149 uint32_t smu_pcie_arg;
2150 int ret, i;
2151
2152 GET_PPTABLE_MEMBER(PcieGenSpeed, &table_member1);
2153 GET_PPTABLE_MEMBER(PcieLaneCount, &table_member2);
2154
2155 min_gen_speed = max_t(uint8_t, 0, table_member1[0]);
2156 max_gen_speed = min(pcie_gen_cap, table_member1[1]);
2157 min_gen_speed = min_gen_speed > max_gen_speed ?
2158 max_gen_speed : min_gen_speed;
2159 min_lane_width = max_t(uint8_t, 1, table_member2[0]);
2160 max_lane_width = min(pcie_width_cap, table_member2[1]);
2161 min_lane_width = min_lane_width > max_lane_width ?
2162 max_lane_width : min_lane_width;
2163
2164 if (!(smu->adev->pm.pp_feature & PP_PCIE_DPM_MASK)) {
2165 pcie_table->pcie_gen[0] = max_gen_speed;
2166 pcie_table->pcie_lane[0] = max_lane_width;
2167 } else {
2168 pcie_table->pcie_gen[0] = min_gen_speed;
2169 pcie_table->pcie_lane[0] = min_lane_width;
2170 }
2171 pcie_table->pcie_gen[1] = max_gen_speed;
2172 pcie_table->pcie_lane[1] = max_lane_width;
2173
2174 for (i = 0; i < NUM_LINK_LEVELS; i++) {
2175 smu_pcie_arg = (i << 16 |
2176 pcie_table->pcie_gen[i] << 8 |
2177 pcie_table->pcie_lane[i]);
2178
2179 ret = smu_cmn_send_smc_msg_with_param(smu,
2180 SMU_MSG_OverridePcieParameters,
2181 smu_pcie_arg,
2182 NULL);
2183 if (ret)
2184 return ret;
2185 }
2186
2187 return 0;
2188 }
2189
sienna_cichlid_get_dpm_ultimate_freq(struct smu_context * smu,enum smu_clk_type clk_type,uint32_t * min,uint32_t * max)2190 static int sienna_cichlid_get_dpm_ultimate_freq(struct smu_context *smu,
2191 enum smu_clk_type clk_type,
2192 uint32_t *min, uint32_t *max)
2193 {
2194 return smu_v11_0_get_dpm_ultimate_freq(smu, clk_type, min, max);
2195 }
2196
sienna_cichlid_dump_od_table(struct smu_context * smu,OverDriveTable_t * od_table)2197 static void sienna_cichlid_dump_od_table(struct smu_context *smu,
2198 OverDriveTable_t *od_table)
2199 {
2200 struct amdgpu_device *adev = smu->adev;
2201
2202 dev_dbg(smu->adev->dev, "OD: Gfxclk: (%d, %d)\n", od_table->GfxclkFmin,
2203 od_table->GfxclkFmax);
2204 dev_dbg(smu->adev->dev, "OD: Uclk: (%d, %d)\n", od_table->UclkFmin,
2205 od_table->UclkFmax);
2206
2207 if (!((amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(11, 0, 7)) &&
2208 (smu->smc_fw_version < 0x003a2900)))
2209 dev_dbg(smu->adev->dev, "OD: VddGfxOffset: %d\n", od_table->VddGfxOffset);
2210 }
2211
sienna_cichlid_set_default_od_settings(struct smu_context * smu)2212 static int sienna_cichlid_set_default_od_settings(struct smu_context *smu)
2213 {
2214 OverDriveTable_t *od_table =
2215 (OverDriveTable_t *)smu->smu_table.overdrive_table;
2216 OverDriveTable_t *boot_od_table =
2217 (OverDriveTable_t *)smu->smu_table.boot_overdrive_table;
2218 OverDriveTable_t *user_od_table =
2219 (OverDriveTable_t *)smu->smu_table.user_overdrive_table;
2220 OverDriveTable_t user_od_table_bak;
2221 int ret = 0;
2222
2223 ret = smu_cmn_update_table(smu, SMU_TABLE_OVERDRIVE,
2224 0, (void *)boot_od_table, false);
2225 if (ret) {
2226 dev_err(smu->adev->dev, "Failed to get overdrive table!\n");
2227 return ret;
2228 }
2229
2230 sienna_cichlid_dump_od_table(smu, boot_od_table);
2231
2232 memcpy(od_table, boot_od_table, sizeof(OverDriveTable_t));
2233
2234 /*
2235 * For S3/S4/Runpm resume, we need to setup those overdrive tables again,
2236 * but we have to preserve user defined values in "user_od_table".
2237 */
2238 if (!smu->adev->in_suspend) {
2239 memcpy(user_od_table, boot_od_table, sizeof(OverDriveTable_t));
2240 smu->user_dpm_profile.user_od = false;
2241 } else if (smu->user_dpm_profile.user_od) {
2242 memcpy(&user_od_table_bak, user_od_table, sizeof(OverDriveTable_t));
2243 memcpy(user_od_table, boot_od_table, sizeof(OverDriveTable_t));
2244 user_od_table->GfxclkFmin = user_od_table_bak.GfxclkFmin;
2245 user_od_table->GfxclkFmax = user_od_table_bak.GfxclkFmax;
2246 user_od_table->UclkFmin = user_od_table_bak.UclkFmin;
2247 user_od_table->UclkFmax = user_od_table_bak.UclkFmax;
2248 user_od_table->VddGfxOffset = user_od_table_bak.VddGfxOffset;
2249 }
2250
2251 return 0;
2252 }
2253
sienna_cichlid_od_setting_check_range(struct smu_context * smu,struct smu_11_0_7_overdrive_table * od_table,enum SMU_11_0_7_ODSETTING_ID setting,uint32_t value)2254 static int sienna_cichlid_od_setting_check_range(struct smu_context *smu,
2255 struct smu_11_0_7_overdrive_table *od_table,
2256 enum SMU_11_0_7_ODSETTING_ID setting,
2257 uint32_t value)
2258 {
2259 if (value < od_table->min[setting]) {
2260 dev_warn(smu->adev->dev, "OD setting (%d, %d) is less than the minimum allowed (%d)\n",
2261 setting, value, od_table->min[setting]);
2262 return -EINVAL;
2263 }
2264 if (value > od_table->max[setting]) {
2265 dev_warn(smu->adev->dev, "OD setting (%d, %d) is greater than the maximum allowed (%d)\n",
2266 setting, value, od_table->max[setting]);
2267 return -EINVAL;
2268 }
2269
2270 return 0;
2271 }
2272
sienna_cichlid_od_edit_dpm_table(struct smu_context * smu,enum PP_OD_DPM_TABLE_COMMAND type,long input[],uint32_t size)2273 static int sienna_cichlid_od_edit_dpm_table(struct smu_context *smu,
2274 enum PP_OD_DPM_TABLE_COMMAND type,
2275 long input[], uint32_t size)
2276 {
2277 struct smu_table_context *table_context = &smu->smu_table;
2278 OverDriveTable_t *od_table =
2279 (OverDriveTable_t *)table_context->overdrive_table;
2280 struct smu_11_0_7_overdrive_table *od_settings =
2281 (struct smu_11_0_7_overdrive_table *)smu->od_settings;
2282 struct amdgpu_device *adev = smu->adev;
2283 enum SMU_11_0_7_ODSETTING_ID freq_setting;
2284 uint16_t *freq_ptr;
2285 int i, ret = 0;
2286
2287 if (!smu->od_enabled) {
2288 dev_warn(smu->adev->dev, "OverDrive is not enabled!\n");
2289 return -EINVAL;
2290 }
2291
2292 if (!smu->od_settings) {
2293 dev_err(smu->adev->dev, "OD board limits are not set!\n");
2294 return -ENOENT;
2295 }
2296
2297 if (!(table_context->overdrive_table && table_context->boot_overdrive_table)) {
2298 dev_err(smu->adev->dev, "Overdrive table was not initialized!\n");
2299 return -EINVAL;
2300 }
2301
2302 switch (type) {
2303 case PP_OD_EDIT_SCLK_VDDC_TABLE:
2304 if (!sienna_cichlid_is_od_feature_supported(od_settings,
2305 SMU_11_0_7_ODCAP_GFXCLK_LIMITS)) {
2306 dev_warn(smu->adev->dev, "GFXCLK_LIMITS not supported!\n");
2307 return -ENOTSUPP;
2308 }
2309
2310 for (i = 0; i < size; i += 2) {
2311 if (i + 2 > size) {
2312 dev_info(smu->adev->dev, "invalid number of input parameters %d\n", size);
2313 return -EINVAL;
2314 }
2315
2316 switch (input[i]) {
2317 case 0:
2318 if (input[i + 1] > od_table->GfxclkFmax) {
2319 dev_info(smu->adev->dev, "GfxclkFmin (%ld) must be <= GfxclkFmax (%u)!\n",
2320 input[i + 1], od_table->GfxclkFmax);
2321 return -EINVAL;
2322 }
2323
2324 freq_setting = SMU_11_0_7_ODSETTING_GFXCLKFMIN;
2325 freq_ptr = &od_table->GfxclkFmin;
2326 break;
2327
2328 case 1:
2329 if (input[i + 1] < od_table->GfxclkFmin) {
2330 dev_info(smu->adev->dev, "GfxclkFmax (%ld) must be >= GfxclkFmin (%u)!\n",
2331 input[i + 1], od_table->GfxclkFmin);
2332 return -EINVAL;
2333 }
2334
2335 freq_setting = SMU_11_0_7_ODSETTING_GFXCLKFMAX;
2336 freq_ptr = &od_table->GfxclkFmax;
2337 break;
2338
2339 default:
2340 dev_info(smu->adev->dev, "Invalid SCLK_VDDC_TABLE index: %ld\n", input[i]);
2341 dev_info(smu->adev->dev, "Supported indices: [0:min,1:max]\n");
2342 return -EINVAL;
2343 }
2344
2345 ret = sienna_cichlid_od_setting_check_range(smu, od_settings,
2346 freq_setting, input[i + 1]);
2347 if (ret)
2348 return ret;
2349
2350 *freq_ptr = (uint16_t)input[i + 1];
2351 }
2352 break;
2353
2354 case PP_OD_EDIT_MCLK_VDDC_TABLE:
2355 if (!sienna_cichlid_is_od_feature_supported(od_settings, SMU_11_0_7_ODCAP_UCLK_LIMITS)) {
2356 dev_warn(smu->adev->dev, "UCLK_LIMITS not supported!\n");
2357 return -ENOTSUPP;
2358 }
2359
2360 for (i = 0; i < size; i += 2) {
2361 if (i + 2 > size) {
2362 dev_info(smu->adev->dev, "invalid number of input parameters %d\n", size);
2363 return -EINVAL;
2364 }
2365
2366 switch (input[i]) {
2367 case 0:
2368 if (input[i + 1] > od_table->UclkFmax) {
2369 dev_info(smu->adev->dev, "UclkFmin (%ld) must be <= UclkFmax (%u)!\n",
2370 input[i + 1], od_table->UclkFmax);
2371 return -EINVAL;
2372 }
2373
2374 freq_setting = SMU_11_0_7_ODSETTING_UCLKFMIN;
2375 freq_ptr = &od_table->UclkFmin;
2376 break;
2377
2378 case 1:
2379 if (input[i + 1] < od_table->UclkFmin) {
2380 dev_info(smu->adev->dev, "UclkFmax (%ld) must be >= UclkFmin (%u)!\n",
2381 input[i + 1], od_table->UclkFmin);
2382 return -EINVAL;
2383 }
2384
2385 freq_setting = SMU_11_0_7_ODSETTING_UCLKFMAX;
2386 freq_ptr = &od_table->UclkFmax;
2387 break;
2388
2389 default:
2390 dev_info(smu->adev->dev, "Invalid MCLK_VDDC_TABLE index: %ld\n", input[i]);
2391 dev_info(smu->adev->dev, "Supported indices: [0:min,1:max]\n");
2392 return -EINVAL;
2393 }
2394
2395 ret = sienna_cichlid_od_setting_check_range(smu, od_settings,
2396 freq_setting, input[i + 1]);
2397 if (ret)
2398 return ret;
2399
2400 *freq_ptr = (uint16_t)input[i + 1];
2401 }
2402 break;
2403
2404 case PP_OD_RESTORE_DEFAULT_TABLE:
2405 memcpy(table_context->overdrive_table,
2406 table_context->boot_overdrive_table,
2407 sizeof(OverDriveTable_t));
2408 fallthrough;
2409
2410 case PP_OD_COMMIT_DPM_TABLE:
2411 if (memcmp(od_table, table_context->user_overdrive_table, sizeof(OverDriveTable_t))) {
2412 sienna_cichlid_dump_od_table(smu, od_table);
2413 ret = smu_cmn_update_table(smu, SMU_TABLE_OVERDRIVE, 0, (void *)od_table, true);
2414 if (ret) {
2415 dev_err(smu->adev->dev, "Failed to import overdrive table!\n");
2416 return ret;
2417 }
2418 memcpy(table_context->user_overdrive_table, od_table, sizeof(OverDriveTable_t));
2419 smu->user_dpm_profile.user_od = true;
2420
2421 if (!memcmp(table_context->user_overdrive_table,
2422 table_context->boot_overdrive_table,
2423 sizeof(OverDriveTable_t)))
2424 smu->user_dpm_profile.user_od = false;
2425 }
2426 break;
2427
2428 case PP_OD_EDIT_VDDGFX_OFFSET:
2429 if (size != 1) {
2430 dev_info(smu->adev->dev, "invalid number of parameters: %d\n", size);
2431 return -EINVAL;
2432 }
2433
2434 /*
2435 * OD GFX Voltage Offset functionality is supported only by 58.41.0
2436 * and onwards SMU firmwares.
2437 */
2438 if ((amdgpu_ip_version(adev, MP1_HWIP, 0) ==
2439 IP_VERSION(11, 0, 7)) &&
2440 (smu->smc_fw_version < 0x003a2900)) {
2441 dev_err(smu->adev->dev, "OD GFX Voltage offset functionality is supported "
2442 "only by 58.41.0 and onwards SMU firmwares!\n");
2443 return -EOPNOTSUPP;
2444 }
2445
2446 od_table->VddGfxOffset = (int16_t)input[0];
2447
2448 sienna_cichlid_dump_od_table(smu, od_table);
2449 break;
2450
2451 default:
2452 return -ENOSYS;
2453 }
2454
2455 return ret;
2456 }
2457
sienna_cichlid_restore_user_od_settings(struct smu_context * smu)2458 static int sienna_cichlid_restore_user_od_settings(struct smu_context *smu)
2459 {
2460 struct smu_table_context *table_context = &smu->smu_table;
2461 OverDriveTable_t *od_table = table_context->overdrive_table;
2462 OverDriveTable_t *user_od_table = table_context->user_overdrive_table;
2463 int res;
2464
2465 res = smu_v11_0_restore_user_od_settings(smu);
2466 if (res == 0)
2467 memcpy(od_table, user_od_table, sizeof(OverDriveTable_t));
2468
2469 return res;
2470 }
2471
sienna_cichlid_run_btc(struct smu_context * smu)2472 static int sienna_cichlid_run_btc(struct smu_context *smu)
2473 {
2474 int res;
2475
2476 res = smu_cmn_send_smc_msg(smu, SMU_MSG_RunDcBtc, NULL);
2477 if (res)
2478 dev_err(smu->adev->dev, "RunDcBtc failed!\n");
2479
2480 return res;
2481 }
2482
sienna_cichlid_baco_enter(struct smu_context * smu)2483 static int sienna_cichlid_baco_enter(struct smu_context *smu)
2484 {
2485 struct amdgpu_device *adev = smu->adev;
2486
2487 if (adev->in_runpm && smu_cmn_is_audio_func_enabled(adev))
2488 return smu_v11_0_baco_set_armd3_sequence(smu, BACO_SEQ_BACO);
2489 else
2490 return smu_v11_0_baco_enter(smu);
2491 }
2492
sienna_cichlid_baco_exit(struct smu_context * smu)2493 static int sienna_cichlid_baco_exit(struct smu_context *smu)
2494 {
2495 struct amdgpu_device *adev = smu->adev;
2496
2497 if (adev->in_runpm && smu_cmn_is_audio_func_enabled(adev)) {
2498 /* Wait for PMFW handling for the Dstate change */
2499 msleep(10);
2500 return smu_v11_0_baco_set_armd3_sequence(smu, BACO_SEQ_ULPS);
2501 } else {
2502 return smu_v11_0_baco_exit(smu);
2503 }
2504 }
2505
sienna_cichlid_is_mode1_reset_supported(struct smu_context * smu)2506 static bool sienna_cichlid_is_mode1_reset_supported(struct smu_context *smu)
2507 {
2508 struct amdgpu_device *adev = smu->adev;
2509 uint32_t val;
2510 uint32_t smu_version;
2511 int ret;
2512
2513 /**
2514 * SRIOV env will not support SMU mode1 reset
2515 * PM FW support mode1 reset from 58.26
2516 */
2517 ret = smu_cmn_get_smc_version(smu, NULL, &smu_version);
2518 if (ret)
2519 return false;
2520
2521 if (amdgpu_sriov_vf(adev) || (smu_version < 0x003a1a00))
2522 return false;
2523
2524 /**
2525 * mode1 reset relies on PSP, so we should check if
2526 * PSP is alive.
2527 */
2528 val = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81);
2529 return val != 0x0;
2530 }
2531
beige_goby_dump_pptable(struct smu_context * smu)2532 static void beige_goby_dump_pptable(struct smu_context *smu)
2533 {
2534 struct smu_table_context *table_context = &smu->smu_table;
2535 PPTable_beige_goby_t *pptable = table_context->driver_pptable;
2536 int i;
2537
2538 dev_info(smu->adev->dev, "Dumped PPTable:\n");
2539
2540 dev_info(smu->adev->dev, "Version = 0x%08x\n", pptable->Version);
2541 dev_info(smu->adev->dev, "FeaturesToRun[0] = 0x%08x\n", pptable->FeaturesToRun[0]);
2542 dev_info(smu->adev->dev, "FeaturesToRun[1] = 0x%08x\n", pptable->FeaturesToRun[1]);
2543
2544 for (i = 0; i < PPT_THROTTLER_COUNT; i++) {
2545 dev_info(smu->adev->dev, "SocketPowerLimitAc[%d] = 0x%x\n", i, pptable->SocketPowerLimitAc[i]);
2546 dev_info(smu->adev->dev, "SocketPowerLimitAcTau[%d] = 0x%x\n", i, pptable->SocketPowerLimitAcTau[i]);
2547 dev_info(smu->adev->dev, "SocketPowerLimitDc[%d] = 0x%x\n", i, pptable->SocketPowerLimitDc[i]);
2548 dev_info(smu->adev->dev, "SocketPowerLimitDcTau[%d] = 0x%x\n", i, pptable->SocketPowerLimitDcTau[i]);
2549 }
2550
2551 for (i = 0; i < TDC_THROTTLER_COUNT; i++) {
2552 dev_info(smu->adev->dev, "TdcLimit[%d] = 0x%x\n", i, pptable->TdcLimit[i]);
2553 dev_info(smu->adev->dev, "TdcLimitTau[%d] = 0x%x\n", i, pptable->TdcLimitTau[i]);
2554 }
2555
2556 for (i = 0; i < TEMP_COUNT; i++) {
2557 dev_info(smu->adev->dev, "TemperatureLimit[%d] = 0x%x\n", i, pptable->TemperatureLimit[i]);
2558 }
2559
2560 dev_info(smu->adev->dev, "FitLimit = 0x%x\n", pptable->FitLimit);
2561 dev_info(smu->adev->dev, "TotalPowerConfig = 0x%x\n", pptable->TotalPowerConfig);
2562 dev_info(smu->adev->dev, "TotalPowerPadding[0] = 0x%x\n", pptable->TotalPowerPadding[0]);
2563 dev_info(smu->adev->dev, "TotalPowerPadding[1] = 0x%x\n", pptable->TotalPowerPadding[1]);
2564 dev_info(smu->adev->dev, "TotalPowerPadding[2] = 0x%x\n", pptable->TotalPowerPadding[2]);
2565
2566 dev_info(smu->adev->dev, "ApccPlusResidencyLimit = 0x%x\n", pptable->ApccPlusResidencyLimit);
2567 for (i = 0; i < NUM_SMNCLK_DPM_LEVELS; i++) {
2568 dev_info(smu->adev->dev, "SmnclkDpmFreq[%d] = 0x%x\n", i, pptable->SmnclkDpmFreq[i]);
2569 dev_info(smu->adev->dev, "SmnclkDpmVoltage[%d] = 0x%x\n", i, pptable->SmnclkDpmVoltage[i]);
2570 }
2571 dev_info(smu->adev->dev, "ThrottlerControlMask = 0x%x\n", pptable->ThrottlerControlMask);
2572
2573 dev_info(smu->adev->dev, "FwDStateMask = 0x%x\n", pptable->FwDStateMask);
2574
2575 dev_info(smu->adev->dev, "UlvVoltageOffsetSoc = 0x%x\n", pptable->UlvVoltageOffsetSoc);
2576 dev_info(smu->adev->dev, "UlvVoltageOffsetGfx = 0x%x\n", pptable->UlvVoltageOffsetGfx);
2577 dev_info(smu->adev->dev, "MinVoltageUlvGfx = 0x%x\n", pptable->MinVoltageUlvGfx);
2578 dev_info(smu->adev->dev, "MinVoltageUlvSoc = 0x%x\n", pptable->MinVoltageUlvSoc);
2579
2580 dev_info(smu->adev->dev, "SocLIVmin = 0x%x\n", pptable->SocLIVmin);
2581
2582 dev_info(smu->adev->dev, "GceaLinkMgrIdleThreshold = 0x%x\n", pptable->GceaLinkMgrIdleThreshold);
2583
2584 dev_info(smu->adev->dev, "MinVoltageGfx = 0x%x\n", pptable->MinVoltageGfx);
2585 dev_info(smu->adev->dev, "MinVoltageSoc = 0x%x\n", pptable->MinVoltageSoc);
2586 dev_info(smu->adev->dev, "MaxVoltageGfx = 0x%x\n", pptable->MaxVoltageGfx);
2587 dev_info(smu->adev->dev, "MaxVoltageSoc = 0x%x\n", pptable->MaxVoltageSoc);
2588
2589 dev_info(smu->adev->dev, "LoadLineResistanceGfx = 0x%x\n", pptable->LoadLineResistanceGfx);
2590 dev_info(smu->adev->dev, "LoadLineResistanceSoc = 0x%x\n", pptable->LoadLineResistanceSoc);
2591
2592 dev_info(smu->adev->dev, "VDDGFX_TVmin = 0x%x\n", pptable->VDDGFX_TVmin);
2593 dev_info(smu->adev->dev, "VDDSOC_TVmin = 0x%x\n", pptable->VDDSOC_TVmin);
2594 dev_info(smu->adev->dev, "VDDGFX_Vmin_HiTemp = 0x%x\n", pptable->VDDGFX_Vmin_HiTemp);
2595 dev_info(smu->adev->dev, "VDDGFX_Vmin_LoTemp = 0x%x\n", pptable->VDDGFX_Vmin_LoTemp);
2596 dev_info(smu->adev->dev, "VDDSOC_Vmin_HiTemp = 0x%x\n", pptable->VDDSOC_Vmin_HiTemp);
2597 dev_info(smu->adev->dev, "VDDSOC_Vmin_LoTemp = 0x%x\n", pptable->VDDSOC_Vmin_LoTemp);
2598 dev_info(smu->adev->dev, "VDDGFX_TVminHystersis = 0x%x\n", pptable->VDDGFX_TVminHystersis);
2599 dev_info(smu->adev->dev, "VDDSOC_TVminHystersis = 0x%x\n", pptable->VDDSOC_TVminHystersis);
2600
2601 dev_info(smu->adev->dev, "[PPCLK_GFXCLK]\n"
2602 " .VoltageMode = 0x%02x\n"
2603 " .SnapToDiscrete = 0x%02x\n"
2604 " .NumDiscreteLevels = 0x%02x\n"
2605 " .padding = 0x%02x\n"
2606 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
2607 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
2608 " .SsFmin = 0x%04x\n"
2609 " .Padding_16 = 0x%04x\n",
2610 pptable->DpmDescriptor[PPCLK_GFXCLK].VoltageMode,
2611 pptable->DpmDescriptor[PPCLK_GFXCLK].SnapToDiscrete,
2612 pptable->DpmDescriptor[PPCLK_GFXCLK].NumDiscreteLevels,
2613 pptable->DpmDescriptor[PPCLK_GFXCLK].Padding,
2614 pptable->DpmDescriptor[PPCLK_GFXCLK].ConversionToAvfsClk.m,
2615 pptable->DpmDescriptor[PPCLK_GFXCLK].ConversionToAvfsClk.b,
2616 pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.a,
2617 pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.b,
2618 pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.c,
2619 pptable->DpmDescriptor[PPCLK_GFXCLK].SsFmin,
2620 pptable->DpmDescriptor[PPCLK_GFXCLK].Padding16);
2621
2622 dev_info(smu->adev->dev, "[PPCLK_SOCCLK]\n"
2623 " .VoltageMode = 0x%02x\n"
2624 " .SnapToDiscrete = 0x%02x\n"
2625 " .NumDiscreteLevels = 0x%02x\n"
2626 " .padding = 0x%02x\n"
2627 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
2628 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
2629 " .SsFmin = 0x%04x\n"
2630 " .Padding_16 = 0x%04x\n",
2631 pptable->DpmDescriptor[PPCLK_SOCCLK].VoltageMode,
2632 pptable->DpmDescriptor[PPCLK_SOCCLK].SnapToDiscrete,
2633 pptable->DpmDescriptor[PPCLK_SOCCLK].NumDiscreteLevels,
2634 pptable->DpmDescriptor[PPCLK_SOCCLK].Padding,
2635 pptable->DpmDescriptor[PPCLK_SOCCLK].ConversionToAvfsClk.m,
2636 pptable->DpmDescriptor[PPCLK_SOCCLK].ConversionToAvfsClk.b,
2637 pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.a,
2638 pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.b,
2639 pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.c,
2640 pptable->DpmDescriptor[PPCLK_SOCCLK].SsFmin,
2641 pptable->DpmDescriptor[PPCLK_SOCCLK].Padding16);
2642
2643 dev_info(smu->adev->dev, "[PPCLK_UCLK]\n"
2644 " .VoltageMode = 0x%02x\n"
2645 " .SnapToDiscrete = 0x%02x\n"
2646 " .NumDiscreteLevels = 0x%02x\n"
2647 " .padding = 0x%02x\n"
2648 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
2649 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
2650 " .SsFmin = 0x%04x\n"
2651 " .Padding_16 = 0x%04x\n",
2652 pptable->DpmDescriptor[PPCLK_UCLK].VoltageMode,
2653 pptable->DpmDescriptor[PPCLK_UCLK].SnapToDiscrete,
2654 pptable->DpmDescriptor[PPCLK_UCLK].NumDiscreteLevels,
2655 pptable->DpmDescriptor[PPCLK_UCLK].Padding,
2656 pptable->DpmDescriptor[PPCLK_UCLK].ConversionToAvfsClk.m,
2657 pptable->DpmDescriptor[PPCLK_UCLK].ConversionToAvfsClk.b,
2658 pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.a,
2659 pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.b,
2660 pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.c,
2661 pptable->DpmDescriptor[PPCLK_UCLK].SsFmin,
2662 pptable->DpmDescriptor[PPCLK_UCLK].Padding16);
2663
2664 dev_info(smu->adev->dev, "[PPCLK_FCLK]\n"
2665 " .VoltageMode = 0x%02x\n"
2666 " .SnapToDiscrete = 0x%02x\n"
2667 " .NumDiscreteLevels = 0x%02x\n"
2668 " .padding = 0x%02x\n"
2669 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
2670 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
2671 " .SsFmin = 0x%04x\n"
2672 " .Padding_16 = 0x%04x\n",
2673 pptable->DpmDescriptor[PPCLK_FCLK].VoltageMode,
2674 pptable->DpmDescriptor[PPCLK_FCLK].SnapToDiscrete,
2675 pptable->DpmDescriptor[PPCLK_FCLK].NumDiscreteLevels,
2676 pptable->DpmDescriptor[PPCLK_FCLK].Padding,
2677 pptable->DpmDescriptor[PPCLK_FCLK].ConversionToAvfsClk.m,
2678 pptable->DpmDescriptor[PPCLK_FCLK].ConversionToAvfsClk.b,
2679 pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.a,
2680 pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.b,
2681 pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.c,
2682 pptable->DpmDescriptor[PPCLK_FCLK].SsFmin,
2683 pptable->DpmDescriptor[PPCLK_FCLK].Padding16);
2684
2685 dev_info(smu->adev->dev, "[PPCLK_DCLK_0]\n"
2686 " .VoltageMode = 0x%02x\n"
2687 " .SnapToDiscrete = 0x%02x\n"
2688 " .NumDiscreteLevels = 0x%02x\n"
2689 " .padding = 0x%02x\n"
2690 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
2691 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
2692 " .SsFmin = 0x%04x\n"
2693 " .Padding_16 = 0x%04x\n",
2694 pptable->DpmDescriptor[PPCLK_DCLK_0].VoltageMode,
2695 pptable->DpmDescriptor[PPCLK_DCLK_0].SnapToDiscrete,
2696 pptable->DpmDescriptor[PPCLK_DCLK_0].NumDiscreteLevels,
2697 pptable->DpmDescriptor[PPCLK_DCLK_0].Padding,
2698 pptable->DpmDescriptor[PPCLK_DCLK_0].ConversionToAvfsClk.m,
2699 pptable->DpmDescriptor[PPCLK_DCLK_0].ConversionToAvfsClk.b,
2700 pptable->DpmDescriptor[PPCLK_DCLK_0].SsCurve.a,
2701 pptable->DpmDescriptor[PPCLK_DCLK_0].SsCurve.b,
2702 pptable->DpmDescriptor[PPCLK_DCLK_0].SsCurve.c,
2703 pptable->DpmDescriptor[PPCLK_DCLK_0].SsFmin,
2704 pptable->DpmDescriptor[PPCLK_DCLK_0].Padding16);
2705
2706 dev_info(smu->adev->dev, "[PPCLK_VCLK_0]\n"
2707 " .VoltageMode = 0x%02x\n"
2708 " .SnapToDiscrete = 0x%02x\n"
2709 " .NumDiscreteLevels = 0x%02x\n"
2710 " .padding = 0x%02x\n"
2711 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
2712 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
2713 " .SsFmin = 0x%04x\n"
2714 " .Padding_16 = 0x%04x\n",
2715 pptable->DpmDescriptor[PPCLK_VCLK_0].VoltageMode,
2716 pptable->DpmDescriptor[PPCLK_VCLK_0].SnapToDiscrete,
2717 pptable->DpmDescriptor[PPCLK_VCLK_0].NumDiscreteLevels,
2718 pptable->DpmDescriptor[PPCLK_VCLK_0].Padding,
2719 pptable->DpmDescriptor[PPCLK_VCLK_0].ConversionToAvfsClk.m,
2720 pptable->DpmDescriptor[PPCLK_VCLK_0].ConversionToAvfsClk.b,
2721 pptable->DpmDescriptor[PPCLK_VCLK_0].SsCurve.a,
2722 pptable->DpmDescriptor[PPCLK_VCLK_0].SsCurve.b,
2723 pptable->DpmDescriptor[PPCLK_VCLK_0].SsCurve.c,
2724 pptable->DpmDescriptor[PPCLK_VCLK_0].SsFmin,
2725 pptable->DpmDescriptor[PPCLK_VCLK_0].Padding16);
2726
2727 dev_info(smu->adev->dev, "[PPCLK_DCLK_1]\n"
2728 " .VoltageMode = 0x%02x\n"
2729 " .SnapToDiscrete = 0x%02x\n"
2730 " .NumDiscreteLevels = 0x%02x\n"
2731 " .padding = 0x%02x\n"
2732 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
2733 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
2734 " .SsFmin = 0x%04x\n"
2735 " .Padding_16 = 0x%04x\n",
2736 pptable->DpmDescriptor[PPCLK_DCLK_1].VoltageMode,
2737 pptable->DpmDescriptor[PPCLK_DCLK_1].SnapToDiscrete,
2738 pptable->DpmDescriptor[PPCLK_DCLK_1].NumDiscreteLevels,
2739 pptable->DpmDescriptor[PPCLK_DCLK_1].Padding,
2740 pptable->DpmDescriptor[PPCLK_DCLK_1].ConversionToAvfsClk.m,
2741 pptable->DpmDescriptor[PPCLK_DCLK_1].ConversionToAvfsClk.b,
2742 pptable->DpmDescriptor[PPCLK_DCLK_1].SsCurve.a,
2743 pptable->DpmDescriptor[PPCLK_DCLK_1].SsCurve.b,
2744 pptable->DpmDescriptor[PPCLK_DCLK_1].SsCurve.c,
2745 pptable->DpmDescriptor[PPCLK_DCLK_1].SsFmin,
2746 pptable->DpmDescriptor[PPCLK_DCLK_1].Padding16);
2747
2748 dev_info(smu->adev->dev, "[PPCLK_VCLK_1]\n"
2749 " .VoltageMode = 0x%02x\n"
2750 " .SnapToDiscrete = 0x%02x\n"
2751 " .NumDiscreteLevels = 0x%02x\n"
2752 " .padding = 0x%02x\n"
2753 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
2754 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
2755 " .SsFmin = 0x%04x\n"
2756 " .Padding_16 = 0x%04x\n",
2757 pptable->DpmDescriptor[PPCLK_VCLK_1].VoltageMode,
2758 pptable->DpmDescriptor[PPCLK_VCLK_1].SnapToDiscrete,
2759 pptable->DpmDescriptor[PPCLK_VCLK_1].NumDiscreteLevels,
2760 pptable->DpmDescriptor[PPCLK_VCLK_1].Padding,
2761 pptable->DpmDescriptor[PPCLK_VCLK_1].ConversionToAvfsClk.m,
2762 pptable->DpmDescriptor[PPCLK_VCLK_1].ConversionToAvfsClk.b,
2763 pptable->DpmDescriptor[PPCLK_VCLK_1].SsCurve.a,
2764 pptable->DpmDescriptor[PPCLK_VCLK_1].SsCurve.b,
2765 pptable->DpmDescriptor[PPCLK_VCLK_1].SsCurve.c,
2766 pptable->DpmDescriptor[PPCLK_VCLK_1].SsFmin,
2767 pptable->DpmDescriptor[PPCLK_VCLK_1].Padding16);
2768
2769 dev_info(smu->adev->dev, "FreqTableGfx\n");
2770 for (i = 0; i < NUM_GFXCLK_DPM_LEVELS; i++)
2771 dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableGfx[i]);
2772
2773 dev_info(smu->adev->dev, "FreqTableVclk\n");
2774 for (i = 0; i < NUM_VCLK_DPM_LEVELS; i++)
2775 dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableVclk[i]);
2776
2777 dev_info(smu->adev->dev, "FreqTableDclk\n");
2778 for (i = 0; i < NUM_DCLK_DPM_LEVELS; i++)
2779 dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableDclk[i]);
2780
2781 dev_info(smu->adev->dev, "FreqTableSocclk\n");
2782 for (i = 0; i < NUM_SOCCLK_DPM_LEVELS; i++)
2783 dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableSocclk[i]);
2784
2785 dev_info(smu->adev->dev, "FreqTableUclk\n");
2786 for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
2787 dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableUclk[i]);
2788
2789 dev_info(smu->adev->dev, "FreqTableFclk\n");
2790 for (i = 0; i < NUM_FCLK_DPM_LEVELS; i++)
2791 dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableFclk[i]);
2792
2793 dev_info(smu->adev->dev, "DcModeMaxFreq\n");
2794 dev_info(smu->adev->dev, " .PPCLK_GFXCLK = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_GFXCLK]);
2795 dev_info(smu->adev->dev, " .PPCLK_SOCCLK = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_SOCCLK]);
2796 dev_info(smu->adev->dev, " .PPCLK_UCLK = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_UCLK]);
2797 dev_info(smu->adev->dev, " .PPCLK_FCLK = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_FCLK]);
2798 dev_info(smu->adev->dev, " .PPCLK_DCLK_0 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_DCLK_0]);
2799 dev_info(smu->adev->dev, " .PPCLK_VCLK_0 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_VCLK_0]);
2800 dev_info(smu->adev->dev, " .PPCLK_DCLK_1 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_DCLK_1]);
2801 dev_info(smu->adev->dev, " .PPCLK_VCLK_1 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_VCLK_1]);
2802
2803 dev_info(smu->adev->dev, "FreqTableUclkDiv\n");
2804 for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
2805 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->FreqTableUclkDiv[i]);
2806
2807 dev_info(smu->adev->dev, "FclkBoostFreq = 0x%x\n", pptable->FclkBoostFreq);
2808 dev_info(smu->adev->dev, "FclkParamPadding = 0x%x\n", pptable->FclkParamPadding);
2809
2810 dev_info(smu->adev->dev, "Mp0clkFreq\n");
2811 for (i = 0; i < NUM_MP0CLK_DPM_LEVELS; i++)
2812 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->Mp0clkFreq[i]);
2813
2814 dev_info(smu->adev->dev, "Mp0DpmVoltage\n");
2815 for (i = 0; i < NUM_MP0CLK_DPM_LEVELS; i++)
2816 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->Mp0DpmVoltage[i]);
2817
2818 dev_info(smu->adev->dev, "MemVddciVoltage\n");
2819 for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
2820 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->MemVddciVoltage[i]);
2821
2822 dev_info(smu->adev->dev, "MemMvddVoltage\n");
2823 for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
2824 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->MemMvddVoltage[i]);
2825
2826 dev_info(smu->adev->dev, "GfxclkFgfxoffEntry = 0x%x\n", pptable->GfxclkFgfxoffEntry);
2827 dev_info(smu->adev->dev, "GfxclkFinit = 0x%x\n", pptable->GfxclkFinit);
2828 dev_info(smu->adev->dev, "GfxclkFidle = 0x%x\n", pptable->GfxclkFidle);
2829 dev_info(smu->adev->dev, "GfxclkSource = 0x%x\n", pptable->GfxclkSource);
2830 dev_info(smu->adev->dev, "GfxclkPadding = 0x%x\n", pptable->GfxclkPadding);
2831
2832 dev_info(smu->adev->dev, "GfxGpoSubFeatureMask = 0x%x\n", pptable->GfxGpoSubFeatureMask);
2833
2834 dev_info(smu->adev->dev, "GfxGpoEnabledWorkPolicyMask = 0x%x\n", pptable->GfxGpoEnabledWorkPolicyMask);
2835 dev_info(smu->adev->dev, "GfxGpoDisabledWorkPolicyMask = 0x%x\n", pptable->GfxGpoDisabledWorkPolicyMask);
2836 dev_info(smu->adev->dev, "GfxGpoPadding[0] = 0x%x\n", pptable->GfxGpoPadding[0]);
2837 dev_info(smu->adev->dev, "GfxGpoVotingAllow = 0x%x\n", pptable->GfxGpoVotingAllow);
2838 dev_info(smu->adev->dev, "GfxGpoPadding32[0] = 0x%x\n", pptable->GfxGpoPadding32[0]);
2839 dev_info(smu->adev->dev, "GfxGpoPadding32[1] = 0x%x\n", pptable->GfxGpoPadding32[1]);
2840 dev_info(smu->adev->dev, "GfxGpoPadding32[2] = 0x%x\n", pptable->GfxGpoPadding32[2]);
2841 dev_info(smu->adev->dev, "GfxGpoPadding32[3] = 0x%x\n", pptable->GfxGpoPadding32[3]);
2842 dev_info(smu->adev->dev, "GfxDcsFopt = 0x%x\n", pptable->GfxDcsFopt);
2843 dev_info(smu->adev->dev, "GfxDcsFclkFopt = 0x%x\n", pptable->GfxDcsFclkFopt);
2844 dev_info(smu->adev->dev, "GfxDcsUclkFopt = 0x%x\n", pptable->GfxDcsUclkFopt);
2845
2846 dev_info(smu->adev->dev, "DcsGfxOffVoltage = 0x%x\n", pptable->DcsGfxOffVoltage);
2847 dev_info(smu->adev->dev, "DcsMinGfxOffTime = 0x%x\n", pptable->DcsMinGfxOffTime);
2848 dev_info(smu->adev->dev, "DcsMaxGfxOffTime = 0x%x\n", pptable->DcsMaxGfxOffTime);
2849 dev_info(smu->adev->dev, "DcsMinCreditAccum = 0x%x\n", pptable->DcsMinCreditAccum);
2850 dev_info(smu->adev->dev, "DcsExitHysteresis = 0x%x\n", pptable->DcsExitHysteresis);
2851 dev_info(smu->adev->dev, "DcsTimeout = 0x%x\n", pptable->DcsTimeout);
2852
2853 dev_info(smu->adev->dev, "DcsParamPadding[0] = 0x%x\n", pptable->DcsParamPadding[0]);
2854 dev_info(smu->adev->dev, "DcsParamPadding[1] = 0x%x\n", pptable->DcsParamPadding[1]);
2855 dev_info(smu->adev->dev, "DcsParamPadding[2] = 0x%x\n", pptable->DcsParamPadding[2]);
2856 dev_info(smu->adev->dev, "DcsParamPadding[3] = 0x%x\n", pptable->DcsParamPadding[3]);
2857 dev_info(smu->adev->dev, "DcsParamPadding[4] = 0x%x\n", pptable->DcsParamPadding[4]);
2858
2859 dev_info(smu->adev->dev, "FlopsPerByteTable\n");
2860 for (i = 0; i < RLC_PACE_TABLE_NUM_LEVELS; i++)
2861 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->FlopsPerByteTable[i]);
2862
2863 dev_info(smu->adev->dev, "LowestUclkReservedForUlv = 0x%x\n", pptable->LowestUclkReservedForUlv);
2864 dev_info(smu->adev->dev, "vddingMem[0] = 0x%x\n", pptable->PaddingMem[0]);
2865 dev_info(smu->adev->dev, "vddingMem[1] = 0x%x\n", pptable->PaddingMem[1]);
2866 dev_info(smu->adev->dev, "vddingMem[2] = 0x%x\n", pptable->PaddingMem[2]);
2867
2868 dev_info(smu->adev->dev, "UclkDpmPstates\n");
2869 for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
2870 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->UclkDpmPstates[i]);
2871
2872 dev_info(smu->adev->dev, "UclkDpmSrcFreqRange\n");
2873 dev_info(smu->adev->dev, " .Fmin = 0x%x\n",
2874 pptable->UclkDpmSrcFreqRange.Fmin);
2875 dev_info(smu->adev->dev, " .Fmax = 0x%x\n",
2876 pptable->UclkDpmSrcFreqRange.Fmax);
2877 dev_info(smu->adev->dev, "UclkDpmTargFreqRange\n");
2878 dev_info(smu->adev->dev, " .Fmin = 0x%x\n",
2879 pptable->UclkDpmTargFreqRange.Fmin);
2880 dev_info(smu->adev->dev, " .Fmax = 0x%x\n",
2881 pptable->UclkDpmTargFreqRange.Fmax);
2882 dev_info(smu->adev->dev, "UclkDpmMidstepFreq = 0x%x\n", pptable->UclkDpmMidstepFreq);
2883 dev_info(smu->adev->dev, "UclkMidstepPadding = 0x%x\n", pptable->UclkMidstepPadding);
2884
2885 dev_info(smu->adev->dev, "PcieGenSpeed\n");
2886 for (i = 0; i < NUM_LINK_LEVELS; i++)
2887 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->PcieGenSpeed[i]);
2888
2889 dev_info(smu->adev->dev, "PcieLaneCount\n");
2890 for (i = 0; i < NUM_LINK_LEVELS; i++)
2891 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->PcieLaneCount[i]);
2892
2893 dev_info(smu->adev->dev, "LclkFreq\n");
2894 for (i = 0; i < NUM_LINK_LEVELS; i++)
2895 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->LclkFreq[i]);
2896
2897 dev_info(smu->adev->dev, "FanStopTemp = 0x%x\n", pptable->FanStopTemp);
2898 dev_info(smu->adev->dev, "FanStartTemp = 0x%x\n", pptable->FanStartTemp);
2899
2900 dev_info(smu->adev->dev, "FanGain\n");
2901 for (i = 0; i < TEMP_COUNT; i++)
2902 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->FanGain[i]);
2903
2904 dev_info(smu->adev->dev, "FanPwmMin = 0x%x\n", pptable->FanPwmMin);
2905 dev_info(smu->adev->dev, "FanAcousticLimitRpm = 0x%x\n", pptable->FanAcousticLimitRpm);
2906 dev_info(smu->adev->dev, "FanThrottlingRpm = 0x%x\n", pptable->FanThrottlingRpm);
2907 dev_info(smu->adev->dev, "FanMaximumRpm = 0x%x\n", pptable->FanMaximumRpm);
2908 dev_info(smu->adev->dev, "MGpuFanBoostLimitRpm = 0x%x\n", pptable->MGpuFanBoostLimitRpm);
2909 dev_info(smu->adev->dev, "FanTargetTemperature = 0x%x\n", pptable->FanTargetTemperature);
2910 dev_info(smu->adev->dev, "FanTargetGfxclk = 0x%x\n", pptable->FanTargetGfxclk);
2911 dev_info(smu->adev->dev, "FanPadding16 = 0x%x\n", pptable->FanPadding16);
2912 dev_info(smu->adev->dev, "FanTempInputSelect = 0x%x\n", pptable->FanTempInputSelect);
2913 dev_info(smu->adev->dev, "FanPadding = 0x%x\n", pptable->FanPadding);
2914 dev_info(smu->adev->dev, "FanZeroRpmEnable = 0x%x\n", pptable->FanZeroRpmEnable);
2915 dev_info(smu->adev->dev, "FanTachEdgePerRev = 0x%x\n", pptable->FanTachEdgePerRev);
2916
2917 dev_info(smu->adev->dev, "FuzzyFan_ErrorSetDelta = 0x%x\n", pptable->FuzzyFan_ErrorSetDelta);
2918 dev_info(smu->adev->dev, "FuzzyFan_ErrorRateSetDelta = 0x%x\n", pptable->FuzzyFan_ErrorRateSetDelta);
2919 dev_info(smu->adev->dev, "FuzzyFan_PwmSetDelta = 0x%x\n", pptable->FuzzyFan_PwmSetDelta);
2920 dev_info(smu->adev->dev, "FuzzyFan_Reserved = 0x%x\n", pptable->FuzzyFan_Reserved);
2921
2922 dev_info(smu->adev->dev, "OverrideAvfsGb[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->OverrideAvfsGb[AVFS_VOLTAGE_GFX]);
2923 dev_info(smu->adev->dev, "OverrideAvfsGb[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->OverrideAvfsGb[AVFS_VOLTAGE_SOC]);
2924 dev_info(smu->adev->dev, "dBtcGbGfxDfllModelSelect = 0x%x\n", pptable->dBtcGbGfxDfllModelSelect);
2925 dev_info(smu->adev->dev, "Padding8_Avfs = 0x%x\n", pptable->Padding8_Avfs);
2926
2927 dev_info(smu->adev->dev, "qAvfsGb[AVFS_VOLTAGE_GFX]{a = 0x%x b = 0x%x c = 0x%x}\n",
2928 pptable->qAvfsGb[AVFS_VOLTAGE_GFX].a,
2929 pptable->qAvfsGb[AVFS_VOLTAGE_GFX].b,
2930 pptable->qAvfsGb[AVFS_VOLTAGE_GFX].c);
2931 dev_info(smu->adev->dev, "qAvfsGb[AVFS_VOLTAGE_SOC]{a = 0x%x b = 0x%x c = 0x%x}\n",
2932 pptable->qAvfsGb[AVFS_VOLTAGE_SOC].a,
2933 pptable->qAvfsGb[AVFS_VOLTAGE_SOC].b,
2934 pptable->qAvfsGb[AVFS_VOLTAGE_SOC].c);
2935 dev_info(smu->adev->dev, "dBtcGbGfxPll{a = 0x%x b = 0x%x c = 0x%x}\n",
2936 pptable->dBtcGbGfxPll.a,
2937 pptable->dBtcGbGfxPll.b,
2938 pptable->dBtcGbGfxPll.c);
2939 dev_info(smu->adev->dev, "dBtcGbGfxAfll{a = 0x%x b = 0x%x c = 0x%x}\n",
2940 pptable->dBtcGbGfxDfll.a,
2941 pptable->dBtcGbGfxDfll.b,
2942 pptable->dBtcGbGfxDfll.c);
2943 dev_info(smu->adev->dev, "dBtcGbSoc{a = 0x%x b = 0x%x c = 0x%x}\n",
2944 pptable->dBtcGbSoc.a,
2945 pptable->dBtcGbSoc.b,
2946 pptable->dBtcGbSoc.c);
2947 dev_info(smu->adev->dev, "qAgingGb[AVFS_VOLTAGE_GFX]{m = 0x%x b = 0x%x}\n",
2948 pptable->qAgingGb[AVFS_VOLTAGE_GFX].m,
2949 pptable->qAgingGb[AVFS_VOLTAGE_GFX].b);
2950 dev_info(smu->adev->dev, "qAgingGb[AVFS_VOLTAGE_SOC]{m = 0x%x b = 0x%x}\n",
2951 pptable->qAgingGb[AVFS_VOLTAGE_SOC].m,
2952 pptable->qAgingGb[AVFS_VOLTAGE_SOC].b);
2953
2954 dev_info(smu->adev->dev, "PiecewiseLinearDroopIntGfxDfll\n");
2955 for (i = 0; i < NUM_PIECE_WISE_LINEAR_DROOP_MODEL_VF_POINTS; i++) {
2956 dev_info(smu->adev->dev, " Fset[%d] = 0x%x\n",
2957 i, pptable->PiecewiseLinearDroopIntGfxDfll.Fset[i]);
2958 dev_info(smu->adev->dev, " Vdroop[%d] = 0x%x\n",
2959 i, pptable->PiecewiseLinearDroopIntGfxDfll.Vdroop[i]);
2960 }
2961
2962 dev_info(smu->adev->dev, "qStaticVoltageOffset[AVFS_VOLTAGE_GFX]{a = 0x%x b = 0x%x c = 0x%x}\n",
2963 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].a,
2964 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].b,
2965 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].c);
2966 dev_info(smu->adev->dev, "qStaticVoltageOffset[AVFS_VOLTAGE_SOC]{a = 0x%x b = 0x%x c = 0x%x}\n",
2967 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].a,
2968 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].b,
2969 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].c);
2970
2971 dev_info(smu->adev->dev, "DcTol[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcTol[AVFS_VOLTAGE_GFX]);
2972 dev_info(smu->adev->dev, "DcTol[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcTol[AVFS_VOLTAGE_SOC]);
2973
2974 dev_info(smu->adev->dev, "DcBtcEnabled[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcEnabled[AVFS_VOLTAGE_GFX]);
2975 dev_info(smu->adev->dev, "DcBtcEnabled[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcEnabled[AVFS_VOLTAGE_SOC]);
2976 dev_info(smu->adev->dev, "Padding8_GfxBtc[0] = 0x%x\n", pptable->Padding8_GfxBtc[0]);
2977 dev_info(smu->adev->dev, "Padding8_GfxBtc[1] = 0x%x\n", pptable->Padding8_GfxBtc[1]);
2978
2979 dev_info(smu->adev->dev, "DcBtcMin[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcMin[AVFS_VOLTAGE_GFX]);
2980 dev_info(smu->adev->dev, "DcBtcMin[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcMin[AVFS_VOLTAGE_SOC]);
2981 dev_info(smu->adev->dev, "DcBtcMax[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcMax[AVFS_VOLTAGE_GFX]);
2982 dev_info(smu->adev->dev, "DcBtcMax[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcMax[AVFS_VOLTAGE_SOC]);
2983
2984 dev_info(smu->adev->dev, "DcBtcGb[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcGb[AVFS_VOLTAGE_GFX]);
2985 dev_info(smu->adev->dev, "DcBtcGb[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcGb[AVFS_VOLTAGE_SOC]);
2986
2987 dev_info(smu->adev->dev, "XgmiDpmPstates\n");
2988 for (i = 0; i < NUM_XGMI_LEVELS; i++)
2989 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->XgmiDpmPstates[i]);
2990 dev_info(smu->adev->dev, "XgmiDpmSpare[0] = 0x%02x\n", pptable->XgmiDpmSpare[0]);
2991 dev_info(smu->adev->dev, "XgmiDpmSpare[1] = 0x%02x\n", pptable->XgmiDpmSpare[1]);
2992
2993 dev_info(smu->adev->dev, "DebugOverrides = 0x%x\n", pptable->DebugOverrides);
2994 dev_info(smu->adev->dev, "ReservedEquation0{a = 0x%x b = 0x%x c = 0x%x}\n",
2995 pptable->ReservedEquation0.a,
2996 pptable->ReservedEquation0.b,
2997 pptable->ReservedEquation0.c);
2998 dev_info(smu->adev->dev, "ReservedEquation1{a = 0x%x b = 0x%x c = 0x%x}\n",
2999 pptable->ReservedEquation1.a,
3000 pptable->ReservedEquation1.b,
3001 pptable->ReservedEquation1.c);
3002 dev_info(smu->adev->dev, "ReservedEquation2{a = 0x%x b = 0x%x c = 0x%x}\n",
3003 pptable->ReservedEquation2.a,
3004 pptable->ReservedEquation2.b,
3005 pptable->ReservedEquation2.c);
3006 dev_info(smu->adev->dev, "ReservedEquation3{a = 0x%x b = 0x%x c = 0x%x}\n",
3007 pptable->ReservedEquation3.a,
3008 pptable->ReservedEquation3.b,
3009 pptable->ReservedEquation3.c);
3010
3011 dev_info(smu->adev->dev, "SkuReserved[0] = 0x%x\n", pptable->SkuReserved[0]);
3012 dev_info(smu->adev->dev, "SkuReserved[1] = 0x%x\n", pptable->SkuReserved[1]);
3013 dev_info(smu->adev->dev, "SkuReserved[2] = 0x%x\n", pptable->SkuReserved[2]);
3014 dev_info(smu->adev->dev, "SkuReserved[3] = 0x%x\n", pptable->SkuReserved[3]);
3015 dev_info(smu->adev->dev, "SkuReserved[4] = 0x%x\n", pptable->SkuReserved[4]);
3016 dev_info(smu->adev->dev, "SkuReserved[5] = 0x%x\n", pptable->SkuReserved[5]);
3017 dev_info(smu->adev->dev, "SkuReserved[6] = 0x%x\n", pptable->SkuReserved[6]);
3018 dev_info(smu->adev->dev, "SkuReserved[7] = 0x%x\n", pptable->SkuReserved[7]);
3019
3020 dev_info(smu->adev->dev, "GamingClk[0] = 0x%x\n", pptable->GamingClk[0]);
3021 dev_info(smu->adev->dev, "GamingClk[1] = 0x%x\n", pptable->GamingClk[1]);
3022 dev_info(smu->adev->dev, "GamingClk[2] = 0x%x\n", pptable->GamingClk[2]);
3023 dev_info(smu->adev->dev, "GamingClk[3] = 0x%x\n", pptable->GamingClk[3]);
3024 dev_info(smu->adev->dev, "GamingClk[4] = 0x%x\n", pptable->GamingClk[4]);
3025 dev_info(smu->adev->dev, "GamingClk[5] = 0x%x\n", pptable->GamingClk[5]);
3026
3027 for (i = 0; i < NUM_I2C_CONTROLLERS; i++) {
3028 dev_info(smu->adev->dev, "I2cControllers[%d]:\n", i);
3029 dev_info(smu->adev->dev, " .Enabled = 0x%x\n",
3030 pptable->I2cControllers[i].Enabled);
3031 dev_info(smu->adev->dev, " .Speed = 0x%x\n",
3032 pptable->I2cControllers[i].Speed);
3033 dev_info(smu->adev->dev, " .SlaveAddress = 0x%x\n",
3034 pptable->I2cControllers[i].SlaveAddress);
3035 dev_info(smu->adev->dev, " .ControllerPort = 0x%x\n",
3036 pptable->I2cControllers[i].ControllerPort);
3037 dev_info(smu->adev->dev, " .ControllerName = 0x%x\n",
3038 pptable->I2cControllers[i].ControllerName);
3039 dev_info(smu->adev->dev, " .ThermalThrottler = 0x%x\n",
3040 pptable->I2cControllers[i].ThermalThrotter);
3041 dev_info(smu->adev->dev, " .I2cProtocol = 0x%x\n",
3042 pptable->I2cControllers[i].I2cProtocol);
3043 dev_info(smu->adev->dev, " .PaddingConfig = 0x%x\n",
3044 pptable->I2cControllers[i].PaddingConfig);
3045 }
3046
3047 dev_info(smu->adev->dev, "GpioScl = 0x%x\n", pptable->GpioScl);
3048 dev_info(smu->adev->dev, "GpioSda = 0x%x\n", pptable->GpioSda);
3049 dev_info(smu->adev->dev, "FchUsbPdSlaveAddr = 0x%x\n", pptable->FchUsbPdSlaveAddr);
3050 dev_info(smu->adev->dev, "I2cSpare[0] = 0x%x\n", pptable->I2cSpare[0]);
3051
3052 dev_info(smu->adev->dev, "Board Parameters:\n");
3053 dev_info(smu->adev->dev, "VddGfxVrMapping = 0x%x\n", pptable->VddGfxVrMapping);
3054 dev_info(smu->adev->dev, "VddSocVrMapping = 0x%x\n", pptable->VddSocVrMapping);
3055 dev_info(smu->adev->dev, "VddMem0VrMapping = 0x%x\n", pptable->VddMem0VrMapping);
3056 dev_info(smu->adev->dev, "VddMem1VrMapping = 0x%x\n", pptable->VddMem1VrMapping);
3057 dev_info(smu->adev->dev, "GfxUlvPhaseSheddingMask = 0x%x\n", pptable->GfxUlvPhaseSheddingMask);
3058 dev_info(smu->adev->dev, "SocUlvPhaseSheddingMask = 0x%x\n", pptable->SocUlvPhaseSheddingMask);
3059 dev_info(smu->adev->dev, "VddciUlvPhaseSheddingMask = 0x%x\n", pptable->VddciUlvPhaseSheddingMask);
3060 dev_info(smu->adev->dev, "MvddUlvPhaseSheddingMask = 0x%x\n", pptable->MvddUlvPhaseSheddingMask);
3061
3062 dev_info(smu->adev->dev, "GfxMaxCurrent = 0x%x\n", pptable->GfxMaxCurrent);
3063 dev_info(smu->adev->dev, "GfxOffset = 0x%x\n", pptable->GfxOffset);
3064 dev_info(smu->adev->dev, "Padding_TelemetryGfx = 0x%x\n", pptable->Padding_TelemetryGfx);
3065
3066 dev_info(smu->adev->dev, "SocMaxCurrent = 0x%x\n", pptable->SocMaxCurrent);
3067 dev_info(smu->adev->dev, "SocOffset = 0x%x\n", pptable->SocOffset);
3068 dev_info(smu->adev->dev, "Padding_TelemetrySoc = 0x%x\n", pptable->Padding_TelemetrySoc);
3069
3070 dev_info(smu->adev->dev, "Mem0MaxCurrent = 0x%x\n", pptable->Mem0MaxCurrent);
3071 dev_info(smu->adev->dev, "Mem0Offset = 0x%x\n", pptable->Mem0Offset);
3072 dev_info(smu->adev->dev, "Padding_TelemetryMem0 = 0x%x\n", pptable->Padding_TelemetryMem0);
3073
3074 dev_info(smu->adev->dev, "Mem1MaxCurrent = 0x%x\n", pptable->Mem1MaxCurrent);
3075 dev_info(smu->adev->dev, "Mem1Offset = 0x%x\n", pptable->Mem1Offset);
3076 dev_info(smu->adev->dev, "Padding_TelemetryMem1 = 0x%x\n", pptable->Padding_TelemetryMem1);
3077
3078 dev_info(smu->adev->dev, "MvddRatio = 0x%x\n", pptable->MvddRatio);
3079
3080 dev_info(smu->adev->dev, "AcDcGpio = 0x%x\n", pptable->AcDcGpio);
3081 dev_info(smu->adev->dev, "AcDcPolarity = 0x%x\n", pptable->AcDcPolarity);
3082 dev_info(smu->adev->dev, "VR0HotGpio = 0x%x\n", pptable->VR0HotGpio);
3083 dev_info(smu->adev->dev, "VR0HotPolarity = 0x%x\n", pptable->VR0HotPolarity);
3084 dev_info(smu->adev->dev, "VR1HotGpio = 0x%x\n", pptable->VR1HotGpio);
3085 dev_info(smu->adev->dev, "VR1HotPolarity = 0x%x\n", pptable->VR1HotPolarity);
3086 dev_info(smu->adev->dev, "GthrGpio = 0x%x\n", pptable->GthrGpio);
3087 dev_info(smu->adev->dev, "GthrPolarity = 0x%x\n", pptable->GthrPolarity);
3088 dev_info(smu->adev->dev, "LedPin0 = 0x%x\n", pptable->LedPin0);
3089 dev_info(smu->adev->dev, "LedPin1 = 0x%x\n", pptable->LedPin1);
3090 dev_info(smu->adev->dev, "LedPin2 = 0x%x\n", pptable->LedPin2);
3091 dev_info(smu->adev->dev, "LedEnableMask = 0x%x\n", pptable->LedEnableMask);
3092 dev_info(smu->adev->dev, "LedPcie = 0x%x\n", pptable->LedPcie);
3093 dev_info(smu->adev->dev, "LedError = 0x%x\n", pptable->LedError);
3094 dev_info(smu->adev->dev, "LedSpare1[0] = 0x%x\n", pptable->LedSpare1[0]);
3095 dev_info(smu->adev->dev, "LedSpare1[1] = 0x%x\n", pptable->LedSpare1[1]);
3096
3097 dev_info(smu->adev->dev, "PllGfxclkSpreadEnabled = 0x%x\n", pptable->PllGfxclkSpreadEnabled);
3098 dev_info(smu->adev->dev, "PllGfxclkSpreadPercent = 0x%x\n", pptable->PllGfxclkSpreadPercent);
3099 dev_info(smu->adev->dev, "PllGfxclkSpreadFreq = 0x%x\n", pptable->PllGfxclkSpreadFreq);
3100
3101 dev_info(smu->adev->dev, "DfllGfxclkSpreadEnabled = 0x%x\n", pptable->DfllGfxclkSpreadEnabled);
3102 dev_info(smu->adev->dev, "DfllGfxclkSpreadPercent = 0x%x\n", pptable->DfllGfxclkSpreadPercent);
3103 dev_info(smu->adev->dev, "DfllGfxclkSpreadFreq = 0x%x\n", pptable->DfllGfxclkSpreadFreq);
3104
3105 dev_info(smu->adev->dev, "UclkSpreadPadding = 0x%x\n", pptable->UclkSpreadPadding);
3106 dev_info(smu->adev->dev, "UclkSpreadFreq = 0x%x\n", pptable->UclkSpreadFreq);
3107
3108 dev_info(smu->adev->dev, "FclkSpreadEnabled = 0x%x\n", pptable->FclkSpreadEnabled);
3109 dev_info(smu->adev->dev, "FclkSpreadPercent = 0x%x\n", pptable->FclkSpreadPercent);
3110 dev_info(smu->adev->dev, "FclkSpreadFreq = 0x%x\n", pptable->FclkSpreadFreq);
3111
3112 dev_info(smu->adev->dev, "MemoryChannelEnabled = 0x%x\n", pptable->MemoryChannelEnabled);
3113 dev_info(smu->adev->dev, "DramBitWidth = 0x%x\n", pptable->DramBitWidth);
3114 dev_info(smu->adev->dev, "PaddingMem1[0] = 0x%x\n", pptable->PaddingMem1[0]);
3115 dev_info(smu->adev->dev, "PaddingMem1[1] = 0x%x\n", pptable->PaddingMem1[1]);
3116 dev_info(smu->adev->dev, "PaddingMem1[2] = 0x%x\n", pptable->PaddingMem1[2]);
3117
3118 dev_info(smu->adev->dev, "TotalBoardPower = 0x%x\n", pptable->TotalBoardPower);
3119 dev_info(smu->adev->dev, "BoardPowerPadding = 0x%x\n", pptable->BoardPowerPadding);
3120
3121 dev_info(smu->adev->dev, "XgmiLinkSpeed\n");
3122 for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
3123 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->XgmiLinkSpeed[i]);
3124 dev_info(smu->adev->dev, "XgmiLinkWidth\n");
3125 for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
3126 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->XgmiLinkWidth[i]);
3127 dev_info(smu->adev->dev, "XgmiFclkFreq\n");
3128 for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
3129 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->XgmiFclkFreq[i]);
3130 dev_info(smu->adev->dev, "XgmiSocVoltage\n");
3131 for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
3132 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->XgmiSocVoltage[i]);
3133
3134 dev_info(smu->adev->dev, "HsrEnabled = 0x%x\n", pptable->HsrEnabled);
3135 dev_info(smu->adev->dev, "VddqOffEnabled = 0x%x\n", pptable->VddqOffEnabled);
3136 dev_info(smu->adev->dev, "PaddingUmcFlags[0] = 0x%x\n", pptable->PaddingUmcFlags[0]);
3137 dev_info(smu->adev->dev, "PaddingUmcFlags[1] = 0x%x\n", pptable->PaddingUmcFlags[1]);
3138
3139 dev_info(smu->adev->dev, "BoardReserved[0] = 0x%x\n", pptable->BoardReserved[0]);
3140 dev_info(smu->adev->dev, "BoardReserved[1] = 0x%x\n", pptable->BoardReserved[1]);
3141 dev_info(smu->adev->dev, "BoardReserved[2] = 0x%x\n", pptable->BoardReserved[2]);
3142 dev_info(smu->adev->dev, "BoardReserved[3] = 0x%x\n", pptable->BoardReserved[3]);
3143 dev_info(smu->adev->dev, "BoardReserved[4] = 0x%x\n", pptable->BoardReserved[4]);
3144 dev_info(smu->adev->dev, "BoardReserved[5] = 0x%x\n", pptable->BoardReserved[5]);
3145 dev_info(smu->adev->dev, "BoardReserved[6] = 0x%x\n", pptable->BoardReserved[6]);
3146 dev_info(smu->adev->dev, "BoardReserved[7] = 0x%x\n", pptable->BoardReserved[7]);
3147 dev_info(smu->adev->dev, "BoardReserved[8] = 0x%x\n", pptable->BoardReserved[8]);
3148 dev_info(smu->adev->dev, "BoardReserved[9] = 0x%x\n", pptable->BoardReserved[9]);
3149 dev_info(smu->adev->dev, "BoardReserved[10] = 0x%x\n", pptable->BoardReserved[10]);
3150
3151 dev_info(smu->adev->dev, "MmHubPadding[0] = 0x%x\n", pptable->MmHubPadding[0]);
3152 dev_info(smu->adev->dev, "MmHubPadding[1] = 0x%x\n", pptable->MmHubPadding[1]);
3153 dev_info(smu->adev->dev, "MmHubPadding[2] = 0x%x\n", pptable->MmHubPadding[2]);
3154 dev_info(smu->adev->dev, "MmHubPadding[3] = 0x%x\n", pptable->MmHubPadding[3]);
3155 dev_info(smu->adev->dev, "MmHubPadding[4] = 0x%x\n", pptable->MmHubPadding[4]);
3156 dev_info(smu->adev->dev, "MmHubPadding[5] = 0x%x\n", pptable->MmHubPadding[5]);
3157 dev_info(smu->adev->dev, "MmHubPadding[6] = 0x%x\n", pptable->MmHubPadding[6]);
3158 dev_info(smu->adev->dev, "MmHubPadding[7] = 0x%x\n", pptable->MmHubPadding[7]);
3159 }
3160
sienna_cichlid_dump_pptable(struct smu_context * smu)3161 static void sienna_cichlid_dump_pptable(struct smu_context *smu)
3162 {
3163 struct smu_table_context *table_context = &smu->smu_table;
3164 PPTable_t *pptable = table_context->driver_pptable;
3165 int i;
3166
3167 if (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) ==
3168 IP_VERSION(11, 0, 13)) {
3169 beige_goby_dump_pptable(smu);
3170 return;
3171 }
3172
3173 dev_info(smu->adev->dev, "Dumped PPTable:\n");
3174
3175 dev_info(smu->adev->dev, "Version = 0x%08x\n", pptable->Version);
3176 dev_info(smu->adev->dev, "FeaturesToRun[0] = 0x%08x\n", pptable->FeaturesToRun[0]);
3177 dev_info(smu->adev->dev, "FeaturesToRun[1] = 0x%08x\n", pptable->FeaturesToRun[1]);
3178
3179 for (i = 0; i < PPT_THROTTLER_COUNT; i++) {
3180 dev_info(smu->adev->dev, "SocketPowerLimitAc[%d] = 0x%x\n", i, pptable->SocketPowerLimitAc[i]);
3181 dev_info(smu->adev->dev, "SocketPowerLimitAcTau[%d] = 0x%x\n", i, pptable->SocketPowerLimitAcTau[i]);
3182 dev_info(smu->adev->dev, "SocketPowerLimitDc[%d] = 0x%x\n", i, pptable->SocketPowerLimitDc[i]);
3183 dev_info(smu->adev->dev, "SocketPowerLimitDcTau[%d] = 0x%x\n", i, pptable->SocketPowerLimitDcTau[i]);
3184 }
3185
3186 for (i = 0; i < TDC_THROTTLER_COUNT; i++) {
3187 dev_info(smu->adev->dev, "TdcLimit[%d] = 0x%x\n", i, pptable->TdcLimit[i]);
3188 dev_info(smu->adev->dev, "TdcLimitTau[%d] = 0x%x\n", i, pptable->TdcLimitTau[i]);
3189 }
3190
3191 for (i = 0; i < TEMP_COUNT; i++) {
3192 dev_info(smu->adev->dev, "TemperatureLimit[%d] = 0x%x\n", i, pptable->TemperatureLimit[i]);
3193 }
3194
3195 dev_info(smu->adev->dev, "FitLimit = 0x%x\n", pptable->FitLimit);
3196 dev_info(smu->adev->dev, "TotalPowerConfig = 0x%x\n", pptable->TotalPowerConfig);
3197 dev_info(smu->adev->dev, "TotalPowerPadding[0] = 0x%x\n", pptable->TotalPowerPadding[0]);
3198 dev_info(smu->adev->dev, "TotalPowerPadding[1] = 0x%x\n", pptable->TotalPowerPadding[1]);
3199 dev_info(smu->adev->dev, "TotalPowerPadding[2] = 0x%x\n", pptable->TotalPowerPadding[2]);
3200
3201 dev_info(smu->adev->dev, "ApccPlusResidencyLimit = 0x%x\n", pptable->ApccPlusResidencyLimit);
3202 for (i = 0; i < NUM_SMNCLK_DPM_LEVELS; i++) {
3203 dev_info(smu->adev->dev, "SmnclkDpmFreq[%d] = 0x%x\n", i, pptable->SmnclkDpmFreq[i]);
3204 dev_info(smu->adev->dev, "SmnclkDpmVoltage[%d] = 0x%x\n", i, pptable->SmnclkDpmVoltage[i]);
3205 }
3206 dev_info(smu->adev->dev, "ThrottlerControlMask = 0x%x\n", pptable->ThrottlerControlMask);
3207
3208 dev_info(smu->adev->dev, "FwDStateMask = 0x%x\n", pptable->FwDStateMask);
3209
3210 dev_info(smu->adev->dev, "UlvVoltageOffsetSoc = 0x%x\n", pptable->UlvVoltageOffsetSoc);
3211 dev_info(smu->adev->dev, "UlvVoltageOffsetGfx = 0x%x\n", pptable->UlvVoltageOffsetGfx);
3212 dev_info(smu->adev->dev, "MinVoltageUlvGfx = 0x%x\n", pptable->MinVoltageUlvGfx);
3213 dev_info(smu->adev->dev, "MinVoltageUlvSoc = 0x%x\n", pptable->MinVoltageUlvSoc);
3214
3215 dev_info(smu->adev->dev, "SocLIVmin = 0x%x\n", pptable->SocLIVmin);
3216 dev_info(smu->adev->dev, "PaddingLIVmin = 0x%x\n", pptable->PaddingLIVmin);
3217
3218 dev_info(smu->adev->dev, "GceaLinkMgrIdleThreshold = 0x%x\n", pptable->GceaLinkMgrIdleThreshold);
3219 dev_info(smu->adev->dev, "paddingRlcUlvParams[0] = 0x%x\n", pptable->paddingRlcUlvParams[0]);
3220 dev_info(smu->adev->dev, "paddingRlcUlvParams[1] = 0x%x\n", pptable->paddingRlcUlvParams[1]);
3221 dev_info(smu->adev->dev, "paddingRlcUlvParams[2] = 0x%x\n", pptable->paddingRlcUlvParams[2]);
3222
3223 dev_info(smu->adev->dev, "MinVoltageGfx = 0x%x\n", pptable->MinVoltageGfx);
3224 dev_info(smu->adev->dev, "MinVoltageSoc = 0x%x\n", pptable->MinVoltageSoc);
3225 dev_info(smu->adev->dev, "MaxVoltageGfx = 0x%x\n", pptable->MaxVoltageGfx);
3226 dev_info(smu->adev->dev, "MaxVoltageSoc = 0x%x\n", pptable->MaxVoltageSoc);
3227
3228 dev_info(smu->adev->dev, "LoadLineResistanceGfx = 0x%x\n", pptable->LoadLineResistanceGfx);
3229 dev_info(smu->adev->dev, "LoadLineResistanceSoc = 0x%x\n", pptable->LoadLineResistanceSoc);
3230
3231 dev_info(smu->adev->dev, "VDDGFX_TVmin = 0x%x\n", pptable->VDDGFX_TVmin);
3232 dev_info(smu->adev->dev, "VDDSOC_TVmin = 0x%x\n", pptable->VDDSOC_TVmin);
3233 dev_info(smu->adev->dev, "VDDGFX_Vmin_HiTemp = 0x%x\n", pptable->VDDGFX_Vmin_HiTemp);
3234 dev_info(smu->adev->dev, "VDDGFX_Vmin_LoTemp = 0x%x\n", pptable->VDDGFX_Vmin_LoTemp);
3235 dev_info(smu->adev->dev, "VDDSOC_Vmin_HiTemp = 0x%x\n", pptable->VDDSOC_Vmin_HiTemp);
3236 dev_info(smu->adev->dev, "VDDSOC_Vmin_LoTemp = 0x%x\n", pptable->VDDSOC_Vmin_LoTemp);
3237 dev_info(smu->adev->dev, "VDDGFX_TVminHystersis = 0x%x\n", pptable->VDDGFX_TVminHystersis);
3238 dev_info(smu->adev->dev, "VDDSOC_TVminHystersis = 0x%x\n", pptable->VDDSOC_TVminHystersis);
3239
3240 dev_info(smu->adev->dev, "[PPCLK_GFXCLK]\n"
3241 " .VoltageMode = 0x%02x\n"
3242 " .SnapToDiscrete = 0x%02x\n"
3243 " .NumDiscreteLevels = 0x%02x\n"
3244 " .padding = 0x%02x\n"
3245 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
3246 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
3247 " .SsFmin = 0x%04x\n"
3248 " .Padding_16 = 0x%04x\n",
3249 pptable->DpmDescriptor[PPCLK_GFXCLK].VoltageMode,
3250 pptable->DpmDescriptor[PPCLK_GFXCLK].SnapToDiscrete,
3251 pptable->DpmDescriptor[PPCLK_GFXCLK].NumDiscreteLevels,
3252 pptable->DpmDescriptor[PPCLK_GFXCLK].Padding,
3253 pptable->DpmDescriptor[PPCLK_GFXCLK].ConversionToAvfsClk.m,
3254 pptable->DpmDescriptor[PPCLK_GFXCLK].ConversionToAvfsClk.b,
3255 pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.a,
3256 pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.b,
3257 pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.c,
3258 pptable->DpmDescriptor[PPCLK_GFXCLK].SsFmin,
3259 pptable->DpmDescriptor[PPCLK_GFXCLK].Padding16);
3260
3261 dev_info(smu->adev->dev, "[PPCLK_SOCCLK]\n"
3262 " .VoltageMode = 0x%02x\n"
3263 " .SnapToDiscrete = 0x%02x\n"
3264 " .NumDiscreteLevels = 0x%02x\n"
3265 " .padding = 0x%02x\n"
3266 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
3267 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
3268 " .SsFmin = 0x%04x\n"
3269 " .Padding_16 = 0x%04x\n",
3270 pptable->DpmDescriptor[PPCLK_SOCCLK].VoltageMode,
3271 pptable->DpmDescriptor[PPCLK_SOCCLK].SnapToDiscrete,
3272 pptable->DpmDescriptor[PPCLK_SOCCLK].NumDiscreteLevels,
3273 pptable->DpmDescriptor[PPCLK_SOCCLK].Padding,
3274 pptable->DpmDescriptor[PPCLK_SOCCLK].ConversionToAvfsClk.m,
3275 pptable->DpmDescriptor[PPCLK_SOCCLK].ConversionToAvfsClk.b,
3276 pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.a,
3277 pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.b,
3278 pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.c,
3279 pptable->DpmDescriptor[PPCLK_SOCCLK].SsFmin,
3280 pptable->DpmDescriptor[PPCLK_SOCCLK].Padding16);
3281
3282 dev_info(smu->adev->dev, "[PPCLK_UCLK]\n"
3283 " .VoltageMode = 0x%02x\n"
3284 " .SnapToDiscrete = 0x%02x\n"
3285 " .NumDiscreteLevels = 0x%02x\n"
3286 " .padding = 0x%02x\n"
3287 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
3288 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
3289 " .SsFmin = 0x%04x\n"
3290 " .Padding_16 = 0x%04x\n",
3291 pptable->DpmDescriptor[PPCLK_UCLK].VoltageMode,
3292 pptable->DpmDescriptor[PPCLK_UCLK].SnapToDiscrete,
3293 pptable->DpmDescriptor[PPCLK_UCLK].NumDiscreteLevels,
3294 pptable->DpmDescriptor[PPCLK_UCLK].Padding,
3295 pptable->DpmDescriptor[PPCLK_UCLK].ConversionToAvfsClk.m,
3296 pptable->DpmDescriptor[PPCLK_UCLK].ConversionToAvfsClk.b,
3297 pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.a,
3298 pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.b,
3299 pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.c,
3300 pptable->DpmDescriptor[PPCLK_UCLK].SsFmin,
3301 pptable->DpmDescriptor[PPCLK_UCLK].Padding16);
3302
3303 dev_info(smu->adev->dev, "[PPCLK_FCLK]\n"
3304 " .VoltageMode = 0x%02x\n"
3305 " .SnapToDiscrete = 0x%02x\n"
3306 " .NumDiscreteLevels = 0x%02x\n"
3307 " .padding = 0x%02x\n"
3308 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
3309 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
3310 " .SsFmin = 0x%04x\n"
3311 " .Padding_16 = 0x%04x\n",
3312 pptable->DpmDescriptor[PPCLK_FCLK].VoltageMode,
3313 pptable->DpmDescriptor[PPCLK_FCLK].SnapToDiscrete,
3314 pptable->DpmDescriptor[PPCLK_FCLK].NumDiscreteLevels,
3315 pptable->DpmDescriptor[PPCLK_FCLK].Padding,
3316 pptable->DpmDescriptor[PPCLK_FCLK].ConversionToAvfsClk.m,
3317 pptable->DpmDescriptor[PPCLK_FCLK].ConversionToAvfsClk.b,
3318 pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.a,
3319 pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.b,
3320 pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.c,
3321 pptable->DpmDescriptor[PPCLK_FCLK].SsFmin,
3322 pptable->DpmDescriptor[PPCLK_FCLK].Padding16);
3323
3324 dev_info(smu->adev->dev, "[PPCLK_DCLK_0]\n"
3325 " .VoltageMode = 0x%02x\n"
3326 " .SnapToDiscrete = 0x%02x\n"
3327 " .NumDiscreteLevels = 0x%02x\n"
3328 " .padding = 0x%02x\n"
3329 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
3330 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
3331 " .SsFmin = 0x%04x\n"
3332 " .Padding_16 = 0x%04x\n",
3333 pptable->DpmDescriptor[PPCLK_DCLK_0].VoltageMode,
3334 pptable->DpmDescriptor[PPCLK_DCLK_0].SnapToDiscrete,
3335 pptable->DpmDescriptor[PPCLK_DCLK_0].NumDiscreteLevels,
3336 pptable->DpmDescriptor[PPCLK_DCLK_0].Padding,
3337 pptable->DpmDescriptor[PPCLK_DCLK_0].ConversionToAvfsClk.m,
3338 pptable->DpmDescriptor[PPCLK_DCLK_0].ConversionToAvfsClk.b,
3339 pptable->DpmDescriptor[PPCLK_DCLK_0].SsCurve.a,
3340 pptable->DpmDescriptor[PPCLK_DCLK_0].SsCurve.b,
3341 pptable->DpmDescriptor[PPCLK_DCLK_0].SsCurve.c,
3342 pptable->DpmDescriptor[PPCLK_DCLK_0].SsFmin,
3343 pptable->DpmDescriptor[PPCLK_DCLK_0].Padding16);
3344
3345 dev_info(smu->adev->dev, "[PPCLK_VCLK_0]\n"
3346 " .VoltageMode = 0x%02x\n"
3347 " .SnapToDiscrete = 0x%02x\n"
3348 " .NumDiscreteLevels = 0x%02x\n"
3349 " .padding = 0x%02x\n"
3350 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
3351 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
3352 " .SsFmin = 0x%04x\n"
3353 " .Padding_16 = 0x%04x\n",
3354 pptable->DpmDescriptor[PPCLK_VCLK_0].VoltageMode,
3355 pptable->DpmDescriptor[PPCLK_VCLK_0].SnapToDiscrete,
3356 pptable->DpmDescriptor[PPCLK_VCLK_0].NumDiscreteLevels,
3357 pptable->DpmDescriptor[PPCLK_VCLK_0].Padding,
3358 pptable->DpmDescriptor[PPCLK_VCLK_0].ConversionToAvfsClk.m,
3359 pptable->DpmDescriptor[PPCLK_VCLK_0].ConversionToAvfsClk.b,
3360 pptable->DpmDescriptor[PPCLK_VCLK_0].SsCurve.a,
3361 pptable->DpmDescriptor[PPCLK_VCLK_0].SsCurve.b,
3362 pptable->DpmDescriptor[PPCLK_VCLK_0].SsCurve.c,
3363 pptable->DpmDescriptor[PPCLK_VCLK_0].SsFmin,
3364 pptable->DpmDescriptor[PPCLK_VCLK_0].Padding16);
3365
3366 dev_info(smu->adev->dev, "[PPCLK_DCLK_1]\n"
3367 " .VoltageMode = 0x%02x\n"
3368 " .SnapToDiscrete = 0x%02x\n"
3369 " .NumDiscreteLevels = 0x%02x\n"
3370 " .padding = 0x%02x\n"
3371 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
3372 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
3373 " .SsFmin = 0x%04x\n"
3374 " .Padding_16 = 0x%04x\n",
3375 pptable->DpmDescriptor[PPCLK_DCLK_1].VoltageMode,
3376 pptable->DpmDescriptor[PPCLK_DCLK_1].SnapToDiscrete,
3377 pptable->DpmDescriptor[PPCLK_DCLK_1].NumDiscreteLevels,
3378 pptable->DpmDescriptor[PPCLK_DCLK_1].Padding,
3379 pptable->DpmDescriptor[PPCLK_DCLK_1].ConversionToAvfsClk.m,
3380 pptable->DpmDescriptor[PPCLK_DCLK_1].ConversionToAvfsClk.b,
3381 pptable->DpmDescriptor[PPCLK_DCLK_1].SsCurve.a,
3382 pptable->DpmDescriptor[PPCLK_DCLK_1].SsCurve.b,
3383 pptable->DpmDescriptor[PPCLK_DCLK_1].SsCurve.c,
3384 pptable->DpmDescriptor[PPCLK_DCLK_1].SsFmin,
3385 pptable->DpmDescriptor[PPCLK_DCLK_1].Padding16);
3386
3387 dev_info(smu->adev->dev, "[PPCLK_VCLK_1]\n"
3388 " .VoltageMode = 0x%02x\n"
3389 " .SnapToDiscrete = 0x%02x\n"
3390 " .NumDiscreteLevels = 0x%02x\n"
3391 " .padding = 0x%02x\n"
3392 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
3393 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
3394 " .SsFmin = 0x%04x\n"
3395 " .Padding_16 = 0x%04x\n",
3396 pptable->DpmDescriptor[PPCLK_VCLK_1].VoltageMode,
3397 pptable->DpmDescriptor[PPCLK_VCLK_1].SnapToDiscrete,
3398 pptable->DpmDescriptor[PPCLK_VCLK_1].NumDiscreteLevels,
3399 pptable->DpmDescriptor[PPCLK_VCLK_1].Padding,
3400 pptable->DpmDescriptor[PPCLK_VCLK_1].ConversionToAvfsClk.m,
3401 pptable->DpmDescriptor[PPCLK_VCLK_1].ConversionToAvfsClk.b,
3402 pptable->DpmDescriptor[PPCLK_VCLK_1].SsCurve.a,
3403 pptable->DpmDescriptor[PPCLK_VCLK_1].SsCurve.b,
3404 pptable->DpmDescriptor[PPCLK_VCLK_1].SsCurve.c,
3405 pptable->DpmDescriptor[PPCLK_VCLK_1].SsFmin,
3406 pptable->DpmDescriptor[PPCLK_VCLK_1].Padding16);
3407
3408 dev_info(smu->adev->dev, "FreqTableGfx\n");
3409 for (i = 0; i < NUM_GFXCLK_DPM_LEVELS; i++)
3410 dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableGfx[i]);
3411
3412 dev_info(smu->adev->dev, "FreqTableVclk\n");
3413 for (i = 0; i < NUM_VCLK_DPM_LEVELS; i++)
3414 dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableVclk[i]);
3415
3416 dev_info(smu->adev->dev, "FreqTableDclk\n");
3417 for (i = 0; i < NUM_DCLK_DPM_LEVELS; i++)
3418 dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableDclk[i]);
3419
3420 dev_info(smu->adev->dev, "FreqTableSocclk\n");
3421 for (i = 0; i < NUM_SOCCLK_DPM_LEVELS; i++)
3422 dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableSocclk[i]);
3423
3424 dev_info(smu->adev->dev, "FreqTableUclk\n");
3425 for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
3426 dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableUclk[i]);
3427
3428 dev_info(smu->adev->dev, "FreqTableFclk\n");
3429 for (i = 0; i < NUM_FCLK_DPM_LEVELS; i++)
3430 dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableFclk[i]);
3431
3432 dev_info(smu->adev->dev, "DcModeMaxFreq\n");
3433 dev_info(smu->adev->dev, " .PPCLK_GFXCLK = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_GFXCLK]);
3434 dev_info(smu->adev->dev, " .PPCLK_SOCCLK = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_SOCCLK]);
3435 dev_info(smu->adev->dev, " .PPCLK_UCLK = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_UCLK]);
3436 dev_info(smu->adev->dev, " .PPCLK_FCLK = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_FCLK]);
3437 dev_info(smu->adev->dev, " .PPCLK_DCLK_0 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_DCLK_0]);
3438 dev_info(smu->adev->dev, " .PPCLK_VCLK_0 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_VCLK_0]);
3439 dev_info(smu->adev->dev, " .PPCLK_DCLK_1 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_DCLK_1]);
3440 dev_info(smu->adev->dev, " .PPCLK_VCLK_1 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_VCLK_1]);
3441
3442 dev_info(smu->adev->dev, "FreqTableUclkDiv\n");
3443 for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
3444 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->FreqTableUclkDiv[i]);
3445
3446 dev_info(smu->adev->dev, "FclkBoostFreq = 0x%x\n", pptable->FclkBoostFreq);
3447 dev_info(smu->adev->dev, "FclkParamPadding = 0x%x\n", pptable->FclkParamPadding);
3448
3449 dev_info(smu->adev->dev, "Mp0clkFreq\n");
3450 for (i = 0; i < NUM_MP0CLK_DPM_LEVELS; i++)
3451 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->Mp0clkFreq[i]);
3452
3453 dev_info(smu->adev->dev, "Mp0DpmVoltage\n");
3454 for (i = 0; i < NUM_MP0CLK_DPM_LEVELS; i++)
3455 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->Mp0DpmVoltage[i]);
3456
3457 dev_info(smu->adev->dev, "MemVddciVoltage\n");
3458 for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
3459 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->MemVddciVoltage[i]);
3460
3461 dev_info(smu->adev->dev, "MemMvddVoltage\n");
3462 for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
3463 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->MemMvddVoltage[i]);
3464
3465 dev_info(smu->adev->dev, "GfxclkFgfxoffEntry = 0x%x\n", pptable->GfxclkFgfxoffEntry);
3466 dev_info(smu->adev->dev, "GfxclkFinit = 0x%x\n", pptable->GfxclkFinit);
3467 dev_info(smu->adev->dev, "GfxclkFidle = 0x%x\n", pptable->GfxclkFidle);
3468 dev_info(smu->adev->dev, "GfxclkSource = 0x%x\n", pptable->GfxclkSource);
3469 dev_info(smu->adev->dev, "GfxclkPadding = 0x%x\n", pptable->GfxclkPadding);
3470
3471 dev_info(smu->adev->dev, "GfxGpoSubFeatureMask = 0x%x\n", pptable->GfxGpoSubFeatureMask);
3472
3473 dev_info(smu->adev->dev, "GfxGpoEnabledWorkPolicyMask = 0x%x\n", pptable->GfxGpoEnabledWorkPolicyMask);
3474 dev_info(smu->adev->dev, "GfxGpoDisabledWorkPolicyMask = 0x%x\n", pptable->GfxGpoDisabledWorkPolicyMask);
3475 dev_info(smu->adev->dev, "GfxGpoPadding[0] = 0x%x\n", pptable->GfxGpoPadding[0]);
3476 dev_info(smu->adev->dev, "GfxGpoVotingAllow = 0x%x\n", pptable->GfxGpoVotingAllow);
3477 dev_info(smu->adev->dev, "GfxGpoPadding32[0] = 0x%x\n", pptable->GfxGpoPadding32[0]);
3478 dev_info(smu->adev->dev, "GfxGpoPadding32[1] = 0x%x\n", pptable->GfxGpoPadding32[1]);
3479 dev_info(smu->adev->dev, "GfxGpoPadding32[2] = 0x%x\n", pptable->GfxGpoPadding32[2]);
3480 dev_info(smu->adev->dev, "GfxGpoPadding32[3] = 0x%x\n", pptable->GfxGpoPadding32[3]);
3481 dev_info(smu->adev->dev, "GfxDcsFopt = 0x%x\n", pptable->GfxDcsFopt);
3482 dev_info(smu->adev->dev, "GfxDcsFclkFopt = 0x%x\n", pptable->GfxDcsFclkFopt);
3483 dev_info(smu->adev->dev, "GfxDcsUclkFopt = 0x%x\n", pptable->GfxDcsUclkFopt);
3484
3485 dev_info(smu->adev->dev, "DcsGfxOffVoltage = 0x%x\n", pptable->DcsGfxOffVoltage);
3486 dev_info(smu->adev->dev, "DcsMinGfxOffTime = 0x%x\n", pptable->DcsMinGfxOffTime);
3487 dev_info(smu->adev->dev, "DcsMaxGfxOffTime = 0x%x\n", pptable->DcsMaxGfxOffTime);
3488 dev_info(smu->adev->dev, "DcsMinCreditAccum = 0x%x\n", pptable->DcsMinCreditAccum);
3489 dev_info(smu->adev->dev, "DcsExitHysteresis = 0x%x\n", pptable->DcsExitHysteresis);
3490 dev_info(smu->adev->dev, "DcsTimeout = 0x%x\n", pptable->DcsTimeout);
3491
3492 dev_info(smu->adev->dev, "DcsParamPadding[0] = 0x%x\n", pptable->DcsParamPadding[0]);
3493 dev_info(smu->adev->dev, "DcsParamPadding[1] = 0x%x\n", pptable->DcsParamPadding[1]);
3494 dev_info(smu->adev->dev, "DcsParamPadding[2] = 0x%x\n", pptable->DcsParamPadding[2]);
3495 dev_info(smu->adev->dev, "DcsParamPadding[3] = 0x%x\n", pptable->DcsParamPadding[3]);
3496 dev_info(smu->adev->dev, "DcsParamPadding[4] = 0x%x\n", pptable->DcsParamPadding[4]);
3497
3498 dev_info(smu->adev->dev, "FlopsPerByteTable\n");
3499 for (i = 0; i < RLC_PACE_TABLE_NUM_LEVELS; i++)
3500 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->FlopsPerByteTable[i]);
3501
3502 dev_info(smu->adev->dev, "LowestUclkReservedForUlv = 0x%x\n", pptable->LowestUclkReservedForUlv);
3503 dev_info(smu->adev->dev, "vddingMem[0] = 0x%x\n", pptable->PaddingMem[0]);
3504 dev_info(smu->adev->dev, "vddingMem[1] = 0x%x\n", pptable->PaddingMem[1]);
3505 dev_info(smu->adev->dev, "vddingMem[2] = 0x%x\n", pptable->PaddingMem[2]);
3506
3507 dev_info(smu->adev->dev, "UclkDpmPstates\n");
3508 for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
3509 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->UclkDpmPstates[i]);
3510
3511 dev_info(smu->adev->dev, "UclkDpmSrcFreqRange\n");
3512 dev_info(smu->adev->dev, " .Fmin = 0x%x\n",
3513 pptable->UclkDpmSrcFreqRange.Fmin);
3514 dev_info(smu->adev->dev, " .Fmax = 0x%x\n",
3515 pptable->UclkDpmSrcFreqRange.Fmax);
3516 dev_info(smu->adev->dev, "UclkDpmTargFreqRange\n");
3517 dev_info(smu->adev->dev, " .Fmin = 0x%x\n",
3518 pptable->UclkDpmTargFreqRange.Fmin);
3519 dev_info(smu->adev->dev, " .Fmax = 0x%x\n",
3520 pptable->UclkDpmTargFreqRange.Fmax);
3521 dev_info(smu->adev->dev, "UclkDpmMidstepFreq = 0x%x\n", pptable->UclkDpmMidstepFreq);
3522 dev_info(smu->adev->dev, "UclkMidstepPadding = 0x%x\n", pptable->UclkMidstepPadding);
3523
3524 dev_info(smu->adev->dev, "PcieGenSpeed\n");
3525 for (i = 0; i < NUM_LINK_LEVELS; i++)
3526 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->PcieGenSpeed[i]);
3527
3528 dev_info(smu->adev->dev, "PcieLaneCount\n");
3529 for (i = 0; i < NUM_LINK_LEVELS; i++)
3530 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->PcieLaneCount[i]);
3531
3532 dev_info(smu->adev->dev, "LclkFreq\n");
3533 for (i = 0; i < NUM_LINK_LEVELS; i++)
3534 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->LclkFreq[i]);
3535
3536 dev_info(smu->adev->dev, "FanStopTemp = 0x%x\n", pptable->FanStopTemp);
3537 dev_info(smu->adev->dev, "FanStartTemp = 0x%x\n", pptable->FanStartTemp);
3538
3539 dev_info(smu->adev->dev, "FanGain\n");
3540 for (i = 0; i < TEMP_COUNT; i++)
3541 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->FanGain[i]);
3542
3543 dev_info(smu->adev->dev, "FanPwmMin = 0x%x\n", pptable->FanPwmMin);
3544 dev_info(smu->adev->dev, "FanAcousticLimitRpm = 0x%x\n", pptable->FanAcousticLimitRpm);
3545 dev_info(smu->adev->dev, "FanThrottlingRpm = 0x%x\n", pptable->FanThrottlingRpm);
3546 dev_info(smu->adev->dev, "FanMaximumRpm = 0x%x\n", pptable->FanMaximumRpm);
3547 dev_info(smu->adev->dev, "MGpuFanBoostLimitRpm = 0x%x\n", pptable->MGpuFanBoostLimitRpm);
3548 dev_info(smu->adev->dev, "FanTargetTemperature = 0x%x\n", pptable->FanTargetTemperature);
3549 dev_info(smu->adev->dev, "FanTargetGfxclk = 0x%x\n", pptable->FanTargetGfxclk);
3550 dev_info(smu->adev->dev, "FanPadding16 = 0x%x\n", pptable->FanPadding16);
3551 dev_info(smu->adev->dev, "FanTempInputSelect = 0x%x\n", pptable->FanTempInputSelect);
3552 dev_info(smu->adev->dev, "FanPadding = 0x%x\n", pptable->FanPadding);
3553 dev_info(smu->adev->dev, "FanZeroRpmEnable = 0x%x\n", pptable->FanZeroRpmEnable);
3554 dev_info(smu->adev->dev, "FanTachEdgePerRev = 0x%x\n", pptable->FanTachEdgePerRev);
3555
3556 dev_info(smu->adev->dev, "FuzzyFan_ErrorSetDelta = 0x%x\n", pptable->FuzzyFan_ErrorSetDelta);
3557 dev_info(smu->adev->dev, "FuzzyFan_ErrorRateSetDelta = 0x%x\n", pptable->FuzzyFan_ErrorRateSetDelta);
3558 dev_info(smu->adev->dev, "FuzzyFan_PwmSetDelta = 0x%x\n", pptable->FuzzyFan_PwmSetDelta);
3559 dev_info(smu->adev->dev, "FuzzyFan_Reserved = 0x%x\n", pptable->FuzzyFan_Reserved);
3560
3561 dev_info(smu->adev->dev, "OverrideAvfsGb[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->OverrideAvfsGb[AVFS_VOLTAGE_GFX]);
3562 dev_info(smu->adev->dev, "OverrideAvfsGb[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->OverrideAvfsGb[AVFS_VOLTAGE_SOC]);
3563 dev_info(smu->adev->dev, "dBtcGbGfxDfllModelSelect = 0x%x\n", pptable->dBtcGbGfxDfllModelSelect);
3564 dev_info(smu->adev->dev, "Padding8_Avfs = 0x%x\n", pptable->Padding8_Avfs);
3565
3566 dev_info(smu->adev->dev, "qAvfsGb[AVFS_VOLTAGE_GFX]{a = 0x%x b = 0x%x c = 0x%x}\n",
3567 pptable->qAvfsGb[AVFS_VOLTAGE_GFX].a,
3568 pptable->qAvfsGb[AVFS_VOLTAGE_GFX].b,
3569 pptable->qAvfsGb[AVFS_VOLTAGE_GFX].c);
3570 dev_info(smu->adev->dev, "qAvfsGb[AVFS_VOLTAGE_SOC]{a = 0x%x b = 0x%x c = 0x%x}\n",
3571 pptable->qAvfsGb[AVFS_VOLTAGE_SOC].a,
3572 pptable->qAvfsGb[AVFS_VOLTAGE_SOC].b,
3573 pptable->qAvfsGb[AVFS_VOLTAGE_SOC].c);
3574 dev_info(smu->adev->dev, "dBtcGbGfxPll{a = 0x%x b = 0x%x c = 0x%x}\n",
3575 pptable->dBtcGbGfxPll.a,
3576 pptable->dBtcGbGfxPll.b,
3577 pptable->dBtcGbGfxPll.c);
3578 dev_info(smu->adev->dev, "dBtcGbGfxAfll{a = 0x%x b = 0x%x c = 0x%x}\n",
3579 pptable->dBtcGbGfxDfll.a,
3580 pptable->dBtcGbGfxDfll.b,
3581 pptable->dBtcGbGfxDfll.c);
3582 dev_info(smu->adev->dev, "dBtcGbSoc{a = 0x%x b = 0x%x c = 0x%x}\n",
3583 pptable->dBtcGbSoc.a,
3584 pptable->dBtcGbSoc.b,
3585 pptable->dBtcGbSoc.c);
3586 dev_info(smu->adev->dev, "qAgingGb[AVFS_VOLTAGE_GFX]{m = 0x%x b = 0x%x}\n",
3587 pptable->qAgingGb[AVFS_VOLTAGE_GFX].m,
3588 pptable->qAgingGb[AVFS_VOLTAGE_GFX].b);
3589 dev_info(smu->adev->dev, "qAgingGb[AVFS_VOLTAGE_SOC]{m = 0x%x b = 0x%x}\n",
3590 pptable->qAgingGb[AVFS_VOLTAGE_SOC].m,
3591 pptable->qAgingGb[AVFS_VOLTAGE_SOC].b);
3592
3593 dev_info(smu->adev->dev, "PiecewiseLinearDroopIntGfxDfll\n");
3594 for (i = 0; i < NUM_PIECE_WISE_LINEAR_DROOP_MODEL_VF_POINTS; i++) {
3595 dev_info(smu->adev->dev, " Fset[%d] = 0x%x\n",
3596 i, pptable->PiecewiseLinearDroopIntGfxDfll.Fset[i]);
3597 dev_info(smu->adev->dev, " Vdroop[%d] = 0x%x\n",
3598 i, pptable->PiecewiseLinearDroopIntGfxDfll.Vdroop[i]);
3599 }
3600
3601 dev_info(smu->adev->dev, "qStaticVoltageOffset[AVFS_VOLTAGE_GFX]{a = 0x%x b = 0x%x c = 0x%x}\n",
3602 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].a,
3603 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].b,
3604 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].c);
3605 dev_info(smu->adev->dev, "qStaticVoltageOffset[AVFS_VOLTAGE_SOC]{a = 0x%x b = 0x%x c = 0x%x}\n",
3606 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].a,
3607 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].b,
3608 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].c);
3609
3610 dev_info(smu->adev->dev, "DcTol[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcTol[AVFS_VOLTAGE_GFX]);
3611 dev_info(smu->adev->dev, "DcTol[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcTol[AVFS_VOLTAGE_SOC]);
3612
3613 dev_info(smu->adev->dev, "DcBtcEnabled[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcEnabled[AVFS_VOLTAGE_GFX]);
3614 dev_info(smu->adev->dev, "DcBtcEnabled[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcEnabled[AVFS_VOLTAGE_SOC]);
3615 dev_info(smu->adev->dev, "Padding8_GfxBtc[0] = 0x%x\n", pptable->Padding8_GfxBtc[0]);
3616 dev_info(smu->adev->dev, "Padding8_GfxBtc[1] = 0x%x\n", pptable->Padding8_GfxBtc[1]);
3617
3618 dev_info(smu->adev->dev, "DcBtcMin[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcMin[AVFS_VOLTAGE_GFX]);
3619 dev_info(smu->adev->dev, "DcBtcMin[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcMin[AVFS_VOLTAGE_SOC]);
3620 dev_info(smu->adev->dev, "DcBtcMax[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcMax[AVFS_VOLTAGE_GFX]);
3621 dev_info(smu->adev->dev, "DcBtcMax[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcMax[AVFS_VOLTAGE_SOC]);
3622
3623 dev_info(smu->adev->dev, "DcBtcGb[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcGb[AVFS_VOLTAGE_GFX]);
3624 dev_info(smu->adev->dev, "DcBtcGb[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcGb[AVFS_VOLTAGE_SOC]);
3625
3626 dev_info(smu->adev->dev, "XgmiDpmPstates\n");
3627 for (i = 0; i < NUM_XGMI_LEVELS; i++)
3628 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->XgmiDpmPstates[i]);
3629 dev_info(smu->adev->dev, "XgmiDpmSpare[0] = 0x%02x\n", pptable->XgmiDpmSpare[0]);
3630 dev_info(smu->adev->dev, "XgmiDpmSpare[1] = 0x%02x\n", pptable->XgmiDpmSpare[1]);
3631
3632 dev_info(smu->adev->dev, "DebugOverrides = 0x%x\n", pptable->DebugOverrides);
3633 dev_info(smu->adev->dev, "ReservedEquation0{a = 0x%x b = 0x%x c = 0x%x}\n",
3634 pptable->ReservedEquation0.a,
3635 pptable->ReservedEquation0.b,
3636 pptable->ReservedEquation0.c);
3637 dev_info(smu->adev->dev, "ReservedEquation1{a = 0x%x b = 0x%x c = 0x%x}\n",
3638 pptable->ReservedEquation1.a,
3639 pptable->ReservedEquation1.b,
3640 pptable->ReservedEquation1.c);
3641 dev_info(smu->adev->dev, "ReservedEquation2{a = 0x%x b = 0x%x c = 0x%x}\n",
3642 pptable->ReservedEquation2.a,
3643 pptable->ReservedEquation2.b,
3644 pptable->ReservedEquation2.c);
3645 dev_info(smu->adev->dev, "ReservedEquation3{a = 0x%x b = 0x%x c = 0x%x}\n",
3646 pptable->ReservedEquation3.a,
3647 pptable->ReservedEquation3.b,
3648 pptable->ReservedEquation3.c);
3649
3650 dev_info(smu->adev->dev, "SkuReserved[0] = 0x%x\n", pptable->SkuReserved[0]);
3651 dev_info(smu->adev->dev, "SkuReserved[1] = 0x%x\n", pptable->SkuReserved[1]);
3652 dev_info(smu->adev->dev, "SkuReserved[2] = 0x%x\n", pptable->SkuReserved[2]);
3653 dev_info(smu->adev->dev, "SkuReserved[3] = 0x%x\n", pptable->SkuReserved[3]);
3654 dev_info(smu->adev->dev, "SkuReserved[4] = 0x%x\n", pptable->SkuReserved[4]);
3655 dev_info(smu->adev->dev, "SkuReserved[5] = 0x%x\n", pptable->SkuReserved[5]);
3656 dev_info(smu->adev->dev, "SkuReserved[6] = 0x%x\n", pptable->SkuReserved[6]);
3657 dev_info(smu->adev->dev, "SkuReserved[7] = 0x%x\n", pptable->SkuReserved[7]);
3658
3659 dev_info(smu->adev->dev, "GamingClk[0] = 0x%x\n", pptable->GamingClk[0]);
3660 dev_info(smu->adev->dev, "GamingClk[1] = 0x%x\n", pptable->GamingClk[1]);
3661 dev_info(smu->adev->dev, "GamingClk[2] = 0x%x\n", pptable->GamingClk[2]);
3662 dev_info(smu->adev->dev, "GamingClk[3] = 0x%x\n", pptable->GamingClk[3]);
3663 dev_info(smu->adev->dev, "GamingClk[4] = 0x%x\n", pptable->GamingClk[4]);
3664 dev_info(smu->adev->dev, "GamingClk[5] = 0x%x\n", pptable->GamingClk[5]);
3665
3666 for (i = 0; i < NUM_I2C_CONTROLLERS; i++) {
3667 dev_info(smu->adev->dev, "I2cControllers[%d]:\n", i);
3668 dev_info(smu->adev->dev, " .Enabled = 0x%x\n",
3669 pptable->I2cControllers[i].Enabled);
3670 dev_info(smu->adev->dev, " .Speed = 0x%x\n",
3671 pptable->I2cControllers[i].Speed);
3672 dev_info(smu->adev->dev, " .SlaveAddress = 0x%x\n",
3673 pptable->I2cControllers[i].SlaveAddress);
3674 dev_info(smu->adev->dev, " .ControllerPort = 0x%x\n",
3675 pptable->I2cControllers[i].ControllerPort);
3676 dev_info(smu->adev->dev, " .ControllerName = 0x%x\n",
3677 pptable->I2cControllers[i].ControllerName);
3678 dev_info(smu->adev->dev, " .ThermalThrottler = 0x%x\n",
3679 pptable->I2cControllers[i].ThermalThrotter);
3680 dev_info(smu->adev->dev, " .I2cProtocol = 0x%x\n",
3681 pptable->I2cControllers[i].I2cProtocol);
3682 dev_info(smu->adev->dev, " .PaddingConfig = 0x%x\n",
3683 pptable->I2cControllers[i].PaddingConfig);
3684 }
3685
3686 dev_info(smu->adev->dev, "GpioScl = 0x%x\n", pptable->GpioScl);
3687 dev_info(smu->adev->dev, "GpioSda = 0x%x\n", pptable->GpioSda);
3688 dev_info(smu->adev->dev, "FchUsbPdSlaveAddr = 0x%x\n", pptable->FchUsbPdSlaveAddr);
3689 dev_info(smu->adev->dev, "I2cSpare[0] = 0x%x\n", pptable->I2cSpare[0]);
3690
3691 dev_info(smu->adev->dev, "Board Parameters:\n");
3692 dev_info(smu->adev->dev, "VddGfxVrMapping = 0x%x\n", pptable->VddGfxVrMapping);
3693 dev_info(smu->adev->dev, "VddSocVrMapping = 0x%x\n", pptable->VddSocVrMapping);
3694 dev_info(smu->adev->dev, "VddMem0VrMapping = 0x%x\n", pptable->VddMem0VrMapping);
3695 dev_info(smu->adev->dev, "VddMem1VrMapping = 0x%x\n", pptable->VddMem1VrMapping);
3696 dev_info(smu->adev->dev, "GfxUlvPhaseSheddingMask = 0x%x\n", pptable->GfxUlvPhaseSheddingMask);
3697 dev_info(smu->adev->dev, "SocUlvPhaseSheddingMask = 0x%x\n", pptable->SocUlvPhaseSheddingMask);
3698 dev_info(smu->adev->dev, "VddciUlvPhaseSheddingMask = 0x%x\n", pptable->VddciUlvPhaseSheddingMask);
3699 dev_info(smu->adev->dev, "MvddUlvPhaseSheddingMask = 0x%x\n", pptable->MvddUlvPhaseSheddingMask);
3700
3701 dev_info(smu->adev->dev, "GfxMaxCurrent = 0x%x\n", pptable->GfxMaxCurrent);
3702 dev_info(smu->adev->dev, "GfxOffset = 0x%x\n", pptable->GfxOffset);
3703 dev_info(smu->adev->dev, "Padding_TelemetryGfx = 0x%x\n", pptable->Padding_TelemetryGfx);
3704
3705 dev_info(smu->adev->dev, "SocMaxCurrent = 0x%x\n", pptable->SocMaxCurrent);
3706 dev_info(smu->adev->dev, "SocOffset = 0x%x\n", pptable->SocOffset);
3707 dev_info(smu->adev->dev, "Padding_TelemetrySoc = 0x%x\n", pptable->Padding_TelemetrySoc);
3708
3709 dev_info(smu->adev->dev, "Mem0MaxCurrent = 0x%x\n", pptable->Mem0MaxCurrent);
3710 dev_info(smu->adev->dev, "Mem0Offset = 0x%x\n", pptable->Mem0Offset);
3711 dev_info(smu->adev->dev, "Padding_TelemetryMem0 = 0x%x\n", pptable->Padding_TelemetryMem0);
3712
3713 dev_info(smu->adev->dev, "Mem1MaxCurrent = 0x%x\n", pptable->Mem1MaxCurrent);
3714 dev_info(smu->adev->dev, "Mem1Offset = 0x%x\n", pptable->Mem1Offset);
3715 dev_info(smu->adev->dev, "Padding_TelemetryMem1 = 0x%x\n", pptable->Padding_TelemetryMem1);
3716
3717 dev_info(smu->adev->dev, "MvddRatio = 0x%x\n", pptable->MvddRatio);
3718
3719 dev_info(smu->adev->dev, "AcDcGpio = 0x%x\n", pptable->AcDcGpio);
3720 dev_info(smu->adev->dev, "AcDcPolarity = 0x%x\n", pptable->AcDcPolarity);
3721 dev_info(smu->adev->dev, "VR0HotGpio = 0x%x\n", pptable->VR0HotGpio);
3722 dev_info(smu->adev->dev, "VR0HotPolarity = 0x%x\n", pptable->VR0HotPolarity);
3723 dev_info(smu->adev->dev, "VR1HotGpio = 0x%x\n", pptable->VR1HotGpio);
3724 dev_info(smu->adev->dev, "VR1HotPolarity = 0x%x\n", pptable->VR1HotPolarity);
3725 dev_info(smu->adev->dev, "GthrGpio = 0x%x\n", pptable->GthrGpio);
3726 dev_info(smu->adev->dev, "GthrPolarity = 0x%x\n", pptable->GthrPolarity);
3727 dev_info(smu->adev->dev, "LedPin0 = 0x%x\n", pptable->LedPin0);
3728 dev_info(smu->adev->dev, "LedPin1 = 0x%x\n", pptable->LedPin1);
3729 dev_info(smu->adev->dev, "LedPin2 = 0x%x\n", pptable->LedPin2);
3730 dev_info(smu->adev->dev, "LedEnableMask = 0x%x\n", pptable->LedEnableMask);
3731 dev_info(smu->adev->dev, "LedPcie = 0x%x\n", pptable->LedPcie);
3732 dev_info(smu->adev->dev, "LedError = 0x%x\n", pptable->LedError);
3733 dev_info(smu->adev->dev, "LedSpare1[0] = 0x%x\n", pptable->LedSpare1[0]);
3734 dev_info(smu->adev->dev, "LedSpare1[1] = 0x%x\n", pptable->LedSpare1[1]);
3735
3736 dev_info(smu->adev->dev, "PllGfxclkSpreadEnabled = 0x%x\n", pptable->PllGfxclkSpreadEnabled);
3737 dev_info(smu->adev->dev, "PllGfxclkSpreadPercent = 0x%x\n", pptable->PllGfxclkSpreadPercent);
3738 dev_info(smu->adev->dev, "PllGfxclkSpreadFreq = 0x%x\n", pptable->PllGfxclkSpreadFreq);
3739
3740 dev_info(smu->adev->dev, "DfllGfxclkSpreadEnabled = 0x%x\n", pptable->DfllGfxclkSpreadEnabled);
3741 dev_info(smu->adev->dev, "DfllGfxclkSpreadPercent = 0x%x\n", pptable->DfllGfxclkSpreadPercent);
3742 dev_info(smu->adev->dev, "DfllGfxclkSpreadFreq = 0x%x\n", pptable->DfllGfxclkSpreadFreq);
3743
3744 dev_info(smu->adev->dev, "UclkSpreadPadding = 0x%x\n", pptable->UclkSpreadPadding);
3745 dev_info(smu->adev->dev, "UclkSpreadFreq = 0x%x\n", pptable->UclkSpreadFreq);
3746
3747 dev_info(smu->adev->dev, "FclkSpreadEnabled = 0x%x\n", pptable->FclkSpreadEnabled);
3748 dev_info(smu->adev->dev, "FclkSpreadPercent = 0x%x\n", pptable->FclkSpreadPercent);
3749 dev_info(smu->adev->dev, "FclkSpreadFreq = 0x%x\n", pptable->FclkSpreadFreq);
3750
3751 dev_info(smu->adev->dev, "MemoryChannelEnabled = 0x%x\n", pptable->MemoryChannelEnabled);
3752 dev_info(smu->adev->dev, "DramBitWidth = 0x%x\n", pptable->DramBitWidth);
3753 dev_info(smu->adev->dev, "PaddingMem1[0] = 0x%x\n", pptable->PaddingMem1[0]);
3754 dev_info(smu->adev->dev, "PaddingMem1[1] = 0x%x\n", pptable->PaddingMem1[1]);
3755 dev_info(smu->adev->dev, "PaddingMem1[2] = 0x%x\n", pptable->PaddingMem1[2]);
3756
3757 dev_info(smu->adev->dev, "TotalBoardPower = 0x%x\n", pptable->TotalBoardPower);
3758 dev_info(smu->adev->dev, "BoardPowerPadding = 0x%x\n", pptable->BoardPowerPadding);
3759
3760 dev_info(smu->adev->dev, "XgmiLinkSpeed\n");
3761 for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
3762 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->XgmiLinkSpeed[i]);
3763 dev_info(smu->adev->dev, "XgmiLinkWidth\n");
3764 for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
3765 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->XgmiLinkWidth[i]);
3766 dev_info(smu->adev->dev, "XgmiFclkFreq\n");
3767 for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
3768 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->XgmiFclkFreq[i]);
3769 dev_info(smu->adev->dev, "XgmiSocVoltage\n");
3770 for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
3771 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->XgmiSocVoltage[i]);
3772
3773 dev_info(smu->adev->dev, "HsrEnabled = 0x%x\n", pptable->HsrEnabled);
3774 dev_info(smu->adev->dev, "VddqOffEnabled = 0x%x\n", pptable->VddqOffEnabled);
3775 dev_info(smu->adev->dev, "PaddingUmcFlags[0] = 0x%x\n", pptable->PaddingUmcFlags[0]);
3776 dev_info(smu->adev->dev, "PaddingUmcFlags[1] = 0x%x\n", pptable->PaddingUmcFlags[1]);
3777
3778 dev_info(smu->adev->dev, "BoardReserved[0] = 0x%x\n", pptable->BoardReserved[0]);
3779 dev_info(smu->adev->dev, "BoardReserved[1] = 0x%x\n", pptable->BoardReserved[1]);
3780 dev_info(smu->adev->dev, "BoardReserved[2] = 0x%x\n", pptable->BoardReserved[2]);
3781 dev_info(smu->adev->dev, "BoardReserved[3] = 0x%x\n", pptable->BoardReserved[3]);
3782 dev_info(smu->adev->dev, "BoardReserved[4] = 0x%x\n", pptable->BoardReserved[4]);
3783 dev_info(smu->adev->dev, "BoardReserved[5] = 0x%x\n", pptable->BoardReserved[5]);
3784 dev_info(smu->adev->dev, "BoardReserved[6] = 0x%x\n", pptable->BoardReserved[6]);
3785 dev_info(smu->adev->dev, "BoardReserved[7] = 0x%x\n", pptable->BoardReserved[7]);
3786 dev_info(smu->adev->dev, "BoardReserved[8] = 0x%x\n", pptable->BoardReserved[8]);
3787 dev_info(smu->adev->dev, "BoardReserved[9] = 0x%x\n", pptable->BoardReserved[9]);
3788 dev_info(smu->adev->dev, "BoardReserved[10] = 0x%x\n", pptable->BoardReserved[10]);
3789
3790 dev_info(smu->adev->dev, "MmHubPadding[0] = 0x%x\n", pptable->MmHubPadding[0]);
3791 dev_info(smu->adev->dev, "MmHubPadding[1] = 0x%x\n", pptable->MmHubPadding[1]);
3792 dev_info(smu->adev->dev, "MmHubPadding[2] = 0x%x\n", pptable->MmHubPadding[2]);
3793 dev_info(smu->adev->dev, "MmHubPadding[3] = 0x%x\n", pptable->MmHubPadding[3]);
3794 dev_info(smu->adev->dev, "MmHubPadding[4] = 0x%x\n", pptable->MmHubPadding[4]);
3795 dev_info(smu->adev->dev, "MmHubPadding[5] = 0x%x\n", pptable->MmHubPadding[5]);
3796 dev_info(smu->adev->dev, "MmHubPadding[6] = 0x%x\n", pptable->MmHubPadding[6]);
3797 dev_info(smu->adev->dev, "MmHubPadding[7] = 0x%x\n", pptable->MmHubPadding[7]);
3798 }
3799
sienna_cichlid_i2c_xfer(struct i2c_adapter * i2c_adap,struct i2c_msg * msg,int num_msgs)3800 static int sienna_cichlid_i2c_xfer(struct i2c_adapter *i2c_adap,
3801 struct i2c_msg *msg, int num_msgs)
3802 {
3803 struct amdgpu_smu_i2c_bus *smu_i2c = i2c_get_adapdata(i2c_adap);
3804 struct amdgpu_device *adev = smu_i2c->adev;
3805 struct smu_context *smu = adev->powerplay.pp_handle;
3806 struct smu_table_context *smu_table = &smu->smu_table;
3807 struct smu_table *table = &smu_table->driver_table;
3808 SwI2cRequest_t *req, *res = (SwI2cRequest_t *)table->cpu_addr;
3809 int i, j, r, c;
3810 u16 dir;
3811
3812 if (!adev->pm.dpm_enabled)
3813 return -EBUSY;
3814
3815 req = kzalloc(sizeof(*req), GFP_KERNEL);
3816 if (!req)
3817 return -ENOMEM;
3818
3819 req->I2CcontrollerPort = smu_i2c->port;
3820 req->I2CSpeed = I2C_SPEED_FAST_400K;
3821 req->SlaveAddress = msg[0].addr << 1; /* wants an 8-bit address */
3822 dir = msg[0].flags & I2C_M_RD;
3823
3824 for (c = i = 0; i < num_msgs; i++) {
3825 for (j = 0; j < msg[i].len; j++, c++) {
3826 SwI2cCmd_t *cmd = &req->SwI2cCmds[c];
3827
3828 if (!(msg[i].flags & I2C_M_RD)) {
3829 /* write */
3830 cmd->CmdConfig |= CMDCONFIG_READWRITE_MASK;
3831 cmd->ReadWriteData = msg[i].buf[j];
3832 }
3833
3834 if ((dir ^ msg[i].flags) & I2C_M_RD) {
3835 /* The direction changes.
3836 */
3837 dir = msg[i].flags & I2C_M_RD;
3838 cmd->CmdConfig |= CMDCONFIG_RESTART_MASK;
3839 }
3840
3841 req->NumCmds++;
3842
3843 /*
3844 * Insert STOP if we are at the last byte of either last
3845 * message for the transaction or the client explicitly
3846 * requires a STOP at this particular message.
3847 */
3848 if ((j == msg[i].len - 1) &&
3849 ((i == num_msgs - 1) || (msg[i].flags & I2C_M_STOP))) {
3850 cmd->CmdConfig &= ~CMDCONFIG_RESTART_MASK;
3851 cmd->CmdConfig |= CMDCONFIG_STOP_MASK;
3852 }
3853 }
3854 }
3855 mutex_lock(&adev->pm.mutex);
3856 r = smu_cmn_update_table(smu, SMU_TABLE_I2C_COMMANDS, 0, req, true);
3857 if (r)
3858 goto fail;
3859
3860 for (c = i = 0; i < num_msgs; i++) {
3861 if (!(msg[i].flags & I2C_M_RD)) {
3862 c += msg[i].len;
3863 continue;
3864 }
3865 for (j = 0; j < msg[i].len; j++, c++) {
3866 SwI2cCmd_t *cmd = &res->SwI2cCmds[c];
3867
3868 msg[i].buf[j] = cmd->ReadWriteData;
3869 }
3870 }
3871 r = num_msgs;
3872 fail:
3873 mutex_unlock(&adev->pm.mutex);
3874 kfree(req);
3875 return r;
3876 }
3877
sienna_cichlid_i2c_func(struct i2c_adapter * adap)3878 static u32 sienna_cichlid_i2c_func(struct i2c_adapter *adap)
3879 {
3880 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
3881 }
3882
3883
3884 static const struct i2c_algorithm sienna_cichlid_i2c_algo = {
3885 .master_xfer = sienna_cichlid_i2c_xfer,
3886 .functionality = sienna_cichlid_i2c_func,
3887 };
3888
3889 static const struct i2c_adapter_quirks sienna_cichlid_i2c_control_quirks = {
3890 .flags = I2C_AQ_COMB | I2C_AQ_COMB_SAME_ADDR | I2C_AQ_NO_ZERO_LEN,
3891 .max_read_len = MAX_SW_I2C_COMMANDS,
3892 .max_write_len = MAX_SW_I2C_COMMANDS,
3893 .max_comb_1st_msg_len = 2,
3894 .max_comb_2nd_msg_len = MAX_SW_I2C_COMMANDS - 2,
3895 };
3896
sienna_cichlid_i2c_control_init(struct smu_context * smu)3897 static int sienna_cichlid_i2c_control_init(struct smu_context *smu)
3898 {
3899 struct amdgpu_device *adev = smu->adev;
3900 int res, i;
3901
3902 for (i = 0; i < MAX_SMU_I2C_BUSES; i++) {
3903 struct amdgpu_smu_i2c_bus *smu_i2c = &adev->pm.smu_i2c[i];
3904 struct i2c_adapter *control = &smu_i2c->adapter;
3905
3906 smu_i2c->adev = adev;
3907 smu_i2c->port = i;
3908 mutex_init(&smu_i2c->mutex);
3909 control->owner = THIS_MODULE;
3910 control->class = I2C_CLASS_HWMON;
3911 control->dev.parent = &adev->pdev->dev;
3912 control->algo = &sienna_cichlid_i2c_algo;
3913 snprintf(control->name, sizeof(control->name), "AMDGPU SMU %d", i);
3914 control->quirks = &sienna_cichlid_i2c_control_quirks;
3915 i2c_set_adapdata(control, smu_i2c);
3916
3917 res = i2c_add_adapter(control);
3918 if (res) {
3919 DRM_ERROR("Failed to register hw i2c, err: %d\n", res);
3920 goto Out_err;
3921 }
3922 }
3923 /* assign the buses used for the FRU EEPROM and RAS EEPROM */
3924 /* XXX ideally this would be something in a vbios data table */
3925 adev->pm.ras_eeprom_i2c_bus = &adev->pm.smu_i2c[1].adapter;
3926 adev->pm.fru_eeprom_i2c_bus = &adev->pm.smu_i2c[0].adapter;
3927
3928 return 0;
3929 Out_err:
3930 for ( ; i >= 0; i--) {
3931 struct amdgpu_smu_i2c_bus *smu_i2c = &adev->pm.smu_i2c[i];
3932 struct i2c_adapter *control = &smu_i2c->adapter;
3933
3934 i2c_del_adapter(control);
3935 }
3936 return res;
3937 }
3938
sienna_cichlid_i2c_control_fini(struct smu_context * smu)3939 static void sienna_cichlid_i2c_control_fini(struct smu_context *smu)
3940 {
3941 struct amdgpu_device *adev = smu->adev;
3942 int i;
3943
3944 for (i = 0; i < MAX_SMU_I2C_BUSES; i++) {
3945 struct amdgpu_smu_i2c_bus *smu_i2c = &adev->pm.smu_i2c[i];
3946 struct i2c_adapter *control = &smu_i2c->adapter;
3947
3948 i2c_del_adapter(control);
3949 }
3950 adev->pm.ras_eeprom_i2c_bus = NULL;
3951 adev->pm.fru_eeprom_i2c_bus = NULL;
3952 }
3953
sienna_cichlid_get_gpu_metrics(struct smu_context * smu,void ** table)3954 static ssize_t sienna_cichlid_get_gpu_metrics(struct smu_context *smu,
3955 void **table)
3956 {
3957 struct smu_table_context *smu_table = &smu->smu_table;
3958 struct gpu_metrics_v1_3 *gpu_metrics =
3959 (struct gpu_metrics_v1_3 *)smu_table->gpu_metrics_table;
3960 SmuMetricsExternal_t metrics_external;
3961 SmuMetrics_t *metrics =
3962 &(metrics_external.SmuMetrics);
3963 SmuMetrics_V2_t *metrics_v2 =
3964 &(metrics_external.SmuMetrics_V2);
3965 SmuMetrics_V3_t *metrics_v3 =
3966 &(metrics_external.SmuMetrics_V3);
3967 struct amdgpu_device *adev = smu->adev;
3968 bool use_metrics_v2 = false;
3969 bool use_metrics_v3 = false;
3970 uint16_t average_gfx_activity;
3971 int ret = 0;
3972
3973 switch (amdgpu_ip_version(smu->adev, MP1_HWIP, 0)) {
3974 case IP_VERSION(11, 0, 7):
3975 if (smu->smc_fw_version >= 0x3A4900)
3976 use_metrics_v3 = true;
3977 else if (smu->smc_fw_version >= 0x3A4300)
3978 use_metrics_v2 = true;
3979 break;
3980 case IP_VERSION(11, 0, 11):
3981 if (smu->smc_fw_version >= 0x412D00)
3982 use_metrics_v2 = true;
3983 break;
3984 case IP_VERSION(11, 0, 12):
3985 if (smu->smc_fw_version >= 0x3B2300)
3986 use_metrics_v2 = true;
3987 break;
3988 case IP_VERSION(11, 0, 13):
3989 if (smu->smc_fw_version >= 0x491100)
3990 use_metrics_v2 = true;
3991 break;
3992 default:
3993 break;
3994 }
3995
3996 ret = smu_cmn_get_metrics_table(smu,
3997 &metrics_external,
3998 true);
3999 if (ret)
4000 return ret;
4001
4002 smu_cmn_init_soft_gpu_metrics(gpu_metrics, 1, 3);
4003
4004 gpu_metrics->temperature_edge = use_metrics_v3 ? metrics_v3->TemperatureEdge :
4005 use_metrics_v2 ? metrics_v2->TemperatureEdge : metrics->TemperatureEdge;
4006 gpu_metrics->temperature_hotspot = use_metrics_v3 ? metrics_v3->TemperatureHotspot :
4007 use_metrics_v2 ? metrics_v2->TemperatureHotspot : metrics->TemperatureHotspot;
4008 gpu_metrics->temperature_mem = use_metrics_v3 ? metrics_v3->TemperatureMem :
4009 use_metrics_v2 ? metrics_v2->TemperatureMem : metrics->TemperatureMem;
4010 gpu_metrics->temperature_vrgfx = use_metrics_v3 ? metrics_v3->TemperatureVrGfx :
4011 use_metrics_v2 ? metrics_v2->TemperatureVrGfx : metrics->TemperatureVrGfx;
4012 gpu_metrics->temperature_vrsoc = use_metrics_v3 ? metrics_v3->TemperatureVrSoc :
4013 use_metrics_v2 ? metrics_v2->TemperatureVrSoc : metrics->TemperatureVrSoc;
4014 gpu_metrics->temperature_vrmem = use_metrics_v3 ? metrics_v3->TemperatureVrMem0 :
4015 use_metrics_v2 ? metrics_v2->TemperatureVrMem0 : metrics->TemperatureVrMem0;
4016
4017 gpu_metrics->average_gfx_activity = use_metrics_v3 ? metrics_v3->AverageGfxActivity :
4018 use_metrics_v2 ? metrics_v2->AverageGfxActivity : metrics->AverageGfxActivity;
4019 gpu_metrics->average_umc_activity = use_metrics_v3 ? metrics_v3->AverageUclkActivity :
4020 use_metrics_v2 ? metrics_v2->AverageUclkActivity : metrics->AverageUclkActivity;
4021 gpu_metrics->average_mm_activity = use_metrics_v3 ?
4022 (metrics_v3->VcnUsagePercentage0 + metrics_v3->VcnUsagePercentage1) / 2 :
4023 use_metrics_v2 ? metrics_v2->VcnActivityPercentage : metrics->VcnActivityPercentage;
4024
4025 gpu_metrics->average_socket_power = use_metrics_v3 ? metrics_v3->AverageSocketPower :
4026 use_metrics_v2 ? metrics_v2->AverageSocketPower : metrics->AverageSocketPower;
4027 gpu_metrics->energy_accumulator = use_metrics_v3 ? metrics_v3->EnergyAccumulator :
4028 use_metrics_v2 ? metrics_v2->EnergyAccumulator : metrics->EnergyAccumulator;
4029
4030 if (metrics->CurrGfxVoltageOffset)
4031 gpu_metrics->voltage_gfx =
4032 (155000 - 625 * metrics->CurrGfxVoltageOffset) / 100;
4033 if (metrics->CurrMemVidOffset)
4034 gpu_metrics->voltage_mem =
4035 (155000 - 625 * metrics->CurrMemVidOffset) / 100;
4036 if (metrics->CurrSocVoltageOffset)
4037 gpu_metrics->voltage_soc =
4038 (155000 - 625 * metrics->CurrSocVoltageOffset) / 100;
4039
4040 average_gfx_activity = use_metrics_v3 ? metrics_v3->AverageGfxActivity :
4041 use_metrics_v2 ? metrics_v2->AverageGfxActivity : metrics->AverageGfxActivity;
4042 if (average_gfx_activity <= SMU_11_0_7_GFX_BUSY_THRESHOLD)
4043 gpu_metrics->average_gfxclk_frequency =
4044 use_metrics_v3 ? metrics_v3->AverageGfxclkFrequencyPostDs :
4045 use_metrics_v2 ? metrics_v2->AverageGfxclkFrequencyPostDs :
4046 metrics->AverageGfxclkFrequencyPostDs;
4047 else
4048 gpu_metrics->average_gfxclk_frequency =
4049 use_metrics_v3 ? metrics_v3->AverageGfxclkFrequencyPreDs :
4050 use_metrics_v2 ? metrics_v2->AverageGfxclkFrequencyPreDs :
4051 metrics->AverageGfxclkFrequencyPreDs;
4052
4053 gpu_metrics->average_uclk_frequency =
4054 use_metrics_v3 ? metrics_v3->AverageUclkFrequencyPostDs :
4055 use_metrics_v2 ? metrics_v2->AverageUclkFrequencyPostDs :
4056 metrics->AverageUclkFrequencyPostDs;
4057 gpu_metrics->average_vclk0_frequency = use_metrics_v3 ? metrics_v3->AverageVclk0Frequency :
4058 use_metrics_v2 ? metrics_v2->AverageVclk0Frequency : metrics->AverageVclk0Frequency;
4059 gpu_metrics->average_dclk0_frequency = use_metrics_v3 ? metrics_v3->AverageDclk0Frequency :
4060 use_metrics_v2 ? metrics_v2->AverageDclk0Frequency : metrics->AverageDclk0Frequency;
4061 gpu_metrics->average_vclk1_frequency = use_metrics_v3 ? metrics_v3->AverageVclk1Frequency :
4062 use_metrics_v2 ? metrics_v2->AverageVclk1Frequency : metrics->AverageVclk1Frequency;
4063 gpu_metrics->average_dclk1_frequency = use_metrics_v3 ? metrics_v3->AverageDclk1Frequency :
4064 use_metrics_v2 ? metrics_v2->AverageDclk1Frequency : metrics->AverageDclk1Frequency;
4065
4066 gpu_metrics->current_gfxclk = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_GFXCLK] :
4067 use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_GFXCLK] : metrics->CurrClock[PPCLK_GFXCLK];
4068 gpu_metrics->current_socclk = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_SOCCLK] :
4069 use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_SOCCLK] : metrics->CurrClock[PPCLK_SOCCLK];
4070 gpu_metrics->current_uclk = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_UCLK] :
4071 use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_UCLK] : metrics->CurrClock[PPCLK_UCLK];
4072 gpu_metrics->current_vclk0 = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_VCLK_0] :
4073 use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_VCLK_0] : metrics->CurrClock[PPCLK_VCLK_0];
4074 gpu_metrics->current_dclk0 = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_DCLK_0] :
4075 use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_DCLK_0] : metrics->CurrClock[PPCLK_DCLK_0];
4076 gpu_metrics->current_vclk1 = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_VCLK_1] :
4077 use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_VCLK_1] : metrics->CurrClock[PPCLK_VCLK_1];
4078 gpu_metrics->current_dclk1 = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_DCLK_1] :
4079 use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_DCLK_1] : metrics->CurrClock[PPCLK_DCLK_1];
4080
4081 gpu_metrics->throttle_status = sienna_cichlid_get_throttler_status_locked(smu, use_metrics_v3, use_metrics_v2);
4082 gpu_metrics->indep_throttle_status =
4083 smu_cmn_get_indep_throttler_status(gpu_metrics->throttle_status,
4084 sienna_cichlid_throttler_map);
4085
4086 gpu_metrics->current_fan_speed = use_metrics_v3 ? metrics_v3->CurrFanSpeed :
4087 use_metrics_v2 ? metrics_v2->CurrFanSpeed : metrics->CurrFanSpeed;
4088
4089 if (((amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(11, 0, 7)) &&
4090 smu->smc_fw_version > 0x003A1E00) ||
4091 ((amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(11, 0, 11)) &&
4092 smu->smc_fw_version > 0x00410400)) {
4093 gpu_metrics->pcie_link_width = use_metrics_v3 ? metrics_v3->PcieWidth :
4094 use_metrics_v2 ? metrics_v2->PcieWidth : metrics->PcieWidth;
4095 gpu_metrics->pcie_link_speed = link_speed[use_metrics_v3 ? metrics_v3->PcieRate :
4096 use_metrics_v2 ? metrics_v2->PcieRate : metrics->PcieRate];
4097 } else {
4098 gpu_metrics->pcie_link_width =
4099 smu_v11_0_get_current_pcie_link_width(smu);
4100 gpu_metrics->pcie_link_speed =
4101 smu_v11_0_get_current_pcie_link_speed(smu);
4102 }
4103
4104 gpu_metrics->system_clock_counter = ktime_get_boottime_ns();
4105
4106 *table = (void *)gpu_metrics;
4107
4108 return sizeof(struct gpu_metrics_v1_3);
4109 }
4110
sienna_cichlid_check_ecc_table_support(struct smu_context * smu)4111 static int sienna_cichlid_check_ecc_table_support(struct smu_context *smu)
4112 {
4113 int ret = 0;
4114
4115 if (smu->smc_fw_version < SUPPORT_ECCTABLE_SMU_VERSION)
4116 ret = -EOPNOTSUPP;
4117
4118 return ret;
4119 }
4120
sienna_cichlid_get_ecc_info(struct smu_context * smu,void * table)4121 static ssize_t sienna_cichlid_get_ecc_info(struct smu_context *smu,
4122 void *table)
4123 {
4124 struct smu_table_context *smu_table = &smu->smu_table;
4125 EccInfoTable_t *ecc_table = NULL;
4126 struct ecc_info_per_ch *ecc_info_per_channel = NULL;
4127 int i, ret = 0;
4128 struct umc_ecc_info *eccinfo = (struct umc_ecc_info *)table;
4129
4130 ret = sienna_cichlid_check_ecc_table_support(smu);
4131 if (ret)
4132 return ret;
4133
4134 ret = smu_cmn_update_table(smu,
4135 SMU_TABLE_ECCINFO,
4136 0,
4137 smu_table->ecc_table,
4138 false);
4139 if (ret) {
4140 dev_info(smu->adev->dev, "Failed to export SMU ecc table!\n");
4141 return ret;
4142 }
4143
4144 ecc_table = (EccInfoTable_t *)smu_table->ecc_table;
4145
4146 for (i = 0; i < SIENNA_CICHLID_UMC_CHANNEL_NUM; i++) {
4147 ecc_info_per_channel = &(eccinfo->ecc[i]);
4148 ecc_info_per_channel->ce_count_lo_chip =
4149 ecc_table->EccInfo[i].ce_count_lo_chip;
4150 ecc_info_per_channel->ce_count_hi_chip =
4151 ecc_table->EccInfo[i].ce_count_hi_chip;
4152 ecc_info_per_channel->mca_umc_status =
4153 ecc_table->EccInfo[i].mca_umc_status;
4154 ecc_info_per_channel->mca_umc_addr =
4155 ecc_table->EccInfo[i].mca_umc_addr;
4156 }
4157
4158 return ret;
4159 }
sienna_cichlid_enable_mgpu_fan_boost(struct smu_context * smu)4160 static int sienna_cichlid_enable_mgpu_fan_boost(struct smu_context *smu)
4161 {
4162 uint16_t *mgpu_fan_boost_limit_rpm;
4163
4164 GET_PPTABLE_MEMBER(MGpuFanBoostLimitRpm, &mgpu_fan_boost_limit_rpm);
4165 /*
4166 * Skip the MGpuFanBoost setting for those ASICs
4167 * which do not support it
4168 */
4169 if (*mgpu_fan_boost_limit_rpm == 0)
4170 return 0;
4171
4172 return smu_cmn_send_smc_msg_with_param(smu,
4173 SMU_MSG_SetMGpuFanBoostLimitRpm,
4174 0,
4175 NULL);
4176 }
4177
sienna_cichlid_gpo_control(struct smu_context * smu,bool enablement)4178 static int sienna_cichlid_gpo_control(struct smu_context *smu,
4179 bool enablement)
4180 {
4181 int ret = 0;
4182
4183
4184 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFX_GPO_BIT)) {
4185
4186 if (enablement) {
4187 if (smu->smc_fw_version < 0x003a2500) {
4188 ret = smu_cmn_send_smc_msg_with_param(smu,
4189 SMU_MSG_SetGpoFeaturePMask,
4190 GFX_GPO_PACE_MASK | GFX_GPO_DEM_MASK,
4191 NULL);
4192 } else {
4193 ret = smu_cmn_send_smc_msg_with_param(smu,
4194 SMU_MSG_DisallowGpo,
4195 0,
4196 NULL);
4197 }
4198 } else {
4199 if (smu->smc_fw_version < 0x003a2500) {
4200 ret = smu_cmn_send_smc_msg_with_param(smu,
4201 SMU_MSG_SetGpoFeaturePMask,
4202 0,
4203 NULL);
4204 } else {
4205 ret = smu_cmn_send_smc_msg_with_param(smu,
4206 SMU_MSG_DisallowGpo,
4207 1,
4208 NULL);
4209 }
4210 }
4211 }
4212
4213 return ret;
4214 }
4215
sienna_cichlid_notify_2nd_usb20_port(struct smu_context * smu)4216 static int sienna_cichlid_notify_2nd_usb20_port(struct smu_context *smu)
4217 {
4218 /*
4219 * Message SMU_MSG_Enable2ndUSB20Port is supported by 58.45
4220 * onwards PMFWs.
4221 */
4222 if (smu->smc_fw_version < 0x003A2D00)
4223 return 0;
4224
4225 return smu_cmn_send_smc_msg_with_param(smu,
4226 SMU_MSG_Enable2ndUSB20Port,
4227 smu->smu_table.boot_values.firmware_caps & ATOM_FIRMWARE_CAP_ENABLE_2ND_USB20PORT ?
4228 1 : 0,
4229 NULL);
4230 }
4231
sienna_cichlid_system_features_control(struct smu_context * smu,bool en)4232 static int sienna_cichlid_system_features_control(struct smu_context *smu,
4233 bool en)
4234 {
4235 int ret = 0;
4236
4237 if (en) {
4238 ret = sienna_cichlid_notify_2nd_usb20_port(smu);
4239 if (ret)
4240 return ret;
4241 }
4242
4243 return smu_v11_0_system_features_control(smu, en);
4244 }
4245
sienna_cichlid_set_mp1_state(struct smu_context * smu,enum pp_mp1_state mp1_state)4246 static int sienna_cichlid_set_mp1_state(struct smu_context *smu,
4247 enum pp_mp1_state mp1_state)
4248 {
4249 int ret;
4250
4251 switch (mp1_state) {
4252 case PP_MP1_STATE_UNLOAD:
4253 ret = smu_cmn_set_mp1_state(smu, mp1_state);
4254 break;
4255 default:
4256 /* Ignore others */
4257 ret = 0;
4258 }
4259
4260 return ret;
4261 }
4262
sienna_cichlid_stb_init(struct smu_context * smu)4263 static void sienna_cichlid_stb_init(struct smu_context *smu)
4264 {
4265 struct amdgpu_device *adev = smu->adev;
4266 uint32_t reg;
4267
4268 reg = RREG32_PCIE(MP1_Public | smnMP1_PMI_3_START);
4269 smu->stb_context.enabled = REG_GET_FIELD(reg, MP1_PMI_3_START, ENABLE);
4270
4271 /* STB is disabled */
4272 if (!smu->stb_context.enabled)
4273 return;
4274
4275 spin_lock_init(&smu->stb_context.lock);
4276
4277 /* STB buffer size in bytes as function of FIFO depth */
4278 reg = RREG32_PCIE(MP1_Public | smnMP1_PMI_3_FIFO);
4279 smu->stb_context.stb_buf_size = 1 << REG_GET_FIELD(reg, MP1_PMI_3_FIFO, DEPTH);
4280 smu->stb_context.stb_buf_size *= SIENNA_CICHLID_STB_DEPTH_UNIT_BYTES;
4281
4282 dev_info(smu->adev->dev, "STB initialized to %d entries",
4283 smu->stb_context.stb_buf_size / SIENNA_CICHLID_STB_DEPTH_UNIT_BYTES);
4284
4285 }
4286
sienna_cichlid_get_default_config_table_settings(struct smu_context * smu,struct config_table_setting * table)4287 static int sienna_cichlid_get_default_config_table_settings(struct smu_context *smu,
4288 struct config_table_setting *table)
4289 {
4290 struct amdgpu_device *adev = smu->adev;
4291
4292 if (!table)
4293 return -EINVAL;
4294
4295 table->gfxclk_average_tau = 10;
4296 table->socclk_average_tau = 10;
4297 table->fclk_average_tau = 10;
4298 table->uclk_average_tau = 10;
4299 table->gfx_activity_average_tau = 10;
4300 table->mem_activity_average_tau = 10;
4301 table->socket_power_average_tau = 100;
4302 if (amdgpu_ip_version(adev, MP1_HWIP, 0) != IP_VERSION(11, 0, 7))
4303 table->apu_socket_power_average_tau = 100;
4304
4305 return 0;
4306 }
4307
sienna_cichlid_set_config_table(struct smu_context * smu,struct config_table_setting * table)4308 static int sienna_cichlid_set_config_table(struct smu_context *smu,
4309 struct config_table_setting *table)
4310 {
4311 DriverSmuConfigExternal_t driver_smu_config_table;
4312
4313 if (!table)
4314 return -EINVAL;
4315
4316 memset(&driver_smu_config_table,
4317 0,
4318 sizeof(driver_smu_config_table));
4319 driver_smu_config_table.DriverSmuConfig.GfxclkAverageLpfTau =
4320 table->gfxclk_average_tau;
4321 driver_smu_config_table.DriverSmuConfig.FclkAverageLpfTau =
4322 table->fclk_average_tau;
4323 driver_smu_config_table.DriverSmuConfig.UclkAverageLpfTau =
4324 table->uclk_average_tau;
4325 driver_smu_config_table.DriverSmuConfig.GfxActivityLpfTau =
4326 table->gfx_activity_average_tau;
4327 driver_smu_config_table.DriverSmuConfig.UclkActivityLpfTau =
4328 table->mem_activity_average_tau;
4329 driver_smu_config_table.DriverSmuConfig.SocketPowerLpfTau =
4330 table->socket_power_average_tau;
4331
4332 return smu_cmn_update_table(smu,
4333 SMU_TABLE_DRIVER_SMU_CONFIG,
4334 0,
4335 (void *)&driver_smu_config_table,
4336 true);
4337 }
4338
sienna_cichlid_stb_get_data_direct(struct smu_context * smu,void * buf,uint32_t size)4339 static int sienna_cichlid_stb_get_data_direct(struct smu_context *smu,
4340 void *buf,
4341 uint32_t size)
4342 {
4343 uint32_t *p = buf;
4344 struct amdgpu_device *adev = smu->adev;
4345
4346 /* No need to disable interrupts for now as we don't lock it yet from ISR */
4347 spin_lock(&smu->stb_context.lock);
4348
4349 /*
4350 * Read the STB FIFO in units of 32bit since this is the accessor window
4351 * (register width) we have.
4352 */
4353 buf = ((char *) buf) + size;
4354 while ((void *)p < buf)
4355 *p++ = cpu_to_le32(RREG32_PCIE(MP1_Public | smnMP1_PMI_3));
4356
4357 spin_unlock(&smu->stb_context.lock);
4358
4359 return 0;
4360 }
4361
sienna_cichlid_is_mode2_reset_supported(struct smu_context * smu)4362 static bool sienna_cichlid_is_mode2_reset_supported(struct smu_context *smu)
4363 {
4364 return true;
4365 }
4366
sienna_cichlid_mode2_reset(struct smu_context * smu)4367 static int sienna_cichlid_mode2_reset(struct smu_context *smu)
4368 {
4369 int ret = 0, index;
4370 struct amdgpu_device *adev = smu->adev;
4371 int timeout = 100;
4372
4373 index = smu_cmn_to_asic_specific_index(smu, CMN2ASIC_MAPPING_MSG,
4374 SMU_MSG_DriverMode2Reset);
4375
4376 mutex_lock(&smu->message_lock);
4377
4378 ret = smu_cmn_send_msg_without_waiting(smu, (uint16_t)index,
4379 SMU_RESET_MODE_2);
4380
4381 ret = smu_cmn_wait_for_response(smu);
4382 while (ret != 0 && timeout) {
4383 ret = smu_cmn_wait_for_response(smu);
4384 /* Wait a bit more time for getting ACK */
4385 if (ret != 0) {
4386 --timeout;
4387 usleep_range(500, 1000);
4388 continue;
4389 } else {
4390 break;
4391 }
4392 }
4393
4394 if (!timeout) {
4395 dev_err(adev->dev,
4396 "failed to send mode2 message \tparam: 0x%08x response %#x\n",
4397 SMU_RESET_MODE_2, ret);
4398 goto out;
4399 }
4400
4401 dev_info(smu->adev->dev, "restore config space...\n");
4402 /* Restore the config space saved during init */
4403 amdgpu_device_load_pci_state(adev->pdev);
4404 out:
4405 mutex_unlock(&smu->message_lock);
4406
4407 return ret;
4408 }
4409
4410 static const struct pptable_funcs sienna_cichlid_ppt_funcs = {
4411 .get_allowed_feature_mask = sienna_cichlid_get_allowed_feature_mask,
4412 .set_default_dpm_table = sienna_cichlid_set_default_dpm_table,
4413 .dpm_set_vcn_enable = sienna_cichlid_dpm_set_vcn_enable,
4414 .dpm_set_jpeg_enable = sienna_cichlid_dpm_set_jpeg_enable,
4415 .i2c_init = sienna_cichlid_i2c_control_init,
4416 .i2c_fini = sienna_cichlid_i2c_control_fini,
4417 .print_clk_levels = sienna_cichlid_print_clk_levels,
4418 .force_clk_levels = sienna_cichlid_force_clk_levels,
4419 .populate_umd_state_clk = sienna_cichlid_populate_umd_state_clk,
4420 .pre_display_config_changed = sienna_cichlid_pre_display_config_changed,
4421 .display_config_changed = sienna_cichlid_display_config_changed,
4422 .notify_smc_display_config = sienna_cichlid_notify_smc_display_config,
4423 .is_dpm_running = sienna_cichlid_is_dpm_running,
4424 .get_fan_speed_pwm = smu_v11_0_get_fan_speed_pwm,
4425 .get_fan_speed_rpm = sienna_cichlid_get_fan_speed_rpm,
4426 .get_power_profile_mode = sienna_cichlid_get_power_profile_mode,
4427 .set_power_profile_mode = sienna_cichlid_set_power_profile_mode,
4428 .set_watermarks_table = sienna_cichlid_set_watermarks_table,
4429 .read_sensor = sienna_cichlid_read_sensor,
4430 .get_uclk_dpm_states = sienna_cichlid_get_uclk_dpm_states,
4431 .set_performance_level = smu_v11_0_set_performance_level,
4432 .get_thermal_temperature_range = sienna_cichlid_get_thermal_temperature_range,
4433 .display_disable_memory_clock_switch = sienna_cichlid_display_disable_memory_clock_switch,
4434 .get_power_limit = sienna_cichlid_get_power_limit,
4435 .update_pcie_parameters = sienna_cichlid_update_pcie_parameters,
4436 .dump_pptable = sienna_cichlid_dump_pptable,
4437 .init_microcode = smu_v11_0_init_microcode,
4438 .load_microcode = smu_v11_0_load_microcode,
4439 .fini_microcode = smu_v11_0_fini_microcode,
4440 .init_smc_tables = sienna_cichlid_init_smc_tables,
4441 .fini_smc_tables = smu_v11_0_fini_smc_tables,
4442 .init_power = smu_v11_0_init_power,
4443 .fini_power = smu_v11_0_fini_power,
4444 .check_fw_status = smu_v11_0_check_fw_status,
4445 .setup_pptable = sienna_cichlid_setup_pptable,
4446 .get_vbios_bootup_values = smu_v11_0_get_vbios_bootup_values,
4447 .check_fw_version = smu_v11_0_check_fw_version,
4448 .write_pptable = smu_cmn_write_pptable,
4449 .set_driver_table_location = smu_v11_0_set_driver_table_location,
4450 .set_tool_table_location = smu_v11_0_set_tool_table_location,
4451 .notify_memory_pool_location = smu_v11_0_notify_memory_pool_location,
4452 .system_features_control = sienna_cichlid_system_features_control,
4453 .send_smc_msg_with_param = smu_cmn_send_smc_msg_with_param,
4454 .send_smc_msg = smu_cmn_send_smc_msg,
4455 .init_display_count = NULL,
4456 .set_allowed_mask = smu_v11_0_set_allowed_mask,
4457 .get_enabled_mask = smu_cmn_get_enabled_mask,
4458 .feature_is_enabled = smu_cmn_feature_is_enabled,
4459 .disable_all_features_with_exception = smu_cmn_disable_all_features_with_exception,
4460 .notify_display_change = NULL,
4461 .set_power_limit = smu_v11_0_set_power_limit,
4462 .init_max_sustainable_clocks = smu_v11_0_init_max_sustainable_clocks,
4463 .enable_thermal_alert = smu_v11_0_enable_thermal_alert,
4464 .disable_thermal_alert = smu_v11_0_disable_thermal_alert,
4465 .set_min_dcef_deep_sleep = NULL,
4466 .display_clock_voltage_request = smu_v11_0_display_clock_voltage_request,
4467 .get_fan_control_mode = smu_v11_0_get_fan_control_mode,
4468 .set_fan_control_mode = smu_v11_0_set_fan_control_mode,
4469 .set_fan_speed_pwm = smu_v11_0_set_fan_speed_pwm,
4470 .set_fan_speed_rpm = smu_v11_0_set_fan_speed_rpm,
4471 .set_xgmi_pstate = smu_v11_0_set_xgmi_pstate,
4472 .gfx_off_control = smu_v11_0_gfx_off_control,
4473 .register_irq_handler = smu_v11_0_register_irq_handler,
4474 .set_azalia_d3_pme = smu_v11_0_set_azalia_d3_pme,
4475 .get_max_sustainable_clocks_by_dc = smu_v11_0_get_max_sustainable_clocks_by_dc,
4476 .get_bamaco_support = smu_v11_0_get_bamaco_support,
4477 .baco_enter = sienna_cichlid_baco_enter,
4478 .baco_exit = sienna_cichlid_baco_exit,
4479 .mode1_reset_is_support = sienna_cichlid_is_mode1_reset_supported,
4480 .mode1_reset = smu_v11_0_mode1_reset,
4481 .get_dpm_ultimate_freq = sienna_cichlid_get_dpm_ultimate_freq,
4482 .set_soft_freq_limited_range = smu_v11_0_set_soft_freq_limited_range,
4483 .set_default_od_settings = sienna_cichlid_set_default_od_settings,
4484 .od_edit_dpm_table = sienna_cichlid_od_edit_dpm_table,
4485 .restore_user_od_settings = sienna_cichlid_restore_user_od_settings,
4486 .run_btc = sienna_cichlid_run_btc,
4487 .set_power_source = smu_v11_0_set_power_source,
4488 .get_pp_feature_mask = smu_cmn_get_pp_feature_mask,
4489 .set_pp_feature_mask = smu_cmn_set_pp_feature_mask,
4490 .get_gpu_metrics = sienna_cichlid_get_gpu_metrics,
4491 .enable_mgpu_fan_boost = sienna_cichlid_enable_mgpu_fan_boost,
4492 .gfx_ulv_control = smu_v11_0_gfx_ulv_control,
4493 .deep_sleep_control = smu_v11_0_deep_sleep_control,
4494 .get_fan_parameters = sienna_cichlid_get_fan_parameters,
4495 .interrupt_work = smu_v11_0_interrupt_work,
4496 .gpo_control = sienna_cichlid_gpo_control,
4497 .set_mp1_state = sienna_cichlid_set_mp1_state,
4498 .stb_collect_info = sienna_cichlid_stb_get_data_direct,
4499 .get_ecc_info = sienna_cichlid_get_ecc_info,
4500 .get_default_config_table_settings = sienna_cichlid_get_default_config_table_settings,
4501 .set_config_table = sienna_cichlid_set_config_table,
4502 .get_unique_id = sienna_cichlid_get_unique_id,
4503 .mode2_reset_is_support = sienna_cichlid_is_mode2_reset_supported,
4504 .mode2_reset = sienna_cichlid_mode2_reset,
4505 };
4506
sienna_cichlid_set_ppt_funcs(struct smu_context * smu)4507 void sienna_cichlid_set_ppt_funcs(struct smu_context *smu)
4508 {
4509 smu->ppt_funcs = &sienna_cichlid_ppt_funcs;
4510 smu->message_map = sienna_cichlid_message_map;
4511 smu->clock_map = sienna_cichlid_clk_map;
4512 smu->feature_map = sienna_cichlid_feature_mask_map;
4513 smu->table_map = sienna_cichlid_table_map;
4514 smu->pwr_src_map = sienna_cichlid_pwr_src_map;
4515 smu->workload_map = sienna_cichlid_workload_map;
4516 smu_v11_0_set_smu_mailbox_registers(smu);
4517 }
4518