1 /*
2 * Copyright 2020 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24 #define SWSMU_CODE_LAYER_L2
25
26 #include "amdgpu.h"
27 #include "amdgpu_smu.h"
28 #include "smu_v11_0.h"
29 #include "smu11_driver_if_vangogh.h"
30 #include "vangogh_ppt.h"
31 #include "smu_v11_5_ppsmc.h"
32 #include "smu_v11_5_pmfw.h"
33 #include "smu_cmn.h"
34 #include "soc15_common.h"
35 #include "asic_reg/gc/gc_10_3_0_offset.h"
36 #include "asic_reg/gc/gc_10_3_0_sh_mask.h"
37 #include <asm/processor.h>
38
39 /*
40 * DO NOT use these for err/warn/info/debug messages.
41 * Use dev_err, dev_warn, dev_info and dev_dbg instead.
42 * They are more MGPU friendly.
43 */
44 #undef pr_err
45 #undef pr_warn
46 #undef pr_info
47 #undef pr_debug
48
49 // Registers related to GFXOFF
50 // addressBlock: smuio_smuio_SmuSmuioDec
51 // base address: 0x5a000
52 #define mmSMUIO_GFX_MISC_CNTL 0x00c5
53 #define mmSMUIO_GFX_MISC_CNTL_BASE_IDX 0
54
55 //SMUIO_GFX_MISC_CNTL
56 #define SMUIO_GFX_MISC_CNTL__SMU_GFX_cold_vs_gfxoff__SHIFT 0x0
57 #define SMUIO_GFX_MISC_CNTL__PWR_GFXOFF_STATUS__SHIFT 0x1
58 #define SMUIO_GFX_MISC_CNTL__SMU_GFX_cold_vs_gfxoff_MASK 0x00000001L
59 #define SMUIO_GFX_MISC_CNTL__PWR_GFXOFF_STATUS_MASK 0x00000006L
60
61 #define FEATURE_MASK(feature) (1ULL << feature)
62 #define SMC_DPM_FEATURE ( \
63 FEATURE_MASK(FEATURE_CCLK_DPM_BIT) | \
64 FEATURE_MASK(FEATURE_VCN_DPM_BIT) | \
65 FEATURE_MASK(FEATURE_FCLK_DPM_BIT) | \
66 FEATURE_MASK(FEATURE_SOCCLK_DPM_BIT) | \
67 FEATURE_MASK(FEATURE_MP0CLK_DPM_BIT) | \
68 FEATURE_MASK(FEATURE_LCLK_DPM_BIT) | \
69 FEATURE_MASK(FEATURE_SHUBCLK_DPM_BIT) | \
70 FEATURE_MASK(FEATURE_DCFCLK_DPM_BIT)| \
71 FEATURE_MASK(FEATURE_GFX_DPM_BIT))
72
73 static struct cmn2asic_msg_mapping vangogh_message_map[SMU_MSG_MAX_COUNT] = {
74 MSG_MAP(TestMessage, PPSMC_MSG_TestMessage, 0),
75 MSG_MAP(GetSmuVersion, PPSMC_MSG_GetSmuVersion, 0),
76 MSG_MAP(GetDriverIfVersion, PPSMC_MSG_GetDriverIfVersion, 0),
77 MSG_MAP(EnableGfxOff, PPSMC_MSG_EnableGfxOff, 0),
78 MSG_MAP(AllowGfxOff, PPSMC_MSG_AllowGfxOff, 0),
79 MSG_MAP(DisallowGfxOff, PPSMC_MSG_DisallowGfxOff, 0),
80 MSG_MAP(PowerDownIspByTile, PPSMC_MSG_PowerDownIspByTile, 0),
81 MSG_MAP(PowerUpIspByTile, PPSMC_MSG_PowerUpIspByTile, 0),
82 MSG_MAP(PowerDownVcn, PPSMC_MSG_PowerDownVcn, 0),
83 MSG_MAP(PowerUpVcn, PPSMC_MSG_PowerUpVcn, 0),
84 MSG_MAP(RlcPowerNotify, PPSMC_MSG_RlcPowerNotify, 0),
85 MSG_MAP(SetHardMinVcn, PPSMC_MSG_SetHardMinVcn, 0),
86 MSG_MAP(SetSoftMinGfxclk, PPSMC_MSG_SetSoftMinGfxclk, 0),
87 MSG_MAP(ActiveProcessNotify, PPSMC_MSG_ActiveProcessNotify, 0),
88 MSG_MAP(SetHardMinIspiclkByFreq, PPSMC_MSG_SetHardMinIspiclkByFreq, 0),
89 MSG_MAP(SetHardMinIspxclkByFreq, PPSMC_MSG_SetHardMinIspxclkByFreq, 0),
90 MSG_MAP(SetDriverDramAddrHigh, PPSMC_MSG_SetDriverDramAddrHigh, 0),
91 MSG_MAP(SetDriverDramAddrLow, PPSMC_MSG_SetDriverDramAddrLow, 0),
92 MSG_MAP(TransferTableSmu2Dram, PPSMC_MSG_TransferTableSmu2Dram, 0),
93 MSG_MAP(TransferTableDram2Smu, PPSMC_MSG_TransferTableDram2Smu, 0),
94 MSG_MAP(GfxDeviceDriverReset, PPSMC_MSG_GfxDeviceDriverReset, 0),
95 MSG_MAP(GetEnabledSmuFeatures, PPSMC_MSG_GetEnabledSmuFeatures, 0),
96 MSG_MAP(SetHardMinSocclkByFreq, PPSMC_MSG_SetHardMinSocclkByFreq, 0),
97 MSG_MAP(SetSoftMinFclk, PPSMC_MSG_SetSoftMinFclk, 0),
98 MSG_MAP(SetSoftMinVcn, PPSMC_MSG_SetSoftMinVcn, 0),
99 MSG_MAP(EnablePostCode, PPSMC_MSG_EnablePostCode, 0),
100 MSG_MAP(GetGfxclkFrequency, PPSMC_MSG_GetGfxclkFrequency, 0),
101 MSG_MAP(GetFclkFrequency, PPSMC_MSG_GetFclkFrequency, 0),
102 MSG_MAP(SetSoftMaxGfxClk, PPSMC_MSG_SetSoftMaxGfxClk, 0),
103 MSG_MAP(SetHardMinGfxClk, PPSMC_MSG_SetHardMinGfxClk, 0),
104 MSG_MAP(SetSoftMaxSocclkByFreq, PPSMC_MSG_SetSoftMaxSocclkByFreq, 0),
105 MSG_MAP(SetSoftMaxFclkByFreq, PPSMC_MSG_SetSoftMaxFclkByFreq, 0),
106 MSG_MAP(SetSoftMaxVcn, PPSMC_MSG_SetSoftMaxVcn, 0),
107 MSG_MAP(SetPowerLimitPercentage, PPSMC_MSG_SetPowerLimitPercentage, 0),
108 MSG_MAP(PowerDownJpeg, PPSMC_MSG_PowerDownJpeg, 0),
109 MSG_MAP(PowerUpJpeg, PPSMC_MSG_PowerUpJpeg, 0),
110 MSG_MAP(SetHardMinFclkByFreq, PPSMC_MSG_SetHardMinFclkByFreq, 0),
111 MSG_MAP(SetSoftMinSocclkByFreq, PPSMC_MSG_SetSoftMinSocclkByFreq, 0),
112 MSG_MAP(PowerUpCvip, PPSMC_MSG_PowerUpCvip, 0),
113 MSG_MAP(PowerDownCvip, PPSMC_MSG_PowerDownCvip, 0),
114 MSG_MAP(GetPptLimit, PPSMC_MSG_GetPptLimit, 0),
115 MSG_MAP(GetThermalLimit, PPSMC_MSG_GetThermalLimit, 0),
116 MSG_MAP(GetCurrentTemperature, PPSMC_MSG_GetCurrentTemperature, 0),
117 MSG_MAP(GetCurrentPower, PPSMC_MSG_GetCurrentPower, 0),
118 MSG_MAP(GetCurrentVoltage, PPSMC_MSG_GetCurrentVoltage, 0),
119 MSG_MAP(GetCurrentCurrent, PPSMC_MSG_GetCurrentCurrent, 0),
120 MSG_MAP(GetAverageCpuActivity, PPSMC_MSG_GetAverageCpuActivity, 0),
121 MSG_MAP(GetAverageGfxActivity, PPSMC_MSG_GetAverageGfxActivity, 0),
122 MSG_MAP(GetAveragePower, PPSMC_MSG_GetAveragePower, 0),
123 MSG_MAP(GetAverageTemperature, PPSMC_MSG_GetAverageTemperature, 0),
124 MSG_MAP(SetAveragePowerTimeConstant, PPSMC_MSG_SetAveragePowerTimeConstant, 0),
125 MSG_MAP(SetAverageActivityTimeConstant, PPSMC_MSG_SetAverageActivityTimeConstant, 0),
126 MSG_MAP(SetAverageTemperatureTimeConstant, PPSMC_MSG_SetAverageTemperatureTimeConstant, 0),
127 MSG_MAP(SetMitigationEndHysteresis, PPSMC_MSG_SetMitigationEndHysteresis, 0),
128 MSG_MAP(GetCurrentFreq, PPSMC_MSG_GetCurrentFreq, 0),
129 MSG_MAP(SetReducedPptLimit, PPSMC_MSG_SetReducedPptLimit, 0),
130 MSG_MAP(SetReducedThermalLimit, PPSMC_MSG_SetReducedThermalLimit, 0),
131 MSG_MAP(DramLogSetDramAddr, PPSMC_MSG_DramLogSetDramAddr, 0),
132 MSG_MAP(StartDramLogging, PPSMC_MSG_StartDramLogging, 0),
133 MSG_MAP(StopDramLogging, PPSMC_MSG_StopDramLogging, 0),
134 MSG_MAP(SetSoftMinCclk, PPSMC_MSG_SetSoftMinCclk, 0),
135 MSG_MAP(SetSoftMaxCclk, PPSMC_MSG_SetSoftMaxCclk, 0),
136 MSG_MAP(RequestActiveWgp, PPSMC_MSG_RequestActiveWgp, 0),
137 MSG_MAP(SetFastPPTLimit, PPSMC_MSG_SetFastPPTLimit, 0),
138 MSG_MAP(SetSlowPPTLimit, PPSMC_MSG_SetSlowPPTLimit, 0),
139 MSG_MAP(GetFastPPTLimit, PPSMC_MSG_GetFastPPTLimit, 0),
140 MSG_MAP(GetSlowPPTLimit, PPSMC_MSG_GetSlowPPTLimit, 0),
141 MSG_MAP(GetGfxOffStatus, PPSMC_MSG_GetGfxOffStatus, 0),
142 MSG_MAP(GetGfxOffEntryCount, PPSMC_MSG_GetGfxOffEntryCount, 0),
143 MSG_MAP(LogGfxOffResidency, PPSMC_MSG_LogGfxOffResidency, 0),
144 };
145
146 static struct cmn2asic_mapping vangogh_feature_mask_map[SMU_FEATURE_COUNT] = {
147 FEA_MAP(PPT),
148 FEA_MAP(TDC),
149 FEA_MAP(THERMAL),
150 FEA_MAP(DS_GFXCLK),
151 FEA_MAP(DS_SOCCLK),
152 FEA_MAP(DS_LCLK),
153 FEA_MAP(DS_FCLK),
154 FEA_MAP(DS_MP1CLK),
155 FEA_MAP(DS_MP0CLK),
156 FEA_MAP(ATHUB_PG),
157 FEA_MAP(CCLK_DPM),
158 FEA_MAP(FAN_CONTROLLER),
159 FEA_MAP(ULV),
160 FEA_MAP(VCN_DPM),
161 FEA_MAP(LCLK_DPM),
162 FEA_MAP(SHUBCLK_DPM),
163 FEA_MAP(DCFCLK_DPM),
164 FEA_MAP(DS_DCFCLK),
165 FEA_MAP(S0I2),
166 FEA_MAP(SMU_LOW_POWER),
167 FEA_MAP(GFX_DEM),
168 FEA_MAP(PSI),
169 FEA_MAP(PROCHOT),
170 FEA_MAP(CPUOFF),
171 FEA_MAP(STAPM),
172 FEA_MAP(S0I3),
173 FEA_MAP(DF_CSTATES),
174 FEA_MAP(PERF_LIMIT),
175 FEA_MAP(CORE_DLDO),
176 FEA_MAP(RSMU_LOW_POWER),
177 FEA_MAP(SMN_LOW_POWER),
178 FEA_MAP(THM_LOW_POWER),
179 FEA_MAP(SMUIO_LOW_POWER),
180 FEA_MAP(MP1_LOW_POWER),
181 FEA_MAP(DS_VCN),
182 FEA_MAP(CPPC),
183 FEA_MAP(OS_CSTATES),
184 FEA_MAP(ISP_DPM),
185 FEA_MAP(A55_DPM),
186 FEA_MAP(CVIP_DSP_DPM),
187 FEA_MAP(MSMU_LOW_POWER),
188 FEA_MAP_REVERSE(SOCCLK),
189 FEA_MAP_REVERSE(FCLK),
190 FEA_MAP_HALF_REVERSE(GFX),
191 };
192
193 static struct cmn2asic_mapping vangogh_table_map[SMU_TABLE_COUNT] = {
194 TAB_MAP_VALID(WATERMARKS),
195 TAB_MAP_VALID(SMU_METRICS),
196 TAB_MAP_VALID(CUSTOM_DPM),
197 TAB_MAP_VALID(DPMCLOCKS),
198 };
199
200 static struct cmn2asic_mapping vangogh_workload_map[PP_SMC_POWER_PROFILE_COUNT] = {
201 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_FULLSCREEN3D, WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT),
202 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VIDEO, WORKLOAD_PPLIB_VIDEO_BIT),
203 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VR, WORKLOAD_PPLIB_VR_BIT),
204 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_COMPUTE, WORKLOAD_PPLIB_COMPUTE_BIT),
205 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_CUSTOM, WORKLOAD_PPLIB_CUSTOM_BIT),
206 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_CAPPED, WORKLOAD_PPLIB_CAPPED_BIT),
207 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_UNCAPPED, WORKLOAD_PPLIB_UNCAPPED_BIT),
208 };
209
210 static const uint8_t vangogh_throttler_map[] = {
211 [THROTTLER_STATUS_BIT_SPL] = (SMU_THROTTLER_SPL_BIT),
212 [THROTTLER_STATUS_BIT_FPPT] = (SMU_THROTTLER_FPPT_BIT),
213 [THROTTLER_STATUS_BIT_SPPT] = (SMU_THROTTLER_SPPT_BIT),
214 [THROTTLER_STATUS_BIT_SPPT_APU] = (SMU_THROTTLER_SPPT_APU_BIT),
215 [THROTTLER_STATUS_BIT_THM_CORE] = (SMU_THROTTLER_TEMP_CORE_BIT),
216 [THROTTLER_STATUS_BIT_THM_GFX] = (SMU_THROTTLER_TEMP_GPU_BIT),
217 [THROTTLER_STATUS_BIT_THM_SOC] = (SMU_THROTTLER_TEMP_SOC_BIT),
218 [THROTTLER_STATUS_BIT_TDC_VDD] = (SMU_THROTTLER_TDC_VDD_BIT),
219 [THROTTLER_STATUS_BIT_TDC_SOC] = (SMU_THROTTLER_TDC_SOC_BIT),
220 [THROTTLER_STATUS_BIT_TDC_GFX] = (SMU_THROTTLER_TDC_GFX_BIT),
221 [THROTTLER_STATUS_BIT_TDC_CVIP] = (SMU_THROTTLER_TDC_CVIP_BIT),
222 };
223
vangogh_tables_init(struct smu_context * smu)224 static int vangogh_tables_init(struct smu_context *smu)
225 {
226 struct smu_table_context *smu_table = &smu->smu_table;
227 struct smu_table *tables = smu_table->tables;
228
229 SMU_TABLE_INIT(tables, SMU_TABLE_WATERMARKS, sizeof(Watermarks_t),
230 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
231 SMU_TABLE_INIT(tables, SMU_TABLE_DPMCLOCKS, sizeof(DpmClocks_t),
232 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
233 SMU_TABLE_INIT(tables, SMU_TABLE_PMSTATUSLOG, SMU11_TOOL_SIZE,
234 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
235 SMU_TABLE_INIT(tables, SMU_TABLE_ACTIVITY_MONITOR_COEFF, sizeof(DpmActivityMonitorCoeffExt_t),
236 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
237 SMU_TABLE_INIT(tables, SMU_TABLE_SMU_METRICS, max(sizeof(SmuMetrics_t), sizeof(SmuMetrics_legacy_t)),
238 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
239
240 smu_table->metrics_table = kzalloc(max(sizeof(SmuMetrics_t), sizeof(SmuMetrics_legacy_t)), GFP_KERNEL);
241 if (!smu_table->metrics_table)
242 goto err0_out;
243 smu_table->metrics_time = 0;
244
245 smu_table->gpu_metrics_table_size = sizeof(struct gpu_metrics_v2_2);
246 smu_table->gpu_metrics_table_size = max(smu_table->gpu_metrics_table_size, sizeof(struct gpu_metrics_v2_3));
247 smu_table->gpu_metrics_table_size = max(smu_table->gpu_metrics_table_size, sizeof(struct gpu_metrics_v2_4));
248 smu_table->gpu_metrics_table = kzalloc(smu_table->gpu_metrics_table_size, GFP_KERNEL);
249 if (!smu_table->gpu_metrics_table)
250 goto err1_out;
251
252 smu_table->watermarks_table = kzalloc(sizeof(Watermarks_t), GFP_KERNEL);
253 if (!smu_table->watermarks_table)
254 goto err2_out;
255
256 smu_table->clocks_table = kzalloc(sizeof(DpmClocks_t), GFP_KERNEL);
257 if (!smu_table->clocks_table)
258 goto err3_out;
259
260 return 0;
261
262 err3_out:
263 kfree(smu_table->watermarks_table);
264 err2_out:
265 kfree(smu_table->gpu_metrics_table);
266 err1_out:
267 kfree(smu_table->metrics_table);
268 err0_out:
269 return -ENOMEM;
270 }
271
vangogh_get_legacy_smu_metrics_data(struct smu_context * smu,MetricsMember_t member,uint32_t * value)272 static int vangogh_get_legacy_smu_metrics_data(struct smu_context *smu,
273 MetricsMember_t member,
274 uint32_t *value)
275 {
276 struct smu_table_context *smu_table = &smu->smu_table;
277 SmuMetrics_legacy_t *metrics = (SmuMetrics_legacy_t *)smu_table->metrics_table;
278 int ret = 0;
279
280 ret = smu_cmn_get_metrics_table(smu,
281 NULL,
282 false);
283 if (ret)
284 return ret;
285
286 switch (member) {
287 case METRICS_CURR_GFXCLK:
288 *value = metrics->GfxclkFrequency;
289 break;
290 case METRICS_AVERAGE_SOCCLK:
291 *value = metrics->SocclkFrequency;
292 break;
293 case METRICS_AVERAGE_VCLK:
294 *value = metrics->VclkFrequency;
295 break;
296 case METRICS_AVERAGE_DCLK:
297 *value = metrics->DclkFrequency;
298 break;
299 case METRICS_CURR_UCLK:
300 *value = metrics->MemclkFrequency;
301 break;
302 case METRICS_AVERAGE_GFXACTIVITY:
303 *value = metrics->GfxActivity / 100;
304 break;
305 case METRICS_AVERAGE_VCNACTIVITY:
306 *value = metrics->UvdActivity / 100;
307 break;
308 case METRICS_AVERAGE_SOCKETPOWER:
309 *value = (metrics->CurrentSocketPower << 8) /
310 1000 ;
311 break;
312 case METRICS_TEMPERATURE_EDGE:
313 *value = metrics->GfxTemperature / 100 *
314 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
315 break;
316 case METRICS_TEMPERATURE_HOTSPOT:
317 *value = metrics->SocTemperature / 100 *
318 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
319 break;
320 case METRICS_THROTTLER_STATUS:
321 *value = metrics->ThrottlerStatus;
322 break;
323 case METRICS_VOLTAGE_VDDGFX:
324 *value = metrics->Voltage[2];
325 break;
326 case METRICS_VOLTAGE_VDDSOC:
327 *value = metrics->Voltage[1];
328 break;
329 case METRICS_AVERAGE_CPUCLK:
330 memcpy(value, &metrics->CoreFrequency[0],
331 smu->cpu_core_num * sizeof(uint16_t));
332 break;
333 default:
334 *value = UINT_MAX;
335 break;
336 }
337
338 return ret;
339 }
340
vangogh_get_smu_metrics_data(struct smu_context * smu,MetricsMember_t member,uint32_t * value)341 static int vangogh_get_smu_metrics_data(struct smu_context *smu,
342 MetricsMember_t member,
343 uint32_t *value)
344 {
345 struct smu_table_context *smu_table = &smu->smu_table;
346 SmuMetrics_t *metrics = (SmuMetrics_t *)smu_table->metrics_table;
347 int ret = 0;
348
349 ret = smu_cmn_get_metrics_table(smu,
350 NULL,
351 false);
352 if (ret)
353 return ret;
354
355 switch (member) {
356 case METRICS_CURR_GFXCLK:
357 *value = metrics->Current.GfxclkFrequency;
358 break;
359 case METRICS_AVERAGE_SOCCLK:
360 *value = metrics->Current.SocclkFrequency;
361 break;
362 case METRICS_AVERAGE_VCLK:
363 *value = metrics->Current.VclkFrequency;
364 break;
365 case METRICS_AVERAGE_DCLK:
366 *value = metrics->Current.DclkFrequency;
367 break;
368 case METRICS_CURR_UCLK:
369 *value = metrics->Current.MemclkFrequency;
370 break;
371 case METRICS_AVERAGE_GFXACTIVITY:
372 *value = metrics->Current.GfxActivity;
373 break;
374 case METRICS_AVERAGE_VCNACTIVITY:
375 *value = metrics->Current.UvdActivity;
376 break;
377 case METRICS_AVERAGE_SOCKETPOWER:
378 *value = (metrics->Average.CurrentSocketPower << 8) /
379 1000;
380 break;
381 case METRICS_CURR_SOCKETPOWER:
382 *value = (metrics->Current.CurrentSocketPower << 8) /
383 1000;
384 break;
385 case METRICS_TEMPERATURE_EDGE:
386 *value = metrics->Current.GfxTemperature / 100 *
387 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
388 break;
389 case METRICS_TEMPERATURE_HOTSPOT:
390 *value = metrics->Current.SocTemperature / 100 *
391 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
392 break;
393 case METRICS_THROTTLER_STATUS:
394 *value = metrics->Current.ThrottlerStatus;
395 break;
396 case METRICS_VOLTAGE_VDDGFX:
397 *value = metrics->Current.Voltage[2];
398 break;
399 case METRICS_VOLTAGE_VDDSOC:
400 *value = metrics->Current.Voltage[1];
401 break;
402 case METRICS_AVERAGE_CPUCLK:
403 memcpy(value, &metrics->Current.CoreFrequency[0],
404 smu->cpu_core_num * sizeof(uint16_t));
405 break;
406 default:
407 *value = UINT_MAX;
408 break;
409 }
410
411 return ret;
412 }
413
vangogh_common_get_smu_metrics_data(struct smu_context * smu,MetricsMember_t member,uint32_t * value)414 static int vangogh_common_get_smu_metrics_data(struct smu_context *smu,
415 MetricsMember_t member,
416 uint32_t *value)
417 {
418 int ret = 0;
419
420 if (smu->smc_fw_if_version < 0x3)
421 ret = vangogh_get_legacy_smu_metrics_data(smu, member, value);
422 else
423 ret = vangogh_get_smu_metrics_data(smu, member, value);
424
425 return ret;
426 }
427
vangogh_allocate_dpm_context(struct smu_context * smu)428 static int vangogh_allocate_dpm_context(struct smu_context *smu)
429 {
430 struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
431
432 smu_dpm->dpm_context = kzalloc(sizeof(struct smu_11_0_dpm_context),
433 GFP_KERNEL);
434 if (!smu_dpm->dpm_context)
435 return -ENOMEM;
436
437 smu_dpm->dpm_context_size = sizeof(struct smu_11_0_dpm_context);
438
439 return 0;
440 }
441
vangogh_init_smc_tables(struct smu_context * smu)442 static int vangogh_init_smc_tables(struct smu_context *smu)
443 {
444 int ret = 0;
445
446 ret = vangogh_tables_init(smu);
447 if (ret)
448 return ret;
449
450 ret = vangogh_allocate_dpm_context(smu);
451 if (ret)
452 return ret;
453
454 #ifdef CONFIG_X86
455 /* AMD x86 APU only */
456 smu->cpu_core_num = topology_num_cores_per_package();
457 #else
458 smu->cpu_core_num = 4;
459 #endif
460
461 return smu_v11_0_init_smc_tables(smu);
462 }
463
vangogh_dpm_set_vcn_enable(struct smu_context * smu,bool enable)464 static int vangogh_dpm_set_vcn_enable(struct smu_context *smu, bool enable)
465 {
466 int ret = 0;
467
468 if (enable) {
469 /* vcn dpm on is a prerequisite for vcn power gate messages */
470 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerUpVcn, 0, NULL);
471 if (ret)
472 return ret;
473 } else {
474 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerDownVcn, 0, NULL);
475 if (ret)
476 return ret;
477 }
478
479 return ret;
480 }
481
vangogh_dpm_set_jpeg_enable(struct smu_context * smu,bool enable)482 static int vangogh_dpm_set_jpeg_enable(struct smu_context *smu, bool enable)
483 {
484 int ret = 0;
485
486 if (enable) {
487 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerUpJpeg, 0, NULL);
488 if (ret)
489 return ret;
490 } else {
491 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerDownJpeg, 0, NULL);
492 if (ret)
493 return ret;
494 }
495
496 return ret;
497 }
498
vangogh_is_dpm_running(struct smu_context * smu)499 static bool vangogh_is_dpm_running(struct smu_context *smu)
500 {
501 struct amdgpu_device *adev = smu->adev;
502 int ret = 0;
503 uint64_t feature_enabled;
504
505 /* we need to re-init after suspend so return false */
506 if (adev->in_suspend)
507 return false;
508
509 ret = smu_cmn_get_enabled_mask(smu, &feature_enabled);
510
511 if (ret)
512 return false;
513
514 return !!(feature_enabled & SMC_DPM_FEATURE);
515 }
516
vangogh_get_dpm_clk_limited(struct smu_context * smu,enum smu_clk_type clk_type,uint32_t dpm_level,uint32_t * freq)517 static int vangogh_get_dpm_clk_limited(struct smu_context *smu, enum smu_clk_type clk_type,
518 uint32_t dpm_level, uint32_t *freq)
519 {
520 DpmClocks_t *clk_table = smu->smu_table.clocks_table;
521
522 if (!clk_table || clk_type >= SMU_CLK_COUNT)
523 return -EINVAL;
524
525 switch (clk_type) {
526 case SMU_SOCCLK:
527 if (dpm_level >= clk_table->NumSocClkLevelsEnabled)
528 return -EINVAL;
529 *freq = clk_table->SocClocks[dpm_level];
530 break;
531 case SMU_VCLK:
532 if (dpm_level >= clk_table->VcnClkLevelsEnabled)
533 return -EINVAL;
534 *freq = clk_table->VcnClocks[dpm_level].vclk;
535 break;
536 case SMU_DCLK:
537 if (dpm_level >= clk_table->VcnClkLevelsEnabled)
538 return -EINVAL;
539 *freq = clk_table->VcnClocks[dpm_level].dclk;
540 break;
541 case SMU_UCLK:
542 case SMU_MCLK:
543 if (dpm_level >= clk_table->NumDfPstatesEnabled)
544 return -EINVAL;
545 *freq = clk_table->DfPstateTable[dpm_level].memclk;
546
547 break;
548 case SMU_FCLK:
549 if (dpm_level >= clk_table->NumDfPstatesEnabled)
550 return -EINVAL;
551 *freq = clk_table->DfPstateTable[dpm_level].fclk;
552 break;
553 default:
554 return -EINVAL;
555 }
556
557 return 0;
558 }
559
vangogh_print_legacy_clk_levels(struct smu_context * smu,enum smu_clk_type clk_type,char * buf)560 static int vangogh_print_legacy_clk_levels(struct smu_context *smu,
561 enum smu_clk_type clk_type, char *buf)
562 {
563 DpmClocks_t *clk_table = smu->smu_table.clocks_table;
564 SmuMetrics_legacy_t metrics;
565 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
566 int i, idx, size = 0, ret = 0;
567 uint32_t cur_value = 0, value = 0, count = 0;
568 bool cur_value_match_level = false;
569
570 memset(&metrics, 0, sizeof(metrics));
571
572 ret = smu_cmn_get_metrics_table(smu, &metrics, false);
573 if (ret)
574 return ret;
575
576 smu_cmn_get_sysfs_buf(&buf, &size);
577
578 switch (clk_type) {
579 case SMU_OD_SCLK:
580 if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL) {
581 size += sysfs_emit_at(buf, size, "%s:\n", "OD_SCLK");
582 size += sysfs_emit_at(buf, size, "0: %10uMhz\n",
583 (smu->gfx_actual_hard_min_freq > 0) ? smu->gfx_actual_hard_min_freq : smu->gfx_default_hard_min_freq);
584 size += sysfs_emit_at(buf, size, "1: %10uMhz\n",
585 (smu->gfx_actual_soft_max_freq > 0) ? smu->gfx_actual_soft_max_freq : smu->gfx_default_soft_max_freq);
586 }
587 break;
588 case SMU_OD_CCLK:
589 if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL) {
590 size += sysfs_emit_at(buf, size, "CCLK_RANGE in Core%d:\n", smu->cpu_core_id_select);
591 size += sysfs_emit_at(buf, size, "0: %10uMhz\n",
592 (smu->cpu_actual_soft_min_freq > 0) ? smu->cpu_actual_soft_min_freq : smu->cpu_default_soft_min_freq);
593 size += sysfs_emit_at(buf, size, "1: %10uMhz\n",
594 (smu->cpu_actual_soft_max_freq > 0) ? smu->cpu_actual_soft_max_freq : smu->cpu_default_soft_max_freq);
595 }
596 break;
597 case SMU_OD_RANGE:
598 if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL) {
599 size += sysfs_emit_at(buf, size, "%s:\n", "OD_RANGE");
600 size += sysfs_emit_at(buf, size, "SCLK: %7uMhz %10uMhz\n",
601 smu->gfx_default_hard_min_freq, smu->gfx_default_soft_max_freq);
602 size += sysfs_emit_at(buf, size, "CCLK: %7uMhz %10uMhz\n",
603 smu->cpu_default_soft_min_freq, smu->cpu_default_soft_max_freq);
604 }
605 break;
606 case SMU_SOCCLK:
607 /* the level 3 ~ 6 of socclk use the same frequency for vangogh */
608 count = clk_table->NumSocClkLevelsEnabled;
609 cur_value = metrics.SocclkFrequency;
610 break;
611 case SMU_VCLK:
612 count = clk_table->VcnClkLevelsEnabled;
613 cur_value = metrics.VclkFrequency;
614 break;
615 case SMU_DCLK:
616 count = clk_table->VcnClkLevelsEnabled;
617 cur_value = metrics.DclkFrequency;
618 break;
619 case SMU_MCLK:
620 count = clk_table->NumDfPstatesEnabled;
621 cur_value = metrics.MemclkFrequency;
622 break;
623 case SMU_FCLK:
624 count = clk_table->NumDfPstatesEnabled;
625 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetFclkFrequency, 0, &cur_value);
626 if (ret)
627 return ret;
628 break;
629 default:
630 break;
631 }
632
633 switch (clk_type) {
634 case SMU_SOCCLK:
635 case SMU_VCLK:
636 case SMU_DCLK:
637 case SMU_MCLK:
638 case SMU_FCLK:
639 for (i = 0; i < count; i++) {
640 idx = (clk_type == SMU_FCLK || clk_type == SMU_MCLK) ? (count - i - 1) : i;
641 ret = vangogh_get_dpm_clk_limited(smu, clk_type, idx, &value);
642 if (ret)
643 return ret;
644 if (!value)
645 continue;
646 size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n", i, value,
647 cur_value == value ? "*" : "");
648 if (cur_value == value)
649 cur_value_match_level = true;
650 }
651
652 if (!cur_value_match_level)
653 size += sysfs_emit_at(buf, size, " %uMhz *\n", cur_value);
654 break;
655 default:
656 break;
657 }
658
659 return size;
660 }
661
vangogh_print_clk_levels(struct smu_context * smu,enum smu_clk_type clk_type,char * buf)662 static int vangogh_print_clk_levels(struct smu_context *smu,
663 enum smu_clk_type clk_type, char *buf)
664 {
665 DpmClocks_t *clk_table = smu->smu_table.clocks_table;
666 SmuMetrics_t metrics;
667 int i, idx, size = 0, ret = 0;
668 uint32_t cur_value = 0, value = 0, count = 0;
669 bool cur_value_match_level = false;
670 uint32_t min, max;
671
672 memset(&metrics, 0, sizeof(metrics));
673
674 ret = smu_cmn_get_metrics_table(smu, &metrics, false);
675 if (ret)
676 return ret;
677
678 smu_cmn_get_sysfs_buf(&buf, &size);
679
680 switch (clk_type) {
681 case SMU_OD_SCLK:
682 size += sysfs_emit_at(buf, size, "%s:\n", "OD_SCLK");
683 size += sysfs_emit_at(buf, size, "0: %10uMhz\n",
684 (smu->gfx_actual_hard_min_freq > 0) ? smu->gfx_actual_hard_min_freq : smu->gfx_default_hard_min_freq);
685 size += sysfs_emit_at(buf, size, "1: %10uMhz\n",
686 (smu->gfx_actual_soft_max_freq > 0) ? smu->gfx_actual_soft_max_freq : smu->gfx_default_soft_max_freq);
687 break;
688 case SMU_OD_CCLK:
689 size += sysfs_emit_at(buf, size, "CCLK_RANGE in Core%d:\n", smu->cpu_core_id_select);
690 size += sysfs_emit_at(buf, size, "0: %10uMhz\n",
691 (smu->cpu_actual_soft_min_freq > 0) ? smu->cpu_actual_soft_min_freq : smu->cpu_default_soft_min_freq);
692 size += sysfs_emit_at(buf, size, "1: %10uMhz\n",
693 (smu->cpu_actual_soft_max_freq > 0) ? smu->cpu_actual_soft_max_freq : smu->cpu_default_soft_max_freq);
694 break;
695 case SMU_OD_RANGE:
696 size += sysfs_emit_at(buf, size, "%s:\n", "OD_RANGE");
697 size += sysfs_emit_at(buf, size, "SCLK: %7uMhz %10uMhz\n",
698 smu->gfx_default_hard_min_freq, smu->gfx_default_soft_max_freq);
699 size += sysfs_emit_at(buf, size, "CCLK: %7uMhz %10uMhz\n",
700 smu->cpu_default_soft_min_freq, smu->cpu_default_soft_max_freq);
701 break;
702 case SMU_SOCCLK:
703 /* the level 3 ~ 6 of socclk use the same frequency for vangogh */
704 count = clk_table->NumSocClkLevelsEnabled;
705 cur_value = metrics.Current.SocclkFrequency;
706 break;
707 case SMU_VCLK:
708 count = clk_table->VcnClkLevelsEnabled;
709 cur_value = metrics.Current.VclkFrequency;
710 break;
711 case SMU_DCLK:
712 count = clk_table->VcnClkLevelsEnabled;
713 cur_value = metrics.Current.DclkFrequency;
714 break;
715 case SMU_MCLK:
716 count = clk_table->NumDfPstatesEnabled;
717 cur_value = metrics.Current.MemclkFrequency;
718 break;
719 case SMU_FCLK:
720 count = clk_table->NumDfPstatesEnabled;
721 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetFclkFrequency, 0, &cur_value);
722 if (ret)
723 return ret;
724 break;
725 case SMU_GFXCLK:
726 case SMU_SCLK:
727 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetGfxclkFrequency, 0, &cur_value);
728 if (ret) {
729 return ret;
730 }
731 break;
732 default:
733 break;
734 }
735
736 switch (clk_type) {
737 case SMU_SOCCLK:
738 case SMU_VCLK:
739 case SMU_DCLK:
740 case SMU_MCLK:
741 case SMU_FCLK:
742 for (i = 0; i < count; i++) {
743 idx = (clk_type == SMU_FCLK || clk_type == SMU_MCLK) ? (count - i - 1) : i;
744 ret = vangogh_get_dpm_clk_limited(smu, clk_type, idx, &value);
745 if (ret)
746 return ret;
747 if (!value)
748 continue;
749 size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n", i, value,
750 cur_value == value ? "*" : "");
751 if (cur_value == value)
752 cur_value_match_level = true;
753 }
754
755 if (!cur_value_match_level)
756 size += sysfs_emit_at(buf, size, " %uMhz *\n", cur_value);
757 break;
758 case SMU_GFXCLK:
759 case SMU_SCLK:
760 min = (smu->gfx_actual_hard_min_freq > 0) ? smu->gfx_actual_hard_min_freq : smu->gfx_default_hard_min_freq;
761 max = (smu->gfx_actual_soft_max_freq > 0) ? smu->gfx_actual_soft_max_freq : smu->gfx_default_soft_max_freq;
762 if (cur_value == max)
763 i = 2;
764 else if (cur_value == min)
765 i = 0;
766 else
767 i = 1;
768 size += sysfs_emit_at(buf, size, "0: %uMhz %s\n", min,
769 i == 0 ? "*" : "");
770 size += sysfs_emit_at(buf, size, "1: %uMhz %s\n",
771 i == 1 ? cur_value : VANGOGH_UMD_PSTATE_STANDARD_GFXCLK,
772 i == 1 ? "*" : "");
773 size += sysfs_emit_at(buf, size, "2: %uMhz %s\n", max,
774 i == 2 ? "*" : "");
775 break;
776 default:
777 break;
778 }
779
780 return size;
781 }
782
vangogh_common_print_clk_levels(struct smu_context * smu,enum smu_clk_type clk_type,char * buf)783 static int vangogh_common_print_clk_levels(struct smu_context *smu,
784 enum smu_clk_type clk_type, char *buf)
785 {
786 int ret = 0;
787
788 if (smu->smc_fw_if_version < 0x3)
789 ret = vangogh_print_legacy_clk_levels(smu, clk_type, buf);
790 else
791 ret = vangogh_print_clk_levels(smu, clk_type, buf);
792
793 return ret;
794 }
795
vangogh_get_profiling_clk_mask(struct smu_context * smu,enum amd_dpm_forced_level level,uint32_t * vclk_mask,uint32_t * dclk_mask,uint32_t * mclk_mask,uint32_t * fclk_mask,uint32_t * soc_mask)796 static int vangogh_get_profiling_clk_mask(struct smu_context *smu,
797 enum amd_dpm_forced_level level,
798 uint32_t *vclk_mask,
799 uint32_t *dclk_mask,
800 uint32_t *mclk_mask,
801 uint32_t *fclk_mask,
802 uint32_t *soc_mask)
803 {
804 DpmClocks_t *clk_table = smu->smu_table.clocks_table;
805
806 if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK) {
807 if (mclk_mask)
808 *mclk_mask = clk_table->NumDfPstatesEnabled - 1;
809
810 if (fclk_mask)
811 *fclk_mask = clk_table->NumDfPstatesEnabled - 1;
812
813 if (soc_mask)
814 *soc_mask = 0;
815 } else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
816 if (mclk_mask)
817 *mclk_mask = 0;
818
819 if (fclk_mask)
820 *fclk_mask = 0;
821
822 if (soc_mask)
823 *soc_mask = 1;
824
825 if (vclk_mask)
826 *vclk_mask = 1;
827
828 if (dclk_mask)
829 *dclk_mask = 1;
830 } else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD) {
831 if (mclk_mask)
832 *mclk_mask = 0;
833
834 if (fclk_mask)
835 *fclk_mask = 0;
836
837 if (soc_mask)
838 *soc_mask = 1;
839
840 if (vclk_mask)
841 *vclk_mask = 1;
842
843 if (dclk_mask)
844 *dclk_mask = 1;
845 }
846
847 return 0;
848 }
849
vangogh_clk_dpm_is_enabled(struct smu_context * smu,enum smu_clk_type clk_type)850 static bool vangogh_clk_dpm_is_enabled(struct smu_context *smu,
851 enum smu_clk_type clk_type)
852 {
853 enum smu_feature_mask feature_id = 0;
854
855 switch (clk_type) {
856 case SMU_MCLK:
857 case SMU_UCLK:
858 case SMU_FCLK:
859 feature_id = SMU_FEATURE_DPM_FCLK_BIT;
860 break;
861 case SMU_GFXCLK:
862 case SMU_SCLK:
863 feature_id = SMU_FEATURE_DPM_GFXCLK_BIT;
864 break;
865 case SMU_SOCCLK:
866 feature_id = SMU_FEATURE_DPM_SOCCLK_BIT;
867 break;
868 case SMU_VCLK:
869 case SMU_DCLK:
870 feature_id = SMU_FEATURE_VCN_DPM_BIT;
871 break;
872 default:
873 return true;
874 }
875
876 if (!smu_cmn_feature_is_enabled(smu, feature_id))
877 return false;
878
879 return true;
880 }
881
vangogh_get_dpm_ultimate_freq(struct smu_context * smu,enum smu_clk_type clk_type,uint32_t * min,uint32_t * max)882 static int vangogh_get_dpm_ultimate_freq(struct smu_context *smu,
883 enum smu_clk_type clk_type,
884 uint32_t *min,
885 uint32_t *max)
886 {
887 int ret = 0;
888 uint32_t soc_mask;
889 uint32_t vclk_mask;
890 uint32_t dclk_mask;
891 uint32_t mclk_mask;
892 uint32_t fclk_mask;
893 uint32_t clock_limit;
894
895 if (!vangogh_clk_dpm_is_enabled(smu, clk_type)) {
896 switch (clk_type) {
897 case SMU_MCLK:
898 case SMU_UCLK:
899 clock_limit = smu->smu_table.boot_values.uclk;
900 break;
901 case SMU_FCLK:
902 clock_limit = smu->smu_table.boot_values.fclk;
903 break;
904 case SMU_GFXCLK:
905 case SMU_SCLK:
906 clock_limit = smu->smu_table.boot_values.gfxclk;
907 break;
908 case SMU_SOCCLK:
909 clock_limit = smu->smu_table.boot_values.socclk;
910 break;
911 case SMU_VCLK:
912 clock_limit = smu->smu_table.boot_values.vclk;
913 break;
914 case SMU_DCLK:
915 clock_limit = smu->smu_table.boot_values.dclk;
916 break;
917 default:
918 clock_limit = 0;
919 break;
920 }
921
922 /* clock in Mhz unit */
923 if (min)
924 *min = clock_limit / 100;
925 if (max)
926 *max = clock_limit / 100;
927
928 return 0;
929 }
930 if (max) {
931 ret = vangogh_get_profiling_clk_mask(smu,
932 AMD_DPM_FORCED_LEVEL_PROFILE_PEAK,
933 &vclk_mask,
934 &dclk_mask,
935 &mclk_mask,
936 &fclk_mask,
937 &soc_mask);
938 if (ret)
939 goto failed;
940
941 switch (clk_type) {
942 case SMU_UCLK:
943 case SMU_MCLK:
944 ret = vangogh_get_dpm_clk_limited(smu, clk_type, mclk_mask, max);
945 if (ret)
946 goto failed;
947 break;
948 case SMU_SOCCLK:
949 ret = vangogh_get_dpm_clk_limited(smu, clk_type, soc_mask, max);
950 if (ret)
951 goto failed;
952 break;
953 case SMU_FCLK:
954 ret = vangogh_get_dpm_clk_limited(smu, clk_type, fclk_mask, max);
955 if (ret)
956 goto failed;
957 break;
958 case SMU_VCLK:
959 ret = vangogh_get_dpm_clk_limited(smu, clk_type, vclk_mask, max);
960 if (ret)
961 goto failed;
962 break;
963 case SMU_DCLK:
964 ret = vangogh_get_dpm_clk_limited(smu, clk_type, dclk_mask, max);
965 if (ret)
966 goto failed;
967 break;
968 default:
969 ret = -EINVAL;
970 goto failed;
971 }
972 }
973 if (min) {
974 ret = vangogh_get_profiling_clk_mask(smu,
975 AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK,
976 NULL,
977 NULL,
978 &mclk_mask,
979 &fclk_mask,
980 &soc_mask);
981 if (ret)
982 goto failed;
983
984 vclk_mask = dclk_mask = 0;
985
986 switch (clk_type) {
987 case SMU_UCLK:
988 case SMU_MCLK:
989 ret = vangogh_get_dpm_clk_limited(smu, clk_type, mclk_mask, min);
990 if (ret)
991 goto failed;
992 break;
993 case SMU_SOCCLK:
994 ret = vangogh_get_dpm_clk_limited(smu, clk_type, soc_mask, min);
995 if (ret)
996 goto failed;
997 break;
998 case SMU_FCLK:
999 ret = vangogh_get_dpm_clk_limited(smu, clk_type, fclk_mask, min);
1000 if (ret)
1001 goto failed;
1002 break;
1003 case SMU_VCLK:
1004 ret = vangogh_get_dpm_clk_limited(smu, clk_type, vclk_mask, min);
1005 if (ret)
1006 goto failed;
1007 break;
1008 case SMU_DCLK:
1009 ret = vangogh_get_dpm_clk_limited(smu, clk_type, dclk_mask, min);
1010 if (ret)
1011 goto failed;
1012 break;
1013 default:
1014 ret = -EINVAL;
1015 goto failed;
1016 }
1017 }
1018 failed:
1019 return ret;
1020 }
1021
vangogh_get_power_profile_mode(struct smu_context * smu,char * buf)1022 static int vangogh_get_power_profile_mode(struct smu_context *smu,
1023 char *buf)
1024 {
1025 uint32_t i, size = 0;
1026 int16_t workload_type = 0;
1027
1028 if (!buf)
1029 return -EINVAL;
1030
1031 for (i = 0; i < PP_SMC_POWER_PROFILE_COUNT; i++) {
1032 /*
1033 * Conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT
1034 * Not all profile modes are supported on vangogh.
1035 */
1036 workload_type = smu_cmn_to_asic_specific_index(smu,
1037 CMN2ASIC_MAPPING_WORKLOAD,
1038 i);
1039
1040 if (workload_type < 0)
1041 continue;
1042
1043 size += sysfs_emit_at(buf, size, "%2d %14s%s\n",
1044 i, amdgpu_pp_profile_name[i], (i == smu->power_profile_mode) ? "*" : " ");
1045 }
1046
1047 return size;
1048 }
1049
vangogh_set_power_profile_mode(struct smu_context * smu,u32 workload_mask,long * custom_params,u32 custom_params_max_idx)1050 static int vangogh_set_power_profile_mode(struct smu_context *smu,
1051 u32 workload_mask,
1052 long *custom_params,
1053 u32 custom_params_max_idx)
1054 {
1055 u32 backend_workload_mask = 0;
1056 int ret;
1057
1058 smu_cmn_get_backend_workload_mask(smu, workload_mask,
1059 &backend_workload_mask);
1060
1061 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_ActiveProcessNotify,
1062 backend_workload_mask,
1063 NULL);
1064 if (ret) {
1065 dev_err_once(smu->adev->dev, "Fail to set workload mask 0x%08x\n",
1066 workload_mask);
1067 return ret;
1068 }
1069
1070 return ret;
1071 }
1072
vangogh_set_soft_freq_limited_range(struct smu_context * smu,enum smu_clk_type clk_type,uint32_t min,uint32_t max)1073 static int vangogh_set_soft_freq_limited_range(struct smu_context *smu,
1074 enum smu_clk_type clk_type,
1075 uint32_t min,
1076 uint32_t max)
1077 {
1078 int ret = 0;
1079
1080 if (!vangogh_clk_dpm_is_enabled(smu, clk_type))
1081 return 0;
1082
1083 switch (clk_type) {
1084 case SMU_GFXCLK:
1085 case SMU_SCLK:
1086 ret = smu_cmn_send_smc_msg_with_param(smu,
1087 SMU_MSG_SetHardMinGfxClk,
1088 min, NULL);
1089 if (ret)
1090 return ret;
1091
1092 ret = smu_cmn_send_smc_msg_with_param(smu,
1093 SMU_MSG_SetSoftMaxGfxClk,
1094 max, NULL);
1095 if (ret)
1096 return ret;
1097 break;
1098 case SMU_FCLK:
1099 ret = smu_cmn_send_smc_msg_with_param(smu,
1100 SMU_MSG_SetHardMinFclkByFreq,
1101 min, NULL);
1102 if (ret)
1103 return ret;
1104
1105 ret = smu_cmn_send_smc_msg_with_param(smu,
1106 SMU_MSG_SetSoftMaxFclkByFreq,
1107 max, NULL);
1108 if (ret)
1109 return ret;
1110 break;
1111 case SMU_SOCCLK:
1112 ret = smu_cmn_send_smc_msg_with_param(smu,
1113 SMU_MSG_SetHardMinSocclkByFreq,
1114 min, NULL);
1115 if (ret)
1116 return ret;
1117
1118 ret = smu_cmn_send_smc_msg_with_param(smu,
1119 SMU_MSG_SetSoftMaxSocclkByFreq,
1120 max, NULL);
1121 if (ret)
1122 return ret;
1123 break;
1124 case SMU_VCLK:
1125 ret = smu_cmn_send_smc_msg_with_param(smu,
1126 SMU_MSG_SetHardMinVcn,
1127 min << 16, NULL);
1128 if (ret)
1129 return ret;
1130 ret = smu_cmn_send_smc_msg_with_param(smu,
1131 SMU_MSG_SetSoftMaxVcn,
1132 max << 16, NULL);
1133 if (ret)
1134 return ret;
1135 break;
1136 case SMU_DCLK:
1137 ret = smu_cmn_send_smc_msg_with_param(smu,
1138 SMU_MSG_SetHardMinVcn,
1139 min, NULL);
1140 if (ret)
1141 return ret;
1142 ret = smu_cmn_send_smc_msg_with_param(smu,
1143 SMU_MSG_SetSoftMaxVcn,
1144 max, NULL);
1145 if (ret)
1146 return ret;
1147 break;
1148 default:
1149 return -EINVAL;
1150 }
1151
1152 return ret;
1153 }
1154
vangogh_force_clk_levels(struct smu_context * smu,enum smu_clk_type clk_type,uint32_t mask)1155 static int vangogh_force_clk_levels(struct smu_context *smu,
1156 enum smu_clk_type clk_type, uint32_t mask)
1157 {
1158 uint32_t soft_min_level = 0, soft_max_level = 0;
1159 uint32_t min_freq = 0, max_freq = 0;
1160 int ret = 0 ;
1161
1162 soft_min_level = mask ? (ffs(mask) - 1) : 0;
1163 soft_max_level = mask ? (fls(mask) - 1) : 0;
1164
1165 switch (clk_type) {
1166 case SMU_SOCCLK:
1167 ret = vangogh_get_dpm_clk_limited(smu, clk_type,
1168 soft_min_level, &min_freq);
1169 if (ret)
1170 return ret;
1171 ret = vangogh_get_dpm_clk_limited(smu, clk_type,
1172 soft_max_level, &max_freq);
1173 if (ret)
1174 return ret;
1175 ret = smu_cmn_send_smc_msg_with_param(smu,
1176 SMU_MSG_SetSoftMaxSocclkByFreq,
1177 max_freq, NULL);
1178 if (ret)
1179 return ret;
1180 ret = smu_cmn_send_smc_msg_with_param(smu,
1181 SMU_MSG_SetHardMinSocclkByFreq,
1182 min_freq, NULL);
1183 if (ret)
1184 return ret;
1185 break;
1186 case SMU_FCLK:
1187 ret = vangogh_get_dpm_clk_limited(smu,
1188 clk_type, soft_min_level, &min_freq);
1189 if (ret)
1190 return ret;
1191 ret = vangogh_get_dpm_clk_limited(smu,
1192 clk_type, soft_max_level, &max_freq);
1193 if (ret)
1194 return ret;
1195 ret = smu_cmn_send_smc_msg_with_param(smu,
1196 SMU_MSG_SetSoftMaxFclkByFreq,
1197 max_freq, NULL);
1198 if (ret)
1199 return ret;
1200 ret = smu_cmn_send_smc_msg_with_param(smu,
1201 SMU_MSG_SetHardMinFclkByFreq,
1202 min_freq, NULL);
1203 if (ret)
1204 return ret;
1205 break;
1206 case SMU_VCLK:
1207 ret = vangogh_get_dpm_clk_limited(smu,
1208 clk_type, soft_min_level, &min_freq);
1209 if (ret)
1210 return ret;
1211
1212 ret = vangogh_get_dpm_clk_limited(smu,
1213 clk_type, soft_max_level, &max_freq);
1214 if (ret)
1215 return ret;
1216
1217
1218 ret = smu_cmn_send_smc_msg_with_param(smu,
1219 SMU_MSG_SetHardMinVcn,
1220 min_freq << 16, NULL);
1221 if (ret)
1222 return ret;
1223
1224 ret = smu_cmn_send_smc_msg_with_param(smu,
1225 SMU_MSG_SetSoftMaxVcn,
1226 max_freq << 16, NULL);
1227 if (ret)
1228 return ret;
1229
1230 break;
1231 case SMU_DCLK:
1232 ret = vangogh_get_dpm_clk_limited(smu,
1233 clk_type, soft_min_level, &min_freq);
1234 if (ret)
1235 return ret;
1236
1237 ret = vangogh_get_dpm_clk_limited(smu,
1238 clk_type, soft_max_level, &max_freq);
1239 if (ret)
1240 return ret;
1241
1242 ret = smu_cmn_send_smc_msg_with_param(smu,
1243 SMU_MSG_SetHardMinVcn,
1244 min_freq, NULL);
1245 if (ret)
1246 return ret;
1247
1248 ret = smu_cmn_send_smc_msg_with_param(smu,
1249 SMU_MSG_SetSoftMaxVcn,
1250 max_freq, NULL);
1251 if (ret)
1252 return ret;
1253
1254 break;
1255 default:
1256 break;
1257 }
1258
1259 return ret;
1260 }
1261
vangogh_force_dpm_limit_value(struct smu_context * smu,bool highest)1262 static int vangogh_force_dpm_limit_value(struct smu_context *smu, bool highest)
1263 {
1264 int ret = 0, i = 0;
1265 uint32_t min_freq, max_freq, force_freq;
1266 enum smu_clk_type clk_type;
1267
1268 enum smu_clk_type clks[] = {
1269 SMU_SOCCLK,
1270 SMU_VCLK,
1271 SMU_DCLK,
1272 SMU_FCLK,
1273 };
1274
1275 for (i = 0; i < ARRAY_SIZE(clks); i++) {
1276 clk_type = clks[i];
1277 ret = vangogh_get_dpm_ultimate_freq(smu, clk_type, &min_freq, &max_freq);
1278 if (ret)
1279 return ret;
1280
1281 force_freq = highest ? max_freq : min_freq;
1282 ret = vangogh_set_soft_freq_limited_range(smu, clk_type, force_freq, force_freq);
1283 if (ret)
1284 return ret;
1285 }
1286
1287 return ret;
1288 }
1289
vangogh_unforce_dpm_levels(struct smu_context * smu)1290 static int vangogh_unforce_dpm_levels(struct smu_context *smu)
1291 {
1292 int ret = 0, i = 0;
1293 uint32_t min_freq, max_freq;
1294 enum smu_clk_type clk_type;
1295
1296 struct clk_feature_map {
1297 enum smu_clk_type clk_type;
1298 uint32_t feature;
1299 } clk_feature_map[] = {
1300 {SMU_FCLK, SMU_FEATURE_DPM_FCLK_BIT},
1301 {SMU_SOCCLK, SMU_FEATURE_DPM_SOCCLK_BIT},
1302 {SMU_VCLK, SMU_FEATURE_VCN_DPM_BIT},
1303 {SMU_DCLK, SMU_FEATURE_VCN_DPM_BIT},
1304 };
1305
1306 for (i = 0; i < ARRAY_SIZE(clk_feature_map); i++) {
1307
1308 if (!smu_cmn_feature_is_enabled(smu, clk_feature_map[i].feature))
1309 continue;
1310
1311 clk_type = clk_feature_map[i].clk_type;
1312
1313 ret = vangogh_get_dpm_ultimate_freq(smu, clk_type, &min_freq, &max_freq);
1314
1315 if (ret)
1316 return ret;
1317
1318 ret = vangogh_set_soft_freq_limited_range(smu, clk_type, min_freq, max_freq);
1319
1320 if (ret)
1321 return ret;
1322 }
1323
1324 return ret;
1325 }
1326
vangogh_set_peak_clock_by_device(struct smu_context * smu)1327 static int vangogh_set_peak_clock_by_device(struct smu_context *smu)
1328 {
1329 int ret = 0;
1330 uint32_t socclk_freq = 0, fclk_freq = 0;
1331 uint32_t vclk_freq = 0, dclk_freq = 0;
1332
1333 ret = vangogh_get_dpm_ultimate_freq(smu, SMU_FCLK, NULL, &fclk_freq);
1334 if (ret)
1335 return ret;
1336
1337 ret = vangogh_set_soft_freq_limited_range(smu, SMU_FCLK, fclk_freq, fclk_freq);
1338 if (ret)
1339 return ret;
1340
1341 ret = vangogh_get_dpm_ultimate_freq(smu, SMU_SOCCLK, NULL, &socclk_freq);
1342 if (ret)
1343 return ret;
1344
1345 ret = vangogh_set_soft_freq_limited_range(smu, SMU_SOCCLK, socclk_freq, socclk_freq);
1346 if (ret)
1347 return ret;
1348
1349 ret = vangogh_get_dpm_ultimate_freq(smu, SMU_VCLK, NULL, &vclk_freq);
1350 if (ret)
1351 return ret;
1352
1353 ret = vangogh_set_soft_freq_limited_range(smu, SMU_VCLK, vclk_freq, vclk_freq);
1354 if (ret)
1355 return ret;
1356
1357 ret = vangogh_get_dpm_ultimate_freq(smu, SMU_DCLK, NULL, &dclk_freq);
1358 if (ret)
1359 return ret;
1360
1361 ret = vangogh_set_soft_freq_limited_range(smu, SMU_DCLK, dclk_freq, dclk_freq);
1362 if (ret)
1363 return ret;
1364
1365 return ret;
1366 }
1367
vangogh_set_performance_level(struct smu_context * smu,enum amd_dpm_forced_level level)1368 static int vangogh_set_performance_level(struct smu_context *smu,
1369 enum amd_dpm_forced_level level)
1370 {
1371 int ret = 0, i;
1372 uint32_t soc_mask, mclk_mask, fclk_mask;
1373 uint32_t vclk_mask = 0, dclk_mask = 0;
1374
1375 smu->cpu_actual_soft_min_freq = smu->cpu_default_soft_min_freq;
1376 smu->cpu_actual_soft_max_freq = smu->cpu_default_soft_max_freq;
1377
1378 switch (level) {
1379 case AMD_DPM_FORCED_LEVEL_HIGH:
1380 smu->gfx_actual_hard_min_freq = smu->gfx_default_soft_max_freq;
1381 smu->gfx_actual_soft_max_freq = smu->gfx_default_soft_max_freq;
1382
1383
1384 ret = vangogh_force_dpm_limit_value(smu, true);
1385 if (ret)
1386 return ret;
1387 break;
1388 case AMD_DPM_FORCED_LEVEL_LOW:
1389 smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq;
1390 smu->gfx_actual_soft_max_freq = smu->gfx_default_hard_min_freq;
1391
1392 ret = vangogh_force_dpm_limit_value(smu, false);
1393 if (ret)
1394 return ret;
1395 break;
1396 case AMD_DPM_FORCED_LEVEL_AUTO:
1397 smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq;
1398 smu->gfx_actual_soft_max_freq = smu->gfx_default_soft_max_freq;
1399
1400 ret = vangogh_unforce_dpm_levels(smu);
1401 if (ret)
1402 return ret;
1403 break;
1404 case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD:
1405 smu->gfx_actual_hard_min_freq = VANGOGH_UMD_PSTATE_STANDARD_GFXCLK;
1406 smu->gfx_actual_soft_max_freq = VANGOGH_UMD_PSTATE_STANDARD_GFXCLK;
1407
1408 ret = vangogh_get_profiling_clk_mask(smu, level,
1409 &vclk_mask,
1410 &dclk_mask,
1411 &mclk_mask,
1412 &fclk_mask,
1413 &soc_mask);
1414 if (ret)
1415 return ret;
1416
1417 vangogh_force_clk_levels(smu, SMU_FCLK, 1 << fclk_mask);
1418 vangogh_force_clk_levels(smu, SMU_SOCCLK, 1 << soc_mask);
1419 vangogh_force_clk_levels(smu, SMU_VCLK, 1 << vclk_mask);
1420 vangogh_force_clk_levels(smu, SMU_DCLK, 1 << dclk_mask);
1421 break;
1422 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK:
1423 smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq;
1424 smu->gfx_actual_soft_max_freq = smu->gfx_default_hard_min_freq;
1425 break;
1426 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK:
1427 smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq;
1428 smu->gfx_actual_soft_max_freq = smu->gfx_default_soft_max_freq;
1429
1430 ret = vangogh_get_profiling_clk_mask(smu, level,
1431 NULL,
1432 NULL,
1433 &mclk_mask,
1434 &fclk_mask,
1435 NULL);
1436 if (ret)
1437 return ret;
1438
1439 vangogh_force_clk_levels(smu, SMU_FCLK, 1 << fclk_mask);
1440 break;
1441 case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK:
1442 smu->gfx_actual_hard_min_freq = VANGOGH_UMD_PSTATE_PEAK_GFXCLK;
1443 smu->gfx_actual_soft_max_freq = VANGOGH_UMD_PSTATE_PEAK_GFXCLK;
1444
1445 ret = vangogh_set_peak_clock_by_device(smu);
1446 if (ret)
1447 return ret;
1448 break;
1449 case AMD_DPM_FORCED_LEVEL_MANUAL:
1450 case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT:
1451 default:
1452 return 0;
1453 }
1454
1455 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinGfxClk,
1456 smu->gfx_actual_hard_min_freq, NULL);
1457 if (ret)
1458 return ret;
1459
1460 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxGfxClk,
1461 smu->gfx_actual_soft_max_freq, NULL);
1462 if (ret)
1463 return ret;
1464
1465 if (smu->adev->pm.fw_version >= 0x43f1b00) {
1466 for (i = 0; i < smu->cpu_core_num; i++) {
1467 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMinCclk,
1468 ((i << 20)
1469 | smu->cpu_actual_soft_min_freq),
1470 NULL);
1471 if (ret)
1472 return ret;
1473
1474 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxCclk,
1475 ((i << 20)
1476 | smu->cpu_actual_soft_max_freq),
1477 NULL);
1478 if (ret)
1479 return ret;
1480 }
1481 }
1482
1483 return ret;
1484 }
1485
vangogh_read_sensor(struct smu_context * smu,enum amd_pp_sensors sensor,void * data,uint32_t * size)1486 static int vangogh_read_sensor(struct smu_context *smu,
1487 enum amd_pp_sensors sensor,
1488 void *data, uint32_t *size)
1489 {
1490 int ret = 0;
1491
1492 if (!data || !size)
1493 return -EINVAL;
1494
1495 switch (sensor) {
1496 case AMDGPU_PP_SENSOR_GPU_LOAD:
1497 ret = vangogh_common_get_smu_metrics_data(smu,
1498 METRICS_AVERAGE_GFXACTIVITY,
1499 (uint32_t *)data);
1500 *size = 4;
1501 break;
1502 case AMDGPU_PP_SENSOR_VCN_LOAD:
1503 ret = vangogh_common_get_smu_metrics_data(smu,
1504 METRICS_AVERAGE_VCNACTIVITY,
1505 (uint32_t *)data);
1506 *size = 4;
1507 break;
1508 case AMDGPU_PP_SENSOR_GPU_AVG_POWER:
1509 ret = vangogh_common_get_smu_metrics_data(smu,
1510 METRICS_AVERAGE_SOCKETPOWER,
1511 (uint32_t *)data);
1512 *size = 4;
1513 break;
1514 case AMDGPU_PP_SENSOR_GPU_INPUT_POWER:
1515 ret = vangogh_common_get_smu_metrics_data(smu,
1516 METRICS_CURR_SOCKETPOWER,
1517 (uint32_t *)data);
1518 *size = 4;
1519 break;
1520 case AMDGPU_PP_SENSOR_EDGE_TEMP:
1521 ret = vangogh_common_get_smu_metrics_data(smu,
1522 METRICS_TEMPERATURE_EDGE,
1523 (uint32_t *)data);
1524 *size = 4;
1525 break;
1526 case AMDGPU_PP_SENSOR_HOTSPOT_TEMP:
1527 ret = vangogh_common_get_smu_metrics_data(smu,
1528 METRICS_TEMPERATURE_HOTSPOT,
1529 (uint32_t *)data);
1530 *size = 4;
1531 break;
1532 case AMDGPU_PP_SENSOR_GFX_MCLK:
1533 ret = vangogh_common_get_smu_metrics_data(smu,
1534 METRICS_CURR_UCLK,
1535 (uint32_t *)data);
1536 *(uint32_t *)data *= 100;
1537 *size = 4;
1538 break;
1539 case AMDGPU_PP_SENSOR_GFX_SCLK:
1540 ret = vangogh_common_get_smu_metrics_data(smu,
1541 METRICS_CURR_GFXCLK,
1542 (uint32_t *)data);
1543 *(uint32_t *)data *= 100;
1544 *size = 4;
1545 break;
1546 case AMDGPU_PP_SENSOR_VDDGFX:
1547 ret = vangogh_common_get_smu_metrics_data(smu,
1548 METRICS_VOLTAGE_VDDGFX,
1549 (uint32_t *)data);
1550 *size = 4;
1551 break;
1552 case AMDGPU_PP_SENSOR_VDDNB:
1553 ret = vangogh_common_get_smu_metrics_data(smu,
1554 METRICS_VOLTAGE_VDDSOC,
1555 (uint32_t *)data);
1556 *size = 4;
1557 break;
1558 case AMDGPU_PP_SENSOR_CPU_CLK:
1559 ret = vangogh_common_get_smu_metrics_data(smu,
1560 METRICS_AVERAGE_CPUCLK,
1561 (uint32_t *)data);
1562 *size = smu->cpu_core_num * sizeof(uint16_t);
1563 break;
1564 default:
1565 ret = -EOPNOTSUPP;
1566 break;
1567 }
1568
1569 return ret;
1570 }
1571
vangogh_get_apu_thermal_limit(struct smu_context * smu,uint32_t * limit)1572 static int vangogh_get_apu_thermal_limit(struct smu_context *smu, uint32_t *limit)
1573 {
1574 return smu_cmn_send_smc_msg_with_param(smu,
1575 SMU_MSG_GetThermalLimit,
1576 0, limit);
1577 }
1578
vangogh_set_apu_thermal_limit(struct smu_context * smu,uint32_t limit)1579 static int vangogh_set_apu_thermal_limit(struct smu_context *smu, uint32_t limit)
1580 {
1581 return smu_cmn_send_smc_msg_with_param(smu,
1582 SMU_MSG_SetReducedThermalLimit,
1583 limit, NULL);
1584 }
1585
1586
vangogh_set_watermarks_table(struct smu_context * smu,struct pp_smu_wm_range_sets * clock_ranges)1587 static int vangogh_set_watermarks_table(struct smu_context *smu,
1588 struct pp_smu_wm_range_sets *clock_ranges)
1589 {
1590 int i;
1591 int ret = 0;
1592 Watermarks_t *table = smu->smu_table.watermarks_table;
1593
1594 if (!table || !clock_ranges)
1595 return -EINVAL;
1596
1597 if (clock_ranges) {
1598 if (clock_ranges->num_reader_wm_sets > NUM_WM_RANGES ||
1599 clock_ranges->num_writer_wm_sets > NUM_WM_RANGES)
1600 return -EINVAL;
1601
1602 for (i = 0; i < clock_ranges->num_reader_wm_sets; i++) {
1603 table->WatermarkRow[WM_DCFCLK][i].MinClock =
1604 clock_ranges->reader_wm_sets[i].min_drain_clk_mhz;
1605 table->WatermarkRow[WM_DCFCLK][i].MaxClock =
1606 clock_ranges->reader_wm_sets[i].max_drain_clk_mhz;
1607 table->WatermarkRow[WM_DCFCLK][i].MinMclk =
1608 clock_ranges->reader_wm_sets[i].min_fill_clk_mhz;
1609 table->WatermarkRow[WM_DCFCLK][i].MaxMclk =
1610 clock_ranges->reader_wm_sets[i].max_fill_clk_mhz;
1611
1612 table->WatermarkRow[WM_DCFCLK][i].WmSetting =
1613 clock_ranges->reader_wm_sets[i].wm_inst;
1614 }
1615
1616 for (i = 0; i < clock_ranges->num_writer_wm_sets; i++) {
1617 table->WatermarkRow[WM_SOCCLK][i].MinClock =
1618 clock_ranges->writer_wm_sets[i].min_fill_clk_mhz;
1619 table->WatermarkRow[WM_SOCCLK][i].MaxClock =
1620 clock_ranges->writer_wm_sets[i].max_fill_clk_mhz;
1621 table->WatermarkRow[WM_SOCCLK][i].MinMclk =
1622 clock_ranges->writer_wm_sets[i].min_drain_clk_mhz;
1623 table->WatermarkRow[WM_SOCCLK][i].MaxMclk =
1624 clock_ranges->writer_wm_sets[i].max_drain_clk_mhz;
1625
1626 table->WatermarkRow[WM_SOCCLK][i].WmSetting =
1627 clock_ranges->writer_wm_sets[i].wm_inst;
1628 }
1629
1630 smu->watermarks_bitmap |= WATERMARKS_EXIST;
1631 }
1632
1633 /* pass data to smu controller */
1634 if ((smu->watermarks_bitmap & WATERMARKS_EXIST) &&
1635 !(smu->watermarks_bitmap & WATERMARKS_LOADED)) {
1636 ret = smu_cmn_write_watermarks_table(smu);
1637 if (ret) {
1638 dev_err(smu->adev->dev, "Failed to update WMTABLE!");
1639 return ret;
1640 }
1641 smu->watermarks_bitmap |= WATERMARKS_LOADED;
1642 }
1643
1644 return 0;
1645 }
1646
vangogh_get_legacy_gpu_metrics_v2_3(struct smu_context * smu,void ** table)1647 static ssize_t vangogh_get_legacy_gpu_metrics_v2_3(struct smu_context *smu,
1648 void **table)
1649 {
1650 struct smu_table_context *smu_table = &smu->smu_table;
1651 struct gpu_metrics_v2_3 *gpu_metrics =
1652 (struct gpu_metrics_v2_3 *)smu_table->gpu_metrics_table;
1653 SmuMetrics_legacy_t metrics;
1654 int ret = 0;
1655
1656 ret = smu_cmn_get_metrics_table(smu, &metrics, true);
1657 if (ret)
1658 return ret;
1659
1660 smu_cmn_init_soft_gpu_metrics(gpu_metrics, 2, 3);
1661
1662 gpu_metrics->temperature_gfx = metrics.GfxTemperature;
1663 gpu_metrics->temperature_soc = metrics.SocTemperature;
1664 memcpy(&gpu_metrics->temperature_core[0],
1665 &metrics.CoreTemperature[0],
1666 sizeof(uint16_t) * 4);
1667 gpu_metrics->temperature_l3[0] = metrics.L3Temperature[0];
1668
1669 gpu_metrics->average_gfx_activity = metrics.GfxActivity;
1670 gpu_metrics->average_mm_activity = metrics.UvdActivity;
1671
1672 gpu_metrics->average_socket_power = metrics.CurrentSocketPower;
1673 gpu_metrics->average_cpu_power = metrics.Power[0];
1674 gpu_metrics->average_soc_power = metrics.Power[1];
1675 gpu_metrics->average_gfx_power = metrics.Power[2];
1676 memcpy(&gpu_metrics->average_core_power[0],
1677 &metrics.CorePower[0],
1678 sizeof(uint16_t) * 4);
1679
1680 gpu_metrics->average_gfxclk_frequency = metrics.GfxclkFrequency;
1681 gpu_metrics->average_socclk_frequency = metrics.SocclkFrequency;
1682 gpu_metrics->average_uclk_frequency = metrics.MemclkFrequency;
1683 gpu_metrics->average_fclk_frequency = metrics.MemclkFrequency;
1684 gpu_metrics->average_vclk_frequency = metrics.VclkFrequency;
1685 gpu_metrics->average_dclk_frequency = metrics.DclkFrequency;
1686
1687 memcpy(&gpu_metrics->current_coreclk[0],
1688 &metrics.CoreFrequency[0],
1689 sizeof(uint16_t) * 4);
1690 gpu_metrics->current_l3clk[0] = metrics.L3Frequency[0];
1691
1692 gpu_metrics->throttle_status = metrics.ThrottlerStatus;
1693 gpu_metrics->indep_throttle_status =
1694 smu_cmn_get_indep_throttler_status(metrics.ThrottlerStatus,
1695 vangogh_throttler_map);
1696
1697 gpu_metrics->system_clock_counter = ktime_get_boottime_ns();
1698
1699 *table = (void *)gpu_metrics;
1700
1701 return sizeof(struct gpu_metrics_v2_3);
1702 }
1703
vangogh_get_legacy_gpu_metrics(struct smu_context * smu,void ** table)1704 static ssize_t vangogh_get_legacy_gpu_metrics(struct smu_context *smu,
1705 void **table)
1706 {
1707 struct smu_table_context *smu_table = &smu->smu_table;
1708 struct gpu_metrics_v2_2 *gpu_metrics =
1709 (struct gpu_metrics_v2_2 *)smu_table->gpu_metrics_table;
1710 SmuMetrics_legacy_t metrics;
1711 int ret = 0;
1712
1713 ret = smu_cmn_get_metrics_table(smu, &metrics, true);
1714 if (ret)
1715 return ret;
1716
1717 smu_cmn_init_soft_gpu_metrics(gpu_metrics, 2, 2);
1718
1719 gpu_metrics->temperature_gfx = metrics.GfxTemperature;
1720 gpu_metrics->temperature_soc = metrics.SocTemperature;
1721 memcpy(&gpu_metrics->temperature_core[0],
1722 &metrics.CoreTemperature[0],
1723 sizeof(uint16_t) * 4);
1724 gpu_metrics->temperature_l3[0] = metrics.L3Temperature[0];
1725
1726 gpu_metrics->average_gfx_activity = metrics.GfxActivity;
1727 gpu_metrics->average_mm_activity = metrics.UvdActivity;
1728
1729 gpu_metrics->average_socket_power = metrics.CurrentSocketPower;
1730 gpu_metrics->average_cpu_power = metrics.Power[0];
1731 gpu_metrics->average_soc_power = metrics.Power[1];
1732 gpu_metrics->average_gfx_power = metrics.Power[2];
1733 memcpy(&gpu_metrics->average_core_power[0],
1734 &metrics.CorePower[0],
1735 sizeof(uint16_t) * 4);
1736
1737 gpu_metrics->average_gfxclk_frequency = metrics.GfxclkFrequency;
1738 gpu_metrics->average_socclk_frequency = metrics.SocclkFrequency;
1739 gpu_metrics->average_uclk_frequency = metrics.MemclkFrequency;
1740 gpu_metrics->average_fclk_frequency = metrics.MemclkFrequency;
1741 gpu_metrics->average_vclk_frequency = metrics.VclkFrequency;
1742 gpu_metrics->average_dclk_frequency = metrics.DclkFrequency;
1743
1744 memcpy(&gpu_metrics->current_coreclk[0],
1745 &metrics.CoreFrequency[0],
1746 sizeof(uint16_t) * 4);
1747 gpu_metrics->current_l3clk[0] = metrics.L3Frequency[0];
1748
1749 gpu_metrics->throttle_status = metrics.ThrottlerStatus;
1750 gpu_metrics->indep_throttle_status =
1751 smu_cmn_get_indep_throttler_status(metrics.ThrottlerStatus,
1752 vangogh_throttler_map);
1753
1754 gpu_metrics->system_clock_counter = ktime_get_boottime_ns();
1755
1756 *table = (void *)gpu_metrics;
1757
1758 return sizeof(struct gpu_metrics_v2_2);
1759 }
1760
vangogh_get_gpu_metrics_v2_3(struct smu_context * smu,void ** table)1761 static ssize_t vangogh_get_gpu_metrics_v2_3(struct smu_context *smu,
1762 void **table)
1763 {
1764 struct smu_table_context *smu_table = &smu->smu_table;
1765 struct gpu_metrics_v2_3 *gpu_metrics =
1766 (struct gpu_metrics_v2_3 *)smu_table->gpu_metrics_table;
1767 SmuMetrics_t metrics;
1768 int ret = 0;
1769
1770 ret = smu_cmn_get_metrics_table(smu, &metrics, true);
1771 if (ret)
1772 return ret;
1773
1774 smu_cmn_init_soft_gpu_metrics(gpu_metrics, 2, 3);
1775
1776 gpu_metrics->temperature_gfx = metrics.Current.GfxTemperature;
1777 gpu_metrics->temperature_soc = metrics.Current.SocTemperature;
1778 memcpy(&gpu_metrics->temperature_core[0],
1779 &metrics.Current.CoreTemperature[0],
1780 sizeof(uint16_t) * 4);
1781 gpu_metrics->temperature_l3[0] = metrics.Current.L3Temperature[0];
1782
1783 gpu_metrics->average_temperature_gfx = metrics.Average.GfxTemperature;
1784 gpu_metrics->average_temperature_soc = metrics.Average.SocTemperature;
1785 memcpy(&gpu_metrics->average_temperature_core[0],
1786 &metrics.Average.CoreTemperature[0],
1787 sizeof(uint16_t) * 4);
1788 gpu_metrics->average_temperature_l3[0] = metrics.Average.L3Temperature[0];
1789
1790 gpu_metrics->average_gfx_activity = metrics.Current.GfxActivity;
1791 gpu_metrics->average_mm_activity = metrics.Current.UvdActivity;
1792
1793 gpu_metrics->average_socket_power = metrics.Current.CurrentSocketPower;
1794 gpu_metrics->average_cpu_power = metrics.Current.Power[0];
1795 gpu_metrics->average_soc_power = metrics.Current.Power[1];
1796 gpu_metrics->average_gfx_power = metrics.Current.Power[2];
1797 memcpy(&gpu_metrics->average_core_power[0],
1798 &metrics.Average.CorePower[0],
1799 sizeof(uint16_t) * 4);
1800
1801 gpu_metrics->average_gfxclk_frequency = metrics.Average.GfxclkFrequency;
1802 gpu_metrics->average_socclk_frequency = metrics.Average.SocclkFrequency;
1803 gpu_metrics->average_uclk_frequency = metrics.Average.MemclkFrequency;
1804 gpu_metrics->average_fclk_frequency = metrics.Average.MemclkFrequency;
1805 gpu_metrics->average_vclk_frequency = metrics.Average.VclkFrequency;
1806 gpu_metrics->average_dclk_frequency = metrics.Average.DclkFrequency;
1807
1808 gpu_metrics->current_gfxclk = metrics.Current.GfxclkFrequency;
1809 gpu_metrics->current_socclk = metrics.Current.SocclkFrequency;
1810 gpu_metrics->current_uclk = metrics.Current.MemclkFrequency;
1811 gpu_metrics->current_fclk = metrics.Current.MemclkFrequency;
1812 gpu_metrics->current_vclk = metrics.Current.VclkFrequency;
1813 gpu_metrics->current_dclk = metrics.Current.DclkFrequency;
1814
1815 memcpy(&gpu_metrics->current_coreclk[0],
1816 &metrics.Current.CoreFrequency[0],
1817 sizeof(uint16_t) * 4);
1818 gpu_metrics->current_l3clk[0] = metrics.Current.L3Frequency[0];
1819
1820 gpu_metrics->throttle_status = metrics.Current.ThrottlerStatus;
1821 gpu_metrics->indep_throttle_status =
1822 smu_cmn_get_indep_throttler_status(metrics.Current.ThrottlerStatus,
1823 vangogh_throttler_map);
1824
1825 gpu_metrics->system_clock_counter = ktime_get_boottime_ns();
1826
1827 *table = (void *)gpu_metrics;
1828
1829 return sizeof(struct gpu_metrics_v2_3);
1830 }
1831
vangogh_get_gpu_metrics_v2_4(struct smu_context * smu,void ** table)1832 static ssize_t vangogh_get_gpu_metrics_v2_4(struct smu_context *smu,
1833 void **table)
1834 {
1835 SmuMetrics_t metrics;
1836 struct smu_table_context *smu_table = &smu->smu_table;
1837 struct gpu_metrics_v2_4 *gpu_metrics =
1838 (struct gpu_metrics_v2_4 *)smu_table->gpu_metrics_table;
1839 int ret = 0;
1840
1841 ret = smu_cmn_get_metrics_table(smu, &metrics, true);
1842 if (ret)
1843 return ret;
1844
1845 smu_cmn_init_soft_gpu_metrics(gpu_metrics, 2, 4);
1846
1847 gpu_metrics->temperature_gfx = metrics.Current.GfxTemperature;
1848 gpu_metrics->temperature_soc = metrics.Current.SocTemperature;
1849 memcpy(&gpu_metrics->temperature_core[0],
1850 &metrics.Current.CoreTemperature[0],
1851 sizeof(uint16_t) * 4);
1852 gpu_metrics->temperature_l3[0] = metrics.Current.L3Temperature[0];
1853
1854 gpu_metrics->average_temperature_gfx = metrics.Average.GfxTemperature;
1855 gpu_metrics->average_temperature_soc = metrics.Average.SocTemperature;
1856 memcpy(&gpu_metrics->average_temperature_core[0],
1857 &metrics.Average.CoreTemperature[0],
1858 sizeof(uint16_t) * 4);
1859 gpu_metrics->average_temperature_l3[0] = metrics.Average.L3Temperature[0];
1860
1861 gpu_metrics->average_gfx_activity = metrics.Average.GfxActivity;
1862 gpu_metrics->average_mm_activity = metrics.Average.UvdActivity;
1863
1864 gpu_metrics->average_socket_power = metrics.Average.CurrentSocketPower;
1865 gpu_metrics->average_cpu_power = metrics.Average.Power[0];
1866 gpu_metrics->average_soc_power = metrics.Average.Power[1];
1867 gpu_metrics->average_gfx_power = metrics.Average.Power[2];
1868
1869 gpu_metrics->average_cpu_voltage = metrics.Average.Voltage[0];
1870 gpu_metrics->average_soc_voltage = metrics.Average.Voltage[1];
1871 gpu_metrics->average_gfx_voltage = metrics.Average.Voltage[2];
1872
1873 gpu_metrics->average_cpu_current = metrics.Average.Current[0];
1874 gpu_metrics->average_soc_current = metrics.Average.Current[1];
1875 gpu_metrics->average_gfx_current = metrics.Average.Current[2];
1876
1877 memcpy(&gpu_metrics->average_core_power[0],
1878 &metrics.Average.CorePower[0],
1879 sizeof(uint16_t) * 4);
1880
1881 gpu_metrics->average_gfxclk_frequency = metrics.Average.GfxclkFrequency;
1882 gpu_metrics->average_socclk_frequency = metrics.Average.SocclkFrequency;
1883 gpu_metrics->average_uclk_frequency = metrics.Average.MemclkFrequency;
1884 gpu_metrics->average_fclk_frequency = metrics.Average.MemclkFrequency;
1885 gpu_metrics->average_vclk_frequency = metrics.Average.VclkFrequency;
1886 gpu_metrics->average_dclk_frequency = metrics.Average.DclkFrequency;
1887
1888 gpu_metrics->current_gfxclk = metrics.Current.GfxclkFrequency;
1889 gpu_metrics->current_socclk = metrics.Current.SocclkFrequency;
1890 gpu_metrics->current_uclk = metrics.Current.MemclkFrequency;
1891 gpu_metrics->current_fclk = metrics.Current.MemclkFrequency;
1892 gpu_metrics->current_vclk = metrics.Current.VclkFrequency;
1893 gpu_metrics->current_dclk = metrics.Current.DclkFrequency;
1894
1895 memcpy(&gpu_metrics->current_coreclk[0],
1896 &metrics.Current.CoreFrequency[0],
1897 sizeof(uint16_t) * 4);
1898 gpu_metrics->current_l3clk[0] = metrics.Current.L3Frequency[0];
1899
1900 gpu_metrics->throttle_status = metrics.Current.ThrottlerStatus;
1901 gpu_metrics->indep_throttle_status =
1902 smu_cmn_get_indep_throttler_status(metrics.Current.ThrottlerStatus,
1903 vangogh_throttler_map);
1904
1905 gpu_metrics->system_clock_counter = ktime_get_boottime_ns();
1906
1907 *table = (void *)gpu_metrics;
1908
1909 return sizeof(struct gpu_metrics_v2_4);
1910 }
1911
vangogh_get_gpu_metrics(struct smu_context * smu,void ** table)1912 static ssize_t vangogh_get_gpu_metrics(struct smu_context *smu,
1913 void **table)
1914 {
1915 struct smu_table_context *smu_table = &smu->smu_table;
1916 struct gpu_metrics_v2_2 *gpu_metrics =
1917 (struct gpu_metrics_v2_2 *)smu_table->gpu_metrics_table;
1918 SmuMetrics_t metrics;
1919 int ret = 0;
1920
1921 ret = smu_cmn_get_metrics_table(smu, &metrics, true);
1922 if (ret)
1923 return ret;
1924
1925 smu_cmn_init_soft_gpu_metrics(gpu_metrics, 2, 2);
1926
1927 gpu_metrics->temperature_gfx = metrics.Current.GfxTemperature;
1928 gpu_metrics->temperature_soc = metrics.Current.SocTemperature;
1929 memcpy(&gpu_metrics->temperature_core[0],
1930 &metrics.Current.CoreTemperature[0],
1931 sizeof(uint16_t) * 4);
1932 gpu_metrics->temperature_l3[0] = metrics.Current.L3Temperature[0];
1933
1934 gpu_metrics->average_gfx_activity = metrics.Current.GfxActivity;
1935 gpu_metrics->average_mm_activity = metrics.Current.UvdActivity;
1936
1937 gpu_metrics->average_socket_power = metrics.Current.CurrentSocketPower;
1938 gpu_metrics->average_cpu_power = metrics.Current.Power[0];
1939 gpu_metrics->average_soc_power = metrics.Current.Power[1];
1940 gpu_metrics->average_gfx_power = metrics.Current.Power[2];
1941 memcpy(&gpu_metrics->average_core_power[0],
1942 &metrics.Average.CorePower[0],
1943 sizeof(uint16_t) * 4);
1944
1945 gpu_metrics->average_gfxclk_frequency = metrics.Average.GfxclkFrequency;
1946 gpu_metrics->average_socclk_frequency = metrics.Average.SocclkFrequency;
1947 gpu_metrics->average_uclk_frequency = metrics.Average.MemclkFrequency;
1948 gpu_metrics->average_fclk_frequency = metrics.Average.MemclkFrequency;
1949 gpu_metrics->average_vclk_frequency = metrics.Average.VclkFrequency;
1950 gpu_metrics->average_dclk_frequency = metrics.Average.DclkFrequency;
1951
1952 gpu_metrics->current_gfxclk = metrics.Current.GfxclkFrequency;
1953 gpu_metrics->current_socclk = metrics.Current.SocclkFrequency;
1954 gpu_metrics->current_uclk = metrics.Current.MemclkFrequency;
1955 gpu_metrics->current_fclk = metrics.Current.MemclkFrequency;
1956 gpu_metrics->current_vclk = metrics.Current.VclkFrequency;
1957 gpu_metrics->current_dclk = metrics.Current.DclkFrequency;
1958
1959 memcpy(&gpu_metrics->current_coreclk[0],
1960 &metrics.Current.CoreFrequency[0],
1961 sizeof(uint16_t) * 4);
1962 gpu_metrics->current_l3clk[0] = metrics.Current.L3Frequency[0];
1963
1964 gpu_metrics->throttle_status = metrics.Current.ThrottlerStatus;
1965 gpu_metrics->indep_throttle_status =
1966 smu_cmn_get_indep_throttler_status(metrics.Current.ThrottlerStatus,
1967 vangogh_throttler_map);
1968
1969 gpu_metrics->system_clock_counter = ktime_get_boottime_ns();
1970
1971 *table = (void *)gpu_metrics;
1972
1973 return sizeof(struct gpu_metrics_v2_2);
1974 }
1975
vangogh_common_get_gpu_metrics(struct smu_context * smu,void ** table)1976 static ssize_t vangogh_common_get_gpu_metrics(struct smu_context *smu,
1977 void **table)
1978 {
1979 uint32_t smu_program;
1980 uint32_t fw_version;
1981 int ret = 0;
1982
1983 smu_program = (smu->smc_fw_version >> 24) & 0xff;
1984 fw_version = smu->smc_fw_version & 0xffffff;
1985 if (smu_program == 6) {
1986 if (fw_version >= 0x3F0800)
1987 ret = vangogh_get_gpu_metrics_v2_4(smu, table);
1988 else
1989 ret = vangogh_get_gpu_metrics_v2_3(smu, table);
1990
1991 } else {
1992 if (smu->smc_fw_version >= 0x043F3E00) {
1993 if (smu->smc_fw_if_version < 0x3)
1994 ret = vangogh_get_legacy_gpu_metrics_v2_3(smu, table);
1995 else
1996 ret = vangogh_get_gpu_metrics_v2_3(smu, table);
1997 } else {
1998 if (smu->smc_fw_if_version < 0x3)
1999 ret = vangogh_get_legacy_gpu_metrics(smu, table);
2000 else
2001 ret = vangogh_get_gpu_metrics(smu, table);
2002 }
2003 }
2004
2005 return ret;
2006 }
2007
vangogh_od_edit_dpm_table(struct smu_context * smu,enum PP_OD_DPM_TABLE_COMMAND type,long input[],uint32_t size)2008 static int vangogh_od_edit_dpm_table(struct smu_context *smu, enum PP_OD_DPM_TABLE_COMMAND type,
2009 long input[], uint32_t size)
2010 {
2011 int ret = 0;
2012 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
2013
2014 if (!(smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL)) {
2015 dev_warn(smu->adev->dev,
2016 "pp_od_clk_voltage is not accessible if power_dpm_force_performance_level is not in manual mode!\n");
2017 return -EINVAL;
2018 }
2019
2020 switch (type) {
2021 case PP_OD_EDIT_CCLK_VDDC_TABLE:
2022 if (size != 3) {
2023 dev_err(smu->adev->dev, "Input parameter number not correct (should be 4 for processor)\n");
2024 return -EINVAL;
2025 }
2026 if (input[0] >= smu->cpu_core_num) {
2027 dev_err(smu->adev->dev, "core index is overflow, should be less than %d\n",
2028 smu->cpu_core_num);
2029 }
2030 smu->cpu_core_id_select = input[0];
2031 if (input[1] == 0) {
2032 if (input[2] < smu->cpu_default_soft_min_freq) {
2033 dev_warn(smu->adev->dev, "Fine grain setting minimum cclk (%ld) MHz is less than the minimum allowed (%d) MHz\n",
2034 input[2], smu->cpu_default_soft_min_freq);
2035 return -EINVAL;
2036 }
2037 smu->cpu_actual_soft_min_freq = input[2];
2038 } else if (input[1] == 1) {
2039 if (input[2] > smu->cpu_default_soft_max_freq) {
2040 dev_warn(smu->adev->dev, "Fine grain setting maximum cclk (%ld) MHz is greater than the maximum allowed (%d) MHz\n",
2041 input[2], smu->cpu_default_soft_max_freq);
2042 return -EINVAL;
2043 }
2044 smu->cpu_actual_soft_max_freq = input[2];
2045 } else {
2046 return -EINVAL;
2047 }
2048 break;
2049 case PP_OD_EDIT_SCLK_VDDC_TABLE:
2050 if (size != 2) {
2051 dev_err(smu->adev->dev, "Input parameter number not correct\n");
2052 return -EINVAL;
2053 }
2054
2055 if (input[0] == 0) {
2056 if (input[1] < smu->gfx_default_hard_min_freq) {
2057 dev_warn(smu->adev->dev,
2058 "Fine grain setting minimum sclk (%ld) MHz is less than the minimum allowed (%d) MHz\n",
2059 input[1], smu->gfx_default_hard_min_freq);
2060 return -EINVAL;
2061 }
2062 smu->gfx_actual_hard_min_freq = input[1];
2063 } else if (input[0] == 1) {
2064 if (input[1] > smu->gfx_default_soft_max_freq) {
2065 dev_warn(smu->adev->dev,
2066 "Fine grain setting maximum sclk (%ld) MHz is greater than the maximum allowed (%d) MHz\n",
2067 input[1], smu->gfx_default_soft_max_freq);
2068 return -EINVAL;
2069 }
2070 smu->gfx_actual_soft_max_freq = input[1];
2071 } else {
2072 return -EINVAL;
2073 }
2074 break;
2075 case PP_OD_RESTORE_DEFAULT_TABLE:
2076 if (size != 0) {
2077 dev_err(smu->adev->dev, "Input parameter number not correct\n");
2078 return -EINVAL;
2079 } else {
2080 smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq;
2081 smu->gfx_actual_soft_max_freq = smu->gfx_default_soft_max_freq;
2082 smu->cpu_actual_soft_min_freq = smu->cpu_default_soft_min_freq;
2083 smu->cpu_actual_soft_max_freq = smu->cpu_default_soft_max_freq;
2084 }
2085 break;
2086 case PP_OD_COMMIT_DPM_TABLE:
2087 if (size != 0) {
2088 dev_err(smu->adev->dev, "Input parameter number not correct\n");
2089 return -EINVAL;
2090 } else {
2091 if (smu->gfx_actual_hard_min_freq > smu->gfx_actual_soft_max_freq) {
2092 dev_err(smu->adev->dev,
2093 "The setting minimum sclk (%d) MHz is greater than the setting maximum sclk (%d) MHz\n",
2094 smu->gfx_actual_hard_min_freq,
2095 smu->gfx_actual_soft_max_freq);
2096 return -EINVAL;
2097 }
2098
2099 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinGfxClk,
2100 smu->gfx_actual_hard_min_freq, NULL);
2101 if (ret) {
2102 dev_err(smu->adev->dev, "Set hard min sclk failed!");
2103 return ret;
2104 }
2105
2106 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxGfxClk,
2107 smu->gfx_actual_soft_max_freq, NULL);
2108 if (ret) {
2109 dev_err(smu->adev->dev, "Set soft max sclk failed!");
2110 return ret;
2111 }
2112
2113 if (smu->adev->pm.fw_version < 0x43f1b00) {
2114 dev_warn(smu->adev->dev, "CPUSoftMax/CPUSoftMin are not supported, please update SBIOS!\n");
2115 break;
2116 }
2117
2118 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMinCclk,
2119 ((smu->cpu_core_id_select << 20)
2120 | smu->cpu_actual_soft_min_freq),
2121 NULL);
2122 if (ret) {
2123 dev_err(smu->adev->dev, "Set hard min cclk failed!");
2124 return ret;
2125 }
2126
2127 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxCclk,
2128 ((smu->cpu_core_id_select << 20)
2129 | smu->cpu_actual_soft_max_freq),
2130 NULL);
2131 if (ret) {
2132 dev_err(smu->adev->dev, "Set soft max cclk failed!");
2133 return ret;
2134 }
2135 }
2136 break;
2137 default:
2138 return -ENOSYS;
2139 }
2140
2141 return ret;
2142 }
2143
vangogh_set_default_dpm_tables(struct smu_context * smu)2144 static int vangogh_set_default_dpm_tables(struct smu_context *smu)
2145 {
2146 struct smu_table_context *smu_table = &smu->smu_table;
2147
2148 return smu_cmn_update_table(smu, SMU_TABLE_DPMCLOCKS, 0, smu_table->clocks_table, false);
2149 }
2150
vangogh_set_fine_grain_gfx_freq_parameters(struct smu_context * smu)2151 static int vangogh_set_fine_grain_gfx_freq_parameters(struct smu_context *smu)
2152 {
2153 DpmClocks_t *clk_table = smu->smu_table.clocks_table;
2154
2155 smu->gfx_default_hard_min_freq = clk_table->MinGfxClk;
2156 smu->gfx_default_soft_max_freq = clk_table->MaxGfxClk;
2157 smu->gfx_actual_hard_min_freq = 0;
2158 smu->gfx_actual_soft_max_freq = 0;
2159
2160 smu->cpu_default_soft_min_freq = 1400;
2161 smu->cpu_default_soft_max_freq = 3500;
2162 smu->cpu_actual_soft_min_freq = 0;
2163 smu->cpu_actual_soft_max_freq = 0;
2164
2165 return 0;
2166 }
2167
vangogh_get_dpm_clock_table(struct smu_context * smu,struct dpm_clocks * clock_table)2168 static int vangogh_get_dpm_clock_table(struct smu_context *smu, struct dpm_clocks *clock_table)
2169 {
2170 DpmClocks_t *table = smu->smu_table.clocks_table;
2171 int i;
2172
2173 if (!clock_table || !table)
2174 return -EINVAL;
2175
2176 for (i = 0; i < NUM_SOCCLK_DPM_LEVELS; i++) {
2177 clock_table->SocClocks[i].Freq = table->SocClocks[i];
2178 clock_table->SocClocks[i].Vol = table->SocVoltage[i];
2179 }
2180
2181 for (i = 0; i < NUM_FCLK_DPM_LEVELS; i++) {
2182 clock_table->FClocks[i].Freq = table->DfPstateTable[i].fclk;
2183 clock_table->FClocks[i].Vol = table->DfPstateTable[i].voltage;
2184 }
2185
2186 for (i = 0; i < NUM_FCLK_DPM_LEVELS; i++) {
2187 clock_table->MemClocks[i].Freq = table->DfPstateTable[i].memclk;
2188 clock_table->MemClocks[i].Vol = table->DfPstateTable[i].voltage;
2189 }
2190
2191 return 0;
2192 }
2193
vangogh_notify_rlc_state(struct smu_context * smu,bool en)2194 static int vangogh_notify_rlc_state(struct smu_context *smu, bool en)
2195 {
2196 struct amdgpu_device *adev = smu->adev;
2197 int ret = 0;
2198
2199 if (adev->pm.fw_version >= 0x43f1700 && !en)
2200 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_RlcPowerNotify,
2201 RLC_STATUS_OFF, NULL);
2202
2203 return ret;
2204 }
2205
vangogh_post_smu_init(struct smu_context * smu)2206 static int vangogh_post_smu_init(struct smu_context *smu)
2207 {
2208 struct amdgpu_device *adev = smu->adev;
2209 uint32_t tmp;
2210 int ret = 0;
2211 uint8_t aon_bits = 0;
2212 /* Two CUs in one WGP */
2213 uint32_t req_active_wgps = adev->gfx.cu_info.number/2;
2214 uint32_t total_cu = adev->gfx.config.max_cu_per_sh *
2215 adev->gfx.config.max_sh_per_se * adev->gfx.config.max_shader_engines;
2216
2217 /* allow message will be sent after enable message on Vangogh*/
2218 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT) &&
2219 (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG)) {
2220 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_EnableGfxOff, NULL);
2221 if (ret) {
2222 dev_err(adev->dev, "Failed to Enable GfxOff!\n");
2223 return ret;
2224 }
2225 } else {
2226 adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
2227 dev_info(adev->dev, "If GFX DPM or power gate disabled, disable GFXOFF\n");
2228 }
2229
2230 /* if all CUs are active, no need to power off any WGPs */
2231 if (total_cu == adev->gfx.cu_info.number)
2232 return 0;
2233
2234 /*
2235 * Calculate the total bits number of always on WGPs for all SA/SEs in
2236 * RLC_PG_ALWAYS_ON_WGP_MASK.
2237 */
2238 tmp = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_ALWAYS_ON_WGP_MASK));
2239 tmp &= RLC_PG_ALWAYS_ON_WGP_MASK__AON_WGP_MASK_MASK;
2240
2241 aon_bits = hweight32(tmp) * adev->gfx.config.max_sh_per_se * adev->gfx.config.max_shader_engines;
2242
2243 /* Do not request any WGPs less than set in the AON_WGP_MASK */
2244 if (aon_bits > req_active_wgps) {
2245 dev_info(adev->dev, "Number of always on WGPs greater than active WGPs: WGP power save not requested.\n");
2246 return 0;
2247 } else {
2248 return smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_RequestActiveWgp, req_active_wgps, NULL);
2249 }
2250 }
2251
vangogh_mode_reset(struct smu_context * smu,int type)2252 static int vangogh_mode_reset(struct smu_context *smu, int type)
2253 {
2254 int ret = 0, index = 0;
2255
2256 index = smu_cmn_to_asic_specific_index(smu, CMN2ASIC_MAPPING_MSG,
2257 SMU_MSG_GfxDeviceDriverReset);
2258 if (index < 0)
2259 return index == -EACCES ? 0 : index;
2260
2261 mutex_lock(&smu->message_lock);
2262
2263 ret = smu_cmn_send_msg_without_waiting(smu, (uint16_t)index, type);
2264
2265 mutex_unlock(&smu->message_lock);
2266
2267 mdelay(10);
2268
2269 return ret;
2270 }
2271
vangogh_mode2_reset(struct smu_context * smu)2272 static int vangogh_mode2_reset(struct smu_context *smu)
2273 {
2274 return vangogh_mode_reset(smu, SMU_RESET_MODE_2);
2275 }
2276
2277 /**
2278 * vangogh_get_gfxoff_status - Get gfxoff status
2279 *
2280 * @smu: amdgpu_device pointer
2281 *
2282 * Get current gfxoff status
2283 *
2284 * Return:
2285 * * 0 - GFXOFF (default if enabled).
2286 * * 1 - Transition out of GFX State.
2287 * * 2 - Not in GFXOFF.
2288 * * 3 - Transition into GFXOFF.
2289 */
vangogh_get_gfxoff_status(struct smu_context * smu)2290 static u32 vangogh_get_gfxoff_status(struct smu_context *smu)
2291 {
2292 struct amdgpu_device *adev = smu->adev;
2293 u32 reg, gfxoff_status;
2294
2295 reg = RREG32_SOC15(SMUIO, 0, mmSMUIO_GFX_MISC_CNTL);
2296 gfxoff_status = (reg & SMUIO_GFX_MISC_CNTL__PWR_GFXOFF_STATUS_MASK)
2297 >> SMUIO_GFX_MISC_CNTL__PWR_GFXOFF_STATUS__SHIFT;
2298
2299 return gfxoff_status;
2300 }
2301
vangogh_get_power_limit(struct smu_context * smu,uint32_t * current_power_limit,uint32_t * default_power_limit,uint32_t * max_power_limit,uint32_t * min_power_limit)2302 static int vangogh_get_power_limit(struct smu_context *smu,
2303 uint32_t *current_power_limit,
2304 uint32_t *default_power_limit,
2305 uint32_t *max_power_limit,
2306 uint32_t *min_power_limit)
2307 {
2308 struct smu_11_5_power_context *power_context =
2309 smu->smu_power.power_context;
2310 uint32_t ppt_limit;
2311 int ret = 0;
2312
2313 if (smu->adev->pm.fw_version < 0x43f1e00)
2314 return ret;
2315
2316 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_GetSlowPPTLimit, &ppt_limit);
2317 if (ret) {
2318 dev_err(smu->adev->dev, "Get slow PPT limit failed!\n");
2319 return ret;
2320 }
2321 /* convert from milliwatt to watt */
2322 if (current_power_limit)
2323 *current_power_limit = ppt_limit / 1000;
2324 if (default_power_limit)
2325 *default_power_limit = ppt_limit / 1000;
2326 if (max_power_limit)
2327 *max_power_limit = 29;
2328 if (min_power_limit)
2329 *min_power_limit = 0;
2330
2331 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_GetFastPPTLimit, &ppt_limit);
2332 if (ret) {
2333 dev_err(smu->adev->dev, "Get fast PPT limit failed!\n");
2334 return ret;
2335 }
2336 /* convert from milliwatt to watt */
2337 power_context->current_fast_ppt_limit =
2338 power_context->default_fast_ppt_limit = ppt_limit / 1000;
2339 power_context->max_fast_ppt_limit = 30;
2340
2341 return ret;
2342 }
2343
vangogh_get_ppt_limit(struct smu_context * smu,uint32_t * ppt_limit,enum smu_ppt_limit_type type,enum smu_ppt_limit_level level)2344 static int vangogh_get_ppt_limit(struct smu_context *smu,
2345 uint32_t *ppt_limit,
2346 enum smu_ppt_limit_type type,
2347 enum smu_ppt_limit_level level)
2348 {
2349 struct smu_11_5_power_context *power_context =
2350 smu->smu_power.power_context;
2351
2352 if (!power_context)
2353 return -EOPNOTSUPP;
2354
2355 if (type == SMU_FAST_PPT_LIMIT) {
2356 switch (level) {
2357 case SMU_PPT_LIMIT_MAX:
2358 *ppt_limit = power_context->max_fast_ppt_limit;
2359 break;
2360 case SMU_PPT_LIMIT_CURRENT:
2361 *ppt_limit = power_context->current_fast_ppt_limit;
2362 break;
2363 case SMU_PPT_LIMIT_DEFAULT:
2364 *ppt_limit = power_context->default_fast_ppt_limit;
2365 break;
2366 default:
2367 break;
2368 }
2369 }
2370
2371 return 0;
2372 }
2373
vangogh_set_power_limit(struct smu_context * smu,enum smu_ppt_limit_type limit_type,uint32_t ppt_limit)2374 static int vangogh_set_power_limit(struct smu_context *smu,
2375 enum smu_ppt_limit_type limit_type,
2376 uint32_t ppt_limit)
2377 {
2378 struct smu_11_5_power_context *power_context =
2379 smu->smu_power.power_context;
2380 int ret = 0;
2381
2382 if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_PPT_BIT)) {
2383 dev_err(smu->adev->dev, "Setting new power limit is not supported!\n");
2384 return -EOPNOTSUPP;
2385 }
2386
2387 switch (limit_type) {
2388 case SMU_DEFAULT_PPT_LIMIT:
2389 ret = smu_cmn_send_smc_msg_with_param(smu,
2390 SMU_MSG_SetSlowPPTLimit,
2391 ppt_limit * 1000, /* convert from watt to milliwatt */
2392 NULL);
2393 if (ret)
2394 return ret;
2395
2396 smu->current_power_limit = ppt_limit;
2397 break;
2398 case SMU_FAST_PPT_LIMIT:
2399 ppt_limit &= ~(SMU_FAST_PPT_LIMIT << 24);
2400 if (ppt_limit > power_context->max_fast_ppt_limit) {
2401 dev_err(smu->adev->dev,
2402 "New power limit (%d) is over the max allowed %d\n",
2403 ppt_limit, power_context->max_fast_ppt_limit);
2404 return ret;
2405 }
2406
2407 ret = smu_cmn_send_smc_msg_with_param(smu,
2408 SMU_MSG_SetFastPPTLimit,
2409 ppt_limit * 1000, /* convert from watt to milliwatt */
2410 NULL);
2411 if (ret)
2412 return ret;
2413
2414 power_context->current_fast_ppt_limit = ppt_limit;
2415 break;
2416 default:
2417 return -EINVAL;
2418 }
2419
2420 return ret;
2421 }
2422
2423 /**
2424 * vangogh_set_gfxoff_residency
2425 *
2426 * @smu: amdgpu_device pointer
2427 * @start: start/stop residency log
2428 *
2429 * This function will be used to log gfxoff residency
2430 *
2431 *
2432 * Returns standard response codes.
2433 */
vangogh_set_gfxoff_residency(struct smu_context * smu,bool start)2434 static u32 vangogh_set_gfxoff_residency(struct smu_context *smu, bool start)
2435 {
2436 int ret = 0;
2437 u32 residency;
2438 struct amdgpu_device *adev = smu->adev;
2439
2440 if (!(adev->pm.pp_feature & PP_GFXOFF_MASK))
2441 return 0;
2442
2443 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_LogGfxOffResidency,
2444 start, &residency);
2445 if (ret)
2446 return ret;
2447
2448 if (!start)
2449 adev->gfx.gfx_off_residency = residency;
2450
2451 return ret;
2452 }
2453
2454 /**
2455 * vangogh_get_gfxoff_residency
2456 *
2457 * @smu: amdgpu_device pointer
2458 * @residency: placeholder for return value
2459 *
2460 * This function will be used to get gfxoff residency.
2461 *
2462 * Returns standard response codes.
2463 */
vangogh_get_gfxoff_residency(struct smu_context * smu,uint32_t * residency)2464 static u32 vangogh_get_gfxoff_residency(struct smu_context *smu, uint32_t *residency)
2465 {
2466 struct amdgpu_device *adev = smu->adev;
2467
2468 *residency = adev->gfx.gfx_off_residency;
2469
2470 return 0;
2471 }
2472
2473 /**
2474 * vangogh_get_gfxoff_entrycount - get gfxoff entry count
2475 *
2476 * @smu: amdgpu_device pointer
2477 * @entrycount: placeholder for return value
2478 *
2479 * This function will be used to get gfxoff entry count
2480 *
2481 * Returns standard response codes.
2482 */
vangogh_get_gfxoff_entrycount(struct smu_context * smu,uint64_t * entrycount)2483 static u32 vangogh_get_gfxoff_entrycount(struct smu_context *smu, uint64_t *entrycount)
2484 {
2485 int ret = 0, value = 0;
2486 struct amdgpu_device *adev = smu->adev;
2487
2488 if (!(adev->pm.pp_feature & PP_GFXOFF_MASK))
2489 return 0;
2490
2491 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_GetGfxOffEntryCount, &value);
2492 *entrycount = value + adev->gfx.gfx_off_entrycount;
2493
2494 return ret;
2495 }
2496
2497 static const struct pptable_funcs vangogh_ppt_funcs = {
2498
2499 .check_fw_status = smu_v11_0_check_fw_status,
2500 .check_fw_version = smu_v11_0_check_fw_version,
2501 .init_smc_tables = vangogh_init_smc_tables,
2502 .fini_smc_tables = smu_v11_0_fini_smc_tables,
2503 .init_power = smu_v11_0_init_power,
2504 .fini_power = smu_v11_0_fini_power,
2505 .register_irq_handler = smu_v11_0_register_irq_handler,
2506 .notify_memory_pool_location = smu_v11_0_notify_memory_pool_location,
2507 .send_smc_msg_with_param = smu_cmn_send_smc_msg_with_param,
2508 .send_smc_msg = smu_cmn_send_smc_msg,
2509 .dpm_set_vcn_enable = vangogh_dpm_set_vcn_enable,
2510 .dpm_set_jpeg_enable = vangogh_dpm_set_jpeg_enable,
2511 .is_dpm_running = vangogh_is_dpm_running,
2512 .read_sensor = vangogh_read_sensor,
2513 .get_apu_thermal_limit = vangogh_get_apu_thermal_limit,
2514 .set_apu_thermal_limit = vangogh_set_apu_thermal_limit,
2515 .get_enabled_mask = smu_cmn_get_enabled_mask,
2516 .get_pp_feature_mask = smu_cmn_get_pp_feature_mask,
2517 .set_watermarks_table = vangogh_set_watermarks_table,
2518 .set_driver_table_location = smu_v11_0_set_driver_table_location,
2519 .interrupt_work = smu_v11_0_interrupt_work,
2520 .get_gpu_metrics = vangogh_common_get_gpu_metrics,
2521 .od_edit_dpm_table = vangogh_od_edit_dpm_table,
2522 .print_clk_levels = vangogh_common_print_clk_levels,
2523 .set_default_dpm_table = vangogh_set_default_dpm_tables,
2524 .set_fine_grain_gfx_freq_parameters = vangogh_set_fine_grain_gfx_freq_parameters,
2525 .notify_rlc_state = vangogh_notify_rlc_state,
2526 .feature_is_enabled = smu_cmn_feature_is_enabled,
2527 .set_power_profile_mode = vangogh_set_power_profile_mode,
2528 .get_power_profile_mode = vangogh_get_power_profile_mode,
2529 .get_dpm_clock_table = vangogh_get_dpm_clock_table,
2530 .force_clk_levels = vangogh_force_clk_levels,
2531 .set_performance_level = vangogh_set_performance_level,
2532 .post_init = vangogh_post_smu_init,
2533 .mode2_reset = vangogh_mode2_reset,
2534 .gfx_off_control = smu_v11_0_gfx_off_control,
2535 .get_gfx_off_status = vangogh_get_gfxoff_status,
2536 .get_gfx_off_entrycount = vangogh_get_gfxoff_entrycount,
2537 .get_gfx_off_residency = vangogh_get_gfxoff_residency,
2538 .set_gfx_off_residency = vangogh_set_gfxoff_residency,
2539 .get_ppt_limit = vangogh_get_ppt_limit,
2540 .get_power_limit = vangogh_get_power_limit,
2541 .set_power_limit = vangogh_set_power_limit,
2542 .get_vbios_bootup_values = smu_v11_0_get_vbios_bootup_values,
2543 };
2544
vangogh_set_ppt_funcs(struct smu_context * smu)2545 void vangogh_set_ppt_funcs(struct smu_context *smu)
2546 {
2547 smu->ppt_funcs = &vangogh_ppt_funcs;
2548 smu->message_map = vangogh_message_map;
2549 smu->feature_map = vangogh_feature_mask_map;
2550 smu->table_map = vangogh_table_map;
2551 smu->workload_map = vangogh_workload_map;
2552 smu->is_apu = true;
2553 smu_v11_0_set_smu_mailbox_registers(smu);
2554 }
2555