1 /*
2 * Copyright 2021 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24 #define SWSMU_CODE_LAYER_L2
25
26 #include <linux/firmware.h>
27 #include "amdgpu.h"
28 #include "amdgpu_smu.h"
29 #include "atomfirmware.h"
30 #include "amdgpu_atomfirmware.h"
31 #include "amdgpu_atombios.h"
32 #include "smu_v13_0_6_pmfw.h"
33 #include "smu13_driver_if_v13_0_6.h"
34 #include "smu_v13_0_6_ppsmc.h"
35 #include "soc15_common.h"
36 #include "atom.h"
37 #include "power_state.h"
38 #include "smu_v13_0.h"
39 #include "smu_v13_0_6_ppt.h"
40 #include "nbio/nbio_7_4_offset.h"
41 #include "nbio/nbio_7_4_sh_mask.h"
42 #include "thm/thm_11_0_2_offset.h"
43 #include "thm/thm_11_0_2_sh_mask.h"
44 #include "amdgpu_xgmi.h"
45 #include <linux/pci.h>
46 #include "amdgpu_ras.h"
47 #include "amdgpu_mca.h"
48 #include "amdgpu_aca.h"
49 #include "smu_cmn.h"
50 #include "mp/mp_13_0_6_offset.h"
51 #include "mp/mp_13_0_6_sh_mask.h"
52 #include "umc_v12_0.h"
53
54 #undef MP1_Public
55 #undef smnMP1_FIRMWARE_FLAGS
56
57 /* TODO: Check final register offsets */
58 #define MP1_Public 0x03b00000
59 #define smnMP1_FIRMWARE_FLAGS 0x3010028
60 /*
61 * DO NOT use these for err/warn/info/debug messages.
62 * Use dev_err, dev_warn, dev_info and dev_dbg instead.
63 * They are more MGPU friendly.
64 */
65 #undef pr_err
66 #undef pr_warn
67 #undef pr_info
68 #undef pr_debug
69
70 MODULE_FIRMWARE("amdgpu/smu_13_0_6.bin");
71 MODULE_FIRMWARE("amdgpu/smu_13_0_14.bin");
72
73 #define to_amdgpu_device(x) (container_of(x, struct amdgpu_device, pm.smu_i2c))
74
75 #define SMU_13_0_6_FEA_MAP(smu_feature, smu_13_0_6_feature) \
76 [smu_feature] = { 1, (smu_13_0_6_feature) }
77
78 #define FEATURE_MASK(feature) (1ULL << feature)
79 #define SMC_DPM_FEATURE \
80 (FEATURE_MASK(FEATURE_DATA_CALCULATION) | \
81 FEATURE_MASK(FEATURE_DPM_GFXCLK) | FEATURE_MASK(FEATURE_DPM_UCLK) | \
82 FEATURE_MASK(FEATURE_DPM_SOCCLK) | FEATURE_MASK(FEATURE_DPM_FCLK) | \
83 FEATURE_MASK(FEATURE_DPM_LCLK) | FEATURE_MASK(FEATURE_DPM_XGMI) | \
84 FEATURE_MASK(FEATURE_DPM_VCN))
85
86 /* possible frequency drift (1Mhz) */
87 #define EPSILON 1
88
89 #define smnPCIE_ESM_CTRL 0x93D0
90 #define smnPCIE_LC_LINK_WIDTH_CNTL 0x1a340288
91 #define PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK 0x00000070L
92 #define PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT 0x4
93 #define MAX_LINK_WIDTH 6
94
95 #define smnPCIE_LC_SPEED_CNTL 0x1a340290
96 #define PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK 0xE0
97 #define PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT 0x5
98 #define LINK_SPEED_MAX 4
99
100 #define SMU_13_0_6_DSCLK_THRESHOLD 140
101
102 #define MCA_BANK_IPID(_ip, _hwid, _type) \
103 [AMDGPU_MCA_IP_##_ip] = { .hwid = _hwid, .mcatype = _type, }
104
105 struct mca_bank_ipid {
106 enum amdgpu_mca_ip ip;
107 uint16_t hwid;
108 uint16_t mcatype;
109 };
110
111 struct mca_ras_info {
112 enum amdgpu_ras_block blkid;
113 enum amdgpu_mca_ip ip;
114 int *err_code_array;
115 int err_code_count;
116 int (*get_err_count)(const struct mca_ras_info *mca_ras, struct amdgpu_device *adev,
117 enum amdgpu_mca_error_type type, struct mca_bank_entry *entry, uint32_t *count);
118 bool (*bank_is_valid)(const struct mca_ras_info *mca_ras, struct amdgpu_device *adev,
119 enum amdgpu_mca_error_type type, struct mca_bank_entry *entry);
120 };
121
122 #define P2S_TABLE_ID_A 0x50325341
123 #define P2S_TABLE_ID_X 0x50325358
124 #define P2S_TABLE_ID_3 0x50325303
125
126 // clang-format off
127 static const struct cmn2asic_msg_mapping smu_v13_0_6_message_map[SMU_MSG_MAX_COUNT] = {
128 MSG_MAP(TestMessage, PPSMC_MSG_TestMessage, 0),
129 MSG_MAP(GetSmuVersion, PPSMC_MSG_GetSmuVersion, 1),
130 MSG_MAP(GetDriverIfVersion, PPSMC_MSG_GetDriverIfVersion, 1),
131 MSG_MAP(EnableAllSmuFeatures, PPSMC_MSG_EnableAllSmuFeatures, 0),
132 MSG_MAP(DisableAllSmuFeatures, PPSMC_MSG_DisableAllSmuFeatures, 0),
133 MSG_MAP(RequestI2cTransaction, PPSMC_MSG_RequestI2cTransaction, 0),
134 MSG_MAP(GetMetricsTable, PPSMC_MSG_GetMetricsTable, 1),
135 MSG_MAP(GetMetricsVersion, PPSMC_MSG_GetMetricsVersion, 1),
136 MSG_MAP(GetEnabledSmuFeaturesHigh, PPSMC_MSG_GetEnabledSmuFeaturesHigh, 1),
137 MSG_MAP(GetEnabledSmuFeaturesLow, PPSMC_MSG_GetEnabledSmuFeaturesLow, 1),
138 MSG_MAP(SetDriverDramAddrHigh, PPSMC_MSG_SetDriverDramAddrHigh, 1),
139 MSG_MAP(SetDriverDramAddrLow, PPSMC_MSG_SetDriverDramAddrLow, 1),
140 MSG_MAP(SetToolsDramAddrHigh, PPSMC_MSG_SetToolsDramAddrHigh, 0),
141 MSG_MAP(SetToolsDramAddrLow, PPSMC_MSG_SetToolsDramAddrLow, 0),
142 MSG_MAP(SetSoftMinByFreq, PPSMC_MSG_SetSoftMinByFreq, 0),
143 MSG_MAP(SetSoftMaxByFreq, PPSMC_MSG_SetSoftMaxByFreq, 1),
144 MSG_MAP(GetMinDpmFreq, PPSMC_MSG_GetMinDpmFreq, 1),
145 MSG_MAP(GetMaxDpmFreq, PPSMC_MSG_GetMaxDpmFreq, 1),
146 MSG_MAP(GetDpmFreqByIndex, PPSMC_MSG_GetDpmFreqByIndex, 1),
147 MSG_MAP(SetPptLimit, PPSMC_MSG_SetPptLimit, 0),
148 MSG_MAP(GetPptLimit, PPSMC_MSG_GetPptLimit, 1),
149 MSG_MAP(GfxDeviceDriverReset, PPSMC_MSG_GfxDriverReset, SMU_MSG_RAS_PRI),
150 MSG_MAP(DramLogSetDramAddrHigh, PPSMC_MSG_DramLogSetDramAddrHigh, 0),
151 MSG_MAP(DramLogSetDramAddrLow, PPSMC_MSG_DramLogSetDramAddrLow, 0),
152 MSG_MAP(DramLogSetDramSize, PPSMC_MSG_DramLogSetDramSize, 0),
153 MSG_MAP(GetDebugData, PPSMC_MSG_GetDebugData, 0),
154 MSG_MAP(SetNumBadHbmPagesRetired, PPSMC_MSG_SetNumBadHbmPagesRetired, 0),
155 MSG_MAP(DFCstateControl, PPSMC_MSG_DFCstateControl, 0),
156 MSG_MAP(GetGmiPwrDnHyst, PPSMC_MSG_GetGmiPwrDnHyst, 0),
157 MSG_MAP(SetGmiPwrDnHyst, PPSMC_MSG_SetGmiPwrDnHyst, 0),
158 MSG_MAP(GmiPwrDnControl, PPSMC_MSG_GmiPwrDnControl, 0),
159 MSG_MAP(EnterGfxoff, PPSMC_MSG_EnterGfxoff, 0),
160 MSG_MAP(ExitGfxoff, PPSMC_MSG_ExitGfxoff, 0),
161 MSG_MAP(EnableDeterminism, PPSMC_MSG_EnableDeterminism, 0),
162 MSG_MAP(DisableDeterminism, PPSMC_MSG_DisableDeterminism, 0),
163 MSG_MAP(GfxDriverResetRecovery, PPSMC_MSG_GfxDriverResetRecovery, 0),
164 MSG_MAP(GetMinGfxclkFrequency, PPSMC_MSG_GetMinGfxDpmFreq, 1),
165 MSG_MAP(GetMaxGfxclkFrequency, PPSMC_MSG_GetMaxGfxDpmFreq, 1),
166 MSG_MAP(SetSoftMinGfxclk, PPSMC_MSG_SetSoftMinGfxClk, 1),
167 MSG_MAP(SetSoftMaxGfxClk, PPSMC_MSG_SetSoftMaxGfxClk, 1),
168 MSG_MAP(PrepareMp1ForUnload, PPSMC_MSG_PrepareForDriverUnload, 0),
169 MSG_MAP(GetCTFLimit, PPSMC_MSG_GetCTFLimit, 0),
170 MSG_MAP(GetThermalLimit, PPSMC_MSG_ReadThrottlerLimit, 0),
171 MSG_MAP(ClearMcaOnRead, PPSMC_MSG_ClearMcaOnRead, 0),
172 MSG_MAP(QueryValidMcaCount, PPSMC_MSG_QueryValidMcaCount, SMU_MSG_RAS_PRI),
173 MSG_MAP(QueryValidMcaCeCount, PPSMC_MSG_QueryValidMcaCeCount, SMU_MSG_RAS_PRI),
174 MSG_MAP(McaBankDumpDW, PPSMC_MSG_McaBankDumpDW, SMU_MSG_RAS_PRI),
175 MSG_MAP(McaBankCeDumpDW, PPSMC_MSG_McaBankCeDumpDW, SMU_MSG_RAS_PRI),
176 MSG_MAP(SelectPLPDMode, PPSMC_MSG_SelectPLPDMode, 0),
177 MSG_MAP(RmaDueToBadPageThreshold, PPSMC_MSG_RmaDueToBadPageThreshold, 0),
178 MSG_MAP(SelectPstatePolicy, PPSMC_MSG_SelectPstatePolicy, 0),
179 };
180
181 // clang-format on
182 static const struct cmn2asic_mapping smu_v13_0_6_clk_map[SMU_CLK_COUNT] = {
183 CLK_MAP(SOCCLK, PPCLK_SOCCLK),
184 CLK_MAP(FCLK, PPCLK_FCLK),
185 CLK_MAP(UCLK, PPCLK_UCLK),
186 CLK_MAP(MCLK, PPCLK_UCLK),
187 CLK_MAP(DCLK, PPCLK_DCLK),
188 CLK_MAP(VCLK, PPCLK_VCLK),
189 CLK_MAP(LCLK, PPCLK_LCLK),
190 };
191
192 static const struct cmn2asic_mapping smu_v13_0_6_feature_mask_map[SMU_FEATURE_COUNT] = {
193 SMU_13_0_6_FEA_MAP(SMU_FEATURE_DATA_CALCULATIONS_BIT, FEATURE_DATA_CALCULATION),
194 SMU_13_0_6_FEA_MAP(SMU_FEATURE_DPM_GFXCLK_BIT, FEATURE_DPM_GFXCLK),
195 SMU_13_0_6_FEA_MAP(SMU_FEATURE_DPM_UCLK_BIT, FEATURE_DPM_UCLK),
196 SMU_13_0_6_FEA_MAP(SMU_FEATURE_DPM_SOCCLK_BIT, FEATURE_DPM_SOCCLK),
197 SMU_13_0_6_FEA_MAP(SMU_FEATURE_DPM_FCLK_BIT, FEATURE_DPM_FCLK),
198 SMU_13_0_6_FEA_MAP(SMU_FEATURE_DPM_LCLK_BIT, FEATURE_DPM_LCLK),
199 SMU_13_0_6_FEA_MAP(SMU_FEATURE_DPM_VCLK_BIT, FEATURE_DPM_VCN),
200 SMU_13_0_6_FEA_MAP(SMU_FEATURE_DPM_DCLK_BIT, FEATURE_DPM_VCN),
201 SMU_13_0_6_FEA_MAP(SMU_FEATURE_DPM_XGMI_BIT, FEATURE_DPM_XGMI),
202 SMU_13_0_6_FEA_MAP(SMU_FEATURE_DS_GFXCLK_BIT, FEATURE_DS_GFXCLK),
203 SMU_13_0_6_FEA_MAP(SMU_FEATURE_DS_SOCCLK_BIT, FEATURE_DS_SOCCLK),
204 SMU_13_0_6_FEA_MAP(SMU_FEATURE_DS_LCLK_BIT, FEATURE_DS_LCLK),
205 SMU_13_0_6_FEA_MAP(SMU_FEATURE_DS_FCLK_BIT, FEATURE_DS_FCLK),
206 SMU_13_0_6_FEA_MAP(SMU_FEATURE_VCN_DPM_BIT, FEATURE_DPM_VCN),
207 SMU_13_0_6_FEA_MAP(SMU_FEATURE_PPT_BIT, FEATURE_PPT),
208 SMU_13_0_6_FEA_MAP(SMU_FEATURE_TDC_BIT, FEATURE_TDC),
209 SMU_13_0_6_FEA_MAP(SMU_FEATURE_APCC_DFLL_BIT, FEATURE_APCC_DFLL),
210 SMU_13_0_6_FEA_MAP(SMU_FEATURE_MP1_CG_BIT, FEATURE_SMU_CG),
211 SMU_13_0_6_FEA_MAP(SMU_FEATURE_GFXOFF_BIT, FEATURE_GFXOFF),
212 SMU_13_0_6_FEA_MAP(SMU_FEATURE_FW_CTF_BIT, FEATURE_FW_CTF),
213 SMU_13_0_6_FEA_MAP(SMU_FEATURE_THERMAL_BIT, FEATURE_THERMAL),
214 SMU_13_0_6_FEA_MAP(SMU_FEATURE_XGMI_PER_LINK_PWR_DWN_BIT, FEATURE_XGMI_PER_LINK_PWR_DOWN),
215 SMU_13_0_6_FEA_MAP(SMU_FEATURE_DF_CSTATE_BIT, FEATURE_DF_CSTATE),
216 };
217
218 #define TABLE_PMSTATUSLOG 0
219 #define TABLE_SMU_METRICS 1
220 #define TABLE_I2C_COMMANDS 2
221 #define TABLE_COUNT 3
222
223 static const struct cmn2asic_mapping smu_v13_0_6_table_map[SMU_TABLE_COUNT] = {
224 TAB_MAP(PMSTATUSLOG),
225 TAB_MAP(SMU_METRICS),
226 TAB_MAP(I2C_COMMANDS),
227 };
228
229 static const uint8_t smu_v13_0_6_throttler_map[] = {
230 [THROTTLER_PPT_BIT] = (SMU_THROTTLER_PPT0_BIT),
231 [THROTTLER_THERMAL_SOCKET_BIT] = (SMU_THROTTLER_TEMP_GPU_BIT),
232 [THROTTLER_THERMAL_HBM_BIT] = (SMU_THROTTLER_TEMP_MEM_BIT),
233 [THROTTLER_THERMAL_VR_BIT] = (SMU_THROTTLER_TEMP_VR_GFX_BIT),
234 [THROTTLER_PROCHOT_BIT] = (SMU_THROTTLER_PROCHOT_GFX_BIT),
235 };
236
237 struct PPTable_t {
238 uint32_t MaxSocketPowerLimit;
239 uint32_t MaxGfxclkFrequency;
240 uint32_t MinGfxclkFrequency;
241 uint32_t FclkFrequencyTable[4];
242 uint32_t UclkFrequencyTable[4];
243 uint32_t SocclkFrequencyTable[4];
244 uint32_t VclkFrequencyTable[4];
245 uint32_t DclkFrequencyTable[4];
246 uint32_t LclkFrequencyTable[4];
247 uint32_t MaxLclkDpmRange;
248 uint32_t MinLclkDpmRange;
249 uint64_t PublicSerialNumber_AID;
250 bool Init;
251 };
252
253 #define SMUQ10_TO_UINT(x) ((x) >> 10)
254 #define SMUQ10_FRAC(x) ((x) & 0x3ff)
255 #define SMUQ10_ROUND(x) ((SMUQ10_TO_UINT(x)) + ((SMUQ10_FRAC(x)) >= 0x200))
256 #define GET_METRIC_FIELD(field) ((adev->flags & AMD_IS_APU) ?\
257 (metrics_a->field) : (metrics_x->field))
258
259 struct smu_v13_0_6_dpm_map {
260 enum smu_clk_type clk_type;
261 uint32_t feature_num;
262 struct smu_13_0_dpm_table *dpm_table;
263 uint32_t *freq_table;
264 };
265
smu_v13_0_6_init_microcode(struct smu_context * smu)266 static int smu_v13_0_6_init_microcode(struct smu_context *smu)
267 {
268 const struct smc_firmware_header_v2_1 *v2_1;
269 const struct common_firmware_header *hdr;
270 struct amdgpu_firmware_info *ucode = NULL;
271 struct smc_soft_pptable_entry *entries;
272 struct amdgpu_device *adev = smu->adev;
273 uint32_t p2s_table_id = P2S_TABLE_ID_A;
274 int ret = 0, i, p2stable_count;
275 int var = (adev->pdev->device & 0xF);
276 char ucode_prefix[15];
277
278 /* No need to load P2S tables in IOV mode or for smu v13.0.12 */
279 if (amdgpu_sriov_vf(adev) ||
280 (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 12)))
281 return 0;
282
283 if (!(adev->flags & AMD_IS_APU)) {
284 p2s_table_id = P2S_TABLE_ID_X;
285 if (var == 0x5)
286 p2s_table_id = P2S_TABLE_ID_3;
287 }
288
289 amdgpu_ucode_ip_version_decode(adev, MP1_HWIP, ucode_prefix,
290 sizeof(ucode_prefix));
291 ret = amdgpu_ucode_request(adev, &adev->pm.fw, "amdgpu/%s.bin", ucode_prefix);
292 if (ret)
293 goto out;
294
295 hdr = (const struct common_firmware_header *)adev->pm.fw->data;
296 amdgpu_ucode_print_smc_hdr(hdr);
297
298 /* SMU v13.0.6 binary file doesn't carry pptables, instead the entries
299 * are used to carry p2s tables.
300 */
301 v2_1 = (const struct smc_firmware_header_v2_1 *)adev->pm.fw->data;
302 entries = (struct smc_soft_pptable_entry
303 *)((uint8_t *)v2_1 +
304 le32_to_cpu(v2_1->pptable_entry_offset));
305 p2stable_count = le32_to_cpu(v2_1->pptable_count);
306 for (i = 0; i < p2stable_count; i++) {
307 if (le32_to_cpu(entries[i].id) == p2s_table_id) {
308 smu->pptable_firmware.data =
309 ((uint8_t *)v2_1 +
310 le32_to_cpu(entries[i].ppt_offset_bytes));
311 smu->pptable_firmware.size =
312 le32_to_cpu(entries[i].ppt_size_bytes);
313 break;
314 }
315 }
316
317 if (smu->pptable_firmware.data && smu->pptable_firmware.size) {
318 ucode = &adev->firmware.ucode[AMDGPU_UCODE_ID_P2S_TABLE];
319 ucode->ucode_id = AMDGPU_UCODE_ID_P2S_TABLE;
320 ucode->fw = &smu->pptable_firmware;
321 adev->firmware.fw_size += ALIGN(ucode->fw->size, PAGE_SIZE);
322 }
323
324 return 0;
325 out:
326 amdgpu_ucode_release(&adev->pm.fw);
327
328 return ret;
329 }
330
smu_v13_0_6_tables_init(struct smu_context * smu)331 static int smu_v13_0_6_tables_init(struct smu_context *smu)
332 {
333 struct smu_table_context *smu_table = &smu->smu_table;
334 struct smu_table *tables = smu_table->tables;
335 struct amdgpu_device *adev = smu->adev;
336
337 if (!(adev->flags & AMD_IS_APU))
338 SMU_TABLE_INIT(tables, SMU_TABLE_PMSTATUSLOG, SMU13_TOOL_SIZE,
339 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
340
341 SMU_TABLE_INIT(tables, SMU_TABLE_SMU_METRICS,
342 max(sizeof(MetricsTableX_t), sizeof(MetricsTableA_t)),
343 PAGE_SIZE,
344 AMDGPU_GEM_DOMAIN_VRAM | AMDGPU_GEM_DOMAIN_GTT);
345
346 SMU_TABLE_INIT(tables, SMU_TABLE_I2C_COMMANDS, sizeof(SwI2cRequest_t),
347 PAGE_SIZE,
348 AMDGPU_GEM_DOMAIN_VRAM | AMDGPU_GEM_DOMAIN_GTT);
349
350 smu_table->metrics_table = kzalloc(max(sizeof(MetricsTableX_t),
351 sizeof(MetricsTableA_t)), GFP_KERNEL);
352 if (!smu_table->metrics_table)
353 return -ENOMEM;
354 smu_table->metrics_time = 0;
355
356 smu_table->gpu_metrics_table_size = sizeof(struct gpu_metrics_v1_5);
357 smu_table->gpu_metrics_table =
358 kzalloc(smu_table->gpu_metrics_table_size, GFP_KERNEL);
359 if (!smu_table->gpu_metrics_table) {
360 kfree(smu_table->metrics_table);
361 return -ENOMEM;
362 }
363
364 smu_table->driver_pptable =
365 kzalloc(sizeof(struct PPTable_t), GFP_KERNEL);
366 if (!smu_table->driver_pptable) {
367 kfree(smu_table->metrics_table);
368 kfree(smu_table->gpu_metrics_table);
369 return -ENOMEM;
370 }
371
372 return 0;
373 }
374
smu_v13_0_6_select_policy_soc_pstate(struct smu_context * smu,int policy)375 static int smu_v13_0_6_select_policy_soc_pstate(struct smu_context *smu,
376 int policy)
377 {
378 struct amdgpu_device *adev = smu->adev;
379 int ret, param;
380
381 switch (policy) {
382 case SOC_PSTATE_DEFAULT:
383 param = 0;
384 break;
385 case SOC_PSTATE_0:
386 param = 1;
387 break;
388 case SOC_PSTATE_1:
389 param = 2;
390 break;
391 case SOC_PSTATE_2:
392 param = 3;
393 break;
394 default:
395 return -EINVAL;
396 }
397
398 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SelectPstatePolicy,
399 param, NULL);
400
401 if (ret)
402 dev_err(adev->dev, "select soc pstate policy %d failed",
403 policy);
404
405 return ret;
406 }
407
smu_v13_0_6_select_plpd_policy(struct smu_context * smu,int level)408 static int smu_v13_0_6_select_plpd_policy(struct smu_context *smu, int level)
409 {
410 struct amdgpu_device *adev = smu->adev;
411 int ret, param;
412
413 switch (level) {
414 case XGMI_PLPD_DEFAULT:
415 param = PPSMC_PLPD_MODE_DEFAULT;
416 break;
417 case XGMI_PLPD_OPTIMIZED:
418 param = PPSMC_PLPD_MODE_OPTIMIZED;
419 break;
420 case XGMI_PLPD_DISALLOW:
421 param = 0;
422 break;
423 default:
424 return -EINVAL;
425 }
426
427 if (level == XGMI_PLPD_DISALLOW)
428 ret = smu_cmn_send_smc_msg_with_param(
429 smu, SMU_MSG_GmiPwrDnControl, param, NULL);
430 else
431 /* change xgmi per-link power down policy */
432 ret = smu_cmn_send_smc_msg_with_param(
433 smu, SMU_MSG_SelectPLPDMode, param, NULL);
434
435 if (ret)
436 dev_err(adev->dev,
437 "select xgmi per-link power down policy %d failed\n",
438 level);
439
440 return ret;
441 }
442
smu_v13_0_6_allocate_dpm_context(struct smu_context * smu)443 static int smu_v13_0_6_allocate_dpm_context(struct smu_context *smu)
444 {
445 struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
446 struct smu_dpm_policy *policy;
447
448 smu_dpm->dpm_context =
449 kzalloc(sizeof(struct smu_13_0_dpm_context), GFP_KERNEL);
450 if (!smu_dpm->dpm_context)
451 return -ENOMEM;
452 smu_dpm->dpm_context_size = sizeof(struct smu_13_0_dpm_context);
453
454 smu_dpm->dpm_policies =
455 kzalloc(sizeof(struct smu_dpm_policy_ctxt), GFP_KERNEL);
456 if (!smu_dpm->dpm_policies) {
457 kfree(smu_dpm->dpm_context);
458 return -ENOMEM;
459 }
460
461 if (!(smu->adev->flags & AMD_IS_APU)) {
462 policy = &(smu_dpm->dpm_policies->policies[0]);
463
464 policy->policy_type = PP_PM_POLICY_SOC_PSTATE;
465 policy->level_mask = BIT(SOC_PSTATE_DEFAULT) |
466 BIT(SOC_PSTATE_0) | BIT(SOC_PSTATE_1) |
467 BIT(SOC_PSTATE_2);
468 policy->current_level = SOC_PSTATE_DEFAULT;
469 policy->set_policy = smu_v13_0_6_select_policy_soc_pstate;
470 smu_cmn_generic_soc_policy_desc(policy);
471 smu_dpm->dpm_policies->policy_mask |=
472 BIT(PP_PM_POLICY_SOC_PSTATE);
473 }
474 policy = &(smu_dpm->dpm_policies->policies[1]);
475
476 policy->policy_type = PP_PM_POLICY_XGMI_PLPD;
477 policy->level_mask = BIT(XGMI_PLPD_DISALLOW) | BIT(XGMI_PLPD_DEFAULT) |
478 BIT(XGMI_PLPD_OPTIMIZED);
479 policy->current_level = XGMI_PLPD_DEFAULT;
480 policy->set_policy = smu_v13_0_6_select_plpd_policy;
481 smu_cmn_generic_plpd_policy_desc(policy);
482 smu_dpm->dpm_policies->policy_mask |= BIT(PP_PM_POLICY_XGMI_PLPD);
483
484 return 0;
485 }
486
smu_v13_0_6_init_smc_tables(struct smu_context * smu)487 static int smu_v13_0_6_init_smc_tables(struct smu_context *smu)
488 {
489 int ret = 0;
490
491 ret = smu_v13_0_6_tables_init(smu);
492 if (ret)
493 return ret;
494
495 ret = smu_v13_0_6_allocate_dpm_context(smu);
496
497 return ret;
498 }
499
smu_v13_0_6_get_allowed_feature_mask(struct smu_context * smu,uint32_t * feature_mask,uint32_t num)500 static int smu_v13_0_6_get_allowed_feature_mask(struct smu_context *smu,
501 uint32_t *feature_mask,
502 uint32_t num)
503 {
504 if (num > 2)
505 return -EINVAL;
506
507 /* pptable will handle the features to enable */
508 memset(feature_mask, 0xFF, sizeof(uint32_t) * num);
509
510 return 0;
511 }
512
smu_v13_0_6_get_metrics_table(struct smu_context * smu,void * metrics_table,bool bypass_cache)513 static int smu_v13_0_6_get_metrics_table(struct smu_context *smu,
514 void *metrics_table, bool bypass_cache)
515 {
516 struct smu_table_context *smu_table = &smu->smu_table;
517 uint32_t table_size = smu_table->tables[SMU_TABLE_SMU_METRICS].size;
518 struct smu_table *table = &smu_table->driver_table;
519 int ret;
520
521 if (bypass_cache || !smu_table->metrics_time ||
522 time_after(jiffies,
523 smu_table->metrics_time + msecs_to_jiffies(1))) {
524 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_GetMetricsTable, NULL);
525 if (ret) {
526 dev_info(smu->adev->dev,
527 "Failed to export SMU metrics table!\n");
528 return ret;
529 }
530
531 amdgpu_asic_invalidate_hdp(smu->adev, NULL);
532 memcpy(smu_table->metrics_table, table->cpu_addr, table_size);
533
534 smu_table->metrics_time = jiffies;
535 }
536
537 if (metrics_table)
538 memcpy(metrics_table, smu_table->metrics_table, table_size);
539
540 return 0;
541 }
542
smu_v13_0_6_get_pm_metrics(struct smu_context * smu,void * metrics,size_t max_size)543 static ssize_t smu_v13_0_6_get_pm_metrics(struct smu_context *smu,
544 void *metrics, size_t max_size)
545 {
546 struct smu_table_context *smu_tbl_ctxt = &smu->smu_table;
547 uint32_t table_version = smu_tbl_ctxt->tables[SMU_TABLE_SMU_METRICS].version;
548 uint32_t table_size = smu_tbl_ctxt->tables[SMU_TABLE_SMU_METRICS].size;
549 struct amdgpu_pm_metrics *pm_metrics = metrics;
550 uint32_t pmfw_version;
551 int ret;
552
553 if (!pm_metrics || !max_size)
554 return -EINVAL;
555
556 if (max_size < (table_size + sizeof(pm_metrics->common_header)))
557 return -EOVERFLOW;
558
559 /* Don't use cached metrics data */
560 ret = smu_v13_0_6_get_metrics_table(smu, pm_metrics->data, true);
561 if (ret)
562 return ret;
563
564 smu_cmn_get_smc_version(smu, NULL, &pmfw_version);
565
566 memset(&pm_metrics->common_header, 0,
567 sizeof(pm_metrics->common_header));
568 if (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 6))
569 pm_metrics->common_header.mp1_ip_discovery_version = IP_VERSION(13, 0, 6);
570 if (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 14))
571 pm_metrics->common_header.mp1_ip_discovery_version = IP_VERSION(13, 0, 14);
572 pm_metrics->common_header.pmfw_version = pmfw_version;
573 pm_metrics->common_header.pmmetrics_version = table_version;
574 pm_metrics->common_header.structure_size =
575 sizeof(pm_metrics->common_header) + table_size;
576
577 return pm_metrics->common_header.structure_size;
578 }
579
smu_v13_0_6_setup_driver_pptable(struct smu_context * smu)580 static int smu_v13_0_6_setup_driver_pptable(struct smu_context *smu)
581 {
582 struct smu_table_context *smu_table = &smu->smu_table;
583 MetricsTableX_t *metrics_x = (MetricsTableX_t *)smu_table->metrics_table;
584 MetricsTableA_t *metrics_a = (MetricsTableA_t *)smu_table->metrics_table;
585 struct PPTable_t *pptable =
586 (struct PPTable_t *)smu_table->driver_pptable;
587 struct amdgpu_device *adev = smu->adev;
588 int ret, i, retry = 100;
589 uint32_t table_version;
590
591 /* Store one-time values in driver PPTable */
592 if (!pptable->Init) {
593 while (--retry) {
594 ret = smu_v13_0_6_get_metrics_table(smu, NULL, true);
595 if (ret)
596 return ret;
597
598 /* Ensure that metrics have been updated */
599 if (GET_METRIC_FIELD(AccumulationCounter))
600 break;
601
602 usleep_range(1000, 1100);
603 }
604
605 if (!retry)
606 return -ETIME;
607
608 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_GetMetricsVersion,
609 &table_version);
610 if (ret)
611 return ret;
612 smu_table->tables[SMU_TABLE_SMU_METRICS].version =
613 table_version;
614
615 pptable->MaxSocketPowerLimit =
616 SMUQ10_ROUND(GET_METRIC_FIELD(MaxSocketPowerLimit));
617 pptable->MaxGfxclkFrequency =
618 SMUQ10_ROUND(GET_METRIC_FIELD(MaxGfxclkFrequency));
619 pptable->MinGfxclkFrequency =
620 SMUQ10_ROUND(GET_METRIC_FIELD(MinGfxclkFrequency));
621
622 for (i = 0; i < 4; ++i) {
623 pptable->FclkFrequencyTable[i] =
624 SMUQ10_ROUND(GET_METRIC_FIELD(FclkFrequencyTable)[i]);
625 pptable->UclkFrequencyTable[i] =
626 SMUQ10_ROUND(GET_METRIC_FIELD(UclkFrequencyTable)[i]);
627 pptable->SocclkFrequencyTable[i] = SMUQ10_ROUND(
628 GET_METRIC_FIELD(SocclkFrequencyTable)[i]);
629 pptable->VclkFrequencyTable[i] =
630 SMUQ10_ROUND(GET_METRIC_FIELD(VclkFrequencyTable)[i]);
631 pptable->DclkFrequencyTable[i] =
632 SMUQ10_ROUND(GET_METRIC_FIELD(DclkFrequencyTable)[i]);
633 pptable->LclkFrequencyTable[i] =
634 SMUQ10_ROUND(GET_METRIC_FIELD(LclkFrequencyTable)[i]);
635 }
636
637 /* use AID0 serial number by default */
638 pptable->PublicSerialNumber_AID = GET_METRIC_FIELD(PublicSerialNumber_AID)[0];
639
640 pptable->Init = true;
641 }
642
643 return 0;
644 }
645
smu_v13_0_6_get_dpm_ultimate_freq(struct smu_context * smu,enum smu_clk_type clk_type,uint32_t * min,uint32_t * max)646 static int smu_v13_0_6_get_dpm_ultimate_freq(struct smu_context *smu,
647 enum smu_clk_type clk_type,
648 uint32_t *min, uint32_t *max)
649 {
650 struct smu_table_context *smu_table = &smu->smu_table;
651 struct PPTable_t *pptable =
652 (struct PPTable_t *)smu_table->driver_pptable;
653 uint32_t clock_limit = 0, param;
654 int ret = 0, clk_id = 0;
655
656 if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type)) {
657 switch (clk_type) {
658 case SMU_MCLK:
659 case SMU_UCLK:
660 if (pptable->Init)
661 clock_limit = pptable->UclkFrequencyTable[0];
662 break;
663 case SMU_GFXCLK:
664 case SMU_SCLK:
665 if (pptable->Init)
666 clock_limit = pptable->MinGfxclkFrequency;
667 break;
668 case SMU_SOCCLK:
669 if (pptable->Init)
670 clock_limit = pptable->SocclkFrequencyTable[0];
671 break;
672 case SMU_FCLK:
673 if (pptable->Init)
674 clock_limit = pptable->FclkFrequencyTable[0];
675 break;
676 case SMU_VCLK:
677 if (pptable->Init)
678 clock_limit = pptable->VclkFrequencyTable[0];
679 break;
680 case SMU_DCLK:
681 if (pptable->Init)
682 clock_limit = pptable->DclkFrequencyTable[0];
683 break;
684 default:
685 break;
686 }
687
688 if (min)
689 *min = clock_limit;
690
691 if (max)
692 *max = clock_limit;
693
694 return 0;
695 }
696
697 if (!(clk_type == SMU_GFXCLK || clk_type == SMU_SCLK)) {
698 clk_id = smu_cmn_to_asic_specific_index(
699 smu, CMN2ASIC_MAPPING_CLK, clk_type);
700 if (clk_id < 0) {
701 ret = -EINVAL;
702 goto failed;
703 }
704 param = (clk_id & 0xffff) << 16;
705 }
706
707 if (max) {
708 if (clk_type == SMU_GFXCLK || clk_type == SMU_SCLK)
709 ret = smu_cmn_send_smc_msg(
710 smu, SMU_MSG_GetMaxGfxclkFrequency, max);
711 else
712 ret = smu_cmn_send_smc_msg_with_param(
713 smu, SMU_MSG_GetMaxDpmFreq, param, max);
714 if (ret)
715 goto failed;
716 }
717
718 if (min) {
719 if (clk_type == SMU_GFXCLK || clk_type == SMU_SCLK)
720 ret = smu_cmn_send_smc_msg(
721 smu, SMU_MSG_GetMinGfxclkFrequency, min);
722 else
723 ret = smu_cmn_send_smc_msg_with_param(
724 smu, SMU_MSG_GetMinDpmFreq, param, min);
725 }
726
727 failed:
728 return ret;
729 }
730
smu_v13_0_6_get_dpm_level_count(struct smu_context * smu,enum smu_clk_type clk_type,uint32_t * levels)731 static int smu_v13_0_6_get_dpm_level_count(struct smu_context *smu,
732 enum smu_clk_type clk_type,
733 uint32_t *levels)
734 {
735 int ret;
736
737 ret = smu_v13_0_get_dpm_freq_by_index(smu, clk_type, 0xff, levels);
738 if (!ret)
739 ++(*levels);
740
741 return ret;
742 }
743
smu_v13_0_6_pm_policy_init(struct smu_context * smu)744 static void smu_v13_0_6_pm_policy_init(struct smu_context *smu)
745 {
746 struct smu_dpm_policy *policy;
747
748 policy = smu_get_pm_policy(smu, PP_PM_POLICY_SOC_PSTATE);
749 if (policy)
750 policy->current_level = SOC_PSTATE_DEFAULT;
751 }
752
smu_v13_0_6_set_default_dpm_table(struct smu_context * smu)753 static int smu_v13_0_6_set_default_dpm_table(struct smu_context *smu)
754 {
755 struct smu_13_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;
756 struct smu_table_context *smu_table = &smu->smu_table;
757 struct smu_13_0_dpm_table *dpm_table = NULL;
758 struct PPTable_t *pptable =
759 (struct PPTable_t *)smu_table->driver_pptable;
760 uint32_t gfxclkmin, gfxclkmax, levels;
761 int ret = 0, i, j;
762 struct smu_v13_0_6_dpm_map dpm_map[] = {
763 { SMU_SOCCLK, SMU_FEATURE_DPM_SOCCLK_BIT,
764 &dpm_context->dpm_tables.soc_table,
765 pptable->SocclkFrequencyTable },
766 { SMU_UCLK, SMU_FEATURE_DPM_UCLK_BIT,
767 &dpm_context->dpm_tables.uclk_table,
768 pptable->UclkFrequencyTable },
769 { SMU_FCLK, SMU_FEATURE_DPM_FCLK_BIT,
770 &dpm_context->dpm_tables.fclk_table,
771 pptable->FclkFrequencyTable },
772 { SMU_VCLK, SMU_FEATURE_DPM_VCLK_BIT,
773 &dpm_context->dpm_tables.vclk_table,
774 pptable->VclkFrequencyTable },
775 { SMU_DCLK, SMU_FEATURE_DPM_DCLK_BIT,
776 &dpm_context->dpm_tables.dclk_table,
777 pptable->DclkFrequencyTable },
778 };
779
780 smu_v13_0_6_setup_driver_pptable(smu);
781
782 /* DPM policy not supported in older firmwares */
783 if (!(smu->adev->flags & AMD_IS_APU) &&
784 (smu->smc_fw_version < 0x00556000)) {
785 struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
786
787 smu_dpm->dpm_policies->policy_mask &=
788 ~BIT(PP_PM_POLICY_SOC_PSTATE);
789 }
790
791 smu_v13_0_6_pm_policy_init(smu);
792 /* gfxclk dpm table setup */
793 dpm_table = &dpm_context->dpm_tables.gfx_table;
794 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT)) {
795 /* In the case of gfxclk, only fine-grained dpm is honored.
796 * Get min/max values from FW.
797 */
798 ret = smu_v13_0_6_get_dpm_ultimate_freq(smu, SMU_GFXCLK,
799 &gfxclkmin, &gfxclkmax);
800 if (ret)
801 return ret;
802
803 dpm_table->count = 2;
804 dpm_table->dpm_levels[0].value = gfxclkmin;
805 dpm_table->dpm_levels[0].enabled = true;
806 dpm_table->dpm_levels[1].value = gfxclkmax;
807 dpm_table->dpm_levels[1].enabled = true;
808 dpm_table->min = dpm_table->dpm_levels[0].value;
809 dpm_table->max = dpm_table->dpm_levels[1].value;
810 } else {
811 dpm_table->count = 1;
812 dpm_table->dpm_levels[0].value = pptable->MinGfxclkFrequency;
813 dpm_table->dpm_levels[0].enabled = true;
814 dpm_table->min = dpm_table->dpm_levels[0].value;
815 dpm_table->max = dpm_table->dpm_levels[0].value;
816 }
817
818 for (j = 0; j < ARRAY_SIZE(dpm_map); j++) {
819 dpm_table = dpm_map[j].dpm_table;
820 levels = 1;
821 if (smu_cmn_feature_is_enabled(smu, dpm_map[j].feature_num)) {
822 ret = smu_v13_0_6_get_dpm_level_count(
823 smu, dpm_map[j].clk_type, &levels);
824 if (ret)
825 return ret;
826 }
827 dpm_table->count = levels;
828 for (i = 0; i < dpm_table->count; ++i) {
829 dpm_table->dpm_levels[i].value =
830 dpm_map[j].freq_table[i];
831 dpm_table->dpm_levels[i].enabled = true;
832
833 }
834 dpm_table->min = dpm_table->dpm_levels[0].value;
835 dpm_table->max = dpm_table->dpm_levels[levels - 1].value;
836
837 }
838
839 return 0;
840 }
841
smu_v13_0_6_setup_pptable(struct smu_context * smu)842 static int smu_v13_0_6_setup_pptable(struct smu_context *smu)
843 {
844 struct smu_table_context *table_context = &smu->smu_table;
845
846 /* TODO: PPTable is not available.
847 * 1) Find an alternate way to get 'PPTable values' here.
848 * 2) Check if there is SW CTF
849 */
850 table_context->thermal_controller_type = 0;
851
852 return 0;
853 }
854
smu_v13_0_6_check_fw_status(struct smu_context * smu)855 static int smu_v13_0_6_check_fw_status(struct smu_context *smu)
856 {
857 struct amdgpu_device *adev = smu->adev;
858 uint32_t mp1_fw_flags;
859
860 mp1_fw_flags =
861 RREG32_PCIE(MP1_Public | (smnMP1_FIRMWARE_FLAGS & 0xffffffff));
862
863 if ((mp1_fw_flags & MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK) >>
864 MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT)
865 return 0;
866
867 return -EIO;
868 }
869
smu_v13_0_6_populate_umd_state_clk(struct smu_context * smu)870 static int smu_v13_0_6_populate_umd_state_clk(struct smu_context *smu)
871 {
872 struct smu_13_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;
873 struct smu_13_0_dpm_table *gfx_table =
874 &dpm_context->dpm_tables.gfx_table;
875 struct smu_13_0_dpm_table *mem_table =
876 &dpm_context->dpm_tables.uclk_table;
877 struct smu_13_0_dpm_table *soc_table =
878 &dpm_context->dpm_tables.soc_table;
879 struct smu_umd_pstate_table *pstate_table = &smu->pstate_table;
880
881 pstate_table->gfxclk_pstate.min = gfx_table->min;
882 pstate_table->gfxclk_pstate.peak = gfx_table->max;
883 pstate_table->gfxclk_pstate.curr.min = gfx_table->min;
884 pstate_table->gfxclk_pstate.curr.max = gfx_table->max;
885
886 pstate_table->uclk_pstate.min = mem_table->min;
887 pstate_table->uclk_pstate.peak = mem_table->max;
888 pstate_table->uclk_pstate.curr.min = mem_table->min;
889 pstate_table->uclk_pstate.curr.max = mem_table->max;
890
891 pstate_table->socclk_pstate.min = soc_table->min;
892 pstate_table->socclk_pstate.peak = soc_table->max;
893 pstate_table->socclk_pstate.curr.min = soc_table->min;
894 pstate_table->socclk_pstate.curr.max = soc_table->max;
895
896 if (gfx_table->count > SMU_13_0_6_UMD_PSTATE_GFXCLK_LEVEL &&
897 mem_table->count > SMU_13_0_6_UMD_PSTATE_MCLK_LEVEL &&
898 soc_table->count > SMU_13_0_6_UMD_PSTATE_SOCCLK_LEVEL) {
899 pstate_table->gfxclk_pstate.standard =
900 gfx_table->dpm_levels[SMU_13_0_6_UMD_PSTATE_GFXCLK_LEVEL].value;
901 pstate_table->uclk_pstate.standard =
902 mem_table->dpm_levels[SMU_13_0_6_UMD_PSTATE_MCLK_LEVEL].value;
903 pstate_table->socclk_pstate.standard =
904 soc_table->dpm_levels[SMU_13_0_6_UMD_PSTATE_SOCCLK_LEVEL].value;
905 } else {
906 pstate_table->gfxclk_pstate.standard =
907 pstate_table->gfxclk_pstate.min;
908 pstate_table->uclk_pstate.standard =
909 pstate_table->uclk_pstate.min;
910 pstate_table->socclk_pstate.standard =
911 pstate_table->socclk_pstate.min;
912 }
913
914 return 0;
915 }
916
smu_v13_0_6_get_clk_table(struct smu_context * smu,struct pp_clock_levels_with_latency * clocks,struct smu_13_0_dpm_table * dpm_table)917 static int smu_v13_0_6_get_clk_table(struct smu_context *smu,
918 struct pp_clock_levels_with_latency *clocks,
919 struct smu_13_0_dpm_table *dpm_table)
920 {
921 int i, count;
922
923 count = (dpm_table->count > MAX_NUM_CLOCKS) ? MAX_NUM_CLOCKS :
924 dpm_table->count;
925 clocks->num_levels = count;
926
927 for (i = 0; i < count; i++) {
928 clocks->data[i].clocks_in_khz =
929 dpm_table->dpm_levels[i].value * 1000;
930 clocks->data[i].latency_in_us = 0;
931 }
932
933 return 0;
934 }
935
smu_v13_0_6_freqs_in_same_level(int32_t frequency1,int32_t frequency2)936 static int smu_v13_0_6_freqs_in_same_level(int32_t frequency1,
937 int32_t frequency2)
938 {
939 return (abs(frequency1 - frequency2) <= EPSILON);
940 }
941
smu_v13_0_6_get_throttler_status(struct smu_context * smu)942 static uint32_t smu_v13_0_6_get_throttler_status(struct smu_context *smu)
943 {
944 struct smu_power_context *smu_power = &smu->smu_power;
945 struct smu_13_0_power_context *power_context = smu_power->power_context;
946 uint32_t throttler_status = 0;
947
948 throttler_status = atomic_read(&power_context->throttle_status);
949 dev_dbg(smu->adev->dev, "SMU Throttler status: %u", throttler_status);
950
951 return throttler_status;
952 }
953
smu_v13_0_6_get_smu_metrics_data(struct smu_context * smu,MetricsMember_t member,uint32_t * value)954 static int smu_v13_0_6_get_smu_metrics_data(struct smu_context *smu,
955 MetricsMember_t member,
956 uint32_t *value)
957 {
958 struct smu_table_context *smu_table = &smu->smu_table;
959 MetricsTableX_t *metrics_x = (MetricsTableX_t *)smu_table->metrics_table;
960 MetricsTableA_t *metrics_a = (MetricsTableA_t *)smu_table->metrics_table;
961 struct amdgpu_device *adev = smu->adev;
962 int ret = 0;
963 int xcc_id;
964
965 ret = smu_v13_0_6_get_metrics_table(smu, NULL, false);
966 if (ret)
967 return ret;
968
969 /* For clocks with multiple instances, only report the first one */
970 switch (member) {
971 case METRICS_CURR_GFXCLK:
972 case METRICS_AVERAGE_GFXCLK:
973 if (smu->smc_fw_version >= 0x552F00) {
974 xcc_id = GET_INST(GC, 0);
975 *value = SMUQ10_ROUND(GET_METRIC_FIELD(GfxclkFrequency)[xcc_id]);
976 } else {
977 *value = 0;
978 }
979 break;
980 case METRICS_CURR_SOCCLK:
981 case METRICS_AVERAGE_SOCCLK:
982 *value = SMUQ10_ROUND(GET_METRIC_FIELD(SocclkFrequency)[0]);
983 break;
984 case METRICS_CURR_UCLK:
985 case METRICS_AVERAGE_UCLK:
986 *value = SMUQ10_ROUND(GET_METRIC_FIELD(UclkFrequency));
987 break;
988 case METRICS_CURR_VCLK:
989 *value = SMUQ10_ROUND(GET_METRIC_FIELD(VclkFrequency)[0]);
990 break;
991 case METRICS_CURR_DCLK:
992 *value = SMUQ10_ROUND(GET_METRIC_FIELD(DclkFrequency)[0]);
993 break;
994 case METRICS_CURR_FCLK:
995 *value = SMUQ10_ROUND(GET_METRIC_FIELD(FclkFrequency));
996 break;
997 case METRICS_AVERAGE_GFXACTIVITY:
998 *value = SMUQ10_ROUND(GET_METRIC_FIELD(SocketGfxBusy));
999 break;
1000 case METRICS_AVERAGE_MEMACTIVITY:
1001 *value = SMUQ10_ROUND(GET_METRIC_FIELD(DramBandwidthUtilization));
1002 break;
1003 case METRICS_CURR_SOCKETPOWER:
1004 *value = SMUQ10_ROUND(GET_METRIC_FIELD(SocketPower)) << 8;
1005 break;
1006 case METRICS_TEMPERATURE_HOTSPOT:
1007 *value = SMUQ10_ROUND(GET_METRIC_FIELD(MaxSocketTemperature)) *
1008 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1009 break;
1010 case METRICS_TEMPERATURE_MEM:
1011 *value = SMUQ10_ROUND(GET_METRIC_FIELD(MaxHbmTemperature)) *
1012 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1013 break;
1014 /* This is the max of all VRs and not just SOC VR.
1015 * No need to define another data type for the same.
1016 */
1017 case METRICS_TEMPERATURE_VRSOC:
1018 *value = SMUQ10_ROUND(GET_METRIC_FIELD(MaxVrTemperature)) *
1019 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1020 break;
1021 default:
1022 *value = UINT_MAX;
1023 break;
1024 }
1025
1026 return ret;
1027 }
1028
smu_v13_0_6_get_current_clk_freq_by_table(struct smu_context * smu,enum smu_clk_type clk_type,uint32_t * value)1029 static int smu_v13_0_6_get_current_clk_freq_by_table(struct smu_context *smu,
1030 enum smu_clk_type clk_type,
1031 uint32_t *value)
1032 {
1033 MetricsMember_t member_type;
1034
1035 if (!value)
1036 return -EINVAL;
1037
1038 switch (clk_type) {
1039 case SMU_GFXCLK:
1040 member_type = METRICS_CURR_GFXCLK;
1041 break;
1042 case SMU_UCLK:
1043 member_type = METRICS_CURR_UCLK;
1044 break;
1045 case SMU_SOCCLK:
1046 member_type = METRICS_CURR_SOCCLK;
1047 break;
1048 case SMU_VCLK:
1049 member_type = METRICS_CURR_VCLK;
1050 break;
1051 case SMU_DCLK:
1052 member_type = METRICS_CURR_DCLK;
1053 break;
1054 case SMU_FCLK:
1055 member_type = METRICS_CURR_FCLK;
1056 break;
1057 default:
1058 return -EINVAL;
1059 }
1060
1061 return smu_v13_0_6_get_smu_metrics_data(smu, member_type, value);
1062 }
1063
smu_v13_0_6_print_clks(struct smu_context * smu,char * buf,int size,struct smu_13_0_dpm_table * single_dpm_table,uint32_t curr_clk,const char * clk_name)1064 static int smu_v13_0_6_print_clks(struct smu_context *smu, char *buf, int size,
1065 struct smu_13_0_dpm_table *single_dpm_table,
1066 uint32_t curr_clk, const char *clk_name)
1067 {
1068 struct pp_clock_levels_with_latency clocks;
1069 int i, ret, level = -1;
1070 uint32_t clk1, clk2;
1071
1072 ret = smu_v13_0_6_get_clk_table(smu, &clocks, single_dpm_table);
1073 if (ret) {
1074 dev_err(smu->adev->dev, "Attempt to get %s clk levels failed!",
1075 clk_name);
1076 return ret;
1077 }
1078
1079 if (!clocks.num_levels)
1080 return -EINVAL;
1081
1082 if (curr_clk < SMU_13_0_6_DSCLK_THRESHOLD) {
1083 size = sysfs_emit_at(buf, size, "S: %uMhz *\n", curr_clk);
1084 for (i = 0; i < clocks.num_levels; i++)
1085 size += sysfs_emit_at(buf, size, "%d: %uMhz\n", i,
1086 clocks.data[i].clocks_in_khz /
1087 1000);
1088
1089 } else {
1090 if ((clocks.num_levels == 1) ||
1091 (curr_clk < (clocks.data[0].clocks_in_khz / 1000)))
1092 level = 0;
1093 for (i = 0; i < clocks.num_levels; i++) {
1094 clk1 = clocks.data[i].clocks_in_khz / 1000;
1095
1096 if (i < (clocks.num_levels - 1))
1097 clk2 = clocks.data[i + 1].clocks_in_khz / 1000;
1098
1099 if (curr_clk == clk1) {
1100 level = i;
1101 } else if (curr_clk >= clk1 && curr_clk < clk2) {
1102 level = (curr_clk - clk1) <= (clk2 - curr_clk) ?
1103 i :
1104 i + 1;
1105 }
1106
1107 size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n", i,
1108 clk1, (level == i) ? "*" : "");
1109 }
1110 }
1111
1112 return size;
1113 }
1114
smu_v13_0_6_print_clk_levels(struct smu_context * smu,enum smu_clk_type type,char * buf)1115 static int smu_v13_0_6_print_clk_levels(struct smu_context *smu,
1116 enum smu_clk_type type, char *buf)
1117 {
1118 int now, size = 0;
1119 int ret = 0;
1120 struct smu_umd_pstate_table *pstate_table = &smu->pstate_table;
1121 struct smu_13_0_dpm_table *single_dpm_table;
1122 struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
1123 struct smu_13_0_dpm_context *dpm_context = NULL;
1124 uint32_t min_clk, max_clk;
1125
1126 smu_cmn_get_sysfs_buf(&buf, &size);
1127
1128 if (amdgpu_ras_intr_triggered()) {
1129 size += sysfs_emit_at(buf, size, "unavailable\n");
1130 return size;
1131 }
1132
1133 dpm_context = smu_dpm->dpm_context;
1134
1135 switch (type) {
1136 case SMU_OD_SCLK:
1137 size += sysfs_emit_at(buf, size, "%s:\n", "OD_SCLK");
1138 size += sysfs_emit_at(buf, size, "0: %uMhz\n1: %uMhz\n",
1139 pstate_table->gfxclk_pstate.curr.min,
1140 pstate_table->gfxclk_pstate.curr.max);
1141 break;
1142 case SMU_SCLK:
1143 ret = smu_v13_0_6_get_current_clk_freq_by_table(smu, SMU_GFXCLK,
1144 &now);
1145 if (ret) {
1146 dev_err(smu->adev->dev,
1147 "Attempt to get current gfx clk Failed!");
1148 return ret;
1149 }
1150
1151 min_clk = pstate_table->gfxclk_pstate.curr.min;
1152 max_clk = pstate_table->gfxclk_pstate.curr.max;
1153
1154 if (now < SMU_13_0_6_DSCLK_THRESHOLD) {
1155 size += sysfs_emit_at(buf, size, "S: %uMhz *\n",
1156 now);
1157 size += sysfs_emit_at(buf, size, "0: %uMhz\n",
1158 min_clk);
1159 size += sysfs_emit_at(buf, size, "1: %uMhz\n",
1160 max_clk);
1161
1162 } else if (!smu_v13_0_6_freqs_in_same_level(now, min_clk) &&
1163 !smu_v13_0_6_freqs_in_same_level(now, max_clk)) {
1164 size += sysfs_emit_at(buf, size, "0: %uMhz\n",
1165 min_clk);
1166 size += sysfs_emit_at(buf, size, "1: %uMhz *\n",
1167 now);
1168 size += sysfs_emit_at(buf, size, "2: %uMhz\n",
1169 max_clk);
1170 } else {
1171 size += sysfs_emit_at(buf, size, "0: %uMhz %s\n",
1172 min_clk,
1173 smu_v13_0_6_freqs_in_same_level(now, min_clk) ? "*" : "");
1174 size += sysfs_emit_at(buf, size, "1: %uMhz %s\n",
1175 max_clk,
1176 smu_v13_0_6_freqs_in_same_level(now, max_clk) ? "*" : "");
1177 }
1178
1179 break;
1180
1181 case SMU_OD_MCLK:
1182 size += sysfs_emit_at(buf, size, "%s:\n", "OD_MCLK");
1183 size += sysfs_emit_at(buf, size, "0: %uMhz\n1: %uMhz\n",
1184 pstate_table->uclk_pstate.curr.min,
1185 pstate_table->uclk_pstate.curr.max);
1186 break;
1187 case SMU_MCLK:
1188 ret = smu_v13_0_6_get_current_clk_freq_by_table(smu, SMU_UCLK,
1189 &now);
1190 if (ret) {
1191 dev_err(smu->adev->dev,
1192 "Attempt to get current mclk Failed!");
1193 return ret;
1194 }
1195
1196 single_dpm_table = &(dpm_context->dpm_tables.uclk_table);
1197
1198 return smu_v13_0_6_print_clks(smu, buf, size, single_dpm_table,
1199 now, "mclk");
1200
1201 case SMU_SOCCLK:
1202 ret = smu_v13_0_6_get_current_clk_freq_by_table(smu, SMU_SOCCLK,
1203 &now);
1204 if (ret) {
1205 dev_err(smu->adev->dev,
1206 "Attempt to get current socclk Failed!");
1207 return ret;
1208 }
1209
1210 single_dpm_table = &(dpm_context->dpm_tables.soc_table);
1211
1212 return smu_v13_0_6_print_clks(smu, buf, size, single_dpm_table,
1213 now, "socclk");
1214
1215 case SMU_FCLK:
1216 ret = smu_v13_0_6_get_current_clk_freq_by_table(smu, SMU_FCLK,
1217 &now);
1218 if (ret) {
1219 dev_err(smu->adev->dev,
1220 "Attempt to get current fclk Failed!");
1221 return ret;
1222 }
1223
1224 single_dpm_table = &(dpm_context->dpm_tables.fclk_table);
1225
1226 return smu_v13_0_6_print_clks(smu, buf, size, single_dpm_table,
1227 now, "fclk");
1228
1229 case SMU_VCLK:
1230 ret = smu_v13_0_6_get_current_clk_freq_by_table(smu, SMU_VCLK,
1231 &now);
1232 if (ret) {
1233 dev_err(smu->adev->dev,
1234 "Attempt to get current vclk Failed!");
1235 return ret;
1236 }
1237
1238 single_dpm_table = &(dpm_context->dpm_tables.vclk_table);
1239
1240 return smu_v13_0_6_print_clks(smu, buf, size, single_dpm_table,
1241 now, "vclk");
1242
1243 case SMU_DCLK:
1244 ret = smu_v13_0_6_get_current_clk_freq_by_table(smu, SMU_DCLK,
1245 &now);
1246 if (ret) {
1247 dev_err(smu->adev->dev,
1248 "Attempt to get current dclk Failed!");
1249 return ret;
1250 }
1251
1252 single_dpm_table = &(dpm_context->dpm_tables.dclk_table);
1253
1254 return smu_v13_0_6_print_clks(smu, buf, size, single_dpm_table,
1255 now, "dclk");
1256
1257 default:
1258 break;
1259 }
1260
1261 return size;
1262 }
1263
smu_v13_0_6_upload_dpm_level(struct smu_context * smu,bool max,uint32_t feature_mask,uint32_t level)1264 static int smu_v13_0_6_upload_dpm_level(struct smu_context *smu, bool max,
1265 uint32_t feature_mask, uint32_t level)
1266 {
1267 struct smu_13_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;
1268 uint32_t freq;
1269 int ret = 0;
1270
1271 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT) &&
1272 (feature_mask & FEATURE_MASK(FEATURE_DPM_GFXCLK))) {
1273 freq = dpm_context->dpm_tables.gfx_table.dpm_levels[level].value;
1274 ret = smu_cmn_send_smc_msg_with_param(
1275 smu,
1276 (max ? SMU_MSG_SetSoftMaxGfxClk :
1277 SMU_MSG_SetSoftMinGfxclk),
1278 freq & 0xffff, NULL);
1279 if (ret) {
1280 dev_err(smu->adev->dev,
1281 "Failed to set soft %s gfxclk !\n",
1282 max ? "max" : "min");
1283 return ret;
1284 }
1285 }
1286
1287 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT) &&
1288 (feature_mask & FEATURE_MASK(FEATURE_DPM_UCLK))) {
1289 freq = dpm_context->dpm_tables.uclk_table.dpm_levels[level]
1290 .value;
1291 ret = smu_cmn_send_smc_msg_with_param(
1292 smu,
1293 (max ? SMU_MSG_SetSoftMaxByFreq :
1294 SMU_MSG_SetSoftMinByFreq),
1295 (PPCLK_UCLK << 16) | (freq & 0xffff), NULL);
1296 if (ret) {
1297 dev_err(smu->adev->dev,
1298 "Failed to set soft %s memclk !\n",
1299 max ? "max" : "min");
1300 return ret;
1301 }
1302 }
1303
1304 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT) &&
1305 (feature_mask & FEATURE_MASK(FEATURE_DPM_SOCCLK))) {
1306 freq = dpm_context->dpm_tables.soc_table.dpm_levels[level].value;
1307 ret = smu_cmn_send_smc_msg_with_param(
1308 smu,
1309 (max ? SMU_MSG_SetSoftMaxByFreq :
1310 SMU_MSG_SetSoftMinByFreq),
1311 (PPCLK_SOCCLK << 16) | (freq & 0xffff), NULL);
1312 if (ret) {
1313 dev_err(smu->adev->dev,
1314 "Failed to set soft %s socclk !\n",
1315 max ? "max" : "min");
1316 return ret;
1317 }
1318 }
1319
1320 return ret;
1321 }
1322
smu_v13_0_6_force_clk_levels(struct smu_context * smu,enum smu_clk_type type,uint32_t mask)1323 static int smu_v13_0_6_force_clk_levels(struct smu_context *smu,
1324 enum smu_clk_type type, uint32_t mask)
1325 {
1326 struct smu_13_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;
1327 struct smu_13_0_dpm_table *single_dpm_table = NULL;
1328 uint32_t soft_min_level, soft_max_level;
1329 int ret = 0;
1330
1331 soft_min_level = mask ? (ffs(mask) - 1) : 0;
1332 soft_max_level = mask ? (fls(mask) - 1) : 0;
1333
1334 switch (type) {
1335 case SMU_SCLK:
1336 single_dpm_table = &(dpm_context->dpm_tables.gfx_table);
1337 if (soft_max_level >= single_dpm_table->count) {
1338 dev_err(smu->adev->dev,
1339 "Clock level specified %d is over max allowed %d\n",
1340 soft_max_level, single_dpm_table->count - 1);
1341 ret = -EINVAL;
1342 break;
1343 }
1344
1345 ret = smu_v13_0_6_upload_dpm_level(
1346 smu, false, FEATURE_MASK(FEATURE_DPM_GFXCLK),
1347 soft_min_level);
1348 if (ret) {
1349 dev_err(smu->adev->dev,
1350 "Failed to upload boot level to lowest!\n");
1351 break;
1352 }
1353
1354 ret = smu_v13_0_6_upload_dpm_level(
1355 smu, true, FEATURE_MASK(FEATURE_DPM_GFXCLK),
1356 soft_max_level);
1357 if (ret)
1358 dev_err(smu->adev->dev,
1359 "Failed to upload dpm max level to highest!\n");
1360
1361 break;
1362
1363 case SMU_MCLK:
1364 case SMU_SOCCLK:
1365 case SMU_FCLK:
1366 /*
1367 * Should not arrive here since smu_13_0_6 does not
1368 * support mclk/socclk/fclk softmin/softmax settings
1369 */
1370 ret = -EINVAL;
1371 break;
1372
1373 default:
1374 break;
1375 }
1376
1377 return ret;
1378 }
1379
smu_v13_0_6_get_current_activity_percent(struct smu_context * smu,enum amd_pp_sensors sensor,uint32_t * value)1380 static int smu_v13_0_6_get_current_activity_percent(struct smu_context *smu,
1381 enum amd_pp_sensors sensor,
1382 uint32_t *value)
1383 {
1384 int ret = 0;
1385
1386 if (!value)
1387 return -EINVAL;
1388
1389 switch (sensor) {
1390 case AMDGPU_PP_SENSOR_GPU_LOAD:
1391 ret = smu_v13_0_6_get_smu_metrics_data(
1392 smu, METRICS_AVERAGE_GFXACTIVITY, value);
1393 break;
1394 case AMDGPU_PP_SENSOR_MEM_LOAD:
1395 ret = smu_v13_0_6_get_smu_metrics_data(
1396 smu, METRICS_AVERAGE_MEMACTIVITY, value);
1397 break;
1398 default:
1399 dev_err(smu->adev->dev,
1400 "Invalid sensor for retrieving clock activity\n");
1401 return -EINVAL;
1402 }
1403
1404 return ret;
1405 }
1406
smu_v13_0_6_thermal_get_temperature(struct smu_context * smu,enum amd_pp_sensors sensor,uint32_t * value)1407 static int smu_v13_0_6_thermal_get_temperature(struct smu_context *smu,
1408 enum amd_pp_sensors sensor,
1409 uint32_t *value)
1410 {
1411 int ret = 0;
1412
1413 if (!value)
1414 return -EINVAL;
1415
1416 switch (sensor) {
1417 case AMDGPU_PP_SENSOR_HOTSPOT_TEMP:
1418 ret = smu_v13_0_6_get_smu_metrics_data(
1419 smu, METRICS_TEMPERATURE_HOTSPOT, value);
1420 break;
1421 case AMDGPU_PP_SENSOR_MEM_TEMP:
1422 ret = smu_v13_0_6_get_smu_metrics_data(
1423 smu, METRICS_TEMPERATURE_MEM, value);
1424 break;
1425 default:
1426 dev_err(smu->adev->dev, "Invalid sensor for retrieving temp\n");
1427 return -EINVAL;
1428 }
1429
1430 return ret;
1431 }
1432
smu_v13_0_6_read_sensor(struct smu_context * smu,enum amd_pp_sensors sensor,void * data,uint32_t * size)1433 static int smu_v13_0_6_read_sensor(struct smu_context *smu,
1434 enum amd_pp_sensors sensor, void *data,
1435 uint32_t *size)
1436 {
1437 int ret = 0;
1438
1439 if (amdgpu_ras_intr_triggered())
1440 return 0;
1441
1442 if (!data || !size)
1443 return -EINVAL;
1444
1445 switch (sensor) {
1446 case AMDGPU_PP_SENSOR_MEM_LOAD:
1447 case AMDGPU_PP_SENSOR_GPU_LOAD:
1448 ret = smu_v13_0_6_get_current_activity_percent(smu, sensor,
1449 (uint32_t *)data);
1450 *size = 4;
1451 break;
1452 case AMDGPU_PP_SENSOR_GPU_INPUT_POWER:
1453 ret = smu_v13_0_6_get_smu_metrics_data(smu,
1454 METRICS_CURR_SOCKETPOWER,
1455 (uint32_t *)data);
1456 *size = 4;
1457 break;
1458 case AMDGPU_PP_SENSOR_HOTSPOT_TEMP:
1459 case AMDGPU_PP_SENSOR_MEM_TEMP:
1460 ret = smu_v13_0_6_thermal_get_temperature(smu, sensor,
1461 (uint32_t *)data);
1462 *size = 4;
1463 break;
1464 case AMDGPU_PP_SENSOR_GFX_MCLK:
1465 ret = smu_v13_0_6_get_current_clk_freq_by_table(
1466 smu, SMU_UCLK, (uint32_t *)data);
1467 /* the output clock frequency in 10K unit */
1468 *(uint32_t *)data *= 100;
1469 *size = 4;
1470 break;
1471 case AMDGPU_PP_SENSOR_GFX_SCLK:
1472 ret = smu_v13_0_6_get_current_clk_freq_by_table(
1473 smu, SMU_GFXCLK, (uint32_t *)data);
1474 *(uint32_t *)data *= 100;
1475 *size = 4;
1476 break;
1477 case AMDGPU_PP_SENSOR_VDDGFX:
1478 ret = smu_v13_0_get_gfx_vdd(smu, (uint32_t *)data);
1479 *size = 4;
1480 break;
1481 case AMDGPU_PP_SENSOR_GPU_AVG_POWER:
1482 default:
1483 ret = -EOPNOTSUPP;
1484 break;
1485 }
1486
1487 return ret;
1488 }
1489
smu_v13_0_6_get_power_limit(struct smu_context * smu,uint32_t * current_power_limit,uint32_t * default_power_limit,uint32_t * max_power_limit,uint32_t * min_power_limit)1490 static int smu_v13_0_6_get_power_limit(struct smu_context *smu,
1491 uint32_t *current_power_limit,
1492 uint32_t *default_power_limit,
1493 uint32_t *max_power_limit,
1494 uint32_t *min_power_limit)
1495 {
1496 struct smu_table_context *smu_table = &smu->smu_table;
1497 struct PPTable_t *pptable =
1498 (struct PPTable_t *)smu_table->driver_pptable;
1499 uint32_t power_limit = 0;
1500 int ret;
1501
1502 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_GetPptLimit, &power_limit);
1503
1504 if (ret) {
1505 dev_err(smu->adev->dev, "Couldn't get PPT limit");
1506 return -EINVAL;
1507 }
1508
1509 if (current_power_limit)
1510 *current_power_limit = power_limit;
1511 if (default_power_limit)
1512 *default_power_limit = power_limit;
1513
1514 if (max_power_limit) {
1515 *max_power_limit = pptable->MaxSocketPowerLimit;
1516 }
1517
1518 if (min_power_limit)
1519 *min_power_limit = 0;
1520 return 0;
1521 }
1522
smu_v13_0_6_set_power_limit(struct smu_context * smu,enum smu_ppt_limit_type limit_type,uint32_t limit)1523 static int smu_v13_0_6_set_power_limit(struct smu_context *smu,
1524 enum smu_ppt_limit_type limit_type,
1525 uint32_t limit)
1526 {
1527 return smu_v13_0_set_power_limit(smu, limit_type, limit);
1528 }
1529
smu_v13_0_6_irq_process(struct amdgpu_device * adev,struct amdgpu_irq_src * source,struct amdgpu_iv_entry * entry)1530 static int smu_v13_0_6_irq_process(struct amdgpu_device *adev,
1531 struct amdgpu_irq_src *source,
1532 struct amdgpu_iv_entry *entry)
1533 {
1534 struct smu_context *smu = adev->powerplay.pp_handle;
1535 struct smu_power_context *smu_power = &smu->smu_power;
1536 struct smu_13_0_power_context *power_context = smu_power->power_context;
1537 uint32_t client_id = entry->client_id;
1538 uint32_t ctxid = entry->src_data[0];
1539 uint32_t src_id = entry->src_id;
1540 uint32_t data;
1541
1542 if (client_id == SOC15_IH_CLIENTID_MP1) {
1543 if (src_id == IH_INTERRUPT_ID_TO_DRIVER) {
1544 /* ACK SMUToHost interrupt */
1545 data = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL);
1546 data = REG_SET_FIELD(data, MP1_SMN_IH_SW_INT_CTRL, INT_ACK, 1);
1547 WREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL, data);
1548 /*
1549 * ctxid is used to distinguish different events for SMCToHost
1550 * interrupt.
1551 */
1552 switch (ctxid) {
1553 case IH_INTERRUPT_CONTEXT_ID_THERMAL_THROTTLING:
1554 /*
1555 * Increment the throttle interrupt counter
1556 */
1557 atomic64_inc(&smu->throttle_int_counter);
1558
1559 if (!atomic_read(&adev->throttling_logging_enabled))
1560 return 0;
1561
1562 /* This uses the new method which fixes the
1563 * incorrect throttling status reporting
1564 * through metrics table. For older FWs,
1565 * it will be ignored.
1566 */
1567 if (__ratelimit(&adev->throttling_logging_rs)) {
1568 atomic_set(
1569 &power_context->throttle_status,
1570 entry->src_data[1]);
1571 schedule_work(&smu->throttling_logging_work);
1572 }
1573 break;
1574 default:
1575 dev_dbg(adev->dev, "Unhandled context id %d from client:%d!\n",
1576 ctxid, client_id);
1577 break;
1578 }
1579 }
1580 }
1581
1582 return 0;
1583 }
1584
smu_v13_0_6_set_irq_state(struct amdgpu_device * adev,struct amdgpu_irq_src * source,unsigned tyep,enum amdgpu_interrupt_state state)1585 static int smu_v13_0_6_set_irq_state(struct amdgpu_device *adev,
1586 struct amdgpu_irq_src *source,
1587 unsigned tyep,
1588 enum amdgpu_interrupt_state state)
1589 {
1590 uint32_t val = 0;
1591
1592 switch (state) {
1593 case AMDGPU_IRQ_STATE_DISABLE:
1594 /* For MP1 SW irqs */
1595 val = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL);
1596 val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT_CTRL, INT_MASK, 1);
1597 WREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL, val);
1598
1599 break;
1600 case AMDGPU_IRQ_STATE_ENABLE:
1601 /* For MP1 SW irqs */
1602 val = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT);
1603 val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT, ID, 0xFE);
1604 val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT, VALID, 0);
1605 WREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT, val);
1606
1607 val = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL);
1608 val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT_CTRL, INT_MASK, 0);
1609 WREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL, val);
1610
1611 break;
1612 default:
1613 break;
1614 }
1615
1616 return 0;
1617 }
1618
1619 static const struct amdgpu_irq_src_funcs smu_v13_0_6_irq_funcs = {
1620 .set = smu_v13_0_6_set_irq_state,
1621 .process = smu_v13_0_6_irq_process,
1622 };
1623
smu_v13_0_6_register_irq_handler(struct smu_context * smu)1624 static int smu_v13_0_6_register_irq_handler(struct smu_context *smu)
1625 {
1626 struct amdgpu_device *adev = smu->adev;
1627 struct amdgpu_irq_src *irq_src = &smu->irq_source;
1628 int ret = 0;
1629
1630 if (amdgpu_sriov_vf(adev))
1631 return 0;
1632
1633 irq_src->num_types = 1;
1634 irq_src->funcs = &smu_v13_0_6_irq_funcs;
1635
1636 ret = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_MP1,
1637 IH_INTERRUPT_ID_TO_DRIVER,
1638 irq_src);
1639 if (ret)
1640 return ret;
1641
1642 return ret;
1643 }
1644
smu_v13_0_6_notify_unload(struct smu_context * smu)1645 static int smu_v13_0_6_notify_unload(struct smu_context *smu)
1646 {
1647 if (amdgpu_in_reset(smu->adev))
1648 return 0;
1649
1650 dev_dbg(smu->adev->dev, "Notify PMFW about driver unload");
1651 /* Ignore return, just intimate FW that driver is not going to be there */
1652 smu_cmn_send_smc_msg(smu, SMU_MSG_PrepareMp1ForUnload, NULL);
1653
1654 return 0;
1655 }
1656
smu_v13_0_6_mca_set_debug_mode(struct smu_context * smu,bool enable)1657 static int smu_v13_0_6_mca_set_debug_mode(struct smu_context *smu, bool enable)
1658 {
1659 /* NOTE: this ClearMcaOnRead message is only supported for smu version 85.72.0 or higher */
1660 if (smu->smc_fw_version < 0x554800)
1661 return 0;
1662
1663 return smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_ClearMcaOnRead,
1664 enable ? 0 : ClearMcaOnRead_UE_FLAG_MASK | ClearMcaOnRead_CE_POLL_MASK,
1665 NULL);
1666 }
1667
smu_v13_0_6_system_features_control(struct smu_context * smu,bool enable)1668 static int smu_v13_0_6_system_features_control(struct smu_context *smu,
1669 bool enable)
1670 {
1671 struct amdgpu_device *adev = smu->adev;
1672 int ret = 0;
1673
1674 if (amdgpu_sriov_vf(adev))
1675 return 0;
1676
1677 if (enable) {
1678 if (!(adev->flags & AMD_IS_APU))
1679 ret = smu_v13_0_system_features_control(smu, enable);
1680 } else {
1681 /* Notify FW that the device is no longer driver managed */
1682 smu_v13_0_6_notify_unload(smu);
1683 }
1684
1685 return ret;
1686 }
1687
smu_v13_0_6_set_gfx_soft_freq_limited_range(struct smu_context * smu,uint32_t min,uint32_t max)1688 static int smu_v13_0_6_set_gfx_soft_freq_limited_range(struct smu_context *smu,
1689 uint32_t min,
1690 uint32_t max)
1691 {
1692 int ret;
1693
1694 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxGfxClk,
1695 max & 0xffff, NULL);
1696 if (ret)
1697 return ret;
1698
1699 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMinGfxclk,
1700 min & 0xffff, NULL);
1701
1702 return ret;
1703 }
1704
smu_v13_0_6_set_performance_level(struct smu_context * smu,enum amd_dpm_forced_level level)1705 static int smu_v13_0_6_set_performance_level(struct smu_context *smu,
1706 enum amd_dpm_forced_level level)
1707 {
1708 struct smu_dpm_context *smu_dpm = &(smu->smu_dpm);
1709 struct smu_13_0_dpm_context *dpm_context = smu_dpm->dpm_context;
1710 struct smu_13_0_dpm_table *gfx_table =
1711 &dpm_context->dpm_tables.gfx_table;
1712 struct smu_13_0_dpm_table *uclk_table =
1713 &dpm_context->dpm_tables.uclk_table;
1714 struct smu_umd_pstate_table *pstate_table = &smu->pstate_table;
1715 int ret;
1716
1717 /* Disable determinism if switching to another mode */
1718 if ((smu_dpm->dpm_level == AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM) &&
1719 (level != AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM)) {
1720 smu_cmn_send_smc_msg(smu, SMU_MSG_DisableDeterminism, NULL);
1721 pstate_table->gfxclk_pstate.curr.max = gfx_table->max;
1722 }
1723
1724 switch (level) {
1725 case AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM:
1726 return 0;
1727
1728 case AMD_DPM_FORCED_LEVEL_AUTO:
1729 if ((gfx_table->min != pstate_table->gfxclk_pstate.curr.min) ||
1730 (gfx_table->max != pstate_table->gfxclk_pstate.curr.max)) {
1731 ret = smu_v13_0_6_set_gfx_soft_freq_limited_range(
1732 smu, gfx_table->min, gfx_table->max);
1733 if (ret)
1734 return ret;
1735
1736 pstate_table->gfxclk_pstate.curr.min = gfx_table->min;
1737 pstate_table->gfxclk_pstate.curr.max = gfx_table->max;
1738 }
1739
1740 if (uclk_table->max != pstate_table->uclk_pstate.curr.max) {
1741 /* Min UCLK is not expected to be changed */
1742 ret = smu_v13_0_set_soft_freq_limited_range(
1743 smu, SMU_UCLK, 0, uclk_table->max);
1744 if (ret)
1745 return ret;
1746 pstate_table->uclk_pstate.curr.max = uclk_table->max;
1747 }
1748 pstate_table->uclk_pstate.custom.max = 0;
1749
1750 return 0;
1751 case AMD_DPM_FORCED_LEVEL_MANUAL:
1752 return 0;
1753 default:
1754 break;
1755 }
1756
1757 return -EINVAL;
1758 }
1759
smu_v13_0_6_set_soft_freq_limited_range(struct smu_context * smu,enum smu_clk_type clk_type,uint32_t min,uint32_t max)1760 static int smu_v13_0_6_set_soft_freq_limited_range(struct smu_context *smu,
1761 enum smu_clk_type clk_type,
1762 uint32_t min, uint32_t max)
1763 {
1764 struct smu_dpm_context *smu_dpm = &(smu->smu_dpm);
1765 struct smu_13_0_dpm_context *dpm_context = smu_dpm->dpm_context;
1766 struct smu_umd_pstate_table *pstate_table = &smu->pstate_table;
1767 struct amdgpu_device *adev = smu->adev;
1768 uint32_t min_clk;
1769 uint32_t max_clk;
1770 int ret = 0;
1771
1772 if (clk_type != SMU_GFXCLK && clk_type != SMU_SCLK &&
1773 clk_type != SMU_UCLK)
1774 return -EINVAL;
1775
1776 if ((smu_dpm->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) &&
1777 (smu_dpm->dpm_level != AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM))
1778 return -EINVAL;
1779
1780 if (smu_dpm->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL) {
1781 if (min >= max) {
1782 dev_err(smu->adev->dev,
1783 "Minimum clk should be less than the maximum allowed clock\n");
1784 return -EINVAL;
1785 }
1786
1787 if (clk_type == SMU_GFXCLK) {
1788 if ((min == pstate_table->gfxclk_pstate.curr.min) &&
1789 (max == pstate_table->gfxclk_pstate.curr.max))
1790 return 0;
1791
1792 ret = smu_v13_0_6_set_gfx_soft_freq_limited_range(
1793 smu, min, max);
1794 if (!ret) {
1795 pstate_table->gfxclk_pstate.curr.min = min;
1796 pstate_table->gfxclk_pstate.curr.max = max;
1797 }
1798 }
1799
1800 if (clk_type == SMU_UCLK) {
1801 if (max == pstate_table->uclk_pstate.curr.max)
1802 return 0;
1803 /* For VF, only allowed in FW versions 85.102 or greater */
1804 if (amdgpu_sriov_vf(adev) &&
1805 ((smu->smc_fw_version < 0x556600) ||
1806 (adev->flags & AMD_IS_APU)))
1807 return -EOPNOTSUPP;
1808 /* Only max clock limiting is allowed for UCLK */
1809 ret = smu_v13_0_set_soft_freq_limited_range(
1810 smu, SMU_UCLK, 0, max);
1811 if (!ret)
1812 pstate_table->uclk_pstate.curr.max = max;
1813 }
1814
1815 return ret;
1816 }
1817
1818 if (smu_dpm->dpm_level == AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM) {
1819 if (!max || (max < dpm_context->dpm_tables.gfx_table.min) ||
1820 (max > dpm_context->dpm_tables.gfx_table.max)) {
1821 dev_warn(
1822 adev->dev,
1823 "Invalid max frequency %d MHz specified for determinism\n",
1824 max);
1825 return -EINVAL;
1826 }
1827
1828 /* Restore default min/max clocks and enable determinism */
1829 min_clk = dpm_context->dpm_tables.gfx_table.min;
1830 max_clk = dpm_context->dpm_tables.gfx_table.max;
1831 ret = smu_v13_0_6_set_gfx_soft_freq_limited_range(smu, min_clk,
1832 max_clk);
1833 if (!ret) {
1834 usleep_range(500, 1000);
1835 ret = smu_cmn_send_smc_msg_with_param(
1836 smu, SMU_MSG_EnableDeterminism, max, NULL);
1837 if (ret) {
1838 dev_err(adev->dev,
1839 "Failed to enable determinism at GFX clock %d MHz\n",
1840 max);
1841 } else {
1842 pstate_table->gfxclk_pstate.curr.min = min_clk;
1843 pstate_table->gfxclk_pstate.curr.max = max;
1844 }
1845 }
1846 }
1847
1848 return ret;
1849 }
1850
smu_v13_0_6_usr_edit_dpm_table(struct smu_context * smu,enum PP_OD_DPM_TABLE_COMMAND type,long input[],uint32_t size)1851 static int smu_v13_0_6_usr_edit_dpm_table(struct smu_context *smu,
1852 enum PP_OD_DPM_TABLE_COMMAND type,
1853 long input[], uint32_t size)
1854 {
1855 struct smu_dpm_context *smu_dpm = &(smu->smu_dpm);
1856 struct smu_13_0_dpm_context *dpm_context = smu_dpm->dpm_context;
1857 struct smu_umd_pstate_table *pstate_table = &smu->pstate_table;
1858 uint32_t min_clk;
1859 uint32_t max_clk;
1860 int ret = 0;
1861
1862 /* Only allowed in manual or determinism mode */
1863 if ((smu_dpm->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) &&
1864 (smu_dpm->dpm_level != AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM))
1865 return -EINVAL;
1866
1867 switch (type) {
1868 case PP_OD_EDIT_SCLK_VDDC_TABLE:
1869 if (size != 2) {
1870 dev_err(smu->adev->dev,
1871 "Input parameter number not correct\n");
1872 return -EINVAL;
1873 }
1874
1875 if (input[0] == 0) {
1876 if (input[1] < dpm_context->dpm_tables.gfx_table.min) {
1877 dev_warn(
1878 smu->adev->dev,
1879 "Minimum GFX clk (%ld) MHz specified is less than the minimum allowed (%d) MHz\n",
1880 input[1],
1881 dpm_context->dpm_tables.gfx_table.min);
1882 pstate_table->gfxclk_pstate.custom.min =
1883 pstate_table->gfxclk_pstate.curr.min;
1884 return -EINVAL;
1885 }
1886
1887 pstate_table->gfxclk_pstate.custom.min = input[1];
1888 } else if (input[0] == 1) {
1889 if (input[1] > dpm_context->dpm_tables.gfx_table.max) {
1890 dev_warn(
1891 smu->adev->dev,
1892 "Maximum GFX clk (%ld) MHz specified is greater than the maximum allowed (%d) MHz\n",
1893 input[1],
1894 dpm_context->dpm_tables.gfx_table.max);
1895 pstate_table->gfxclk_pstate.custom.max =
1896 pstate_table->gfxclk_pstate.curr.max;
1897 return -EINVAL;
1898 }
1899
1900 pstate_table->gfxclk_pstate.custom.max = input[1];
1901 } else {
1902 return -EINVAL;
1903 }
1904 break;
1905 case PP_OD_EDIT_MCLK_VDDC_TABLE:
1906 if (size != 2) {
1907 dev_err(smu->adev->dev,
1908 "Input parameter number not correct\n");
1909 return -EINVAL;
1910 }
1911
1912 if (!smu_cmn_feature_is_enabled(smu,
1913 SMU_FEATURE_DPM_UCLK_BIT)) {
1914 dev_warn(smu->adev->dev,
1915 "UCLK_LIMITS setting not supported!\n");
1916 return -EOPNOTSUPP;
1917 }
1918
1919 if (input[0] == 0) {
1920 dev_info(smu->adev->dev,
1921 "Setting min UCLK level is not supported");
1922 return -EINVAL;
1923 } else if (input[0] == 1) {
1924 if (input[1] > dpm_context->dpm_tables.uclk_table.max) {
1925 dev_warn(
1926 smu->adev->dev,
1927 "Maximum UCLK (%ld) MHz specified is greater than the maximum allowed (%d) MHz\n",
1928 input[1],
1929 dpm_context->dpm_tables.uclk_table.max);
1930 pstate_table->uclk_pstate.custom.max =
1931 pstate_table->uclk_pstate.curr.max;
1932 return -EINVAL;
1933 }
1934
1935 pstate_table->uclk_pstate.custom.max = input[1];
1936 }
1937 break;
1938
1939 case PP_OD_RESTORE_DEFAULT_TABLE:
1940 if (size != 0) {
1941 dev_err(smu->adev->dev,
1942 "Input parameter number not correct\n");
1943 return -EINVAL;
1944 } else {
1945 /* Use the default frequencies for manual and determinism mode */
1946 min_clk = dpm_context->dpm_tables.gfx_table.min;
1947 max_clk = dpm_context->dpm_tables.gfx_table.max;
1948
1949 ret = smu_v13_0_6_set_soft_freq_limited_range(
1950 smu, SMU_GFXCLK, min_clk, max_clk);
1951
1952 if (ret)
1953 return ret;
1954
1955 min_clk = dpm_context->dpm_tables.uclk_table.min;
1956 max_clk = dpm_context->dpm_tables.uclk_table.max;
1957 ret = smu_v13_0_6_set_soft_freq_limited_range(
1958 smu, SMU_UCLK, min_clk, max_clk);
1959 if (ret)
1960 return ret;
1961 pstate_table->uclk_pstate.custom.max = 0;
1962 }
1963 break;
1964 case PP_OD_COMMIT_DPM_TABLE:
1965 if (size != 0) {
1966 dev_err(smu->adev->dev,
1967 "Input parameter number not correct\n");
1968 return -EINVAL;
1969 } else {
1970 if (!pstate_table->gfxclk_pstate.custom.min)
1971 pstate_table->gfxclk_pstate.custom.min =
1972 pstate_table->gfxclk_pstate.curr.min;
1973
1974 if (!pstate_table->gfxclk_pstate.custom.max)
1975 pstate_table->gfxclk_pstate.custom.max =
1976 pstate_table->gfxclk_pstate.curr.max;
1977
1978 min_clk = pstate_table->gfxclk_pstate.custom.min;
1979 max_clk = pstate_table->gfxclk_pstate.custom.max;
1980
1981 ret = smu_v13_0_6_set_soft_freq_limited_range(
1982 smu, SMU_GFXCLK, min_clk, max_clk);
1983
1984 if (ret)
1985 return ret;
1986
1987 if (!pstate_table->uclk_pstate.custom.max)
1988 return 0;
1989
1990 min_clk = pstate_table->uclk_pstate.curr.min;
1991 max_clk = pstate_table->uclk_pstate.custom.max;
1992 return smu_v13_0_6_set_soft_freq_limited_range(
1993 smu, SMU_UCLK, min_clk, max_clk);
1994 }
1995 break;
1996 default:
1997 return -ENOSYS;
1998 }
1999
2000 return ret;
2001 }
2002
smu_v13_0_6_get_enabled_mask(struct smu_context * smu,uint64_t * feature_mask)2003 static int smu_v13_0_6_get_enabled_mask(struct smu_context *smu,
2004 uint64_t *feature_mask)
2005 {
2006 int ret;
2007
2008 ret = smu_cmn_get_enabled_mask(smu, feature_mask);
2009
2010 if (ret == -EIO && smu->smc_fw_version < 0x552F00) {
2011 *feature_mask = 0;
2012 ret = 0;
2013 }
2014
2015 return ret;
2016 }
2017
smu_v13_0_6_is_dpm_running(struct smu_context * smu)2018 static bool smu_v13_0_6_is_dpm_running(struct smu_context *smu)
2019 {
2020 int ret;
2021 uint64_t feature_enabled;
2022
2023 ret = smu_v13_0_6_get_enabled_mask(smu, &feature_enabled);
2024
2025 if (ret)
2026 return false;
2027
2028 return !!(feature_enabled & SMC_DPM_FEATURE);
2029 }
2030
smu_v13_0_6_request_i2c_xfer(struct smu_context * smu,void * table_data)2031 static int smu_v13_0_6_request_i2c_xfer(struct smu_context *smu,
2032 void *table_data)
2033 {
2034 struct smu_table_context *smu_table = &smu->smu_table;
2035 struct smu_table *table = &smu_table->driver_table;
2036 struct amdgpu_device *adev = smu->adev;
2037 uint32_t table_size;
2038 int ret = 0;
2039
2040 if (!table_data)
2041 return -EINVAL;
2042
2043 table_size = smu_table->tables[SMU_TABLE_I2C_COMMANDS].size;
2044
2045 memcpy(table->cpu_addr, table_data, table_size);
2046 /* Flush hdp cache */
2047 amdgpu_asic_flush_hdp(adev, NULL);
2048 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_RequestI2cTransaction,
2049 NULL);
2050
2051 return ret;
2052 }
2053
smu_v13_0_6_i2c_xfer(struct i2c_adapter * i2c_adap,struct i2c_msg * msg,int num_msgs)2054 static int smu_v13_0_6_i2c_xfer(struct i2c_adapter *i2c_adap,
2055 struct i2c_msg *msg, int num_msgs)
2056 {
2057 struct amdgpu_smu_i2c_bus *smu_i2c = i2c_get_adapdata(i2c_adap);
2058 struct amdgpu_device *adev = smu_i2c->adev;
2059 struct smu_context *smu = adev->powerplay.pp_handle;
2060 struct smu_table_context *smu_table = &smu->smu_table;
2061 struct smu_table *table = &smu_table->driver_table;
2062 SwI2cRequest_t *req, *res = (SwI2cRequest_t *)table->cpu_addr;
2063 int i, j, r, c;
2064 u16 dir;
2065
2066 if (!adev->pm.dpm_enabled)
2067 return -EBUSY;
2068
2069 req = kzalloc(sizeof(*req), GFP_KERNEL);
2070 if (!req)
2071 return -ENOMEM;
2072
2073 req->I2CcontrollerPort = smu_i2c->port;
2074 req->I2CSpeed = I2C_SPEED_FAST_400K;
2075 req->SlaveAddress = msg[0].addr << 1; /* wants an 8-bit address */
2076 dir = msg[0].flags & I2C_M_RD;
2077
2078 for (c = i = 0; i < num_msgs; i++) {
2079 for (j = 0; j < msg[i].len; j++, c++) {
2080 SwI2cCmd_t *cmd = &req->SwI2cCmds[c];
2081
2082 if (!(msg[i].flags & I2C_M_RD)) {
2083 /* write */
2084 cmd->CmdConfig |= CMDCONFIG_READWRITE_MASK;
2085 cmd->ReadWriteData = msg[i].buf[j];
2086 }
2087
2088 if ((dir ^ msg[i].flags) & I2C_M_RD) {
2089 /* The direction changes.
2090 */
2091 dir = msg[i].flags & I2C_M_RD;
2092 cmd->CmdConfig |= CMDCONFIG_RESTART_MASK;
2093 }
2094
2095 req->NumCmds++;
2096
2097 /*
2098 * Insert STOP if we are at the last byte of either last
2099 * message for the transaction or the client explicitly
2100 * requires a STOP at this particular message.
2101 */
2102 if ((j == msg[i].len - 1) &&
2103 ((i == num_msgs - 1) || (msg[i].flags & I2C_M_STOP))) {
2104 cmd->CmdConfig &= ~CMDCONFIG_RESTART_MASK;
2105 cmd->CmdConfig |= CMDCONFIG_STOP_MASK;
2106 }
2107 }
2108 }
2109 mutex_lock(&adev->pm.mutex);
2110 r = smu_v13_0_6_request_i2c_xfer(smu, req);
2111 if (r) {
2112 /* Retry once, in case of an i2c collision */
2113 r = smu_v13_0_6_request_i2c_xfer(smu, req);
2114 if (r)
2115 goto fail;
2116 }
2117
2118 for (c = i = 0; i < num_msgs; i++) {
2119 if (!(msg[i].flags & I2C_M_RD)) {
2120 c += msg[i].len;
2121 continue;
2122 }
2123 for (j = 0; j < msg[i].len; j++, c++) {
2124 SwI2cCmd_t *cmd = &res->SwI2cCmds[c];
2125
2126 msg[i].buf[j] = cmd->ReadWriteData;
2127 }
2128 }
2129 r = num_msgs;
2130 fail:
2131 mutex_unlock(&adev->pm.mutex);
2132 kfree(req);
2133 return r;
2134 }
2135
smu_v13_0_6_i2c_func(struct i2c_adapter * adap)2136 static u32 smu_v13_0_6_i2c_func(struct i2c_adapter *adap)
2137 {
2138 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
2139 }
2140
2141 static const struct i2c_algorithm smu_v13_0_6_i2c_algo = {
2142 .master_xfer = smu_v13_0_6_i2c_xfer,
2143 .functionality = smu_v13_0_6_i2c_func,
2144 };
2145
2146 static const struct i2c_adapter_quirks smu_v13_0_6_i2c_control_quirks = {
2147 .flags = I2C_AQ_COMB | I2C_AQ_COMB_SAME_ADDR | I2C_AQ_NO_ZERO_LEN,
2148 .max_read_len = MAX_SW_I2C_COMMANDS,
2149 .max_write_len = MAX_SW_I2C_COMMANDS,
2150 .max_comb_1st_msg_len = 2,
2151 .max_comb_2nd_msg_len = MAX_SW_I2C_COMMANDS - 2,
2152 };
2153
smu_v13_0_6_i2c_control_init(struct smu_context * smu)2154 static int smu_v13_0_6_i2c_control_init(struct smu_context *smu)
2155 {
2156 struct amdgpu_device *adev = smu->adev;
2157 int res, i;
2158
2159 for (i = 0; i < MAX_SMU_I2C_BUSES; i++) {
2160 struct amdgpu_smu_i2c_bus *smu_i2c = &adev->pm.smu_i2c[i];
2161 struct i2c_adapter *control = &smu_i2c->adapter;
2162
2163 smu_i2c->adev = adev;
2164 smu_i2c->port = i;
2165 mutex_init(&smu_i2c->mutex);
2166 control->owner = THIS_MODULE;
2167 control->dev.parent = &adev->pdev->dev;
2168 control->algo = &smu_v13_0_6_i2c_algo;
2169 snprintf(control->name, sizeof(control->name), "AMDGPU SMU %d", i);
2170 control->quirks = &smu_v13_0_6_i2c_control_quirks;
2171 i2c_set_adapdata(control, smu_i2c);
2172
2173 res = i2c_add_adapter(control);
2174 if (res) {
2175 DRM_ERROR("Failed to register hw i2c, err: %d\n", res);
2176 goto Out_err;
2177 }
2178 }
2179
2180 adev->pm.ras_eeprom_i2c_bus = &adev->pm.smu_i2c[0].adapter;
2181 adev->pm.fru_eeprom_i2c_bus = &adev->pm.smu_i2c[0].adapter;
2182
2183 return 0;
2184 Out_err:
2185 for ( ; i >= 0; i--) {
2186 struct amdgpu_smu_i2c_bus *smu_i2c = &adev->pm.smu_i2c[i];
2187 struct i2c_adapter *control = &smu_i2c->adapter;
2188
2189 i2c_del_adapter(control);
2190 }
2191 return res;
2192 }
2193
smu_v13_0_6_i2c_control_fini(struct smu_context * smu)2194 static void smu_v13_0_6_i2c_control_fini(struct smu_context *smu)
2195 {
2196 struct amdgpu_device *adev = smu->adev;
2197 int i;
2198
2199 for (i = 0; i < MAX_SMU_I2C_BUSES; i++) {
2200 struct amdgpu_smu_i2c_bus *smu_i2c = &adev->pm.smu_i2c[i];
2201 struct i2c_adapter *control = &smu_i2c->adapter;
2202
2203 i2c_del_adapter(control);
2204 }
2205 adev->pm.ras_eeprom_i2c_bus = NULL;
2206 adev->pm.fru_eeprom_i2c_bus = NULL;
2207 }
2208
smu_v13_0_6_get_unique_id(struct smu_context * smu)2209 static void smu_v13_0_6_get_unique_id(struct smu_context *smu)
2210 {
2211 struct amdgpu_device *adev = smu->adev;
2212 struct smu_table_context *smu_table = &smu->smu_table;
2213 struct PPTable_t *pptable =
2214 (struct PPTable_t *)smu_table->driver_pptable;
2215
2216 adev->unique_id = pptable->PublicSerialNumber_AID;
2217 }
2218
smu_v13_0_6_get_bamaco_support(struct smu_context * smu)2219 static int smu_v13_0_6_get_bamaco_support(struct smu_context *smu)
2220 {
2221 /* smu_13_0_6 does not support baco */
2222
2223 return 0;
2224 }
2225
2226 static const char *const throttling_logging_label[] = {
2227 [THROTTLER_PROCHOT_BIT] = "Prochot",
2228 [THROTTLER_PPT_BIT] = "PPT",
2229 [THROTTLER_THERMAL_SOCKET_BIT] = "SOC",
2230 [THROTTLER_THERMAL_VR_BIT] = "VR",
2231 [THROTTLER_THERMAL_HBM_BIT] = "HBM"
2232 };
2233
smu_v13_0_6_log_thermal_throttling_event(struct smu_context * smu)2234 static void smu_v13_0_6_log_thermal_throttling_event(struct smu_context *smu)
2235 {
2236 int throttler_idx, throttling_events = 0, buf_idx = 0;
2237 struct amdgpu_device *adev = smu->adev;
2238 uint32_t throttler_status;
2239 char log_buf[256];
2240
2241 throttler_status = smu_v13_0_6_get_throttler_status(smu);
2242 if (!throttler_status)
2243 return;
2244
2245 memset(log_buf, 0, sizeof(log_buf));
2246 for (throttler_idx = 0;
2247 throttler_idx < ARRAY_SIZE(throttling_logging_label);
2248 throttler_idx++) {
2249 if (throttler_status & (1U << throttler_idx)) {
2250 throttling_events++;
2251 buf_idx += snprintf(
2252 log_buf + buf_idx, sizeof(log_buf) - buf_idx,
2253 "%s%s", throttling_events > 1 ? " and " : "",
2254 throttling_logging_label[throttler_idx]);
2255 if (buf_idx >= sizeof(log_buf)) {
2256 dev_err(adev->dev, "buffer overflow!\n");
2257 log_buf[sizeof(log_buf) - 1] = '\0';
2258 break;
2259 }
2260 }
2261 }
2262
2263 dev_warn(adev->dev,
2264 "WARN: GPU is throttled, expect performance decrease. %s.\n",
2265 log_buf);
2266 kgd2kfd_smi_event_throttle(
2267 smu->adev->kfd.dev,
2268 smu_cmn_get_indep_throttler_status(throttler_status,
2269 smu_v13_0_6_throttler_map));
2270 }
2271
2272 static int
smu_v13_0_6_get_current_pcie_link_width_level(struct smu_context * smu)2273 smu_v13_0_6_get_current_pcie_link_width_level(struct smu_context *smu)
2274 {
2275 struct amdgpu_device *adev = smu->adev;
2276
2277 return REG_GET_FIELD(RREG32_PCIE(smnPCIE_LC_LINK_WIDTH_CNTL),
2278 PCIE_LC_LINK_WIDTH_CNTL, LC_LINK_WIDTH_RD);
2279 }
2280
smu_v13_0_6_get_current_pcie_link_speed(struct smu_context * smu)2281 static int smu_v13_0_6_get_current_pcie_link_speed(struct smu_context *smu)
2282 {
2283 struct amdgpu_device *adev = smu->adev;
2284 uint32_t speed_level;
2285 uint32_t esm_ctrl;
2286
2287 /* TODO: confirm this on real target */
2288 esm_ctrl = RREG32_PCIE(smnPCIE_ESM_CTRL);
2289 if ((esm_ctrl >> 15) & 0x1)
2290 return (((esm_ctrl >> 8) & 0x7F) + 128);
2291
2292 speed_level = (RREG32_PCIE(smnPCIE_LC_SPEED_CNTL) &
2293 PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK)
2294 >> PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT;
2295 if (speed_level > LINK_SPEED_MAX)
2296 speed_level = 0;
2297
2298 return pcie_gen_to_speed(speed_level + 1);
2299 }
2300
smu_v13_0_6_get_gpu_metrics(struct smu_context * smu,void ** table)2301 static ssize_t smu_v13_0_6_get_gpu_metrics(struct smu_context *smu, void **table)
2302 {
2303 struct smu_table_context *smu_table = &smu->smu_table;
2304 struct gpu_metrics_v1_5 *gpu_metrics =
2305 (struct gpu_metrics_v1_5 *)smu_table->gpu_metrics_table;
2306 struct amdgpu_device *adev = smu->adev;
2307 int ret = 0, xcc_id, inst, i, j;
2308 MetricsTableX_t *metrics_x;
2309 MetricsTableA_t *metrics_a;
2310 u16 link_width_level;
2311
2312 metrics_x = kzalloc(max(sizeof(MetricsTableX_t), sizeof(MetricsTableA_t)), GFP_KERNEL);
2313 ret = smu_v13_0_6_get_metrics_table(smu, metrics_x, true);
2314 if (ret) {
2315 kfree(metrics_x);
2316 return ret;
2317 }
2318
2319 metrics_a = (MetricsTableA_t *)metrics_x;
2320
2321 smu_cmn_init_soft_gpu_metrics(gpu_metrics, 1, 5);
2322
2323 gpu_metrics->temperature_hotspot =
2324 SMUQ10_ROUND(GET_METRIC_FIELD(MaxSocketTemperature));
2325 /* Individual HBM stack temperature is not reported */
2326 gpu_metrics->temperature_mem =
2327 SMUQ10_ROUND(GET_METRIC_FIELD(MaxHbmTemperature));
2328 /* Reports max temperature of all voltage rails */
2329 gpu_metrics->temperature_vrsoc =
2330 SMUQ10_ROUND(GET_METRIC_FIELD(MaxVrTemperature));
2331
2332 gpu_metrics->average_gfx_activity =
2333 SMUQ10_ROUND(GET_METRIC_FIELD(SocketGfxBusy));
2334 gpu_metrics->average_umc_activity =
2335 SMUQ10_ROUND(GET_METRIC_FIELD(DramBandwidthUtilization));
2336
2337 gpu_metrics->curr_socket_power =
2338 SMUQ10_ROUND(GET_METRIC_FIELD(SocketPower));
2339 /* Energy counter reported in 15.259uJ (2^-16) units */
2340 gpu_metrics->energy_accumulator = GET_METRIC_FIELD(SocketEnergyAcc);
2341
2342 for (i = 0; i < MAX_GFX_CLKS; i++) {
2343 xcc_id = GET_INST(GC, i);
2344 if (xcc_id >= 0)
2345 gpu_metrics->current_gfxclk[i] =
2346 SMUQ10_ROUND(GET_METRIC_FIELD(GfxclkFrequency)[xcc_id]);
2347
2348 if (i < MAX_CLKS) {
2349 gpu_metrics->current_socclk[i] =
2350 SMUQ10_ROUND(GET_METRIC_FIELD(SocclkFrequency)[i]);
2351 inst = GET_INST(VCN, i);
2352 if (inst >= 0) {
2353 gpu_metrics->current_vclk0[i] =
2354 SMUQ10_ROUND(GET_METRIC_FIELD(VclkFrequency)[inst]);
2355 gpu_metrics->current_dclk0[i] =
2356 SMUQ10_ROUND(GET_METRIC_FIELD(DclkFrequency)[inst]);
2357 }
2358 }
2359 }
2360
2361 gpu_metrics->current_uclk = SMUQ10_ROUND(GET_METRIC_FIELD(UclkFrequency));
2362
2363 /* Throttle status is not reported through metrics now */
2364 gpu_metrics->throttle_status = 0;
2365
2366 /* Clock Lock Status. Each bit corresponds to each GFXCLK instance */
2367 gpu_metrics->gfxclk_lock_status = GET_METRIC_FIELD(GfxLockXCDMak) >> GET_INST(GC, 0);
2368
2369 if (!(adev->flags & AMD_IS_APU)) {
2370 /*Check smu version, PCIE link speed and width will be reported from pmfw metric
2371 * table for both pf & one vf for smu version 85.99.0 or higher else report only
2372 * for pf from registers
2373 */
2374 if (smu->smc_fw_version >= 0x556300) {
2375 gpu_metrics->pcie_link_width = metrics_x->PCIeLinkWidth;
2376 gpu_metrics->pcie_link_speed =
2377 pcie_gen_to_speed(metrics_x->PCIeLinkSpeed);
2378 } else if (!amdgpu_sriov_vf(adev)) {
2379 link_width_level = smu_v13_0_6_get_current_pcie_link_width_level(smu);
2380 if (link_width_level > MAX_LINK_WIDTH)
2381 link_width_level = 0;
2382
2383 gpu_metrics->pcie_link_width =
2384 DECODE_LANE_WIDTH(link_width_level);
2385 gpu_metrics->pcie_link_speed =
2386 smu_v13_0_6_get_current_pcie_link_speed(smu);
2387 }
2388
2389 gpu_metrics->pcie_bandwidth_acc =
2390 SMUQ10_ROUND(metrics_x->PcieBandwidthAcc[0]);
2391 gpu_metrics->pcie_bandwidth_inst =
2392 SMUQ10_ROUND(metrics_x->PcieBandwidth[0]);
2393 gpu_metrics->pcie_l0_to_recov_count_acc =
2394 metrics_x->PCIeL0ToRecoveryCountAcc;
2395 gpu_metrics->pcie_replay_count_acc =
2396 metrics_x->PCIenReplayAAcc;
2397 gpu_metrics->pcie_replay_rover_count_acc =
2398 metrics_x->PCIenReplayARolloverCountAcc;
2399 gpu_metrics->pcie_nak_sent_count_acc =
2400 metrics_x->PCIeNAKSentCountAcc;
2401 gpu_metrics->pcie_nak_rcvd_count_acc =
2402 metrics_x->PCIeNAKReceivedCountAcc;
2403 }
2404
2405 gpu_metrics->system_clock_counter = ktime_get_boottime_ns();
2406
2407 gpu_metrics->gfx_activity_acc =
2408 SMUQ10_ROUND(GET_METRIC_FIELD(SocketGfxBusyAcc));
2409 gpu_metrics->mem_activity_acc =
2410 SMUQ10_ROUND(GET_METRIC_FIELD(DramBandwidthUtilizationAcc));
2411
2412 for (i = 0; i < NUM_XGMI_LINKS; i++) {
2413 gpu_metrics->xgmi_read_data_acc[i] =
2414 SMUQ10_ROUND(GET_METRIC_FIELD(XgmiReadDataSizeAcc)[i]);
2415 gpu_metrics->xgmi_write_data_acc[i] =
2416 SMUQ10_ROUND(GET_METRIC_FIELD(XgmiWriteDataSizeAcc)[i]);
2417 }
2418
2419 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) {
2420 inst = GET_INST(JPEG, i);
2421 for (j = 0; j < adev->jpeg.num_jpeg_rings; ++j) {
2422 gpu_metrics->jpeg_activity[(i * adev->jpeg.num_jpeg_rings) + j] =
2423 SMUQ10_ROUND(GET_METRIC_FIELD(JpegBusy)
2424 [(inst * adev->jpeg.num_jpeg_rings) + j]);
2425 }
2426 }
2427
2428 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
2429 inst = GET_INST(VCN, i);
2430 gpu_metrics->vcn_activity[i] =
2431 SMUQ10_ROUND(GET_METRIC_FIELD(VcnBusy)[inst]);
2432 }
2433
2434 gpu_metrics->xgmi_link_width = SMUQ10_ROUND(GET_METRIC_FIELD(XgmiWidth));
2435 gpu_metrics->xgmi_link_speed = SMUQ10_ROUND(GET_METRIC_FIELD(XgmiBitrate));
2436
2437 gpu_metrics->firmware_timestamp = GET_METRIC_FIELD(Timestamp);
2438
2439 *table = (void *)gpu_metrics;
2440 kfree(metrics_x);
2441
2442 return sizeof(*gpu_metrics);
2443 }
2444
smu_v13_0_6_restore_pci_config(struct smu_context * smu)2445 static void smu_v13_0_6_restore_pci_config(struct smu_context *smu)
2446 {
2447 struct amdgpu_device *adev = smu->adev;
2448 int i;
2449
2450 for (i = 0; i < 16; i++)
2451 pci_write_config_dword(adev->pdev, i * 4,
2452 adev->pdev->saved_config_space[i]);
2453 pci_restore_msi_state(adev->pdev);
2454 }
2455
smu_v13_0_6_mode2_reset(struct smu_context * smu)2456 static int smu_v13_0_6_mode2_reset(struct smu_context *smu)
2457 {
2458 int ret = 0, index;
2459 struct amdgpu_device *adev = smu->adev;
2460 int timeout = 10;
2461
2462 index = smu_cmn_to_asic_specific_index(smu, CMN2ASIC_MAPPING_MSG,
2463 SMU_MSG_GfxDeviceDriverReset);
2464 if (index < 0)
2465 return index;
2466
2467 mutex_lock(&smu->message_lock);
2468
2469 ret = smu_cmn_send_msg_without_waiting(smu, (uint16_t)index,
2470 SMU_RESET_MODE_2);
2471
2472 /* Reset takes a bit longer, wait for 200ms. */
2473 msleep(200);
2474
2475 dev_dbg(smu->adev->dev, "restore config space...\n");
2476 /* Restore the config space saved during init */
2477 amdgpu_device_load_pci_state(adev->pdev);
2478
2479 /* Certain platforms have switches which assign virtual BAR values to
2480 * devices. OS uses the virtual BAR values and device behind the switch
2481 * is assgined another BAR value. When device's config space registers
2482 * are queried, switch returns the virtual BAR values. When mode-2 reset
2483 * is performed, switch is unaware of it, and will continue to return
2484 * the same virtual values to the OS.This affects
2485 * pci_restore_config_space() API as it doesn't write the value saved if
2486 * the current value read from config space is the same as what is
2487 * saved. As a workaround, make sure the config space is restored
2488 * always.
2489 */
2490 if (!(adev->flags & AMD_IS_APU))
2491 smu_v13_0_6_restore_pci_config(smu);
2492
2493 dev_dbg(smu->adev->dev, "wait for reset ack\n");
2494 do {
2495 ret = smu_cmn_wait_for_response(smu);
2496 /* Wait a bit more time for getting ACK */
2497 if (ret == -ETIME) {
2498 --timeout;
2499 usleep_range(500, 1000);
2500 continue;
2501 }
2502
2503 if (ret)
2504 goto out;
2505
2506 } while (ret == -ETIME && timeout);
2507
2508 out:
2509 mutex_unlock(&smu->message_lock);
2510
2511 if (ret)
2512 dev_err(adev->dev, "failed to send mode2 reset, error code %d",
2513 ret);
2514
2515 return ret;
2516 }
2517
smu_v13_0_6_get_thermal_temperature_range(struct smu_context * smu,struct smu_temperature_range * range)2518 static int smu_v13_0_6_get_thermal_temperature_range(struct smu_context *smu,
2519 struct smu_temperature_range *range)
2520 {
2521 struct amdgpu_device *adev = smu->adev;
2522 u32 aid_temp, xcd_temp, max_temp;
2523 u32 ccd_temp = 0;
2524 int ret;
2525
2526 if (amdgpu_sriov_vf(smu->adev))
2527 return 0;
2528
2529 if (!range)
2530 return -EINVAL;
2531
2532 /*Check smu version, GetCtfLimit message only supported for smu version 85.69 or higher */
2533 if (smu->smc_fw_version < 0x554500)
2534 return 0;
2535
2536 /* Get SOC Max operating temperature */
2537 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetCTFLimit,
2538 PPSMC_AID_THM_TYPE, &aid_temp);
2539 if (ret)
2540 goto failed;
2541 if (adev->flags & AMD_IS_APU) {
2542 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetCTFLimit,
2543 PPSMC_CCD_THM_TYPE, &ccd_temp);
2544 if (ret)
2545 goto failed;
2546 }
2547 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetCTFLimit,
2548 PPSMC_XCD_THM_TYPE, &xcd_temp);
2549 if (ret)
2550 goto failed;
2551 range->hotspot_emergency_max = max3(aid_temp, xcd_temp, ccd_temp) *
2552 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
2553
2554 /* Get HBM Max operating temperature */
2555 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetCTFLimit,
2556 PPSMC_HBM_THM_TYPE, &max_temp);
2557 if (ret)
2558 goto failed;
2559 range->mem_emergency_max =
2560 max_temp * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
2561
2562 /* Get SOC thermal throttle limit */
2563 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetThermalLimit,
2564 PPSMC_THROTTLING_LIMIT_TYPE_SOCKET,
2565 &max_temp);
2566 if (ret)
2567 goto failed;
2568 range->hotspot_crit_max =
2569 max_temp * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
2570
2571 /* Get HBM thermal throttle limit */
2572 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetThermalLimit,
2573 PPSMC_THROTTLING_LIMIT_TYPE_HBM,
2574 &max_temp);
2575 if (ret)
2576 goto failed;
2577
2578 range->mem_crit_max = max_temp * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
2579
2580 failed:
2581 return ret;
2582 }
2583
smu_v13_0_6_mode1_reset(struct smu_context * smu)2584 static int smu_v13_0_6_mode1_reset(struct smu_context *smu)
2585 {
2586 struct amdgpu_device *adev = smu->adev;
2587 u32 fatal_err, param;
2588 int ret = 0;
2589
2590 fatal_err = 0;
2591 param = SMU_RESET_MODE_1;
2592
2593 /* fatal error triggered by ras, PMFW supports the flag */
2594 if (amdgpu_ras_get_fed_status(adev))
2595 fatal_err = 1;
2596
2597 param |= (fatal_err << 16);
2598 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GfxDeviceDriverReset,
2599 param, NULL);
2600
2601 if (!ret)
2602 msleep(SMU13_MODE1_RESET_WAIT_TIME_IN_MS);
2603
2604 return ret;
2605 }
2606
smu_v13_0_6_is_mode1_reset_supported(struct smu_context * smu)2607 static bool smu_v13_0_6_is_mode1_reset_supported(struct smu_context *smu)
2608 {
2609 return true;
2610 }
2611
smu_v13_0_6_is_mode2_reset_supported(struct smu_context * smu)2612 static bool smu_v13_0_6_is_mode2_reset_supported(struct smu_context *smu)
2613 {
2614 return true;
2615 }
2616
smu_v13_0_6_smu_send_hbm_bad_page_num(struct smu_context * smu,uint32_t size)2617 static int smu_v13_0_6_smu_send_hbm_bad_page_num(struct smu_context *smu,
2618 uint32_t size)
2619 {
2620 int ret = 0;
2621
2622 /* message SMU to update the bad page number on SMUBUS */
2623 ret = smu_cmn_send_smc_msg_with_param(
2624 smu, SMU_MSG_SetNumBadHbmPagesRetired, size, NULL);
2625 if (ret)
2626 dev_err(smu->adev->dev,
2627 "[%s] failed to message SMU to update HBM bad pages number\n",
2628 __func__);
2629
2630 return ret;
2631 }
2632
smu_v13_0_6_send_rma_reason(struct smu_context * smu)2633 static int smu_v13_0_6_send_rma_reason(struct smu_context *smu)
2634 {
2635 struct amdgpu_device *adev = smu->adev;
2636 int ret;
2637
2638 /* NOTE: the message is only valid on dGPU with pmfw 85.90.0 and above */
2639 if ((adev->flags & AMD_IS_APU) || smu->smc_fw_version < 0x00555a00)
2640 return 0;
2641
2642 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_RmaDueToBadPageThreshold, NULL);
2643 if (ret)
2644 dev_err(smu->adev->dev,
2645 "[%s] failed to send BadPageThreshold event to SMU\n",
2646 __func__);
2647
2648 return ret;
2649 }
2650
mca_smu_set_debug_mode(struct amdgpu_device * adev,bool enable)2651 static int mca_smu_set_debug_mode(struct amdgpu_device *adev, bool enable)
2652 {
2653 struct smu_context *smu = adev->powerplay.pp_handle;
2654
2655 return smu_v13_0_6_mca_set_debug_mode(smu, enable);
2656 }
2657
smu_v13_0_6_get_valid_mca_count(struct smu_context * smu,enum amdgpu_mca_error_type type,uint32_t * count)2658 static int smu_v13_0_6_get_valid_mca_count(struct smu_context *smu, enum amdgpu_mca_error_type type, uint32_t *count)
2659 {
2660 uint32_t msg;
2661 int ret;
2662
2663 if (!count)
2664 return -EINVAL;
2665
2666 switch (type) {
2667 case AMDGPU_MCA_ERROR_TYPE_UE:
2668 msg = SMU_MSG_QueryValidMcaCount;
2669 break;
2670 case AMDGPU_MCA_ERROR_TYPE_CE:
2671 msg = SMU_MSG_QueryValidMcaCeCount;
2672 break;
2673 default:
2674 return -EINVAL;
2675 }
2676
2677 ret = smu_cmn_send_smc_msg(smu, msg, count);
2678 if (ret) {
2679 *count = 0;
2680 return ret;
2681 }
2682
2683 return 0;
2684 }
2685
__smu_v13_0_6_mca_dump_bank(struct smu_context * smu,enum amdgpu_mca_error_type type,int idx,int offset,uint32_t * val)2686 static int __smu_v13_0_6_mca_dump_bank(struct smu_context *smu, enum amdgpu_mca_error_type type,
2687 int idx, int offset, uint32_t *val)
2688 {
2689 uint32_t msg, param;
2690
2691 switch (type) {
2692 case AMDGPU_MCA_ERROR_TYPE_UE:
2693 msg = SMU_MSG_McaBankDumpDW;
2694 break;
2695 case AMDGPU_MCA_ERROR_TYPE_CE:
2696 msg = SMU_MSG_McaBankCeDumpDW;
2697 break;
2698 default:
2699 return -EINVAL;
2700 }
2701
2702 param = ((idx & 0xffff) << 16) | (offset & 0xfffc);
2703
2704 return smu_cmn_send_smc_msg_with_param(smu, msg, param, val);
2705 }
2706
smu_v13_0_6_mca_dump_bank(struct smu_context * smu,enum amdgpu_mca_error_type type,int idx,int offset,uint32_t * val,int count)2707 static int smu_v13_0_6_mca_dump_bank(struct smu_context *smu, enum amdgpu_mca_error_type type,
2708 int idx, int offset, uint32_t *val, int count)
2709 {
2710 int ret, i;
2711
2712 if (!val)
2713 return -EINVAL;
2714
2715 for (i = 0; i < count; i++) {
2716 ret = __smu_v13_0_6_mca_dump_bank(smu, type, idx, offset + (i << 2), &val[i]);
2717 if (ret)
2718 return ret;
2719 }
2720
2721 return 0;
2722 }
2723
2724 static const struct mca_bank_ipid smu_v13_0_6_mca_ipid_table[AMDGPU_MCA_IP_COUNT] = {
2725 MCA_BANK_IPID(UMC, 0x96, 0x0),
2726 MCA_BANK_IPID(SMU, 0x01, 0x1),
2727 MCA_BANK_IPID(MP5, 0x01, 0x2),
2728 MCA_BANK_IPID(PCS_XGMI, 0x50, 0x0),
2729 };
2730
mca_bank_entry_info_decode(struct mca_bank_entry * entry,struct mca_bank_info * info)2731 static void mca_bank_entry_info_decode(struct mca_bank_entry *entry, struct mca_bank_info *info)
2732 {
2733 u64 ipid = entry->regs[MCA_REG_IDX_IPID];
2734 u32 instidhi, instid;
2735
2736 /* NOTE: All MCA IPID register share the same format,
2737 * so the driver can share the MCMP1 register header file.
2738 * */
2739
2740 info->hwid = REG_GET_FIELD(ipid, MCMP1_IPIDT0, HardwareID);
2741 info->mcatype = REG_GET_FIELD(ipid, MCMP1_IPIDT0, McaType);
2742
2743 /*
2744 * Unfied DieID Format: SAASS. A:AID, S:Socket.
2745 * Unfied DieID[4] = InstanceId[0]
2746 * Unfied DieID[0:3] = InstanceIdHi[0:3]
2747 */
2748 instidhi = REG_GET_FIELD(ipid, MCMP1_IPIDT0, InstanceIdHi);
2749 instid = REG_GET_FIELD(ipid, MCMP1_IPIDT0, InstanceIdLo);
2750 info->aid = ((instidhi >> 2) & 0x03);
2751 info->socket_id = ((instid & 0x1) << 2) | (instidhi & 0x03);
2752 }
2753
mca_bank_read_reg(struct amdgpu_device * adev,enum amdgpu_mca_error_type type,int idx,int reg_idx,uint64_t * val)2754 static int mca_bank_read_reg(struct amdgpu_device *adev, enum amdgpu_mca_error_type type,
2755 int idx, int reg_idx, uint64_t *val)
2756 {
2757 struct smu_context *smu = adev->powerplay.pp_handle;
2758 uint32_t data[2] = {0, 0};
2759 int ret;
2760
2761 if (!val || reg_idx >= MCA_REG_IDX_COUNT)
2762 return -EINVAL;
2763
2764 ret = smu_v13_0_6_mca_dump_bank(smu, type, idx, reg_idx * 8, data, ARRAY_SIZE(data));
2765 if (ret)
2766 return ret;
2767
2768 *val = (uint64_t)data[1] << 32 | data[0];
2769
2770 dev_dbg(adev->dev, "mca read bank reg: type:%s, index: %d, reg_idx: %d, val: 0x%016llx\n",
2771 type == AMDGPU_MCA_ERROR_TYPE_UE ? "UE" : "CE", idx, reg_idx, *val);
2772
2773 return 0;
2774 }
2775
mca_get_mca_entry(struct amdgpu_device * adev,enum amdgpu_mca_error_type type,int idx,struct mca_bank_entry * entry)2776 static int mca_get_mca_entry(struct amdgpu_device *adev, enum amdgpu_mca_error_type type,
2777 int idx, struct mca_bank_entry *entry)
2778 {
2779 int i, ret;
2780
2781 /* NOTE: populated all mca register by default */
2782 for (i = 0; i < ARRAY_SIZE(entry->regs); i++) {
2783 ret = mca_bank_read_reg(adev, type, idx, i, &entry->regs[i]);
2784 if (ret)
2785 return ret;
2786 }
2787
2788 entry->idx = idx;
2789 entry->type = type;
2790
2791 mca_bank_entry_info_decode(entry, &entry->info);
2792
2793 return 0;
2794 }
2795
mca_decode_ipid_to_hwip(uint64_t val)2796 static int mca_decode_ipid_to_hwip(uint64_t val)
2797 {
2798 const struct mca_bank_ipid *ipid;
2799 uint16_t hwid, mcatype;
2800 int i;
2801
2802 hwid = REG_GET_FIELD(val, MCMP1_IPIDT0, HardwareID);
2803 mcatype = REG_GET_FIELD(val, MCMP1_IPIDT0, McaType);
2804
2805 for (i = 0; i < ARRAY_SIZE(smu_v13_0_6_mca_ipid_table); i++) {
2806 ipid = &smu_v13_0_6_mca_ipid_table[i];
2807
2808 if (!ipid->hwid)
2809 continue;
2810
2811 if (ipid->hwid == hwid && ipid->mcatype == mcatype)
2812 return i;
2813 }
2814
2815 return AMDGPU_MCA_IP_UNKNOW;
2816 }
2817
mca_umc_mca_get_err_count(const struct mca_ras_info * mca_ras,struct amdgpu_device * adev,enum amdgpu_mca_error_type type,struct mca_bank_entry * entry,uint32_t * count)2818 static int mca_umc_mca_get_err_count(const struct mca_ras_info *mca_ras, struct amdgpu_device *adev,
2819 enum amdgpu_mca_error_type type, struct mca_bank_entry *entry, uint32_t *count)
2820 {
2821 uint64_t status0;
2822 uint32_t ext_error_code;
2823 uint32_t odecc_err_cnt;
2824
2825 status0 = entry->regs[MCA_REG_IDX_STATUS];
2826 ext_error_code = MCA_REG__STATUS__ERRORCODEEXT(status0);
2827 odecc_err_cnt = MCA_REG__MISC0__ERRCNT(entry->regs[MCA_REG_IDX_MISC0]);
2828
2829 if (!REG_GET_FIELD(status0, MCMP1_STATUST0, Val)) {
2830 *count = 0;
2831 return 0;
2832 }
2833
2834 if (umc_v12_0_is_deferred_error(adev, status0) ||
2835 umc_v12_0_is_uncorrectable_error(adev, status0) ||
2836 umc_v12_0_is_correctable_error(adev, status0))
2837 *count = (ext_error_code == 0) ? odecc_err_cnt : 1;
2838
2839 amdgpu_umc_update_ecc_status(adev,
2840 entry->regs[MCA_REG_IDX_STATUS],
2841 entry->regs[MCA_REG_IDX_IPID],
2842 entry->regs[MCA_REG_IDX_ADDR]);
2843
2844 return 0;
2845 }
2846
mca_pcs_xgmi_mca_get_err_count(const struct mca_ras_info * mca_ras,struct amdgpu_device * adev,enum amdgpu_mca_error_type type,struct mca_bank_entry * entry,uint32_t * count)2847 static int mca_pcs_xgmi_mca_get_err_count(const struct mca_ras_info *mca_ras, struct amdgpu_device *adev,
2848 enum amdgpu_mca_error_type type, struct mca_bank_entry *entry,
2849 uint32_t *count)
2850 {
2851 u32 ext_error_code;
2852 u32 err_cnt;
2853
2854 ext_error_code = MCA_REG__STATUS__ERRORCODEEXT(entry->regs[MCA_REG_IDX_STATUS]);
2855 err_cnt = MCA_REG__MISC0__ERRCNT(entry->regs[MCA_REG_IDX_MISC0]);
2856
2857 if (type == AMDGPU_MCA_ERROR_TYPE_UE &&
2858 (ext_error_code == 0 || ext_error_code == 9))
2859 *count = err_cnt;
2860 else if (type == AMDGPU_MCA_ERROR_TYPE_CE && ext_error_code == 6)
2861 *count = err_cnt;
2862
2863 return 0;
2864 }
2865
mca_smu_check_error_code(struct amdgpu_device * adev,const struct mca_ras_info * mca_ras,uint32_t errcode)2866 static bool mca_smu_check_error_code(struct amdgpu_device *adev, const struct mca_ras_info *mca_ras,
2867 uint32_t errcode)
2868 {
2869 int i;
2870
2871 if (!mca_ras->err_code_count || !mca_ras->err_code_array)
2872 return true;
2873
2874 for (i = 0; i < mca_ras->err_code_count; i++) {
2875 if (errcode == mca_ras->err_code_array[i])
2876 return true;
2877 }
2878
2879 return false;
2880 }
2881
mca_gfx_mca_get_err_count(const struct mca_ras_info * mca_ras,struct amdgpu_device * adev,enum amdgpu_mca_error_type type,struct mca_bank_entry * entry,uint32_t * count)2882 static int mca_gfx_mca_get_err_count(const struct mca_ras_info *mca_ras, struct amdgpu_device *adev,
2883 enum amdgpu_mca_error_type type, struct mca_bank_entry *entry, uint32_t *count)
2884 {
2885 uint64_t status0, misc0;
2886
2887 status0 = entry->regs[MCA_REG_IDX_STATUS];
2888 if (!REG_GET_FIELD(status0, MCMP1_STATUST0, Val)) {
2889 *count = 0;
2890 return 0;
2891 }
2892
2893 if (type == AMDGPU_MCA_ERROR_TYPE_UE &&
2894 REG_GET_FIELD(status0, MCMP1_STATUST0, UC) == 1 &&
2895 REG_GET_FIELD(status0, MCMP1_STATUST0, PCC) == 1) {
2896 *count = 1;
2897 return 0;
2898 } else {
2899 misc0 = entry->regs[MCA_REG_IDX_MISC0];
2900 *count = REG_GET_FIELD(misc0, MCMP1_MISC0T0, ErrCnt);
2901 }
2902
2903 return 0;
2904 }
2905
mca_smu_mca_get_err_count(const struct mca_ras_info * mca_ras,struct amdgpu_device * adev,enum amdgpu_mca_error_type type,struct mca_bank_entry * entry,uint32_t * count)2906 static int mca_smu_mca_get_err_count(const struct mca_ras_info *mca_ras, struct amdgpu_device *adev,
2907 enum amdgpu_mca_error_type type, struct mca_bank_entry *entry, uint32_t *count)
2908 {
2909 uint64_t status0, misc0;
2910
2911 status0 = entry->regs[MCA_REG_IDX_STATUS];
2912 if (!REG_GET_FIELD(status0, MCMP1_STATUST0, Val)) {
2913 *count = 0;
2914 return 0;
2915 }
2916
2917 if (type == AMDGPU_MCA_ERROR_TYPE_UE &&
2918 REG_GET_FIELD(status0, MCMP1_STATUST0, UC) == 1 &&
2919 REG_GET_FIELD(status0, MCMP1_STATUST0, PCC) == 1) {
2920 if (count)
2921 *count = 1;
2922 return 0;
2923 }
2924
2925 misc0 = entry->regs[MCA_REG_IDX_MISC0];
2926 *count = REG_GET_FIELD(misc0, MCMP1_MISC0T0, ErrCnt);
2927
2928 return 0;
2929 }
2930
mca_gfx_smu_bank_is_valid(const struct mca_ras_info * mca_ras,struct amdgpu_device * adev,enum amdgpu_mca_error_type type,struct mca_bank_entry * entry)2931 static bool mca_gfx_smu_bank_is_valid(const struct mca_ras_info *mca_ras, struct amdgpu_device *adev,
2932 enum amdgpu_mca_error_type type, struct mca_bank_entry *entry)
2933 {
2934 uint32_t instlo;
2935
2936 instlo = REG_GET_FIELD(entry->regs[MCA_REG_IDX_IPID], MCMP1_IPIDT0, InstanceIdLo);
2937 instlo &= GENMASK(31, 1);
2938 switch (instlo) {
2939 case 0x36430400: /* SMNAID XCD 0 */
2940 case 0x38430400: /* SMNAID XCD 1 */
2941 case 0x40430400: /* SMNXCD XCD 0, NOTE: FIXME: fix this error later */
2942 return true;
2943 default:
2944 return false;
2945 }
2946
2947 return false;
2948 };
2949
mca_smu_bank_is_valid(const struct mca_ras_info * mca_ras,struct amdgpu_device * adev,enum amdgpu_mca_error_type type,struct mca_bank_entry * entry)2950 static bool mca_smu_bank_is_valid(const struct mca_ras_info *mca_ras, struct amdgpu_device *adev,
2951 enum amdgpu_mca_error_type type, struct mca_bank_entry *entry)
2952 {
2953 struct smu_context *smu = adev->powerplay.pp_handle;
2954 uint32_t errcode, instlo;
2955
2956 instlo = REG_GET_FIELD(entry->regs[MCA_REG_IDX_IPID], MCMP1_IPIDT0, InstanceIdLo);
2957 instlo &= GENMASK(31, 1);
2958 if (instlo != 0x03b30400)
2959 return false;
2960
2961 if (!(adev->flags & AMD_IS_APU) && smu->smc_fw_version >= 0x00555600) {
2962 errcode = MCA_REG__SYND__ERRORINFORMATION(entry->regs[MCA_REG_IDX_SYND]);
2963 errcode &= 0xff;
2964 } else {
2965 errcode = REG_GET_FIELD(entry->regs[MCA_REG_IDX_STATUS], MCMP1_STATUST0, ErrorCode);
2966 }
2967
2968 return mca_smu_check_error_code(adev, mca_ras, errcode);
2969 }
2970
2971 static int sdma_err_codes[] = { CODE_SDMA0, CODE_SDMA1, CODE_SDMA2, CODE_SDMA3 };
2972 static int mmhub_err_codes[] = {
2973 CODE_DAGB0, CODE_DAGB0 + 1, CODE_DAGB0 + 2, CODE_DAGB0 + 3, CODE_DAGB0 + 4, /* DAGB0-4 */
2974 CODE_EA0, CODE_EA0 + 1, CODE_EA0 + 2, CODE_EA0 + 3, CODE_EA0 + 4, /* MMEA0-4*/
2975 CODE_VML2, CODE_VML2_WALKER, CODE_MMCANE,
2976 };
2977
2978 static const struct mca_ras_info mca_ras_table[] = {
2979 {
2980 .blkid = AMDGPU_RAS_BLOCK__UMC,
2981 .ip = AMDGPU_MCA_IP_UMC,
2982 .get_err_count = mca_umc_mca_get_err_count,
2983 }, {
2984 .blkid = AMDGPU_RAS_BLOCK__GFX,
2985 .ip = AMDGPU_MCA_IP_SMU,
2986 .get_err_count = mca_gfx_mca_get_err_count,
2987 .bank_is_valid = mca_gfx_smu_bank_is_valid,
2988 }, {
2989 .blkid = AMDGPU_RAS_BLOCK__SDMA,
2990 .ip = AMDGPU_MCA_IP_SMU,
2991 .err_code_array = sdma_err_codes,
2992 .err_code_count = ARRAY_SIZE(sdma_err_codes),
2993 .get_err_count = mca_smu_mca_get_err_count,
2994 .bank_is_valid = mca_smu_bank_is_valid,
2995 }, {
2996 .blkid = AMDGPU_RAS_BLOCK__MMHUB,
2997 .ip = AMDGPU_MCA_IP_SMU,
2998 .err_code_array = mmhub_err_codes,
2999 .err_code_count = ARRAY_SIZE(mmhub_err_codes),
3000 .get_err_count = mca_smu_mca_get_err_count,
3001 .bank_is_valid = mca_smu_bank_is_valid,
3002 }, {
3003 .blkid = AMDGPU_RAS_BLOCK__XGMI_WAFL,
3004 .ip = AMDGPU_MCA_IP_PCS_XGMI,
3005 .get_err_count = mca_pcs_xgmi_mca_get_err_count,
3006 },
3007 };
3008
mca_get_mca_ras_info(struct amdgpu_device * adev,enum amdgpu_ras_block blkid)3009 static const struct mca_ras_info *mca_get_mca_ras_info(struct amdgpu_device *adev, enum amdgpu_ras_block blkid)
3010 {
3011 int i;
3012
3013 for (i = 0; i < ARRAY_SIZE(mca_ras_table); i++) {
3014 if (mca_ras_table[i].blkid == blkid)
3015 return &mca_ras_table[i];
3016 }
3017
3018 return NULL;
3019 }
3020
mca_get_valid_mca_count(struct amdgpu_device * adev,enum amdgpu_mca_error_type type,uint32_t * count)3021 static int mca_get_valid_mca_count(struct amdgpu_device *adev, enum amdgpu_mca_error_type type, uint32_t *count)
3022 {
3023 struct smu_context *smu = adev->powerplay.pp_handle;
3024 int ret;
3025
3026 switch (type) {
3027 case AMDGPU_MCA_ERROR_TYPE_UE:
3028 case AMDGPU_MCA_ERROR_TYPE_CE:
3029 ret = smu_v13_0_6_get_valid_mca_count(smu, type, count);
3030 break;
3031 default:
3032 ret = -EINVAL;
3033 break;
3034 }
3035
3036 return ret;
3037 }
3038
mca_bank_is_valid(struct amdgpu_device * adev,const struct mca_ras_info * mca_ras,enum amdgpu_mca_error_type type,struct mca_bank_entry * entry)3039 static bool mca_bank_is_valid(struct amdgpu_device *adev, const struct mca_ras_info *mca_ras,
3040 enum amdgpu_mca_error_type type, struct mca_bank_entry *entry)
3041 {
3042 if (mca_decode_ipid_to_hwip(entry->regs[MCA_REG_IDX_IPID]) != mca_ras->ip)
3043 return false;
3044
3045 if (mca_ras->bank_is_valid)
3046 return mca_ras->bank_is_valid(mca_ras, adev, type, entry);
3047
3048 return true;
3049 }
3050
mca_smu_parse_mca_error_count(struct amdgpu_device * adev,enum amdgpu_ras_block blk,enum amdgpu_mca_error_type type,struct mca_bank_entry * entry,uint32_t * count)3051 static int mca_smu_parse_mca_error_count(struct amdgpu_device *adev, enum amdgpu_ras_block blk, enum amdgpu_mca_error_type type,
3052 struct mca_bank_entry *entry, uint32_t *count)
3053 {
3054 const struct mca_ras_info *mca_ras;
3055
3056 if (!entry || !count)
3057 return -EINVAL;
3058
3059 mca_ras = mca_get_mca_ras_info(adev, blk);
3060 if (!mca_ras)
3061 return -EOPNOTSUPP;
3062
3063 if (!mca_bank_is_valid(adev, mca_ras, type, entry)) {
3064 *count = 0;
3065 return 0;
3066 }
3067
3068 return mca_ras->get_err_count(mca_ras, adev, type, entry, count);
3069 }
3070
mca_smu_get_mca_entry(struct amdgpu_device * adev,enum amdgpu_mca_error_type type,int idx,struct mca_bank_entry * entry)3071 static int mca_smu_get_mca_entry(struct amdgpu_device *adev,
3072 enum amdgpu_mca_error_type type, int idx, struct mca_bank_entry *entry)
3073 {
3074 return mca_get_mca_entry(adev, type, idx, entry);
3075 }
3076
mca_smu_get_valid_mca_count(struct amdgpu_device * adev,enum amdgpu_mca_error_type type,uint32_t * count)3077 static int mca_smu_get_valid_mca_count(struct amdgpu_device *adev,
3078 enum amdgpu_mca_error_type type, uint32_t *count)
3079 {
3080 return mca_get_valid_mca_count(adev, type, count);
3081 }
3082
3083 static const struct amdgpu_mca_smu_funcs smu_v13_0_6_mca_smu_funcs = {
3084 .max_ue_count = 12,
3085 .max_ce_count = 12,
3086 .mca_set_debug_mode = mca_smu_set_debug_mode,
3087 .mca_parse_mca_error_count = mca_smu_parse_mca_error_count,
3088 .mca_get_mca_entry = mca_smu_get_mca_entry,
3089 .mca_get_valid_mca_count = mca_smu_get_valid_mca_count,
3090 };
3091
aca_smu_set_debug_mode(struct amdgpu_device * adev,bool enable)3092 static int aca_smu_set_debug_mode(struct amdgpu_device *adev, bool enable)
3093 {
3094 struct smu_context *smu = adev->powerplay.pp_handle;
3095
3096 return smu_v13_0_6_mca_set_debug_mode(smu, enable);
3097 }
3098
smu_v13_0_6_get_valid_aca_count(struct smu_context * smu,enum aca_smu_type type,u32 * count)3099 static int smu_v13_0_6_get_valid_aca_count(struct smu_context *smu, enum aca_smu_type type, u32 *count)
3100 {
3101 uint32_t msg;
3102 int ret;
3103
3104 if (!count)
3105 return -EINVAL;
3106
3107 switch (type) {
3108 case ACA_SMU_TYPE_UE:
3109 msg = SMU_MSG_QueryValidMcaCount;
3110 break;
3111 case ACA_SMU_TYPE_CE:
3112 msg = SMU_MSG_QueryValidMcaCeCount;
3113 break;
3114 default:
3115 return -EINVAL;
3116 }
3117
3118 ret = smu_cmn_send_smc_msg(smu, msg, count);
3119 if (ret) {
3120 *count = 0;
3121 return ret;
3122 }
3123
3124 return 0;
3125 }
3126
aca_smu_get_valid_aca_count(struct amdgpu_device * adev,enum aca_smu_type type,u32 * count)3127 static int aca_smu_get_valid_aca_count(struct amdgpu_device *adev,
3128 enum aca_smu_type type, u32 *count)
3129 {
3130 struct smu_context *smu = adev->powerplay.pp_handle;
3131 int ret;
3132
3133 switch (type) {
3134 case ACA_SMU_TYPE_UE:
3135 case ACA_SMU_TYPE_CE:
3136 ret = smu_v13_0_6_get_valid_aca_count(smu, type, count);
3137 break;
3138 default:
3139 ret = -EINVAL;
3140 break;
3141 }
3142
3143 return ret;
3144 }
3145
__smu_v13_0_6_aca_bank_dump(struct smu_context * smu,enum aca_smu_type type,int idx,int offset,u32 * val)3146 static int __smu_v13_0_6_aca_bank_dump(struct smu_context *smu, enum aca_smu_type type,
3147 int idx, int offset, u32 *val)
3148 {
3149 uint32_t msg, param;
3150
3151 switch (type) {
3152 case ACA_SMU_TYPE_UE:
3153 msg = SMU_MSG_McaBankDumpDW;
3154 break;
3155 case ACA_SMU_TYPE_CE:
3156 msg = SMU_MSG_McaBankCeDumpDW;
3157 break;
3158 default:
3159 return -EINVAL;
3160 }
3161
3162 param = ((idx & 0xffff) << 16) | (offset & 0xfffc);
3163
3164 return smu_cmn_send_smc_msg_with_param(smu, msg, param, (uint32_t *)val);
3165 }
3166
smu_v13_0_6_aca_bank_dump(struct smu_context * smu,enum aca_smu_type type,int idx,int offset,u32 * val,int count)3167 static int smu_v13_0_6_aca_bank_dump(struct smu_context *smu, enum aca_smu_type type,
3168 int idx, int offset, u32 *val, int count)
3169 {
3170 int ret, i;
3171
3172 if (!val)
3173 return -EINVAL;
3174
3175 for (i = 0; i < count; i++) {
3176 ret = __smu_v13_0_6_aca_bank_dump(smu, type, idx, offset + (i << 2), &val[i]);
3177 if (ret)
3178 return ret;
3179 }
3180
3181 return 0;
3182 }
3183
aca_bank_read_reg(struct amdgpu_device * adev,enum aca_smu_type type,int idx,int reg_idx,u64 * val)3184 static int aca_bank_read_reg(struct amdgpu_device *adev, enum aca_smu_type type,
3185 int idx, int reg_idx, u64 *val)
3186 {
3187 struct smu_context *smu = adev->powerplay.pp_handle;
3188 u32 data[2] = {0, 0};
3189 int ret;
3190
3191 if (!val || reg_idx >= ACA_REG_IDX_COUNT)
3192 return -EINVAL;
3193
3194 ret = smu_v13_0_6_aca_bank_dump(smu, type, idx, reg_idx * 8, data, ARRAY_SIZE(data));
3195 if (ret)
3196 return ret;
3197
3198 *val = (u64)data[1] << 32 | data[0];
3199
3200 dev_dbg(adev->dev, "mca read bank reg: type:%s, index: %d, reg_idx: %d, val: 0x%016llx\n",
3201 type == ACA_SMU_TYPE_UE ? "UE" : "CE", idx, reg_idx, *val);
3202
3203 return 0;
3204 }
3205
aca_smu_get_valid_aca_bank(struct amdgpu_device * adev,enum aca_smu_type type,int idx,struct aca_bank * bank)3206 static int aca_smu_get_valid_aca_bank(struct amdgpu_device *adev,
3207 enum aca_smu_type type, int idx, struct aca_bank *bank)
3208 {
3209 int i, ret, count;
3210
3211 count = min_t(int, 16, ARRAY_SIZE(bank->regs));
3212 for (i = 0; i < count; i++) {
3213 ret = aca_bank_read_reg(adev, type, idx, i, &bank->regs[i]);
3214 if (ret)
3215 return ret;
3216 }
3217
3218 return 0;
3219 }
3220
aca_smu_parse_error_code(struct amdgpu_device * adev,struct aca_bank * bank)3221 static int aca_smu_parse_error_code(struct amdgpu_device *adev, struct aca_bank *bank)
3222 {
3223 int error_code;
3224
3225 if (!(adev->flags & AMD_IS_APU) && adev->pm.fw_version >= 0x00555600)
3226 error_code = ACA_REG__SYND__ERRORINFORMATION(bank->regs[ACA_REG_IDX_SYND]);
3227 else
3228 error_code = ACA_REG__STATUS__ERRORCODE(bank->regs[ACA_REG_IDX_STATUS]);
3229
3230 return error_code & 0xff;
3231 }
3232
3233 static const struct aca_smu_funcs smu_v13_0_6_aca_smu_funcs = {
3234 .max_ue_bank_count = 12,
3235 .max_ce_bank_count = 12,
3236 .set_debug_mode = aca_smu_set_debug_mode,
3237 .get_valid_aca_count = aca_smu_get_valid_aca_count,
3238 .get_valid_aca_bank = aca_smu_get_valid_aca_bank,
3239 .parse_error_code = aca_smu_parse_error_code,
3240 };
3241
3242 static const struct pptable_funcs smu_v13_0_6_ppt_funcs = {
3243 /* init dpm */
3244 .get_allowed_feature_mask = smu_v13_0_6_get_allowed_feature_mask,
3245 /* dpm/clk tables */
3246 .set_default_dpm_table = smu_v13_0_6_set_default_dpm_table,
3247 .populate_umd_state_clk = smu_v13_0_6_populate_umd_state_clk,
3248 .print_clk_levels = smu_v13_0_6_print_clk_levels,
3249 .force_clk_levels = smu_v13_0_6_force_clk_levels,
3250 .read_sensor = smu_v13_0_6_read_sensor,
3251 .set_performance_level = smu_v13_0_6_set_performance_level,
3252 .get_power_limit = smu_v13_0_6_get_power_limit,
3253 .is_dpm_running = smu_v13_0_6_is_dpm_running,
3254 .get_unique_id = smu_v13_0_6_get_unique_id,
3255 .init_microcode = smu_v13_0_6_init_microcode,
3256 .fini_microcode = smu_v13_0_fini_microcode,
3257 .init_smc_tables = smu_v13_0_6_init_smc_tables,
3258 .fini_smc_tables = smu_v13_0_fini_smc_tables,
3259 .init_power = smu_v13_0_init_power,
3260 .fini_power = smu_v13_0_fini_power,
3261 .check_fw_status = smu_v13_0_6_check_fw_status,
3262 /* pptable related */
3263 .check_fw_version = smu_v13_0_check_fw_version,
3264 .set_driver_table_location = smu_v13_0_set_driver_table_location,
3265 .set_tool_table_location = smu_v13_0_set_tool_table_location,
3266 .notify_memory_pool_location = smu_v13_0_notify_memory_pool_location,
3267 .system_features_control = smu_v13_0_6_system_features_control,
3268 .send_smc_msg_with_param = smu_cmn_send_smc_msg_with_param,
3269 .send_smc_msg = smu_cmn_send_smc_msg,
3270 .get_enabled_mask = smu_v13_0_6_get_enabled_mask,
3271 .feature_is_enabled = smu_cmn_feature_is_enabled,
3272 .set_power_limit = smu_v13_0_6_set_power_limit,
3273 .set_xgmi_pstate = smu_v13_0_set_xgmi_pstate,
3274 .register_irq_handler = smu_v13_0_6_register_irq_handler,
3275 .enable_thermal_alert = smu_v13_0_enable_thermal_alert,
3276 .disable_thermal_alert = smu_v13_0_disable_thermal_alert,
3277 .setup_pptable = smu_v13_0_6_setup_pptable,
3278 .get_bamaco_support = smu_v13_0_6_get_bamaco_support,
3279 .get_dpm_ultimate_freq = smu_v13_0_6_get_dpm_ultimate_freq,
3280 .set_soft_freq_limited_range = smu_v13_0_6_set_soft_freq_limited_range,
3281 .od_edit_dpm_table = smu_v13_0_6_usr_edit_dpm_table,
3282 .log_thermal_throttling_event = smu_v13_0_6_log_thermal_throttling_event,
3283 .get_pp_feature_mask = smu_cmn_get_pp_feature_mask,
3284 .get_gpu_metrics = smu_v13_0_6_get_gpu_metrics,
3285 .get_pm_metrics = smu_v13_0_6_get_pm_metrics,
3286 .get_thermal_temperature_range = smu_v13_0_6_get_thermal_temperature_range,
3287 .mode1_reset_is_support = smu_v13_0_6_is_mode1_reset_supported,
3288 .mode2_reset_is_support = smu_v13_0_6_is_mode2_reset_supported,
3289 .mode1_reset = smu_v13_0_6_mode1_reset,
3290 .mode2_reset = smu_v13_0_6_mode2_reset,
3291 .wait_for_event = smu_v13_0_wait_for_event,
3292 .i2c_init = smu_v13_0_6_i2c_control_init,
3293 .i2c_fini = smu_v13_0_6_i2c_control_fini,
3294 .send_hbm_bad_pages_num = smu_v13_0_6_smu_send_hbm_bad_page_num,
3295 .send_rma_reason = smu_v13_0_6_send_rma_reason,
3296 };
3297
smu_v13_0_6_set_ppt_funcs(struct smu_context * smu)3298 void smu_v13_0_6_set_ppt_funcs(struct smu_context *smu)
3299 {
3300 smu->ppt_funcs = &smu_v13_0_6_ppt_funcs;
3301 smu->message_map = smu_v13_0_6_message_map;
3302 smu->clock_map = smu_v13_0_6_clk_map;
3303 smu->feature_map = smu_v13_0_6_feature_mask_map;
3304 smu->table_map = smu_v13_0_6_table_map;
3305 smu->smc_driver_if_version = SMU13_0_6_DRIVER_IF_VERSION;
3306 smu->smc_fw_caps |= SMU_FW_CAP_RAS_PRI;
3307 smu_v13_0_set_smu_mailbox_registers(smu);
3308 amdgpu_mca_smu_init_funcs(smu->adev, &smu_v13_0_6_mca_smu_funcs);
3309 amdgpu_aca_set_smu_funcs(smu->adev, &smu_v13_0_6_aca_smu_funcs);
3310 }
3311