1 /*
2 * Copyright 2023 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24 #define SWSMU_CODE_LAYER_L2
25
26 #include <linux/firmware.h>
27 #include <linux/pci.h>
28 #include <linux/i2c.h>
29 #include "amdgpu.h"
30 #include "amdgpu_smu.h"
31 #include "atomfirmware.h"
32 #include "amdgpu_atomfirmware.h"
33 #include "amdgpu_atombios.h"
34 #include "smu_v14_0.h"
35 #include "smu14_driver_if_v14_0.h"
36 #include "soc15_common.h"
37 #include "atom.h"
38 #include "smu_v14_0_2_ppt.h"
39 #include "smu_v14_0_2_pptable.h"
40 #include "smu_v14_0_2_ppsmc.h"
41 #include "mp/mp_14_0_2_offset.h"
42 #include "mp/mp_14_0_2_sh_mask.h"
43
44 #include "smu_cmn.h"
45 #include "amdgpu_ras.h"
46
47 /*
48 * DO NOT use these for err/warn/info/debug messages.
49 * Use dev_err, dev_warn, dev_info and dev_dbg instead.
50 * They are more MGPU friendly.
51 */
52 #undef pr_err
53 #undef pr_warn
54 #undef pr_info
55 #undef pr_debug
56
57 #define to_amdgpu_device(x) (container_of(x, struct amdgpu_device, pm.smu_i2c))
58
59 #define FEATURE_MASK(feature) (1ULL << feature)
60 #define SMC_DPM_FEATURE ( \
61 FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT) | \
62 FEATURE_MASK(FEATURE_DPM_UCLK_BIT) | \
63 FEATURE_MASK(FEATURE_DPM_LINK_BIT) | \
64 FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT) | \
65 FEATURE_MASK(FEATURE_DPM_FCLK_BIT))
66
67 #define MP0_MP1_DATA_REGION_SIZE_COMBOPPTABLE 0x4000
68 #define DEBUGSMC_MSG_Mode1Reset 2
69 #define LINK_SPEED_MAX 3
70
71 #define PP_OD_FEATURE_GFXCLK_FMIN 0
72 #define PP_OD_FEATURE_GFXCLK_FMAX 1
73 #define PP_OD_FEATURE_UCLK_FMIN 2
74 #define PP_OD_FEATURE_UCLK_FMAX 3
75 #define PP_OD_FEATURE_GFX_VF_CURVE 4
76 #define PP_OD_FEATURE_FAN_CURVE_TEMP 5
77 #define PP_OD_FEATURE_FAN_CURVE_PWM 6
78 #define PP_OD_FEATURE_FAN_ACOUSTIC_LIMIT 7
79 #define PP_OD_FEATURE_FAN_ACOUSTIC_TARGET 8
80 #define PP_OD_FEATURE_FAN_TARGET_TEMPERATURE 9
81 #define PP_OD_FEATURE_FAN_MINIMUM_PWM 10
82
83 static struct cmn2asic_msg_mapping smu_v14_0_2_message_map[SMU_MSG_MAX_COUNT] = {
84 MSG_MAP(TestMessage, PPSMC_MSG_TestMessage, 1),
85 MSG_MAP(GetSmuVersion, PPSMC_MSG_GetSmuVersion, 1),
86 MSG_MAP(GetDriverIfVersion, PPSMC_MSG_GetDriverIfVersion, 1),
87 MSG_MAP(SetAllowedFeaturesMaskLow, PPSMC_MSG_SetAllowedFeaturesMaskLow, 0),
88 MSG_MAP(SetAllowedFeaturesMaskHigh, PPSMC_MSG_SetAllowedFeaturesMaskHigh, 0),
89 MSG_MAP(EnableAllSmuFeatures, PPSMC_MSG_EnableAllSmuFeatures, 0),
90 MSG_MAP(DisableAllSmuFeatures, PPSMC_MSG_DisableAllSmuFeatures, 0),
91 MSG_MAP(EnableSmuFeaturesLow, PPSMC_MSG_EnableSmuFeaturesLow, 1),
92 MSG_MAP(EnableSmuFeaturesHigh, PPSMC_MSG_EnableSmuFeaturesHigh, 1),
93 MSG_MAP(DisableSmuFeaturesLow, PPSMC_MSG_DisableSmuFeaturesLow, 1),
94 MSG_MAP(DisableSmuFeaturesHigh, PPSMC_MSG_DisableSmuFeaturesHigh, 1),
95 MSG_MAP(GetEnabledSmuFeaturesLow, PPSMC_MSG_GetRunningSmuFeaturesLow, 1),
96 MSG_MAP(GetEnabledSmuFeaturesHigh, PPSMC_MSG_GetRunningSmuFeaturesHigh, 1),
97 MSG_MAP(SetWorkloadMask, PPSMC_MSG_SetWorkloadMask, 1),
98 MSG_MAP(SetPptLimit, PPSMC_MSG_SetPptLimit, 0),
99 MSG_MAP(SetDriverDramAddrHigh, PPSMC_MSG_SetDriverDramAddrHigh, 1),
100 MSG_MAP(SetDriverDramAddrLow, PPSMC_MSG_SetDriverDramAddrLow, 1),
101 MSG_MAP(SetToolsDramAddrHigh, PPSMC_MSG_SetToolsDramAddrHigh, 0),
102 MSG_MAP(SetToolsDramAddrLow, PPSMC_MSG_SetToolsDramAddrLow, 0),
103 MSG_MAP(TransferTableSmu2Dram, PPSMC_MSG_TransferTableSmu2Dram, 1),
104 MSG_MAP(TransferTableDram2Smu, PPSMC_MSG_TransferTableDram2Smu, 0),
105 MSG_MAP(UseDefaultPPTable, PPSMC_MSG_UseDefaultPPTable, 0),
106 MSG_MAP(RunDcBtc, PPSMC_MSG_RunDcBtc, 0),
107 MSG_MAP(EnterBaco, PPSMC_MSG_EnterBaco, 0),
108 MSG_MAP(ExitBaco, PPSMC_MSG_ExitBaco, 0),
109 MSG_MAP(SetSoftMinByFreq, PPSMC_MSG_SetSoftMinByFreq, 1),
110 MSG_MAP(SetSoftMaxByFreq, PPSMC_MSG_SetSoftMaxByFreq, 1),
111 MSG_MAP(SetHardMinByFreq, PPSMC_MSG_SetHardMinByFreq, 1),
112 MSG_MAP(SetHardMaxByFreq, PPSMC_MSG_SetHardMaxByFreq, 0),
113 MSG_MAP(GetMinDpmFreq, PPSMC_MSG_GetMinDpmFreq, 1),
114 MSG_MAP(GetMaxDpmFreq, PPSMC_MSG_GetMaxDpmFreq, 1),
115 MSG_MAP(GetDpmFreqByIndex, PPSMC_MSG_GetDpmFreqByIndex, 1),
116 MSG_MAP(PowerUpVcn, PPSMC_MSG_PowerUpVcn, 0),
117 MSG_MAP(PowerDownVcn, PPSMC_MSG_PowerDownVcn, 0),
118 MSG_MAP(PowerUpJpeg, PPSMC_MSG_PowerUpJpeg, 0),
119 MSG_MAP(PowerDownJpeg, PPSMC_MSG_PowerDownJpeg, 0),
120 MSG_MAP(GetDcModeMaxDpmFreq, PPSMC_MSG_GetDcModeMaxDpmFreq, 1),
121 MSG_MAP(OverridePcieParameters, PPSMC_MSG_OverridePcieParameters, 0),
122 MSG_MAP(DramLogSetDramAddrHigh, PPSMC_MSG_DramLogSetDramAddrHigh, 0),
123 MSG_MAP(DramLogSetDramAddrLow, PPSMC_MSG_DramLogSetDramAddrLow, 0),
124 MSG_MAP(DramLogSetDramSize, PPSMC_MSG_DramLogSetDramSize, 0),
125 MSG_MAP(AllowGfxOff, PPSMC_MSG_AllowGfxOff, 0),
126 MSG_MAP(DisallowGfxOff, PPSMC_MSG_DisallowGfxOff, 0),
127 MSG_MAP(SetMGpuFanBoostLimitRpm, PPSMC_MSG_SetMGpuFanBoostLimitRpm, 0),
128 MSG_MAP(GetPptLimit, PPSMC_MSG_GetPptLimit, 0),
129 MSG_MAP(NotifyPowerSource, PPSMC_MSG_NotifyPowerSource, 0),
130 MSG_MAP(PrepareMp1ForUnload, PPSMC_MSG_PrepareMp1ForUnload, 0),
131 MSG_MAP(DFCstateControl, PPSMC_MSG_SetExternalClientDfCstateAllow, 0),
132 MSG_MAP(ArmD3, PPSMC_MSG_ArmD3, 0),
133 MSG_MAP(SetNumBadMemoryPagesRetired, PPSMC_MSG_SetNumBadMemoryPagesRetired, 0),
134 MSG_MAP(SetBadMemoryPagesRetiredFlagsPerChannel,
135 PPSMC_MSG_SetBadMemoryPagesRetiredFlagsPerChannel, 0),
136 MSG_MAP(AllowIHHostInterrupt, PPSMC_MSG_AllowIHHostInterrupt, 0),
137 MSG_MAP(ReenableAcDcInterrupt, PPSMC_MSG_ReenableAcDcInterrupt, 0),
138 };
139
140 static struct cmn2asic_mapping smu_v14_0_2_clk_map[SMU_CLK_COUNT] = {
141 CLK_MAP(GFXCLK, PPCLK_GFXCLK),
142 CLK_MAP(SCLK, PPCLK_GFXCLK),
143 CLK_MAP(SOCCLK, PPCLK_SOCCLK),
144 CLK_MAP(FCLK, PPCLK_FCLK),
145 CLK_MAP(UCLK, PPCLK_UCLK),
146 CLK_MAP(MCLK, PPCLK_UCLK),
147 CLK_MAP(VCLK, PPCLK_VCLK_0),
148 CLK_MAP(DCLK, PPCLK_DCLK_0),
149 CLK_MAP(DCEFCLK, PPCLK_DCFCLK),
150 };
151
152 static struct cmn2asic_mapping smu_v14_0_2_feature_mask_map[SMU_FEATURE_COUNT] = {
153 FEA_MAP(FW_DATA_READ),
154 FEA_MAP(DPM_GFXCLK),
155 FEA_MAP(DPM_GFX_POWER_OPTIMIZER),
156 FEA_MAP(DPM_UCLK),
157 FEA_MAP(DPM_FCLK),
158 FEA_MAP(DPM_SOCCLK),
159 FEA_MAP(DPM_LINK),
160 FEA_MAP(DPM_DCN),
161 FEA_MAP(VMEMP_SCALING),
162 FEA_MAP(VDDIO_MEM_SCALING),
163 FEA_MAP(DS_GFXCLK),
164 FEA_MAP(DS_SOCCLK),
165 FEA_MAP(DS_FCLK),
166 FEA_MAP(DS_LCLK),
167 FEA_MAP(DS_DCFCLK),
168 FEA_MAP(DS_UCLK),
169 FEA_MAP(GFX_ULV),
170 FEA_MAP(FW_DSTATE),
171 FEA_MAP(GFXOFF),
172 FEA_MAP(BACO),
173 FEA_MAP(MM_DPM),
174 FEA_MAP(SOC_MPCLK_DS),
175 FEA_MAP(BACO_MPCLK_DS),
176 FEA_MAP(THROTTLERS),
177 FEA_MAP(SMARTSHIFT),
178 FEA_MAP(GTHR),
179 FEA_MAP(ACDC),
180 FEA_MAP(VR0HOT),
181 FEA_MAP(FW_CTF),
182 FEA_MAP(FAN_CONTROL),
183 FEA_MAP(GFX_DCS),
184 FEA_MAP(GFX_READ_MARGIN),
185 FEA_MAP(LED_DISPLAY),
186 FEA_MAP(GFXCLK_SPREAD_SPECTRUM),
187 FEA_MAP(OUT_OF_BAND_MONITOR),
188 FEA_MAP(OPTIMIZED_VMIN),
189 FEA_MAP(GFX_IMU),
190 FEA_MAP(BOOT_TIME_CAL),
191 FEA_MAP(GFX_PCC_DFLL),
192 FEA_MAP(SOC_CG),
193 FEA_MAP(DF_CSTATE),
194 FEA_MAP(GFX_EDC),
195 FEA_MAP(BOOT_POWER_OPT),
196 FEA_MAP(CLOCK_POWER_DOWN_BYPASS),
197 FEA_MAP(DS_VCN),
198 FEA_MAP(BACO_CG),
199 FEA_MAP(MEM_TEMP_READ),
200 FEA_MAP(ATHUB_MMHUB_PG),
201 FEA_MAP(SOC_PCC),
202 FEA_MAP(EDC_PWRBRK),
203 FEA_MAP(SOC_EDC_XVMIN),
204 FEA_MAP(GFX_PSM_DIDT),
205 FEA_MAP(APT_ALL_ENABLE),
206 FEA_MAP(APT_SQ_THROTTLE),
207 FEA_MAP(APT_PF_DCS),
208 FEA_MAP(GFX_EDC_XVMIN),
209 FEA_MAP(GFX_DIDT_XVMIN),
210 FEA_MAP(FAN_ABNORMAL),
211 [SMU_FEATURE_DPM_VCLK_BIT] = {1, FEATURE_MM_DPM_BIT},
212 [SMU_FEATURE_DPM_DCLK_BIT] = {1, FEATURE_MM_DPM_BIT},
213 [SMU_FEATURE_PPT_BIT] = {1, FEATURE_THROTTLERS_BIT},
214 };
215
216 static struct cmn2asic_mapping smu_v14_0_2_table_map[SMU_TABLE_COUNT] = {
217 TAB_MAP(PPTABLE),
218 TAB_MAP(WATERMARKS),
219 TAB_MAP(AVFS_PSM_DEBUG),
220 TAB_MAP(PMSTATUSLOG),
221 TAB_MAP(SMU_METRICS),
222 TAB_MAP(DRIVER_SMU_CONFIG),
223 TAB_MAP(ACTIVITY_MONITOR_COEFF),
224 [SMU_TABLE_COMBO_PPTABLE] = {1, TABLE_COMBO_PPTABLE},
225 TAB_MAP(I2C_COMMANDS),
226 TAB_MAP(ECCINFO),
227 TAB_MAP(OVERDRIVE),
228 };
229
230 static struct cmn2asic_mapping smu_v14_0_2_pwr_src_map[SMU_POWER_SOURCE_COUNT] = {
231 PWR_MAP(AC),
232 PWR_MAP(DC),
233 };
234
235 static struct cmn2asic_mapping smu_v14_0_2_workload_map[PP_SMC_POWER_PROFILE_COUNT] = {
236 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT, WORKLOAD_PPLIB_DEFAULT_BIT),
237 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_FULLSCREEN3D, WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT),
238 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_POWERSAVING, WORKLOAD_PPLIB_POWER_SAVING_BIT),
239 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VIDEO, WORKLOAD_PPLIB_VIDEO_BIT),
240 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VR, WORKLOAD_PPLIB_VR_BIT),
241 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_COMPUTE, WORKLOAD_PPLIB_COMPUTE_BIT),
242 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_CUSTOM, WORKLOAD_PPLIB_CUSTOM_BIT),
243 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_WINDOW3D, WORKLOAD_PPLIB_WINDOW_3D_BIT),
244 };
245
246 static const uint8_t smu_v14_0_2_throttler_map[] = {
247 [THROTTLER_PPT0_BIT] = (SMU_THROTTLER_PPT0_BIT),
248 [THROTTLER_PPT1_BIT] = (SMU_THROTTLER_PPT1_BIT),
249 [THROTTLER_PPT2_BIT] = (SMU_THROTTLER_PPT2_BIT),
250 [THROTTLER_PPT3_BIT] = (SMU_THROTTLER_PPT3_BIT),
251 [THROTTLER_TDC_GFX_BIT] = (SMU_THROTTLER_TDC_GFX_BIT),
252 [THROTTLER_TDC_SOC_BIT] = (SMU_THROTTLER_TDC_SOC_BIT),
253 [THROTTLER_TEMP_EDGE_BIT] = (SMU_THROTTLER_TEMP_EDGE_BIT),
254 [THROTTLER_TEMP_HOTSPOT_BIT] = (SMU_THROTTLER_TEMP_HOTSPOT_BIT),
255 [THROTTLER_TEMP_MEM_BIT] = (SMU_THROTTLER_TEMP_MEM_BIT),
256 [THROTTLER_TEMP_VR_GFX_BIT] = (SMU_THROTTLER_TEMP_VR_GFX_BIT),
257 [THROTTLER_TEMP_VR_SOC_BIT] = (SMU_THROTTLER_TEMP_VR_SOC_BIT),
258 [THROTTLER_TEMP_VR_MEM0_BIT] = (SMU_THROTTLER_TEMP_VR_MEM0_BIT),
259 [THROTTLER_TEMP_VR_MEM1_BIT] = (SMU_THROTTLER_TEMP_VR_MEM1_BIT),
260 [THROTTLER_TEMP_LIQUID0_BIT] = (SMU_THROTTLER_TEMP_LIQUID0_BIT),
261 [THROTTLER_TEMP_LIQUID1_BIT] = (SMU_THROTTLER_TEMP_LIQUID1_BIT),
262 [THROTTLER_GFX_APCC_PLUS_BIT] = (SMU_THROTTLER_APCC_BIT),
263 [THROTTLER_FIT_BIT] = (SMU_THROTTLER_FIT_BIT),
264 };
265
266 static int
smu_v14_0_2_get_allowed_feature_mask(struct smu_context * smu,uint32_t * feature_mask,uint32_t num)267 smu_v14_0_2_get_allowed_feature_mask(struct smu_context *smu,
268 uint32_t *feature_mask, uint32_t num)
269 {
270 struct amdgpu_device *adev = smu->adev;
271 /*u32 smu_version;*/
272
273 if (num > 2)
274 return -EINVAL;
275
276 memset(feature_mask, 0xff, sizeof(uint32_t) * num);
277
278 if (adev->pm.pp_feature & PP_SCLK_DPM_MASK) {
279 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT);
280 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFX_IMU_BIT);
281 }
282 #if 0
283 if (!(adev->pg_flags & AMD_PG_SUPPORT_ATHUB) ||
284 !(adev->pg_flags & AMD_PG_SUPPORT_MMHUB))
285 *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_ATHUB_MMHUB_PG_BIT);
286
287 if (!(adev->pm.pp_feature & PP_SOCCLK_DPM_MASK))
288 *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT);
289
290 /* PMFW 78.58 contains a critical fix for gfxoff feature */
291 smu_cmn_get_smc_version(smu, NULL, &smu_version);
292 if ((smu_version < 0x004e3a00) ||
293 !(adev->pm.pp_feature & PP_GFXOFF_MASK))
294 *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_GFXOFF_BIT);
295
296 if (!(adev->pm.pp_feature & PP_MCLK_DPM_MASK)) {
297 *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_DPM_UCLK_BIT);
298 *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_VMEMP_SCALING_BIT);
299 *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_VDDIO_MEM_SCALING_BIT);
300 }
301
302 if (!(adev->pm.pp_feature & PP_SCLK_DEEP_SLEEP_MASK))
303 *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_DS_GFXCLK_BIT);
304
305 if (!(adev->pm.pp_feature & PP_PCIE_DPM_MASK)) {
306 *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_DPM_LINK_BIT);
307 *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_DS_LCLK_BIT);
308 }
309
310 if (!(adev->pm.pp_feature & PP_ULV_MASK))
311 *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_GFX_ULV_BIT);
312 #endif
313
314 return 0;
315 }
316
smu_v14_0_2_check_powerplay_table(struct smu_context * smu)317 static int smu_v14_0_2_check_powerplay_table(struct smu_context *smu)
318 {
319 struct smu_table_context *table_context = &smu->smu_table;
320 struct smu_14_0_2_powerplay_table *powerplay_table =
321 table_context->power_play_table;
322 struct smu_baco_context *smu_baco = &smu->smu_baco;
323 PPTable_t *pptable = smu->smu_table.driver_pptable;
324 const OverDriveLimits_t * const overdrive_upperlimits =
325 &pptable->SkuTable.OverDriveLimitsBasicMax;
326 const OverDriveLimits_t * const overdrive_lowerlimits =
327 &pptable->SkuTable.OverDriveLimitsBasicMin;
328
329 if (powerplay_table->platform_caps & SMU_14_0_2_PP_PLATFORM_CAP_HARDWAREDC)
330 smu->dc_controlled_by_gpio = true;
331
332 if (powerplay_table->platform_caps & SMU_14_0_2_PP_PLATFORM_CAP_BACO) {
333 smu_baco->platform_support = true;
334
335 if (powerplay_table->platform_caps & SMU_14_0_2_PP_PLATFORM_CAP_MACO)
336 smu_baco->maco_support = true;
337 }
338
339 if (!overdrive_lowerlimits->FeatureCtrlMask ||
340 !overdrive_upperlimits->FeatureCtrlMask)
341 smu->od_enabled = false;
342
343 table_context->thermal_controller_type =
344 powerplay_table->thermal_controller_type;
345
346 /*
347 * Instead of having its own buffer space and get overdrive_table copied,
348 * smu->od_settings just points to the actual overdrive_table
349 */
350 smu->od_settings = &powerplay_table->overdrive_table;
351
352 smu->adev->pm.no_fan =
353 !(pptable->PFE_Settings.FeaturesToRun[0] & (1 << FEATURE_FAN_CONTROL_BIT));
354
355 return 0;
356 }
357
smu_v14_0_2_store_powerplay_table(struct smu_context * smu)358 static int smu_v14_0_2_store_powerplay_table(struct smu_context *smu)
359 {
360 struct smu_table_context *table_context = &smu->smu_table;
361 struct smu_14_0_2_powerplay_table *powerplay_table =
362 table_context->power_play_table;
363
364 memcpy(table_context->driver_pptable, &powerplay_table->smc_pptable,
365 sizeof(PPTable_t));
366
367 return 0;
368 }
369
smu_v14_0_2_get_pptable_from_pmfw(struct smu_context * smu,void ** table,uint32_t * size)370 static int smu_v14_0_2_get_pptable_from_pmfw(struct smu_context *smu,
371 void **table,
372 uint32_t *size)
373 {
374 struct smu_table_context *smu_table = &smu->smu_table;
375 void *combo_pptable = smu_table->combo_pptable;
376 int ret = 0;
377
378 ret = smu_cmn_get_combo_pptable(smu);
379 if (ret)
380 return ret;
381
382 *table = combo_pptable;
383 *size = sizeof(struct smu_14_0_2_powerplay_table);
384
385 return 0;
386 }
387
smu_v14_0_2_setup_pptable(struct smu_context * smu)388 static int smu_v14_0_2_setup_pptable(struct smu_context *smu)
389 {
390 struct smu_table_context *smu_table = &smu->smu_table;
391 int ret = 0;
392
393 if (amdgpu_sriov_vf(smu->adev))
394 return 0;
395
396 ret = smu_v14_0_2_get_pptable_from_pmfw(smu,
397 &smu_table->power_play_table,
398 &smu_table->power_play_table_size);
399 if (ret)
400 return ret;
401
402 ret = smu_v14_0_2_store_powerplay_table(smu);
403 if (ret)
404 return ret;
405
406 ret = smu_v14_0_2_check_powerplay_table(smu);
407 if (ret)
408 return ret;
409
410 return ret;
411 }
412
smu_v14_0_2_tables_init(struct smu_context * smu)413 static int smu_v14_0_2_tables_init(struct smu_context *smu)
414 {
415 struct smu_table_context *smu_table = &smu->smu_table;
416 struct smu_table *tables = smu_table->tables;
417
418 SMU_TABLE_INIT(tables, SMU_TABLE_PPTABLE, sizeof(PPTable_t),
419 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
420 SMU_TABLE_INIT(tables, SMU_TABLE_WATERMARKS, sizeof(Watermarks_t),
421 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
422 SMU_TABLE_INIT(tables, SMU_TABLE_SMU_METRICS, sizeof(SmuMetricsExternal_t),
423 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
424 SMU_TABLE_INIT(tables, SMU_TABLE_I2C_COMMANDS, sizeof(SwI2cRequest_t),
425 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
426 SMU_TABLE_INIT(tables, SMU_TABLE_OVERDRIVE, sizeof(OverDriveTable_t),
427 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
428 SMU_TABLE_INIT(tables, SMU_TABLE_PMSTATUSLOG, SMU14_TOOL_SIZE,
429 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
430 SMU_TABLE_INIT(tables, SMU_TABLE_ACTIVITY_MONITOR_COEFF,
431 sizeof(DpmActivityMonitorCoeffIntExternal_t), PAGE_SIZE,
432 AMDGPU_GEM_DOMAIN_VRAM);
433 SMU_TABLE_INIT(tables, SMU_TABLE_COMBO_PPTABLE, MP0_MP1_DATA_REGION_SIZE_COMBOPPTABLE,
434 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
435 SMU_TABLE_INIT(tables, SMU_TABLE_ECCINFO, sizeof(EccInfoTable_t),
436 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
437
438 smu_table->metrics_table = kzalloc(sizeof(SmuMetricsExternal_t), GFP_KERNEL);
439 if (!smu_table->metrics_table)
440 goto err0_out;
441 smu_table->metrics_time = 0;
442
443 smu_table->gpu_metrics_table_size = sizeof(struct gpu_metrics_v1_3);
444 smu_table->gpu_metrics_table = kzalloc(smu_table->gpu_metrics_table_size, GFP_KERNEL);
445 if (!smu_table->gpu_metrics_table)
446 goto err1_out;
447
448 smu_table->watermarks_table = kzalloc(sizeof(Watermarks_t), GFP_KERNEL);
449 if (!smu_table->watermarks_table)
450 goto err2_out;
451
452 smu_table->ecc_table = kzalloc(tables[SMU_TABLE_ECCINFO].size, GFP_KERNEL);
453 if (!smu_table->ecc_table)
454 goto err3_out;
455
456 return 0;
457
458 err3_out:
459 kfree(smu_table->watermarks_table);
460 err2_out:
461 kfree(smu_table->gpu_metrics_table);
462 err1_out:
463 kfree(smu_table->metrics_table);
464 err0_out:
465 return -ENOMEM;
466 }
467
smu_v14_0_2_allocate_dpm_context(struct smu_context * smu)468 static int smu_v14_0_2_allocate_dpm_context(struct smu_context *smu)
469 {
470 struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
471
472 smu_dpm->dpm_context = kzalloc(sizeof(struct smu_14_0_dpm_context),
473 GFP_KERNEL);
474 if (!smu_dpm->dpm_context)
475 return -ENOMEM;
476
477 smu_dpm->dpm_context_size = sizeof(struct smu_14_0_dpm_context);
478
479 return 0;
480 }
481
smu_v14_0_2_init_smc_tables(struct smu_context * smu)482 static int smu_v14_0_2_init_smc_tables(struct smu_context *smu)
483 {
484 int ret = 0;
485
486 ret = smu_v14_0_2_tables_init(smu);
487 if (ret)
488 return ret;
489
490 ret = smu_v14_0_2_allocate_dpm_context(smu);
491 if (ret)
492 return ret;
493
494 return smu_v14_0_init_smc_tables(smu);
495 }
496
smu_v14_0_2_set_default_dpm_table(struct smu_context * smu)497 static int smu_v14_0_2_set_default_dpm_table(struct smu_context *smu)
498 {
499 struct smu_14_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;
500 struct smu_table_context *table_context = &smu->smu_table;
501 PPTable_t *pptable = table_context->driver_pptable;
502 SkuTable_t *skutable = &pptable->SkuTable;
503 struct smu_14_0_dpm_table *dpm_table;
504 struct smu_14_0_pcie_table *pcie_table;
505 uint32_t link_level;
506 int ret = 0;
507
508 /* socclk dpm table setup */
509 dpm_table = &dpm_context->dpm_tables.soc_table;
510 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
511 ret = smu_v14_0_set_single_dpm_table(smu,
512 SMU_SOCCLK,
513 dpm_table);
514 if (ret)
515 return ret;
516 } else {
517 dpm_table->count = 1;
518 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.socclk / 100;
519 dpm_table->dpm_levels[0].enabled = true;
520 dpm_table->min = dpm_table->dpm_levels[0].value;
521 dpm_table->max = dpm_table->dpm_levels[0].value;
522 }
523
524 /* gfxclk dpm table setup */
525 dpm_table = &dpm_context->dpm_tables.gfx_table;
526 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT)) {
527 ret = smu_v14_0_set_single_dpm_table(smu,
528 SMU_GFXCLK,
529 dpm_table);
530 if (ret)
531 return ret;
532
533 /*
534 * Update the reported maximum shader clock to the value
535 * which can be guarded to be achieved on all cards. This
536 * is aligned with Window setting. And considering that value
537 * might be not the peak frequency the card can achieve, it
538 * is normal some real-time clock frequency can overtake this
539 * labelled maximum clock frequency(for example in pp_dpm_sclk
540 * sysfs output).
541 */
542 if (skutable->DriverReportedClocks.GameClockAc &&
543 (dpm_table->dpm_levels[dpm_table->count - 1].value >
544 skutable->DriverReportedClocks.GameClockAc)) {
545 dpm_table->dpm_levels[dpm_table->count - 1].value =
546 skutable->DriverReportedClocks.GameClockAc;
547 dpm_table->max = skutable->DriverReportedClocks.GameClockAc;
548 }
549 } else {
550 dpm_table->count = 1;
551 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.gfxclk / 100;
552 dpm_table->dpm_levels[0].enabled = true;
553 dpm_table->min = dpm_table->dpm_levels[0].value;
554 dpm_table->max = dpm_table->dpm_levels[0].value;
555 }
556
557 /* uclk dpm table setup */
558 dpm_table = &dpm_context->dpm_tables.uclk_table;
559 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
560 ret = smu_v14_0_set_single_dpm_table(smu,
561 SMU_UCLK,
562 dpm_table);
563 if (ret)
564 return ret;
565 } else {
566 dpm_table->count = 1;
567 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.uclk / 100;
568 dpm_table->dpm_levels[0].enabled = true;
569 dpm_table->min = dpm_table->dpm_levels[0].value;
570 dpm_table->max = dpm_table->dpm_levels[0].value;
571 }
572
573 /* fclk dpm table setup */
574 dpm_table = &dpm_context->dpm_tables.fclk_table;
575 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_FCLK_BIT)) {
576 ret = smu_v14_0_set_single_dpm_table(smu,
577 SMU_FCLK,
578 dpm_table);
579 if (ret)
580 return ret;
581 } else {
582 dpm_table->count = 1;
583 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.fclk / 100;
584 dpm_table->dpm_levels[0].enabled = true;
585 dpm_table->min = dpm_table->dpm_levels[0].value;
586 dpm_table->max = dpm_table->dpm_levels[0].value;
587 }
588
589 /* vclk dpm table setup */
590 dpm_table = &dpm_context->dpm_tables.vclk_table;
591 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_VCLK_BIT)) {
592 ret = smu_v14_0_set_single_dpm_table(smu,
593 SMU_VCLK,
594 dpm_table);
595 if (ret)
596 return ret;
597 } else {
598 dpm_table->count = 1;
599 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.vclk / 100;
600 dpm_table->dpm_levels[0].enabled = true;
601 dpm_table->min = dpm_table->dpm_levels[0].value;
602 dpm_table->max = dpm_table->dpm_levels[0].value;
603 }
604
605 /* dclk dpm table setup */
606 dpm_table = &dpm_context->dpm_tables.dclk_table;
607 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCLK_BIT)) {
608 ret = smu_v14_0_set_single_dpm_table(smu,
609 SMU_DCLK,
610 dpm_table);
611 if (ret)
612 return ret;
613 } else {
614 dpm_table->count = 1;
615 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dclk / 100;
616 dpm_table->dpm_levels[0].enabled = true;
617 dpm_table->min = dpm_table->dpm_levels[0].value;
618 dpm_table->max = dpm_table->dpm_levels[0].value;
619 }
620
621 /* lclk dpm table setup */
622 pcie_table = &dpm_context->dpm_tables.pcie_table;
623 pcie_table->num_of_link_levels = 0;
624 for (link_level = 0; link_level < NUM_LINK_LEVELS; link_level++) {
625 if (!skutable->PcieGenSpeed[link_level] &&
626 !skutable->PcieLaneCount[link_level] &&
627 !skutable->LclkFreq[link_level])
628 continue;
629
630 pcie_table->pcie_gen[pcie_table->num_of_link_levels] =
631 skutable->PcieGenSpeed[link_level];
632 pcie_table->pcie_lane[pcie_table->num_of_link_levels] =
633 skutable->PcieLaneCount[link_level];
634 pcie_table->clk_freq[pcie_table->num_of_link_levels] =
635 skutable->LclkFreq[link_level];
636 pcie_table->num_of_link_levels++;
637
638 if (link_level == 0)
639 link_level++;
640 }
641
642 /* dcefclk dpm table setup */
643 dpm_table = &dpm_context->dpm_tables.dcef_table;
644 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCN_BIT)) {
645 ret = smu_v14_0_set_single_dpm_table(smu,
646 SMU_DCEFCLK,
647 dpm_table);
648 if (ret)
649 return ret;
650 } else {
651 dpm_table->count = 1;
652 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100;
653 dpm_table->dpm_levels[0].enabled = true;
654 dpm_table->min = dpm_table->dpm_levels[0].value;
655 dpm_table->max = dpm_table->dpm_levels[0].value;
656 }
657
658 return 0;
659 }
660
smu_v14_0_2_is_dpm_running(struct smu_context * smu)661 static bool smu_v14_0_2_is_dpm_running(struct smu_context *smu)
662 {
663 int ret = 0;
664 uint64_t feature_enabled;
665
666 ret = smu_cmn_get_enabled_mask(smu, &feature_enabled);
667 if (ret)
668 return false;
669
670 return !!(feature_enabled & SMC_DPM_FEATURE);
671 }
672
smu_v14_0_2_dump_pptable(struct smu_context * smu)673 static void smu_v14_0_2_dump_pptable(struct smu_context *smu)
674 {
675 struct smu_table_context *table_context = &smu->smu_table;
676 PPTable_t *pptable = table_context->driver_pptable;
677 PFE_Settings_t *PFEsettings = &pptable->PFE_Settings;
678
679 dev_info(smu->adev->dev, "Dumped PPTable:\n");
680
681 dev_info(smu->adev->dev, "Version = 0x%08x\n", PFEsettings->Version);
682 dev_info(smu->adev->dev, "FeaturesToRun[0] = 0x%08x\n", PFEsettings->FeaturesToRun[0]);
683 dev_info(smu->adev->dev, "FeaturesToRun[1] = 0x%08x\n", PFEsettings->FeaturesToRun[1]);
684 }
685
smu_v14_0_2_get_throttler_status(SmuMetrics_t * metrics)686 static uint32_t smu_v14_0_2_get_throttler_status(SmuMetrics_t *metrics)
687 {
688 uint32_t throttler_status = 0;
689 int i;
690
691 for (i = 0; i < THROTTLER_COUNT; i++)
692 throttler_status |=
693 (metrics->ThrottlingPercentage[i] ? 1U << i : 0);
694
695 return throttler_status;
696 }
697
698 #define SMU_14_0_2_BUSY_THRESHOLD 5
smu_v14_0_2_get_smu_metrics_data(struct smu_context * smu,MetricsMember_t member,uint32_t * value)699 static int smu_v14_0_2_get_smu_metrics_data(struct smu_context *smu,
700 MetricsMember_t member,
701 uint32_t *value)
702 {
703 struct smu_table_context *smu_table = &smu->smu_table;
704 SmuMetrics_t *metrics =
705 &(((SmuMetricsExternal_t *)(smu_table->metrics_table))->SmuMetrics);
706 int ret = 0;
707
708 ret = smu_cmn_get_metrics_table(smu,
709 NULL,
710 false);
711 if (ret)
712 return ret;
713
714 switch (member) {
715 case METRICS_CURR_GFXCLK:
716 *value = metrics->CurrClock[PPCLK_GFXCLK];
717 break;
718 case METRICS_CURR_SOCCLK:
719 *value = metrics->CurrClock[PPCLK_SOCCLK];
720 break;
721 case METRICS_CURR_UCLK:
722 *value = metrics->CurrClock[PPCLK_UCLK];
723 break;
724 case METRICS_CURR_VCLK:
725 *value = metrics->CurrClock[PPCLK_VCLK_0];
726 break;
727 case METRICS_CURR_DCLK:
728 *value = metrics->CurrClock[PPCLK_DCLK_0];
729 break;
730 case METRICS_CURR_FCLK:
731 *value = metrics->CurrClock[PPCLK_FCLK];
732 break;
733 case METRICS_CURR_DCEFCLK:
734 *value = metrics->CurrClock[PPCLK_DCFCLK];
735 break;
736 case METRICS_AVERAGE_GFXCLK:
737 if (metrics->AverageGfxActivity <= SMU_14_0_2_BUSY_THRESHOLD)
738 *value = metrics->AverageGfxclkFrequencyPostDs;
739 else
740 *value = metrics->AverageGfxclkFrequencyPreDs;
741 break;
742 case METRICS_AVERAGE_FCLK:
743 if (metrics->AverageUclkActivity <= SMU_14_0_2_BUSY_THRESHOLD)
744 *value = metrics->AverageFclkFrequencyPostDs;
745 else
746 *value = metrics->AverageFclkFrequencyPreDs;
747 break;
748 case METRICS_AVERAGE_UCLK:
749 if (metrics->AverageUclkActivity <= SMU_14_0_2_BUSY_THRESHOLD)
750 *value = metrics->AverageMemclkFrequencyPostDs;
751 else
752 *value = metrics->AverageMemclkFrequencyPreDs;
753 break;
754 case METRICS_AVERAGE_VCLK:
755 *value = metrics->AverageVclk0Frequency;
756 break;
757 case METRICS_AVERAGE_DCLK:
758 *value = metrics->AverageDclk0Frequency;
759 break;
760 case METRICS_AVERAGE_VCLK1:
761 *value = metrics->AverageVclk1Frequency;
762 break;
763 case METRICS_AVERAGE_DCLK1:
764 *value = metrics->AverageDclk1Frequency;
765 break;
766 case METRICS_AVERAGE_GFXACTIVITY:
767 *value = metrics->AverageGfxActivity;
768 break;
769 case METRICS_AVERAGE_MEMACTIVITY:
770 *value = metrics->AverageUclkActivity;
771 break;
772 case METRICS_AVERAGE_SOCKETPOWER:
773 *value = metrics->AverageSocketPower << 8;
774 break;
775 case METRICS_TEMPERATURE_EDGE:
776 *value = metrics->AvgTemperature[TEMP_EDGE] *
777 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
778 break;
779 case METRICS_TEMPERATURE_HOTSPOT:
780 *value = metrics->AvgTemperature[TEMP_HOTSPOT] *
781 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
782 break;
783 case METRICS_TEMPERATURE_MEM:
784 *value = metrics->AvgTemperature[TEMP_MEM] *
785 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
786 break;
787 case METRICS_TEMPERATURE_VRGFX:
788 *value = metrics->AvgTemperature[TEMP_VR_GFX] *
789 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
790 break;
791 case METRICS_TEMPERATURE_VRSOC:
792 *value = metrics->AvgTemperature[TEMP_VR_SOC] *
793 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
794 break;
795 case METRICS_THROTTLER_STATUS:
796 *value = smu_v14_0_2_get_throttler_status(metrics);
797 break;
798 case METRICS_CURR_FANSPEED:
799 *value = metrics->AvgFanRpm;
800 break;
801 case METRICS_CURR_FANPWM:
802 *value = metrics->AvgFanPwm;
803 break;
804 case METRICS_VOLTAGE_VDDGFX:
805 *value = metrics->AvgVoltage[SVI_PLANE_VDD_GFX];
806 break;
807 case METRICS_PCIE_RATE:
808 *value = metrics->PcieRate;
809 break;
810 case METRICS_PCIE_WIDTH:
811 *value = metrics->PcieWidth;
812 break;
813 default:
814 *value = UINT_MAX;
815 break;
816 }
817
818 return ret;
819 }
820
smu_v14_0_2_get_dpm_ultimate_freq(struct smu_context * smu,enum smu_clk_type clk_type,uint32_t * min,uint32_t * max)821 static int smu_v14_0_2_get_dpm_ultimate_freq(struct smu_context *smu,
822 enum smu_clk_type clk_type,
823 uint32_t *min,
824 uint32_t *max)
825 {
826 struct smu_14_0_dpm_context *dpm_context =
827 smu->smu_dpm.dpm_context;
828 struct smu_14_0_dpm_table *dpm_table;
829
830 switch (clk_type) {
831 case SMU_MCLK:
832 case SMU_UCLK:
833 /* uclk dpm table */
834 dpm_table = &dpm_context->dpm_tables.uclk_table;
835 break;
836 case SMU_GFXCLK:
837 case SMU_SCLK:
838 /* gfxclk dpm table */
839 dpm_table = &dpm_context->dpm_tables.gfx_table;
840 break;
841 case SMU_SOCCLK:
842 /* socclk dpm table */
843 dpm_table = &dpm_context->dpm_tables.soc_table;
844 break;
845 case SMU_FCLK:
846 /* fclk dpm table */
847 dpm_table = &dpm_context->dpm_tables.fclk_table;
848 break;
849 case SMU_VCLK:
850 case SMU_VCLK1:
851 /* vclk dpm table */
852 dpm_table = &dpm_context->dpm_tables.vclk_table;
853 break;
854 case SMU_DCLK:
855 case SMU_DCLK1:
856 /* dclk dpm table */
857 dpm_table = &dpm_context->dpm_tables.dclk_table;
858 break;
859 default:
860 dev_err(smu->adev->dev, "Unsupported clock type!\n");
861 return -EINVAL;
862 }
863
864 if (min)
865 *min = dpm_table->min;
866 if (max)
867 *max = dpm_table->max;
868
869 return 0;
870 }
871
smu_v14_0_2_read_sensor(struct smu_context * smu,enum amd_pp_sensors sensor,void * data,uint32_t * size)872 static int smu_v14_0_2_read_sensor(struct smu_context *smu,
873 enum amd_pp_sensors sensor,
874 void *data,
875 uint32_t *size)
876 {
877 struct smu_table_context *table_context = &smu->smu_table;
878 PPTable_t *smc_pptable = table_context->driver_pptable;
879 int ret = 0;
880
881 switch (sensor) {
882 case AMDGPU_PP_SENSOR_MAX_FAN_RPM:
883 *(uint16_t *)data = smc_pptable->CustomSkuTable.FanMaximumRpm;
884 *size = 4;
885 break;
886 case AMDGPU_PP_SENSOR_MEM_LOAD:
887 ret = smu_v14_0_2_get_smu_metrics_data(smu,
888 METRICS_AVERAGE_MEMACTIVITY,
889 (uint32_t *)data);
890 *size = 4;
891 break;
892 case AMDGPU_PP_SENSOR_GPU_LOAD:
893 ret = smu_v14_0_2_get_smu_metrics_data(smu,
894 METRICS_AVERAGE_GFXACTIVITY,
895 (uint32_t *)data);
896 *size = 4;
897 break;
898 case AMDGPU_PP_SENSOR_GPU_AVG_POWER:
899 ret = smu_v14_0_2_get_smu_metrics_data(smu,
900 METRICS_AVERAGE_SOCKETPOWER,
901 (uint32_t *)data);
902 *size = 4;
903 break;
904 case AMDGPU_PP_SENSOR_HOTSPOT_TEMP:
905 ret = smu_v14_0_2_get_smu_metrics_data(smu,
906 METRICS_TEMPERATURE_HOTSPOT,
907 (uint32_t *)data);
908 *size = 4;
909 break;
910 case AMDGPU_PP_SENSOR_EDGE_TEMP:
911 ret = smu_v14_0_2_get_smu_metrics_data(smu,
912 METRICS_TEMPERATURE_EDGE,
913 (uint32_t *)data);
914 *size = 4;
915 break;
916 case AMDGPU_PP_SENSOR_MEM_TEMP:
917 ret = smu_v14_0_2_get_smu_metrics_data(smu,
918 METRICS_TEMPERATURE_MEM,
919 (uint32_t *)data);
920 *size = 4;
921 break;
922 case AMDGPU_PP_SENSOR_GFX_MCLK:
923 ret = smu_v14_0_2_get_smu_metrics_data(smu,
924 METRICS_CURR_UCLK,
925 (uint32_t *)data);
926 *(uint32_t *)data *= 100;
927 *size = 4;
928 break;
929 case AMDGPU_PP_SENSOR_GFX_SCLK:
930 ret = smu_v14_0_2_get_smu_metrics_data(smu,
931 METRICS_AVERAGE_GFXCLK,
932 (uint32_t *)data);
933 *(uint32_t *)data *= 100;
934 *size = 4;
935 break;
936 case AMDGPU_PP_SENSOR_VDDGFX:
937 ret = smu_v14_0_2_get_smu_metrics_data(smu,
938 METRICS_VOLTAGE_VDDGFX,
939 (uint32_t *)data);
940 *size = 4;
941 break;
942 default:
943 ret = -EOPNOTSUPP;
944 break;
945 }
946
947 return ret;
948 }
949
smu_v14_0_2_get_current_clk_freq_by_table(struct smu_context * smu,enum smu_clk_type clk_type,uint32_t * value)950 static int smu_v14_0_2_get_current_clk_freq_by_table(struct smu_context *smu,
951 enum smu_clk_type clk_type,
952 uint32_t *value)
953 {
954 MetricsMember_t member_type;
955 int clk_id = 0;
956
957 clk_id = smu_cmn_to_asic_specific_index(smu,
958 CMN2ASIC_MAPPING_CLK,
959 clk_type);
960 if (clk_id < 0)
961 return -EINVAL;
962
963 switch (clk_id) {
964 case PPCLK_GFXCLK:
965 member_type = METRICS_AVERAGE_GFXCLK;
966 break;
967 case PPCLK_UCLK:
968 member_type = METRICS_CURR_UCLK;
969 break;
970 case PPCLK_FCLK:
971 member_type = METRICS_CURR_FCLK;
972 break;
973 case PPCLK_SOCCLK:
974 member_type = METRICS_CURR_SOCCLK;
975 break;
976 case PPCLK_VCLK_0:
977 member_type = METRICS_AVERAGE_VCLK;
978 break;
979 case PPCLK_DCLK_0:
980 member_type = METRICS_AVERAGE_DCLK;
981 break;
982 case PPCLK_DCFCLK:
983 member_type = METRICS_CURR_DCEFCLK;
984 break;
985 default:
986 return -EINVAL;
987 }
988
989 return smu_v14_0_2_get_smu_metrics_data(smu,
990 member_type,
991 value);
992 }
993
smu_v14_0_2_is_od_feature_supported(struct smu_context * smu,int od_feature_bit)994 static bool smu_v14_0_2_is_od_feature_supported(struct smu_context *smu,
995 int od_feature_bit)
996 {
997 PPTable_t *pptable = smu->smu_table.driver_pptable;
998 const OverDriveLimits_t * const overdrive_upperlimits =
999 &pptable->SkuTable.OverDriveLimitsBasicMax;
1000
1001 return overdrive_upperlimits->FeatureCtrlMask & (1U << od_feature_bit);
1002 }
1003
smu_v14_0_2_get_od_setting_limits(struct smu_context * smu,int od_feature_bit,int32_t * min,int32_t * max)1004 static void smu_v14_0_2_get_od_setting_limits(struct smu_context *smu,
1005 int od_feature_bit,
1006 int32_t *min,
1007 int32_t *max)
1008 {
1009 PPTable_t *pptable = smu->smu_table.driver_pptable;
1010 const OverDriveLimits_t * const overdrive_upperlimits =
1011 &pptable->SkuTable.OverDriveLimitsBasicMax;
1012 const OverDriveLimits_t * const overdrive_lowerlimits =
1013 &pptable->SkuTable.OverDriveLimitsBasicMin;
1014 int32_t od_min_setting, od_max_setting;
1015
1016 switch (od_feature_bit) {
1017 case PP_OD_FEATURE_GFXCLK_FMIN:
1018 case PP_OD_FEATURE_GFXCLK_FMAX:
1019 od_min_setting = overdrive_lowerlimits->GfxclkFoffset;
1020 od_max_setting = overdrive_upperlimits->GfxclkFoffset;
1021 break;
1022 case PP_OD_FEATURE_UCLK_FMIN:
1023 od_min_setting = overdrive_lowerlimits->UclkFmin;
1024 od_max_setting = overdrive_upperlimits->UclkFmin;
1025 break;
1026 case PP_OD_FEATURE_UCLK_FMAX:
1027 od_min_setting = overdrive_lowerlimits->UclkFmax;
1028 od_max_setting = overdrive_upperlimits->UclkFmax;
1029 break;
1030 case PP_OD_FEATURE_GFX_VF_CURVE:
1031 od_min_setting = overdrive_lowerlimits->VoltageOffsetPerZoneBoundary[0];
1032 od_max_setting = overdrive_upperlimits->VoltageOffsetPerZoneBoundary[0];
1033 break;
1034 case PP_OD_FEATURE_FAN_CURVE_TEMP:
1035 od_min_setting = overdrive_lowerlimits->FanLinearTempPoints[0];
1036 od_max_setting = overdrive_upperlimits->FanLinearTempPoints[0];
1037 break;
1038 case PP_OD_FEATURE_FAN_CURVE_PWM:
1039 od_min_setting = overdrive_lowerlimits->FanLinearPwmPoints[0];
1040 od_max_setting = overdrive_upperlimits->FanLinearPwmPoints[0];
1041 break;
1042 case PP_OD_FEATURE_FAN_ACOUSTIC_LIMIT:
1043 od_min_setting = overdrive_lowerlimits->AcousticLimitRpmThreshold;
1044 od_max_setting = overdrive_upperlimits->AcousticLimitRpmThreshold;
1045 break;
1046 case PP_OD_FEATURE_FAN_ACOUSTIC_TARGET:
1047 od_min_setting = overdrive_lowerlimits->AcousticTargetRpmThreshold;
1048 od_max_setting = overdrive_upperlimits->AcousticTargetRpmThreshold;
1049 break;
1050 case PP_OD_FEATURE_FAN_TARGET_TEMPERATURE:
1051 od_min_setting = overdrive_lowerlimits->FanTargetTemperature;
1052 od_max_setting = overdrive_upperlimits->FanTargetTemperature;
1053 break;
1054 case PP_OD_FEATURE_FAN_MINIMUM_PWM:
1055 od_min_setting = overdrive_lowerlimits->FanMinimumPwm;
1056 od_max_setting = overdrive_upperlimits->FanMinimumPwm;
1057 break;
1058 default:
1059 od_min_setting = od_max_setting = INT_MAX;
1060 break;
1061 }
1062
1063 if (min)
1064 *min = od_min_setting;
1065 if (max)
1066 *max = od_max_setting;
1067 }
1068
smu_v14_0_2_print_clk_levels(struct smu_context * smu,enum smu_clk_type clk_type,char * buf)1069 static int smu_v14_0_2_print_clk_levels(struct smu_context *smu,
1070 enum smu_clk_type clk_type,
1071 char *buf)
1072 {
1073 struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
1074 struct smu_14_0_dpm_context *dpm_context = smu_dpm->dpm_context;
1075 OverDriveTableExternal_t *od_table =
1076 (OverDriveTableExternal_t *)smu->smu_table.overdrive_table;
1077 struct smu_14_0_dpm_table *single_dpm_table;
1078 struct smu_14_0_pcie_table *pcie_table;
1079 uint32_t gen_speed, lane_width;
1080 int i, curr_freq, size = 0;
1081 int32_t min_value, max_value;
1082 int ret = 0;
1083
1084 smu_cmn_get_sysfs_buf(&buf, &size);
1085
1086 if (amdgpu_ras_intr_triggered()) {
1087 size += sysfs_emit_at(buf, size, "unavailable\n");
1088 return size;
1089 }
1090
1091 switch (clk_type) {
1092 case SMU_SCLK:
1093 single_dpm_table = &(dpm_context->dpm_tables.gfx_table);
1094 break;
1095 case SMU_MCLK:
1096 single_dpm_table = &(dpm_context->dpm_tables.uclk_table);
1097 break;
1098 case SMU_SOCCLK:
1099 single_dpm_table = &(dpm_context->dpm_tables.soc_table);
1100 break;
1101 case SMU_FCLK:
1102 single_dpm_table = &(dpm_context->dpm_tables.fclk_table);
1103 break;
1104 case SMU_VCLK:
1105 case SMU_VCLK1:
1106 single_dpm_table = &(dpm_context->dpm_tables.vclk_table);
1107 break;
1108 case SMU_DCLK:
1109 case SMU_DCLK1:
1110 single_dpm_table = &(dpm_context->dpm_tables.dclk_table);
1111 break;
1112 case SMU_DCEFCLK:
1113 single_dpm_table = &(dpm_context->dpm_tables.dcef_table);
1114 break;
1115 default:
1116 break;
1117 }
1118
1119 switch (clk_type) {
1120 case SMU_SCLK:
1121 case SMU_MCLK:
1122 case SMU_SOCCLK:
1123 case SMU_FCLK:
1124 case SMU_VCLK:
1125 case SMU_VCLK1:
1126 case SMU_DCLK:
1127 case SMU_DCLK1:
1128 case SMU_DCEFCLK:
1129 ret = smu_v14_0_2_get_current_clk_freq_by_table(smu, clk_type, &curr_freq);
1130 if (ret) {
1131 dev_err(smu->adev->dev, "Failed to get current clock freq!");
1132 return ret;
1133 }
1134
1135 if (single_dpm_table->is_fine_grained) {
1136 /*
1137 * For fine grained dpms, there are only two dpm levels:
1138 * - level 0 -> min clock freq
1139 * - level 1 -> max clock freq
1140 * And the current clock frequency can be any value between them.
1141 * So, if the current clock frequency is not at level 0 or level 1,
1142 * we will fake it as three dpm levels:
1143 * - level 0 -> min clock freq
1144 * - level 1 -> current actual clock freq
1145 * - level 2 -> max clock freq
1146 */
1147 if ((single_dpm_table->dpm_levels[0].value != curr_freq) &&
1148 (single_dpm_table->dpm_levels[1].value != curr_freq)) {
1149 size += sysfs_emit_at(buf, size, "0: %uMhz\n",
1150 single_dpm_table->dpm_levels[0].value);
1151 size += sysfs_emit_at(buf, size, "1: %uMhz *\n",
1152 curr_freq);
1153 size += sysfs_emit_at(buf, size, "2: %uMhz\n",
1154 single_dpm_table->dpm_levels[1].value);
1155 } else {
1156 size += sysfs_emit_at(buf, size, "0: %uMhz %s\n",
1157 single_dpm_table->dpm_levels[0].value,
1158 single_dpm_table->dpm_levels[0].value == curr_freq ? "*" : "");
1159 size += sysfs_emit_at(buf, size, "1: %uMhz %s\n",
1160 single_dpm_table->dpm_levels[1].value,
1161 single_dpm_table->dpm_levels[1].value == curr_freq ? "*" : "");
1162 }
1163 } else {
1164 for (i = 0; i < single_dpm_table->count; i++)
1165 size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n",
1166 i, single_dpm_table->dpm_levels[i].value,
1167 single_dpm_table->dpm_levels[i].value == curr_freq ? "*" : "");
1168 }
1169 break;
1170 case SMU_PCIE:
1171 ret = smu_v14_0_2_get_smu_metrics_data(smu,
1172 METRICS_PCIE_RATE,
1173 &gen_speed);
1174 if (ret)
1175 return ret;
1176
1177 ret = smu_v14_0_2_get_smu_metrics_data(smu,
1178 METRICS_PCIE_WIDTH,
1179 &lane_width);
1180 if (ret)
1181 return ret;
1182
1183 pcie_table = &(dpm_context->dpm_tables.pcie_table);
1184 for (i = 0; i < pcie_table->num_of_link_levels; i++)
1185 size += sysfs_emit_at(buf, size, "%d: %s %s %dMhz %s\n", i,
1186 (pcie_table->pcie_gen[i] == 0) ? "2.5GT/s," :
1187 (pcie_table->pcie_gen[i] == 1) ? "5.0GT/s," :
1188 (pcie_table->pcie_gen[i] == 2) ? "8.0GT/s," :
1189 (pcie_table->pcie_gen[i] == 3) ? "16.0GT/s," :
1190 (pcie_table->pcie_gen[i] == 4) ? "32.0GT/s," : "",
1191 (pcie_table->pcie_lane[i] == 1) ? "x1" :
1192 (pcie_table->pcie_lane[i] == 2) ? "x2" :
1193 (pcie_table->pcie_lane[i] == 3) ? "x4" :
1194 (pcie_table->pcie_lane[i] == 4) ? "x8" :
1195 (pcie_table->pcie_lane[i] == 5) ? "x12" :
1196 (pcie_table->pcie_lane[i] == 6) ? "x16" :
1197 (pcie_table->pcie_lane[i] == 7) ? "x32" : "",
1198 pcie_table->clk_freq[i],
1199 (gen_speed == DECODE_GEN_SPEED(pcie_table->pcie_gen[i])) &&
1200 (lane_width == DECODE_LANE_WIDTH(pcie_table->pcie_lane[i])) ?
1201 "*" : "");
1202 break;
1203
1204 case SMU_OD_SCLK:
1205 if (!smu_v14_0_2_is_od_feature_supported(smu,
1206 PP_OD_FEATURE_GFXCLK_BIT))
1207 break;
1208
1209 size += sysfs_emit_at(buf, size, "OD_SCLK_OFFSET:\n");
1210 size += sysfs_emit_at(buf, size, "%dMhz\n",
1211 od_table->OverDriveTable.GfxclkFoffset);
1212 break;
1213
1214 case SMU_OD_MCLK:
1215 if (!smu_v14_0_2_is_od_feature_supported(smu,
1216 PP_OD_FEATURE_UCLK_BIT))
1217 break;
1218
1219 size += sysfs_emit_at(buf, size, "OD_MCLK:\n");
1220 size += sysfs_emit_at(buf, size, "0: %uMhz\n1: %uMHz\n",
1221 od_table->OverDriveTable.UclkFmin,
1222 od_table->OverDriveTable.UclkFmax);
1223 break;
1224
1225 case SMU_OD_VDDGFX_OFFSET:
1226 if (!smu_v14_0_2_is_od_feature_supported(smu,
1227 PP_OD_FEATURE_GFX_VF_CURVE_BIT))
1228 break;
1229
1230 size += sysfs_emit_at(buf, size, "OD_VDDGFX_OFFSET:\n");
1231 size += sysfs_emit_at(buf, size, "%dmV\n",
1232 od_table->OverDriveTable.VoltageOffsetPerZoneBoundary[0]);
1233 break;
1234
1235 case SMU_OD_FAN_CURVE:
1236 if (!smu_v14_0_2_is_od_feature_supported(smu,
1237 PP_OD_FEATURE_FAN_CURVE_BIT))
1238 break;
1239
1240 size += sysfs_emit_at(buf, size, "OD_FAN_CURVE:\n");
1241 for (i = 0; i < NUM_OD_FAN_MAX_POINTS - 1; i++)
1242 size += sysfs_emit_at(buf, size, "%d: %dC %d%%\n",
1243 i,
1244 (int)od_table->OverDriveTable.FanLinearTempPoints[i],
1245 (int)od_table->OverDriveTable.FanLinearPwmPoints[i]);
1246
1247 size += sysfs_emit_at(buf, size, "%s:\n", "OD_RANGE");
1248 smu_v14_0_2_get_od_setting_limits(smu,
1249 PP_OD_FEATURE_FAN_CURVE_TEMP,
1250 &min_value,
1251 &max_value);
1252 size += sysfs_emit_at(buf, size, "FAN_CURVE(hotspot temp): %uC %uC\n",
1253 min_value, max_value);
1254
1255 smu_v14_0_2_get_od_setting_limits(smu,
1256 PP_OD_FEATURE_FAN_CURVE_PWM,
1257 &min_value,
1258 &max_value);
1259 size += sysfs_emit_at(buf, size, "FAN_CURVE(fan speed): %u%% %u%%\n",
1260 min_value, max_value);
1261
1262 break;
1263
1264 case SMU_OD_ACOUSTIC_LIMIT:
1265 if (!smu_v14_0_2_is_od_feature_supported(smu,
1266 PP_OD_FEATURE_FAN_CURVE_BIT))
1267 break;
1268
1269 size += sysfs_emit_at(buf, size, "OD_ACOUSTIC_LIMIT:\n");
1270 size += sysfs_emit_at(buf, size, "%d\n",
1271 (int)od_table->OverDriveTable.AcousticLimitRpmThreshold);
1272
1273 size += sysfs_emit_at(buf, size, "%s:\n", "OD_RANGE");
1274 smu_v14_0_2_get_od_setting_limits(smu,
1275 PP_OD_FEATURE_FAN_ACOUSTIC_LIMIT,
1276 &min_value,
1277 &max_value);
1278 size += sysfs_emit_at(buf, size, "ACOUSTIC_LIMIT: %u %u\n",
1279 min_value, max_value);
1280 break;
1281
1282 case SMU_OD_ACOUSTIC_TARGET:
1283 if (!smu_v14_0_2_is_od_feature_supported(smu,
1284 PP_OD_FEATURE_FAN_CURVE_BIT))
1285 break;
1286
1287 size += sysfs_emit_at(buf, size, "OD_ACOUSTIC_TARGET:\n");
1288 size += sysfs_emit_at(buf, size, "%d\n",
1289 (int)od_table->OverDriveTable.AcousticTargetRpmThreshold);
1290
1291 size += sysfs_emit_at(buf, size, "%s:\n", "OD_RANGE");
1292 smu_v14_0_2_get_od_setting_limits(smu,
1293 PP_OD_FEATURE_FAN_ACOUSTIC_TARGET,
1294 &min_value,
1295 &max_value);
1296 size += sysfs_emit_at(buf, size, "ACOUSTIC_TARGET: %u %u\n",
1297 min_value, max_value);
1298 break;
1299
1300 case SMU_OD_FAN_TARGET_TEMPERATURE:
1301 if (!smu_v14_0_2_is_od_feature_supported(smu,
1302 PP_OD_FEATURE_FAN_CURVE_BIT))
1303 break;
1304
1305 size += sysfs_emit_at(buf, size, "FAN_TARGET_TEMPERATURE:\n");
1306 size += sysfs_emit_at(buf, size, "%d\n",
1307 (int)od_table->OverDriveTable.FanTargetTemperature);
1308
1309 size += sysfs_emit_at(buf, size, "%s:\n", "OD_RANGE");
1310 smu_v14_0_2_get_od_setting_limits(smu,
1311 PP_OD_FEATURE_FAN_TARGET_TEMPERATURE,
1312 &min_value,
1313 &max_value);
1314 size += sysfs_emit_at(buf, size, "TARGET_TEMPERATURE: %u %u\n",
1315 min_value, max_value);
1316 break;
1317
1318 case SMU_OD_FAN_MINIMUM_PWM:
1319 if (!smu_v14_0_2_is_od_feature_supported(smu,
1320 PP_OD_FEATURE_FAN_CURVE_BIT))
1321 break;
1322
1323 size += sysfs_emit_at(buf, size, "FAN_MINIMUM_PWM:\n");
1324 size += sysfs_emit_at(buf, size, "%d\n",
1325 (int)od_table->OverDriveTable.FanMinimumPwm);
1326
1327 size += sysfs_emit_at(buf, size, "%s:\n", "OD_RANGE");
1328 smu_v14_0_2_get_od_setting_limits(smu,
1329 PP_OD_FEATURE_FAN_MINIMUM_PWM,
1330 &min_value,
1331 &max_value);
1332 size += sysfs_emit_at(buf, size, "MINIMUM_PWM: %u %u\n",
1333 min_value, max_value);
1334 break;
1335
1336 case SMU_OD_RANGE:
1337 if (!smu_v14_0_2_is_od_feature_supported(smu, PP_OD_FEATURE_GFXCLK_BIT) &&
1338 !smu_v14_0_2_is_od_feature_supported(smu, PP_OD_FEATURE_UCLK_BIT) &&
1339 !smu_v14_0_2_is_od_feature_supported(smu, PP_OD_FEATURE_GFX_VF_CURVE_BIT))
1340 break;
1341
1342 size += sysfs_emit_at(buf, size, "%s:\n", "OD_RANGE");
1343
1344 if (smu_v14_0_2_is_od_feature_supported(smu, PP_OD_FEATURE_GFXCLK_BIT)) {
1345 smu_v14_0_2_get_od_setting_limits(smu,
1346 PP_OD_FEATURE_GFXCLK_FMAX,
1347 &min_value,
1348 &max_value);
1349 size += sysfs_emit_at(buf, size, "SCLK_OFFSET: %7dMhz %10uMhz\n",
1350 min_value, max_value);
1351 }
1352
1353 if (smu_v14_0_2_is_od_feature_supported(smu, PP_OD_FEATURE_UCLK_BIT)) {
1354 smu_v14_0_2_get_od_setting_limits(smu,
1355 PP_OD_FEATURE_UCLK_FMIN,
1356 &min_value,
1357 NULL);
1358 smu_v14_0_2_get_od_setting_limits(smu,
1359 PP_OD_FEATURE_UCLK_FMAX,
1360 NULL,
1361 &max_value);
1362 size += sysfs_emit_at(buf, size, "MCLK: %7uMhz %10uMhz\n",
1363 min_value, max_value);
1364 }
1365
1366 if (smu_v14_0_2_is_od_feature_supported(smu, PP_OD_FEATURE_GFX_VF_CURVE_BIT)) {
1367 smu_v14_0_2_get_od_setting_limits(smu,
1368 PP_OD_FEATURE_GFX_VF_CURVE,
1369 &min_value,
1370 &max_value);
1371 size += sysfs_emit_at(buf, size, "VDDGFX_OFFSET: %7dmv %10dmv\n",
1372 min_value, max_value);
1373 }
1374 break;
1375
1376 default:
1377 break;
1378 }
1379
1380 return size;
1381 }
1382
smu_v14_0_2_force_clk_levels(struct smu_context * smu,enum smu_clk_type clk_type,uint32_t mask)1383 static int smu_v14_0_2_force_clk_levels(struct smu_context *smu,
1384 enum smu_clk_type clk_type,
1385 uint32_t mask)
1386 {
1387 struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
1388 struct smu_14_0_dpm_context *dpm_context = smu_dpm->dpm_context;
1389 struct smu_14_0_dpm_table *single_dpm_table;
1390 uint32_t soft_min_level, soft_max_level;
1391 uint32_t min_freq, max_freq;
1392 int ret = 0;
1393
1394 soft_min_level = mask ? (ffs(mask) - 1) : 0;
1395 soft_max_level = mask ? (fls(mask) - 1) : 0;
1396
1397 switch (clk_type) {
1398 case SMU_GFXCLK:
1399 case SMU_SCLK:
1400 single_dpm_table = &(dpm_context->dpm_tables.gfx_table);
1401 break;
1402 case SMU_MCLK:
1403 case SMU_UCLK:
1404 single_dpm_table = &(dpm_context->dpm_tables.uclk_table);
1405 break;
1406 case SMU_SOCCLK:
1407 single_dpm_table = &(dpm_context->dpm_tables.soc_table);
1408 break;
1409 case SMU_FCLK:
1410 single_dpm_table = &(dpm_context->dpm_tables.fclk_table);
1411 break;
1412 case SMU_VCLK:
1413 case SMU_VCLK1:
1414 single_dpm_table = &(dpm_context->dpm_tables.vclk_table);
1415 break;
1416 case SMU_DCLK:
1417 case SMU_DCLK1:
1418 single_dpm_table = &(dpm_context->dpm_tables.dclk_table);
1419 break;
1420 default:
1421 break;
1422 }
1423
1424 switch (clk_type) {
1425 case SMU_GFXCLK:
1426 case SMU_SCLK:
1427 case SMU_MCLK:
1428 case SMU_UCLK:
1429 case SMU_SOCCLK:
1430 case SMU_FCLK:
1431 case SMU_VCLK:
1432 case SMU_VCLK1:
1433 case SMU_DCLK:
1434 case SMU_DCLK1:
1435 if (single_dpm_table->is_fine_grained) {
1436 /* There is only 2 levels for fine grained DPM */
1437 soft_max_level = (soft_max_level >= 1 ? 1 : 0);
1438 soft_min_level = (soft_min_level >= 1 ? 1 : 0);
1439 } else {
1440 if ((soft_max_level >= single_dpm_table->count) ||
1441 (soft_min_level >= single_dpm_table->count))
1442 return -EINVAL;
1443 }
1444
1445 min_freq = single_dpm_table->dpm_levels[soft_min_level].value;
1446 max_freq = single_dpm_table->dpm_levels[soft_max_level].value;
1447
1448 ret = smu_v14_0_set_soft_freq_limited_range(smu,
1449 clk_type,
1450 min_freq,
1451 max_freq);
1452 break;
1453 case SMU_DCEFCLK:
1454 case SMU_PCIE:
1455 default:
1456 break;
1457 }
1458
1459 return ret;
1460 }
1461
smu_v14_0_2_update_pcie_parameters(struct smu_context * smu,uint8_t pcie_gen_cap,uint8_t pcie_width_cap)1462 static int smu_v14_0_2_update_pcie_parameters(struct smu_context *smu,
1463 uint8_t pcie_gen_cap,
1464 uint8_t pcie_width_cap)
1465 {
1466 struct smu_14_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;
1467 struct smu_14_0_pcie_table *pcie_table =
1468 &dpm_context->dpm_tables.pcie_table;
1469 int num_of_levels = pcie_table->num_of_link_levels;
1470 uint32_t smu_pcie_arg;
1471 int ret, i;
1472
1473 if (!num_of_levels)
1474 return 0;
1475
1476 if (!(smu->adev->pm.pp_feature & PP_PCIE_DPM_MASK)) {
1477 if (pcie_table->pcie_gen[num_of_levels - 1] < pcie_gen_cap)
1478 pcie_gen_cap = pcie_table->pcie_gen[num_of_levels - 1];
1479
1480 if (pcie_table->pcie_lane[num_of_levels - 1] < pcie_width_cap)
1481 pcie_width_cap = pcie_table->pcie_lane[num_of_levels - 1];
1482
1483 /* Force all levels to use the same settings */
1484 for (i = 0; i < num_of_levels; i++) {
1485 pcie_table->pcie_gen[i] = pcie_gen_cap;
1486 pcie_table->pcie_lane[i] = pcie_width_cap;
1487 }
1488 } else {
1489 for (i = 0; i < num_of_levels; i++) {
1490 if (pcie_table->pcie_gen[i] > pcie_gen_cap)
1491 pcie_table->pcie_gen[i] = pcie_gen_cap;
1492 if (pcie_table->pcie_lane[i] > pcie_width_cap)
1493 pcie_table->pcie_lane[i] = pcie_width_cap;
1494 }
1495 }
1496
1497 for (i = 0; i < num_of_levels; i++) {
1498 smu_pcie_arg = i << 16;
1499 smu_pcie_arg |= pcie_table->pcie_gen[i] << 8;
1500 smu_pcie_arg |= pcie_table->pcie_lane[i];
1501
1502 ret = smu_cmn_send_smc_msg_with_param(smu,
1503 SMU_MSG_OverridePcieParameters,
1504 smu_pcie_arg,
1505 NULL);
1506 if (ret)
1507 return ret;
1508 }
1509
1510 return 0;
1511 }
1512
1513 static const struct smu_temperature_range smu14_thermal_policy[] = {
1514 {-273150, 99000, 99000, -273150, 99000, 99000, -273150, 99000, 99000},
1515 { 120000, 120000, 120000, 120000, 120000, 120000, 120000, 120000, 120000},
1516 };
1517
smu_v14_0_2_get_thermal_temperature_range(struct smu_context * smu,struct smu_temperature_range * range)1518 static int smu_v14_0_2_get_thermal_temperature_range(struct smu_context *smu,
1519 struct smu_temperature_range *range)
1520 {
1521 struct smu_table_context *table_context = &smu->smu_table;
1522 struct smu_14_0_2_powerplay_table *powerplay_table =
1523 table_context->power_play_table;
1524 PPTable_t *pptable = smu->smu_table.driver_pptable;
1525
1526 if (amdgpu_sriov_vf(smu->adev))
1527 return 0;
1528
1529 if (!range)
1530 return -EINVAL;
1531
1532 memcpy(range, &smu14_thermal_policy[0], sizeof(struct smu_temperature_range));
1533
1534 range->max = pptable->CustomSkuTable.TemperatureLimit[TEMP_EDGE] *
1535 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1536 range->edge_emergency_max = (pptable->CustomSkuTable.TemperatureLimit[TEMP_EDGE] + CTF_OFFSET_EDGE) *
1537 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1538 range->hotspot_crit_max = pptable->CustomSkuTable.TemperatureLimit[TEMP_HOTSPOT] *
1539 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1540 range->hotspot_emergency_max = (pptable->CustomSkuTable.TemperatureLimit[TEMP_HOTSPOT] + CTF_OFFSET_HOTSPOT) *
1541 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1542 range->mem_crit_max = pptable->CustomSkuTable.TemperatureLimit[TEMP_MEM] *
1543 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1544 range->mem_emergency_max = (pptable->CustomSkuTable.TemperatureLimit[TEMP_MEM] + CTF_OFFSET_MEM)*
1545 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1546 range->software_shutdown_temp = powerplay_table->software_shutdown_temp;
1547 range->software_shutdown_temp_offset = pptable->CustomSkuTable.FanAbnormalTempLimitOffset;
1548
1549 return 0;
1550 }
1551
smu_v14_0_2_populate_umd_state_clk(struct smu_context * smu)1552 static int smu_v14_0_2_populate_umd_state_clk(struct smu_context *smu)
1553 {
1554 struct smu_14_0_dpm_context *dpm_context =
1555 smu->smu_dpm.dpm_context;
1556 struct smu_14_0_dpm_table *gfx_table =
1557 &dpm_context->dpm_tables.gfx_table;
1558 struct smu_14_0_dpm_table *mem_table =
1559 &dpm_context->dpm_tables.uclk_table;
1560 struct smu_14_0_dpm_table *soc_table =
1561 &dpm_context->dpm_tables.soc_table;
1562 struct smu_14_0_dpm_table *vclk_table =
1563 &dpm_context->dpm_tables.vclk_table;
1564 struct smu_14_0_dpm_table *dclk_table =
1565 &dpm_context->dpm_tables.dclk_table;
1566 struct smu_14_0_dpm_table *fclk_table =
1567 &dpm_context->dpm_tables.fclk_table;
1568 struct smu_umd_pstate_table *pstate_table =
1569 &smu->pstate_table;
1570 struct smu_table_context *table_context = &smu->smu_table;
1571 PPTable_t *pptable = table_context->driver_pptable;
1572 DriverReportedClocks_t driver_clocks =
1573 pptable->SkuTable.DriverReportedClocks;
1574
1575 pstate_table->gfxclk_pstate.min = gfx_table->min;
1576 if (driver_clocks.GameClockAc &&
1577 (driver_clocks.GameClockAc < gfx_table->max))
1578 pstate_table->gfxclk_pstate.peak = driver_clocks.GameClockAc;
1579 else
1580 pstate_table->gfxclk_pstate.peak = gfx_table->max;
1581
1582 pstate_table->uclk_pstate.min = mem_table->min;
1583 pstate_table->uclk_pstate.peak = mem_table->max;
1584
1585 pstate_table->socclk_pstate.min = soc_table->min;
1586 pstate_table->socclk_pstate.peak = soc_table->max;
1587
1588 pstate_table->vclk_pstate.min = vclk_table->min;
1589 pstate_table->vclk_pstate.peak = vclk_table->max;
1590
1591 pstate_table->dclk_pstate.min = dclk_table->min;
1592 pstate_table->dclk_pstate.peak = dclk_table->max;
1593
1594 pstate_table->fclk_pstate.min = fclk_table->min;
1595 pstate_table->fclk_pstate.peak = fclk_table->max;
1596
1597 if (driver_clocks.BaseClockAc &&
1598 driver_clocks.BaseClockAc < gfx_table->max)
1599 pstate_table->gfxclk_pstate.standard = driver_clocks.BaseClockAc;
1600 else
1601 pstate_table->gfxclk_pstate.standard = gfx_table->max;
1602 pstate_table->uclk_pstate.standard = mem_table->max;
1603 pstate_table->socclk_pstate.standard = soc_table->min;
1604 pstate_table->vclk_pstate.standard = vclk_table->min;
1605 pstate_table->dclk_pstate.standard = dclk_table->min;
1606 pstate_table->fclk_pstate.standard = fclk_table->min;
1607
1608 return 0;
1609 }
1610
smu_v14_0_2_get_unique_id(struct smu_context * smu)1611 static void smu_v14_0_2_get_unique_id(struct smu_context *smu)
1612 {
1613 struct smu_table_context *smu_table = &smu->smu_table;
1614 SmuMetrics_t *metrics =
1615 &(((SmuMetricsExternal_t *)(smu_table->metrics_table))->SmuMetrics);
1616 struct amdgpu_device *adev = smu->adev;
1617 uint32_t upper32 = 0, lower32 = 0;
1618 int ret;
1619
1620 ret = smu_cmn_get_metrics_table(smu, NULL, false);
1621 if (ret)
1622 goto out;
1623
1624 upper32 = metrics->PublicSerialNumberUpper;
1625 lower32 = metrics->PublicSerialNumberLower;
1626
1627 out:
1628 adev->unique_id = ((uint64_t)upper32 << 32) | lower32;
1629 }
1630
smu_v14_0_2_get_fan_speed_pwm(struct smu_context * smu,uint32_t * speed)1631 static int smu_v14_0_2_get_fan_speed_pwm(struct smu_context *smu,
1632 uint32_t *speed)
1633 {
1634 int ret;
1635
1636 if (!speed)
1637 return -EINVAL;
1638
1639 ret = smu_v14_0_2_get_smu_metrics_data(smu,
1640 METRICS_CURR_FANPWM,
1641 speed);
1642 if (ret) {
1643 dev_err(smu->adev->dev, "Failed to get fan speed(PWM)!");
1644 return ret;
1645 }
1646
1647 /* Convert the PMFW output which is in percent to pwm(255) based */
1648 *speed = min(*speed * 255 / 100, (uint32_t)255);
1649
1650 return 0;
1651 }
1652
smu_v14_0_2_get_fan_speed_rpm(struct smu_context * smu,uint32_t * speed)1653 static int smu_v14_0_2_get_fan_speed_rpm(struct smu_context *smu,
1654 uint32_t *speed)
1655 {
1656 if (!speed)
1657 return -EINVAL;
1658
1659 return smu_v14_0_2_get_smu_metrics_data(smu,
1660 METRICS_CURR_FANSPEED,
1661 speed);
1662 }
1663
smu_v14_0_2_get_power_limit(struct smu_context * smu,uint32_t * current_power_limit,uint32_t * default_power_limit,uint32_t * max_power_limit,uint32_t * min_power_limit)1664 static int smu_v14_0_2_get_power_limit(struct smu_context *smu,
1665 uint32_t *current_power_limit,
1666 uint32_t *default_power_limit,
1667 uint32_t *max_power_limit,
1668 uint32_t *min_power_limit)
1669 {
1670 struct smu_table_context *table_context = &smu->smu_table;
1671 struct smu_14_0_2_powerplay_table *powerplay_table =
1672 table_context->power_play_table;
1673 PPTable_t *pptable = table_context->driver_pptable;
1674 CustomSkuTable_t *skutable = &pptable->CustomSkuTable;
1675 uint32_t power_limit, od_percent_upper = 0, od_percent_lower = 0;
1676 uint32_t msg_limit = pptable->SkuTable.MsgLimits.Power[PPT_THROTTLER_PPT0][POWER_SOURCE_AC];
1677
1678 if (smu_v14_0_get_current_power_limit(smu, &power_limit))
1679 power_limit = smu->adev->pm.ac_power ?
1680 skutable->SocketPowerLimitAc[PPT_THROTTLER_PPT0] :
1681 skutable->SocketPowerLimitDc[PPT_THROTTLER_PPT0];
1682
1683 if (current_power_limit)
1684 *current_power_limit = power_limit;
1685 if (default_power_limit)
1686 *default_power_limit = power_limit;
1687
1688 if (powerplay_table) {
1689 if (smu->od_enabled &&
1690 smu_v14_0_2_is_od_feature_supported(smu, PP_OD_FEATURE_PPT_BIT)) {
1691 od_percent_upper = pptable->SkuTable.OverDriveLimitsBasicMax.Ppt;
1692 od_percent_lower = pptable->SkuTable.OverDriveLimitsBasicMin.Ppt;
1693 } else if (smu_v14_0_2_is_od_feature_supported(smu, PP_OD_FEATURE_PPT_BIT)) {
1694 od_percent_upper = 0;
1695 od_percent_lower = pptable->SkuTable.OverDriveLimitsBasicMin.Ppt;
1696 }
1697 }
1698
1699 dev_dbg(smu->adev->dev, "od percent upper:%d, od percent lower:%d (default power: %d)\n",
1700 od_percent_upper, od_percent_lower, power_limit);
1701
1702 if (max_power_limit) {
1703 *max_power_limit = msg_limit * (100 + od_percent_upper);
1704 *max_power_limit /= 100;
1705 }
1706
1707 if (min_power_limit) {
1708 *min_power_limit = power_limit * (100 + od_percent_lower);
1709 *min_power_limit /= 100;
1710 }
1711
1712 return 0;
1713 }
1714
smu_v14_0_2_get_power_profile_mode(struct smu_context * smu,char * buf)1715 static int smu_v14_0_2_get_power_profile_mode(struct smu_context *smu,
1716 char *buf)
1717 {
1718 DpmActivityMonitorCoeffIntExternal_t activity_monitor_external;
1719 DpmActivityMonitorCoeffInt_t *activity_monitor =
1720 &(activity_monitor_external.DpmActivityMonitorCoeffInt);
1721 static const char *title[] = {
1722 "PROFILE_INDEX(NAME)",
1723 "CLOCK_TYPE(NAME)",
1724 "FPS",
1725 "MinActiveFreqType",
1726 "MinActiveFreq",
1727 "BoosterFreqType",
1728 "BoosterFreq",
1729 "PD_Data_limit_c",
1730 "PD_Data_error_coeff",
1731 "PD_Data_error_rate_coeff"};
1732 int16_t workload_type = 0;
1733 uint32_t i, size = 0;
1734 int result = 0;
1735
1736 if (!buf)
1737 return -EINVAL;
1738
1739 size += sysfs_emit_at(buf, size, "%16s %s %s %s %s %s %s %s %s %s\n",
1740 title[0], title[1], title[2], title[3], title[4], title[5],
1741 title[6], title[7], title[8], title[9]);
1742
1743 for (i = 0; i < PP_SMC_POWER_PROFILE_COUNT; i++) {
1744 /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */
1745 workload_type = smu_cmn_to_asic_specific_index(smu,
1746 CMN2ASIC_MAPPING_WORKLOAD,
1747 i);
1748 if (workload_type == -ENOTSUPP)
1749 continue;
1750 else if (workload_type < 0)
1751 return -EINVAL;
1752
1753 result = smu_cmn_update_table(smu,
1754 SMU_TABLE_ACTIVITY_MONITOR_COEFF,
1755 workload_type,
1756 (void *)(&activity_monitor_external),
1757 false);
1758 if (result) {
1759 dev_err(smu->adev->dev, "[%s] Failed to get activity monitor!", __func__);
1760 return result;
1761 }
1762
1763 size += sysfs_emit_at(buf, size, "%2d %14s%s:\n",
1764 i, amdgpu_pp_profile_name[i], (i == smu->power_profile_mode) ? "*" : " ");
1765
1766 size += sysfs_emit_at(buf, size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d\n",
1767 " ",
1768 0,
1769 "GFXCLK",
1770 activity_monitor->Gfx_FPS,
1771 activity_monitor->Gfx_MinActiveFreqType,
1772 activity_monitor->Gfx_MinActiveFreq,
1773 activity_monitor->Gfx_BoosterFreqType,
1774 activity_monitor->Gfx_BoosterFreq,
1775 activity_monitor->Gfx_PD_Data_limit_c,
1776 activity_monitor->Gfx_PD_Data_error_coeff,
1777 activity_monitor->Gfx_PD_Data_error_rate_coeff);
1778
1779 size += sysfs_emit_at(buf, size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d\n",
1780 " ",
1781 1,
1782 "FCLK",
1783 activity_monitor->Fclk_FPS,
1784 activity_monitor->Fclk_MinActiveFreqType,
1785 activity_monitor->Fclk_MinActiveFreq,
1786 activity_monitor->Fclk_BoosterFreqType,
1787 activity_monitor->Fclk_BoosterFreq,
1788 activity_monitor->Fclk_PD_Data_limit_c,
1789 activity_monitor->Fclk_PD_Data_error_coeff,
1790 activity_monitor->Fclk_PD_Data_error_rate_coeff);
1791 }
1792
1793 return size;
1794 }
1795
1796 #define SMU_14_0_2_CUSTOM_PARAMS_COUNT 9
1797 #define SMU_14_0_2_CUSTOM_PARAMS_CLOCK_COUNT 2
1798 #define SMU_14_0_2_CUSTOM_PARAMS_SIZE (SMU_14_0_2_CUSTOM_PARAMS_CLOCK_COUNT * SMU_14_0_2_CUSTOM_PARAMS_COUNT * sizeof(long))
1799
smu_v14_0_2_set_power_profile_mode_coeff(struct smu_context * smu,long * input)1800 static int smu_v14_0_2_set_power_profile_mode_coeff(struct smu_context *smu,
1801 long *input)
1802 {
1803 DpmActivityMonitorCoeffIntExternal_t activity_monitor_external;
1804 DpmActivityMonitorCoeffInt_t *activity_monitor =
1805 &(activity_monitor_external.DpmActivityMonitorCoeffInt);
1806 int ret, idx;
1807
1808 ret = smu_cmn_update_table(smu,
1809 SMU_TABLE_ACTIVITY_MONITOR_COEFF,
1810 WORKLOAD_PPLIB_CUSTOM_BIT,
1811 (void *)(&activity_monitor_external),
1812 false);
1813 if (ret) {
1814 dev_err(smu->adev->dev, "[%s] Failed to get activity monitor!", __func__);
1815 return ret;
1816 }
1817
1818 idx = 0 * SMU_14_0_2_CUSTOM_PARAMS_COUNT;
1819 if (input[idx]) {
1820 /* Gfxclk */
1821 activity_monitor->Gfx_FPS = input[idx + 1];
1822 activity_monitor->Gfx_MinActiveFreqType = input[idx + 2];
1823 activity_monitor->Gfx_MinActiveFreq = input[idx + 3];
1824 activity_monitor->Gfx_BoosterFreqType = input[idx + 4];
1825 activity_monitor->Gfx_BoosterFreq = input[idx + 5];
1826 activity_monitor->Gfx_PD_Data_limit_c = input[idx + 6];
1827 activity_monitor->Gfx_PD_Data_error_coeff = input[idx + 7];
1828 activity_monitor->Gfx_PD_Data_error_rate_coeff = input[idx + 8];
1829 }
1830 idx = 1 * SMU_14_0_2_CUSTOM_PARAMS_COUNT;
1831 if (input[idx]) {
1832 /* Fclk */
1833 activity_monitor->Fclk_FPS = input[idx + 1];
1834 activity_monitor->Fclk_MinActiveFreqType = input[idx + 2];
1835 activity_monitor->Fclk_MinActiveFreq = input[idx + 3];
1836 activity_monitor->Fclk_BoosterFreqType = input[idx + 4];
1837 activity_monitor->Fclk_BoosterFreq = input[idx + 5];
1838 activity_monitor->Fclk_PD_Data_limit_c = input[idx + 6];
1839 activity_monitor->Fclk_PD_Data_error_coeff = input[idx + 7];
1840 activity_monitor->Fclk_PD_Data_error_rate_coeff = input[idx + 8];
1841 }
1842
1843 ret = smu_cmn_update_table(smu,
1844 SMU_TABLE_ACTIVITY_MONITOR_COEFF,
1845 WORKLOAD_PPLIB_CUSTOM_BIT,
1846 (void *)(&activity_monitor_external),
1847 true);
1848 if (ret) {
1849 dev_err(smu->adev->dev, "[%s] Failed to set activity monitor!", __func__);
1850 return ret;
1851 }
1852
1853 return ret;
1854 }
1855
smu_v14_0_2_set_power_profile_mode(struct smu_context * smu,u32 workload_mask,long * custom_params,u32 custom_params_max_idx)1856 static int smu_v14_0_2_set_power_profile_mode(struct smu_context *smu,
1857 u32 workload_mask,
1858 long *custom_params,
1859 u32 custom_params_max_idx)
1860 {
1861 u32 backend_workload_mask = 0;
1862 int ret, idx = -1, i;
1863
1864 smu_cmn_get_backend_workload_mask(smu, workload_mask,
1865 &backend_workload_mask);
1866
1867 /* disable deep sleep if compute is enabled */
1868 if (workload_mask & (1 << PP_SMC_POWER_PROFILE_COMPUTE))
1869 smu_v14_0_deep_sleep_control(smu, false);
1870 else
1871 smu_v14_0_deep_sleep_control(smu, true);
1872
1873 if (workload_mask & (1 << PP_SMC_POWER_PROFILE_CUSTOM)) {
1874 if (!smu->custom_profile_params) {
1875 smu->custom_profile_params =
1876 kzalloc(SMU_14_0_2_CUSTOM_PARAMS_SIZE, GFP_KERNEL);
1877 if (!smu->custom_profile_params)
1878 return -ENOMEM;
1879 }
1880 if (custom_params && custom_params_max_idx) {
1881 if (custom_params_max_idx != SMU_14_0_2_CUSTOM_PARAMS_COUNT)
1882 return -EINVAL;
1883 if (custom_params[0] >= SMU_14_0_2_CUSTOM_PARAMS_CLOCK_COUNT)
1884 return -EINVAL;
1885 idx = custom_params[0] * SMU_14_0_2_CUSTOM_PARAMS_COUNT;
1886 smu->custom_profile_params[idx] = 1;
1887 for (i = 1; i < custom_params_max_idx; i++)
1888 smu->custom_profile_params[idx + i] = custom_params[i];
1889 }
1890 ret = smu_v14_0_2_set_power_profile_mode_coeff(smu,
1891 smu->custom_profile_params);
1892 if (ret) {
1893 if (idx != -1)
1894 smu->custom_profile_params[idx] = 0;
1895 return ret;
1896 }
1897 } else if (smu->custom_profile_params) {
1898 memset(smu->custom_profile_params, 0, SMU_14_0_2_CUSTOM_PARAMS_SIZE);
1899 }
1900
1901 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetWorkloadMask,
1902 backend_workload_mask, NULL);
1903 if (ret) {
1904 dev_err(smu->adev->dev, "Failed to set workload mask 0x%08x\n",
1905 workload_mask);
1906 if (idx != -1)
1907 smu->custom_profile_params[idx] = 0;
1908 return ret;
1909 }
1910
1911 return ret;
1912 }
1913
smu_v14_0_2_baco_enter(struct smu_context * smu)1914 static int smu_v14_0_2_baco_enter(struct smu_context *smu)
1915 {
1916 struct smu_baco_context *smu_baco = &smu->smu_baco;
1917 struct amdgpu_device *adev = smu->adev;
1918
1919 if (adev->in_runpm && smu_cmn_is_audio_func_enabled(adev))
1920 return smu_v14_0_baco_set_armd3_sequence(smu,
1921 smu_baco->maco_support ? BACO_SEQ_BAMACO : BACO_SEQ_BACO);
1922 else
1923 return smu_v14_0_baco_enter(smu);
1924 }
1925
smu_v14_0_2_baco_exit(struct smu_context * smu)1926 static int smu_v14_0_2_baco_exit(struct smu_context *smu)
1927 {
1928 struct amdgpu_device *adev = smu->adev;
1929
1930 if (adev->in_runpm && smu_cmn_is_audio_func_enabled(adev)) {
1931 /* Wait for PMFW handling for the Dstate change */
1932 usleep_range(10000, 11000);
1933 return smu_v14_0_baco_set_armd3_sequence(smu, BACO_SEQ_ULPS);
1934 } else {
1935 return smu_v14_0_baco_exit(smu);
1936 }
1937 }
1938
smu_v14_0_2_is_mode1_reset_supported(struct smu_context * smu)1939 static bool smu_v14_0_2_is_mode1_reset_supported(struct smu_context *smu)
1940 {
1941 // TODO
1942
1943 return true;
1944 }
1945
smu_v14_0_2_i2c_xfer(struct i2c_adapter * i2c_adap,struct i2c_msg * msg,int num_msgs)1946 static int smu_v14_0_2_i2c_xfer(struct i2c_adapter *i2c_adap,
1947 struct i2c_msg *msg, int num_msgs)
1948 {
1949 struct amdgpu_smu_i2c_bus *smu_i2c = i2c_get_adapdata(i2c_adap);
1950 struct amdgpu_device *adev = smu_i2c->adev;
1951 struct smu_context *smu = adev->powerplay.pp_handle;
1952 struct smu_table_context *smu_table = &smu->smu_table;
1953 struct smu_table *table = &smu_table->driver_table;
1954 SwI2cRequest_t *req, *res = (SwI2cRequest_t *)table->cpu_addr;
1955 int i, j, r, c;
1956 u16 dir;
1957
1958 if (!adev->pm.dpm_enabled)
1959 return -EBUSY;
1960
1961 req = kzalloc(sizeof(*req), GFP_KERNEL);
1962 if (!req)
1963 return -ENOMEM;
1964
1965 req->I2CcontrollerPort = smu_i2c->port;
1966 req->I2CSpeed = I2C_SPEED_FAST_400K;
1967 req->SlaveAddress = msg[0].addr << 1; /* wants an 8-bit address */
1968 dir = msg[0].flags & I2C_M_RD;
1969
1970 for (c = i = 0; i < num_msgs; i++) {
1971 for (j = 0; j < msg[i].len; j++, c++) {
1972 SwI2cCmd_t *cmd = &req->SwI2cCmds[c];
1973
1974 if (!(msg[i].flags & I2C_M_RD)) {
1975 /* write */
1976 cmd->CmdConfig |= CMDCONFIG_READWRITE_MASK;
1977 cmd->ReadWriteData = msg[i].buf[j];
1978 }
1979
1980 if ((dir ^ msg[i].flags) & I2C_M_RD) {
1981 /* The direction changes.
1982 */
1983 dir = msg[i].flags & I2C_M_RD;
1984 cmd->CmdConfig |= CMDCONFIG_RESTART_MASK;
1985 }
1986
1987 req->NumCmds++;
1988
1989 /*
1990 * Insert STOP if we are at the last byte of either last
1991 * message for the transaction or the client explicitly
1992 * requires a STOP at this particular message.
1993 */
1994 if ((j == msg[i].len - 1) &&
1995 ((i == num_msgs - 1) || (msg[i].flags & I2C_M_STOP))) {
1996 cmd->CmdConfig &= ~CMDCONFIG_RESTART_MASK;
1997 cmd->CmdConfig |= CMDCONFIG_STOP_MASK;
1998 }
1999 }
2000 }
2001 mutex_lock(&adev->pm.mutex);
2002 r = smu_cmn_update_table(smu, SMU_TABLE_I2C_COMMANDS, 0, req, true);
2003 mutex_unlock(&adev->pm.mutex);
2004 if (r)
2005 goto fail;
2006
2007 for (c = i = 0; i < num_msgs; i++) {
2008 if (!(msg[i].flags & I2C_M_RD)) {
2009 c += msg[i].len;
2010 continue;
2011 }
2012 for (j = 0; j < msg[i].len; j++, c++) {
2013 SwI2cCmd_t *cmd = &res->SwI2cCmds[c];
2014
2015 msg[i].buf[j] = cmd->ReadWriteData;
2016 }
2017 }
2018 r = num_msgs;
2019 fail:
2020 kfree(req);
2021 return r;
2022 }
2023
smu_v14_0_2_i2c_func(struct i2c_adapter * adap)2024 static u32 smu_v14_0_2_i2c_func(struct i2c_adapter *adap)
2025 {
2026 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
2027 }
2028
2029 static const struct i2c_algorithm smu_v14_0_2_i2c_algo = {
2030 .master_xfer = smu_v14_0_2_i2c_xfer,
2031 .functionality = smu_v14_0_2_i2c_func,
2032 };
2033
2034 static const struct i2c_adapter_quirks smu_v14_0_2_i2c_control_quirks = {
2035 .flags = I2C_AQ_COMB | I2C_AQ_COMB_SAME_ADDR | I2C_AQ_NO_ZERO_LEN,
2036 .max_read_len = MAX_SW_I2C_COMMANDS,
2037 .max_write_len = MAX_SW_I2C_COMMANDS,
2038 .max_comb_1st_msg_len = 2,
2039 .max_comb_2nd_msg_len = MAX_SW_I2C_COMMANDS - 2,
2040 };
2041
smu_v14_0_2_i2c_control_init(struct smu_context * smu)2042 static int smu_v14_0_2_i2c_control_init(struct smu_context *smu)
2043 {
2044 struct amdgpu_device *adev = smu->adev;
2045 int res, i;
2046
2047 for (i = 0; i < MAX_SMU_I2C_BUSES; i++) {
2048 struct amdgpu_smu_i2c_bus *smu_i2c = &adev->pm.smu_i2c[i];
2049 struct i2c_adapter *control = &smu_i2c->adapter;
2050
2051 smu_i2c->adev = adev;
2052 smu_i2c->port = i;
2053 mutex_init(&smu_i2c->mutex);
2054 control->owner = THIS_MODULE;
2055 control->dev.parent = &adev->pdev->dev;
2056 control->algo = &smu_v14_0_2_i2c_algo;
2057 snprintf(control->name, sizeof(control->name), "AMDGPU SMU %d", i);
2058 control->quirks = &smu_v14_0_2_i2c_control_quirks;
2059 i2c_set_adapdata(control, smu_i2c);
2060
2061 res = i2c_add_adapter(control);
2062 if (res) {
2063 DRM_ERROR("Failed to register hw i2c, err: %d\n", res);
2064 goto Out_err;
2065 }
2066 }
2067
2068 /* assign the buses used for the FRU EEPROM and RAS EEPROM */
2069 /* XXX ideally this would be something in a vbios data table */
2070 adev->pm.ras_eeprom_i2c_bus = &adev->pm.smu_i2c[1].adapter;
2071 adev->pm.fru_eeprom_i2c_bus = &adev->pm.smu_i2c[0].adapter;
2072
2073 return 0;
2074 Out_err:
2075 for ( ; i >= 0; i--) {
2076 struct amdgpu_smu_i2c_bus *smu_i2c = &adev->pm.smu_i2c[i];
2077 struct i2c_adapter *control = &smu_i2c->adapter;
2078
2079 i2c_del_adapter(control);
2080 }
2081 return res;
2082 }
2083
smu_v14_0_2_i2c_control_fini(struct smu_context * smu)2084 static void smu_v14_0_2_i2c_control_fini(struct smu_context *smu)
2085 {
2086 struct amdgpu_device *adev = smu->adev;
2087 int i;
2088
2089 for (i = 0; i < MAX_SMU_I2C_BUSES; i++) {
2090 struct amdgpu_smu_i2c_bus *smu_i2c = &adev->pm.smu_i2c[i];
2091 struct i2c_adapter *control = &smu_i2c->adapter;
2092
2093 i2c_del_adapter(control);
2094 }
2095 adev->pm.ras_eeprom_i2c_bus = NULL;
2096 adev->pm.fru_eeprom_i2c_bus = NULL;
2097 }
2098
smu_v14_0_2_set_mp1_state(struct smu_context * smu,enum pp_mp1_state mp1_state)2099 static int smu_v14_0_2_set_mp1_state(struct smu_context *smu,
2100 enum pp_mp1_state mp1_state)
2101 {
2102 int ret;
2103
2104 switch (mp1_state) {
2105 case PP_MP1_STATE_UNLOAD:
2106 ret = smu_cmn_set_mp1_state(smu, mp1_state);
2107 break;
2108 default:
2109 /* Ignore others */
2110 ret = 0;
2111 }
2112
2113 return ret;
2114 }
2115
smu_v14_0_2_set_df_cstate(struct smu_context * smu,enum pp_df_cstate state)2116 static int smu_v14_0_2_set_df_cstate(struct smu_context *smu,
2117 enum pp_df_cstate state)
2118 {
2119 return smu_cmn_send_smc_msg_with_param(smu,
2120 SMU_MSG_DFCstateControl,
2121 state,
2122 NULL);
2123 }
2124
smu_v14_0_2_mode1_reset(struct smu_context * smu)2125 static int smu_v14_0_2_mode1_reset(struct smu_context *smu)
2126 {
2127 int ret = 0;
2128
2129 ret = smu_cmn_send_debug_smc_msg(smu, DEBUGSMC_MSG_Mode1Reset);
2130 if (!ret) {
2131 if (amdgpu_emu_mode == 1)
2132 msleep(50000);
2133 else
2134 msleep(1000);
2135 }
2136
2137 return ret;
2138 }
2139
smu_v14_0_2_mode2_reset(struct smu_context * smu)2140 static int smu_v14_0_2_mode2_reset(struct smu_context *smu)
2141 {
2142 int ret = 0;
2143
2144 // TODO
2145
2146 return ret;
2147 }
2148
smu_v14_0_2_enable_gfx_features(struct smu_context * smu)2149 static int smu_v14_0_2_enable_gfx_features(struct smu_context *smu)
2150 {
2151 struct amdgpu_device *adev = smu->adev;
2152
2153 if (amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(14, 0, 2))
2154 return smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_EnableAllSmuFeatures,
2155 FEATURE_PWR_GFX, NULL);
2156 else
2157 return -EOPNOTSUPP;
2158 }
2159
smu_v14_0_2_set_smu_mailbox_registers(struct smu_context * smu)2160 static void smu_v14_0_2_set_smu_mailbox_registers(struct smu_context *smu)
2161 {
2162 struct amdgpu_device *adev = smu->adev;
2163
2164 smu->param_reg = SOC15_REG_OFFSET(MP1, 0, regMP1_SMN_C2PMSG_82);
2165 smu->msg_reg = SOC15_REG_OFFSET(MP1, 0, regMP1_SMN_C2PMSG_66);
2166 smu->resp_reg = SOC15_REG_OFFSET(MP1, 0, regMP1_SMN_C2PMSG_90);
2167
2168 smu->debug_param_reg = SOC15_REG_OFFSET(MP1, 0, regMP1_SMN_C2PMSG_53);
2169 smu->debug_msg_reg = SOC15_REG_OFFSET(MP1, 0, regMP1_SMN_C2PMSG_75);
2170 smu->debug_resp_reg = SOC15_REG_OFFSET(MP1, 0, regMP1_SMN_C2PMSG_54);
2171 }
2172
smu_v14_0_2_get_gpu_metrics(struct smu_context * smu,void ** table)2173 static ssize_t smu_v14_0_2_get_gpu_metrics(struct smu_context *smu,
2174 void **table)
2175 {
2176 struct smu_table_context *smu_table = &smu->smu_table;
2177 struct gpu_metrics_v1_3 *gpu_metrics =
2178 (struct gpu_metrics_v1_3 *)smu_table->gpu_metrics_table;
2179 SmuMetricsExternal_t metrics_ext;
2180 SmuMetrics_t *metrics = &metrics_ext.SmuMetrics;
2181 int ret = 0;
2182
2183 ret = smu_cmn_get_metrics_table(smu,
2184 &metrics_ext,
2185 true);
2186 if (ret)
2187 return ret;
2188
2189 smu_cmn_init_soft_gpu_metrics(gpu_metrics, 1, 3);
2190
2191 gpu_metrics->temperature_edge = metrics->AvgTemperature[TEMP_EDGE];
2192 gpu_metrics->temperature_hotspot = metrics->AvgTemperature[TEMP_HOTSPOT];
2193 gpu_metrics->temperature_mem = metrics->AvgTemperature[TEMP_MEM];
2194 gpu_metrics->temperature_vrgfx = metrics->AvgTemperature[TEMP_VR_GFX];
2195 gpu_metrics->temperature_vrsoc = metrics->AvgTemperature[TEMP_VR_SOC];
2196 gpu_metrics->temperature_vrmem = max(metrics->AvgTemperature[TEMP_VR_MEM0],
2197 metrics->AvgTemperature[TEMP_VR_MEM1]);
2198
2199 gpu_metrics->average_gfx_activity = metrics->AverageGfxActivity;
2200 gpu_metrics->average_umc_activity = metrics->AverageUclkActivity;
2201 gpu_metrics->average_mm_activity = max(metrics->AverageVcn0ActivityPercentage,
2202 metrics->Vcn1ActivityPercentage);
2203
2204 gpu_metrics->average_socket_power = metrics->AverageSocketPower;
2205 gpu_metrics->energy_accumulator = metrics->EnergyAccumulator;
2206
2207 if (metrics->AverageGfxActivity <= SMU_14_0_2_BUSY_THRESHOLD)
2208 gpu_metrics->average_gfxclk_frequency = metrics->AverageGfxclkFrequencyPostDs;
2209 else
2210 gpu_metrics->average_gfxclk_frequency = metrics->AverageGfxclkFrequencyPreDs;
2211
2212 if (metrics->AverageUclkActivity <= SMU_14_0_2_BUSY_THRESHOLD)
2213 gpu_metrics->average_uclk_frequency = metrics->AverageMemclkFrequencyPostDs;
2214 else
2215 gpu_metrics->average_uclk_frequency = metrics->AverageMemclkFrequencyPreDs;
2216
2217 gpu_metrics->average_vclk0_frequency = metrics->AverageVclk0Frequency;
2218 gpu_metrics->average_dclk0_frequency = metrics->AverageDclk0Frequency;
2219 gpu_metrics->average_vclk1_frequency = metrics->AverageVclk1Frequency;
2220 gpu_metrics->average_dclk1_frequency = metrics->AverageDclk1Frequency;
2221
2222 gpu_metrics->current_gfxclk = gpu_metrics->average_gfxclk_frequency;
2223 gpu_metrics->current_socclk = metrics->CurrClock[PPCLK_SOCCLK];
2224 gpu_metrics->current_uclk = metrics->CurrClock[PPCLK_UCLK];
2225 gpu_metrics->current_vclk0 = metrics->CurrClock[PPCLK_VCLK_0];
2226 gpu_metrics->current_dclk0 = metrics->CurrClock[PPCLK_DCLK_0];
2227 gpu_metrics->current_vclk1 = metrics->CurrClock[PPCLK_VCLK_0];
2228 gpu_metrics->current_dclk1 = metrics->CurrClock[PPCLK_DCLK_0];
2229
2230 gpu_metrics->throttle_status =
2231 smu_v14_0_2_get_throttler_status(metrics);
2232 gpu_metrics->indep_throttle_status =
2233 smu_cmn_get_indep_throttler_status(gpu_metrics->throttle_status,
2234 smu_v14_0_2_throttler_map);
2235
2236 gpu_metrics->current_fan_speed = metrics->AvgFanRpm;
2237
2238 gpu_metrics->pcie_link_width = metrics->PcieWidth;
2239 if ((metrics->PcieRate - 1) > LINK_SPEED_MAX)
2240 gpu_metrics->pcie_link_speed = pcie_gen_to_speed(1);
2241 else
2242 gpu_metrics->pcie_link_speed = pcie_gen_to_speed(metrics->PcieRate);
2243
2244 gpu_metrics->system_clock_counter = ktime_get_boottime_ns();
2245
2246 gpu_metrics->voltage_gfx = metrics->AvgVoltage[SVI_PLANE_VDD_GFX];
2247 gpu_metrics->voltage_soc = metrics->AvgVoltage[SVI_PLANE_VDD_SOC];
2248 gpu_metrics->voltage_mem = metrics->AvgVoltage[SVI_PLANE_VDDIO_MEM];
2249
2250 *table = (void *)gpu_metrics;
2251
2252 return sizeof(struct gpu_metrics_v1_3);
2253 }
2254
smu_v14_0_2_dump_od_table(struct smu_context * smu,OverDriveTableExternal_t * od_table)2255 static void smu_v14_0_2_dump_od_table(struct smu_context *smu,
2256 OverDriveTableExternal_t *od_table)
2257 {
2258 struct amdgpu_device *adev = smu->adev;
2259
2260 dev_dbg(adev->dev, "OD: Gfxclk offset: (%d)\n", od_table->OverDriveTable.GfxclkFoffset);
2261 dev_dbg(adev->dev, "OD: Uclk: (%d, %d)\n", od_table->OverDriveTable.UclkFmin,
2262 od_table->OverDriveTable.UclkFmax);
2263 }
2264
smu_v14_0_2_upload_overdrive_table(struct smu_context * smu,OverDriveTableExternal_t * od_table)2265 static int smu_v14_0_2_upload_overdrive_table(struct smu_context *smu,
2266 OverDriveTableExternal_t *od_table)
2267 {
2268 int ret;
2269 ret = smu_cmn_update_table(smu,
2270 SMU_TABLE_OVERDRIVE,
2271 0,
2272 (void *)od_table,
2273 true);
2274 if (ret)
2275 dev_err(smu->adev->dev, "Failed to upload overdrive table!\n");
2276
2277 return ret;
2278 }
2279
smu_v14_0_2_set_supported_od_feature_mask(struct smu_context * smu)2280 static void smu_v14_0_2_set_supported_od_feature_mask(struct smu_context *smu)
2281 {
2282 struct amdgpu_device *adev = smu->adev;
2283
2284 if (smu_v14_0_2_is_od_feature_supported(smu,
2285 PP_OD_FEATURE_FAN_CURVE_BIT))
2286 adev->pm.od_feature_mask |= OD_OPS_SUPPORT_FAN_CURVE_RETRIEVE |
2287 OD_OPS_SUPPORT_FAN_CURVE_SET |
2288 OD_OPS_SUPPORT_ACOUSTIC_LIMIT_THRESHOLD_RETRIEVE |
2289 OD_OPS_SUPPORT_ACOUSTIC_LIMIT_THRESHOLD_SET |
2290 OD_OPS_SUPPORT_ACOUSTIC_TARGET_THRESHOLD_RETRIEVE |
2291 OD_OPS_SUPPORT_ACOUSTIC_TARGET_THRESHOLD_SET |
2292 OD_OPS_SUPPORT_FAN_TARGET_TEMPERATURE_RETRIEVE |
2293 OD_OPS_SUPPORT_FAN_TARGET_TEMPERATURE_SET |
2294 OD_OPS_SUPPORT_FAN_MINIMUM_PWM_RETRIEVE |
2295 OD_OPS_SUPPORT_FAN_MINIMUM_PWM_SET;
2296 }
2297
smu_v14_0_2_get_overdrive_table(struct smu_context * smu,OverDriveTableExternal_t * od_table)2298 static int smu_v14_0_2_get_overdrive_table(struct smu_context *smu,
2299 OverDriveTableExternal_t *od_table)
2300 {
2301 int ret;
2302 ret = smu_cmn_update_table(smu,
2303 SMU_TABLE_OVERDRIVE,
2304 0,
2305 (void *)od_table,
2306 false);
2307 if (ret)
2308 dev_err(smu->adev->dev, "Failed to get overdrive table!\n");
2309
2310 return ret;
2311 }
2312
smu_v14_0_2_set_default_od_settings(struct smu_context * smu)2313 static int smu_v14_0_2_set_default_od_settings(struct smu_context *smu)
2314 {
2315 OverDriveTableExternal_t *od_table =
2316 (OverDriveTableExternal_t *)smu->smu_table.overdrive_table;
2317 OverDriveTableExternal_t *boot_od_table =
2318 (OverDriveTableExternal_t *)smu->smu_table.boot_overdrive_table;
2319 OverDriveTableExternal_t *user_od_table =
2320 (OverDriveTableExternal_t *)smu->smu_table.user_overdrive_table;
2321 OverDriveTableExternal_t user_od_table_bak;
2322 int ret;
2323 int i;
2324
2325 ret = smu_v14_0_2_get_overdrive_table(smu, boot_od_table);
2326 if (ret)
2327 return ret;
2328
2329 smu_v14_0_2_dump_od_table(smu, boot_od_table);
2330
2331 memcpy(od_table,
2332 boot_od_table,
2333 sizeof(OverDriveTableExternal_t));
2334
2335 /*
2336 * For S3/S4/Runpm resume, we need to setup those overdrive tables again,
2337 * but we have to preserve user defined values in "user_od_table".
2338 */
2339 if (!smu->adev->in_suspend) {
2340 memcpy(user_od_table,
2341 boot_od_table,
2342 sizeof(OverDriveTableExternal_t));
2343 smu->user_dpm_profile.user_od = false;
2344 } else if (smu->user_dpm_profile.user_od) {
2345 memcpy(&user_od_table_bak,
2346 user_od_table,
2347 sizeof(OverDriveTableExternal_t));
2348 memcpy(user_od_table,
2349 boot_od_table,
2350 sizeof(OverDriveTableExternal_t));
2351 user_od_table->OverDriveTable.GfxclkFoffset =
2352 user_od_table_bak.OverDriveTable.GfxclkFoffset;
2353 user_od_table->OverDriveTable.UclkFmin =
2354 user_od_table_bak.OverDriveTable.UclkFmin;
2355 user_od_table->OverDriveTable.UclkFmax =
2356 user_od_table_bak.OverDriveTable.UclkFmax;
2357 for (i = 0; i < PP_NUM_OD_VF_CURVE_POINTS; i++)
2358 user_od_table->OverDriveTable.VoltageOffsetPerZoneBoundary[i] =
2359 user_od_table_bak.OverDriveTable.VoltageOffsetPerZoneBoundary[i];
2360 for (i = 0; i < NUM_OD_FAN_MAX_POINTS - 1; i++) {
2361 user_od_table->OverDriveTable.FanLinearTempPoints[i] =
2362 user_od_table_bak.OverDriveTable.FanLinearTempPoints[i];
2363 user_od_table->OverDriveTable.FanLinearPwmPoints[i] =
2364 user_od_table_bak.OverDriveTable.FanLinearPwmPoints[i];
2365 }
2366 user_od_table->OverDriveTable.AcousticLimitRpmThreshold =
2367 user_od_table_bak.OverDriveTable.AcousticLimitRpmThreshold;
2368 user_od_table->OverDriveTable.AcousticTargetRpmThreshold =
2369 user_od_table_bak.OverDriveTable.AcousticTargetRpmThreshold;
2370 user_od_table->OverDriveTable.FanTargetTemperature =
2371 user_od_table_bak.OverDriveTable.FanTargetTemperature;
2372 user_od_table->OverDriveTable.FanMinimumPwm =
2373 user_od_table_bak.OverDriveTable.FanMinimumPwm;
2374 }
2375
2376 smu_v14_0_2_set_supported_od_feature_mask(smu);
2377
2378 return 0;
2379 }
2380
smu_v14_0_2_restore_user_od_settings(struct smu_context * smu)2381 static int smu_v14_0_2_restore_user_od_settings(struct smu_context *smu)
2382 {
2383 struct smu_table_context *table_context = &smu->smu_table;
2384 OverDriveTableExternal_t *od_table = table_context->overdrive_table;
2385 OverDriveTableExternal_t *user_od_table = table_context->user_overdrive_table;
2386 int res;
2387
2388 user_od_table->OverDriveTable.FeatureCtrlMask = BIT(PP_OD_FEATURE_GFXCLK_BIT) |
2389 BIT(PP_OD_FEATURE_UCLK_BIT) |
2390 BIT(PP_OD_FEATURE_GFX_VF_CURVE_BIT) |
2391 BIT(PP_OD_FEATURE_FAN_CURVE_BIT);
2392 res = smu_v14_0_2_upload_overdrive_table(smu, user_od_table);
2393 user_od_table->OverDriveTable.FeatureCtrlMask = 0;
2394 if (res == 0)
2395 memcpy(od_table, user_od_table, sizeof(OverDriveTableExternal_t));
2396
2397 return res;
2398 }
2399
smu_v14_0_2_od_restore_table_single(struct smu_context * smu,long input)2400 static int smu_v14_0_2_od_restore_table_single(struct smu_context *smu, long input)
2401 {
2402 struct smu_table_context *table_context = &smu->smu_table;
2403 OverDriveTableExternal_t *boot_overdrive_table =
2404 (OverDriveTableExternal_t *)table_context->boot_overdrive_table;
2405 OverDriveTableExternal_t *od_table =
2406 (OverDriveTableExternal_t *)table_context->overdrive_table;
2407 struct amdgpu_device *adev = smu->adev;
2408 int i;
2409
2410 switch (input) {
2411 case PP_OD_EDIT_FAN_CURVE:
2412 for (i = 0; i < NUM_OD_FAN_MAX_POINTS; i++) {
2413 od_table->OverDriveTable.FanLinearTempPoints[i] =
2414 boot_overdrive_table->OverDriveTable.FanLinearTempPoints[i];
2415 od_table->OverDriveTable.FanLinearPwmPoints[i] =
2416 boot_overdrive_table->OverDriveTable.FanLinearPwmPoints[i];
2417 }
2418 od_table->OverDriveTable.FanMode = FAN_MODE_AUTO;
2419 od_table->OverDriveTable.FeatureCtrlMask |= BIT(PP_OD_FEATURE_FAN_CURVE_BIT);
2420 break;
2421 case PP_OD_EDIT_ACOUSTIC_LIMIT:
2422 od_table->OverDriveTable.AcousticLimitRpmThreshold =
2423 boot_overdrive_table->OverDriveTable.AcousticLimitRpmThreshold;
2424 od_table->OverDriveTable.FanMode = FAN_MODE_AUTO;
2425 od_table->OverDriveTable.FeatureCtrlMask |= BIT(PP_OD_FEATURE_FAN_CURVE_BIT);
2426 break;
2427 case PP_OD_EDIT_ACOUSTIC_TARGET:
2428 od_table->OverDriveTable.AcousticTargetRpmThreshold =
2429 boot_overdrive_table->OverDriveTable.AcousticTargetRpmThreshold;
2430 od_table->OverDriveTable.FanMode = FAN_MODE_AUTO;
2431 od_table->OverDriveTable.FeatureCtrlMask |= BIT(PP_OD_FEATURE_FAN_CURVE_BIT);
2432 break;
2433 case PP_OD_EDIT_FAN_TARGET_TEMPERATURE:
2434 od_table->OverDriveTable.FanTargetTemperature =
2435 boot_overdrive_table->OverDriveTable.FanTargetTemperature;
2436 od_table->OverDriveTable.FanMode = FAN_MODE_AUTO;
2437 od_table->OverDriveTable.FeatureCtrlMask |= BIT(PP_OD_FEATURE_FAN_CURVE_BIT);
2438 break;
2439 case PP_OD_EDIT_FAN_MINIMUM_PWM:
2440 od_table->OverDriveTable.FanMinimumPwm =
2441 boot_overdrive_table->OverDriveTable.FanMinimumPwm;
2442 od_table->OverDriveTable.FanMode = FAN_MODE_AUTO;
2443 od_table->OverDriveTable.FeatureCtrlMask |= BIT(PP_OD_FEATURE_FAN_CURVE_BIT);
2444 break;
2445 default:
2446 dev_info(adev->dev, "Invalid table index: %ld\n", input);
2447 return -EINVAL;
2448 }
2449
2450 return 0;
2451 }
2452
smu_v14_0_2_od_edit_dpm_table(struct smu_context * smu,enum PP_OD_DPM_TABLE_COMMAND type,long input[],uint32_t size)2453 static int smu_v14_0_2_od_edit_dpm_table(struct smu_context *smu,
2454 enum PP_OD_DPM_TABLE_COMMAND type,
2455 long input[],
2456 uint32_t size)
2457 {
2458 struct smu_table_context *table_context = &smu->smu_table;
2459 OverDriveTableExternal_t *od_table =
2460 (OverDriveTableExternal_t *)table_context->overdrive_table;
2461 struct amdgpu_device *adev = smu->adev;
2462 uint32_t offset_of_voltageoffset;
2463 int32_t minimum, maximum;
2464 uint32_t feature_ctrlmask;
2465 int i, ret = 0;
2466
2467 switch (type) {
2468 case PP_OD_EDIT_SCLK_VDDC_TABLE:
2469 if (!smu_v14_0_2_is_od_feature_supported(smu, PP_OD_FEATURE_GFXCLK_BIT)) {
2470 dev_warn(adev->dev, "GFXCLK_LIMITS setting not supported!\n");
2471 return -ENOTSUPP;
2472 }
2473
2474 if (size != 1) {
2475 dev_info(adev->dev, "invalid number of input parameters %d\n", size);
2476 return -EINVAL;
2477 }
2478
2479 smu_v14_0_2_get_od_setting_limits(smu,
2480 PP_OD_FEATURE_GFXCLK_FMAX,
2481 &minimum,
2482 &maximum);
2483 if (input[0] < minimum ||
2484 input[0] > maximum) {
2485 dev_info(adev->dev, "GfxclkFoffset must be within [%d, %u]!\n",
2486 minimum, maximum);
2487 return -EINVAL;
2488 }
2489
2490 od_table->OverDriveTable.GfxclkFoffset = input[0];
2491 od_table->OverDriveTable.FeatureCtrlMask |= 1U << PP_OD_FEATURE_GFXCLK_BIT;
2492 break;
2493
2494 case PP_OD_EDIT_MCLK_VDDC_TABLE:
2495 if (!smu_v14_0_2_is_od_feature_supported(smu, PP_OD_FEATURE_UCLK_BIT)) {
2496 dev_warn(adev->dev, "UCLK_LIMITS setting not supported!\n");
2497 return -ENOTSUPP;
2498 }
2499
2500 for (i = 0; i < size; i += 2) {
2501 if (i + 2 > size) {
2502 dev_info(adev->dev, "invalid number of input parameters %d\n", size);
2503 return -EINVAL;
2504 }
2505
2506 switch (input[i]) {
2507 case 0:
2508 smu_v14_0_2_get_od_setting_limits(smu,
2509 PP_OD_FEATURE_UCLK_FMIN,
2510 &minimum,
2511 &maximum);
2512 if (input[i + 1] < minimum ||
2513 input[i + 1] > maximum) {
2514 dev_info(adev->dev, "UclkFmin (%ld) must be within [%u, %u]!\n",
2515 input[i + 1], minimum, maximum);
2516 return -EINVAL;
2517 }
2518
2519 od_table->OverDriveTable.UclkFmin = input[i + 1];
2520 od_table->OverDriveTable.FeatureCtrlMask |= 1U << PP_OD_FEATURE_UCLK_BIT;
2521 break;
2522
2523 case 1:
2524 smu_v14_0_2_get_od_setting_limits(smu,
2525 PP_OD_FEATURE_UCLK_FMAX,
2526 &minimum,
2527 &maximum);
2528 if (input[i + 1] < minimum ||
2529 input[i + 1] > maximum) {
2530 dev_info(adev->dev, "UclkFmax (%ld) must be within [%u, %u]!\n",
2531 input[i + 1], minimum, maximum);
2532 return -EINVAL;
2533 }
2534
2535 od_table->OverDriveTable.UclkFmax = input[i + 1];
2536 od_table->OverDriveTable.FeatureCtrlMask |= 1U << PP_OD_FEATURE_UCLK_BIT;
2537 break;
2538
2539 default:
2540 dev_info(adev->dev, "Invalid MCLK_VDDC_TABLE index: %ld\n", input[i]);
2541 dev_info(adev->dev, "Supported indices: [0:min,1:max]\n");
2542 return -EINVAL;
2543 }
2544 }
2545
2546 if (od_table->OverDriveTable.UclkFmin > od_table->OverDriveTable.UclkFmax) {
2547 dev_err(adev->dev,
2548 "Invalid setting: UclkFmin(%u) is bigger than UclkFmax(%u)\n",
2549 (uint32_t)od_table->OverDriveTable.UclkFmin,
2550 (uint32_t)od_table->OverDriveTable.UclkFmax);
2551 return -EINVAL;
2552 }
2553 break;
2554
2555 case PP_OD_EDIT_VDDGFX_OFFSET:
2556 if (!smu_v14_0_2_is_od_feature_supported(smu, PP_OD_FEATURE_GFX_VF_CURVE_BIT)) {
2557 dev_warn(adev->dev, "Gfx offset setting not supported!\n");
2558 return -ENOTSUPP;
2559 }
2560
2561 smu_v14_0_2_get_od_setting_limits(smu,
2562 PP_OD_FEATURE_GFX_VF_CURVE,
2563 &minimum,
2564 &maximum);
2565 if (input[0] < minimum ||
2566 input[0] > maximum) {
2567 dev_info(adev->dev, "Voltage offset (%ld) must be within [%d, %d]!\n",
2568 input[0], minimum, maximum);
2569 return -EINVAL;
2570 }
2571
2572 for (i = 0; i < PP_NUM_OD_VF_CURVE_POINTS; i++)
2573 od_table->OverDriveTable.VoltageOffsetPerZoneBoundary[i] = input[0];
2574 od_table->OverDriveTable.FeatureCtrlMask |= BIT(PP_OD_FEATURE_GFX_VF_CURVE_BIT);
2575 break;
2576
2577 case PP_OD_EDIT_FAN_CURVE:
2578 if (!smu_v14_0_2_is_od_feature_supported(smu, PP_OD_FEATURE_FAN_CURVE_BIT)) {
2579 dev_warn(adev->dev, "Fan curve setting not supported!\n");
2580 return -ENOTSUPP;
2581 }
2582
2583 if (input[0] >= NUM_OD_FAN_MAX_POINTS - 1 ||
2584 input[0] < 0)
2585 return -EINVAL;
2586
2587 smu_v14_0_2_get_od_setting_limits(smu,
2588 PP_OD_FEATURE_FAN_CURVE_TEMP,
2589 &minimum,
2590 &maximum);
2591 if (input[1] < minimum ||
2592 input[1] > maximum) {
2593 dev_info(adev->dev, "Fan curve temp setting(%ld) must be within [%d, %d]!\n",
2594 input[1], minimum, maximum);
2595 return -EINVAL;
2596 }
2597
2598 smu_v14_0_2_get_od_setting_limits(smu,
2599 PP_OD_FEATURE_FAN_CURVE_PWM,
2600 &minimum,
2601 &maximum);
2602 if (input[2] < minimum ||
2603 input[2] > maximum) {
2604 dev_info(adev->dev, "Fan curve pwm setting(%ld) must be within [%d, %d]!\n",
2605 input[2], minimum, maximum);
2606 return -EINVAL;
2607 }
2608
2609 od_table->OverDriveTable.FanLinearTempPoints[input[0]] = input[1];
2610 od_table->OverDriveTable.FanLinearPwmPoints[input[0]] = input[2];
2611 od_table->OverDriveTable.FanMode = FAN_MODE_MANUAL_LINEAR;
2612 od_table->OverDriveTable.FeatureCtrlMask |= BIT(PP_OD_FEATURE_FAN_CURVE_BIT);
2613 break;
2614
2615 case PP_OD_EDIT_ACOUSTIC_LIMIT:
2616 if (!smu_v14_0_2_is_od_feature_supported(smu, PP_OD_FEATURE_FAN_CURVE_BIT)) {
2617 dev_warn(adev->dev, "Fan curve setting not supported!\n");
2618 return -ENOTSUPP;
2619 }
2620
2621 smu_v14_0_2_get_od_setting_limits(smu,
2622 PP_OD_FEATURE_FAN_ACOUSTIC_LIMIT,
2623 &minimum,
2624 &maximum);
2625 if (input[0] < minimum ||
2626 input[0] > maximum) {
2627 dev_info(adev->dev, "acoustic limit threshold setting(%ld) must be within [%d, %d]!\n",
2628 input[0], minimum, maximum);
2629 return -EINVAL;
2630 }
2631
2632 od_table->OverDriveTable.AcousticLimitRpmThreshold = input[0];
2633 od_table->OverDriveTable.FanMode = FAN_MODE_AUTO;
2634 od_table->OverDriveTable.FeatureCtrlMask |= BIT(PP_OD_FEATURE_FAN_CURVE_BIT);
2635 break;
2636
2637 case PP_OD_EDIT_ACOUSTIC_TARGET:
2638 if (!smu_v14_0_2_is_od_feature_supported(smu, PP_OD_FEATURE_FAN_CURVE_BIT)) {
2639 dev_warn(adev->dev, "Fan curve setting not supported!\n");
2640 return -ENOTSUPP;
2641 }
2642
2643 smu_v14_0_2_get_od_setting_limits(smu,
2644 PP_OD_FEATURE_FAN_ACOUSTIC_TARGET,
2645 &minimum,
2646 &maximum);
2647 if (input[0] < minimum ||
2648 input[0] > maximum) {
2649 dev_info(adev->dev, "acoustic target threshold setting(%ld) must be within [%d, %d]!\n",
2650 input[0], minimum, maximum);
2651 return -EINVAL;
2652 }
2653
2654 od_table->OverDriveTable.AcousticTargetRpmThreshold = input[0];
2655 od_table->OverDriveTable.FanMode = FAN_MODE_AUTO;
2656 od_table->OverDriveTable.FeatureCtrlMask |= BIT(PP_OD_FEATURE_FAN_CURVE_BIT);
2657 break;
2658
2659 case PP_OD_EDIT_FAN_TARGET_TEMPERATURE:
2660 if (!smu_v14_0_2_is_od_feature_supported(smu, PP_OD_FEATURE_FAN_CURVE_BIT)) {
2661 dev_warn(adev->dev, "Fan curve setting not supported!\n");
2662 return -ENOTSUPP;
2663 }
2664
2665 smu_v14_0_2_get_od_setting_limits(smu,
2666 PP_OD_FEATURE_FAN_TARGET_TEMPERATURE,
2667 &minimum,
2668 &maximum);
2669 if (input[0] < minimum ||
2670 input[0] > maximum) {
2671 dev_info(adev->dev, "fan target temperature setting(%ld) must be within [%d, %d]!\n",
2672 input[0], minimum, maximum);
2673 return -EINVAL;
2674 }
2675
2676 od_table->OverDriveTable.FanTargetTemperature = input[0];
2677 od_table->OverDriveTable.FanMode = FAN_MODE_AUTO;
2678 od_table->OverDriveTable.FeatureCtrlMask |= BIT(PP_OD_FEATURE_FAN_CURVE_BIT);
2679 break;
2680
2681 case PP_OD_EDIT_FAN_MINIMUM_PWM:
2682 if (!smu_v14_0_2_is_od_feature_supported(smu, PP_OD_FEATURE_FAN_CURVE_BIT)) {
2683 dev_warn(adev->dev, "Fan curve setting not supported!\n");
2684 return -ENOTSUPP;
2685 }
2686
2687 smu_v14_0_2_get_od_setting_limits(smu,
2688 PP_OD_FEATURE_FAN_MINIMUM_PWM,
2689 &minimum,
2690 &maximum);
2691 if (input[0] < minimum ||
2692 input[0] > maximum) {
2693 dev_info(adev->dev, "fan minimum pwm setting(%ld) must be within [%d, %d]!\n",
2694 input[0], minimum, maximum);
2695 return -EINVAL;
2696 }
2697
2698 od_table->OverDriveTable.FanMinimumPwm = input[0];
2699 od_table->OverDriveTable.FanMode = FAN_MODE_AUTO;
2700 od_table->OverDriveTable.FeatureCtrlMask |= BIT(PP_OD_FEATURE_FAN_CURVE_BIT);
2701 break;
2702
2703 case PP_OD_RESTORE_DEFAULT_TABLE:
2704 if (size == 1) {
2705 ret = smu_v14_0_2_od_restore_table_single(smu, input[0]);
2706 if (ret)
2707 return ret;
2708 } else {
2709 feature_ctrlmask = od_table->OverDriveTable.FeatureCtrlMask;
2710 memcpy(od_table,
2711 table_context->boot_overdrive_table,
2712 sizeof(OverDriveTableExternal_t));
2713 od_table->OverDriveTable.FeatureCtrlMask = feature_ctrlmask;
2714 }
2715 fallthrough;
2716 case PP_OD_COMMIT_DPM_TABLE:
2717 /*
2718 * The member below instructs PMFW the settings focused in
2719 * this single operation.
2720 * `uint32_t FeatureCtrlMask;`
2721 * It does not contain actual informations about user's custom
2722 * settings. Thus we do not cache it.
2723 */
2724 offset_of_voltageoffset = offsetof(OverDriveTable_t, VoltageOffsetPerZoneBoundary);
2725 if (memcmp((u8 *)od_table + offset_of_voltageoffset,
2726 table_context->user_overdrive_table + offset_of_voltageoffset,
2727 sizeof(OverDriveTableExternal_t) - offset_of_voltageoffset)) {
2728 smu_v14_0_2_dump_od_table(smu, od_table);
2729
2730 ret = smu_v14_0_2_upload_overdrive_table(smu, od_table);
2731 if (ret) {
2732 dev_err(adev->dev, "Failed to upload overdrive table!\n");
2733 return ret;
2734 }
2735
2736 od_table->OverDriveTable.FeatureCtrlMask = 0;
2737 memcpy(table_context->user_overdrive_table + offset_of_voltageoffset,
2738 (u8 *)od_table + offset_of_voltageoffset,
2739 sizeof(OverDriveTableExternal_t) - offset_of_voltageoffset);
2740
2741 if (!memcmp(table_context->user_overdrive_table,
2742 table_context->boot_overdrive_table,
2743 sizeof(OverDriveTableExternal_t)))
2744 smu->user_dpm_profile.user_od = false;
2745 else
2746 smu->user_dpm_profile.user_od = true;
2747 }
2748 break;
2749
2750 default:
2751 return -ENOSYS;
2752 }
2753
2754 return ret;
2755 }
2756
smu_v14_0_2_set_power_limit(struct smu_context * smu,enum smu_ppt_limit_type limit_type,uint32_t limit)2757 static int smu_v14_0_2_set_power_limit(struct smu_context *smu,
2758 enum smu_ppt_limit_type limit_type,
2759 uint32_t limit)
2760 {
2761 PPTable_t *pptable = smu->smu_table.driver_pptable;
2762 uint32_t msg_limit = pptable->SkuTable.MsgLimits.Power[PPT_THROTTLER_PPT0][POWER_SOURCE_AC];
2763 struct smu_table_context *table_context = &smu->smu_table;
2764 OverDriveTableExternal_t *od_table =
2765 (OverDriveTableExternal_t *)table_context->overdrive_table;
2766 int ret = 0;
2767
2768 if (limit_type != SMU_DEFAULT_PPT_LIMIT)
2769 return -EINVAL;
2770
2771 if (limit <= msg_limit) {
2772 if (smu->current_power_limit > msg_limit) {
2773 od_table->OverDriveTable.Ppt = 0;
2774 od_table->OverDriveTable.FeatureCtrlMask |= 1U << PP_OD_FEATURE_PPT_BIT;
2775
2776 ret = smu_v14_0_2_upload_overdrive_table(smu, od_table);
2777 if (ret) {
2778 dev_err(smu->adev->dev, "Failed to upload overdrive table!\n");
2779 return ret;
2780 }
2781 }
2782 return smu_v14_0_set_power_limit(smu, limit_type, limit);
2783 } else if (smu->od_enabled) {
2784 ret = smu_v14_0_set_power_limit(smu, limit_type, msg_limit);
2785 if (ret)
2786 return ret;
2787
2788 od_table->OverDriveTable.Ppt = (limit * 100) / msg_limit - 100;
2789 od_table->OverDriveTable.FeatureCtrlMask |= 1U << PP_OD_FEATURE_PPT_BIT;
2790
2791 ret = smu_v14_0_2_upload_overdrive_table(smu, od_table);
2792 if (ret) {
2793 dev_err(smu->adev->dev, "Failed to upload overdrive table!\n");
2794 return ret;
2795 }
2796
2797 smu->current_power_limit = limit;
2798 } else {
2799 return -EINVAL;
2800 }
2801
2802 return 0;
2803 }
2804
2805 static const struct pptable_funcs smu_v14_0_2_ppt_funcs = {
2806 .get_allowed_feature_mask = smu_v14_0_2_get_allowed_feature_mask,
2807 .set_default_dpm_table = smu_v14_0_2_set_default_dpm_table,
2808 .i2c_init = smu_v14_0_2_i2c_control_init,
2809 .i2c_fini = smu_v14_0_2_i2c_control_fini,
2810 .is_dpm_running = smu_v14_0_2_is_dpm_running,
2811 .dump_pptable = smu_v14_0_2_dump_pptable,
2812 .init_microcode = smu_v14_0_init_microcode,
2813 .load_microcode = smu_v14_0_load_microcode,
2814 .fini_microcode = smu_v14_0_fini_microcode,
2815 .init_smc_tables = smu_v14_0_2_init_smc_tables,
2816 .fini_smc_tables = smu_v14_0_fini_smc_tables,
2817 .init_power = smu_v14_0_init_power,
2818 .fini_power = smu_v14_0_fini_power,
2819 .check_fw_status = smu_v14_0_check_fw_status,
2820 .setup_pptable = smu_v14_0_2_setup_pptable,
2821 .check_fw_version = smu_v14_0_check_fw_version,
2822 .set_driver_table_location = smu_v14_0_set_driver_table_location,
2823 .system_features_control = smu_v14_0_system_features_control,
2824 .set_allowed_mask = smu_v14_0_set_allowed_mask,
2825 .get_enabled_mask = smu_cmn_get_enabled_mask,
2826 .dpm_set_vcn_enable = smu_v14_0_set_vcn_enable,
2827 .dpm_set_jpeg_enable = smu_v14_0_set_jpeg_enable,
2828 .get_dpm_ultimate_freq = smu_v14_0_2_get_dpm_ultimate_freq,
2829 .get_vbios_bootup_values = smu_v14_0_get_vbios_bootup_values,
2830 .read_sensor = smu_v14_0_2_read_sensor,
2831 .feature_is_enabled = smu_cmn_feature_is_enabled,
2832 .print_clk_levels = smu_v14_0_2_print_clk_levels,
2833 .force_clk_levels = smu_v14_0_2_force_clk_levels,
2834 .update_pcie_parameters = smu_v14_0_2_update_pcie_parameters,
2835 .get_thermal_temperature_range = smu_v14_0_2_get_thermal_temperature_range,
2836 .register_irq_handler = smu_v14_0_register_irq_handler,
2837 .enable_thermal_alert = smu_v14_0_enable_thermal_alert,
2838 .disable_thermal_alert = smu_v14_0_disable_thermal_alert,
2839 .notify_memory_pool_location = smu_v14_0_notify_memory_pool_location,
2840 .get_gpu_metrics = smu_v14_0_2_get_gpu_metrics,
2841 .set_soft_freq_limited_range = smu_v14_0_set_soft_freq_limited_range,
2842 .set_default_od_settings = smu_v14_0_2_set_default_od_settings,
2843 .restore_user_od_settings = smu_v14_0_2_restore_user_od_settings,
2844 .od_edit_dpm_table = smu_v14_0_2_od_edit_dpm_table,
2845 .init_pptable_microcode = smu_v14_0_init_pptable_microcode,
2846 .populate_umd_state_clk = smu_v14_0_2_populate_umd_state_clk,
2847 .set_performance_level = smu_v14_0_set_performance_level,
2848 .gfx_off_control = smu_v14_0_gfx_off_control,
2849 .get_unique_id = smu_v14_0_2_get_unique_id,
2850 .get_fan_speed_pwm = smu_v14_0_2_get_fan_speed_pwm,
2851 .get_fan_speed_rpm = smu_v14_0_2_get_fan_speed_rpm,
2852 .get_power_limit = smu_v14_0_2_get_power_limit,
2853 .set_power_limit = smu_v14_0_2_set_power_limit,
2854 .get_power_profile_mode = smu_v14_0_2_get_power_profile_mode,
2855 .set_power_profile_mode = smu_v14_0_2_set_power_profile_mode,
2856 .run_btc = smu_v14_0_run_btc,
2857 .get_pp_feature_mask = smu_cmn_get_pp_feature_mask,
2858 .set_pp_feature_mask = smu_cmn_set_pp_feature_mask,
2859 .set_tool_table_location = smu_v14_0_set_tool_table_location,
2860 .deep_sleep_control = smu_v14_0_deep_sleep_control,
2861 .gfx_ulv_control = smu_v14_0_gfx_ulv_control,
2862 .get_bamaco_support = smu_v14_0_get_bamaco_support,
2863 .baco_get_state = smu_v14_0_baco_get_state,
2864 .baco_set_state = smu_v14_0_baco_set_state,
2865 .baco_enter = smu_v14_0_2_baco_enter,
2866 .baco_exit = smu_v14_0_2_baco_exit,
2867 .mode1_reset_is_support = smu_v14_0_2_is_mode1_reset_supported,
2868 .mode1_reset = smu_v14_0_2_mode1_reset,
2869 .mode2_reset = smu_v14_0_2_mode2_reset,
2870 .enable_gfx_features = smu_v14_0_2_enable_gfx_features,
2871 .set_mp1_state = smu_v14_0_2_set_mp1_state,
2872 .set_df_cstate = smu_v14_0_2_set_df_cstate,
2873 #if 0
2874 .gpo_control = smu_v14_0_gpo_control,
2875 #endif
2876 };
2877
smu_v14_0_2_set_ppt_funcs(struct smu_context * smu)2878 void smu_v14_0_2_set_ppt_funcs(struct smu_context *smu)
2879 {
2880 smu->ppt_funcs = &smu_v14_0_2_ppt_funcs;
2881 smu->message_map = smu_v14_0_2_message_map;
2882 smu->clock_map = smu_v14_0_2_clk_map;
2883 smu->feature_map = smu_v14_0_2_feature_mask_map;
2884 smu->table_map = smu_v14_0_2_table_map;
2885 smu->pwr_src_map = smu_v14_0_2_pwr_src_map;
2886 smu->workload_map = smu_v14_0_2_workload_map;
2887 smu_v14_0_2_set_smu_mailbox_registers(smu);
2888 }
2889