1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (c) 2018, The Linux Foundation. All rights reserved.
4 * datasheet: https://www.ti.com/lit/ds/symlink/sn65dsi86.pdf
5 */
6
7 #include <linux/atomic.h>
8 #include <linux/auxiliary_bus.h>
9 #include <linux/bitfield.h>
10 #include <linux/bits.h>
11 #include <linux/clk.h>
12 #include <linux/debugfs.h>
13 #include <linux/gpio/consumer.h>
14 #include <linux/gpio/driver.h>
15 #include <linux/i2c.h>
16 #include <linux/iopoll.h>
17 #include <linux/module.h>
18 #include <linux/of_graph.h>
19 #include <linux/pm_runtime.h>
20 #include <linux/pwm.h>
21 #include <linux/regmap.h>
22 #include <linux/regulator/consumer.h>
23
24 #include <linux/unaligned.h>
25
26 #include <drm/display/drm_dp_aux_bus.h>
27 #include <drm/display/drm_dp_helper.h>
28 #include <drm/drm_atomic.h>
29 #include <drm/drm_atomic_helper.h>
30 #include <drm/drm_bridge.h>
31 #include <drm/drm_bridge_connector.h>
32 #include <drm/drm_edid.h>
33 #include <drm/drm_mipi_dsi.h>
34 #include <drm/drm_of.h>
35 #include <drm/drm_panel.h>
36 #include <drm/drm_print.h>
37 #include <drm/drm_probe_helper.h>
38
39 #define SN_DEVICE_REV_REG 0x08
40 #define SN_DPPLL_SRC_REG 0x0A
41 #define DPPLL_CLK_SRC_DSICLK BIT(0)
42 #define REFCLK_FREQ_MASK GENMASK(3, 1)
43 #define REFCLK_FREQ(x) ((x) << 1)
44 #define DPPLL_SRC_DP_PLL_LOCK BIT(7)
45 #define SN_PLL_ENABLE_REG 0x0D
46 #define SN_DSI_LANES_REG 0x10
47 #define CHA_DSI_LANES_MASK GENMASK(4, 3)
48 #define CHA_DSI_LANES(x) ((x) << 3)
49 #define SN_DSIA_CLK_FREQ_REG 0x12
50 #define SN_CHA_ACTIVE_LINE_LENGTH_LOW_REG 0x20
51 #define SN_CHA_VERTICAL_DISPLAY_SIZE_LOW_REG 0x24
52 #define SN_CHA_HSYNC_PULSE_WIDTH_LOW_REG 0x2C
53 #define SN_CHA_HSYNC_PULSE_WIDTH_HIGH_REG 0x2D
54 #define CHA_HSYNC_POLARITY BIT(7)
55 #define SN_CHA_VSYNC_PULSE_WIDTH_LOW_REG 0x30
56 #define SN_CHA_VSYNC_PULSE_WIDTH_HIGH_REG 0x31
57 #define CHA_VSYNC_POLARITY BIT(7)
58 #define SN_CHA_HORIZONTAL_BACK_PORCH_REG 0x34
59 #define SN_CHA_VERTICAL_BACK_PORCH_REG 0x36
60 #define SN_CHA_HORIZONTAL_FRONT_PORCH_REG 0x38
61 #define SN_CHA_VERTICAL_FRONT_PORCH_REG 0x3A
62 #define SN_LN_ASSIGN_REG 0x59
63 #define LN_ASSIGN_WIDTH 2
64 #define SN_ENH_FRAME_REG 0x5A
65 #define VSTREAM_ENABLE BIT(3)
66 #define LN_POLRS_OFFSET 4
67 #define LN_POLRS_MASK 0xf0
68 #define SN_DATA_FORMAT_REG 0x5B
69 #define BPP_18_RGB BIT(0)
70 #define SN_HPD_DISABLE_REG 0x5C
71 #define HPD_DISABLE BIT(0)
72 #define HPD_DEBOUNCED_STATE BIT(4)
73 #define SN_GPIO_IO_REG 0x5E
74 #define SN_GPIO_INPUT_SHIFT 4
75 #define SN_GPIO_OUTPUT_SHIFT 0
76 #define SN_GPIO_CTRL_REG 0x5F
77 #define SN_GPIO_MUX_INPUT 0
78 #define SN_GPIO_MUX_OUTPUT 1
79 #define SN_GPIO_MUX_SPECIAL 2
80 #define SN_GPIO_MUX_MASK 0x3
81 #define SN_AUX_WDATA_REG(x) (0x64 + (x))
82 #define SN_AUX_ADDR_19_16_REG 0x74
83 #define SN_AUX_ADDR_15_8_REG 0x75
84 #define SN_AUX_ADDR_7_0_REG 0x76
85 #define SN_AUX_ADDR_MASK GENMASK(19, 0)
86 #define SN_AUX_LENGTH_REG 0x77
87 #define SN_AUX_CMD_REG 0x78
88 #define AUX_CMD_SEND BIT(0)
89 #define AUX_CMD_REQ(x) ((x) << 4)
90 #define SN_AUX_RDATA_REG(x) (0x79 + (x))
91 #define SN_SSC_CONFIG_REG 0x93
92 #define DP_NUM_LANES_MASK GENMASK(5, 4)
93 #define DP_NUM_LANES(x) ((x) << 4)
94 #define SN_DATARATE_CONFIG_REG 0x94
95 #define DP_DATARATE_MASK GENMASK(7, 5)
96 #define DP_DATARATE(x) ((x) << 5)
97 #define SN_TRAINING_SETTING_REG 0x95
98 #define SCRAMBLE_DISABLE BIT(4)
99 #define SN_ML_TX_MODE_REG 0x96
100 #define ML_TX_MAIN_LINK_OFF 0
101 #define ML_TX_NORMAL_MODE BIT(0)
102 #define SN_PWM_PRE_DIV_REG 0xA0
103 #define SN_BACKLIGHT_SCALE_REG 0xA1
104 #define BACKLIGHT_SCALE_MAX 0xFFFF
105 #define SN_BACKLIGHT_REG 0xA3
106 #define SN_PWM_EN_INV_REG 0xA5
107 #define SN_PWM_INV_MASK BIT(0)
108 #define SN_PWM_EN_MASK BIT(1)
109 #define SN_AUX_CMD_STATUS_REG 0xF4
110 #define AUX_IRQ_STATUS_AUX_RPLY_TOUT BIT(3)
111 #define AUX_IRQ_STATUS_AUX_SHORT BIT(5)
112 #define AUX_IRQ_STATUS_NAT_I2C_FAIL BIT(6)
113
114 #define MIN_DSI_CLK_FREQ_MHZ 40
115
116 /* fudge factor required to account for 8b/10b encoding */
117 #define DP_CLK_FUDGE_NUM 10
118 #define DP_CLK_FUDGE_DEN 8
119
120 /* Matches DP_AUX_MAX_PAYLOAD_BYTES (for now) */
121 #define SN_AUX_MAX_PAYLOAD_BYTES 16
122
123 #define SN_REGULATOR_SUPPLY_NUM 4
124
125 #define SN_MAX_DP_LANES 4
126 #define SN_NUM_GPIOS 4
127 #define SN_GPIO_PHYSICAL_OFFSET 1
128
129 #define SN_LINK_TRAINING_TRIES 10
130
131 #define SN_PWM_GPIO_IDX 3 /* 4th GPIO */
132
133 /**
134 * struct ti_sn65dsi86 - Platform data for ti-sn65dsi86 driver.
135 * @bridge_aux: AUX-bus sub device for MIPI-to-eDP bridge functionality.
136 * @gpio_aux: AUX-bus sub device for GPIO controller functionality.
137 * @aux_aux: AUX-bus sub device for eDP AUX channel functionality.
138 * @pwm_aux: AUX-bus sub device for PWM controller functionality.
139 *
140 * @dev: Pointer to the top level (i2c) device.
141 * @regmap: Regmap for accessing i2c.
142 * @aux: Our aux channel.
143 * @bridge: Our bridge.
144 * @connector: Our connector.
145 * @host_node: Remote DSI node.
146 * @dsi: Our MIPI DSI source.
147 * @refclk: Our reference clock.
148 * @next_bridge: The bridge on the eDP side.
149 * @enable_gpio: The GPIO we toggle to enable the bridge.
150 * @supplies: Data for bulk enabling/disabling our regulators.
151 * @dp_lanes: Count of dp_lanes we're using.
152 * @ln_assign: Value to program to the LN_ASSIGN register.
153 * @ln_polrs: Value for the 4-bit LN_POLRS field of SN_ENH_FRAME_REG.
154 * @comms_enabled: If true then communication over the aux channel is enabled.
155 * @comms_mutex: Protects modification of comms_enabled.
156 *
157 * @gchip: If we expose our GPIOs, this is used.
158 * @gchip_output: A cache of whether we've set GPIOs to output. This
159 * serves double-duty of keeping track of the direction and
160 * also keeping track of whether we've incremented the
161 * pm_runtime reference count for this pin, which we do
162 * whenever a pin is configured as an output. This is a
163 * bitmap so we can do atomic ops on it without an extra
164 * lock so concurrent users of our 4 GPIOs don't stomp on
165 * each other's read-modify-write.
166 *
167 * @pchip: pwm_chip if the PWM is exposed.
168 * @pwm_enabled: Used to track if the PWM signal is currently enabled.
169 * @pwm_pin_busy: Track if GPIO4 is currently requested for GPIO or PWM.
170 * @pwm_refclk_freq: Cache for the reference clock input to the PWM.
171 */
172 struct ti_sn65dsi86 {
173 struct auxiliary_device *bridge_aux;
174 struct auxiliary_device *gpio_aux;
175 struct auxiliary_device *aux_aux;
176 struct auxiliary_device *pwm_aux;
177
178 struct device *dev;
179 struct regmap *regmap;
180 struct drm_dp_aux aux;
181 struct drm_bridge bridge;
182 struct drm_connector *connector;
183 struct device_node *host_node;
184 struct mipi_dsi_device *dsi;
185 struct clk *refclk;
186 struct drm_bridge *next_bridge;
187 struct gpio_desc *enable_gpio;
188 struct regulator_bulk_data supplies[SN_REGULATOR_SUPPLY_NUM];
189 int dp_lanes;
190 u8 ln_assign;
191 u8 ln_polrs;
192 bool comms_enabled;
193 struct mutex comms_mutex;
194
195 #if defined(CONFIG_OF_GPIO)
196 struct gpio_chip gchip;
197 DECLARE_BITMAP(gchip_output, SN_NUM_GPIOS);
198 #endif
199 #if defined(CONFIG_PWM)
200 struct pwm_chip *pchip;
201 bool pwm_enabled;
202 atomic_t pwm_pin_busy;
203 #endif
204 unsigned int pwm_refclk_freq;
205 };
206
207 static const struct regmap_range ti_sn65dsi86_volatile_ranges[] = {
208 { .range_min = 0, .range_max = 0xFF },
209 };
210
211 static const struct regmap_access_table ti_sn_bridge_volatile_table = {
212 .yes_ranges = ti_sn65dsi86_volatile_ranges,
213 .n_yes_ranges = ARRAY_SIZE(ti_sn65dsi86_volatile_ranges),
214 };
215
216 static const struct regmap_config ti_sn65dsi86_regmap_config = {
217 .reg_bits = 8,
218 .val_bits = 8,
219 .volatile_table = &ti_sn_bridge_volatile_table,
220 .cache_type = REGCACHE_NONE,
221 .max_register = 0xFF,
222 };
223
ti_sn65dsi86_read_u16(struct ti_sn65dsi86 * pdata,unsigned int reg,u16 * val)224 static int __maybe_unused ti_sn65dsi86_read_u16(struct ti_sn65dsi86 *pdata,
225 unsigned int reg, u16 *val)
226 {
227 u8 buf[2];
228 int ret;
229
230 ret = regmap_bulk_read(pdata->regmap, reg, buf, ARRAY_SIZE(buf));
231 if (ret)
232 return ret;
233
234 *val = buf[0] | (buf[1] << 8);
235
236 return 0;
237 }
238
ti_sn65dsi86_write_u16(struct ti_sn65dsi86 * pdata,unsigned int reg,u16 val)239 static void ti_sn65dsi86_write_u16(struct ti_sn65dsi86 *pdata,
240 unsigned int reg, u16 val)
241 {
242 u8 buf[2] = { val & 0xff, val >> 8 };
243
244 regmap_bulk_write(pdata->regmap, reg, buf, ARRAY_SIZE(buf));
245 }
246
ti_sn_bridge_get_dsi_freq(struct ti_sn65dsi86 * pdata)247 static u32 ti_sn_bridge_get_dsi_freq(struct ti_sn65dsi86 *pdata)
248 {
249 u32 bit_rate_khz, clk_freq_khz;
250 struct drm_display_mode *mode =
251 &pdata->bridge.encoder->crtc->state->adjusted_mode;
252
253 bit_rate_khz = mode->clock *
254 mipi_dsi_pixel_format_to_bpp(pdata->dsi->format);
255 clk_freq_khz = bit_rate_khz / (pdata->dsi->lanes * 2);
256
257 return clk_freq_khz;
258 }
259
260 /* clk frequencies supported by bridge in Hz in case derived from REFCLK pin */
261 static const u32 ti_sn_bridge_refclk_lut[] = {
262 12000000,
263 19200000,
264 26000000,
265 27000000,
266 38400000,
267 };
268
269 /* clk frequencies supported by bridge in Hz in case derived from DACP/N pin */
270 static const u32 ti_sn_bridge_dsiclk_lut[] = {
271 468000000,
272 384000000,
273 416000000,
274 486000000,
275 460800000,
276 };
277
ti_sn_bridge_set_refclk_freq(struct ti_sn65dsi86 * pdata)278 static void ti_sn_bridge_set_refclk_freq(struct ti_sn65dsi86 *pdata)
279 {
280 int i;
281 u32 refclk_rate;
282 const u32 *refclk_lut;
283 size_t refclk_lut_size;
284
285 if (pdata->refclk) {
286 refclk_rate = clk_get_rate(pdata->refclk);
287 refclk_lut = ti_sn_bridge_refclk_lut;
288 refclk_lut_size = ARRAY_SIZE(ti_sn_bridge_refclk_lut);
289 clk_prepare_enable(pdata->refclk);
290 } else {
291 refclk_rate = ti_sn_bridge_get_dsi_freq(pdata) * 1000;
292 refclk_lut = ti_sn_bridge_dsiclk_lut;
293 refclk_lut_size = ARRAY_SIZE(ti_sn_bridge_dsiclk_lut);
294 }
295
296 /* for i equals to refclk_lut_size means default frequency */
297 for (i = 0; i < refclk_lut_size; i++)
298 if (refclk_lut[i] == refclk_rate)
299 break;
300
301 /* avoid buffer overflow and "1" is the default rate in the datasheet. */
302 if (i >= refclk_lut_size)
303 i = 1;
304
305 regmap_update_bits(pdata->regmap, SN_DPPLL_SRC_REG, REFCLK_FREQ_MASK,
306 REFCLK_FREQ(i));
307
308 /*
309 * The PWM refclk is based on the value written to SN_DPPLL_SRC_REG,
310 * regardless of its actual sourcing.
311 */
312 pdata->pwm_refclk_freq = ti_sn_bridge_refclk_lut[i];
313 }
314
ti_sn65dsi86_enable_comms(struct ti_sn65dsi86 * pdata)315 static void ti_sn65dsi86_enable_comms(struct ti_sn65dsi86 *pdata)
316 {
317 mutex_lock(&pdata->comms_mutex);
318
319 /* configure bridge ref_clk */
320 ti_sn_bridge_set_refclk_freq(pdata);
321
322 /*
323 * HPD on this bridge chip is a bit useless. This is an eDP bridge
324 * so the HPD is an internal signal that's only there to signal that
325 * the panel is done powering up. ...but the bridge chip debounces
326 * this signal by between 100 ms and 400 ms (depending on process,
327 * voltage, and temperate--I measured it at about 200 ms). One
328 * particular panel asserted HPD 84 ms after it was powered on meaning
329 * that we saw HPD 284 ms after power on. ...but the same panel said
330 * that instead of looking at HPD you could just hardcode a delay of
331 * 200 ms. We'll assume that the panel driver will have the hardcoded
332 * delay in its prepare and always disable HPD.
333 *
334 * For DisplayPort bridge type, we need HPD. So we use the bridge type
335 * to conditionally disable HPD.
336 * NOTE: The bridge type is set in ti_sn_bridge_probe() but enable_comms()
337 * can be called before. So for DisplayPort, HPD will be enabled once
338 * bridge type is set. We are using bridge type instead of "no-hpd"
339 * property because it is not used properly in devicetree description
340 * and hence is unreliable.
341 */
342
343 if (pdata->bridge.type != DRM_MODE_CONNECTOR_DisplayPort)
344 regmap_update_bits(pdata->regmap, SN_HPD_DISABLE_REG, HPD_DISABLE,
345 HPD_DISABLE);
346
347 pdata->comms_enabled = true;
348
349 mutex_unlock(&pdata->comms_mutex);
350 }
351
ti_sn65dsi86_disable_comms(struct ti_sn65dsi86 * pdata)352 static void ti_sn65dsi86_disable_comms(struct ti_sn65dsi86 *pdata)
353 {
354 mutex_lock(&pdata->comms_mutex);
355
356 pdata->comms_enabled = false;
357 clk_disable_unprepare(pdata->refclk);
358
359 mutex_unlock(&pdata->comms_mutex);
360 }
361
ti_sn65dsi86_resume(struct device * dev)362 static int __maybe_unused ti_sn65dsi86_resume(struct device *dev)
363 {
364 struct ti_sn65dsi86 *pdata = dev_get_drvdata(dev);
365 int ret;
366
367 ret = regulator_bulk_enable(SN_REGULATOR_SUPPLY_NUM, pdata->supplies);
368 if (ret) {
369 DRM_ERROR("failed to enable supplies %d\n", ret);
370 return ret;
371 }
372
373 /* td2: min 100 us after regulators before enabling the GPIO */
374 usleep_range(100, 110);
375
376 gpiod_set_value_cansleep(pdata->enable_gpio, 1);
377
378 /*
379 * After EN is deasserted and an external clock is detected, the bridge
380 * will sample GPIO3:1 to determine its frequency. The driver will
381 * overwrite this setting in ti_sn_bridge_set_refclk_freq(). But this is
382 * racy. Thus we have to wait a couple of us. According to the datasheet
383 * the GPIO lines has to be stable at least 5 us (td5) but it seems that
384 * is not enough and the refclk frequency value is still lost or
385 * overwritten by the bridge itself. Waiting for 20us seems to work.
386 */
387 usleep_range(20, 30);
388
389 /*
390 * If we have a reference clock we can enable communication w/ the
391 * panel (including the aux channel) w/out any need for an input clock
392 * so we can do it in resume which lets us read the EDID before
393 * pre_enable(). Without a reference clock we need the MIPI reference
394 * clock so reading early doesn't work.
395 */
396 if (pdata->refclk)
397 ti_sn65dsi86_enable_comms(pdata);
398
399 return ret;
400 }
401
ti_sn65dsi86_suspend(struct device * dev)402 static int __maybe_unused ti_sn65dsi86_suspend(struct device *dev)
403 {
404 struct ti_sn65dsi86 *pdata = dev_get_drvdata(dev);
405 int ret;
406
407 if (pdata->refclk)
408 ti_sn65dsi86_disable_comms(pdata);
409
410 gpiod_set_value_cansleep(pdata->enable_gpio, 0);
411
412 ret = regulator_bulk_disable(SN_REGULATOR_SUPPLY_NUM, pdata->supplies);
413 if (ret)
414 DRM_ERROR("failed to disable supplies %d\n", ret);
415
416 return ret;
417 }
418
419 static const struct dev_pm_ops ti_sn65dsi86_pm_ops = {
420 SET_RUNTIME_PM_OPS(ti_sn65dsi86_suspend, ti_sn65dsi86_resume, NULL)
421 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
422 pm_runtime_force_resume)
423 };
424
status_show(struct seq_file * s,void * data)425 static int status_show(struct seq_file *s, void *data)
426 {
427 struct ti_sn65dsi86 *pdata = s->private;
428 unsigned int reg, val;
429
430 seq_puts(s, "STATUS REGISTERS:\n");
431
432 pm_runtime_get_sync(pdata->dev);
433
434 /* IRQ Status Registers, see Table 31 in datasheet */
435 for (reg = 0xf0; reg <= 0xf8; reg++) {
436 regmap_read(pdata->regmap, reg, &val);
437 seq_printf(s, "[0x%02x] = 0x%08x\n", reg, val);
438 }
439
440 pm_runtime_put_autosuspend(pdata->dev);
441
442 return 0;
443 }
444 DEFINE_SHOW_ATTRIBUTE(status);
445
446 /* -----------------------------------------------------------------------------
447 * Auxiliary Devices (*not* AUX)
448 */
449
ti_sn65dsi86_uninit_aux(void * data)450 static void ti_sn65dsi86_uninit_aux(void *data)
451 {
452 auxiliary_device_uninit(data);
453 }
454
ti_sn65dsi86_delete_aux(void * data)455 static void ti_sn65dsi86_delete_aux(void *data)
456 {
457 auxiliary_device_delete(data);
458 }
459
ti_sn65dsi86_aux_device_release(struct device * dev)460 static void ti_sn65dsi86_aux_device_release(struct device *dev)
461 {
462 struct auxiliary_device *aux = container_of(dev, struct auxiliary_device, dev);
463
464 kfree(aux);
465 }
466
ti_sn65dsi86_add_aux_device(struct ti_sn65dsi86 * pdata,struct auxiliary_device ** aux_out,const char * name)467 static int ti_sn65dsi86_add_aux_device(struct ti_sn65dsi86 *pdata,
468 struct auxiliary_device **aux_out,
469 const char *name)
470 {
471 struct device *dev = pdata->dev;
472 const struct i2c_client *client = to_i2c_client(dev);
473 struct auxiliary_device *aux;
474 int ret;
475
476 aux = kzalloc(sizeof(*aux), GFP_KERNEL);
477 if (!aux)
478 return -ENOMEM;
479
480 aux->name = name;
481 aux->id = (client->adapter->nr << 10) | client->addr;
482 aux->dev.parent = dev;
483 aux->dev.release = ti_sn65dsi86_aux_device_release;
484 device_set_of_node_from_dev(&aux->dev, dev);
485 ret = auxiliary_device_init(aux);
486 if (ret) {
487 kfree(aux);
488 return ret;
489 }
490 ret = devm_add_action_or_reset(dev, ti_sn65dsi86_uninit_aux, aux);
491 if (ret)
492 return ret;
493
494 ret = auxiliary_device_add(aux);
495 if (ret)
496 return ret;
497 ret = devm_add_action_or_reset(dev, ti_sn65dsi86_delete_aux, aux);
498 if (!ret)
499 *aux_out = aux;
500
501 return ret;
502 }
503
504 /* -----------------------------------------------------------------------------
505 * AUX Adapter
506 */
507
aux_to_ti_sn65dsi86(struct drm_dp_aux * aux)508 static struct ti_sn65dsi86 *aux_to_ti_sn65dsi86(struct drm_dp_aux *aux)
509 {
510 return container_of(aux, struct ti_sn65dsi86, aux);
511 }
512
ti_sn_aux_transfer(struct drm_dp_aux * aux,struct drm_dp_aux_msg * msg)513 static ssize_t ti_sn_aux_transfer(struct drm_dp_aux *aux,
514 struct drm_dp_aux_msg *msg)
515 {
516 struct ti_sn65dsi86 *pdata = aux_to_ti_sn65dsi86(aux);
517 u32 request = msg->request & ~(DP_AUX_I2C_MOT | DP_AUX_I2C_WRITE_STATUS_UPDATE);
518 u32 request_val = AUX_CMD_REQ(msg->request);
519 u8 *buf = msg->buffer;
520 unsigned int len = msg->size;
521 unsigned int short_len;
522 unsigned int val;
523 int ret;
524 u8 addr_len[SN_AUX_LENGTH_REG + 1 - SN_AUX_ADDR_19_16_REG];
525
526 if (len > SN_AUX_MAX_PAYLOAD_BYTES)
527 return -EINVAL;
528
529 pm_runtime_get_sync(pdata->dev);
530 mutex_lock(&pdata->comms_mutex);
531
532 /*
533 * If someone tries to do a DDC over AUX transaction before pre_enable()
534 * on a device without a dedicated reference clock then we just can't
535 * do it. Fail right away. This prevents non-refclk users from reading
536 * the EDID before enabling the panel but such is life.
537 */
538 if (!pdata->comms_enabled) {
539 ret = -EIO;
540 goto exit;
541 }
542
543 switch (request) {
544 case DP_AUX_NATIVE_WRITE:
545 case DP_AUX_I2C_WRITE:
546 case DP_AUX_NATIVE_READ:
547 case DP_AUX_I2C_READ:
548 regmap_write(pdata->regmap, SN_AUX_CMD_REG, request_val);
549 /* Assume it's good */
550 msg->reply = 0;
551 break;
552 default:
553 ret = -EINVAL;
554 goto exit;
555 }
556
557 BUILD_BUG_ON(sizeof(addr_len) != sizeof(__be32));
558 put_unaligned_be32((msg->address & SN_AUX_ADDR_MASK) << 8 | len,
559 addr_len);
560 regmap_bulk_write(pdata->regmap, SN_AUX_ADDR_19_16_REG, addr_len,
561 ARRAY_SIZE(addr_len));
562
563 if (request == DP_AUX_NATIVE_WRITE || request == DP_AUX_I2C_WRITE)
564 regmap_bulk_write(pdata->regmap, SN_AUX_WDATA_REG(0), buf, len);
565
566 /* Clear old status bits before start so we don't get confused */
567 regmap_write(pdata->regmap, SN_AUX_CMD_STATUS_REG,
568 AUX_IRQ_STATUS_NAT_I2C_FAIL |
569 AUX_IRQ_STATUS_AUX_RPLY_TOUT |
570 AUX_IRQ_STATUS_AUX_SHORT);
571
572 regmap_write(pdata->regmap, SN_AUX_CMD_REG, request_val | AUX_CMD_SEND);
573
574 /* Zero delay loop because i2c transactions are slow already */
575 ret = regmap_read_poll_timeout(pdata->regmap, SN_AUX_CMD_REG, val,
576 !(val & AUX_CMD_SEND), 0, 50 * 1000);
577 if (ret)
578 goto exit;
579
580 ret = regmap_read(pdata->regmap, SN_AUX_CMD_STATUS_REG, &val);
581 if (ret)
582 goto exit;
583
584 if (val & AUX_IRQ_STATUS_AUX_RPLY_TOUT) {
585 /*
586 * The hardware tried the message seven times per the DP spec
587 * but it hit a timeout. We ignore defers here because they're
588 * handled in hardware.
589 */
590 ret = -ETIMEDOUT;
591 goto exit;
592 }
593
594 if (val & AUX_IRQ_STATUS_AUX_SHORT) {
595 ret = regmap_read(pdata->regmap, SN_AUX_LENGTH_REG, &short_len);
596 len = min(len, short_len);
597 if (ret)
598 goto exit;
599 } else if (val & AUX_IRQ_STATUS_NAT_I2C_FAIL) {
600 switch (request) {
601 case DP_AUX_I2C_WRITE:
602 case DP_AUX_I2C_READ:
603 msg->reply |= DP_AUX_I2C_REPLY_NACK;
604 break;
605 case DP_AUX_NATIVE_READ:
606 case DP_AUX_NATIVE_WRITE:
607 msg->reply |= DP_AUX_NATIVE_REPLY_NACK;
608 break;
609 }
610 len = 0;
611 goto exit;
612 }
613
614 if (request != DP_AUX_NATIVE_WRITE && request != DP_AUX_I2C_WRITE && len != 0)
615 ret = regmap_bulk_read(pdata->regmap, SN_AUX_RDATA_REG(0), buf, len);
616
617 exit:
618 mutex_unlock(&pdata->comms_mutex);
619 pm_runtime_mark_last_busy(pdata->dev);
620 pm_runtime_put_autosuspend(pdata->dev);
621
622 if (ret)
623 return ret;
624 return len;
625 }
626
ti_sn_aux_wait_hpd_asserted(struct drm_dp_aux * aux,unsigned long wait_us)627 static int ti_sn_aux_wait_hpd_asserted(struct drm_dp_aux *aux, unsigned long wait_us)
628 {
629 /*
630 * The HPD in this chip is a bit useless (See comment in
631 * ti_sn65dsi86_enable_comms) so if our driver is expected to wait
632 * for HPD, we just assume it's asserted after the wait_us delay.
633 *
634 * In case we are asked to wait forever (wait_us=0) take conservative
635 * 500ms delay.
636 */
637 if (wait_us == 0)
638 wait_us = 500000;
639
640 usleep_range(wait_us, wait_us + 1000);
641
642 return 0;
643 }
644
ti_sn_aux_probe(struct auxiliary_device * adev,const struct auxiliary_device_id * id)645 static int ti_sn_aux_probe(struct auxiliary_device *adev,
646 const struct auxiliary_device_id *id)
647 {
648 struct ti_sn65dsi86 *pdata = dev_get_drvdata(adev->dev.parent);
649 int ret;
650
651 pdata->aux.name = "ti-sn65dsi86-aux";
652 pdata->aux.dev = &adev->dev;
653 pdata->aux.transfer = ti_sn_aux_transfer;
654 pdata->aux.wait_hpd_asserted = ti_sn_aux_wait_hpd_asserted;
655 drm_dp_aux_init(&pdata->aux);
656
657 ret = devm_of_dp_aux_populate_ep_devices(&pdata->aux);
658 if (ret)
659 return ret;
660
661 /*
662 * The eDP to MIPI bridge parts don't work until the AUX channel is
663 * setup so we don't add it in the main driver probe, we add it now.
664 */
665 return ti_sn65dsi86_add_aux_device(pdata, &pdata->bridge_aux, "bridge");
666 }
667
668 static const struct auxiliary_device_id ti_sn_aux_id_table[] = {
669 { .name = "ti_sn65dsi86.aux", },
670 {},
671 };
672
673 static struct auxiliary_driver ti_sn_aux_driver = {
674 .name = "aux",
675 .probe = ti_sn_aux_probe,
676 .id_table = ti_sn_aux_id_table,
677 };
678
679 /*------------------------------------------------------------------------------
680 * DRM Bridge
681 */
682
bridge_to_ti_sn65dsi86(struct drm_bridge * bridge)683 static struct ti_sn65dsi86 *bridge_to_ti_sn65dsi86(struct drm_bridge *bridge)
684 {
685 return container_of(bridge, struct ti_sn65dsi86, bridge);
686 }
687
ti_sn_attach_host(struct auxiliary_device * adev,struct ti_sn65dsi86 * pdata)688 static int ti_sn_attach_host(struct auxiliary_device *adev, struct ti_sn65dsi86 *pdata)
689 {
690 int val;
691 struct mipi_dsi_host *host;
692 struct mipi_dsi_device *dsi;
693 struct device *dev = pdata->dev;
694 const struct mipi_dsi_device_info info = { .type = "ti_sn_bridge",
695 .channel = 0,
696 .node = NULL,
697 };
698
699 host = of_find_mipi_dsi_host_by_node(pdata->host_node);
700 if (!host)
701 return -EPROBE_DEFER;
702
703 dsi = devm_mipi_dsi_device_register_full(&adev->dev, host, &info);
704 if (IS_ERR(dsi))
705 return PTR_ERR(dsi);
706
707 /* TODO: setting to 4 MIPI lanes always for now */
708 dsi->lanes = 4;
709 dsi->format = MIPI_DSI_FMT_RGB888;
710 dsi->mode_flags = MIPI_DSI_MODE_VIDEO;
711
712 /* check if continuous dsi clock is required or not */
713 pm_runtime_get_sync(dev);
714 regmap_read(pdata->regmap, SN_DPPLL_SRC_REG, &val);
715 pm_runtime_put_autosuspend(dev);
716 if (!(val & DPPLL_CLK_SRC_DSICLK))
717 dsi->mode_flags |= MIPI_DSI_CLOCK_NON_CONTINUOUS;
718
719 pdata->dsi = dsi;
720
721 return devm_mipi_dsi_attach(&adev->dev, dsi);
722 }
723
ti_sn_bridge_attach(struct drm_bridge * bridge,enum drm_bridge_attach_flags flags)724 static int ti_sn_bridge_attach(struct drm_bridge *bridge,
725 enum drm_bridge_attach_flags flags)
726 {
727 struct ti_sn65dsi86 *pdata = bridge_to_ti_sn65dsi86(bridge);
728 int ret;
729
730 pdata->aux.drm_dev = bridge->dev;
731 ret = drm_dp_aux_register(&pdata->aux);
732 if (ret < 0) {
733 drm_err(bridge->dev, "Failed to register DP AUX channel: %d\n", ret);
734 return ret;
735 }
736
737 /*
738 * Attach the next bridge.
739 * We never want the next bridge to *also* create a connector.
740 */
741 ret = drm_bridge_attach(bridge->encoder, pdata->next_bridge,
742 &pdata->bridge, flags | DRM_BRIDGE_ATTACH_NO_CONNECTOR);
743 if (ret < 0)
744 goto err_initted_aux;
745
746 if (flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR)
747 return 0;
748
749 pdata->connector = drm_bridge_connector_init(pdata->bridge.dev,
750 pdata->bridge.encoder);
751 if (IS_ERR(pdata->connector)) {
752 ret = PTR_ERR(pdata->connector);
753 goto err_initted_aux;
754 }
755
756 drm_connector_attach_encoder(pdata->connector, pdata->bridge.encoder);
757
758 return 0;
759
760 err_initted_aux:
761 drm_dp_aux_unregister(&pdata->aux);
762 return ret;
763 }
764
ti_sn_bridge_detach(struct drm_bridge * bridge)765 static void ti_sn_bridge_detach(struct drm_bridge *bridge)
766 {
767 drm_dp_aux_unregister(&bridge_to_ti_sn65dsi86(bridge)->aux);
768 }
769
770 static enum drm_mode_status
ti_sn_bridge_mode_valid(struct drm_bridge * bridge,const struct drm_display_info * info,const struct drm_display_mode * mode)771 ti_sn_bridge_mode_valid(struct drm_bridge *bridge,
772 const struct drm_display_info *info,
773 const struct drm_display_mode *mode)
774 {
775 /* maximum supported resolution is 4K at 60 fps */
776 if (mode->clock > 594000)
777 return MODE_CLOCK_HIGH;
778
779 /*
780 * The front and back porch registers are 8 bits, and pulse width
781 * registers are 15 bits, so reject any modes with larger periods.
782 */
783
784 if ((mode->hsync_start - mode->hdisplay) > 0xff)
785 return MODE_HBLANK_WIDE;
786
787 if ((mode->vsync_start - mode->vdisplay) > 0xff)
788 return MODE_VBLANK_WIDE;
789
790 if ((mode->hsync_end - mode->hsync_start) > 0x7fff)
791 return MODE_HSYNC_WIDE;
792
793 if ((mode->vsync_end - mode->vsync_start) > 0x7fff)
794 return MODE_VSYNC_WIDE;
795
796 if ((mode->htotal - mode->hsync_end) > 0xff)
797 return MODE_HBLANK_WIDE;
798
799 if ((mode->vtotal - mode->vsync_end) > 0xff)
800 return MODE_VBLANK_WIDE;
801
802 return MODE_OK;
803 }
804
ti_sn_bridge_atomic_disable(struct drm_bridge * bridge,struct drm_bridge_state * old_bridge_state)805 static void ti_sn_bridge_atomic_disable(struct drm_bridge *bridge,
806 struct drm_bridge_state *old_bridge_state)
807 {
808 struct ti_sn65dsi86 *pdata = bridge_to_ti_sn65dsi86(bridge);
809
810 /* disable video stream */
811 regmap_update_bits(pdata->regmap, SN_ENH_FRAME_REG, VSTREAM_ENABLE, 0);
812 }
813
ti_sn_bridge_set_dsi_rate(struct ti_sn65dsi86 * pdata)814 static void ti_sn_bridge_set_dsi_rate(struct ti_sn65dsi86 *pdata)
815 {
816 unsigned int bit_rate_mhz, clk_freq_mhz;
817 unsigned int val;
818 struct drm_display_mode *mode =
819 &pdata->bridge.encoder->crtc->state->adjusted_mode;
820
821 /* set DSIA clk frequency */
822 bit_rate_mhz = (mode->clock / 1000) *
823 mipi_dsi_pixel_format_to_bpp(pdata->dsi->format);
824 clk_freq_mhz = bit_rate_mhz / (pdata->dsi->lanes * 2);
825
826 /* for each increment in val, frequency increases by 5MHz */
827 val = (MIN_DSI_CLK_FREQ_MHZ / 5) +
828 (((clk_freq_mhz - MIN_DSI_CLK_FREQ_MHZ) / 5) & 0xFF);
829 regmap_write(pdata->regmap, SN_DSIA_CLK_FREQ_REG, val);
830 }
831
ti_sn_bridge_get_bpp(struct drm_connector * connector)832 static unsigned int ti_sn_bridge_get_bpp(struct drm_connector *connector)
833 {
834 if (connector->display_info.bpc <= 6)
835 return 18;
836 else
837 return 24;
838 }
839
840 /*
841 * LUT index corresponds to register value and
842 * LUT values corresponds to dp data rate supported
843 * by the bridge in Mbps unit.
844 */
845 static const unsigned int ti_sn_bridge_dp_rate_lut[] = {
846 0, 1620, 2160, 2430, 2700, 3240, 4320, 5400
847 };
848
ti_sn_bridge_calc_min_dp_rate_idx(struct ti_sn65dsi86 * pdata,unsigned int bpp)849 static int ti_sn_bridge_calc_min_dp_rate_idx(struct ti_sn65dsi86 *pdata, unsigned int bpp)
850 {
851 unsigned int bit_rate_khz, dp_rate_mhz;
852 unsigned int i;
853 struct drm_display_mode *mode =
854 &pdata->bridge.encoder->crtc->state->adjusted_mode;
855
856 /* Calculate minimum bit rate based on our pixel clock. */
857 bit_rate_khz = mode->clock * bpp;
858
859 /* Calculate minimum DP data rate, taking 80% as per DP spec */
860 dp_rate_mhz = DIV_ROUND_UP(bit_rate_khz * DP_CLK_FUDGE_NUM,
861 1000 * pdata->dp_lanes * DP_CLK_FUDGE_DEN);
862
863 for (i = 1; i < ARRAY_SIZE(ti_sn_bridge_dp_rate_lut) - 1; i++)
864 if (ti_sn_bridge_dp_rate_lut[i] >= dp_rate_mhz)
865 break;
866
867 return i;
868 }
869
ti_sn_bridge_read_valid_rates(struct ti_sn65dsi86 * pdata)870 static unsigned int ti_sn_bridge_read_valid_rates(struct ti_sn65dsi86 *pdata)
871 {
872 unsigned int valid_rates = 0;
873 unsigned int rate_per_200khz;
874 unsigned int rate_mhz;
875 u8 dpcd_val;
876 int ret;
877 int i, j;
878
879 ret = drm_dp_dpcd_readb(&pdata->aux, DP_EDP_DPCD_REV, &dpcd_val);
880 if (ret != 1) {
881 DRM_DEV_ERROR(pdata->dev,
882 "Can't read eDP rev (%d), assuming 1.1\n", ret);
883 dpcd_val = DP_EDP_11;
884 }
885
886 if (dpcd_val >= DP_EDP_14) {
887 /* eDP 1.4 devices must provide a custom table */
888 __le16 sink_rates[DP_MAX_SUPPORTED_RATES];
889
890 ret = drm_dp_dpcd_read(&pdata->aux, DP_SUPPORTED_LINK_RATES,
891 sink_rates, sizeof(sink_rates));
892
893 if (ret != sizeof(sink_rates)) {
894 DRM_DEV_ERROR(pdata->dev,
895 "Can't read supported rate table (%d)\n", ret);
896
897 /* By zeroing we'll fall back to DP_MAX_LINK_RATE. */
898 memset(sink_rates, 0, sizeof(sink_rates));
899 }
900
901 for (i = 0; i < ARRAY_SIZE(sink_rates); i++) {
902 rate_per_200khz = le16_to_cpu(sink_rates[i]);
903
904 if (!rate_per_200khz)
905 break;
906
907 rate_mhz = rate_per_200khz * 200 / 1000;
908 for (j = 0;
909 j < ARRAY_SIZE(ti_sn_bridge_dp_rate_lut);
910 j++) {
911 if (ti_sn_bridge_dp_rate_lut[j] == rate_mhz)
912 valid_rates |= BIT(j);
913 }
914 }
915
916 for (i = 0; i < ARRAY_SIZE(ti_sn_bridge_dp_rate_lut); i++) {
917 if (valid_rates & BIT(i))
918 return valid_rates;
919 }
920 DRM_DEV_ERROR(pdata->dev,
921 "No matching eDP rates in table; falling back\n");
922 }
923
924 /* On older versions best we can do is use DP_MAX_LINK_RATE */
925 ret = drm_dp_dpcd_readb(&pdata->aux, DP_MAX_LINK_RATE, &dpcd_val);
926 if (ret != 1) {
927 DRM_DEV_ERROR(pdata->dev,
928 "Can't read max rate (%d); assuming 5.4 GHz\n",
929 ret);
930 dpcd_val = DP_LINK_BW_5_4;
931 }
932
933 switch (dpcd_val) {
934 default:
935 DRM_DEV_ERROR(pdata->dev,
936 "Unexpected max rate (%#x); assuming 5.4 GHz\n",
937 (int)dpcd_val);
938 fallthrough;
939 case DP_LINK_BW_5_4:
940 valid_rates |= BIT(7);
941 fallthrough;
942 case DP_LINK_BW_2_7:
943 valid_rates |= BIT(4);
944 fallthrough;
945 case DP_LINK_BW_1_62:
946 valid_rates |= BIT(1);
947 break;
948 }
949
950 return valid_rates;
951 }
952
ti_sn_bridge_set_video_timings(struct ti_sn65dsi86 * pdata)953 static void ti_sn_bridge_set_video_timings(struct ti_sn65dsi86 *pdata)
954 {
955 struct drm_display_mode *mode =
956 &pdata->bridge.encoder->crtc->state->adjusted_mode;
957 u8 hsync_polarity = 0, vsync_polarity = 0;
958
959 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
960 hsync_polarity = CHA_HSYNC_POLARITY;
961 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
962 vsync_polarity = CHA_VSYNC_POLARITY;
963
964 ti_sn65dsi86_write_u16(pdata, SN_CHA_ACTIVE_LINE_LENGTH_LOW_REG,
965 mode->hdisplay);
966 ti_sn65dsi86_write_u16(pdata, SN_CHA_VERTICAL_DISPLAY_SIZE_LOW_REG,
967 mode->vdisplay);
968 regmap_write(pdata->regmap, SN_CHA_HSYNC_PULSE_WIDTH_LOW_REG,
969 (mode->hsync_end - mode->hsync_start) & 0xFF);
970 regmap_write(pdata->regmap, SN_CHA_HSYNC_PULSE_WIDTH_HIGH_REG,
971 (((mode->hsync_end - mode->hsync_start) >> 8) & 0x7F) |
972 hsync_polarity);
973 regmap_write(pdata->regmap, SN_CHA_VSYNC_PULSE_WIDTH_LOW_REG,
974 (mode->vsync_end - mode->vsync_start) & 0xFF);
975 regmap_write(pdata->regmap, SN_CHA_VSYNC_PULSE_WIDTH_HIGH_REG,
976 (((mode->vsync_end - mode->vsync_start) >> 8) & 0x7F) |
977 vsync_polarity);
978
979 regmap_write(pdata->regmap, SN_CHA_HORIZONTAL_BACK_PORCH_REG,
980 (mode->htotal - mode->hsync_end) & 0xFF);
981 regmap_write(pdata->regmap, SN_CHA_VERTICAL_BACK_PORCH_REG,
982 (mode->vtotal - mode->vsync_end) & 0xFF);
983
984 regmap_write(pdata->regmap, SN_CHA_HORIZONTAL_FRONT_PORCH_REG,
985 (mode->hsync_start - mode->hdisplay) & 0xFF);
986 regmap_write(pdata->regmap, SN_CHA_VERTICAL_FRONT_PORCH_REG,
987 (mode->vsync_start - mode->vdisplay) & 0xFF);
988
989 usleep_range(10000, 10500); /* 10ms delay recommended by spec */
990 }
991
ti_sn_get_max_lanes(struct ti_sn65dsi86 * pdata)992 static unsigned int ti_sn_get_max_lanes(struct ti_sn65dsi86 *pdata)
993 {
994 u8 data;
995 int ret;
996
997 ret = drm_dp_dpcd_readb(&pdata->aux, DP_MAX_LANE_COUNT, &data);
998 if (ret != 1) {
999 DRM_DEV_ERROR(pdata->dev,
1000 "Can't read lane count (%d); assuming 4\n", ret);
1001 return 4;
1002 }
1003
1004 return data & DP_LANE_COUNT_MASK;
1005 }
1006
ti_sn_link_training(struct ti_sn65dsi86 * pdata,int dp_rate_idx,const char ** last_err_str)1007 static int ti_sn_link_training(struct ti_sn65dsi86 *pdata, int dp_rate_idx,
1008 const char **last_err_str)
1009 {
1010 unsigned int val;
1011 int ret;
1012 int i;
1013
1014 /* set dp clk frequency value */
1015 regmap_update_bits(pdata->regmap, SN_DATARATE_CONFIG_REG,
1016 DP_DATARATE_MASK, DP_DATARATE(dp_rate_idx));
1017
1018 /* enable DP PLL */
1019 regmap_write(pdata->regmap, SN_PLL_ENABLE_REG, 1);
1020
1021 ret = regmap_read_poll_timeout(pdata->regmap, SN_DPPLL_SRC_REG, val,
1022 val & DPPLL_SRC_DP_PLL_LOCK, 1000,
1023 50 * 1000);
1024 if (ret) {
1025 *last_err_str = "DP_PLL_LOCK polling failed";
1026 goto exit;
1027 }
1028
1029 /*
1030 * We'll try to link train several times. As part of link training
1031 * the bridge chip will write DP_SET_POWER_D0 to DP_SET_POWER. If
1032 * the panel isn't ready quite it might respond NAK here which means
1033 * we need to try again.
1034 */
1035 for (i = 0; i < SN_LINK_TRAINING_TRIES; i++) {
1036 /* Semi auto link training mode */
1037 regmap_write(pdata->regmap, SN_ML_TX_MODE_REG, 0x0A);
1038 ret = regmap_read_poll_timeout(pdata->regmap, SN_ML_TX_MODE_REG, val,
1039 val == ML_TX_MAIN_LINK_OFF ||
1040 val == ML_TX_NORMAL_MODE, 1000,
1041 500 * 1000);
1042 if (ret) {
1043 *last_err_str = "Training complete polling failed";
1044 } else if (val == ML_TX_MAIN_LINK_OFF) {
1045 *last_err_str = "Link training failed, link is off";
1046 ret = -EIO;
1047 continue;
1048 }
1049
1050 break;
1051 }
1052
1053 /* If we saw quite a few retries, add a note about it */
1054 if (!ret && i > SN_LINK_TRAINING_TRIES / 2)
1055 DRM_DEV_INFO(pdata->dev, "Link training needed %d retries\n", i);
1056
1057 exit:
1058 /* Disable the PLL if we failed */
1059 if (ret)
1060 regmap_write(pdata->regmap, SN_PLL_ENABLE_REG, 0);
1061
1062 return ret;
1063 }
1064
ti_sn_bridge_atomic_enable(struct drm_bridge * bridge,struct drm_bridge_state * old_bridge_state)1065 static void ti_sn_bridge_atomic_enable(struct drm_bridge *bridge,
1066 struct drm_bridge_state *old_bridge_state)
1067 {
1068 struct ti_sn65dsi86 *pdata = bridge_to_ti_sn65dsi86(bridge);
1069 struct drm_connector *connector;
1070 const char *last_err_str = "No supported DP rate";
1071 unsigned int valid_rates;
1072 int dp_rate_idx;
1073 unsigned int val;
1074 int ret = -EINVAL;
1075 int max_dp_lanes;
1076 unsigned int bpp;
1077
1078 connector = drm_atomic_get_new_connector_for_encoder(old_bridge_state->base.state,
1079 bridge->encoder);
1080 if (!connector) {
1081 dev_err_ratelimited(pdata->dev, "Could not get the connector\n");
1082 return;
1083 }
1084
1085 max_dp_lanes = ti_sn_get_max_lanes(pdata);
1086 pdata->dp_lanes = min(pdata->dp_lanes, max_dp_lanes);
1087
1088 /* DSI_A lane config */
1089 val = CHA_DSI_LANES(SN_MAX_DP_LANES - pdata->dsi->lanes);
1090 regmap_update_bits(pdata->regmap, SN_DSI_LANES_REG,
1091 CHA_DSI_LANES_MASK, val);
1092
1093 regmap_write(pdata->regmap, SN_LN_ASSIGN_REG, pdata->ln_assign);
1094 regmap_update_bits(pdata->regmap, SN_ENH_FRAME_REG, LN_POLRS_MASK,
1095 pdata->ln_polrs << LN_POLRS_OFFSET);
1096
1097 /* set dsi clk frequency value */
1098 ti_sn_bridge_set_dsi_rate(pdata);
1099
1100 /*
1101 * The SN65DSI86 only supports ASSR Display Authentication method and
1102 * this method is enabled for eDP panels. An eDP panel must support this
1103 * authentication method. We need to enable this method in the eDP panel
1104 * at DisplayPort address 0x0010A prior to link training.
1105 *
1106 * As only ASSR is supported by SN65DSI86, for full DisplayPort displays
1107 * we need to disable the scrambler.
1108 */
1109 if (pdata->bridge.type == DRM_MODE_CONNECTOR_eDP) {
1110 drm_dp_dpcd_writeb(&pdata->aux, DP_EDP_CONFIGURATION_SET,
1111 DP_ALTERNATE_SCRAMBLER_RESET_ENABLE);
1112
1113 regmap_update_bits(pdata->regmap, SN_TRAINING_SETTING_REG,
1114 SCRAMBLE_DISABLE, 0);
1115 } else {
1116 regmap_update_bits(pdata->regmap, SN_TRAINING_SETTING_REG,
1117 SCRAMBLE_DISABLE, SCRAMBLE_DISABLE);
1118 }
1119
1120 bpp = ti_sn_bridge_get_bpp(connector);
1121 /* Set the DP output format (18 bpp or 24 bpp) */
1122 val = bpp == 18 ? BPP_18_RGB : 0;
1123 regmap_update_bits(pdata->regmap, SN_DATA_FORMAT_REG, BPP_18_RGB, val);
1124
1125 /* DP lane config */
1126 val = DP_NUM_LANES(min(pdata->dp_lanes, 3));
1127 regmap_update_bits(pdata->regmap, SN_SSC_CONFIG_REG, DP_NUM_LANES_MASK,
1128 val);
1129
1130 valid_rates = ti_sn_bridge_read_valid_rates(pdata);
1131
1132 /* Train until we run out of rates */
1133 for (dp_rate_idx = ti_sn_bridge_calc_min_dp_rate_idx(pdata, bpp);
1134 dp_rate_idx < ARRAY_SIZE(ti_sn_bridge_dp_rate_lut);
1135 dp_rate_idx++) {
1136 if (!(valid_rates & BIT(dp_rate_idx)))
1137 continue;
1138
1139 ret = ti_sn_link_training(pdata, dp_rate_idx, &last_err_str);
1140 if (!ret)
1141 break;
1142 }
1143 if (ret) {
1144 DRM_DEV_ERROR(pdata->dev, "%s (%d)\n", last_err_str, ret);
1145 return;
1146 }
1147
1148 /* config video parameters */
1149 ti_sn_bridge_set_video_timings(pdata);
1150
1151 /* enable video stream */
1152 regmap_update_bits(pdata->regmap, SN_ENH_FRAME_REG, VSTREAM_ENABLE,
1153 VSTREAM_ENABLE);
1154 }
1155
ti_sn_bridge_atomic_pre_enable(struct drm_bridge * bridge,struct drm_bridge_state * old_bridge_state)1156 static void ti_sn_bridge_atomic_pre_enable(struct drm_bridge *bridge,
1157 struct drm_bridge_state *old_bridge_state)
1158 {
1159 struct ti_sn65dsi86 *pdata = bridge_to_ti_sn65dsi86(bridge);
1160
1161 pm_runtime_get_sync(pdata->dev);
1162
1163 if (!pdata->refclk)
1164 ti_sn65dsi86_enable_comms(pdata);
1165
1166 /* td7: min 100 us after enable before DSI data */
1167 usleep_range(100, 110);
1168 }
1169
ti_sn_bridge_atomic_post_disable(struct drm_bridge * bridge,struct drm_bridge_state * old_bridge_state)1170 static void ti_sn_bridge_atomic_post_disable(struct drm_bridge *bridge,
1171 struct drm_bridge_state *old_bridge_state)
1172 {
1173 struct ti_sn65dsi86 *pdata = bridge_to_ti_sn65dsi86(bridge);
1174
1175 /* semi auto link training mode OFF */
1176 regmap_write(pdata->regmap, SN_ML_TX_MODE_REG, 0);
1177 /* Num lanes to 0 as per power sequencing in data sheet */
1178 regmap_update_bits(pdata->regmap, SN_SSC_CONFIG_REG, DP_NUM_LANES_MASK, 0);
1179 /* disable DP PLL */
1180 regmap_write(pdata->regmap, SN_PLL_ENABLE_REG, 0);
1181
1182 if (!pdata->refclk)
1183 ti_sn65dsi86_disable_comms(pdata);
1184
1185 pm_runtime_put_sync(pdata->dev);
1186 }
1187
ti_sn_bridge_detect(struct drm_bridge * bridge)1188 static enum drm_connector_status ti_sn_bridge_detect(struct drm_bridge *bridge)
1189 {
1190 struct ti_sn65dsi86 *pdata = bridge_to_ti_sn65dsi86(bridge);
1191 int val = 0;
1192
1193 /*
1194 * Runtime reference is grabbed in ti_sn_bridge_hpd_enable()
1195 * as the chip won't report HPD just after being powered on.
1196 * HPD_DEBOUNCED_STATE reflects correct state only after the
1197 * debounce time (~100-400 ms).
1198 */
1199
1200 regmap_read(pdata->regmap, SN_HPD_DISABLE_REG, &val);
1201
1202 return val & HPD_DEBOUNCED_STATE ? connector_status_connected
1203 : connector_status_disconnected;
1204 }
1205
ti_sn_bridge_edid_read(struct drm_bridge * bridge,struct drm_connector * connector)1206 static const struct drm_edid *ti_sn_bridge_edid_read(struct drm_bridge *bridge,
1207 struct drm_connector *connector)
1208 {
1209 struct ti_sn65dsi86 *pdata = bridge_to_ti_sn65dsi86(bridge);
1210
1211 return drm_edid_read_ddc(connector, &pdata->aux.ddc);
1212 }
1213
ti_sn65dsi86_debugfs_init(struct drm_bridge * bridge,struct dentry * root)1214 static void ti_sn65dsi86_debugfs_init(struct drm_bridge *bridge, struct dentry *root)
1215 {
1216 struct ti_sn65dsi86 *pdata = bridge_to_ti_sn65dsi86(bridge);
1217 struct dentry *debugfs;
1218
1219 debugfs = debugfs_create_dir(dev_name(pdata->dev), root);
1220 debugfs_create_file("status", 0600, debugfs, pdata, &status_fops);
1221 }
1222
ti_sn_bridge_hpd_enable(struct drm_bridge * bridge)1223 static void ti_sn_bridge_hpd_enable(struct drm_bridge *bridge)
1224 {
1225 struct ti_sn65dsi86 *pdata = bridge_to_ti_sn65dsi86(bridge);
1226
1227 /*
1228 * Device needs to be powered on before reading the HPD state
1229 * for reliable hpd detection in ti_sn_bridge_detect() due to
1230 * the high debounce time.
1231 */
1232
1233 pm_runtime_get_sync(pdata->dev);
1234 }
1235
ti_sn_bridge_hpd_disable(struct drm_bridge * bridge)1236 static void ti_sn_bridge_hpd_disable(struct drm_bridge *bridge)
1237 {
1238 struct ti_sn65dsi86 *pdata = bridge_to_ti_sn65dsi86(bridge);
1239
1240 pm_runtime_put_autosuspend(pdata->dev);
1241 }
1242
1243 static const struct drm_bridge_funcs ti_sn_bridge_funcs = {
1244 .attach = ti_sn_bridge_attach,
1245 .detach = ti_sn_bridge_detach,
1246 .mode_valid = ti_sn_bridge_mode_valid,
1247 .edid_read = ti_sn_bridge_edid_read,
1248 .detect = ti_sn_bridge_detect,
1249 .atomic_pre_enable = ti_sn_bridge_atomic_pre_enable,
1250 .atomic_enable = ti_sn_bridge_atomic_enable,
1251 .atomic_disable = ti_sn_bridge_atomic_disable,
1252 .atomic_post_disable = ti_sn_bridge_atomic_post_disable,
1253 .atomic_reset = drm_atomic_helper_bridge_reset,
1254 .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state,
1255 .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state,
1256 .debugfs_init = ti_sn65dsi86_debugfs_init,
1257 .hpd_enable = ti_sn_bridge_hpd_enable,
1258 .hpd_disable = ti_sn_bridge_hpd_disable,
1259 };
1260
ti_sn_bridge_parse_lanes(struct ti_sn65dsi86 * pdata,struct device_node * np)1261 static void ti_sn_bridge_parse_lanes(struct ti_sn65dsi86 *pdata,
1262 struct device_node *np)
1263 {
1264 u32 lane_assignments[SN_MAX_DP_LANES] = { 0, 1, 2, 3 };
1265 u32 lane_polarities[SN_MAX_DP_LANES] = { };
1266 struct device_node *endpoint;
1267 u8 ln_assign = 0;
1268 u8 ln_polrs = 0;
1269 int dp_lanes;
1270 int i;
1271
1272 /*
1273 * Read config from the device tree about lane remapping and lane
1274 * polarities. These are optional and we assume identity map and
1275 * normal polarity if nothing is specified. It's OK to specify just
1276 * data-lanes but not lane-polarities but not vice versa.
1277 *
1278 * Error checking is light (we just make sure we don't crash or
1279 * buffer overrun) and we assume dts is well formed and specifying
1280 * mappings that the hardware supports.
1281 */
1282 endpoint = of_graph_get_endpoint_by_regs(np, 1, -1);
1283 dp_lanes = drm_of_get_data_lanes_count(endpoint, 1, SN_MAX_DP_LANES);
1284 if (dp_lanes > 0) {
1285 of_property_read_u32_array(endpoint, "data-lanes",
1286 lane_assignments, dp_lanes);
1287 of_property_read_u32_array(endpoint, "lane-polarities",
1288 lane_polarities, dp_lanes);
1289 } else {
1290 dp_lanes = SN_MAX_DP_LANES;
1291 }
1292 of_node_put(endpoint);
1293
1294 /*
1295 * Convert into register format. Loop over all lanes even if
1296 * data-lanes had fewer elements so that we nicely initialize
1297 * the LN_ASSIGN register.
1298 */
1299 for (i = SN_MAX_DP_LANES - 1; i >= 0; i--) {
1300 ln_assign = ln_assign << LN_ASSIGN_WIDTH | lane_assignments[i];
1301 ln_polrs = ln_polrs << 1 | lane_polarities[i];
1302 }
1303
1304 /* Stash in our struct for when we power on */
1305 pdata->dp_lanes = dp_lanes;
1306 pdata->ln_assign = ln_assign;
1307 pdata->ln_polrs = ln_polrs;
1308 }
1309
ti_sn_bridge_parse_dsi_host(struct ti_sn65dsi86 * pdata)1310 static int ti_sn_bridge_parse_dsi_host(struct ti_sn65dsi86 *pdata)
1311 {
1312 struct device_node *np = pdata->dev->of_node;
1313
1314 pdata->host_node = of_graph_get_remote_node(np, 0, 0);
1315
1316 if (!pdata->host_node) {
1317 DRM_ERROR("remote dsi host node not found\n");
1318 return -ENODEV;
1319 }
1320
1321 return 0;
1322 }
1323
ti_sn_bridge_probe(struct auxiliary_device * adev,const struct auxiliary_device_id * id)1324 static int ti_sn_bridge_probe(struct auxiliary_device *adev,
1325 const struct auxiliary_device_id *id)
1326 {
1327 struct ti_sn65dsi86 *pdata = dev_get_drvdata(adev->dev.parent);
1328 struct device_node *np = pdata->dev->of_node;
1329 int ret;
1330
1331 pdata->next_bridge = devm_drm_of_get_bridge(&adev->dev, np, 1, 0);
1332 if (IS_ERR(pdata->next_bridge))
1333 return dev_err_probe(&adev->dev, PTR_ERR(pdata->next_bridge),
1334 "failed to create panel bridge\n");
1335
1336 ti_sn_bridge_parse_lanes(pdata, np);
1337
1338 ret = ti_sn_bridge_parse_dsi_host(pdata);
1339 if (ret)
1340 return ret;
1341
1342 pdata->bridge.funcs = &ti_sn_bridge_funcs;
1343 pdata->bridge.of_node = np;
1344 pdata->bridge.type = pdata->next_bridge->type == DRM_MODE_CONNECTOR_DisplayPort
1345 ? DRM_MODE_CONNECTOR_DisplayPort : DRM_MODE_CONNECTOR_eDP;
1346
1347 if (pdata->bridge.type == DRM_MODE_CONNECTOR_DisplayPort) {
1348 pdata->bridge.ops = DRM_BRIDGE_OP_EDID | DRM_BRIDGE_OP_DETECT |
1349 DRM_BRIDGE_OP_HPD;
1350 /*
1351 * If comms were already enabled they would have been enabled
1352 * with the wrong value of HPD_DISABLE. Update it now. Comms
1353 * could be enabled if anyone is holding a pm_runtime reference
1354 * (like if a GPIO is in use). Note that in most cases nobody
1355 * is doing AUX channel xfers before the bridge is added so
1356 * HPD doesn't _really_ matter then. The only exception is in
1357 * the eDP case where the panel wants to read the EDID before
1358 * the bridge is added. We always consistently have HPD disabled
1359 * for eDP.
1360 */
1361 mutex_lock(&pdata->comms_mutex);
1362 if (pdata->comms_enabled)
1363 regmap_update_bits(pdata->regmap, SN_HPD_DISABLE_REG,
1364 HPD_DISABLE, 0);
1365 mutex_unlock(&pdata->comms_mutex);
1366 }
1367
1368 drm_bridge_add(&pdata->bridge);
1369
1370 ret = ti_sn_attach_host(adev, pdata);
1371 if (ret) {
1372 dev_err_probe(&adev->dev, ret, "failed to attach dsi host\n");
1373 goto err_remove_bridge;
1374 }
1375
1376 return 0;
1377
1378 err_remove_bridge:
1379 drm_bridge_remove(&pdata->bridge);
1380 return ret;
1381 }
1382
ti_sn_bridge_remove(struct auxiliary_device * adev)1383 static void ti_sn_bridge_remove(struct auxiliary_device *adev)
1384 {
1385 struct ti_sn65dsi86 *pdata = dev_get_drvdata(adev->dev.parent);
1386
1387 if (!pdata)
1388 return;
1389
1390 drm_bridge_remove(&pdata->bridge);
1391
1392 of_node_put(pdata->host_node);
1393 }
1394
1395 static const struct auxiliary_device_id ti_sn_bridge_id_table[] = {
1396 { .name = "ti_sn65dsi86.bridge", },
1397 {},
1398 };
1399
1400 static struct auxiliary_driver ti_sn_bridge_driver = {
1401 .name = "bridge",
1402 .probe = ti_sn_bridge_probe,
1403 .remove = ti_sn_bridge_remove,
1404 .id_table = ti_sn_bridge_id_table,
1405 };
1406
1407 /* -----------------------------------------------------------------------------
1408 * PWM Controller
1409 */
1410 #if defined(CONFIG_PWM)
ti_sn_pwm_pin_request(struct ti_sn65dsi86 * pdata)1411 static int ti_sn_pwm_pin_request(struct ti_sn65dsi86 *pdata)
1412 {
1413 return atomic_xchg(&pdata->pwm_pin_busy, 1) ? -EBUSY : 0;
1414 }
1415
ti_sn_pwm_pin_release(struct ti_sn65dsi86 * pdata)1416 static void ti_sn_pwm_pin_release(struct ti_sn65dsi86 *pdata)
1417 {
1418 atomic_set(&pdata->pwm_pin_busy, 0);
1419 }
1420
pwm_chip_to_ti_sn_bridge(struct pwm_chip * chip)1421 static struct ti_sn65dsi86 *pwm_chip_to_ti_sn_bridge(struct pwm_chip *chip)
1422 {
1423 return pwmchip_get_drvdata(chip);
1424 }
1425
ti_sn_pwm_request(struct pwm_chip * chip,struct pwm_device * pwm)1426 static int ti_sn_pwm_request(struct pwm_chip *chip, struct pwm_device *pwm)
1427 {
1428 struct ti_sn65dsi86 *pdata = pwm_chip_to_ti_sn_bridge(chip);
1429
1430 return ti_sn_pwm_pin_request(pdata);
1431 }
1432
ti_sn_pwm_free(struct pwm_chip * chip,struct pwm_device * pwm)1433 static void ti_sn_pwm_free(struct pwm_chip *chip, struct pwm_device *pwm)
1434 {
1435 struct ti_sn65dsi86 *pdata = pwm_chip_to_ti_sn_bridge(chip);
1436
1437 ti_sn_pwm_pin_release(pdata);
1438 }
1439
1440 /*
1441 * Limitations:
1442 * - The PWM signal is not driven when the chip is powered down, or in its
1443 * reset state and the driver does not implement the "suspend state"
1444 * described in the documentation. In order to save power, state->enabled is
1445 * interpreted as denoting if the signal is expected to be valid, and is used
1446 * to determine if the chip needs to be kept powered.
1447 * - Changing both period and duty_cycle is not done atomically, neither is the
1448 * multi-byte register updates, so the output might briefly be undefined
1449 * during update.
1450 */
ti_sn_pwm_apply(struct pwm_chip * chip,struct pwm_device * pwm,const struct pwm_state * state)1451 static int ti_sn_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
1452 const struct pwm_state *state)
1453 {
1454 struct ti_sn65dsi86 *pdata = pwm_chip_to_ti_sn_bridge(chip);
1455 unsigned int pwm_en_inv;
1456 unsigned int backlight;
1457 unsigned int pre_div;
1458 unsigned int scale;
1459 u64 period_max;
1460 u64 period;
1461 int ret;
1462
1463 if (!pdata->pwm_enabled) {
1464 ret = pm_runtime_resume_and_get(pwmchip_parent(chip));
1465 if (ret < 0)
1466 return ret;
1467 }
1468
1469 if (state->enabled) {
1470 if (!pdata->pwm_enabled) {
1471 /*
1472 * The chip might have been powered down while we
1473 * didn't hold a PM runtime reference, so mux in the
1474 * PWM function on the GPIO pin again.
1475 */
1476 ret = regmap_update_bits(pdata->regmap, SN_GPIO_CTRL_REG,
1477 SN_GPIO_MUX_MASK << (2 * SN_PWM_GPIO_IDX),
1478 SN_GPIO_MUX_SPECIAL << (2 * SN_PWM_GPIO_IDX));
1479 if (ret) {
1480 dev_err(pwmchip_parent(chip), "failed to mux in PWM function\n");
1481 goto out;
1482 }
1483 }
1484
1485 /*
1486 * Per the datasheet the PWM frequency is given by:
1487 *
1488 * REFCLK_FREQ
1489 * PWM_FREQ = -----------------------------------
1490 * PWM_PRE_DIV * BACKLIGHT_SCALE + 1
1491 *
1492 * However, after careful review the author is convinced that
1493 * the documentation has lost some parenthesis around
1494 * "BACKLIGHT_SCALE + 1".
1495 *
1496 * With the period T_pwm = 1/PWM_FREQ this can be written:
1497 *
1498 * T_pwm * REFCLK_FREQ = PWM_PRE_DIV * (BACKLIGHT_SCALE + 1)
1499 *
1500 * In order to keep BACKLIGHT_SCALE within its 16 bits,
1501 * PWM_PRE_DIV must be:
1502 *
1503 * T_pwm * REFCLK_FREQ
1504 * PWM_PRE_DIV >= -------------------------
1505 * BACKLIGHT_SCALE_MAX + 1
1506 *
1507 * To simplify the search and to favour higher resolution of
1508 * the duty cycle over accuracy of the period, the lowest
1509 * possible PWM_PRE_DIV is used. Finally the scale is
1510 * calculated as:
1511 *
1512 * T_pwm * REFCLK_FREQ
1513 * BACKLIGHT_SCALE = ---------------------- - 1
1514 * PWM_PRE_DIV
1515 *
1516 * Here T_pwm is represented in seconds, so appropriate scaling
1517 * to nanoseconds is necessary.
1518 */
1519
1520 /* Minimum T_pwm is 1 / REFCLK_FREQ */
1521 if (state->period <= NSEC_PER_SEC / pdata->pwm_refclk_freq) {
1522 ret = -EINVAL;
1523 goto out;
1524 }
1525
1526 /*
1527 * Maximum T_pwm is 255 * (65535 + 1) / REFCLK_FREQ
1528 * Limit period to this to avoid overflows
1529 */
1530 period_max = div_u64((u64)NSEC_PER_SEC * 255 * (65535 + 1),
1531 pdata->pwm_refclk_freq);
1532 period = min(state->period, period_max);
1533
1534 pre_div = DIV64_U64_ROUND_UP(period * pdata->pwm_refclk_freq,
1535 (u64)NSEC_PER_SEC * (BACKLIGHT_SCALE_MAX + 1));
1536 scale = div64_u64(period * pdata->pwm_refclk_freq, (u64)NSEC_PER_SEC * pre_div) - 1;
1537
1538 /*
1539 * The documentation has the duty ratio given as:
1540 *
1541 * duty BACKLIGHT
1542 * ------- = ---------------------
1543 * period BACKLIGHT_SCALE + 1
1544 *
1545 * Solve for BACKLIGHT, substituting BACKLIGHT_SCALE according
1546 * to definition above and adjusting for nanosecond
1547 * representation of duty cycle gives us:
1548 */
1549 backlight = div64_u64(state->duty_cycle * pdata->pwm_refclk_freq,
1550 (u64)NSEC_PER_SEC * pre_div);
1551 if (backlight > scale)
1552 backlight = scale;
1553
1554 ret = regmap_write(pdata->regmap, SN_PWM_PRE_DIV_REG, pre_div);
1555 if (ret) {
1556 dev_err(pwmchip_parent(chip), "failed to update PWM_PRE_DIV\n");
1557 goto out;
1558 }
1559
1560 ti_sn65dsi86_write_u16(pdata, SN_BACKLIGHT_SCALE_REG, scale);
1561 ti_sn65dsi86_write_u16(pdata, SN_BACKLIGHT_REG, backlight);
1562 }
1563
1564 pwm_en_inv = FIELD_PREP(SN_PWM_EN_MASK, state->enabled) |
1565 FIELD_PREP(SN_PWM_INV_MASK, state->polarity == PWM_POLARITY_INVERSED);
1566 ret = regmap_write(pdata->regmap, SN_PWM_EN_INV_REG, pwm_en_inv);
1567 if (ret) {
1568 dev_err(pwmchip_parent(chip), "failed to update PWM_EN/PWM_INV\n");
1569 goto out;
1570 }
1571
1572 pdata->pwm_enabled = state->enabled;
1573 out:
1574
1575 if (!pdata->pwm_enabled)
1576 pm_runtime_put_sync(pwmchip_parent(chip));
1577
1578 return ret;
1579 }
1580
ti_sn_pwm_get_state(struct pwm_chip * chip,struct pwm_device * pwm,struct pwm_state * state)1581 static int ti_sn_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm,
1582 struct pwm_state *state)
1583 {
1584 struct ti_sn65dsi86 *pdata = pwm_chip_to_ti_sn_bridge(chip);
1585 unsigned int pwm_en_inv;
1586 unsigned int pre_div;
1587 u16 backlight;
1588 u16 scale;
1589 int ret;
1590
1591 ret = regmap_read(pdata->regmap, SN_PWM_EN_INV_REG, &pwm_en_inv);
1592 if (ret)
1593 return ret;
1594
1595 ret = ti_sn65dsi86_read_u16(pdata, SN_BACKLIGHT_SCALE_REG, &scale);
1596 if (ret)
1597 return ret;
1598
1599 ret = ti_sn65dsi86_read_u16(pdata, SN_BACKLIGHT_REG, &backlight);
1600 if (ret)
1601 return ret;
1602
1603 ret = regmap_read(pdata->regmap, SN_PWM_PRE_DIV_REG, &pre_div);
1604 if (ret)
1605 return ret;
1606
1607 state->enabled = FIELD_GET(SN_PWM_EN_MASK, pwm_en_inv);
1608 if (FIELD_GET(SN_PWM_INV_MASK, pwm_en_inv))
1609 state->polarity = PWM_POLARITY_INVERSED;
1610 else
1611 state->polarity = PWM_POLARITY_NORMAL;
1612
1613 state->period = DIV_ROUND_UP_ULL((u64)NSEC_PER_SEC * pre_div * (scale + 1),
1614 pdata->pwm_refclk_freq);
1615 state->duty_cycle = DIV_ROUND_UP_ULL((u64)NSEC_PER_SEC * pre_div * backlight,
1616 pdata->pwm_refclk_freq);
1617
1618 if (state->duty_cycle > state->period)
1619 state->duty_cycle = state->period;
1620
1621 return 0;
1622 }
1623
1624 static const struct pwm_ops ti_sn_pwm_ops = {
1625 .request = ti_sn_pwm_request,
1626 .free = ti_sn_pwm_free,
1627 .apply = ti_sn_pwm_apply,
1628 .get_state = ti_sn_pwm_get_state,
1629 };
1630
ti_sn_pwm_probe(struct auxiliary_device * adev,const struct auxiliary_device_id * id)1631 static int ti_sn_pwm_probe(struct auxiliary_device *adev,
1632 const struct auxiliary_device_id *id)
1633 {
1634 struct pwm_chip *chip;
1635 struct ti_sn65dsi86 *pdata = dev_get_drvdata(adev->dev.parent);
1636
1637 pdata->pchip = chip = devm_pwmchip_alloc(&adev->dev, 1, 0);
1638 if (IS_ERR(chip))
1639 return PTR_ERR(chip);
1640
1641 pwmchip_set_drvdata(chip, pdata);
1642
1643 chip->ops = &ti_sn_pwm_ops;
1644 chip->of_xlate = of_pwm_single_xlate;
1645
1646 devm_pm_runtime_enable(&adev->dev);
1647
1648 return pwmchip_add(chip);
1649 }
1650
ti_sn_pwm_remove(struct auxiliary_device * adev)1651 static void ti_sn_pwm_remove(struct auxiliary_device *adev)
1652 {
1653 struct ti_sn65dsi86 *pdata = dev_get_drvdata(adev->dev.parent);
1654
1655 pwmchip_remove(pdata->pchip);
1656
1657 if (pdata->pwm_enabled)
1658 pm_runtime_put_sync(&adev->dev);
1659 }
1660
1661 static const struct auxiliary_device_id ti_sn_pwm_id_table[] = {
1662 { .name = "ti_sn65dsi86.pwm", },
1663 {},
1664 };
1665
1666 static struct auxiliary_driver ti_sn_pwm_driver = {
1667 .name = "pwm",
1668 .probe = ti_sn_pwm_probe,
1669 .remove = ti_sn_pwm_remove,
1670 .id_table = ti_sn_pwm_id_table,
1671 };
1672
ti_sn_pwm_register(void)1673 static int __init ti_sn_pwm_register(void)
1674 {
1675 return auxiliary_driver_register(&ti_sn_pwm_driver);
1676 }
1677
ti_sn_pwm_unregister(void)1678 static void ti_sn_pwm_unregister(void)
1679 {
1680 auxiliary_driver_unregister(&ti_sn_pwm_driver);
1681 }
1682
1683 #else
ti_sn_pwm_pin_request(struct ti_sn65dsi86 * pdata)1684 static inline int ti_sn_pwm_pin_request(struct ti_sn65dsi86 *pdata) { return 0; }
ti_sn_pwm_pin_release(struct ti_sn65dsi86 * pdata)1685 static inline void ti_sn_pwm_pin_release(struct ti_sn65dsi86 *pdata) {}
1686
ti_sn_pwm_register(void)1687 static inline int ti_sn_pwm_register(void) { return 0; }
ti_sn_pwm_unregister(void)1688 static inline void ti_sn_pwm_unregister(void) {}
1689 #endif
1690
1691 /* -----------------------------------------------------------------------------
1692 * GPIO Controller
1693 */
1694 #if defined(CONFIG_OF_GPIO)
1695
tn_sn_bridge_of_xlate(struct gpio_chip * chip,const struct of_phandle_args * gpiospec,u32 * flags)1696 static int tn_sn_bridge_of_xlate(struct gpio_chip *chip,
1697 const struct of_phandle_args *gpiospec,
1698 u32 *flags)
1699 {
1700 if (WARN_ON(gpiospec->args_count < chip->of_gpio_n_cells))
1701 return -EINVAL;
1702
1703 if (gpiospec->args[0] > chip->ngpio || gpiospec->args[0] < 1)
1704 return -EINVAL;
1705
1706 if (flags)
1707 *flags = gpiospec->args[1];
1708
1709 return gpiospec->args[0] - SN_GPIO_PHYSICAL_OFFSET;
1710 }
1711
ti_sn_bridge_gpio_get_direction(struct gpio_chip * chip,unsigned int offset)1712 static int ti_sn_bridge_gpio_get_direction(struct gpio_chip *chip,
1713 unsigned int offset)
1714 {
1715 struct ti_sn65dsi86 *pdata = gpiochip_get_data(chip);
1716
1717 /*
1718 * We already have to keep track of the direction because we use
1719 * that to figure out whether we've powered the device. We can
1720 * just return that rather than (maybe) powering up the device
1721 * to ask its direction.
1722 */
1723 return test_bit(offset, pdata->gchip_output) ?
1724 GPIO_LINE_DIRECTION_OUT : GPIO_LINE_DIRECTION_IN;
1725 }
1726
ti_sn_bridge_gpio_get(struct gpio_chip * chip,unsigned int offset)1727 static int ti_sn_bridge_gpio_get(struct gpio_chip *chip, unsigned int offset)
1728 {
1729 struct ti_sn65dsi86 *pdata = gpiochip_get_data(chip);
1730 unsigned int val;
1731 int ret;
1732
1733 /*
1734 * When the pin is an input we don't forcibly keep the bridge
1735 * powered--we just power it on to read the pin. NOTE: part of
1736 * the reason this works is that the bridge defaults (when
1737 * powered back on) to all 4 GPIOs being configured as GPIO input.
1738 * Also note that if something else is keeping the chip powered the
1739 * pm_runtime functions are lightweight increments of a refcount.
1740 */
1741 pm_runtime_get_sync(pdata->dev);
1742 ret = regmap_read(pdata->regmap, SN_GPIO_IO_REG, &val);
1743 pm_runtime_put_autosuspend(pdata->dev);
1744
1745 if (ret)
1746 return ret;
1747
1748 return !!(val & BIT(SN_GPIO_INPUT_SHIFT + offset));
1749 }
1750
ti_sn_bridge_gpio_set(struct gpio_chip * chip,unsigned int offset,int val)1751 static void ti_sn_bridge_gpio_set(struct gpio_chip *chip, unsigned int offset,
1752 int val)
1753 {
1754 struct ti_sn65dsi86 *pdata = gpiochip_get_data(chip);
1755 int ret;
1756
1757 if (!test_bit(offset, pdata->gchip_output)) {
1758 dev_err(pdata->dev, "Ignoring GPIO set while input\n");
1759 return;
1760 }
1761
1762 val &= 1;
1763 ret = regmap_update_bits(pdata->regmap, SN_GPIO_IO_REG,
1764 BIT(SN_GPIO_OUTPUT_SHIFT + offset),
1765 val << (SN_GPIO_OUTPUT_SHIFT + offset));
1766 if (ret)
1767 dev_warn(pdata->dev,
1768 "Failed to set bridge GPIO %u: %d\n", offset, ret);
1769 }
1770
ti_sn_bridge_gpio_direction_input(struct gpio_chip * chip,unsigned int offset)1771 static int ti_sn_bridge_gpio_direction_input(struct gpio_chip *chip,
1772 unsigned int offset)
1773 {
1774 struct ti_sn65dsi86 *pdata = gpiochip_get_data(chip);
1775 int shift = offset * 2;
1776 int ret;
1777
1778 if (!test_and_clear_bit(offset, pdata->gchip_output))
1779 return 0;
1780
1781 ret = regmap_update_bits(pdata->regmap, SN_GPIO_CTRL_REG,
1782 SN_GPIO_MUX_MASK << shift,
1783 SN_GPIO_MUX_INPUT << shift);
1784 if (ret) {
1785 set_bit(offset, pdata->gchip_output);
1786 return ret;
1787 }
1788
1789 /*
1790 * NOTE: if nobody else is powering the device this may fully power
1791 * it off and when it comes back it will have lost all state, but
1792 * that's OK because the default is input and we're now an input.
1793 */
1794 pm_runtime_put_autosuspend(pdata->dev);
1795
1796 return 0;
1797 }
1798
ti_sn_bridge_gpio_direction_output(struct gpio_chip * chip,unsigned int offset,int val)1799 static int ti_sn_bridge_gpio_direction_output(struct gpio_chip *chip,
1800 unsigned int offset, int val)
1801 {
1802 struct ti_sn65dsi86 *pdata = gpiochip_get_data(chip);
1803 int shift = offset * 2;
1804 int ret;
1805
1806 if (test_and_set_bit(offset, pdata->gchip_output))
1807 return 0;
1808
1809 pm_runtime_get_sync(pdata->dev);
1810
1811 /* Set value first to avoid glitching */
1812 ti_sn_bridge_gpio_set(chip, offset, val);
1813
1814 /* Set direction */
1815 ret = regmap_update_bits(pdata->regmap, SN_GPIO_CTRL_REG,
1816 SN_GPIO_MUX_MASK << shift,
1817 SN_GPIO_MUX_OUTPUT << shift);
1818 if (ret) {
1819 clear_bit(offset, pdata->gchip_output);
1820 pm_runtime_put_autosuspend(pdata->dev);
1821 }
1822
1823 return ret;
1824 }
1825
ti_sn_bridge_gpio_request(struct gpio_chip * chip,unsigned int offset)1826 static int ti_sn_bridge_gpio_request(struct gpio_chip *chip, unsigned int offset)
1827 {
1828 struct ti_sn65dsi86 *pdata = gpiochip_get_data(chip);
1829
1830 if (offset == SN_PWM_GPIO_IDX)
1831 return ti_sn_pwm_pin_request(pdata);
1832
1833 return 0;
1834 }
1835
ti_sn_bridge_gpio_free(struct gpio_chip * chip,unsigned int offset)1836 static void ti_sn_bridge_gpio_free(struct gpio_chip *chip, unsigned int offset)
1837 {
1838 struct ti_sn65dsi86 *pdata = gpiochip_get_data(chip);
1839
1840 /* We won't keep pm_runtime if we're input, so switch there on free */
1841 ti_sn_bridge_gpio_direction_input(chip, offset);
1842
1843 if (offset == SN_PWM_GPIO_IDX)
1844 ti_sn_pwm_pin_release(pdata);
1845 }
1846
1847 static const char * const ti_sn_bridge_gpio_names[SN_NUM_GPIOS] = {
1848 "GPIO1", "GPIO2", "GPIO3", "GPIO4"
1849 };
1850
ti_sn_gpio_probe(struct auxiliary_device * adev,const struct auxiliary_device_id * id)1851 static int ti_sn_gpio_probe(struct auxiliary_device *adev,
1852 const struct auxiliary_device_id *id)
1853 {
1854 struct ti_sn65dsi86 *pdata = dev_get_drvdata(adev->dev.parent);
1855 int ret;
1856
1857 /* Only init if someone is going to use us as a GPIO controller */
1858 if (!of_property_read_bool(pdata->dev->of_node, "gpio-controller"))
1859 return 0;
1860
1861 pdata->gchip.label = dev_name(pdata->dev);
1862 pdata->gchip.parent = pdata->dev;
1863 pdata->gchip.owner = THIS_MODULE;
1864 pdata->gchip.of_xlate = tn_sn_bridge_of_xlate;
1865 pdata->gchip.of_gpio_n_cells = 2;
1866 pdata->gchip.request = ti_sn_bridge_gpio_request;
1867 pdata->gchip.free = ti_sn_bridge_gpio_free;
1868 pdata->gchip.get_direction = ti_sn_bridge_gpio_get_direction;
1869 pdata->gchip.direction_input = ti_sn_bridge_gpio_direction_input;
1870 pdata->gchip.direction_output = ti_sn_bridge_gpio_direction_output;
1871 pdata->gchip.get = ti_sn_bridge_gpio_get;
1872 pdata->gchip.set = ti_sn_bridge_gpio_set;
1873 pdata->gchip.can_sleep = true;
1874 pdata->gchip.names = ti_sn_bridge_gpio_names;
1875 pdata->gchip.ngpio = SN_NUM_GPIOS;
1876 pdata->gchip.base = -1;
1877 ret = devm_gpiochip_add_data(&adev->dev, &pdata->gchip, pdata);
1878 if (ret)
1879 dev_err(pdata->dev, "can't add gpio chip\n");
1880
1881 return ret;
1882 }
1883
1884 static const struct auxiliary_device_id ti_sn_gpio_id_table[] = {
1885 { .name = "ti_sn65dsi86.gpio", },
1886 {},
1887 };
1888
1889 MODULE_DEVICE_TABLE(auxiliary, ti_sn_gpio_id_table);
1890
1891 static struct auxiliary_driver ti_sn_gpio_driver = {
1892 .name = "gpio",
1893 .probe = ti_sn_gpio_probe,
1894 .id_table = ti_sn_gpio_id_table,
1895 };
1896
ti_sn_gpio_register(void)1897 static int __init ti_sn_gpio_register(void)
1898 {
1899 return auxiliary_driver_register(&ti_sn_gpio_driver);
1900 }
1901
ti_sn_gpio_unregister(void)1902 static void ti_sn_gpio_unregister(void)
1903 {
1904 auxiliary_driver_unregister(&ti_sn_gpio_driver);
1905 }
1906
1907 #else
1908
ti_sn_gpio_register(void)1909 static inline int ti_sn_gpio_register(void) { return 0; }
ti_sn_gpio_unregister(void)1910 static inline void ti_sn_gpio_unregister(void) {}
1911
1912 #endif
1913
1914 /* -----------------------------------------------------------------------------
1915 * Probe & Remove
1916 */
1917
ti_sn65dsi86_runtime_disable(void * data)1918 static void ti_sn65dsi86_runtime_disable(void *data)
1919 {
1920 pm_runtime_dont_use_autosuspend(data);
1921 pm_runtime_disable(data);
1922 }
1923
ti_sn65dsi86_parse_regulators(struct ti_sn65dsi86 * pdata)1924 static int ti_sn65dsi86_parse_regulators(struct ti_sn65dsi86 *pdata)
1925 {
1926 unsigned int i;
1927 const char * const ti_sn_bridge_supply_names[] = {
1928 "vcca", "vcc", "vccio", "vpll",
1929 };
1930
1931 for (i = 0; i < SN_REGULATOR_SUPPLY_NUM; i++)
1932 pdata->supplies[i].supply = ti_sn_bridge_supply_names[i];
1933
1934 return devm_regulator_bulk_get(pdata->dev, SN_REGULATOR_SUPPLY_NUM,
1935 pdata->supplies);
1936 }
1937
ti_sn65dsi86_probe(struct i2c_client * client)1938 static int ti_sn65dsi86_probe(struct i2c_client *client)
1939 {
1940 struct device *dev = &client->dev;
1941 struct ti_sn65dsi86 *pdata;
1942 int ret;
1943
1944 if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C)) {
1945 DRM_ERROR("device doesn't support I2C\n");
1946 return -ENODEV;
1947 }
1948
1949 pdata = devm_kzalloc(dev, sizeof(struct ti_sn65dsi86), GFP_KERNEL);
1950 if (!pdata)
1951 return -ENOMEM;
1952 dev_set_drvdata(dev, pdata);
1953 pdata->dev = dev;
1954
1955 mutex_init(&pdata->comms_mutex);
1956
1957 pdata->regmap = devm_regmap_init_i2c(client,
1958 &ti_sn65dsi86_regmap_config);
1959 if (IS_ERR(pdata->regmap))
1960 return dev_err_probe(dev, PTR_ERR(pdata->regmap),
1961 "regmap i2c init failed\n");
1962
1963 pdata->enable_gpio = devm_gpiod_get_optional(dev, "enable",
1964 GPIOD_OUT_LOW);
1965 if (IS_ERR(pdata->enable_gpio))
1966 return dev_err_probe(dev, PTR_ERR(pdata->enable_gpio),
1967 "failed to get enable gpio from DT\n");
1968
1969 ret = ti_sn65dsi86_parse_regulators(pdata);
1970 if (ret)
1971 return dev_err_probe(dev, ret, "failed to parse regulators\n");
1972
1973 pdata->refclk = devm_clk_get_optional(dev, "refclk");
1974 if (IS_ERR(pdata->refclk))
1975 return dev_err_probe(dev, PTR_ERR(pdata->refclk),
1976 "failed to get reference clock\n");
1977
1978 pm_runtime_enable(dev);
1979 pm_runtime_set_autosuspend_delay(pdata->dev, 500);
1980 pm_runtime_use_autosuspend(pdata->dev);
1981 ret = devm_add_action_or_reset(dev, ti_sn65dsi86_runtime_disable, dev);
1982 if (ret)
1983 return ret;
1984
1985 /*
1986 * Break ourselves up into a collection of aux devices. The only real
1987 * motiviation here is to solve the chicken-and-egg problem of probe
1988 * ordering. The bridge wants the panel to be there when it probes.
1989 * The panel wants its HPD GPIO (provided by sn65dsi86 on some boards)
1990 * when it probes. The panel and maybe backlight might want the DDC
1991 * bus or the pwm_chip. Having sub-devices allows the some sub devices
1992 * to finish probing even if others return -EPROBE_DEFER and gets us
1993 * around the problems.
1994 */
1995
1996 if (IS_ENABLED(CONFIG_OF_GPIO)) {
1997 ret = ti_sn65dsi86_add_aux_device(pdata, &pdata->gpio_aux, "gpio");
1998 if (ret)
1999 return ret;
2000 }
2001
2002 if (IS_ENABLED(CONFIG_PWM)) {
2003 ret = ti_sn65dsi86_add_aux_device(pdata, &pdata->pwm_aux, "pwm");
2004 if (ret)
2005 return ret;
2006 }
2007
2008 /*
2009 * NOTE: At the end of the AUX channel probe we'll add the aux device
2010 * for the bridge. This is because the bridge can't be used until the
2011 * AUX channel is there and this is a very simple solution to the
2012 * dependency problem.
2013 */
2014 return ti_sn65dsi86_add_aux_device(pdata, &pdata->aux_aux, "aux");
2015 }
2016
2017 static struct i2c_device_id ti_sn65dsi86_id[] = {
2018 { "ti,sn65dsi86", 0},
2019 {},
2020 };
2021 MODULE_DEVICE_TABLE(i2c, ti_sn65dsi86_id);
2022
2023 static const struct of_device_id ti_sn65dsi86_match_table[] = {
2024 {.compatible = "ti,sn65dsi86"},
2025 {},
2026 };
2027 MODULE_DEVICE_TABLE(of, ti_sn65dsi86_match_table);
2028
2029 static struct i2c_driver ti_sn65dsi86_driver = {
2030 .driver = {
2031 .name = "ti_sn65dsi86",
2032 .of_match_table = ti_sn65dsi86_match_table,
2033 .pm = &ti_sn65dsi86_pm_ops,
2034 },
2035 .probe = ti_sn65dsi86_probe,
2036 .id_table = ti_sn65dsi86_id,
2037 };
2038
ti_sn65dsi86_init(void)2039 static int __init ti_sn65dsi86_init(void)
2040 {
2041 int ret;
2042
2043 ret = i2c_add_driver(&ti_sn65dsi86_driver);
2044 if (ret)
2045 return ret;
2046
2047 ret = ti_sn_gpio_register();
2048 if (ret)
2049 goto err_main_was_registered;
2050
2051 ret = ti_sn_pwm_register();
2052 if (ret)
2053 goto err_gpio_was_registered;
2054
2055 ret = auxiliary_driver_register(&ti_sn_aux_driver);
2056 if (ret)
2057 goto err_pwm_was_registered;
2058
2059 ret = auxiliary_driver_register(&ti_sn_bridge_driver);
2060 if (ret)
2061 goto err_aux_was_registered;
2062
2063 return 0;
2064
2065 err_aux_was_registered:
2066 auxiliary_driver_unregister(&ti_sn_aux_driver);
2067 err_pwm_was_registered:
2068 ti_sn_pwm_unregister();
2069 err_gpio_was_registered:
2070 ti_sn_gpio_unregister();
2071 err_main_was_registered:
2072 i2c_del_driver(&ti_sn65dsi86_driver);
2073
2074 return ret;
2075 }
2076 module_init(ti_sn65dsi86_init);
2077
ti_sn65dsi86_exit(void)2078 static void __exit ti_sn65dsi86_exit(void)
2079 {
2080 auxiliary_driver_unregister(&ti_sn_bridge_driver);
2081 auxiliary_driver_unregister(&ti_sn_aux_driver);
2082 ti_sn_pwm_unregister();
2083 ti_sn_gpio_unregister();
2084 i2c_del_driver(&ti_sn65dsi86_driver);
2085 }
2086 module_exit(ti_sn65dsi86_exit);
2087
2088 MODULE_AUTHOR("Sandeep Panda <spanda@codeaurora.org>");
2089 MODULE_DESCRIPTION("sn65dsi86 DSI to eDP bridge driver");
2090 MODULE_LICENSE("GPL v2");
2091