1 // SPDX-License-Identifier: GPL-2.0-only
2 /* Copyright (c) 2015-2018, 2020-2021 The Linux Foundation. All rights reserved.
3 */
4
5 #define pr_fmt(fmt) "[drm:%s:%d] " fmt, __func__, __LINE__
6 #include "dpu_encoder_phys.h"
7 #include "dpu_hw_interrupts.h"
8 #include "dpu_hw_merge3d.h"
9 #include "dpu_core_irq.h"
10 #include "dpu_formats.h"
11 #include "dpu_trace.h"
12 #include "disp/msm_disp_snapshot.h"
13
14 #include <drm/display/drm_dsc_helper.h>
15 #include <drm/drm_managed.h>
16
17 #define DPU_DEBUG_VIDENC(e, fmt, ...) DPU_DEBUG("enc%d intf%d " fmt, \
18 (e) && (e)->parent ? \
19 (e)->parent->base.id : -1, \
20 (e) && (e)->hw_intf ? \
21 (e)->hw_intf->idx - INTF_0 : -1, ##__VA_ARGS__)
22
23 #define DPU_ERROR_VIDENC(e, fmt, ...) DPU_ERROR("enc%d intf%d " fmt, \
24 (e) && (e)->parent ? \
25 (e)->parent->base.id : -1, \
26 (e) && (e)->hw_intf ? \
27 (e)->hw_intf->idx - INTF_0 : -1, ##__VA_ARGS__)
28
29 #define to_dpu_encoder_phys_vid(x) \
30 container_of(x, struct dpu_encoder_phys_vid, base)
31
dpu_encoder_phys_vid_is_master(struct dpu_encoder_phys * phys_enc)32 static bool dpu_encoder_phys_vid_is_master(
33 struct dpu_encoder_phys *phys_enc)
34 {
35 bool ret = false;
36
37 if (phys_enc->split_role != ENC_ROLE_SLAVE)
38 ret = true;
39
40 return ret;
41 }
42
drm_mode_to_intf_timing_params(const struct dpu_encoder_phys * phys_enc,const struct drm_display_mode * mode,struct dpu_hw_intf_timing_params * timing)43 static void drm_mode_to_intf_timing_params(
44 const struct dpu_encoder_phys *phys_enc,
45 const struct drm_display_mode *mode,
46 struct dpu_hw_intf_timing_params *timing)
47 {
48 memset(timing, 0, sizeof(*timing));
49
50 if ((mode->htotal < mode->hsync_end)
51 || (mode->hsync_start < mode->hdisplay)
52 || (mode->vtotal < mode->vsync_end)
53 || (mode->vsync_start < mode->vdisplay)
54 || (mode->hsync_end < mode->hsync_start)
55 || (mode->vsync_end < mode->vsync_start)) {
56 DPU_ERROR(
57 "invalid params - hstart:%d,hend:%d,htot:%d,hdisplay:%d\n",
58 mode->hsync_start, mode->hsync_end,
59 mode->htotal, mode->hdisplay);
60 DPU_ERROR("vstart:%d,vend:%d,vtot:%d,vdisplay:%d\n",
61 mode->vsync_start, mode->vsync_end,
62 mode->vtotal, mode->vdisplay);
63 return;
64 }
65
66 /*
67 * https://www.kernel.org/doc/htmldocs/drm/ch02s05.html
68 * Active Region Front Porch Sync Back Porch
69 * <-----------------><------------><-----><----------->
70 * <- [hv]display --->
71 * <--------- [hv]sync_start ------>
72 * <----------------- [hv]sync_end ------->
73 * <---------------------------- [hv]total ------------->
74 */
75 timing->width = mode->hdisplay; /* active width */
76 timing->height = mode->vdisplay; /* active height */
77 timing->xres = timing->width;
78 timing->yres = timing->height;
79 timing->h_back_porch = mode->htotal - mode->hsync_end;
80 timing->h_front_porch = mode->hsync_start - mode->hdisplay;
81 timing->v_back_porch = mode->vtotal - mode->vsync_end;
82 timing->v_front_porch = mode->vsync_start - mode->vdisplay;
83 timing->hsync_pulse_width = mode->hsync_end - mode->hsync_start;
84 timing->vsync_pulse_width = mode->vsync_end - mode->vsync_start;
85 timing->hsync_polarity = (mode->flags & DRM_MODE_FLAG_NHSYNC) ? 1 : 0;
86 timing->vsync_polarity = (mode->flags & DRM_MODE_FLAG_NVSYNC) ? 1 : 0;
87 timing->border_clr = 0;
88 timing->underflow_clr = 0xff;
89 timing->hsync_skew = mode->hskew;
90
91 /* DSI controller cannot handle active-low sync signals. */
92 if (phys_enc->hw_intf->cap->type == INTF_DSI) {
93 timing->hsync_polarity = 0;
94 timing->vsync_polarity = 0;
95 }
96
97 timing->wide_bus_en = dpu_encoder_is_widebus_enabled(phys_enc->parent);
98 timing->compression_en = dpu_encoder_is_dsc_enabled(phys_enc->parent);
99
100 /*
101 * For DP/EDP, Shift timings to align it to bottom right.
102 * wide_bus_en is set for everything excluding SDM845 &
103 * porch changes cause DisplayPort failure and HDMI tearing.
104 */
105 if (phys_enc->hw_intf->cap->type == INTF_DP && timing->wide_bus_en) {
106 timing->h_back_porch += timing->h_front_porch;
107 timing->h_front_porch = 0;
108 timing->v_back_porch += timing->v_front_porch;
109 timing->v_front_porch = 0;
110 }
111
112 /*
113 * for DP, divide the horizonal parameters by 2 when
114 * widebus is enabled
115 */
116 if (phys_enc->hw_intf->cap->type == INTF_DP && timing->wide_bus_en) {
117 timing->width = timing->width >> 1;
118 timing->xres = timing->xres >> 1;
119 timing->h_back_porch = timing->h_back_porch >> 1;
120 timing->h_front_porch = timing->h_front_porch >> 1;
121 timing->hsync_pulse_width = timing->hsync_pulse_width >> 1;
122 }
123
124 /*
125 * for DSI, if compression is enabled, then divide the horizonal active
126 * timing parameters by compression ratio. bits of 3 components(R/G/B)
127 * is compressed into bits of 1 pixel.
128 */
129 if (phys_enc->hw_intf->cap->type != INTF_DP && timing->compression_en) {
130 struct drm_dsc_config *dsc =
131 dpu_encoder_get_dsc_config(phys_enc->parent);
132 /*
133 * TODO: replace drm_dsc_get_bpp_int with logic to handle
134 * fractional part if there is fraction
135 */
136 timing->width = timing->width * drm_dsc_get_bpp_int(dsc) /
137 (dsc->bits_per_component * 3);
138 timing->xres = timing->width;
139 }
140 }
141
get_horizontal_total(const struct dpu_hw_intf_timing_params * timing)142 static u32 get_horizontal_total(const struct dpu_hw_intf_timing_params *timing)
143 {
144 u32 active = timing->xres;
145 u32 inactive =
146 timing->h_back_porch + timing->h_front_porch +
147 timing->hsync_pulse_width;
148 return active + inactive;
149 }
150
get_vertical_total(const struct dpu_hw_intf_timing_params * timing)151 static u32 get_vertical_total(const struct dpu_hw_intf_timing_params *timing)
152 {
153 u32 active = timing->yres;
154 u32 inactive =
155 timing->v_back_porch + timing->v_front_porch +
156 timing->vsync_pulse_width;
157 return active + inactive;
158 }
159
160 /*
161 * programmable_fetch_get_num_lines:
162 * Number of fetch lines in vertical front porch
163 * @timing: Pointer to the intf timing information for the requested mode
164 *
165 * Returns the number of fetch lines in vertical front porch at which mdp
166 * can start fetching the next frame.
167 *
168 * Number of needed prefetch lines is anything that cannot be absorbed in the
169 * start of frame time (back porch + vsync pulse width).
170 *
171 * Some panels have very large VFP, however we only need a total number of
172 * lines based on the chip worst case latencies.
173 */
programmable_fetch_get_num_lines(struct dpu_encoder_phys * phys_enc,const struct dpu_hw_intf_timing_params * timing)174 static u32 programmable_fetch_get_num_lines(
175 struct dpu_encoder_phys *phys_enc,
176 const struct dpu_hw_intf_timing_params *timing)
177 {
178 u32 worst_case_needed_lines =
179 phys_enc->hw_intf->cap->prog_fetch_lines_worst_case;
180 u32 start_of_frame_lines =
181 timing->v_back_porch + timing->vsync_pulse_width;
182 u32 needed_vfp_lines = worst_case_needed_lines - start_of_frame_lines;
183 u32 actual_vfp_lines = 0;
184
185 /* Fetch must be outside active lines, otherwise undefined. */
186 if (start_of_frame_lines >= worst_case_needed_lines) {
187 DPU_DEBUG_VIDENC(phys_enc,
188 "prog fetch is not needed, large vbp+vsw\n");
189 actual_vfp_lines = 0;
190 } else if (timing->v_front_porch < needed_vfp_lines) {
191 /* Warn fetch needed, but not enough porch in panel config */
192 pr_warn_once
193 ("low vbp+vfp may lead to perf issues in some cases\n");
194 DPU_DEBUG_VIDENC(phys_enc,
195 "less vfp than fetch req, using entire vfp\n");
196 actual_vfp_lines = timing->v_front_porch;
197 } else {
198 DPU_DEBUG_VIDENC(phys_enc, "room in vfp for needed prefetch\n");
199 actual_vfp_lines = needed_vfp_lines;
200 }
201
202 DPU_DEBUG_VIDENC(phys_enc,
203 "v_front_porch %u v_back_porch %u vsync_pulse_width %u\n",
204 timing->v_front_porch, timing->v_back_porch,
205 timing->vsync_pulse_width);
206 DPU_DEBUG_VIDENC(phys_enc,
207 "wc_lines %u needed_vfp_lines %u actual_vfp_lines %u\n",
208 worst_case_needed_lines, needed_vfp_lines, actual_vfp_lines);
209
210 return actual_vfp_lines;
211 }
212
213 /*
214 * programmable_fetch_config: Programs HW to prefetch lines by offsetting
215 * the start of fetch into the vertical front porch for cases where the
216 * vsync pulse width and vertical back porch time is insufficient
217 *
218 * Gets # of lines to pre-fetch, then calculate VSYNC counter value.
219 * HW layer requires VSYNC counter of first pixel of tgt VFP line.
220 *
221 * @timing: Pointer to the intf timing information for the requested mode
222 */
programmable_fetch_config(struct dpu_encoder_phys * phys_enc,const struct dpu_hw_intf_timing_params * timing)223 static void programmable_fetch_config(struct dpu_encoder_phys *phys_enc,
224 const struct dpu_hw_intf_timing_params *timing)
225 {
226 struct dpu_hw_intf_prog_fetch f = { 0 };
227 u32 vfp_fetch_lines = 0;
228 u32 horiz_total = 0;
229 u32 vert_total = 0;
230 u32 vfp_fetch_start_vsync_counter = 0;
231 unsigned long lock_flags;
232
233 if (WARN_ON_ONCE(!phys_enc->hw_intf->ops.setup_prg_fetch))
234 return;
235
236 vfp_fetch_lines = programmable_fetch_get_num_lines(phys_enc, timing);
237 if (vfp_fetch_lines) {
238 vert_total = get_vertical_total(timing);
239 horiz_total = get_horizontal_total(timing);
240 vfp_fetch_start_vsync_counter =
241 (vert_total - vfp_fetch_lines) * horiz_total + 1;
242 f.enable = 1;
243 f.fetch_start = vfp_fetch_start_vsync_counter;
244 }
245
246 DPU_DEBUG_VIDENC(phys_enc,
247 "vfp_fetch_lines %u vfp_fetch_start_vsync_counter %u\n",
248 vfp_fetch_lines, vfp_fetch_start_vsync_counter);
249
250 spin_lock_irqsave(phys_enc->enc_spinlock, lock_flags);
251 phys_enc->hw_intf->ops.setup_prg_fetch(phys_enc->hw_intf, &f);
252 spin_unlock_irqrestore(phys_enc->enc_spinlock, lock_flags);
253 }
254
dpu_encoder_phys_vid_setup_timing_engine(struct dpu_encoder_phys * phys_enc)255 static void dpu_encoder_phys_vid_setup_timing_engine(
256 struct dpu_encoder_phys *phys_enc)
257 {
258 struct drm_display_mode mode;
259 struct dpu_hw_intf_timing_params timing_params = { 0 };
260 const struct msm_format *fmt = NULL;
261 u32 fmt_fourcc;
262 unsigned long lock_flags;
263 struct dpu_hw_intf_cfg intf_cfg = { 0 };
264
265 drm_mode_init(&mode, &phys_enc->cached_mode);
266
267 if (!phys_enc->hw_ctl->ops.setup_intf_cfg) {
268 DPU_ERROR("invalid encoder %d\n", phys_enc != NULL);
269 return;
270 }
271
272 if (!phys_enc->hw_intf->ops.setup_timing_gen) {
273 DPU_ERROR("timing engine setup is not supported\n");
274 return;
275 }
276
277 DPU_DEBUG_VIDENC(phys_enc, "enabling mode:\n");
278 drm_mode_debug_printmodeline(&mode);
279
280 fmt_fourcc = dpu_encoder_get_drm_fmt(phys_enc);
281
282 if (phys_enc->split_role != ENC_ROLE_SOLO || fmt_fourcc == DRM_FORMAT_YUV420) {
283 mode.hdisplay >>= 1;
284 mode.htotal >>= 1;
285 mode.hsync_start >>= 1;
286 mode.hsync_end >>= 1;
287 mode.hskew >>= 1;
288
289 DPU_DEBUG_VIDENC(phys_enc,
290 "split_role %d, halve horizontal %d %d %d %d %d\n",
291 phys_enc->split_role,
292 mode.hdisplay, mode.htotal,
293 mode.hsync_start, mode.hsync_end,
294 mode.hskew);
295 }
296
297 drm_mode_to_intf_timing_params(phys_enc, &mode, &timing_params);
298
299 fmt = mdp_get_format(&phys_enc->dpu_kms->base, fmt_fourcc, 0);
300 DPU_DEBUG_VIDENC(phys_enc, "fmt_fourcc 0x%X\n", fmt_fourcc);
301
302 if (phys_enc->hw_cdm)
303 intf_cfg.cdm = phys_enc->hw_cdm->idx;
304 intf_cfg.intf = phys_enc->hw_intf->idx;
305 intf_cfg.intf_mode_sel = DPU_CTL_MODE_SEL_VID;
306 intf_cfg.stream_sel = 0; /* Don't care value for video mode */
307 intf_cfg.mode_3d = dpu_encoder_helper_get_3d_blend_mode(phys_enc);
308 intf_cfg.dsc = dpu_encoder_helper_get_dsc(phys_enc);
309 if (intf_cfg.mode_3d && phys_enc->hw_pp->merge_3d)
310 intf_cfg.merge_3d = phys_enc->hw_pp->merge_3d->idx;
311
312 spin_lock_irqsave(phys_enc->enc_spinlock, lock_flags);
313 phys_enc->hw_intf->ops.setup_timing_gen(phys_enc->hw_intf,
314 &timing_params, fmt,
315 phys_enc->dpu_kms->catalog->mdss_ver);
316 phys_enc->hw_ctl->ops.setup_intf_cfg(phys_enc->hw_ctl, &intf_cfg);
317
318 /* setup which pp blk will connect to this intf */
319 if (phys_enc->hw_intf->ops.bind_pingpong_blk)
320 phys_enc->hw_intf->ops.bind_pingpong_blk(
321 phys_enc->hw_intf,
322 phys_enc->hw_pp->idx);
323
324 if (phys_enc->hw_pp->merge_3d)
325 phys_enc->hw_pp->merge_3d->ops.setup_3d_mode(phys_enc->hw_pp->merge_3d, intf_cfg.mode_3d);
326
327 spin_unlock_irqrestore(phys_enc->enc_spinlock, lock_flags);
328
329 programmable_fetch_config(phys_enc, &timing_params);
330 }
331
dpu_encoder_phys_vid_vblank_irq(void * arg)332 static void dpu_encoder_phys_vid_vblank_irq(void *arg)
333 {
334 struct dpu_encoder_phys *phys_enc = arg;
335 struct dpu_hw_ctl *hw_ctl;
336 unsigned long lock_flags;
337 u32 flush_register = 0;
338
339 hw_ctl = phys_enc->hw_ctl;
340
341 DPU_ATRACE_BEGIN("vblank_irq");
342
343 dpu_encoder_vblank_callback(phys_enc->parent, phys_enc);
344
345 atomic_read(&phys_enc->pending_kickoff_cnt);
346
347 /*
348 * only decrement the pending flush count if we've actually flushed
349 * hardware. due to sw irq latency, vblank may have already happened
350 * so we need to double-check with hw that it accepted the flush bits
351 */
352 spin_lock_irqsave(phys_enc->enc_spinlock, lock_flags);
353 if (hw_ctl->ops.get_flush_register)
354 flush_register = hw_ctl->ops.get_flush_register(hw_ctl);
355
356 if (!(flush_register & hw_ctl->ops.get_pending_flush(hw_ctl)))
357 atomic_add_unless(&phys_enc->pending_kickoff_cnt, -1, 0);
358 spin_unlock_irqrestore(phys_enc->enc_spinlock, lock_flags);
359
360 /* Signal any waiting atomic commit thread */
361 wake_up_all(&phys_enc->pending_kickoff_wq);
362
363 dpu_encoder_frame_done_callback(phys_enc->parent, phys_enc,
364 DPU_ENCODER_FRAME_EVENT_DONE);
365
366 DPU_ATRACE_END("vblank_irq");
367 }
368
dpu_encoder_phys_vid_underrun_irq(void * arg)369 static void dpu_encoder_phys_vid_underrun_irq(void *arg)
370 {
371 struct dpu_encoder_phys *phys_enc = arg;
372
373 dpu_encoder_underrun_callback(phys_enc->parent, phys_enc);
374 }
375
dpu_encoder_phys_vid_needs_single_flush(struct dpu_encoder_phys * phys_enc)376 static bool dpu_encoder_phys_vid_needs_single_flush(
377 struct dpu_encoder_phys *phys_enc)
378 {
379 return phys_enc->split_role != ENC_ROLE_SOLO;
380 }
381
dpu_encoder_phys_vid_atomic_mode_set(struct dpu_encoder_phys * phys_enc,struct drm_crtc_state * crtc_state,struct drm_connector_state * conn_state)382 static void dpu_encoder_phys_vid_atomic_mode_set(
383 struct dpu_encoder_phys *phys_enc,
384 struct drm_crtc_state *crtc_state,
385 struct drm_connector_state *conn_state)
386 {
387 phys_enc->irq[INTR_IDX_VSYNC] = phys_enc->hw_intf->cap->intr_vsync;
388
389 phys_enc->irq[INTR_IDX_UNDERRUN] = phys_enc->hw_intf->cap->intr_underrun;
390 }
391
dpu_encoder_phys_vid_control_vblank_irq(struct dpu_encoder_phys * phys_enc,bool enable)392 static int dpu_encoder_phys_vid_control_vblank_irq(
393 struct dpu_encoder_phys *phys_enc,
394 bool enable)
395 {
396 int ret = 0;
397 int refcount;
398
399 mutex_lock(&phys_enc->vblank_ctl_lock);
400 refcount = phys_enc->vblank_refcount;
401
402 /* Slave encoders don't report vblank */
403 if (!dpu_encoder_phys_vid_is_master(phys_enc))
404 goto end;
405
406 /* protect against negative */
407 if (!enable && refcount == 0) {
408 ret = -EINVAL;
409 goto end;
410 }
411
412 DRM_DEBUG_VBL("id:%u enable=%d/%d\n", DRMID(phys_enc->parent), enable,
413 refcount);
414
415 if (enable) {
416 if (phys_enc->vblank_refcount == 0)
417 ret = dpu_core_irq_register_callback(phys_enc->dpu_kms,
418 phys_enc->irq[INTR_IDX_VSYNC],
419 dpu_encoder_phys_vid_vblank_irq,
420 phys_enc);
421 if (!ret)
422 phys_enc->vblank_refcount++;
423 } else if (!enable) {
424 if (phys_enc->vblank_refcount == 1)
425 ret = dpu_core_irq_unregister_callback(phys_enc->dpu_kms,
426 phys_enc->irq[INTR_IDX_VSYNC]);
427 if (!ret)
428 phys_enc->vblank_refcount--;
429 }
430
431 end:
432 mutex_unlock(&phys_enc->vblank_ctl_lock);
433 if (ret) {
434 DRM_ERROR("failed: id:%u intf:%d ret:%d enable:%d refcnt:%d\n",
435 DRMID(phys_enc->parent),
436 phys_enc->hw_intf->idx - INTF_0, ret, enable,
437 refcount);
438 }
439 return ret;
440 }
441
dpu_encoder_phys_vid_enable(struct dpu_encoder_phys * phys_enc)442 static void dpu_encoder_phys_vid_enable(struct dpu_encoder_phys *phys_enc)
443 {
444 struct dpu_hw_ctl *ctl;
445 const struct msm_format *fmt;
446 u32 fmt_fourcc;
447 u32 mode_3d;
448
449 ctl = phys_enc->hw_ctl;
450 fmt_fourcc = dpu_encoder_get_drm_fmt(phys_enc);
451 fmt = mdp_get_format(&phys_enc->dpu_kms->base, fmt_fourcc, 0);
452 mode_3d = dpu_encoder_helper_get_3d_blend_mode(phys_enc);
453
454 DPU_DEBUG_VIDENC(phys_enc, "\n");
455
456 if (WARN_ON(!phys_enc->hw_intf->ops.enable_timing))
457 return;
458
459 dpu_encoder_helper_split_config(phys_enc, phys_enc->hw_intf->idx);
460
461 dpu_encoder_helper_phys_setup_cdm(phys_enc, fmt, CDM_CDWN_OUTPUT_HDMI);
462
463 dpu_encoder_phys_vid_setup_timing_engine(phys_enc);
464
465 /*
466 * For single flush cases (dual-ctl or pp-split), skip setting the
467 * flush bit for the slave intf, since both intfs use same ctl
468 * and HW will only flush the master.
469 */
470 if (dpu_encoder_phys_vid_needs_single_flush(phys_enc) &&
471 !dpu_encoder_phys_vid_is_master(phys_enc))
472 goto skip_flush;
473
474 ctl->ops.update_pending_flush_intf(ctl, phys_enc->hw_intf->idx);
475 if (mode_3d && ctl->ops.update_pending_flush_merge_3d &&
476 phys_enc->hw_pp->merge_3d)
477 ctl->ops.update_pending_flush_merge_3d(ctl, phys_enc->hw_pp->merge_3d->idx);
478
479 if (ctl->ops.update_pending_flush_cdm && phys_enc->hw_cdm)
480 ctl->ops.update_pending_flush_cdm(ctl, phys_enc->hw_cdm->idx);
481
482 /*
483 * Peripheral flush must be updated whenever flushing SDP packets is needed.
484 * SDP packets are required for any YUV format (YUV420, YUV422, YUV444).
485 */
486 if (ctl->ops.update_pending_flush_periph && dpu_encoder_needs_periph_flush(phys_enc))
487 ctl->ops.update_pending_flush_periph(ctl, phys_enc->hw_intf->idx);
488
489 skip_flush:
490 DPU_DEBUG_VIDENC(phys_enc,
491 "update pending flush ctl %d intf %d\n",
492 ctl->idx - CTL_0, phys_enc->hw_intf->idx);
493
494 atomic_set(&phys_enc->underrun_cnt, 0);
495
496 /* ctl_flush & timing engine enable will be triggered by framework */
497 if (phys_enc->enable_state == DPU_ENC_DISABLED)
498 phys_enc->enable_state = DPU_ENC_ENABLING;
499 }
500
dpu_encoder_phys_vid_wait_for_tx_complete(struct dpu_encoder_phys * phys_enc)501 static int dpu_encoder_phys_vid_wait_for_tx_complete(
502 struct dpu_encoder_phys *phys_enc)
503 {
504 struct dpu_encoder_wait_info wait_info;
505 int ret;
506
507 wait_info.wq = &phys_enc->pending_kickoff_wq;
508 wait_info.atomic_cnt = &phys_enc->pending_kickoff_cnt;
509 wait_info.timeout_ms = KICKOFF_TIMEOUT_MS;
510
511 if (!dpu_encoder_phys_vid_is_master(phys_enc)) {
512 return 0;
513 }
514
515 /* Wait for kickoff to complete */
516 ret = dpu_encoder_helper_wait_for_irq(phys_enc,
517 phys_enc->irq[INTR_IDX_VSYNC],
518 dpu_encoder_phys_vid_vblank_irq,
519 &wait_info);
520
521 if (ret == -ETIMEDOUT) {
522 dpu_encoder_helper_report_irq_timeout(phys_enc, INTR_IDX_VSYNC);
523 }
524
525 return ret;
526 }
527
dpu_encoder_phys_vid_wait_for_commit_done(struct dpu_encoder_phys * phys_enc)528 static int dpu_encoder_phys_vid_wait_for_commit_done(
529 struct dpu_encoder_phys *phys_enc)
530 {
531 struct dpu_hw_ctl *hw_ctl = phys_enc->hw_ctl;
532 int ret;
533
534 if (!hw_ctl)
535 return 0;
536
537 ret = wait_event_timeout(phys_enc->pending_kickoff_wq,
538 (hw_ctl->ops.get_flush_register(hw_ctl) == 0),
539 msecs_to_jiffies(50));
540 if (ret <= 0) {
541 DPU_ERROR("vblank timeout: %x\n", hw_ctl->ops.get_flush_register(hw_ctl));
542 return -ETIMEDOUT;
543 }
544
545 return 0;
546 }
547
dpu_encoder_phys_vid_prepare_for_kickoff(struct dpu_encoder_phys * phys_enc)548 static void dpu_encoder_phys_vid_prepare_for_kickoff(
549 struct dpu_encoder_phys *phys_enc)
550 {
551 struct dpu_hw_ctl *ctl;
552 int rc;
553 struct drm_encoder *drm_enc;
554
555 drm_enc = phys_enc->parent;
556
557 ctl = phys_enc->hw_ctl;
558 if (!ctl->ops.wait_reset_status)
559 return;
560
561 /*
562 * hw supports hardware initiated ctl reset, so before we kickoff a new
563 * frame, need to check and wait for hw initiated ctl reset completion
564 */
565 rc = ctl->ops.wait_reset_status(ctl);
566 if (rc) {
567 DPU_ERROR_VIDENC(phys_enc, "ctl %d reset failure: %d\n",
568 ctl->idx, rc);
569 msm_disp_snapshot_state(drm_enc->dev);
570 dpu_core_irq_unregister_callback(phys_enc->dpu_kms,
571 phys_enc->irq[INTR_IDX_VSYNC]);
572 }
573 }
574
dpu_encoder_phys_vid_disable(struct dpu_encoder_phys * phys_enc)575 static void dpu_encoder_phys_vid_disable(struct dpu_encoder_phys *phys_enc)
576 {
577 unsigned long lock_flags;
578 int ret;
579 struct dpu_hw_intf_status intf_status = {0};
580
581 if (!phys_enc->parent || !phys_enc->parent->dev) {
582 DPU_ERROR("invalid encoder/device\n");
583 return;
584 }
585
586 if (!phys_enc->hw_intf) {
587 DPU_ERROR("invalid hw_intf %d hw_ctl %d\n",
588 phys_enc->hw_intf != NULL, phys_enc->hw_ctl != NULL);
589 return;
590 }
591
592 if (WARN_ON(!phys_enc->hw_intf->ops.enable_timing))
593 return;
594
595 if (phys_enc->enable_state == DPU_ENC_DISABLED) {
596 DPU_ERROR("already disabled\n");
597 return;
598 }
599
600 spin_lock_irqsave(phys_enc->enc_spinlock, lock_flags);
601 phys_enc->hw_intf->ops.enable_timing(phys_enc->hw_intf, 0);
602 if (dpu_encoder_phys_vid_is_master(phys_enc))
603 dpu_encoder_phys_inc_pending(phys_enc);
604 spin_unlock_irqrestore(phys_enc->enc_spinlock, lock_flags);
605
606 /*
607 * Wait for a vsync so we know the ENABLE=0 latched before
608 * the (connector) source of the vsync's gets disabled,
609 * otherwise we end up in a funny state if we re-enable
610 * before the disable latches, which results that some of
611 * the settings changes for the new modeset (like new
612 * scanout buffer) don't latch properly..
613 */
614 if (dpu_encoder_phys_vid_is_master(phys_enc)) {
615 ret = dpu_encoder_phys_vid_wait_for_tx_complete(phys_enc);
616 if (ret) {
617 atomic_set(&phys_enc->pending_kickoff_cnt, 0);
618 DRM_ERROR("wait disable failed: id:%u intf:%d ret:%d\n",
619 DRMID(phys_enc->parent),
620 phys_enc->hw_intf->idx - INTF_0, ret);
621 }
622 }
623
624 if (phys_enc->hw_intf && phys_enc->hw_intf->ops.get_status)
625 phys_enc->hw_intf->ops.get_status(phys_enc->hw_intf, &intf_status);
626
627 /*
628 * Wait for a vsync if timing en status is on after timing engine
629 * is disabled.
630 */
631 if (intf_status.is_en && dpu_encoder_phys_vid_is_master(phys_enc)) {
632 spin_lock_irqsave(phys_enc->enc_spinlock, lock_flags);
633 dpu_encoder_phys_inc_pending(phys_enc);
634 spin_unlock_irqrestore(phys_enc->enc_spinlock, lock_flags);
635 ret = dpu_encoder_phys_vid_wait_for_tx_complete(phys_enc);
636 if (ret) {
637 atomic_set(&phys_enc->pending_kickoff_cnt, 0);
638 DRM_ERROR("wait disable failed: id:%u intf:%d ret:%d\n",
639 DRMID(phys_enc->parent),
640 phys_enc->hw_intf->idx - INTF_0, ret);
641 }
642 }
643
644 dpu_encoder_helper_phys_cleanup(phys_enc);
645 phys_enc->enable_state = DPU_ENC_DISABLED;
646 }
647
dpu_encoder_phys_vid_handle_post_kickoff(struct dpu_encoder_phys * phys_enc)648 static void dpu_encoder_phys_vid_handle_post_kickoff(
649 struct dpu_encoder_phys *phys_enc)
650 {
651 unsigned long lock_flags;
652
653 /*
654 * Video mode must flush CTL before enabling timing engine
655 * Video encoders need to turn on their interfaces now
656 */
657 if (phys_enc->enable_state == DPU_ENC_ENABLING) {
658 trace_dpu_enc_phys_vid_post_kickoff(DRMID(phys_enc->parent),
659 phys_enc->hw_intf->idx - INTF_0);
660 spin_lock_irqsave(phys_enc->enc_spinlock, lock_flags);
661 phys_enc->hw_intf->ops.enable_timing(phys_enc->hw_intf, 1);
662 spin_unlock_irqrestore(phys_enc->enc_spinlock, lock_flags);
663 phys_enc->enable_state = DPU_ENC_ENABLED;
664 }
665 }
666
dpu_encoder_phys_vid_irq_enable(struct dpu_encoder_phys * phys_enc)667 static void dpu_encoder_phys_vid_irq_enable(struct dpu_encoder_phys *phys_enc)
668 {
669 int ret;
670
671 trace_dpu_enc_phys_vid_irq_enable(DRMID(phys_enc->parent),
672 phys_enc->hw_intf->idx - INTF_0,
673 phys_enc->vblank_refcount);
674
675 ret = dpu_encoder_phys_vid_control_vblank_irq(phys_enc, true);
676 if (WARN_ON(ret))
677 return;
678
679 dpu_core_irq_register_callback(phys_enc->dpu_kms,
680 phys_enc->irq[INTR_IDX_UNDERRUN],
681 dpu_encoder_phys_vid_underrun_irq,
682 phys_enc);
683 }
684
dpu_encoder_phys_vid_irq_disable(struct dpu_encoder_phys * phys_enc)685 static void dpu_encoder_phys_vid_irq_disable(struct dpu_encoder_phys *phys_enc)
686 {
687 trace_dpu_enc_phys_vid_irq_disable(DRMID(phys_enc->parent),
688 phys_enc->hw_intf->idx - INTF_0,
689 phys_enc->vblank_refcount);
690
691 dpu_encoder_phys_vid_control_vblank_irq(phys_enc, false);
692 dpu_core_irq_unregister_callback(phys_enc->dpu_kms,
693 phys_enc->irq[INTR_IDX_UNDERRUN]);
694 }
695
dpu_encoder_phys_vid_get_line_count(struct dpu_encoder_phys * phys_enc)696 static int dpu_encoder_phys_vid_get_line_count(
697 struct dpu_encoder_phys *phys_enc)
698 {
699 if (!dpu_encoder_phys_vid_is_master(phys_enc))
700 return -EINVAL;
701
702 if (!phys_enc->hw_intf || !phys_enc->hw_intf->ops.get_line_count)
703 return -EINVAL;
704
705 return phys_enc->hw_intf->ops.get_line_count(phys_enc->hw_intf);
706 }
707
dpu_encoder_phys_vid_get_frame_count(struct dpu_encoder_phys * phys_enc)708 static int dpu_encoder_phys_vid_get_frame_count(
709 struct dpu_encoder_phys *phys_enc)
710 {
711 struct dpu_hw_intf_status s = {0};
712 u32 fetch_start = 0;
713 struct drm_display_mode mode;
714
715 drm_mode_init(&mode, &phys_enc->cached_mode);
716
717 if (!dpu_encoder_phys_vid_is_master(phys_enc))
718 return -EINVAL;
719
720 if (!phys_enc->hw_intf || !phys_enc->hw_intf->ops.get_status)
721 return -EINVAL;
722
723 phys_enc->hw_intf->ops.get_status(phys_enc->hw_intf, &s);
724
725 if (s.is_prog_fetch_en && s.is_en) {
726 fetch_start = mode.vtotal - (mode.vsync_start - mode.vdisplay);
727 if ((s.line_count > fetch_start) &&
728 (s.line_count <= mode.vtotal))
729 return s.frame_count + 1;
730 }
731
732 return s.frame_count;
733 }
734
dpu_encoder_phys_vid_init_ops(struct dpu_encoder_phys_ops * ops)735 static void dpu_encoder_phys_vid_init_ops(struct dpu_encoder_phys_ops *ops)
736 {
737 ops->is_master = dpu_encoder_phys_vid_is_master;
738 ops->atomic_mode_set = dpu_encoder_phys_vid_atomic_mode_set;
739 ops->enable = dpu_encoder_phys_vid_enable;
740 ops->disable = dpu_encoder_phys_vid_disable;
741 ops->control_vblank_irq = dpu_encoder_phys_vid_control_vblank_irq;
742 ops->wait_for_commit_done = dpu_encoder_phys_vid_wait_for_commit_done;
743 ops->wait_for_tx_complete = dpu_encoder_phys_vid_wait_for_tx_complete;
744 ops->irq_enable = dpu_encoder_phys_vid_irq_enable;
745 ops->irq_disable = dpu_encoder_phys_vid_irq_disable;
746 ops->prepare_for_kickoff = dpu_encoder_phys_vid_prepare_for_kickoff;
747 ops->handle_post_kickoff = dpu_encoder_phys_vid_handle_post_kickoff;
748 ops->needs_single_flush = dpu_encoder_phys_vid_needs_single_flush;
749 ops->get_line_count = dpu_encoder_phys_vid_get_line_count;
750 ops->get_frame_count = dpu_encoder_phys_vid_get_frame_count;
751 }
752
dpu_encoder_phys_vid_init(struct drm_device * dev,struct dpu_enc_phys_init_params * p)753 struct dpu_encoder_phys *dpu_encoder_phys_vid_init(struct drm_device *dev,
754 struct dpu_enc_phys_init_params *p)
755 {
756 struct dpu_encoder_phys *phys_enc = NULL;
757
758 if (!p) {
759 DPU_ERROR("failed to create encoder due to invalid parameter\n");
760 return ERR_PTR(-EINVAL);
761 }
762
763 phys_enc = drmm_kzalloc(dev, sizeof(*phys_enc), GFP_KERNEL);
764 if (!phys_enc) {
765 DPU_ERROR("failed to create encoder due to memory allocation error\n");
766 return ERR_PTR(-ENOMEM);
767 }
768
769 DPU_DEBUG_VIDENC(phys_enc, "\n");
770
771 dpu_encoder_phys_init(phys_enc, p);
772 mutex_init(&phys_enc->vblank_ctl_lock);
773 phys_enc->vblank_refcount = 0;
774
775 dpu_encoder_phys_vid_init_ops(&phys_enc->ops);
776 phys_enc->intf_mode = INTF_MODE_VIDEO;
777
778 DPU_DEBUG_VIDENC(phys_enc, "created intf idx:%d\n", p->hw_intf->idx);
779
780 return phys_enc;
781 }
782