1 /*
2 * Copyright (C) 2013, NVIDIA Corporation. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sub license,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the
12 * next paragraph) shall be included in all copies or substantial portions
13 * of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 */
23
24 #include <linux/delay.h>
25 #include <linux/gpio/consumer.h>
26 #include <linux/i2c.h>
27 #include <linux/media-bus-format.h>
28 #include <linux/module.h>
29 #include <linux/of_platform.h>
30 #include <linux/platform_device.h>
31 #include <linux/pm_runtime.h>
32 #include <linux/regulator/consumer.h>
33
34 #include <video/display_timing.h>
35 #include <video/of_display_timing.h>
36 #include <video/videomode.h>
37
38 #include <drm/drm_crtc.h>
39 #include <drm/drm_device.h>
40 #include <drm/drm_edid.h>
41 #include <drm/drm_mipi_dsi.h>
42 #include <drm/drm_panel.h>
43 #include <drm/drm_of.h>
44
45 /**
46 * struct panel_desc - Describes a simple panel.
47 */
48 struct panel_desc {
49 /**
50 * @modes: Pointer to array of fixed modes appropriate for this panel.
51 *
52 * If only one mode then this can just be the address of the mode.
53 * NOTE: cannot be used with "timings" and also if this is specified
54 * then you cannot override the mode in the device tree.
55 */
56 const struct drm_display_mode *modes;
57
58 /** @num_modes: Number of elements in modes array. */
59 unsigned int num_modes;
60
61 /**
62 * @timings: Pointer to array of display timings
63 *
64 * NOTE: cannot be used with "modes" and also these will be used to
65 * validate a device tree override if one is present.
66 */
67 const struct display_timing *timings;
68
69 /** @num_timings: Number of elements in timings array. */
70 unsigned int num_timings;
71
72 /** @bpc: Bits per color. */
73 unsigned int bpc;
74
75 /** @size: Structure containing the physical size of this panel. */
76 struct {
77 /**
78 * @size.width: Width (in mm) of the active display area.
79 */
80 unsigned int width;
81
82 /**
83 * @size.height: Height (in mm) of the active display area.
84 */
85 unsigned int height;
86 } size;
87
88 /** @delay: Structure containing various delay values for this panel. */
89 struct {
90 /**
91 * @delay.prepare: Time for the panel to become ready.
92 *
93 * The time (in milliseconds) that it takes for the panel to
94 * become ready and start receiving video data
95 */
96 unsigned int prepare;
97
98 /**
99 * @delay.enable: Time for the panel to display a valid frame.
100 *
101 * The time (in milliseconds) that it takes for the panel to
102 * display the first valid frame after starting to receive
103 * video data.
104 */
105 unsigned int enable;
106
107 /**
108 * @delay.disable: Time for the panel to turn the display off.
109 *
110 * The time (in milliseconds) that it takes for the panel to
111 * turn the display off (no content is visible).
112 */
113 unsigned int disable;
114
115 /**
116 * @delay.unprepare: Time to power down completely.
117 *
118 * The time (in milliseconds) that it takes for the panel
119 * to power itself down completely.
120 *
121 * This time is used to prevent a future "prepare" from
122 * starting until at least this many milliseconds has passed.
123 * If at prepare time less time has passed since unprepare
124 * finished, the driver waits for the remaining time.
125 */
126 unsigned int unprepare;
127 } delay;
128
129 /** @bus_format: See MEDIA_BUS_FMT_... defines. */
130 u32 bus_format;
131
132 /** @bus_flags: See DRM_BUS_FLAG_... defines. */
133 u32 bus_flags;
134
135 /** @connector_type: LVDS, eDP, DSI, DPI, etc. */
136 int connector_type;
137 };
138
139 struct panel_simple {
140 struct drm_panel base;
141
142 ktime_t unprepared_time;
143
144 const struct panel_desc *desc;
145
146 struct regulator *supply;
147 struct i2c_adapter *ddc;
148
149 struct gpio_desc *enable_gpio;
150
151 const struct drm_edid *drm_edid;
152
153 struct drm_display_mode override_mode;
154
155 enum drm_panel_orientation orientation;
156 };
157
to_panel_simple(struct drm_panel * panel)158 static inline struct panel_simple *to_panel_simple(struct drm_panel *panel)
159 {
160 return container_of(panel, struct panel_simple, base);
161 }
162
panel_simple_get_timings_modes(struct panel_simple * panel,struct drm_connector * connector)163 static unsigned int panel_simple_get_timings_modes(struct panel_simple *panel,
164 struct drm_connector *connector)
165 {
166 struct drm_display_mode *mode;
167 unsigned int i, num = 0;
168
169 for (i = 0; i < panel->desc->num_timings; i++) {
170 const struct display_timing *dt = &panel->desc->timings[i];
171 struct videomode vm;
172
173 videomode_from_timing(dt, &vm);
174 mode = drm_mode_create(connector->dev);
175 if (!mode) {
176 dev_err(panel->base.dev, "failed to add mode %ux%u\n",
177 dt->hactive.typ, dt->vactive.typ);
178 continue;
179 }
180
181 drm_display_mode_from_videomode(&vm, mode);
182
183 mode->type |= DRM_MODE_TYPE_DRIVER;
184
185 if (panel->desc->num_timings == 1)
186 mode->type |= DRM_MODE_TYPE_PREFERRED;
187
188 drm_mode_probed_add(connector, mode);
189 num++;
190 }
191
192 return num;
193 }
194
panel_simple_get_display_modes(struct panel_simple * panel,struct drm_connector * connector)195 static unsigned int panel_simple_get_display_modes(struct panel_simple *panel,
196 struct drm_connector *connector)
197 {
198 struct drm_display_mode *mode;
199 unsigned int i, num = 0;
200
201 for (i = 0; i < panel->desc->num_modes; i++) {
202 const struct drm_display_mode *m = &panel->desc->modes[i];
203
204 mode = drm_mode_duplicate(connector->dev, m);
205 if (!mode) {
206 dev_err(panel->base.dev, "failed to add mode %ux%u@%u\n",
207 m->hdisplay, m->vdisplay,
208 drm_mode_vrefresh(m));
209 continue;
210 }
211
212 mode->type |= DRM_MODE_TYPE_DRIVER;
213
214 if (panel->desc->num_modes == 1)
215 mode->type |= DRM_MODE_TYPE_PREFERRED;
216
217 drm_mode_set_name(mode);
218
219 drm_mode_probed_add(connector, mode);
220 num++;
221 }
222
223 return num;
224 }
225
panel_simple_get_non_edid_modes(struct panel_simple * panel,struct drm_connector * connector)226 static int panel_simple_get_non_edid_modes(struct panel_simple *panel,
227 struct drm_connector *connector)
228 {
229 struct drm_display_mode *mode;
230 bool has_override = panel->override_mode.type;
231 unsigned int num = 0;
232
233 if (!panel->desc)
234 return 0;
235
236 if (has_override) {
237 mode = drm_mode_duplicate(connector->dev,
238 &panel->override_mode);
239 if (mode) {
240 drm_mode_probed_add(connector, mode);
241 num = 1;
242 } else {
243 dev_err(panel->base.dev, "failed to add override mode\n");
244 }
245 }
246
247 /* Only add timings if override was not there or failed to validate */
248 if (num == 0 && panel->desc->num_timings)
249 num = panel_simple_get_timings_modes(panel, connector);
250
251 /*
252 * Only add fixed modes if timings/override added no mode.
253 *
254 * We should only ever have either the display timings specified
255 * or a fixed mode. Anything else is rather bogus.
256 */
257 WARN_ON(panel->desc->num_timings && panel->desc->num_modes);
258 if (num == 0)
259 num = panel_simple_get_display_modes(panel, connector);
260
261 connector->display_info.bpc = panel->desc->bpc;
262 connector->display_info.width_mm = panel->desc->size.width;
263 connector->display_info.height_mm = panel->desc->size.height;
264 if (panel->desc->bus_format)
265 drm_display_info_set_bus_formats(&connector->display_info,
266 &panel->desc->bus_format, 1);
267 connector->display_info.bus_flags = panel->desc->bus_flags;
268
269 return num;
270 }
271
panel_simple_wait(ktime_t start_ktime,unsigned int min_ms)272 static void panel_simple_wait(ktime_t start_ktime, unsigned int min_ms)
273 {
274 ktime_t now_ktime, min_ktime;
275
276 if (!min_ms)
277 return;
278
279 min_ktime = ktime_add(start_ktime, ms_to_ktime(min_ms));
280 now_ktime = ktime_get_boottime();
281
282 if (ktime_before(now_ktime, min_ktime))
283 msleep(ktime_to_ms(ktime_sub(min_ktime, now_ktime)) + 1);
284 }
285
panel_simple_disable(struct drm_panel * panel)286 static int panel_simple_disable(struct drm_panel *panel)
287 {
288 struct panel_simple *p = to_panel_simple(panel);
289
290 if (p->desc->delay.disable)
291 msleep(p->desc->delay.disable);
292
293 return 0;
294 }
295
panel_simple_suspend(struct device * dev)296 static int panel_simple_suspend(struct device *dev)
297 {
298 struct panel_simple *p = dev_get_drvdata(dev);
299
300 gpiod_set_value_cansleep(p->enable_gpio, 0);
301 regulator_disable(p->supply);
302 p->unprepared_time = ktime_get_boottime();
303
304 drm_edid_free(p->drm_edid);
305 p->drm_edid = NULL;
306
307 return 0;
308 }
309
panel_simple_unprepare(struct drm_panel * panel)310 static int panel_simple_unprepare(struct drm_panel *panel)
311 {
312 int ret;
313
314 pm_runtime_mark_last_busy(panel->dev);
315 ret = pm_runtime_put_autosuspend(panel->dev);
316 if (ret < 0)
317 return ret;
318
319 return 0;
320 }
321
panel_simple_resume(struct device * dev)322 static int panel_simple_resume(struct device *dev)
323 {
324 struct panel_simple *p = dev_get_drvdata(dev);
325 int err;
326
327 panel_simple_wait(p->unprepared_time, p->desc->delay.unprepare);
328
329 err = regulator_enable(p->supply);
330 if (err < 0) {
331 dev_err(dev, "failed to enable supply: %d\n", err);
332 return err;
333 }
334
335 gpiod_set_value_cansleep(p->enable_gpio, 1);
336
337 if (p->desc->delay.prepare)
338 msleep(p->desc->delay.prepare);
339
340 return 0;
341 }
342
panel_simple_prepare(struct drm_panel * panel)343 static int panel_simple_prepare(struct drm_panel *panel)
344 {
345 int ret;
346
347 ret = pm_runtime_get_sync(panel->dev);
348 if (ret < 0) {
349 pm_runtime_put_autosuspend(panel->dev);
350 return ret;
351 }
352
353 return 0;
354 }
355
panel_simple_enable(struct drm_panel * panel)356 static int panel_simple_enable(struct drm_panel *panel)
357 {
358 struct panel_simple *p = to_panel_simple(panel);
359
360 if (p->desc->delay.enable)
361 msleep(p->desc->delay.enable);
362
363 return 0;
364 }
365
panel_simple_get_modes(struct drm_panel * panel,struct drm_connector * connector)366 static int panel_simple_get_modes(struct drm_panel *panel,
367 struct drm_connector *connector)
368 {
369 struct panel_simple *p = to_panel_simple(panel);
370 int num = 0;
371
372 /* probe EDID if a DDC bus is available */
373 if (p->ddc) {
374 pm_runtime_get_sync(panel->dev);
375
376 if (!p->drm_edid)
377 p->drm_edid = drm_edid_read_ddc(connector, p->ddc);
378
379 drm_edid_connector_update(connector, p->drm_edid);
380
381 num += drm_edid_connector_add_modes(connector);
382
383 pm_runtime_mark_last_busy(panel->dev);
384 pm_runtime_put_autosuspend(panel->dev);
385 }
386
387 /* add hard-coded panel modes */
388 num += panel_simple_get_non_edid_modes(p, connector);
389
390 /*
391 * TODO: Remove once all drm drivers call
392 * drm_connector_set_orientation_from_panel()
393 */
394 drm_connector_set_panel_orientation(connector, p->orientation);
395
396 return num;
397 }
398
panel_simple_get_timings(struct drm_panel * panel,unsigned int num_timings,struct display_timing * timings)399 static int panel_simple_get_timings(struct drm_panel *panel,
400 unsigned int num_timings,
401 struct display_timing *timings)
402 {
403 struct panel_simple *p = to_panel_simple(panel);
404 unsigned int i;
405
406 if (p->desc->num_timings < num_timings)
407 num_timings = p->desc->num_timings;
408
409 if (timings)
410 for (i = 0; i < num_timings; i++)
411 timings[i] = p->desc->timings[i];
412
413 return p->desc->num_timings;
414 }
415
panel_simple_get_orientation(struct drm_panel * panel)416 static enum drm_panel_orientation panel_simple_get_orientation(struct drm_panel *panel)
417 {
418 struct panel_simple *p = to_panel_simple(panel);
419
420 return p->orientation;
421 }
422
423 static const struct drm_panel_funcs panel_simple_funcs = {
424 .disable = panel_simple_disable,
425 .unprepare = panel_simple_unprepare,
426 .prepare = panel_simple_prepare,
427 .enable = panel_simple_enable,
428 .get_modes = panel_simple_get_modes,
429 .get_orientation = panel_simple_get_orientation,
430 .get_timings = panel_simple_get_timings,
431 };
432
433 static struct panel_desc panel_dpi;
434
panel_dpi_probe(struct device * dev,struct panel_simple * panel)435 static int panel_dpi_probe(struct device *dev,
436 struct panel_simple *panel)
437 {
438 struct display_timing *timing;
439 const struct device_node *np;
440 struct panel_desc *desc;
441 unsigned int bus_flags;
442 struct videomode vm;
443 int ret;
444
445 np = dev->of_node;
446 desc = devm_kzalloc(dev, sizeof(*desc), GFP_KERNEL);
447 if (!desc)
448 return -ENOMEM;
449
450 timing = devm_kzalloc(dev, sizeof(*timing), GFP_KERNEL);
451 if (!timing)
452 return -ENOMEM;
453
454 ret = of_get_display_timing(np, "panel-timing", timing);
455 if (ret < 0) {
456 dev_err(dev, "%pOF: no panel-timing node found for \"panel-dpi\" binding\n",
457 np);
458 return ret;
459 }
460
461 desc->timings = timing;
462 desc->num_timings = 1;
463
464 of_property_read_u32(np, "width-mm", &desc->size.width);
465 of_property_read_u32(np, "height-mm", &desc->size.height);
466
467 /* Extract bus_flags from display_timing */
468 bus_flags = 0;
469 vm.flags = timing->flags;
470 drm_bus_flags_from_videomode(&vm, &bus_flags);
471 desc->bus_flags = bus_flags;
472
473 /* We do not know the connector for the DT node, so guess it */
474 desc->connector_type = DRM_MODE_CONNECTOR_DPI;
475
476 panel->desc = desc;
477
478 return 0;
479 }
480
481 #define PANEL_SIMPLE_BOUNDS_CHECK(to_check, bounds, field) \
482 (to_check->field.typ >= bounds->field.min && \
483 to_check->field.typ <= bounds->field.max)
panel_simple_parse_panel_timing_node(struct device * dev,struct panel_simple * panel,const struct display_timing * ot)484 static void panel_simple_parse_panel_timing_node(struct device *dev,
485 struct panel_simple *panel,
486 const struct display_timing *ot)
487 {
488 const struct panel_desc *desc = panel->desc;
489 struct videomode vm;
490 unsigned int i;
491
492 if (WARN_ON(desc->num_modes)) {
493 dev_err(dev, "Reject override mode: panel has a fixed mode\n");
494 return;
495 }
496 if (WARN_ON(!desc->num_timings)) {
497 dev_err(dev, "Reject override mode: no timings specified\n");
498 return;
499 }
500
501 for (i = 0; i < panel->desc->num_timings; i++) {
502 const struct display_timing *dt = &panel->desc->timings[i];
503
504 if (!PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hactive) ||
505 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hfront_porch) ||
506 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hback_porch) ||
507 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hsync_len) ||
508 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vactive) ||
509 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vfront_porch) ||
510 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vback_porch) ||
511 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vsync_len))
512 continue;
513
514 if (ot->flags != dt->flags)
515 continue;
516
517 videomode_from_timing(ot, &vm);
518 drm_display_mode_from_videomode(&vm, &panel->override_mode);
519 panel->override_mode.type |= DRM_MODE_TYPE_DRIVER |
520 DRM_MODE_TYPE_PREFERRED;
521 break;
522 }
523
524 if (WARN_ON(!panel->override_mode.type))
525 dev_err(dev, "Reject override mode: No display_timing found\n");
526 }
527
panel_simple_override_nondefault_lvds_datamapping(struct device * dev,struct panel_simple * panel)528 static int panel_simple_override_nondefault_lvds_datamapping(struct device *dev,
529 struct panel_simple *panel)
530 {
531 int ret, bpc;
532
533 ret = drm_of_lvds_get_data_mapping(dev->of_node);
534 if (ret < 0) {
535 if (ret == -EINVAL)
536 dev_warn(dev, "Ignore invalid data-mapping property\n");
537
538 /*
539 * Ignore non-existing or malformatted property, fallback to
540 * default data-mapping, and return 0.
541 */
542 return 0;
543 }
544
545 switch (ret) {
546 default:
547 WARN_ON(1);
548 fallthrough;
549 case MEDIA_BUS_FMT_RGB888_1X7X4_SPWG:
550 fallthrough;
551 case MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA:
552 bpc = 8;
553 break;
554 case MEDIA_BUS_FMT_RGB666_1X7X3_SPWG:
555 bpc = 6;
556 }
557
558 if (panel->desc->bpc != bpc || panel->desc->bus_format != ret) {
559 struct panel_desc *override_desc;
560
561 override_desc = devm_kmemdup(dev, panel->desc, sizeof(*panel->desc), GFP_KERNEL);
562 if (!override_desc)
563 return -ENOMEM;
564
565 override_desc->bus_format = ret;
566 override_desc->bpc = bpc;
567 panel->desc = override_desc;
568 }
569
570 return 0;
571 }
572
panel_simple_probe(struct device * dev,const struct panel_desc * desc)573 static int panel_simple_probe(struct device *dev, const struct panel_desc *desc)
574 {
575 struct panel_simple *panel;
576 struct display_timing dt;
577 struct device_node *ddc;
578 int connector_type;
579 u32 bus_flags;
580 int err;
581
582 panel = devm_kzalloc(dev, sizeof(*panel), GFP_KERNEL);
583 if (!panel)
584 return -ENOMEM;
585
586 panel->desc = desc;
587
588 panel->supply = devm_regulator_get(dev, "power");
589 if (IS_ERR(panel->supply))
590 return PTR_ERR(panel->supply);
591
592 panel->enable_gpio = devm_gpiod_get_optional(dev, "enable",
593 GPIOD_OUT_LOW);
594 if (IS_ERR(panel->enable_gpio))
595 return dev_err_probe(dev, PTR_ERR(panel->enable_gpio),
596 "failed to request GPIO\n");
597
598 err = of_drm_get_panel_orientation(dev->of_node, &panel->orientation);
599 if (err) {
600 dev_err(dev, "%pOF: failed to get orientation %d\n", dev->of_node, err);
601 return err;
602 }
603
604 ddc = of_parse_phandle(dev->of_node, "ddc-i2c-bus", 0);
605 if (ddc) {
606 panel->ddc = of_find_i2c_adapter_by_node(ddc);
607 of_node_put(ddc);
608
609 if (!panel->ddc)
610 return -EPROBE_DEFER;
611 }
612
613 if (desc == &panel_dpi) {
614 /* Handle the generic panel-dpi binding */
615 err = panel_dpi_probe(dev, panel);
616 if (err)
617 goto free_ddc;
618 desc = panel->desc;
619 } else {
620 if (!of_get_display_timing(dev->of_node, "panel-timing", &dt))
621 panel_simple_parse_panel_timing_node(dev, panel, &dt);
622 }
623
624 if (desc->connector_type == DRM_MODE_CONNECTOR_LVDS) {
625 /* Optional data-mapping property for overriding bus format */
626 err = panel_simple_override_nondefault_lvds_datamapping(dev, panel);
627 if (err)
628 goto free_ddc;
629 }
630
631 connector_type = desc->connector_type;
632 /* Catch common mistakes for panels. */
633 switch (connector_type) {
634 case 0:
635 dev_warn(dev, "Specify missing connector_type\n");
636 connector_type = DRM_MODE_CONNECTOR_DPI;
637 break;
638 case DRM_MODE_CONNECTOR_LVDS:
639 WARN_ON(desc->bus_flags &
640 ~(DRM_BUS_FLAG_DE_LOW |
641 DRM_BUS_FLAG_DE_HIGH |
642 DRM_BUS_FLAG_DATA_MSB_TO_LSB |
643 DRM_BUS_FLAG_DATA_LSB_TO_MSB));
644 WARN_ON(desc->bus_format != MEDIA_BUS_FMT_RGB666_1X7X3_SPWG &&
645 desc->bus_format != MEDIA_BUS_FMT_RGB888_1X7X4_SPWG &&
646 desc->bus_format != MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA);
647 WARN_ON(desc->bus_format == MEDIA_BUS_FMT_RGB666_1X7X3_SPWG &&
648 desc->bpc != 6);
649 WARN_ON((desc->bus_format == MEDIA_BUS_FMT_RGB888_1X7X4_SPWG ||
650 desc->bus_format == MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA) &&
651 desc->bpc != 8);
652 break;
653 case DRM_MODE_CONNECTOR_eDP:
654 dev_warn(dev, "eDP panels moved to panel-edp\n");
655 err = -EINVAL;
656 goto free_ddc;
657 case DRM_MODE_CONNECTOR_DSI:
658 if (desc->bpc != 6 && desc->bpc != 8)
659 dev_warn(dev, "Expected bpc in {6,8} but got: %u\n", desc->bpc);
660 break;
661 case DRM_MODE_CONNECTOR_DPI:
662 bus_flags = DRM_BUS_FLAG_DE_LOW |
663 DRM_BUS_FLAG_DE_HIGH |
664 DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE |
665 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE |
666 DRM_BUS_FLAG_DATA_MSB_TO_LSB |
667 DRM_BUS_FLAG_DATA_LSB_TO_MSB |
668 DRM_BUS_FLAG_SYNC_SAMPLE_POSEDGE |
669 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE;
670 if (desc->bus_flags & ~bus_flags)
671 dev_warn(dev, "Unexpected bus_flags(%d)\n", desc->bus_flags & ~bus_flags);
672 if (!(desc->bus_flags & bus_flags))
673 dev_warn(dev, "Specify missing bus_flags\n");
674 if (desc->bus_format == 0)
675 dev_warn(dev, "Specify missing bus_format\n");
676 if (desc->bpc != 6 && desc->bpc != 8)
677 dev_warn(dev, "Expected bpc in {6,8} but got: %u\n", desc->bpc);
678 break;
679 default:
680 dev_warn(dev, "Specify a valid connector_type: %d\n", desc->connector_type);
681 connector_type = DRM_MODE_CONNECTOR_DPI;
682 break;
683 }
684
685 dev_set_drvdata(dev, panel);
686
687 /*
688 * We use runtime PM for prepare / unprepare since those power the panel
689 * on and off and those can be very slow operations. This is important
690 * to optimize powering the panel on briefly to read the EDID before
691 * fully enabling the panel.
692 */
693 pm_runtime_enable(dev);
694 pm_runtime_set_autosuspend_delay(dev, 1000);
695 pm_runtime_use_autosuspend(dev);
696
697 drm_panel_init(&panel->base, dev, &panel_simple_funcs, connector_type);
698
699 err = drm_panel_of_backlight(&panel->base);
700 if (err) {
701 dev_err_probe(dev, err, "Could not find backlight\n");
702 goto disable_pm_runtime;
703 }
704
705 drm_panel_add(&panel->base);
706
707 return 0;
708
709 disable_pm_runtime:
710 pm_runtime_dont_use_autosuspend(dev);
711 pm_runtime_disable(dev);
712 free_ddc:
713 if (panel->ddc)
714 put_device(&panel->ddc->dev);
715
716 return err;
717 }
718
panel_simple_shutdown(struct device * dev)719 static void panel_simple_shutdown(struct device *dev)
720 {
721 struct panel_simple *panel = dev_get_drvdata(dev);
722
723 /*
724 * NOTE: the following two calls don't really belong here. It is the
725 * responsibility of a correctly written DRM modeset driver to call
726 * drm_atomic_helper_shutdown() at shutdown time and that should
727 * cause the panel to be disabled / unprepared if needed. For now,
728 * however, we'll keep these calls due to the sheer number of
729 * different DRM modeset drivers used with panel-simple. Once we've
730 * confirmed that all DRM modeset drivers using this panel properly
731 * call drm_atomic_helper_shutdown() we can simply delete the two
732 * calls below.
733 *
734 * TO BE EXPLICIT: THE CALLS BELOW SHOULDN'T BE COPIED TO ANY NEW
735 * PANEL DRIVERS.
736 *
737 * FIXME: If we're still haven't figured out if all DRM modeset
738 * drivers properly call drm_atomic_helper_shutdown() but we _have_
739 * managed to make sure that DRM modeset drivers get their shutdown()
740 * callback before the panel's shutdown() callback (perhaps using
741 * device link), we could add a WARN_ON here to help move forward.
742 */
743 if (panel->base.enabled)
744 drm_panel_disable(&panel->base);
745 if (panel->base.prepared)
746 drm_panel_unprepare(&panel->base);
747 }
748
panel_simple_remove(struct device * dev)749 static void panel_simple_remove(struct device *dev)
750 {
751 struct panel_simple *panel = dev_get_drvdata(dev);
752
753 drm_panel_remove(&panel->base);
754 panel_simple_shutdown(dev);
755
756 pm_runtime_dont_use_autosuspend(dev);
757 pm_runtime_disable(dev);
758 if (panel->ddc)
759 put_device(&panel->ddc->dev);
760 }
761
762 static const struct drm_display_mode ampire_am_1280800n3tzqw_t00h_mode = {
763 .clock = 71100,
764 .hdisplay = 1280,
765 .hsync_start = 1280 + 40,
766 .hsync_end = 1280 + 40 + 80,
767 .htotal = 1280 + 40 + 80 + 40,
768 .vdisplay = 800,
769 .vsync_start = 800 + 3,
770 .vsync_end = 800 + 3 + 10,
771 .vtotal = 800 + 3 + 10 + 10,
772 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
773 };
774
775 static const struct panel_desc ampire_am_1280800n3tzqw_t00h = {
776 .modes = &ire_am_1280800n3tzqw_t00h_mode,
777 .num_modes = 1,
778 .bpc = 8,
779 .size = {
780 .width = 217,
781 .height = 136,
782 },
783 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
784 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
785 .connector_type = DRM_MODE_CONNECTOR_LVDS,
786 };
787
788 static const struct drm_display_mode ampire_am_480272h3tmqw_t01h_mode = {
789 .clock = 9000,
790 .hdisplay = 480,
791 .hsync_start = 480 + 2,
792 .hsync_end = 480 + 2 + 41,
793 .htotal = 480 + 2 + 41 + 2,
794 .vdisplay = 272,
795 .vsync_start = 272 + 2,
796 .vsync_end = 272 + 2 + 10,
797 .vtotal = 272 + 2 + 10 + 2,
798 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
799 };
800
801 static const struct panel_desc ampire_am_480272h3tmqw_t01h = {
802 .modes = &ire_am_480272h3tmqw_t01h_mode,
803 .num_modes = 1,
804 .bpc = 8,
805 .size = {
806 .width = 99,
807 .height = 58,
808 },
809 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
810 };
811
812 static const struct drm_display_mode ampire_am800480r3tmqwa1h_mode = {
813 .clock = 33333,
814 .hdisplay = 800,
815 .hsync_start = 800 + 0,
816 .hsync_end = 800 + 0 + 255,
817 .htotal = 800 + 0 + 255 + 0,
818 .vdisplay = 480,
819 .vsync_start = 480 + 2,
820 .vsync_end = 480 + 2 + 45,
821 .vtotal = 480 + 2 + 45 + 0,
822 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
823 };
824
825 static const struct display_timing ampire_am_800480l1tmqw_t00h_timing = {
826 .pixelclock = { 29930000, 33260000, 36590000 },
827 .hactive = { 800, 800, 800 },
828 .hfront_porch = { 1, 40, 168 },
829 .hback_porch = { 88, 88, 88 },
830 .hsync_len = { 1, 128, 128 },
831 .vactive = { 480, 480, 480 },
832 .vfront_porch = { 1, 35, 37 },
833 .vback_porch = { 8, 8, 8 },
834 .vsync_len = { 1, 2, 2 },
835 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
836 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE |
837 DISPLAY_FLAGS_SYNC_POSEDGE,
838 };
839
840 static const struct panel_desc ampire_am_800480l1tmqw_t00h = {
841 .timings = &ire_am_800480l1tmqw_t00h_timing,
842 .num_timings = 1,
843 .bpc = 8,
844 .size = {
845 .width = 111,
846 .height = 67,
847 },
848 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
849 .bus_flags = DRM_BUS_FLAG_DE_HIGH |
850 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE |
851 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE,
852 .connector_type = DRM_MODE_CONNECTOR_DPI,
853 };
854
855 static const struct panel_desc ampire_am800480r3tmqwa1h = {
856 .modes = &ire_am800480r3tmqwa1h_mode,
857 .num_modes = 1,
858 .bpc = 6,
859 .size = {
860 .width = 152,
861 .height = 91,
862 },
863 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
864 };
865
866 static const struct display_timing ampire_am800600p5tmqw_tb8h_timing = {
867 .pixelclock = { 34500000, 39600000, 50400000 },
868 .hactive = { 800, 800, 800 },
869 .hfront_porch = { 12, 112, 312 },
870 .hback_porch = { 87, 87, 48 },
871 .hsync_len = { 1, 1, 40 },
872 .vactive = { 600, 600, 600 },
873 .vfront_porch = { 1, 21, 61 },
874 .vback_porch = { 38, 38, 19 },
875 .vsync_len = { 1, 1, 20 },
876 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
877 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE |
878 DISPLAY_FLAGS_SYNC_POSEDGE,
879 };
880
881 static const struct panel_desc ampire_am800600p5tmqwtb8h = {
882 .timings = &ire_am800600p5tmqw_tb8h_timing,
883 .num_timings = 1,
884 .bpc = 6,
885 .size = {
886 .width = 162,
887 .height = 122,
888 },
889 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
890 .bus_flags = DRM_BUS_FLAG_DE_HIGH |
891 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE |
892 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE,
893 .connector_type = DRM_MODE_CONNECTOR_DPI,
894 };
895
896 static const struct display_timing santek_st0700i5y_rbslw_f_timing = {
897 .pixelclock = { 26400000, 33300000, 46800000 },
898 .hactive = { 800, 800, 800 },
899 .hfront_porch = { 16, 210, 354 },
900 .hback_porch = { 45, 36, 6 },
901 .hsync_len = { 1, 10, 40 },
902 .vactive = { 480, 480, 480 },
903 .vfront_porch = { 7, 22, 147 },
904 .vback_porch = { 22, 13, 3 },
905 .vsync_len = { 1, 10, 20 },
906 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
907 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE
908 };
909
910 static const struct panel_desc armadeus_st0700_adapt = {
911 .timings = &santek_st0700i5y_rbslw_f_timing,
912 .num_timings = 1,
913 .bpc = 6,
914 .size = {
915 .width = 154,
916 .height = 86,
917 },
918 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
919 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
920 };
921
922 static const struct drm_display_mode auo_b101aw03_mode = {
923 .clock = 51450,
924 .hdisplay = 1024,
925 .hsync_start = 1024 + 156,
926 .hsync_end = 1024 + 156 + 8,
927 .htotal = 1024 + 156 + 8 + 156,
928 .vdisplay = 600,
929 .vsync_start = 600 + 16,
930 .vsync_end = 600 + 16 + 6,
931 .vtotal = 600 + 16 + 6 + 16,
932 };
933
934 static const struct panel_desc auo_b101aw03 = {
935 .modes = &auo_b101aw03_mode,
936 .num_modes = 1,
937 .bpc = 6,
938 .size = {
939 .width = 223,
940 .height = 125,
941 },
942 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
943 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
944 .connector_type = DRM_MODE_CONNECTOR_LVDS,
945 };
946
947 static const struct drm_display_mode auo_b101xtn01_mode = {
948 .clock = 72000,
949 .hdisplay = 1366,
950 .hsync_start = 1366 + 20,
951 .hsync_end = 1366 + 20 + 70,
952 .htotal = 1366 + 20 + 70,
953 .vdisplay = 768,
954 .vsync_start = 768 + 14,
955 .vsync_end = 768 + 14 + 42,
956 .vtotal = 768 + 14 + 42,
957 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
958 };
959
960 static const struct panel_desc auo_b101xtn01 = {
961 .modes = &auo_b101xtn01_mode,
962 .num_modes = 1,
963 .bpc = 6,
964 .size = {
965 .width = 223,
966 .height = 125,
967 },
968 };
969
970 static const struct drm_display_mode auo_b116xw03_mode = {
971 .clock = 70589,
972 .hdisplay = 1366,
973 .hsync_start = 1366 + 40,
974 .hsync_end = 1366 + 40 + 40,
975 .htotal = 1366 + 40 + 40 + 32,
976 .vdisplay = 768,
977 .vsync_start = 768 + 10,
978 .vsync_end = 768 + 10 + 12,
979 .vtotal = 768 + 10 + 12 + 6,
980 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
981 };
982
983 static const struct panel_desc auo_b116xw03 = {
984 .modes = &auo_b116xw03_mode,
985 .num_modes = 1,
986 .bpc = 6,
987 .size = {
988 .width = 256,
989 .height = 144,
990 },
991 .delay = {
992 .prepare = 1,
993 .enable = 200,
994 .disable = 200,
995 .unprepare = 500,
996 },
997 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
998 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
999 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1000 };
1001
1002 static const struct display_timing auo_g070vvn01_timings = {
1003 .pixelclock = { 33300000, 34209000, 45000000 },
1004 .hactive = { 800, 800, 800 },
1005 .hfront_porch = { 20, 40, 200 },
1006 .hback_porch = { 87, 40, 1 },
1007 .hsync_len = { 1, 48, 87 },
1008 .vactive = { 480, 480, 480 },
1009 .vfront_porch = { 5, 13, 200 },
1010 .vback_porch = { 31, 31, 29 },
1011 .vsync_len = { 1, 1, 3 },
1012 };
1013
1014 static const struct panel_desc auo_g070vvn01 = {
1015 .timings = &auo_g070vvn01_timings,
1016 .num_timings = 1,
1017 .bpc = 8,
1018 .size = {
1019 .width = 152,
1020 .height = 91,
1021 },
1022 .delay = {
1023 .prepare = 200,
1024 .enable = 50,
1025 .disable = 50,
1026 .unprepare = 1000,
1027 },
1028 };
1029
1030 static const struct display_timing auo_g101evn010_timing = {
1031 .pixelclock = { 64000000, 68930000, 85000000 },
1032 .hactive = { 1280, 1280, 1280 },
1033 .hfront_porch = { 8, 64, 256 },
1034 .hback_porch = { 8, 64, 256 },
1035 .hsync_len = { 40, 168, 767 },
1036 .vactive = { 800, 800, 800 },
1037 .vfront_porch = { 4, 8, 100 },
1038 .vback_porch = { 4, 8, 100 },
1039 .vsync_len = { 8, 16, 223 },
1040 };
1041
1042 static const struct panel_desc auo_g101evn010 = {
1043 .timings = &auo_g101evn010_timing,
1044 .num_timings = 1,
1045 .bpc = 6,
1046 .size = {
1047 .width = 216,
1048 .height = 135,
1049 },
1050 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
1051 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
1052 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1053 };
1054
1055 static const struct drm_display_mode auo_g104sn02_mode = {
1056 .clock = 40000,
1057 .hdisplay = 800,
1058 .hsync_start = 800 + 40,
1059 .hsync_end = 800 + 40 + 216,
1060 .htotal = 800 + 40 + 216 + 128,
1061 .vdisplay = 600,
1062 .vsync_start = 600 + 10,
1063 .vsync_end = 600 + 10 + 35,
1064 .vtotal = 600 + 10 + 35 + 2,
1065 };
1066
1067 static const struct panel_desc auo_g104sn02 = {
1068 .modes = &auo_g104sn02_mode,
1069 .num_modes = 1,
1070 .bpc = 8,
1071 .size = {
1072 .width = 211,
1073 .height = 158,
1074 },
1075 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1076 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1077 };
1078
1079 static const struct drm_display_mode auo_g104stn01_mode = {
1080 .clock = 40000,
1081 .hdisplay = 800,
1082 .hsync_start = 800 + 40,
1083 .hsync_end = 800 + 40 + 88,
1084 .htotal = 800 + 40 + 88 + 128,
1085 .vdisplay = 600,
1086 .vsync_start = 600 + 1,
1087 .vsync_end = 600 + 1 + 23,
1088 .vtotal = 600 + 1 + 23 + 4,
1089 };
1090
1091 static const struct panel_desc auo_g104stn01 = {
1092 .modes = &auo_g104stn01_mode,
1093 .num_modes = 1,
1094 .bpc = 8,
1095 .size = {
1096 .width = 211,
1097 .height = 158,
1098 },
1099 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1100 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1101 };
1102
1103 static const struct display_timing auo_g121ean01_timing = {
1104 .pixelclock = { 60000000, 74400000, 90000000 },
1105 .hactive = { 1280, 1280, 1280 },
1106 .hfront_porch = { 20, 50, 100 },
1107 .hback_porch = { 20, 50, 100 },
1108 .hsync_len = { 30, 100, 200 },
1109 .vactive = { 800, 800, 800 },
1110 .vfront_porch = { 2, 10, 25 },
1111 .vback_porch = { 2, 10, 25 },
1112 .vsync_len = { 4, 18, 50 },
1113 };
1114
1115 static const struct panel_desc auo_g121ean01 = {
1116 .timings = &auo_g121ean01_timing,
1117 .num_timings = 1,
1118 .bpc = 8,
1119 .size = {
1120 .width = 261,
1121 .height = 163,
1122 },
1123 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1124 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1125 };
1126
1127 static const struct display_timing auo_g133han01_timings = {
1128 .pixelclock = { 134000000, 141200000, 149000000 },
1129 .hactive = { 1920, 1920, 1920 },
1130 .hfront_porch = { 39, 58, 77 },
1131 .hback_porch = { 59, 88, 117 },
1132 .hsync_len = { 28, 42, 56 },
1133 .vactive = { 1080, 1080, 1080 },
1134 .vfront_porch = { 3, 8, 11 },
1135 .vback_porch = { 5, 14, 19 },
1136 .vsync_len = { 4, 14, 19 },
1137 };
1138
1139 static const struct panel_desc auo_g133han01 = {
1140 .timings = &auo_g133han01_timings,
1141 .num_timings = 1,
1142 .bpc = 8,
1143 .size = {
1144 .width = 293,
1145 .height = 165,
1146 },
1147 .delay = {
1148 .prepare = 200,
1149 .enable = 50,
1150 .disable = 50,
1151 .unprepare = 1000,
1152 },
1153 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA,
1154 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1155 };
1156
1157 static const struct display_timing auo_g156han04_timings = {
1158 .pixelclock = { 137000000, 141000000, 146000000 },
1159 .hactive = { 1920, 1920, 1920 },
1160 .hfront_porch = { 60, 60, 60 },
1161 .hback_porch = { 90, 92, 111 },
1162 .hsync_len = { 32, 32, 32 },
1163 .vactive = { 1080, 1080, 1080 },
1164 .vfront_porch = { 12, 12, 12 },
1165 .vback_porch = { 24, 36, 56 },
1166 .vsync_len = { 8, 8, 8 },
1167 };
1168
1169 static const struct panel_desc auo_g156han04 = {
1170 .timings = &auo_g156han04_timings,
1171 .num_timings = 1,
1172 .bpc = 8,
1173 .size = {
1174 .width = 344,
1175 .height = 194,
1176 },
1177 .delay = {
1178 .prepare = 50, /* T2 */
1179 .enable = 200, /* T3 */
1180 .disable = 110, /* T10 */
1181 .unprepare = 1000, /* T13 */
1182 },
1183 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1184 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
1185 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1186 };
1187
1188 static const struct drm_display_mode auo_g156xtn01_mode = {
1189 .clock = 76000,
1190 .hdisplay = 1366,
1191 .hsync_start = 1366 + 33,
1192 .hsync_end = 1366 + 33 + 67,
1193 .htotal = 1560,
1194 .vdisplay = 768,
1195 .vsync_start = 768 + 4,
1196 .vsync_end = 768 + 4 + 4,
1197 .vtotal = 806,
1198 };
1199
1200 static const struct panel_desc auo_g156xtn01 = {
1201 .modes = &auo_g156xtn01_mode,
1202 .num_modes = 1,
1203 .bpc = 8,
1204 .size = {
1205 .width = 344,
1206 .height = 194,
1207 },
1208 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1209 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1210 };
1211
1212 static const struct display_timing auo_g185han01_timings = {
1213 .pixelclock = { 120000000, 144000000, 175000000 },
1214 .hactive = { 1920, 1920, 1920 },
1215 .hfront_porch = { 36, 120, 148 },
1216 .hback_porch = { 24, 88, 108 },
1217 .hsync_len = { 20, 48, 64 },
1218 .vactive = { 1080, 1080, 1080 },
1219 .vfront_porch = { 6, 10, 40 },
1220 .vback_porch = { 2, 5, 20 },
1221 .vsync_len = { 2, 5, 20 },
1222 };
1223
1224 static const struct panel_desc auo_g185han01 = {
1225 .timings = &auo_g185han01_timings,
1226 .num_timings = 1,
1227 .bpc = 8,
1228 .size = {
1229 .width = 409,
1230 .height = 230,
1231 },
1232 .delay = {
1233 .prepare = 50,
1234 .enable = 200,
1235 .disable = 110,
1236 .unprepare = 1000,
1237 },
1238 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1239 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1240 };
1241
1242 static const struct display_timing auo_g190ean01_timings = {
1243 .pixelclock = { 90000000, 108000000, 135000000 },
1244 .hactive = { 1280, 1280, 1280 },
1245 .hfront_porch = { 126, 184, 1266 },
1246 .hback_porch = { 84, 122, 844 },
1247 .hsync_len = { 70, 102, 704 },
1248 .vactive = { 1024, 1024, 1024 },
1249 .vfront_porch = { 4, 26, 76 },
1250 .vback_porch = { 2, 8, 25 },
1251 .vsync_len = { 2, 8, 25 },
1252 };
1253
1254 static const struct panel_desc auo_g190ean01 = {
1255 .timings = &auo_g190ean01_timings,
1256 .num_timings = 1,
1257 .bpc = 8,
1258 .size = {
1259 .width = 376,
1260 .height = 301,
1261 },
1262 .delay = {
1263 .prepare = 50,
1264 .enable = 200,
1265 .disable = 110,
1266 .unprepare = 1000,
1267 },
1268 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1269 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1270 };
1271
1272 static const struct display_timing auo_p320hvn03_timings = {
1273 .pixelclock = { 106000000, 148500000, 164000000 },
1274 .hactive = { 1920, 1920, 1920 },
1275 .hfront_porch = { 25, 50, 130 },
1276 .hback_porch = { 25, 50, 130 },
1277 .hsync_len = { 20, 40, 105 },
1278 .vactive = { 1080, 1080, 1080 },
1279 .vfront_porch = { 8, 17, 150 },
1280 .vback_porch = { 8, 17, 150 },
1281 .vsync_len = { 4, 11, 100 },
1282 };
1283
1284 static const struct panel_desc auo_p320hvn03 = {
1285 .timings = &auo_p320hvn03_timings,
1286 .num_timings = 1,
1287 .bpc = 8,
1288 .size = {
1289 .width = 698,
1290 .height = 393,
1291 },
1292 .delay = {
1293 .prepare = 1,
1294 .enable = 450,
1295 .unprepare = 500,
1296 },
1297 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1298 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1299 };
1300
1301 static const struct drm_display_mode auo_t215hvn01_mode = {
1302 .clock = 148800,
1303 .hdisplay = 1920,
1304 .hsync_start = 1920 + 88,
1305 .hsync_end = 1920 + 88 + 44,
1306 .htotal = 1920 + 88 + 44 + 148,
1307 .vdisplay = 1080,
1308 .vsync_start = 1080 + 4,
1309 .vsync_end = 1080 + 4 + 5,
1310 .vtotal = 1080 + 4 + 5 + 36,
1311 };
1312
1313 static const struct panel_desc auo_t215hvn01 = {
1314 .modes = &auo_t215hvn01_mode,
1315 .num_modes = 1,
1316 .bpc = 8,
1317 .size = {
1318 .width = 430,
1319 .height = 270,
1320 },
1321 .delay = {
1322 .disable = 5,
1323 .unprepare = 1000,
1324 },
1325 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1326 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1327 };
1328
1329 static const struct drm_display_mode avic_tm070ddh03_mode = {
1330 .clock = 51200,
1331 .hdisplay = 1024,
1332 .hsync_start = 1024 + 160,
1333 .hsync_end = 1024 + 160 + 4,
1334 .htotal = 1024 + 160 + 4 + 156,
1335 .vdisplay = 600,
1336 .vsync_start = 600 + 17,
1337 .vsync_end = 600 + 17 + 1,
1338 .vtotal = 600 + 17 + 1 + 17,
1339 };
1340
1341 static const struct panel_desc avic_tm070ddh03 = {
1342 .modes = &avic_tm070ddh03_mode,
1343 .num_modes = 1,
1344 .bpc = 8,
1345 .size = {
1346 .width = 154,
1347 .height = 90,
1348 },
1349 .delay = {
1350 .prepare = 20,
1351 .enable = 200,
1352 .disable = 200,
1353 },
1354 };
1355
1356 static const struct drm_display_mode bananapi_s070wv20_ct16_mode = {
1357 .clock = 30000,
1358 .hdisplay = 800,
1359 .hsync_start = 800 + 40,
1360 .hsync_end = 800 + 40 + 48,
1361 .htotal = 800 + 40 + 48 + 40,
1362 .vdisplay = 480,
1363 .vsync_start = 480 + 13,
1364 .vsync_end = 480 + 13 + 3,
1365 .vtotal = 480 + 13 + 3 + 29,
1366 };
1367
1368 static const struct panel_desc bananapi_s070wv20_ct16 = {
1369 .modes = &bananapi_s070wv20_ct16_mode,
1370 .num_modes = 1,
1371 .bpc = 6,
1372 .size = {
1373 .width = 154,
1374 .height = 86,
1375 },
1376 };
1377
1378 static const struct drm_display_mode boe_bp101wx1_100_mode = {
1379 .clock = 78945,
1380 .hdisplay = 1280,
1381 .hsync_start = 1280 + 0,
1382 .hsync_end = 1280 + 0 + 2,
1383 .htotal = 1280 + 62 + 0 + 2,
1384 .vdisplay = 800,
1385 .vsync_start = 800 + 8,
1386 .vsync_end = 800 + 8 + 2,
1387 .vtotal = 800 + 6 + 8 + 2,
1388 };
1389
1390 static const struct panel_desc boe_bp082wx1_100 = {
1391 .modes = &boe_bp101wx1_100_mode,
1392 .num_modes = 1,
1393 .bpc = 8,
1394 .size = {
1395 .width = 177,
1396 .height = 110,
1397 },
1398 .delay = {
1399 .enable = 50,
1400 .disable = 50,
1401 },
1402 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA,
1403 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
1404 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1405 };
1406
1407 static const struct panel_desc boe_bp101wx1_100 = {
1408 .modes = &boe_bp101wx1_100_mode,
1409 .num_modes = 1,
1410 .bpc = 8,
1411 .size = {
1412 .width = 217,
1413 .height = 136,
1414 },
1415 .delay = {
1416 .enable = 50,
1417 .disable = 50,
1418 },
1419 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA,
1420 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
1421 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1422 };
1423
1424 static const struct display_timing boe_ev121wxm_n10_1850_timing = {
1425 .pixelclock = { 69922000, 71000000, 72293000 },
1426 .hactive = { 1280, 1280, 1280 },
1427 .hfront_porch = { 48, 48, 48 },
1428 .hback_porch = { 80, 80, 80 },
1429 .hsync_len = { 32, 32, 32 },
1430 .vactive = { 800, 800, 800 },
1431 .vfront_porch = { 3, 3, 3 },
1432 .vback_porch = { 14, 14, 14 },
1433 .vsync_len = { 6, 6, 6 },
1434 };
1435
1436 static const struct panel_desc boe_ev121wxm_n10_1850 = {
1437 .timings = &boe_ev121wxm_n10_1850_timing,
1438 .num_timings = 1,
1439 .bpc = 8,
1440 .size = {
1441 .width = 261,
1442 .height = 163,
1443 },
1444 .delay = {
1445 .prepare = 9,
1446 .enable = 300,
1447 .unprepare = 300,
1448 .disable = 560,
1449 },
1450 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1451 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
1452 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1453 };
1454
1455 static const struct drm_display_mode boe_hv070wsa_mode = {
1456 .clock = 42105,
1457 .hdisplay = 1024,
1458 .hsync_start = 1024 + 30,
1459 .hsync_end = 1024 + 30 + 30,
1460 .htotal = 1024 + 30 + 30 + 30,
1461 .vdisplay = 600,
1462 .vsync_start = 600 + 10,
1463 .vsync_end = 600 + 10 + 10,
1464 .vtotal = 600 + 10 + 10 + 10,
1465 };
1466
1467 static const struct panel_desc boe_hv070wsa = {
1468 .modes = &boe_hv070wsa_mode,
1469 .num_modes = 1,
1470 .bpc = 8,
1471 .size = {
1472 .width = 154,
1473 .height = 90,
1474 },
1475 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1476 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
1477 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1478 };
1479
1480 static const struct display_timing cct_cmt430b19n00_timing = {
1481 .pixelclock = { 8000000, 9000000, 12000000 },
1482 .hactive = { 480, 480, 480 },
1483 .hfront_porch = { 2, 8, 75 },
1484 .hback_porch = { 3, 43, 43 },
1485 .hsync_len = { 2, 4, 75 },
1486 .vactive = { 272, 272, 272 },
1487 .vfront_porch = { 2, 8, 37 },
1488 .vback_porch = { 2, 12, 12 },
1489 .vsync_len = { 2, 4, 37 },
1490 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW
1491 };
1492
1493 static const struct panel_desc cct_cmt430b19n00 = {
1494 .timings = &cct_cmt430b19n00_timing,
1495 .num_timings = 1,
1496 .bpc = 8,
1497 .size = {
1498 .width = 95,
1499 .height = 53,
1500 },
1501 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1502 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE,
1503 .connector_type = DRM_MODE_CONNECTOR_DPI,
1504 };
1505
1506 static const struct drm_display_mode cdtech_s043wq26h_ct7_mode = {
1507 .clock = 9000,
1508 .hdisplay = 480,
1509 .hsync_start = 480 + 5,
1510 .hsync_end = 480 + 5 + 5,
1511 .htotal = 480 + 5 + 5 + 40,
1512 .vdisplay = 272,
1513 .vsync_start = 272 + 8,
1514 .vsync_end = 272 + 8 + 8,
1515 .vtotal = 272 + 8 + 8 + 8,
1516 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1517 };
1518
1519 static const struct panel_desc cdtech_s043wq26h_ct7 = {
1520 .modes = &cdtech_s043wq26h_ct7_mode,
1521 .num_modes = 1,
1522 .bpc = 8,
1523 .size = {
1524 .width = 95,
1525 .height = 54,
1526 },
1527 .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
1528 };
1529
1530 /* S070PWS19HP-FC21 2017/04/22 */
1531 static const struct drm_display_mode cdtech_s070pws19hp_fc21_mode = {
1532 .clock = 51200,
1533 .hdisplay = 1024,
1534 .hsync_start = 1024 + 160,
1535 .hsync_end = 1024 + 160 + 20,
1536 .htotal = 1024 + 160 + 20 + 140,
1537 .vdisplay = 600,
1538 .vsync_start = 600 + 12,
1539 .vsync_end = 600 + 12 + 3,
1540 .vtotal = 600 + 12 + 3 + 20,
1541 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1542 };
1543
1544 static const struct panel_desc cdtech_s070pws19hp_fc21 = {
1545 .modes = &cdtech_s070pws19hp_fc21_mode,
1546 .num_modes = 1,
1547 .bpc = 6,
1548 .size = {
1549 .width = 154,
1550 .height = 86,
1551 },
1552 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1553 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
1554 .connector_type = DRM_MODE_CONNECTOR_DPI,
1555 };
1556
1557 /* S070SWV29HG-DC44 2017/09/21 */
1558 static const struct drm_display_mode cdtech_s070swv29hg_dc44_mode = {
1559 .clock = 33300,
1560 .hdisplay = 800,
1561 .hsync_start = 800 + 210,
1562 .hsync_end = 800 + 210 + 2,
1563 .htotal = 800 + 210 + 2 + 44,
1564 .vdisplay = 480,
1565 .vsync_start = 480 + 22,
1566 .vsync_end = 480 + 22 + 2,
1567 .vtotal = 480 + 22 + 2 + 21,
1568 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1569 };
1570
1571 static const struct panel_desc cdtech_s070swv29hg_dc44 = {
1572 .modes = &cdtech_s070swv29hg_dc44_mode,
1573 .num_modes = 1,
1574 .bpc = 6,
1575 .size = {
1576 .width = 154,
1577 .height = 86,
1578 },
1579 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1580 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
1581 .connector_type = DRM_MODE_CONNECTOR_DPI,
1582 };
1583
1584 static const struct drm_display_mode cdtech_s070wv95_ct16_mode = {
1585 .clock = 35000,
1586 .hdisplay = 800,
1587 .hsync_start = 800 + 40,
1588 .hsync_end = 800 + 40 + 40,
1589 .htotal = 800 + 40 + 40 + 48,
1590 .vdisplay = 480,
1591 .vsync_start = 480 + 29,
1592 .vsync_end = 480 + 29 + 13,
1593 .vtotal = 480 + 29 + 13 + 3,
1594 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1595 };
1596
1597 static const struct panel_desc cdtech_s070wv95_ct16 = {
1598 .modes = &cdtech_s070wv95_ct16_mode,
1599 .num_modes = 1,
1600 .bpc = 8,
1601 .size = {
1602 .width = 154,
1603 .height = 85,
1604 },
1605 };
1606
1607 static const struct display_timing chefree_ch101olhlwh_002_timing = {
1608 .pixelclock = { 68900000, 71100000, 73400000 },
1609 .hactive = { 1280, 1280, 1280 },
1610 .hfront_porch = { 65, 80, 95 },
1611 .hback_porch = { 64, 79, 94 },
1612 .hsync_len = { 1, 1, 1 },
1613 .vactive = { 800, 800, 800 },
1614 .vfront_porch = { 7, 11, 14 },
1615 .vback_porch = { 7, 11, 14 },
1616 .vsync_len = { 1, 1, 1 },
1617 .flags = DISPLAY_FLAGS_DE_HIGH,
1618 };
1619
1620 static const struct panel_desc chefree_ch101olhlwh_002 = {
1621 .timings = &chefree_ch101olhlwh_002_timing,
1622 .num_timings = 1,
1623 .bpc = 8,
1624 .size = {
1625 .width = 217,
1626 .height = 135,
1627 },
1628 .delay = {
1629 .enable = 200,
1630 .disable = 200,
1631 },
1632 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
1633 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1634 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1635 };
1636
1637 static const struct drm_display_mode chunghwa_claa070wp03xg_mode = {
1638 .clock = 66770,
1639 .hdisplay = 800,
1640 .hsync_start = 800 + 49,
1641 .hsync_end = 800 + 49 + 33,
1642 .htotal = 800 + 49 + 33 + 17,
1643 .vdisplay = 1280,
1644 .vsync_start = 1280 + 1,
1645 .vsync_end = 1280 + 1 + 7,
1646 .vtotal = 1280 + 1 + 7 + 15,
1647 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1648 };
1649
1650 static const struct panel_desc chunghwa_claa070wp03xg = {
1651 .modes = &chunghwa_claa070wp03xg_mode,
1652 .num_modes = 1,
1653 .bpc = 6,
1654 .size = {
1655 .width = 94,
1656 .height = 150,
1657 },
1658 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
1659 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
1660 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1661 };
1662
1663 static const struct drm_display_mode chunghwa_claa101wa01a_mode = {
1664 .clock = 72070,
1665 .hdisplay = 1366,
1666 .hsync_start = 1366 + 58,
1667 .hsync_end = 1366 + 58 + 58,
1668 .htotal = 1366 + 58 + 58 + 58,
1669 .vdisplay = 768,
1670 .vsync_start = 768 + 4,
1671 .vsync_end = 768 + 4 + 4,
1672 .vtotal = 768 + 4 + 4 + 4,
1673 };
1674
1675 static const struct panel_desc chunghwa_claa101wa01a = {
1676 .modes = &chunghwa_claa101wa01a_mode,
1677 .num_modes = 1,
1678 .bpc = 6,
1679 .size = {
1680 .width = 220,
1681 .height = 120,
1682 },
1683 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
1684 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
1685 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1686 };
1687
1688 static const struct drm_display_mode chunghwa_claa101wb01_mode = {
1689 .clock = 69300,
1690 .hdisplay = 1366,
1691 .hsync_start = 1366 + 48,
1692 .hsync_end = 1366 + 48 + 32,
1693 .htotal = 1366 + 48 + 32 + 20,
1694 .vdisplay = 768,
1695 .vsync_start = 768 + 16,
1696 .vsync_end = 768 + 16 + 8,
1697 .vtotal = 768 + 16 + 8 + 16,
1698 };
1699
1700 static const struct panel_desc chunghwa_claa101wb01 = {
1701 .modes = &chunghwa_claa101wb01_mode,
1702 .num_modes = 1,
1703 .bpc = 6,
1704 .size = {
1705 .width = 223,
1706 .height = 125,
1707 },
1708 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
1709 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
1710 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1711 };
1712
1713 static const struct display_timing dataimage_fg040346dsswbg04_timing = {
1714 .pixelclock = { 5000000, 9000000, 12000000 },
1715 .hactive = { 480, 480, 480 },
1716 .hfront_porch = { 12, 12, 12 },
1717 .hback_porch = { 12, 12, 12 },
1718 .hsync_len = { 21, 21, 21 },
1719 .vactive = { 272, 272, 272 },
1720 .vfront_porch = { 4, 4, 4 },
1721 .vback_porch = { 4, 4, 4 },
1722 .vsync_len = { 8, 8, 8 },
1723 };
1724
1725 static const struct panel_desc dataimage_fg040346dsswbg04 = {
1726 .timings = &dataimage_fg040346dsswbg04_timing,
1727 .num_timings = 1,
1728 .bpc = 8,
1729 .size = {
1730 .width = 95,
1731 .height = 54,
1732 },
1733 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1734 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
1735 .connector_type = DRM_MODE_CONNECTOR_DPI,
1736 };
1737
1738 static const struct display_timing dataimage_fg1001l0dsswmg01_timing = {
1739 .pixelclock = { 68900000, 71110000, 73400000 },
1740 .hactive = { 1280, 1280, 1280 },
1741 .vactive = { 800, 800, 800 },
1742 .hback_porch = { 100, 100, 100 },
1743 .hfront_porch = { 100, 100, 100 },
1744 .vback_porch = { 5, 5, 5 },
1745 .vfront_porch = { 5, 5, 5 },
1746 .hsync_len = { 24, 24, 24 },
1747 .vsync_len = { 3, 3, 3 },
1748 .flags = DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE |
1749 DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW,
1750 };
1751
1752 static const struct panel_desc dataimage_fg1001l0dsswmg01 = {
1753 .timings = &dataimage_fg1001l0dsswmg01_timing,
1754 .num_timings = 1,
1755 .bpc = 8,
1756 .size = {
1757 .width = 217,
1758 .height = 136,
1759 },
1760 };
1761
1762 static const struct drm_display_mode dataimage_scf0700c48ggu18_mode = {
1763 .clock = 33260,
1764 .hdisplay = 800,
1765 .hsync_start = 800 + 40,
1766 .hsync_end = 800 + 40 + 128,
1767 .htotal = 800 + 40 + 128 + 88,
1768 .vdisplay = 480,
1769 .vsync_start = 480 + 10,
1770 .vsync_end = 480 + 10 + 2,
1771 .vtotal = 480 + 10 + 2 + 33,
1772 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1773 };
1774
1775 static const struct panel_desc dataimage_scf0700c48ggu18 = {
1776 .modes = &dataimage_scf0700c48ggu18_mode,
1777 .num_modes = 1,
1778 .bpc = 8,
1779 .size = {
1780 .width = 152,
1781 .height = 91,
1782 },
1783 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1784 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
1785 };
1786
1787 static const struct display_timing dlc_dlc0700yzg_1_timing = {
1788 .pixelclock = { 45000000, 51200000, 57000000 },
1789 .hactive = { 1024, 1024, 1024 },
1790 .hfront_porch = { 100, 106, 113 },
1791 .hback_porch = { 100, 106, 113 },
1792 .hsync_len = { 100, 108, 114 },
1793 .vactive = { 600, 600, 600 },
1794 .vfront_porch = { 8, 11, 15 },
1795 .vback_porch = { 8, 11, 15 },
1796 .vsync_len = { 9, 13, 15 },
1797 .flags = DISPLAY_FLAGS_DE_HIGH,
1798 };
1799
1800 static const struct panel_desc dlc_dlc0700yzg_1 = {
1801 .timings = &dlc_dlc0700yzg_1_timing,
1802 .num_timings = 1,
1803 .bpc = 6,
1804 .size = {
1805 .width = 154,
1806 .height = 86,
1807 },
1808 .delay = {
1809 .prepare = 30,
1810 .enable = 200,
1811 .disable = 200,
1812 },
1813 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
1814 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1815 };
1816
1817 static const struct display_timing dlc_dlc1010gig_timing = {
1818 .pixelclock = { 68900000, 71100000, 73400000 },
1819 .hactive = { 1280, 1280, 1280 },
1820 .hfront_porch = { 43, 53, 63 },
1821 .hback_porch = { 43, 53, 63 },
1822 .hsync_len = { 44, 54, 64 },
1823 .vactive = { 800, 800, 800 },
1824 .vfront_porch = { 5, 8, 11 },
1825 .vback_porch = { 5, 8, 11 },
1826 .vsync_len = { 5, 7, 11 },
1827 .flags = DISPLAY_FLAGS_DE_HIGH,
1828 };
1829
1830 static const struct panel_desc dlc_dlc1010gig = {
1831 .timings = &dlc_dlc1010gig_timing,
1832 .num_timings = 1,
1833 .bpc = 8,
1834 .size = {
1835 .width = 216,
1836 .height = 135,
1837 },
1838 .delay = {
1839 .prepare = 60,
1840 .enable = 150,
1841 .disable = 100,
1842 .unprepare = 60,
1843 },
1844 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1845 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1846 };
1847
1848 static const struct drm_display_mode edt_et035012dm6_mode = {
1849 .clock = 6500,
1850 .hdisplay = 320,
1851 .hsync_start = 320 + 20,
1852 .hsync_end = 320 + 20 + 30,
1853 .htotal = 320 + 20 + 68,
1854 .vdisplay = 240,
1855 .vsync_start = 240 + 4,
1856 .vsync_end = 240 + 4 + 4,
1857 .vtotal = 240 + 4 + 4 + 14,
1858 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1859 };
1860
1861 static const struct panel_desc edt_et035012dm6 = {
1862 .modes = &edt_et035012dm6_mode,
1863 .num_modes = 1,
1864 .bpc = 8,
1865 .size = {
1866 .width = 70,
1867 .height = 52,
1868 },
1869 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1870 .bus_flags = DRM_BUS_FLAG_DE_LOW | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE,
1871 };
1872
1873 static const struct drm_display_mode edt_etm0350g0dh6_mode = {
1874 .clock = 6520,
1875 .hdisplay = 320,
1876 .hsync_start = 320 + 20,
1877 .hsync_end = 320 + 20 + 68,
1878 .htotal = 320 + 20 + 68,
1879 .vdisplay = 240,
1880 .vsync_start = 240 + 4,
1881 .vsync_end = 240 + 4 + 18,
1882 .vtotal = 240 + 4 + 18,
1883 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1884 };
1885
1886 static const struct panel_desc edt_etm0350g0dh6 = {
1887 .modes = &edt_etm0350g0dh6_mode,
1888 .num_modes = 1,
1889 .bpc = 6,
1890 .size = {
1891 .width = 70,
1892 .height = 53,
1893 },
1894 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1895 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE,
1896 .connector_type = DRM_MODE_CONNECTOR_DPI,
1897 };
1898
1899 static const struct drm_display_mode edt_etm043080dh6gp_mode = {
1900 .clock = 10870,
1901 .hdisplay = 480,
1902 .hsync_start = 480 + 8,
1903 .hsync_end = 480 + 8 + 4,
1904 .htotal = 480 + 8 + 4 + 41,
1905
1906 /*
1907 * IWG22M: Y resolution changed for "dc_linuxfb" module crashing while
1908 * fb_align
1909 */
1910
1911 .vdisplay = 288,
1912 .vsync_start = 288 + 2,
1913 .vsync_end = 288 + 2 + 4,
1914 .vtotal = 288 + 2 + 4 + 10,
1915 };
1916
1917 static const struct panel_desc edt_etm043080dh6gp = {
1918 .modes = &edt_etm043080dh6gp_mode,
1919 .num_modes = 1,
1920 .bpc = 8,
1921 .size = {
1922 .width = 100,
1923 .height = 65,
1924 },
1925 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1926 .connector_type = DRM_MODE_CONNECTOR_DPI,
1927 };
1928
1929 static const struct drm_display_mode edt_etm0430g0dh6_mode = {
1930 .clock = 9000,
1931 .hdisplay = 480,
1932 .hsync_start = 480 + 2,
1933 .hsync_end = 480 + 2 + 41,
1934 .htotal = 480 + 2 + 41 + 2,
1935 .vdisplay = 272,
1936 .vsync_start = 272 + 2,
1937 .vsync_end = 272 + 2 + 10,
1938 .vtotal = 272 + 2 + 10 + 2,
1939 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1940 };
1941
1942 static const struct panel_desc edt_etm0430g0dh6 = {
1943 .modes = &edt_etm0430g0dh6_mode,
1944 .num_modes = 1,
1945 .bpc = 6,
1946 .size = {
1947 .width = 95,
1948 .height = 54,
1949 },
1950 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1951 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE,
1952 .connector_type = DRM_MODE_CONNECTOR_DPI,
1953 };
1954
1955 static const struct drm_display_mode edt_et057090dhu_mode = {
1956 .clock = 25175,
1957 .hdisplay = 640,
1958 .hsync_start = 640 + 16,
1959 .hsync_end = 640 + 16 + 30,
1960 .htotal = 640 + 16 + 30 + 114,
1961 .vdisplay = 480,
1962 .vsync_start = 480 + 10,
1963 .vsync_end = 480 + 10 + 3,
1964 .vtotal = 480 + 10 + 3 + 32,
1965 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1966 };
1967
1968 static const struct panel_desc edt_et057090dhu = {
1969 .modes = &edt_et057090dhu_mode,
1970 .num_modes = 1,
1971 .bpc = 6,
1972 .size = {
1973 .width = 115,
1974 .height = 86,
1975 },
1976 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1977 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE,
1978 .connector_type = DRM_MODE_CONNECTOR_DPI,
1979 };
1980
1981 static const struct drm_display_mode edt_etm0700g0dh6_mode = {
1982 .clock = 33260,
1983 .hdisplay = 800,
1984 .hsync_start = 800 + 40,
1985 .hsync_end = 800 + 40 + 128,
1986 .htotal = 800 + 40 + 128 + 88,
1987 .vdisplay = 480,
1988 .vsync_start = 480 + 10,
1989 .vsync_end = 480 + 10 + 2,
1990 .vtotal = 480 + 10 + 2 + 33,
1991 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1992 };
1993
1994 static const struct panel_desc edt_etm0700g0dh6 = {
1995 .modes = &edt_etm0700g0dh6_mode,
1996 .num_modes = 1,
1997 .bpc = 6,
1998 .size = {
1999 .width = 152,
2000 .height = 91,
2001 },
2002 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
2003 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE,
2004 .connector_type = DRM_MODE_CONNECTOR_DPI,
2005 };
2006
2007 static const struct panel_desc edt_etm0700g0bdh6 = {
2008 .modes = &edt_etm0700g0dh6_mode,
2009 .num_modes = 1,
2010 .bpc = 6,
2011 .size = {
2012 .width = 152,
2013 .height = 91,
2014 },
2015 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
2016 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
2017 .connector_type = DRM_MODE_CONNECTOR_DPI,
2018 };
2019
2020 static const struct display_timing edt_etml0700y5dha_timing = {
2021 .pixelclock = { 40800000, 51200000, 67200000 },
2022 .hactive = { 1024, 1024, 1024 },
2023 .hfront_porch = { 30, 106, 125 },
2024 .hback_porch = { 30, 106, 125 },
2025 .hsync_len = { 30, 108, 126 },
2026 .vactive = { 600, 600, 600 },
2027 .vfront_porch = { 3, 12, 67},
2028 .vback_porch = { 3, 12, 67 },
2029 .vsync_len = { 4, 11, 66 },
2030 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
2031 DISPLAY_FLAGS_DE_HIGH,
2032 };
2033
2034 static const struct panel_desc edt_etml0700y5dha = {
2035 .timings = &edt_etml0700y5dha_timing,
2036 .num_timings = 1,
2037 .bpc = 8,
2038 .size = {
2039 .width = 155,
2040 .height = 86,
2041 },
2042 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2043 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2044 };
2045
2046 static const struct display_timing edt_etml1010g3dra_timing = {
2047 .pixelclock = { 66300000, 72400000, 78900000 },
2048 .hactive = { 1280, 1280, 1280 },
2049 .hfront_porch = { 12, 72, 132 },
2050 .hback_porch = { 86, 86, 86 },
2051 .hsync_len = { 2, 2, 2 },
2052 .vactive = { 800, 800, 800 },
2053 .vfront_porch = { 1, 15, 49 },
2054 .vback_porch = { 21, 21, 21 },
2055 .vsync_len = { 2, 2, 2 },
2056 .flags = DISPLAY_FLAGS_VSYNC_LOW | DISPLAY_FLAGS_HSYNC_LOW |
2057 DISPLAY_FLAGS_DE_HIGH,
2058 };
2059
2060 static const struct panel_desc edt_etml1010g3dra = {
2061 .timings = &edt_etml1010g3dra_timing,
2062 .num_timings = 1,
2063 .bpc = 8,
2064 .size = {
2065 .width = 216,
2066 .height = 135,
2067 },
2068 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2069 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
2070 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2071 };
2072
2073 static const struct drm_display_mode edt_etmv570g2dhu_mode = {
2074 .clock = 25175,
2075 .hdisplay = 640,
2076 .hsync_start = 640,
2077 .hsync_end = 640 + 16,
2078 .htotal = 640 + 16 + 30 + 114,
2079 .vdisplay = 480,
2080 .vsync_start = 480 + 10,
2081 .vsync_end = 480 + 10 + 3,
2082 .vtotal = 480 + 10 + 3 + 35,
2083 .flags = DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_PHSYNC,
2084 };
2085
2086 static const struct panel_desc edt_etmv570g2dhu = {
2087 .modes = &edt_etmv570g2dhu_mode,
2088 .num_modes = 1,
2089 .bpc = 6,
2090 .size = {
2091 .width = 115,
2092 .height = 86,
2093 },
2094 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2095 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE,
2096 .connector_type = DRM_MODE_CONNECTOR_DPI,
2097 };
2098
2099 static const struct display_timing eink_vb3300_kca_timing = {
2100 .pixelclock = { 40000000, 40000000, 40000000 },
2101 .hactive = { 334, 334, 334 },
2102 .hfront_porch = { 1, 1, 1 },
2103 .hback_porch = { 1, 1, 1 },
2104 .hsync_len = { 1, 1, 1 },
2105 .vactive = { 1405, 1405, 1405 },
2106 .vfront_porch = { 1, 1, 1 },
2107 .vback_porch = { 1, 1, 1 },
2108 .vsync_len = { 1, 1, 1 },
2109 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
2110 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE,
2111 };
2112
2113 static const struct panel_desc eink_vb3300_kca = {
2114 .timings = &eink_vb3300_kca_timing,
2115 .num_timings = 1,
2116 .bpc = 6,
2117 .size = {
2118 .width = 157,
2119 .height = 209,
2120 },
2121 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2122 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
2123 .connector_type = DRM_MODE_CONNECTOR_DPI,
2124 };
2125
2126 static const struct display_timing evervision_vgg644804_timing = {
2127 .pixelclock = { 25175000, 25175000, 25175000 },
2128 .hactive = { 640, 640, 640 },
2129 .hfront_porch = { 16, 16, 16 },
2130 .hback_porch = { 82, 114, 170 },
2131 .hsync_len = { 5, 30, 30 },
2132 .vactive = { 480, 480, 480 },
2133 .vfront_porch = { 10, 10, 10 },
2134 .vback_porch = { 30, 32, 34 },
2135 .vsync_len = { 1, 3, 5 },
2136 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
2137 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE |
2138 DISPLAY_FLAGS_SYNC_POSEDGE,
2139 };
2140
2141 static const struct panel_desc evervision_vgg644804 = {
2142 .timings = &evervision_vgg644804_timing,
2143 .num_timings = 1,
2144 .bpc = 6,
2145 .size = {
2146 .width = 115,
2147 .height = 86,
2148 },
2149 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
2150 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
2151 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2152 };
2153
2154 static const struct display_timing evervision_vgg804821_timing = {
2155 .pixelclock = { 27600000, 33300000, 50000000 },
2156 .hactive = { 800, 800, 800 },
2157 .hfront_porch = { 40, 66, 70 },
2158 .hback_porch = { 40, 67, 70 },
2159 .hsync_len = { 40, 67, 70 },
2160 .vactive = { 480, 480, 480 },
2161 .vfront_porch = { 6, 10, 10 },
2162 .vback_porch = { 7, 11, 11 },
2163 .vsync_len = { 7, 11, 11 },
2164 .flags = DISPLAY_FLAGS_HSYNC_HIGH | DISPLAY_FLAGS_VSYNC_HIGH |
2165 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_NEGEDGE |
2166 DISPLAY_FLAGS_SYNC_NEGEDGE,
2167 };
2168
2169 static const struct panel_desc evervision_vgg804821 = {
2170 .timings = &evervision_vgg804821_timing,
2171 .num_timings = 1,
2172 .bpc = 8,
2173 .size = {
2174 .width = 108,
2175 .height = 64,
2176 },
2177 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2178 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE,
2179 };
2180
2181 static const struct drm_display_mode foxlink_fl500wvr00_a0t_mode = {
2182 .clock = 32260,
2183 .hdisplay = 800,
2184 .hsync_start = 800 + 168,
2185 .hsync_end = 800 + 168 + 64,
2186 .htotal = 800 + 168 + 64 + 88,
2187 .vdisplay = 480,
2188 .vsync_start = 480 + 37,
2189 .vsync_end = 480 + 37 + 2,
2190 .vtotal = 480 + 37 + 2 + 8,
2191 };
2192
2193 static const struct panel_desc foxlink_fl500wvr00_a0t = {
2194 .modes = &foxlink_fl500wvr00_a0t_mode,
2195 .num_modes = 1,
2196 .bpc = 8,
2197 .size = {
2198 .width = 108,
2199 .height = 65,
2200 },
2201 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2202 };
2203
2204 static const struct drm_display_mode frida_frd350h54004_modes[] = {
2205 { /* 60 Hz */
2206 .clock = 6000,
2207 .hdisplay = 320,
2208 .hsync_start = 320 + 44,
2209 .hsync_end = 320 + 44 + 16,
2210 .htotal = 320 + 44 + 16 + 20,
2211 .vdisplay = 240,
2212 .vsync_start = 240 + 2,
2213 .vsync_end = 240 + 2 + 6,
2214 .vtotal = 240 + 2 + 6 + 2,
2215 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
2216 },
2217 { /* 50 Hz */
2218 .clock = 5400,
2219 .hdisplay = 320,
2220 .hsync_start = 320 + 56,
2221 .hsync_end = 320 + 56 + 16,
2222 .htotal = 320 + 56 + 16 + 40,
2223 .vdisplay = 240,
2224 .vsync_start = 240 + 2,
2225 .vsync_end = 240 + 2 + 6,
2226 .vtotal = 240 + 2 + 6 + 2,
2227 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
2228 },
2229 };
2230
2231 static const struct panel_desc frida_frd350h54004 = {
2232 .modes = frida_frd350h54004_modes,
2233 .num_modes = ARRAY_SIZE(frida_frd350h54004_modes),
2234 .bpc = 8,
2235 .size = {
2236 .width = 77,
2237 .height = 64,
2238 },
2239 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2240 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
2241 .connector_type = DRM_MODE_CONNECTOR_DPI,
2242 };
2243
2244 static const struct drm_display_mode friendlyarm_hd702e_mode = {
2245 .clock = 67185,
2246 .hdisplay = 800,
2247 .hsync_start = 800 + 20,
2248 .hsync_end = 800 + 20 + 24,
2249 .htotal = 800 + 20 + 24 + 20,
2250 .vdisplay = 1280,
2251 .vsync_start = 1280 + 4,
2252 .vsync_end = 1280 + 4 + 8,
2253 .vtotal = 1280 + 4 + 8 + 4,
2254 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
2255 };
2256
2257 static const struct panel_desc friendlyarm_hd702e = {
2258 .modes = &friendlyarm_hd702e_mode,
2259 .num_modes = 1,
2260 .size = {
2261 .width = 94,
2262 .height = 151,
2263 },
2264 };
2265
2266 static const struct drm_display_mode giantplus_gpg482739qs5_mode = {
2267 .clock = 9000,
2268 .hdisplay = 480,
2269 .hsync_start = 480 + 5,
2270 .hsync_end = 480 + 5 + 1,
2271 .htotal = 480 + 5 + 1 + 40,
2272 .vdisplay = 272,
2273 .vsync_start = 272 + 8,
2274 .vsync_end = 272 + 8 + 1,
2275 .vtotal = 272 + 8 + 1 + 8,
2276 };
2277
2278 static const struct panel_desc giantplus_gpg482739qs5 = {
2279 .modes = &giantplus_gpg482739qs5_mode,
2280 .num_modes = 1,
2281 .bpc = 8,
2282 .size = {
2283 .width = 95,
2284 .height = 54,
2285 },
2286 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2287 };
2288
2289 static const struct display_timing giantplus_gpm940b0_timing = {
2290 .pixelclock = { 13500000, 27000000, 27500000 },
2291 .hactive = { 320, 320, 320 },
2292 .hfront_porch = { 14, 686, 718 },
2293 .hback_porch = { 50, 70, 255 },
2294 .hsync_len = { 1, 1, 1 },
2295 .vactive = { 240, 240, 240 },
2296 .vfront_porch = { 1, 1, 179 },
2297 .vback_porch = { 1, 21, 31 },
2298 .vsync_len = { 1, 1, 6 },
2299 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW,
2300 };
2301
2302 static const struct panel_desc giantplus_gpm940b0 = {
2303 .timings = &giantplus_gpm940b0_timing,
2304 .num_timings = 1,
2305 .bpc = 8,
2306 .size = {
2307 .width = 60,
2308 .height = 45,
2309 },
2310 .bus_format = MEDIA_BUS_FMT_RGB888_3X8,
2311 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE,
2312 };
2313
2314 static const struct display_timing hannstar_hsd070pww1_timing = {
2315 .pixelclock = { 64300000, 71100000, 82000000 },
2316 .hactive = { 1280, 1280, 1280 },
2317 .hfront_porch = { 1, 1, 10 },
2318 .hback_porch = { 1, 1, 10 },
2319 /*
2320 * According to the data sheet, the minimum horizontal blanking interval
2321 * is 54 clocks (1 + 52 + 1), but tests with a Nitrogen6X have shown the
2322 * minimum working horizontal blanking interval to be 60 clocks.
2323 */
2324 .hsync_len = { 58, 158, 661 },
2325 .vactive = { 800, 800, 800 },
2326 .vfront_porch = { 1, 1, 10 },
2327 .vback_porch = { 1, 1, 10 },
2328 .vsync_len = { 1, 21, 203 },
2329 .flags = DISPLAY_FLAGS_DE_HIGH,
2330 };
2331
2332 static const struct panel_desc hannstar_hsd070pww1 = {
2333 .timings = &hannstar_hsd070pww1_timing,
2334 .num_timings = 1,
2335 .bpc = 6,
2336 .size = {
2337 .width = 151,
2338 .height = 94,
2339 },
2340 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
2341 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2342 };
2343
2344 static const struct display_timing hannstar_hsd100pxn1_timing = {
2345 .pixelclock = { 55000000, 65000000, 75000000 },
2346 .hactive = { 1024, 1024, 1024 },
2347 .hfront_porch = { 40, 40, 40 },
2348 .hback_porch = { 220, 220, 220 },
2349 .hsync_len = { 20, 60, 100 },
2350 .vactive = { 768, 768, 768 },
2351 .vfront_porch = { 7, 7, 7 },
2352 .vback_porch = { 21, 21, 21 },
2353 .vsync_len = { 10, 10, 10 },
2354 .flags = DISPLAY_FLAGS_DE_HIGH,
2355 };
2356
2357 static const struct panel_desc hannstar_hsd100pxn1 = {
2358 .timings = &hannstar_hsd100pxn1_timing,
2359 .num_timings = 1,
2360 .bpc = 6,
2361 .size = {
2362 .width = 203,
2363 .height = 152,
2364 },
2365 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
2366 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2367 };
2368
2369 static const struct display_timing hannstar_hsd101pww2_timing = {
2370 .pixelclock = { 64300000, 71100000, 82000000 },
2371 .hactive = { 1280, 1280, 1280 },
2372 .hfront_porch = { 1, 1, 10 },
2373 .hback_porch = { 1, 1, 10 },
2374 .hsync_len = { 58, 158, 661 },
2375 .vactive = { 800, 800, 800 },
2376 .vfront_porch = { 1, 1, 10 },
2377 .vback_porch = { 1, 1, 10 },
2378 .vsync_len = { 1, 21, 203 },
2379 .flags = DISPLAY_FLAGS_DE_HIGH,
2380 };
2381
2382 static const struct panel_desc hannstar_hsd101pww2 = {
2383 .timings = &hannstar_hsd101pww2_timing,
2384 .num_timings = 1,
2385 .bpc = 8,
2386 .size = {
2387 .width = 217,
2388 .height = 136,
2389 },
2390 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2391 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2392 };
2393
2394 static const struct drm_display_mode hitachi_tx23d38vm0caa_mode = {
2395 .clock = 33333,
2396 .hdisplay = 800,
2397 .hsync_start = 800 + 85,
2398 .hsync_end = 800 + 85 + 86,
2399 .htotal = 800 + 85 + 86 + 85,
2400 .vdisplay = 480,
2401 .vsync_start = 480 + 16,
2402 .vsync_end = 480 + 16 + 13,
2403 .vtotal = 480 + 16 + 13 + 16,
2404 };
2405
2406 static const struct panel_desc hitachi_tx23d38vm0caa = {
2407 .modes = &hitachi_tx23d38vm0caa_mode,
2408 .num_modes = 1,
2409 .bpc = 6,
2410 .size = {
2411 .width = 195,
2412 .height = 117,
2413 },
2414 .delay = {
2415 .enable = 160,
2416 .disable = 160,
2417 },
2418 };
2419
2420 static const struct drm_display_mode innolux_at043tn24_mode = {
2421 .clock = 9000,
2422 .hdisplay = 480,
2423 .hsync_start = 480 + 2,
2424 .hsync_end = 480 + 2 + 41,
2425 .htotal = 480 + 2 + 41 + 2,
2426 .vdisplay = 272,
2427 .vsync_start = 272 + 2,
2428 .vsync_end = 272 + 2 + 10,
2429 .vtotal = 272 + 2 + 10 + 2,
2430 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
2431 };
2432
2433 static const struct panel_desc innolux_at043tn24 = {
2434 .modes = &innolux_at043tn24_mode,
2435 .num_modes = 1,
2436 .bpc = 8,
2437 .size = {
2438 .width = 95,
2439 .height = 54,
2440 },
2441 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2442 .connector_type = DRM_MODE_CONNECTOR_DPI,
2443 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
2444 };
2445
2446 static const struct drm_display_mode innolux_at070tn92_mode = {
2447 .clock = 33333,
2448 .hdisplay = 800,
2449 .hsync_start = 800 + 210,
2450 .hsync_end = 800 + 210 + 20,
2451 .htotal = 800 + 210 + 20 + 46,
2452 .vdisplay = 480,
2453 .vsync_start = 480 + 22,
2454 .vsync_end = 480 + 22 + 10,
2455 .vtotal = 480 + 22 + 23 + 10,
2456 };
2457
2458 static const struct panel_desc innolux_at070tn92 = {
2459 .modes = &innolux_at070tn92_mode,
2460 .num_modes = 1,
2461 .size = {
2462 .width = 154,
2463 .height = 86,
2464 },
2465 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2466 };
2467
2468 static const struct display_timing innolux_g070ace_l01_timing = {
2469 .pixelclock = { 25200000, 35000000, 35700000 },
2470 .hactive = { 800, 800, 800 },
2471 .hfront_porch = { 30, 32, 87 },
2472 .hback_porch = { 30, 32, 87 },
2473 .hsync_len = { 1, 1, 1 },
2474 .vactive = { 480, 480, 480 },
2475 .vfront_porch = { 3, 3, 3 },
2476 .vback_porch = { 13, 13, 13 },
2477 .vsync_len = { 1, 1, 4 },
2478 .flags = DISPLAY_FLAGS_DE_HIGH,
2479 };
2480
2481 static const struct panel_desc innolux_g070ace_l01 = {
2482 .timings = &innolux_g070ace_l01_timing,
2483 .num_timings = 1,
2484 .bpc = 8,
2485 .size = {
2486 .width = 152,
2487 .height = 91,
2488 },
2489 .delay = {
2490 .prepare = 10,
2491 .enable = 50,
2492 .disable = 50,
2493 .unprepare = 500,
2494 },
2495 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2496 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
2497 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2498 };
2499
2500 static const struct display_timing innolux_g070y2_l01_timing = {
2501 .pixelclock = { 28000000, 29500000, 32000000 },
2502 .hactive = { 800, 800, 800 },
2503 .hfront_porch = { 61, 91, 141 },
2504 .hback_porch = { 60, 90, 140 },
2505 .hsync_len = { 12, 12, 12 },
2506 .vactive = { 480, 480, 480 },
2507 .vfront_porch = { 4, 9, 30 },
2508 .vback_porch = { 4, 8, 28 },
2509 .vsync_len = { 2, 2, 2 },
2510 .flags = DISPLAY_FLAGS_DE_HIGH,
2511 };
2512
2513 static const struct panel_desc innolux_g070y2_l01 = {
2514 .timings = &innolux_g070y2_l01_timing,
2515 .num_timings = 1,
2516 .bpc = 8,
2517 .size = {
2518 .width = 152,
2519 .height = 91,
2520 },
2521 .delay = {
2522 .prepare = 10,
2523 .enable = 100,
2524 .disable = 100,
2525 .unprepare = 800,
2526 },
2527 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2528 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
2529 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2530 };
2531
2532 static const struct display_timing innolux_g070ace_lh3_timing = {
2533 .pixelclock = { 25200000, 25400000, 35700000 },
2534 .hactive = { 800, 800, 800 },
2535 .hfront_porch = { 30, 32, 87 },
2536 .hback_porch = { 29, 31, 86 },
2537 .hsync_len = { 1, 1, 1 },
2538 .vactive = { 480, 480, 480 },
2539 .vfront_porch = { 4, 5, 65 },
2540 .vback_porch = { 3, 4, 65 },
2541 .vsync_len = { 1, 1, 1 },
2542 .flags = DISPLAY_FLAGS_DE_HIGH,
2543 };
2544
2545 static const struct panel_desc innolux_g070ace_lh3 = {
2546 .timings = &innolux_g070ace_lh3_timing,
2547 .num_timings = 1,
2548 .bpc = 8,
2549 .size = {
2550 .width = 152,
2551 .height = 91,
2552 },
2553 .delay = {
2554 .prepare = 10,
2555 .enable = 450,
2556 .disable = 200,
2557 .unprepare = 510,
2558 },
2559 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2560 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
2561 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2562 };
2563
2564 static const struct drm_display_mode innolux_g070y2_t02_mode = {
2565 .clock = 33333,
2566 .hdisplay = 800,
2567 .hsync_start = 800 + 210,
2568 .hsync_end = 800 + 210 + 20,
2569 .htotal = 800 + 210 + 20 + 46,
2570 .vdisplay = 480,
2571 .vsync_start = 480 + 22,
2572 .vsync_end = 480 + 22 + 10,
2573 .vtotal = 480 + 22 + 23 + 10,
2574 };
2575
2576 static const struct panel_desc innolux_g070y2_t02 = {
2577 .modes = &innolux_g070y2_t02_mode,
2578 .num_modes = 1,
2579 .bpc = 8,
2580 .size = {
2581 .width = 152,
2582 .height = 92,
2583 },
2584 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2585 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
2586 .connector_type = DRM_MODE_CONNECTOR_DPI,
2587 };
2588
2589 static const struct display_timing innolux_g101ice_l01_timing = {
2590 .pixelclock = { 60400000, 71100000, 74700000 },
2591 .hactive = { 1280, 1280, 1280 },
2592 .hfront_porch = { 30, 60, 70 },
2593 .hback_porch = { 30, 60, 70 },
2594 .hsync_len = { 22, 40, 60 },
2595 .vactive = { 800, 800, 800 },
2596 .vfront_porch = { 3, 8, 14 },
2597 .vback_porch = { 3, 8, 14 },
2598 .vsync_len = { 4, 7, 12 },
2599 .flags = DISPLAY_FLAGS_DE_HIGH,
2600 };
2601
2602 static const struct panel_desc innolux_g101ice_l01 = {
2603 .timings = &innolux_g101ice_l01_timing,
2604 .num_timings = 1,
2605 .bpc = 8,
2606 .size = {
2607 .width = 217,
2608 .height = 135,
2609 },
2610 .delay = {
2611 .enable = 200,
2612 .disable = 200,
2613 },
2614 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2615 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
2616 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2617 };
2618
2619 static const struct display_timing innolux_g121i1_l01_timing = {
2620 .pixelclock = { 67450000, 71000000, 74550000 },
2621 .hactive = { 1280, 1280, 1280 },
2622 .hfront_porch = { 40, 80, 160 },
2623 .hback_porch = { 39, 79, 159 },
2624 .hsync_len = { 1, 1, 1 },
2625 .vactive = { 800, 800, 800 },
2626 .vfront_porch = { 5, 11, 100 },
2627 .vback_porch = { 4, 11, 99 },
2628 .vsync_len = { 1, 1, 1 },
2629 };
2630
2631 static const struct panel_desc innolux_g121i1_l01 = {
2632 .timings = &innolux_g121i1_l01_timing,
2633 .num_timings = 1,
2634 .bpc = 6,
2635 .size = {
2636 .width = 261,
2637 .height = 163,
2638 },
2639 .delay = {
2640 .enable = 200,
2641 .disable = 20,
2642 },
2643 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
2644 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2645 };
2646
2647 static const struct display_timing innolux_g121x1_l03_timings = {
2648 .pixelclock = { 57500000, 64900000, 74400000 },
2649 .hactive = { 1024, 1024, 1024 },
2650 .hfront_porch = { 90, 140, 190 },
2651 .hback_porch = { 90, 140, 190 },
2652 .hsync_len = { 36, 40, 60 },
2653 .vactive = { 768, 768, 768 },
2654 .vfront_porch = { 2, 15, 30 },
2655 .vback_porch = { 2, 15, 30 },
2656 .vsync_len = { 2, 8, 20 },
2657 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW,
2658 };
2659
2660 static const struct panel_desc innolux_g121x1_l03 = {
2661 .timings = &innolux_g121x1_l03_timings,
2662 .num_timings = 1,
2663 .bpc = 6,
2664 .size = {
2665 .width = 246,
2666 .height = 185,
2667 },
2668 .delay = {
2669 .enable = 200,
2670 .unprepare = 200,
2671 .disable = 400,
2672 },
2673 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
2674 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
2675 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2676 };
2677
2678 static const struct panel_desc innolux_g121xce_l01 = {
2679 .timings = &innolux_g121x1_l03_timings,
2680 .num_timings = 1,
2681 .bpc = 8,
2682 .size = {
2683 .width = 246,
2684 .height = 185,
2685 },
2686 .delay = {
2687 .enable = 200,
2688 .unprepare = 200,
2689 .disable = 400,
2690 },
2691 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2692 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
2693 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2694 };
2695
2696 static const struct display_timing innolux_g156hce_l01_timings = {
2697 .pixelclock = { 120000000, 141860000, 150000000 },
2698 .hactive = { 1920, 1920, 1920 },
2699 .hfront_porch = { 80, 90, 100 },
2700 .hback_porch = { 80, 90, 100 },
2701 .hsync_len = { 20, 30, 30 },
2702 .vactive = { 1080, 1080, 1080 },
2703 .vfront_porch = { 3, 10, 20 },
2704 .vback_porch = { 3, 10, 20 },
2705 .vsync_len = { 4, 10, 10 },
2706 };
2707
2708 static const struct panel_desc innolux_g156hce_l01 = {
2709 .timings = &innolux_g156hce_l01_timings,
2710 .num_timings = 1,
2711 .bpc = 8,
2712 .size = {
2713 .width = 344,
2714 .height = 194,
2715 },
2716 .delay = {
2717 .prepare = 1, /* T1+T2 */
2718 .enable = 450, /* T5 */
2719 .disable = 200, /* T6 */
2720 .unprepare = 10, /* T3+T7 */
2721 },
2722 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2723 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
2724 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2725 };
2726
2727 static const struct drm_display_mode innolux_n156bge_l21_mode = {
2728 .clock = 69300,
2729 .hdisplay = 1366,
2730 .hsync_start = 1366 + 16,
2731 .hsync_end = 1366 + 16 + 34,
2732 .htotal = 1366 + 16 + 34 + 50,
2733 .vdisplay = 768,
2734 .vsync_start = 768 + 2,
2735 .vsync_end = 768 + 2 + 6,
2736 .vtotal = 768 + 2 + 6 + 12,
2737 };
2738
2739 static const struct panel_desc innolux_n156bge_l21 = {
2740 .modes = &innolux_n156bge_l21_mode,
2741 .num_modes = 1,
2742 .bpc = 6,
2743 .size = {
2744 .width = 344,
2745 .height = 193,
2746 },
2747 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
2748 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
2749 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2750 };
2751
2752 static const struct drm_display_mode innolux_zj070na_01p_mode = {
2753 .clock = 51501,
2754 .hdisplay = 1024,
2755 .hsync_start = 1024 + 128,
2756 .hsync_end = 1024 + 128 + 64,
2757 .htotal = 1024 + 128 + 64 + 128,
2758 .vdisplay = 600,
2759 .vsync_start = 600 + 16,
2760 .vsync_end = 600 + 16 + 4,
2761 .vtotal = 600 + 16 + 4 + 16,
2762 };
2763
2764 static const struct panel_desc innolux_zj070na_01p = {
2765 .modes = &innolux_zj070na_01p_mode,
2766 .num_modes = 1,
2767 .bpc = 6,
2768 .size = {
2769 .width = 154,
2770 .height = 90,
2771 },
2772 };
2773
2774 static const struct display_timing koe_tx14d24vm1bpa_timing = {
2775 .pixelclock = { 5580000, 5850000, 6200000 },
2776 .hactive = { 320, 320, 320 },
2777 .hfront_porch = { 30, 30, 30 },
2778 .hback_porch = { 30, 30, 30 },
2779 .hsync_len = { 1, 5, 17 },
2780 .vactive = { 240, 240, 240 },
2781 .vfront_porch = { 6, 6, 6 },
2782 .vback_porch = { 5, 5, 5 },
2783 .vsync_len = { 1, 2, 11 },
2784 .flags = DISPLAY_FLAGS_DE_HIGH,
2785 };
2786
2787 static const struct panel_desc koe_tx14d24vm1bpa = {
2788 .timings = &koe_tx14d24vm1bpa_timing,
2789 .num_timings = 1,
2790 .bpc = 6,
2791 .size = {
2792 .width = 115,
2793 .height = 86,
2794 },
2795 };
2796
2797 static const struct display_timing koe_tx26d202vm0bwa_timing = {
2798 .pixelclock = { 151820000, 156720000, 159780000 },
2799 .hactive = { 1920, 1920, 1920 },
2800 .hfront_porch = { 105, 130, 142 },
2801 .hback_porch = { 45, 70, 82 },
2802 .hsync_len = { 30, 30, 30 },
2803 .vactive = { 1200, 1200, 1200},
2804 .vfront_porch = { 3, 5, 10 },
2805 .vback_porch = { 2, 5, 10 },
2806 .vsync_len = { 5, 5, 5 },
2807 .flags = DISPLAY_FLAGS_DE_HIGH,
2808 };
2809
2810 static const struct panel_desc koe_tx26d202vm0bwa = {
2811 .timings = &koe_tx26d202vm0bwa_timing,
2812 .num_timings = 1,
2813 .bpc = 8,
2814 .size = {
2815 .width = 217,
2816 .height = 136,
2817 },
2818 .delay = {
2819 .prepare = 1000,
2820 .enable = 1000,
2821 .unprepare = 1000,
2822 .disable = 1000,
2823 },
2824 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2825 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
2826 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2827 };
2828
2829 static const struct display_timing koe_tx31d200vm0baa_timing = {
2830 .pixelclock = { 39600000, 43200000, 48000000 },
2831 .hactive = { 1280, 1280, 1280 },
2832 .hfront_porch = { 16, 36, 56 },
2833 .hback_porch = { 16, 36, 56 },
2834 .hsync_len = { 8, 8, 8 },
2835 .vactive = { 480, 480, 480 },
2836 .vfront_porch = { 6, 21, 33 },
2837 .vback_porch = { 6, 21, 33 },
2838 .vsync_len = { 8, 8, 8 },
2839 .flags = DISPLAY_FLAGS_DE_HIGH,
2840 };
2841
2842 static const struct panel_desc koe_tx31d200vm0baa = {
2843 .timings = &koe_tx31d200vm0baa_timing,
2844 .num_timings = 1,
2845 .bpc = 6,
2846 .size = {
2847 .width = 292,
2848 .height = 109,
2849 },
2850 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
2851 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2852 };
2853
2854 static const struct display_timing kyo_tcg121xglp_timing = {
2855 .pixelclock = { 52000000, 65000000, 71000000 },
2856 .hactive = { 1024, 1024, 1024 },
2857 .hfront_porch = { 2, 2, 2 },
2858 .hback_porch = { 2, 2, 2 },
2859 .hsync_len = { 86, 124, 244 },
2860 .vactive = { 768, 768, 768 },
2861 .vfront_porch = { 2, 2, 2 },
2862 .vback_porch = { 2, 2, 2 },
2863 .vsync_len = { 6, 34, 73 },
2864 .flags = DISPLAY_FLAGS_DE_HIGH,
2865 };
2866
2867 static const struct panel_desc kyo_tcg121xglp = {
2868 .timings = &kyo_tcg121xglp_timing,
2869 .num_timings = 1,
2870 .bpc = 8,
2871 .size = {
2872 .width = 246,
2873 .height = 184,
2874 },
2875 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2876 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2877 };
2878
2879 static const struct drm_display_mode lemaker_bl035_rgb_002_mode = {
2880 .clock = 7000,
2881 .hdisplay = 320,
2882 .hsync_start = 320 + 20,
2883 .hsync_end = 320 + 20 + 30,
2884 .htotal = 320 + 20 + 30 + 38,
2885 .vdisplay = 240,
2886 .vsync_start = 240 + 4,
2887 .vsync_end = 240 + 4 + 3,
2888 .vtotal = 240 + 4 + 3 + 15,
2889 };
2890
2891 static const struct panel_desc lemaker_bl035_rgb_002 = {
2892 .modes = &lemaker_bl035_rgb_002_mode,
2893 .num_modes = 1,
2894 .size = {
2895 .width = 70,
2896 .height = 52,
2897 },
2898 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2899 .bus_flags = DRM_BUS_FLAG_DE_LOW,
2900 };
2901
2902 static const struct display_timing lg_lb070wv8_timing = {
2903 .pixelclock = { 31950000, 33260000, 34600000 },
2904 .hactive = { 800, 800, 800 },
2905 .hfront_porch = { 88, 88, 88 },
2906 .hback_porch = { 88, 88, 88 },
2907 .hsync_len = { 80, 80, 80 },
2908 .vactive = { 480, 480, 480 },
2909 .vfront_porch = { 10, 10, 10 },
2910 .vback_porch = { 10, 10, 10 },
2911 .vsync_len = { 25, 25, 25 },
2912 };
2913
2914 static const struct panel_desc lg_lb070wv8 = {
2915 .timings = &lg_lb070wv8_timing,
2916 .num_timings = 1,
2917 .bpc = 8,
2918 .size = {
2919 .width = 151,
2920 .height = 91,
2921 },
2922 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2923 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2924 };
2925
2926 static const struct drm_display_mode lincolntech_lcd185_101ct_mode = {
2927 .clock = 155127,
2928 .hdisplay = 1920,
2929 .hsync_start = 1920 + 128,
2930 .hsync_end = 1920 + 128 + 20,
2931 .htotal = 1920 + 128 + 20 + 12,
2932 .vdisplay = 1200,
2933 .vsync_start = 1200 + 19,
2934 .vsync_end = 1200 + 19 + 4,
2935 .vtotal = 1200 + 19 + 4 + 20,
2936 };
2937
2938 static const struct panel_desc lincolntech_lcd185_101ct = {
2939 .modes = &lincolntech_lcd185_101ct_mode,
2940 .bpc = 8,
2941 .num_modes = 1,
2942 .size = {
2943 .width = 217,
2944 .height = 136,
2945 },
2946 .delay = {
2947 .prepare = 50,
2948 .disable = 50,
2949 },
2950 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
2951 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2952 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2953 };
2954
2955 static const struct display_timing logictechno_lt161010_2nh_timing = {
2956 .pixelclock = { 26400000, 33300000, 46800000 },
2957 .hactive = { 800, 800, 800 },
2958 .hfront_porch = { 16, 210, 354 },
2959 .hback_porch = { 46, 46, 46 },
2960 .hsync_len = { 1, 20, 40 },
2961 .vactive = { 480, 480, 480 },
2962 .vfront_porch = { 7, 22, 147 },
2963 .vback_porch = { 23, 23, 23 },
2964 .vsync_len = { 1, 10, 20 },
2965 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
2966 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE |
2967 DISPLAY_FLAGS_SYNC_POSEDGE,
2968 };
2969
2970 static const struct panel_desc logictechno_lt161010_2nh = {
2971 .timings = &logictechno_lt161010_2nh_timing,
2972 .num_timings = 1,
2973 .bpc = 6,
2974 .size = {
2975 .width = 154,
2976 .height = 86,
2977 },
2978 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
2979 .bus_flags = DRM_BUS_FLAG_DE_HIGH |
2980 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE |
2981 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE,
2982 .connector_type = DRM_MODE_CONNECTOR_DPI,
2983 };
2984
2985 static const struct display_timing logictechno_lt170410_2whc_timing = {
2986 .pixelclock = { 68900000, 71100000, 73400000 },
2987 .hactive = { 1280, 1280, 1280 },
2988 .hfront_porch = { 23, 60, 71 },
2989 .hback_porch = { 23, 60, 71 },
2990 .hsync_len = { 15, 40, 47 },
2991 .vactive = { 800, 800, 800 },
2992 .vfront_porch = { 5, 7, 10 },
2993 .vback_porch = { 5, 7, 10 },
2994 .vsync_len = { 6, 9, 12 },
2995 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
2996 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE |
2997 DISPLAY_FLAGS_SYNC_POSEDGE,
2998 };
2999
3000 static const struct panel_desc logictechno_lt170410_2whc = {
3001 .timings = &logictechno_lt170410_2whc_timing,
3002 .num_timings = 1,
3003 .bpc = 8,
3004 .size = {
3005 .width = 217,
3006 .height = 136,
3007 },
3008 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
3009 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
3010 .connector_type = DRM_MODE_CONNECTOR_LVDS,
3011 };
3012
3013 static const struct drm_display_mode logictechno_lttd800480070_l2rt_mode = {
3014 .clock = 33000,
3015 .hdisplay = 800,
3016 .hsync_start = 800 + 112,
3017 .hsync_end = 800 + 112 + 3,
3018 .htotal = 800 + 112 + 3 + 85,
3019 .vdisplay = 480,
3020 .vsync_start = 480 + 38,
3021 .vsync_end = 480 + 38 + 3,
3022 .vtotal = 480 + 38 + 3 + 29,
3023 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
3024 };
3025
3026 static const struct panel_desc logictechno_lttd800480070_l2rt = {
3027 .modes = &logictechno_lttd800480070_l2rt_mode,
3028 .num_modes = 1,
3029 .bpc = 8,
3030 .size = {
3031 .width = 154,
3032 .height = 86,
3033 },
3034 .delay = {
3035 .prepare = 45,
3036 .enable = 100,
3037 .disable = 100,
3038 .unprepare = 45
3039 },
3040 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3041 .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
3042 .connector_type = DRM_MODE_CONNECTOR_DPI,
3043 };
3044
3045 static const struct drm_display_mode logictechno_lttd800480070_l6wh_rt_mode = {
3046 .clock = 33000,
3047 .hdisplay = 800,
3048 .hsync_start = 800 + 154,
3049 .hsync_end = 800 + 154 + 3,
3050 .htotal = 800 + 154 + 3 + 43,
3051 .vdisplay = 480,
3052 .vsync_start = 480 + 47,
3053 .vsync_end = 480 + 47 + 3,
3054 .vtotal = 480 + 47 + 3 + 20,
3055 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
3056 };
3057
3058 static const struct panel_desc logictechno_lttd800480070_l6wh_rt = {
3059 .modes = &logictechno_lttd800480070_l6wh_rt_mode,
3060 .num_modes = 1,
3061 .bpc = 8,
3062 .size = {
3063 .width = 154,
3064 .height = 86,
3065 },
3066 .delay = {
3067 .prepare = 45,
3068 .enable = 100,
3069 .disable = 100,
3070 .unprepare = 45
3071 },
3072 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3073 .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
3074 .connector_type = DRM_MODE_CONNECTOR_DPI,
3075 };
3076
3077 static const struct drm_display_mode logicpd_type_28_mode = {
3078 .clock = 9107,
3079 .hdisplay = 480,
3080 .hsync_start = 480 + 3,
3081 .hsync_end = 480 + 3 + 42,
3082 .htotal = 480 + 3 + 42 + 2,
3083
3084 .vdisplay = 272,
3085 .vsync_start = 272 + 2,
3086 .vsync_end = 272 + 2 + 11,
3087 .vtotal = 272 + 2 + 11 + 3,
3088 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
3089 };
3090
3091 static const struct panel_desc logicpd_type_28 = {
3092 .modes = &logicpd_type_28_mode,
3093 .num_modes = 1,
3094 .bpc = 8,
3095 .size = {
3096 .width = 105,
3097 .height = 67,
3098 },
3099 .delay = {
3100 .prepare = 200,
3101 .enable = 200,
3102 .unprepare = 200,
3103 .disable = 200,
3104 },
3105 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3106 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE |
3107 DRM_BUS_FLAG_SYNC_DRIVE_NEGEDGE,
3108 .connector_type = DRM_MODE_CONNECTOR_DPI,
3109 };
3110
3111 static const struct drm_display_mode microtips_mf_101hiebcaf0_c_mode = {
3112 .clock = 150275,
3113 .hdisplay = 1920,
3114 .hsync_start = 1920 + 32,
3115 .hsync_end = 1920 + 32 + 52,
3116 .htotal = 1920 + 32 + 52 + 24,
3117 .vdisplay = 1200,
3118 .vsync_start = 1200 + 24,
3119 .vsync_end = 1200 + 24 + 8,
3120 .vtotal = 1200 + 24 + 8 + 3,
3121 };
3122
3123 static const struct panel_desc microtips_mf_101hiebcaf0_c = {
3124 .modes = µtips_mf_101hiebcaf0_c_mode,
3125 .bpc = 8,
3126 .num_modes = 1,
3127 .size = {
3128 .width = 217,
3129 .height = 136,
3130 },
3131 .delay = {
3132 .prepare = 50,
3133 .disable = 50,
3134 },
3135 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
3136 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
3137 .connector_type = DRM_MODE_CONNECTOR_LVDS,
3138 };
3139
3140 static const struct drm_display_mode microtips_mf_103hieb0ga0_mode = {
3141 .clock = 93301,
3142 .hdisplay = 1920,
3143 .hsync_start = 1920 + 72,
3144 .hsync_end = 1920 + 72 + 72,
3145 .htotal = 1920 + 72 + 72 + 72,
3146 .vdisplay = 720,
3147 .vsync_start = 720 + 3,
3148 .vsync_end = 720 + 3 + 3,
3149 .vtotal = 720 + 3 + 3 + 2,
3150 };
3151
3152 static const struct panel_desc microtips_mf_103hieb0ga0 = {
3153 .modes = µtips_mf_103hieb0ga0_mode,
3154 .bpc = 8,
3155 .num_modes = 1,
3156 .size = {
3157 .width = 244,
3158 .height = 92,
3159 },
3160 .delay = {
3161 .prepare = 50,
3162 .disable = 50,
3163 },
3164 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
3165 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
3166 .connector_type = DRM_MODE_CONNECTOR_LVDS,
3167 };
3168
3169 static const struct drm_display_mode mitsubishi_aa070mc01_mode = {
3170 .clock = 30400,
3171 .hdisplay = 800,
3172 .hsync_start = 800 + 0,
3173 .hsync_end = 800 + 1,
3174 .htotal = 800 + 0 + 1 + 160,
3175 .vdisplay = 480,
3176 .vsync_start = 480 + 0,
3177 .vsync_end = 480 + 48 + 1,
3178 .vtotal = 480 + 48 + 1 + 0,
3179 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
3180 };
3181
3182 static const struct panel_desc mitsubishi_aa070mc01 = {
3183 .modes = &mitsubishi_aa070mc01_mode,
3184 .num_modes = 1,
3185 .bpc = 8,
3186 .size = {
3187 .width = 152,
3188 .height = 91,
3189 },
3190
3191 .delay = {
3192 .enable = 200,
3193 .unprepare = 200,
3194 .disable = 400,
3195 },
3196 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
3197 .connector_type = DRM_MODE_CONNECTOR_LVDS,
3198 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
3199 };
3200
3201 static const struct drm_display_mode mitsubishi_aa084xe01_mode = {
3202 .clock = 56234,
3203 .hdisplay = 1024,
3204 .hsync_start = 1024 + 24,
3205 .hsync_end = 1024 + 24 + 63,
3206 .htotal = 1024 + 24 + 63 + 1,
3207 .vdisplay = 768,
3208 .vsync_start = 768 + 3,
3209 .vsync_end = 768 + 3 + 6,
3210 .vtotal = 768 + 3 + 6 + 1,
3211 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
3212 };
3213
3214 static const struct panel_desc mitsubishi_aa084xe01 = {
3215 .modes = &mitsubishi_aa084xe01_mode,
3216 .num_modes = 1,
3217 .bpc = 8,
3218 .size = {
3219 .width = 1024,
3220 .height = 768,
3221 },
3222 .bus_format = MEDIA_BUS_FMT_RGB565_1X16,
3223 .connector_type = DRM_MODE_CONNECTOR_DPI,
3224 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
3225 };
3226
3227 static const struct display_timing multi_inno_mi0700s4t_6_timing = {
3228 .pixelclock = { 29000000, 33000000, 38000000 },
3229 .hactive = { 800, 800, 800 },
3230 .hfront_porch = { 180, 210, 240 },
3231 .hback_porch = { 16, 16, 16 },
3232 .hsync_len = { 30, 30, 30 },
3233 .vactive = { 480, 480, 480 },
3234 .vfront_porch = { 12, 22, 32 },
3235 .vback_porch = { 10, 10, 10 },
3236 .vsync_len = { 13, 13, 13 },
3237 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
3238 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE |
3239 DISPLAY_FLAGS_SYNC_POSEDGE,
3240 };
3241
3242 static const struct panel_desc multi_inno_mi0700s4t_6 = {
3243 .timings = &multi_inno_mi0700s4t_6_timing,
3244 .num_timings = 1,
3245 .bpc = 8,
3246 .size = {
3247 .width = 154,
3248 .height = 86,
3249 },
3250 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3251 .bus_flags = DRM_BUS_FLAG_DE_HIGH |
3252 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE |
3253 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE,
3254 .connector_type = DRM_MODE_CONNECTOR_DPI,
3255 };
3256
3257 static const struct display_timing multi_inno_mi0800ft_9_timing = {
3258 .pixelclock = { 32000000, 40000000, 50000000 },
3259 .hactive = { 800, 800, 800 },
3260 .hfront_porch = { 16, 210, 354 },
3261 .hback_porch = { 6, 26, 45 },
3262 .hsync_len = { 1, 20, 40 },
3263 .vactive = { 600, 600, 600 },
3264 .vfront_porch = { 1, 12, 77 },
3265 .vback_porch = { 3, 13, 22 },
3266 .vsync_len = { 1, 10, 20 },
3267 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
3268 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE |
3269 DISPLAY_FLAGS_SYNC_POSEDGE,
3270 };
3271
3272 static const struct panel_desc multi_inno_mi0800ft_9 = {
3273 .timings = &multi_inno_mi0800ft_9_timing,
3274 .num_timings = 1,
3275 .bpc = 8,
3276 .size = {
3277 .width = 162,
3278 .height = 122,
3279 },
3280 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3281 .bus_flags = DRM_BUS_FLAG_DE_HIGH |
3282 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE |
3283 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE,
3284 .connector_type = DRM_MODE_CONNECTOR_DPI,
3285 };
3286
3287 static const struct display_timing multi_inno_mi1010ait_1cp_timing = {
3288 .pixelclock = { 68900000, 70000000, 73400000 },
3289 .hactive = { 1280, 1280, 1280 },
3290 .hfront_porch = { 30, 60, 71 },
3291 .hback_porch = { 30, 60, 71 },
3292 .hsync_len = { 10, 10, 48 },
3293 .vactive = { 800, 800, 800 },
3294 .vfront_porch = { 5, 10, 10 },
3295 .vback_porch = { 5, 10, 10 },
3296 .vsync_len = { 5, 6, 13 },
3297 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
3298 DISPLAY_FLAGS_DE_HIGH,
3299 };
3300
3301 static const struct panel_desc multi_inno_mi1010ait_1cp = {
3302 .timings = &multi_inno_mi1010ait_1cp_timing,
3303 .num_timings = 1,
3304 .bpc = 8,
3305 .size = {
3306 .width = 217,
3307 .height = 136,
3308 },
3309 .delay = {
3310 .enable = 50,
3311 .disable = 50,
3312 },
3313 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
3314 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
3315 .connector_type = DRM_MODE_CONNECTOR_LVDS,
3316 };
3317
3318 static const struct display_timing nec_nl12880bc20_05_timing = {
3319 .pixelclock = { 67000000, 71000000, 75000000 },
3320 .hactive = { 1280, 1280, 1280 },
3321 .hfront_porch = { 2, 30, 30 },
3322 .hback_porch = { 6, 100, 100 },
3323 .hsync_len = { 2, 30, 30 },
3324 .vactive = { 800, 800, 800 },
3325 .vfront_porch = { 5, 5, 5 },
3326 .vback_porch = { 11, 11, 11 },
3327 .vsync_len = { 7, 7, 7 },
3328 };
3329
3330 static const struct panel_desc nec_nl12880bc20_05 = {
3331 .timings = &nec_nl12880bc20_05_timing,
3332 .num_timings = 1,
3333 .bpc = 8,
3334 .size = {
3335 .width = 261,
3336 .height = 163,
3337 },
3338 .delay = {
3339 .enable = 50,
3340 .disable = 50,
3341 },
3342 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
3343 .connector_type = DRM_MODE_CONNECTOR_LVDS,
3344 };
3345
3346 static const struct drm_display_mode nec_nl4827hc19_05b_mode = {
3347 .clock = 10870,
3348 .hdisplay = 480,
3349 .hsync_start = 480 + 2,
3350 .hsync_end = 480 + 2 + 41,
3351 .htotal = 480 + 2 + 41 + 2,
3352 .vdisplay = 272,
3353 .vsync_start = 272 + 2,
3354 .vsync_end = 272 + 2 + 4,
3355 .vtotal = 272 + 2 + 4 + 2,
3356 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
3357 };
3358
3359 static const struct panel_desc nec_nl4827hc19_05b = {
3360 .modes = &nec_nl4827hc19_05b_mode,
3361 .num_modes = 1,
3362 .bpc = 8,
3363 .size = {
3364 .width = 95,
3365 .height = 54,
3366 },
3367 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3368 .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
3369 };
3370
3371 static const struct drm_display_mode netron_dy_e231732_mode = {
3372 .clock = 66000,
3373 .hdisplay = 1024,
3374 .hsync_start = 1024 + 160,
3375 .hsync_end = 1024 + 160 + 70,
3376 .htotal = 1024 + 160 + 70 + 90,
3377 .vdisplay = 600,
3378 .vsync_start = 600 + 127,
3379 .vsync_end = 600 + 127 + 20,
3380 .vtotal = 600 + 127 + 20 + 3,
3381 };
3382
3383 static const struct panel_desc netron_dy_e231732 = {
3384 .modes = &netron_dy_e231732_mode,
3385 .num_modes = 1,
3386 .size = {
3387 .width = 154,
3388 .height = 87,
3389 },
3390 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
3391 };
3392
3393 static const struct drm_display_mode newhaven_nhd_43_480272ef_atxl_mode = {
3394 .clock = 9000,
3395 .hdisplay = 480,
3396 .hsync_start = 480 + 2,
3397 .hsync_end = 480 + 2 + 41,
3398 .htotal = 480 + 2 + 41 + 2,
3399 .vdisplay = 272,
3400 .vsync_start = 272 + 2,
3401 .vsync_end = 272 + 2 + 10,
3402 .vtotal = 272 + 2 + 10 + 2,
3403 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
3404 };
3405
3406 static const struct panel_desc newhaven_nhd_43_480272ef_atxl = {
3407 .modes = &newhaven_nhd_43_480272ef_atxl_mode,
3408 .num_modes = 1,
3409 .bpc = 8,
3410 .size = {
3411 .width = 95,
3412 .height = 54,
3413 },
3414 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3415 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE |
3416 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE,
3417 .connector_type = DRM_MODE_CONNECTOR_DPI,
3418 };
3419
3420 static const struct display_timing nlt_nl192108ac18_02d_timing = {
3421 .pixelclock = { 130000000, 148350000, 163000000 },
3422 .hactive = { 1920, 1920, 1920 },
3423 .hfront_porch = { 80, 100, 100 },
3424 .hback_porch = { 100, 120, 120 },
3425 .hsync_len = { 50, 60, 60 },
3426 .vactive = { 1080, 1080, 1080 },
3427 .vfront_porch = { 12, 30, 30 },
3428 .vback_porch = { 4, 10, 10 },
3429 .vsync_len = { 4, 5, 5 },
3430 };
3431
3432 static const struct panel_desc nlt_nl192108ac18_02d = {
3433 .timings = &nlt_nl192108ac18_02d_timing,
3434 .num_timings = 1,
3435 .bpc = 8,
3436 .size = {
3437 .width = 344,
3438 .height = 194,
3439 },
3440 .delay = {
3441 .unprepare = 500,
3442 },
3443 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
3444 .connector_type = DRM_MODE_CONNECTOR_LVDS,
3445 };
3446
3447 static const struct drm_display_mode nvd_9128_mode = {
3448 .clock = 29500,
3449 .hdisplay = 800,
3450 .hsync_start = 800 + 130,
3451 .hsync_end = 800 + 130 + 98,
3452 .htotal = 800 + 0 + 130 + 98,
3453 .vdisplay = 480,
3454 .vsync_start = 480 + 10,
3455 .vsync_end = 480 + 10 + 50,
3456 .vtotal = 480 + 0 + 10 + 50,
3457 };
3458
3459 static const struct panel_desc nvd_9128 = {
3460 .modes = &nvd_9128_mode,
3461 .num_modes = 1,
3462 .bpc = 8,
3463 .size = {
3464 .width = 156,
3465 .height = 88,
3466 },
3467 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
3468 .connector_type = DRM_MODE_CONNECTOR_LVDS,
3469 };
3470
3471 static const struct display_timing okaya_rs800480t_7x0gp_timing = {
3472 .pixelclock = { 30000000, 30000000, 40000000 },
3473 .hactive = { 800, 800, 800 },
3474 .hfront_porch = { 40, 40, 40 },
3475 .hback_porch = { 40, 40, 40 },
3476 .hsync_len = { 1, 48, 48 },
3477 .vactive = { 480, 480, 480 },
3478 .vfront_porch = { 13, 13, 13 },
3479 .vback_porch = { 29, 29, 29 },
3480 .vsync_len = { 3, 3, 3 },
3481 .flags = DISPLAY_FLAGS_DE_HIGH,
3482 };
3483
3484 static const struct panel_desc okaya_rs800480t_7x0gp = {
3485 .timings = &okaya_rs800480t_7x0gp_timing,
3486 .num_timings = 1,
3487 .bpc = 6,
3488 .size = {
3489 .width = 154,
3490 .height = 87,
3491 },
3492 .delay = {
3493 .prepare = 41,
3494 .enable = 50,
3495 .unprepare = 41,
3496 .disable = 50,
3497 },
3498 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
3499 };
3500
3501 static const struct drm_display_mode olimex_lcd_olinuxino_43ts_mode = {
3502 .clock = 9000,
3503 .hdisplay = 480,
3504 .hsync_start = 480 + 5,
3505 .hsync_end = 480 + 5 + 30,
3506 .htotal = 480 + 5 + 30 + 10,
3507 .vdisplay = 272,
3508 .vsync_start = 272 + 8,
3509 .vsync_end = 272 + 8 + 5,
3510 .vtotal = 272 + 8 + 5 + 3,
3511 };
3512
3513 static const struct panel_desc olimex_lcd_olinuxino_43ts = {
3514 .modes = &olimex_lcd_olinuxino_43ts_mode,
3515 .num_modes = 1,
3516 .size = {
3517 .width = 95,
3518 .height = 54,
3519 },
3520 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3521 };
3522
3523 static const struct display_timing ontat_kd50g21_40nt_a1_timing = {
3524 .pixelclock = { 30000000, 30000000, 50000000 },
3525 .hactive = { 800, 800, 800 },
3526 .hfront_porch = { 1, 40, 255 },
3527 .hback_porch = { 1, 40, 87 },
3528 .hsync_len = { 1, 48, 87 },
3529 .vactive = { 480, 480, 480 },
3530 .vfront_porch = { 1, 13, 255 },
3531 .vback_porch = { 1, 29, 29 },
3532 .vsync_len = { 3, 3, 31 },
3533 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
3534 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE,
3535 };
3536
3537 static const struct panel_desc ontat_kd50g21_40nt_a1 = {
3538 .timings = &ontat_kd50g21_40nt_a1_timing,
3539 .num_timings = 1,
3540 .bpc = 8,
3541 .size = {
3542 .width = 108,
3543 .height = 65,
3544 },
3545 .delay = {
3546 .prepare = 147, /* 5 VSDs */
3547 .enable = 147, /* 5 VSDs */
3548 .disable = 88, /* 3 VSDs */
3549 .unprepare = 117, /* 4 VSDs */
3550 },
3551 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3552 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
3553 .connector_type = DRM_MODE_CONNECTOR_DPI,
3554 };
3555
3556 /*
3557 * 800x480 CVT. The panel appears to be quite accepting, at least as far as
3558 * pixel clocks, but this is the timing that was being used in the Adafruit
3559 * installation instructions.
3560 */
3561 static const struct drm_display_mode ontat_yx700wv03_mode = {
3562 .clock = 29500,
3563 .hdisplay = 800,
3564 .hsync_start = 824,
3565 .hsync_end = 896,
3566 .htotal = 992,
3567 .vdisplay = 480,
3568 .vsync_start = 483,
3569 .vsync_end = 493,
3570 .vtotal = 500,
3571 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
3572 };
3573
3574 /*
3575 * Specification at:
3576 * https://www.adafruit.com/images/product-files/2406/c3163.pdf
3577 */
3578 static const struct panel_desc ontat_yx700wv03 = {
3579 .modes = &ontat_yx700wv03_mode,
3580 .num_modes = 1,
3581 .bpc = 8,
3582 .size = {
3583 .width = 154,
3584 .height = 83,
3585 },
3586 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
3587 };
3588
3589 static const struct drm_display_mode ortustech_com37h3m_mode = {
3590 .clock = 22230,
3591 .hdisplay = 480,
3592 .hsync_start = 480 + 40,
3593 .hsync_end = 480 + 40 + 10,
3594 .htotal = 480 + 40 + 10 + 40,
3595 .vdisplay = 640,
3596 .vsync_start = 640 + 4,
3597 .vsync_end = 640 + 4 + 2,
3598 .vtotal = 640 + 4 + 2 + 4,
3599 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
3600 };
3601
3602 static const struct panel_desc ortustech_com37h3m = {
3603 .modes = &ortustech_com37h3m_mode,
3604 .num_modes = 1,
3605 .bpc = 8,
3606 .size = {
3607 .width = 56, /* 56.16mm */
3608 .height = 75, /* 74.88mm */
3609 },
3610 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3611 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE |
3612 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE,
3613 };
3614
3615 static const struct drm_display_mode ortustech_com43h4m85ulc_mode = {
3616 .clock = 25000,
3617 .hdisplay = 480,
3618 .hsync_start = 480 + 10,
3619 .hsync_end = 480 + 10 + 10,
3620 .htotal = 480 + 10 + 10 + 15,
3621 .vdisplay = 800,
3622 .vsync_start = 800 + 3,
3623 .vsync_end = 800 + 3 + 3,
3624 .vtotal = 800 + 3 + 3 + 3,
3625 };
3626
3627 static const struct panel_desc ortustech_com43h4m85ulc = {
3628 .modes = &ortustech_com43h4m85ulc_mode,
3629 .num_modes = 1,
3630 .bpc = 6,
3631 .size = {
3632 .width = 56,
3633 .height = 93,
3634 },
3635 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
3636 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
3637 .connector_type = DRM_MODE_CONNECTOR_DPI,
3638 };
3639
3640 static const struct drm_display_mode osddisplays_osd070t1718_19ts_mode = {
3641 .clock = 33000,
3642 .hdisplay = 800,
3643 .hsync_start = 800 + 210,
3644 .hsync_end = 800 + 210 + 30,
3645 .htotal = 800 + 210 + 30 + 16,
3646 .vdisplay = 480,
3647 .vsync_start = 480 + 22,
3648 .vsync_end = 480 + 22 + 13,
3649 .vtotal = 480 + 22 + 13 + 10,
3650 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
3651 };
3652
3653 static const struct panel_desc osddisplays_osd070t1718_19ts = {
3654 .modes = &osddisplays_osd070t1718_19ts_mode,
3655 .num_modes = 1,
3656 .bpc = 8,
3657 .size = {
3658 .width = 152,
3659 .height = 91,
3660 },
3661 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3662 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE |
3663 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE,
3664 .connector_type = DRM_MODE_CONNECTOR_DPI,
3665 };
3666
3667 static const struct drm_display_mode pda_91_00156_a0_mode = {
3668 .clock = 33300,
3669 .hdisplay = 800,
3670 .hsync_start = 800 + 1,
3671 .hsync_end = 800 + 1 + 64,
3672 .htotal = 800 + 1 + 64 + 64,
3673 .vdisplay = 480,
3674 .vsync_start = 480 + 1,
3675 .vsync_end = 480 + 1 + 23,
3676 .vtotal = 480 + 1 + 23 + 22,
3677 };
3678
3679 static const struct panel_desc pda_91_00156_a0 = {
3680 .modes = &pda_91_00156_a0_mode,
3681 .num_modes = 1,
3682 .size = {
3683 .width = 152,
3684 .height = 91,
3685 },
3686 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3687 };
3688
3689 static const struct drm_display_mode powertip_ph128800t006_zhc01_mode = {
3690 .clock = 66500,
3691 .hdisplay = 1280,
3692 .hsync_start = 1280 + 12,
3693 .hsync_end = 1280 + 12 + 20,
3694 .htotal = 1280 + 12 + 20 + 56,
3695 .vdisplay = 800,
3696 .vsync_start = 800 + 1,
3697 .vsync_end = 800 + 1 + 3,
3698 .vtotal = 800 + 1 + 3 + 20,
3699 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
3700 };
3701
3702 static const struct panel_desc powertip_ph128800t006_zhc01 = {
3703 .modes = &powertip_ph128800t006_zhc01_mode,
3704 .num_modes = 1,
3705 .bpc = 8,
3706 .size = {
3707 .width = 216,
3708 .height = 135,
3709 },
3710 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
3711 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
3712 .connector_type = DRM_MODE_CONNECTOR_LVDS,
3713 };
3714
3715 static const struct drm_display_mode powertip_ph800480t013_idf02_mode = {
3716 .clock = 24750,
3717 .hdisplay = 800,
3718 .hsync_start = 800 + 54,
3719 .hsync_end = 800 + 54 + 2,
3720 .htotal = 800 + 54 + 2 + 44,
3721 .vdisplay = 480,
3722 .vsync_start = 480 + 49,
3723 .vsync_end = 480 + 49 + 2,
3724 .vtotal = 480 + 49 + 2 + 22,
3725 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
3726 };
3727
3728 static const struct panel_desc powertip_ph800480t013_idf02 = {
3729 .modes = &powertip_ph800480t013_idf02_mode,
3730 .num_modes = 1,
3731 .bpc = 8,
3732 .size = {
3733 .width = 152,
3734 .height = 91,
3735 },
3736 .bus_flags = DRM_BUS_FLAG_DE_HIGH |
3737 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE |
3738 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE,
3739 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3740 .connector_type = DRM_MODE_CONNECTOR_DPI,
3741 };
3742
3743 static const struct drm_display_mode primeview_pm070wl4_mode = {
3744 .clock = 32000,
3745 .hdisplay = 800,
3746 .hsync_start = 800 + 42,
3747 .hsync_end = 800 + 42 + 128,
3748 .htotal = 800 + 42 + 128 + 86,
3749 .vdisplay = 480,
3750 .vsync_start = 480 + 10,
3751 .vsync_end = 480 + 10 + 2,
3752 .vtotal = 480 + 10 + 2 + 33,
3753 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
3754 };
3755
3756 static const struct panel_desc primeview_pm070wl4 = {
3757 .modes = &primeview_pm070wl4_mode,
3758 .num_modes = 1,
3759 .bpc = 6,
3760 .size = {
3761 .width = 152,
3762 .height = 91,
3763 },
3764 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE,
3765 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
3766 .connector_type = DRM_MODE_CONNECTOR_DPI,
3767 };
3768
3769 static const struct drm_display_mode qd43003c0_40_mode = {
3770 .clock = 9000,
3771 .hdisplay = 480,
3772 .hsync_start = 480 + 8,
3773 .hsync_end = 480 + 8 + 4,
3774 .htotal = 480 + 8 + 4 + 39,
3775 .vdisplay = 272,
3776 .vsync_start = 272 + 4,
3777 .vsync_end = 272 + 4 + 10,
3778 .vtotal = 272 + 4 + 10 + 2,
3779 };
3780
3781 static const struct panel_desc qd43003c0_40 = {
3782 .modes = &qd43003c0_40_mode,
3783 .num_modes = 1,
3784 .bpc = 8,
3785 .size = {
3786 .width = 95,
3787 .height = 53,
3788 },
3789 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3790 };
3791
3792 static const struct drm_display_mode qishenglong_gopher2b_lcd_modes[] = {
3793 { /* 60 Hz */
3794 .clock = 10800,
3795 .hdisplay = 480,
3796 .hsync_start = 480 + 77,
3797 .hsync_end = 480 + 77 + 41,
3798 .htotal = 480 + 77 + 41 + 2,
3799 .vdisplay = 272,
3800 .vsync_start = 272 + 16,
3801 .vsync_end = 272 + 16 + 10,
3802 .vtotal = 272 + 16 + 10 + 2,
3803 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
3804 },
3805 { /* 50 Hz */
3806 .clock = 10800,
3807 .hdisplay = 480,
3808 .hsync_start = 480 + 17,
3809 .hsync_end = 480 + 17 + 41,
3810 .htotal = 480 + 17 + 41 + 2,
3811 .vdisplay = 272,
3812 .vsync_start = 272 + 116,
3813 .vsync_end = 272 + 116 + 10,
3814 .vtotal = 272 + 116 + 10 + 2,
3815 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
3816 },
3817 };
3818
3819 static const struct panel_desc qishenglong_gopher2b_lcd = {
3820 .modes = qishenglong_gopher2b_lcd_modes,
3821 .num_modes = ARRAY_SIZE(qishenglong_gopher2b_lcd_modes),
3822 .bpc = 8,
3823 .size = {
3824 .width = 95,
3825 .height = 54,
3826 },
3827 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3828 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
3829 .connector_type = DRM_MODE_CONNECTOR_DPI,
3830 };
3831
3832 static const struct display_timing rocktech_rk043fn48h_timing = {
3833 .pixelclock = { 6000000, 9000000, 12000000 },
3834 .hactive = { 480, 480, 480 },
3835 .hback_porch = { 8, 43, 43 },
3836 .hfront_porch = { 2, 8, 10 },
3837 .hsync_len = { 1, 1, 1 },
3838 .vactive = { 272, 272, 272 },
3839 .vback_porch = { 2, 12, 26 },
3840 .vfront_porch = { 1, 4, 4 },
3841 .vsync_len = { 1, 10, 10 },
3842 .flags = DISPLAY_FLAGS_VSYNC_LOW | DISPLAY_FLAGS_HSYNC_LOW |
3843 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE |
3844 DISPLAY_FLAGS_SYNC_POSEDGE,
3845 };
3846
3847 static const struct panel_desc rocktech_rk043fn48h = {
3848 .timings = &rocktech_rk043fn48h_timing,
3849 .num_timings = 1,
3850 .bpc = 8,
3851 .size = {
3852 .width = 95,
3853 .height = 54,
3854 },
3855 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3856 .connector_type = DRM_MODE_CONNECTOR_DPI,
3857 };
3858
3859 static const struct display_timing rocktech_rk070er9427_timing = {
3860 .pixelclock = { 26400000, 33300000, 46800000 },
3861 .hactive = { 800, 800, 800 },
3862 .hfront_porch = { 16, 210, 354 },
3863 .hback_porch = { 46, 46, 46 },
3864 .hsync_len = { 1, 1, 1 },
3865 .vactive = { 480, 480, 480 },
3866 .vfront_porch = { 7, 22, 147 },
3867 .vback_porch = { 23, 23, 23 },
3868 .vsync_len = { 1, 1, 1 },
3869 .flags = DISPLAY_FLAGS_DE_HIGH,
3870 };
3871
3872 static const struct panel_desc rocktech_rk070er9427 = {
3873 .timings = &rocktech_rk070er9427_timing,
3874 .num_timings = 1,
3875 .bpc = 6,
3876 .size = {
3877 .width = 154,
3878 .height = 86,
3879 },
3880 .delay = {
3881 .prepare = 41,
3882 .enable = 50,
3883 .unprepare = 41,
3884 .disable = 50,
3885 },
3886 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
3887 };
3888
3889 static const struct drm_display_mode rocktech_rk101ii01d_ct_mode = {
3890 .clock = 71100,
3891 .hdisplay = 1280,
3892 .hsync_start = 1280 + 48,
3893 .hsync_end = 1280 + 48 + 32,
3894 .htotal = 1280 + 48 + 32 + 80,
3895 .vdisplay = 800,
3896 .vsync_start = 800 + 2,
3897 .vsync_end = 800 + 2 + 5,
3898 .vtotal = 800 + 2 + 5 + 16,
3899 };
3900
3901 static const struct panel_desc rocktech_rk101ii01d_ct = {
3902 .modes = &rocktech_rk101ii01d_ct_mode,
3903 .bpc = 8,
3904 .num_modes = 1,
3905 .size = {
3906 .width = 217,
3907 .height = 136,
3908 },
3909 .delay = {
3910 .prepare = 50,
3911 .disable = 50,
3912 },
3913 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
3914 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
3915 .connector_type = DRM_MODE_CONNECTOR_LVDS,
3916 };
3917
3918 static const struct display_timing samsung_ltl101al01_timing = {
3919 .pixelclock = { 66663000, 66663000, 66663000 },
3920 .hactive = { 1280, 1280, 1280 },
3921 .hfront_porch = { 18, 18, 18 },
3922 .hback_porch = { 36, 36, 36 },
3923 .hsync_len = { 16, 16, 16 },
3924 .vactive = { 800, 800, 800 },
3925 .vfront_porch = { 4, 4, 4 },
3926 .vback_porch = { 16, 16, 16 },
3927 .vsync_len = { 3, 3, 3 },
3928 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW,
3929 };
3930
3931 static const struct panel_desc samsung_ltl101al01 = {
3932 .timings = &samsung_ltl101al01_timing,
3933 .num_timings = 1,
3934 .bpc = 8,
3935 .size = {
3936 .width = 217,
3937 .height = 135,
3938 },
3939 .delay = {
3940 .prepare = 40,
3941 .enable = 300,
3942 .disable = 200,
3943 .unprepare = 600,
3944 },
3945 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
3946 .connector_type = DRM_MODE_CONNECTOR_LVDS,
3947 };
3948
3949 static const struct drm_display_mode samsung_ltn101nt05_mode = {
3950 .clock = 54030,
3951 .hdisplay = 1024,
3952 .hsync_start = 1024 + 24,
3953 .hsync_end = 1024 + 24 + 136,
3954 .htotal = 1024 + 24 + 136 + 160,
3955 .vdisplay = 600,
3956 .vsync_start = 600 + 3,
3957 .vsync_end = 600 + 3 + 6,
3958 .vtotal = 600 + 3 + 6 + 61,
3959 };
3960
3961 static const struct panel_desc samsung_ltn101nt05 = {
3962 .modes = &samsung_ltn101nt05_mode,
3963 .num_modes = 1,
3964 .bpc = 6,
3965 .size = {
3966 .width = 223,
3967 .height = 125,
3968 },
3969 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
3970 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
3971 .connector_type = DRM_MODE_CONNECTOR_LVDS,
3972 };
3973
3974 static const struct display_timing satoz_sat050at40h12r2_timing = {
3975 .pixelclock = {33300000, 33300000, 50000000},
3976 .hactive = {800, 800, 800},
3977 .hfront_porch = {16, 210, 354},
3978 .hback_porch = {46, 46, 46},
3979 .hsync_len = {1, 1, 40},
3980 .vactive = {480, 480, 480},
3981 .vfront_porch = {7, 22, 147},
3982 .vback_porch = {23, 23, 23},
3983 .vsync_len = {1, 1, 20},
3984 };
3985
3986 static const struct panel_desc satoz_sat050at40h12r2 = {
3987 .timings = &satoz_sat050at40h12r2_timing,
3988 .num_timings = 1,
3989 .bpc = 8,
3990 .size = {
3991 .width = 108,
3992 .height = 65,
3993 },
3994 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
3995 .connector_type = DRM_MODE_CONNECTOR_LVDS,
3996 };
3997
3998 static const struct drm_display_mode sharp_lq070y3dg3b_mode = {
3999 .clock = 33260,
4000 .hdisplay = 800,
4001 .hsync_start = 800 + 64,
4002 .hsync_end = 800 + 64 + 128,
4003 .htotal = 800 + 64 + 128 + 64,
4004 .vdisplay = 480,
4005 .vsync_start = 480 + 8,
4006 .vsync_end = 480 + 8 + 2,
4007 .vtotal = 480 + 8 + 2 + 35,
4008 .flags = DISPLAY_FLAGS_PIXDATA_POSEDGE,
4009 };
4010
4011 static const struct panel_desc sharp_lq070y3dg3b = {
4012 .modes = &sharp_lq070y3dg3b_mode,
4013 .num_modes = 1,
4014 .bpc = 8,
4015 .size = {
4016 .width = 152, /* 152.4mm */
4017 .height = 91, /* 91.4mm */
4018 },
4019 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
4020 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE |
4021 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE,
4022 };
4023
4024 static const struct drm_display_mode sharp_lq035q7db03_mode = {
4025 .clock = 5500,
4026 .hdisplay = 240,
4027 .hsync_start = 240 + 16,
4028 .hsync_end = 240 + 16 + 7,
4029 .htotal = 240 + 16 + 7 + 5,
4030 .vdisplay = 320,
4031 .vsync_start = 320 + 9,
4032 .vsync_end = 320 + 9 + 1,
4033 .vtotal = 320 + 9 + 1 + 7,
4034 };
4035
4036 static const struct panel_desc sharp_lq035q7db03 = {
4037 .modes = &sharp_lq035q7db03_mode,
4038 .num_modes = 1,
4039 .bpc = 6,
4040 .size = {
4041 .width = 54,
4042 .height = 72,
4043 },
4044 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
4045 };
4046
4047 static const struct display_timing sharp_lq101k1ly04_timing = {
4048 .pixelclock = { 60000000, 65000000, 80000000 },
4049 .hactive = { 1280, 1280, 1280 },
4050 .hfront_porch = { 20, 20, 20 },
4051 .hback_porch = { 20, 20, 20 },
4052 .hsync_len = { 10, 10, 10 },
4053 .vactive = { 800, 800, 800 },
4054 .vfront_porch = { 4, 4, 4 },
4055 .vback_porch = { 4, 4, 4 },
4056 .vsync_len = { 4, 4, 4 },
4057 .flags = DISPLAY_FLAGS_PIXDATA_POSEDGE,
4058 };
4059
4060 static const struct panel_desc sharp_lq101k1ly04 = {
4061 .timings = &sharp_lq101k1ly04_timing,
4062 .num_timings = 1,
4063 .bpc = 8,
4064 .size = {
4065 .width = 217,
4066 .height = 136,
4067 },
4068 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA,
4069 .connector_type = DRM_MODE_CONNECTOR_LVDS,
4070 };
4071
4072 static const struct drm_display_mode sharp_ls020b1dd01d_modes[] = {
4073 { /* 50 Hz */
4074 .clock = 3000,
4075 .hdisplay = 240,
4076 .hsync_start = 240 + 58,
4077 .hsync_end = 240 + 58 + 1,
4078 .htotal = 240 + 58 + 1 + 1,
4079 .vdisplay = 160,
4080 .vsync_start = 160 + 24,
4081 .vsync_end = 160 + 24 + 10,
4082 .vtotal = 160 + 24 + 10 + 6,
4083 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC,
4084 },
4085 { /* 60 Hz */
4086 .clock = 3000,
4087 .hdisplay = 240,
4088 .hsync_start = 240 + 8,
4089 .hsync_end = 240 + 8 + 1,
4090 .htotal = 240 + 8 + 1 + 1,
4091 .vdisplay = 160,
4092 .vsync_start = 160 + 24,
4093 .vsync_end = 160 + 24 + 10,
4094 .vtotal = 160 + 24 + 10 + 6,
4095 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC,
4096 },
4097 };
4098
4099 static const struct panel_desc sharp_ls020b1dd01d = {
4100 .modes = sharp_ls020b1dd01d_modes,
4101 .num_modes = ARRAY_SIZE(sharp_ls020b1dd01d_modes),
4102 .bpc = 6,
4103 .size = {
4104 .width = 42,
4105 .height = 28,
4106 },
4107 .bus_format = MEDIA_BUS_FMT_RGB565_1X16,
4108 .bus_flags = DRM_BUS_FLAG_DE_HIGH
4109 | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE
4110 | DRM_BUS_FLAG_SHARP_SIGNALS,
4111 };
4112
4113 static const struct drm_display_mode shelly_sca07010_bfn_lnn_mode = {
4114 .clock = 33300,
4115 .hdisplay = 800,
4116 .hsync_start = 800 + 1,
4117 .hsync_end = 800 + 1 + 64,
4118 .htotal = 800 + 1 + 64 + 64,
4119 .vdisplay = 480,
4120 .vsync_start = 480 + 1,
4121 .vsync_end = 480 + 1 + 23,
4122 .vtotal = 480 + 1 + 23 + 22,
4123 };
4124
4125 static const struct panel_desc shelly_sca07010_bfn_lnn = {
4126 .modes = &shelly_sca07010_bfn_lnn_mode,
4127 .num_modes = 1,
4128 .size = {
4129 .width = 152,
4130 .height = 91,
4131 },
4132 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
4133 };
4134
4135 static const struct drm_display_mode starry_kr070pe2t_mode = {
4136 .clock = 33000,
4137 .hdisplay = 800,
4138 .hsync_start = 800 + 209,
4139 .hsync_end = 800 + 209 + 1,
4140 .htotal = 800 + 209 + 1 + 45,
4141 .vdisplay = 480,
4142 .vsync_start = 480 + 22,
4143 .vsync_end = 480 + 22 + 1,
4144 .vtotal = 480 + 22 + 1 + 22,
4145 };
4146
4147 static const struct panel_desc starry_kr070pe2t = {
4148 .modes = &starry_kr070pe2t_mode,
4149 .num_modes = 1,
4150 .bpc = 8,
4151 .size = {
4152 .width = 152,
4153 .height = 86,
4154 },
4155 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
4156 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE,
4157 .connector_type = DRM_MODE_CONNECTOR_DPI,
4158 };
4159
4160 static const struct display_timing startek_kd070wvfpa_mode = {
4161 .pixelclock = { 25200000, 27200000, 30500000 },
4162 .hactive = { 800, 800, 800 },
4163 .hfront_porch = { 19, 44, 115 },
4164 .hback_porch = { 5, 16, 101 },
4165 .hsync_len = { 1, 2, 100 },
4166 .vactive = { 480, 480, 480 },
4167 .vfront_porch = { 5, 43, 67 },
4168 .vback_porch = { 5, 5, 67 },
4169 .vsync_len = { 1, 2, 66 },
4170 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
4171 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE |
4172 DISPLAY_FLAGS_SYNC_POSEDGE,
4173 };
4174
4175 static const struct panel_desc startek_kd070wvfpa = {
4176 .timings = &startek_kd070wvfpa_mode,
4177 .num_timings = 1,
4178 .bpc = 8,
4179 .size = {
4180 .width = 152,
4181 .height = 91,
4182 },
4183 .delay = {
4184 .prepare = 20,
4185 .enable = 200,
4186 .disable = 200,
4187 },
4188 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
4189 .connector_type = DRM_MODE_CONNECTOR_DPI,
4190 .bus_flags = DRM_BUS_FLAG_DE_HIGH |
4191 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE |
4192 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE,
4193 };
4194
4195 static const struct display_timing tsd_tst043015cmhx_timing = {
4196 .pixelclock = { 5000000, 9000000, 12000000 },
4197 .hactive = { 480, 480, 480 },
4198 .hfront_porch = { 4, 5, 65 },
4199 .hback_porch = { 36, 40, 255 },
4200 .hsync_len = { 1, 1, 1 },
4201 .vactive = { 272, 272, 272 },
4202 .vfront_porch = { 2, 8, 97 },
4203 .vback_porch = { 3, 8, 31 },
4204 .vsync_len = { 1, 1, 1 },
4205
4206 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
4207 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE,
4208 };
4209
4210 static const struct panel_desc tsd_tst043015cmhx = {
4211 .timings = &tsd_tst043015cmhx_timing,
4212 .num_timings = 1,
4213 .bpc = 8,
4214 .size = {
4215 .width = 105,
4216 .height = 67,
4217 },
4218 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
4219 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
4220 };
4221
4222 static const struct drm_display_mode tfc_s9700rtwv43tr_01b_mode = {
4223 .clock = 30000,
4224 .hdisplay = 800,
4225 .hsync_start = 800 + 39,
4226 .hsync_end = 800 + 39 + 47,
4227 .htotal = 800 + 39 + 47 + 39,
4228 .vdisplay = 480,
4229 .vsync_start = 480 + 13,
4230 .vsync_end = 480 + 13 + 2,
4231 .vtotal = 480 + 13 + 2 + 29,
4232 };
4233
4234 static const struct panel_desc tfc_s9700rtwv43tr_01b = {
4235 .modes = &tfc_s9700rtwv43tr_01b_mode,
4236 .num_modes = 1,
4237 .bpc = 8,
4238 .size = {
4239 .width = 155,
4240 .height = 90,
4241 },
4242 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
4243 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
4244 };
4245
4246 static const struct display_timing tianma_tm070jdhg30_timing = {
4247 .pixelclock = { 62600000, 68200000, 78100000 },
4248 .hactive = { 1280, 1280, 1280 },
4249 .hfront_porch = { 15, 64, 159 },
4250 .hback_porch = { 5, 5, 5 },
4251 .hsync_len = { 1, 1, 256 },
4252 .vactive = { 800, 800, 800 },
4253 .vfront_porch = { 3, 40, 99 },
4254 .vback_porch = { 2, 2, 2 },
4255 .vsync_len = { 1, 1, 128 },
4256 .flags = DISPLAY_FLAGS_DE_HIGH,
4257 };
4258
4259 static const struct panel_desc tianma_tm070jdhg30 = {
4260 .timings = &tianma_tm070jdhg30_timing,
4261 .num_timings = 1,
4262 .bpc = 8,
4263 .size = {
4264 .width = 151,
4265 .height = 95,
4266 },
4267 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
4268 .connector_type = DRM_MODE_CONNECTOR_LVDS,
4269 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
4270 };
4271
4272 static const struct panel_desc tianma_tm070jvhg33 = {
4273 .timings = &tianma_tm070jdhg30_timing,
4274 .num_timings = 1,
4275 .bpc = 8,
4276 .size = {
4277 .width = 150,
4278 .height = 94,
4279 },
4280 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
4281 .connector_type = DRM_MODE_CONNECTOR_LVDS,
4282 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
4283 };
4284
4285 static const struct display_timing tianma_tm070rvhg71_timing = {
4286 .pixelclock = { 27700000, 29200000, 39600000 },
4287 .hactive = { 800, 800, 800 },
4288 .hfront_porch = { 12, 40, 212 },
4289 .hback_porch = { 88, 88, 88 },
4290 .hsync_len = { 1, 1, 40 },
4291 .vactive = { 480, 480, 480 },
4292 .vfront_porch = { 1, 13, 88 },
4293 .vback_porch = { 32, 32, 32 },
4294 .vsync_len = { 1, 1, 3 },
4295 .flags = DISPLAY_FLAGS_DE_HIGH,
4296 };
4297
4298 static const struct panel_desc tianma_tm070rvhg71 = {
4299 .timings = &tianma_tm070rvhg71_timing,
4300 .num_timings = 1,
4301 .bpc = 8,
4302 .size = {
4303 .width = 154,
4304 .height = 86,
4305 },
4306 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
4307 .connector_type = DRM_MODE_CONNECTOR_LVDS,
4308 };
4309
4310 static const struct drm_display_mode ti_nspire_cx_lcd_mode[] = {
4311 {
4312 .clock = 10000,
4313 .hdisplay = 320,
4314 .hsync_start = 320 + 50,
4315 .hsync_end = 320 + 50 + 6,
4316 .htotal = 320 + 50 + 6 + 38,
4317 .vdisplay = 240,
4318 .vsync_start = 240 + 3,
4319 .vsync_end = 240 + 3 + 1,
4320 .vtotal = 240 + 3 + 1 + 17,
4321 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
4322 },
4323 };
4324
4325 static const struct panel_desc ti_nspire_cx_lcd_panel = {
4326 .modes = ti_nspire_cx_lcd_mode,
4327 .num_modes = 1,
4328 .bpc = 8,
4329 .size = {
4330 .width = 65,
4331 .height = 49,
4332 },
4333 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
4334 .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE,
4335 };
4336
4337 static const struct drm_display_mode ti_nspire_classic_lcd_mode[] = {
4338 {
4339 .clock = 10000,
4340 .hdisplay = 320,
4341 .hsync_start = 320 + 6,
4342 .hsync_end = 320 + 6 + 6,
4343 .htotal = 320 + 6 + 6 + 6,
4344 .vdisplay = 240,
4345 .vsync_start = 240 + 0,
4346 .vsync_end = 240 + 0 + 1,
4347 .vtotal = 240 + 0 + 1 + 0,
4348 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
4349 },
4350 };
4351
4352 static const struct panel_desc ti_nspire_classic_lcd_panel = {
4353 .modes = ti_nspire_classic_lcd_mode,
4354 .num_modes = 1,
4355 /* The grayscale panel has 8 bit for the color .. Y (black) */
4356 .bpc = 8,
4357 .size = {
4358 .width = 71,
4359 .height = 53,
4360 },
4361 /* This is the grayscale bus format */
4362 .bus_format = MEDIA_BUS_FMT_Y8_1X8,
4363 .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
4364 };
4365
4366 static const struct drm_display_mode toshiba_lt089ac29000_mode = {
4367 .clock = 79500,
4368 .hdisplay = 1280,
4369 .hsync_start = 1280 + 192,
4370 .hsync_end = 1280 + 192 + 128,
4371 .htotal = 1280 + 192 + 128 + 64,
4372 .vdisplay = 768,
4373 .vsync_start = 768 + 20,
4374 .vsync_end = 768 + 20 + 7,
4375 .vtotal = 768 + 20 + 7 + 3,
4376 };
4377
4378 static const struct panel_desc toshiba_lt089ac29000 = {
4379 .modes = &toshiba_lt089ac29000_mode,
4380 .num_modes = 1,
4381 .size = {
4382 .width = 194,
4383 .height = 116,
4384 },
4385 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA,
4386 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
4387 .connector_type = DRM_MODE_CONNECTOR_LVDS,
4388 };
4389
4390 static const struct drm_display_mode tpk_f07a_0102_mode = {
4391 .clock = 33260,
4392 .hdisplay = 800,
4393 .hsync_start = 800 + 40,
4394 .hsync_end = 800 + 40 + 128,
4395 .htotal = 800 + 40 + 128 + 88,
4396 .vdisplay = 480,
4397 .vsync_start = 480 + 10,
4398 .vsync_end = 480 + 10 + 2,
4399 .vtotal = 480 + 10 + 2 + 33,
4400 };
4401
4402 static const struct panel_desc tpk_f07a_0102 = {
4403 .modes = &tpk_f07a_0102_mode,
4404 .num_modes = 1,
4405 .size = {
4406 .width = 152,
4407 .height = 91,
4408 },
4409 .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
4410 };
4411
4412 static const struct drm_display_mode tpk_f10a_0102_mode = {
4413 .clock = 45000,
4414 .hdisplay = 1024,
4415 .hsync_start = 1024 + 176,
4416 .hsync_end = 1024 + 176 + 5,
4417 .htotal = 1024 + 176 + 5 + 88,
4418 .vdisplay = 600,
4419 .vsync_start = 600 + 20,
4420 .vsync_end = 600 + 20 + 5,
4421 .vtotal = 600 + 20 + 5 + 25,
4422 };
4423
4424 static const struct panel_desc tpk_f10a_0102 = {
4425 .modes = &tpk_f10a_0102_mode,
4426 .num_modes = 1,
4427 .size = {
4428 .width = 223,
4429 .height = 125,
4430 },
4431 };
4432
4433 static const struct display_timing urt_umsh_8596md_timing = {
4434 .pixelclock = { 33260000, 33260000, 33260000 },
4435 .hactive = { 800, 800, 800 },
4436 .hfront_porch = { 41, 41, 41 },
4437 .hback_porch = { 216 - 128, 216 - 128, 216 - 128 },
4438 .hsync_len = { 71, 128, 128 },
4439 .vactive = { 480, 480, 480 },
4440 .vfront_porch = { 10, 10, 10 },
4441 .vback_porch = { 35 - 2, 35 - 2, 35 - 2 },
4442 .vsync_len = { 2, 2, 2 },
4443 .flags = DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_NEGEDGE |
4444 DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW,
4445 };
4446
4447 static const struct panel_desc urt_umsh_8596md_lvds = {
4448 .timings = &urt_umsh_8596md_timing,
4449 .num_timings = 1,
4450 .bpc = 6,
4451 .size = {
4452 .width = 152,
4453 .height = 91,
4454 },
4455 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
4456 .connector_type = DRM_MODE_CONNECTOR_LVDS,
4457 };
4458
4459 static const struct panel_desc urt_umsh_8596md_parallel = {
4460 .timings = &urt_umsh_8596md_timing,
4461 .num_timings = 1,
4462 .bpc = 6,
4463 .size = {
4464 .width = 152,
4465 .height = 91,
4466 },
4467 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
4468 };
4469
4470 static const struct drm_display_mode vivax_tpc9150_panel_mode = {
4471 .clock = 60000,
4472 .hdisplay = 1024,
4473 .hsync_start = 1024 + 160,
4474 .hsync_end = 1024 + 160 + 100,
4475 .htotal = 1024 + 160 + 100 + 60,
4476 .vdisplay = 600,
4477 .vsync_start = 600 + 12,
4478 .vsync_end = 600 + 12 + 10,
4479 .vtotal = 600 + 12 + 10 + 13,
4480 };
4481
4482 static const struct panel_desc vivax_tpc9150_panel = {
4483 .modes = &vivax_tpc9150_panel_mode,
4484 .num_modes = 1,
4485 .bpc = 6,
4486 .size = {
4487 .width = 200,
4488 .height = 115,
4489 },
4490 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
4491 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
4492 .connector_type = DRM_MODE_CONNECTOR_LVDS,
4493 };
4494
4495 static const struct drm_display_mode vl050_8048nt_c01_mode = {
4496 .clock = 33333,
4497 .hdisplay = 800,
4498 .hsync_start = 800 + 210,
4499 .hsync_end = 800 + 210 + 20,
4500 .htotal = 800 + 210 + 20 + 46,
4501 .vdisplay = 480,
4502 .vsync_start = 480 + 22,
4503 .vsync_end = 480 + 22 + 10,
4504 .vtotal = 480 + 22 + 10 + 23,
4505 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
4506 };
4507
4508 static const struct panel_desc vl050_8048nt_c01 = {
4509 .modes = &vl050_8048nt_c01_mode,
4510 .num_modes = 1,
4511 .bpc = 8,
4512 .size = {
4513 .width = 120,
4514 .height = 76,
4515 },
4516 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
4517 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
4518 };
4519
4520 static const struct drm_display_mode winstar_wf35ltiacd_mode = {
4521 .clock = 6410,
4522 .hdisplay = 320,
4523 .hsync_start = 320 + 20,
4524 .hsync_end = 320 + 20 + 30,
4525 .htotal = 320 + 20 + 30 + 38,
4526 .vdisplay = 240,
4527 .vsync_start = 240 + 4,
4528 .vsync_end = 240 + 4 + 3,
4529 .vtotal = 240 + 4 + 3 + 15,
4530 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
4531 };
4532
4533 static const struct panel_desc winstar_wf35ltiacd = {
4534 .modes = &winstar_wf35ltiacd_mode,
4535 .num_modes = 1,
4536 .bpc = 8,
4537 .size = {
4538 .width = 70,
4539 .height = 53,
4540 },
4541 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
4542 };
4543
4544 static const struct drm_display_mode yes_optoelectronics_ytc700tlag_05_201c_mode = {
4545 .clock = 51200,
4546 .hdisplay = 1024,
4547 .hsync_start = 1024 + 100,
4548 .hsync_end = 1024 + 100 + 100,
4549 .htotal = 1024 + 100 + 100 + 120,
4550 .vdisplay = 600,
4551 .vsync_start = 600 + 10,
4552 .vsync_end = 600 + 10 + 10,
4553 .vtotal = 600 + 10 + 10 + 15,
4554 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
4555 };
4556
4557 static const struct panel_desc yes_optoelectronics_ytc700tlag_05_201c = {
4558 .modes = &yes_optoelectronics_ytc700tlag_05_201c_mode,
4559 .num_modes = 1,
4560 .bpc = 8,
4561 .size = {
4562 .width = 154,
4563 .height = 90,
4564 },
4565 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
4566 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
4567 .connector_type = DRM_MODE_CONNECTOR_LVDS,
4568 };
4569
4570 static const struct drm_display_mode mchp_ac69t88a_mode = {
4571 .clock = 25000,
4572 .hdisplay = 800,
4573 .hsync_start = 800 + 88,
4574 .hsync_end = 800 + 88 + 5,
4575 .htotal = 800 + 88 + 5 + 40,
4576 .vdisplay = 480,
4577 .vsync_start = 480 + 23,
4578 .vsync_end = 480 + 23 + 5,
4579 .vtotal = 480 + 23 + 5 + 1,
4580 };
4581
4582 static const struct panel_desc mchp_ac69t88a = {
4583 .modes = &mchp_ac69t88a_mode,
4584 .num_modes = 1,
4585 .bpc = 8,
4586 .size = {
4587 .width = 108,
4588 .height = 65,
4589 },
4590 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
4591 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA,
4592 .connector_type = DRM_MODE_CONNECTOR_LVDS,
4593 };
4594
4595 static const struct drm_display_mode arm_rtsm_mode[] = {
4596 {
4597 .clock = 65000,
4598 .hdisplay = 1024,
4599 .hsync_start = 1024 + 24,
4600 .hsync_end = 1024 + 24 + 136,
4601 .htotal = 1024 + 24 + 136 + 160,
4602 .vdisplay = 768,
4603 .vsync_start = 768 + 3,
4604 .vsync_end = 768 + 3 + 6,
4605 .vtotal = 768 + 3 + 6 + 29,
4606 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
4607 },
4608 };
4609
4610 static const struct panel_desc arm_rtsm = {
4611 .modes = arm_rtsm_mode,
4612 .num_modes = 1,
4613 .bpc = 8,
4614 .size = {
4615 .width = 400,
4616 .height = 300,
4617 },
4618 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
4619 };
4620
4621 static const struct of_device_id platform_of_match[] = {
4622 {
4623 .compatible = "ampire,am-1280800n3tzqw-t00h",
4624 .data = &ire_am_1280800n3tzqw_t00h,
4625 }, {
4626 .compatible = "ampire,am-480272h3tmqw-t01h",
4627 .data = &ire_am_480272h3tmqw_t01h,
4628 }, {
4629 .compatible = "ampire,am-800480l1tmqw-t00h",
4630 .data = &ire_am_800480l1tmqw_t00h,
4631 }, {
4632 .compatible = "ampire,am800480r3tmqwa1h",
4633 .data = &ire_am800480r3tmqwa1h,
4634 }, {
4635 .compatible = "ampire,am800600p5tmqw-tb8h",
4636 .data = &ire_am800600p5tmqwtb8h,
4637 }, {
4638 .compatible = "arm,rtsm-display",
4639 .data = &arm_rtsm,
4640 }, {
4641 .compatible = "armadeus,st0700-adapt",
4642 .data = &armadeus_st0700_adapt,
4643 }, {
4644 .compatible = "auo,b101aw03",
4645 .data = &auo_b101aw03,
4646 }, {
4647 .compatible = "auo,b101xtn01",
4648 .data = &auo_b101xtn01,
4649 }, {
4650 .compatible = "auo,b116xw03",
4651 .data = &auo_b116xw03,
4652 }, {
4653 .compatible = "auo,g070vvn01",
4654 .data = &auo_g070vvn01,
4655 }, {
4656 .compatible = "auo,g101evn010",
4657 .data = &auo_g101evn010,
4658 }, {
4659 .compatible = "auo,g104sn02",
4660 .data = &auo_g104sn02,
4661 }, {
4662 .compatible = "auo,g104stn01",
4663 .data = &auo_g104stn01,
4664 }, {
4665 .compatible = "auo,g121ean01",
4666 .data = &auo_g121ean01,
4667 }, {
4668 .compatible = "auo,g133han01",
4669 .data = &auo_g133han01,
4670 }, {
4671 .compatible = "auo,g156han04",
4672 .data = &auo_g156han04,
4673 }, {
4674 .compatible = "auo,g156xtn01",
4675 .data = &auo_g156xtn01,
4676 }, {
4677 .compatible = "auo,g185han01",
4678 .data = &auo_g185han01,
4679 }, {
4680 .compatible = "auo,g190ean01",
4681 .data = &auo_g190ean01,
4682 }, {
4683 .compatible = "auo,p320hvn03",
4684 .data = &auo_p320hvn03,
4685 }, {
4686 .compatible = "auo,t215hvn01",
4687 .data = &auo_t215hvn01,
4688 }, {
4689 .compatible = "avic,tm070ddh03",
4690 .data = &avic_tm070ddh03,
4691 }, {
4692 .compatible = "bananapi,s070wv20-ct16",
4693 .data = &bananapi_s070wv20_ct16,
4694 }, {
4695 .compatible = "boe,bp082wx1-100",
4696 .data = &boe_bp082wx1_100,
4697 }, {
4698 .compatible = "boe,bp101wx1-100",
4699 .data = &boe_bp101wx1_100,
4700 }, {
4701 .compatible = "boe,ev121wxm-n10-1850",
4702 .data = &boe_ev121wxm_n10_1850,
4703 }, {
4704 .compatible = "boe,hv070wsa-100",
4705 .data = &boe_hv070wsa
4706 }, {
4707 .compatible = "cct,cmt430b19n00",
4708 .data = &cct_cmt430b19n00,
4709 }, {
4710 .compatible = "cdtech,s043wq26h-ct7",
4711 .data = &cdtech_s043wq26h_ct7,
4712 }, {
4713 .compatible = "cdtech,s070pws19hp-fc21",
4714 .data = &cdtech_s070pws19hp_fc21,
4715 }, {
4716 .compatible = "cdtech,s070swv29hg-dc44",
4717 .data = &cdtech_s070swv29hg_dc44,
4718 }, {
4719 .compatible = "cdtech,s070wv95-ct16",
4720 .data = &cdtech_s070wv95_ct16,
4721 }, {
4722 .compatible = "chefree,ch101olhlwh-002",
4723 .data = &chefree_ch101olhlwh_002,
4724 }, {
4725 .compatible = "chunghwa,claa070wp03xg",
4726 .data = &chunghwa_claa070wp03xg,
4727 }, {
4728 .compatible = "chunghwa,claa101wa01a",
4729 .data = &chunghwa_claa101wa01a
4730 }, {
4731 .compatible = "chunghwa,claa101wb01",
4732 .data = &chunghwa_claa101wb01
4733 }, {
4734 .compatible = "dataimage,fg040346dsswbg04",
4735 .data = &dataimage_fg040346dsswbg04,
4736 }, {
4737 .compatible = "dataimage,fg1001l0dsswmg01",
4738 .data = &dataimage_fg1001l0dsswmg01,
4739 }, {
4740 .compatible = "dataimage,scf0700c48ggu18",
4741 .data = &dataimage_scf0700c48ggu18,
4742 }, {
4743 .compatible = "dlc,dlc0700yzg-1",
4744 .data = &dlc_dlc0700yzg_1,
4745 }, {
4746 .compatible = "dlc,dlc1010gig",
4747 .data = &dlc_dlc1010gig,
4748 }, {
4749 .compatible = "edt,et035012dm6",
4750 .data = &edt_et035012dm6,
4751 }, {
4752 .compatible = "edt,etm0350g0dh6",
4753 .data = &edt_etm0350g0dh6,
4754 }, {
4755 .compatible = "edt,etm043080dh6gp",
4756 .data = &edt_etm043080dh6gp,
4757 }, {
4758 .compatible = "edt,etm0430g0dh6",
4759 .data = &edt_etm0430g0dh6,
4760 }, {
4761 .compatible = "edt,et057090dhu",
4762 .data = &edt_et057090dhu,
4763 }, {
4764 .compatible = "edt,et070080dh6",
4765 .data = &edt_etm0700g0dh6,
4766 }, {
4767 .compatible = "edt,etm0700g0dh6",
4768 .data = &edt_etm0700g0dh6,
4769 }, {
4770 .compatible = "edt,etm0700g0bdh6",
4771 .data = &edt_etm0700g0bdh6,
4772 }, {
4773 .compatible = "edt,etm0700g0edh6",
4774 .data = &edt_etm0700g0bdh6,
4775 }, {
4776 .compatible = "edt,etml0700y5dha",
4777 .data = &edt_etml0700y5dha,
4778 }, {
4779 .compatible = "edt,etml1010g3dra",
4780 .data = &edt_etml1010g3dra,
4781 }, {
4782 .compatible = "edt,etmv570g2dhu",
4783 .data = &edt_etmv570g2dhu,
4784 }, {
4785 .compatible = "eink,vb3300-kca",
4786 .data = &eink_vb3300_kca,
4787 }, {
4788 .compatible = "evervision,vgg644804",
4789 .data = &evervision_vgg644804,
4790 }, {
4791 .compatible = "evervision,vgg804821",
4792 .data = &evervision_vgg804821,
4793 }, {
4794 .compatible = "foxlink,fl500wvr00-a0t",
4795 .data = &foxlink_fl500wvr00_a0t,
4796 }, {
4797 .compatible = "frida,frd350h54004",
4798 .data = &frida_frd350h54004,
4799 }, {
4800 .compatible = "friendlyarm,hd702e",
4801 .data = &friendlyarm_hd702e,
4802 }, {
4803 .compatible = "giantplus,gpg482739qs5",
4804 .data = &giantplus_gpg482739qs5
4805 }, {
4806 .compatible = "giantplus,gpm940b0",
4807 .data = &giantplus_gpm940b0,
4808 }, {
4809 .compatible = "hannstar,hsd070pww1",
4810 .data = &hannstar_hsd070pww1,
4811 }, {
4812 .compatible = "hannstar,hsd100pxn1",
4813 .data = &hannstar_hsd100pxn1,
4814 }, {
4815 .compatible = "hannstar,hsd101pww2",
4816 .data = &hannstar_hsd101pww2,
4817 }, {
4818 .compatible = "hit,tx23d38vm0caa",
4819 .data = &hitachi_tx23d38vm0caa
4820 }, {
4821 .compatible = "innolux,at043tn24",
4822 .data = &innolux_at043tn24,
4823 }, {
4824 .compatible = "innolux,at070tn92",
4825 .data = &innolux_at070tn92,
4826 }, {
4827 .compatible = "innolux,g070ace-l01",
4828 .data = &innolux_g070ace_l01,
4829 }, {
4830 .compatible = "innolux,g070ace-lh3",
4831 .data = &innolux_g070ace_lh3,
4832 }, {
4833 .compatible = "innolux,g070y2-l01",
4834 .data = &innolux_g070y2_l01,
4835 }, {
4836 .compatible = "innolux,g070y2-t02",
4837 .data = &innolux_g070y2_t02,
4838 }, {
4839 .compatible = "innolux,g101ice-l01",
4840 .data = &innolux_g101ice_l01
4841 }, {
4842 .compatible = "innolux,g121i1-l01",
4843 .data = &innolux_g121i1_l01
4844 }, {
4845 .compatible = "innolux,g121x1-l03",
4846 .data = &innolux_g121x1_l03,
4847 }, {
4848 .compatible = "innolux,g121xce-l01",
4849 .data = &innolux_g121xce_l01,
4850 }, {
4851 .compatible = "innolux,g156hce-l01",
4852 .data = &innolux_g156hce_l01,
4853 }, {
4854 .compatible = "innolux,n156bge-l21",
4855 .data = &innolux_n156bge_l21,
4856 }, {
4857 .compatible = "innolux,zj070na-01p",
4858 .data = &innolux_zj070na_01p,
4859 }, {
4860 .compatible = "koe,tx14d24vm1bpa",
4861 .data = &koe_tx14d24vm1bpa,
4862 }, {
4863 .compatible = "koe,tx26d202vm0bwa",
4864 .data = &koe_tx26d202vm0bwa,
4865 }, {
4866 .compatible = "koe,tx31d200vm0baa",
4867 .data = &koe_tx31d200vm0baa,
4868 }, {
4869 .compatible = "kyo,tcg121xglp",
4870 .data = &kyo_tcg121xglp,
4871 }, {
4872 .compatible = "lemaker,bl035-rgb-002",
4873 .data = &lemaker_bl035_rgb_002,
4874 }, {
4875 .compatible = "lg,lb070wv8",
4876 .data = &lg_lb070wv8,
4877 }, {
4878 .compatible = "lincolntech,lcd185-101ct",
4879 .data = &lincolntech_lcd185_101ct,
4880 }, {
4881 .compatible = "logicpd,type28",
4882 .data = &logicpd_type_28,
4883 }, {
4884 .compatible = "logictechno,lt161010-2nhc",
4885 .data = &logictechno_lt161010_2nh,
4886 }, {
4887 .compatible = "logictechno,lt161010-2nhr",
4888 .data = &logictechno_lt161010_2nh,
4889 }, {
4890 .compatible = "logictechno,lt170410-2whc",
4891 .data = &logictechno_lt170410_2whc,
4892 }, {
4893 .compatible = "logictechno,lttd800480070-l2rt",
4894 .data = &logictechno_lttd800480070_l2rt,
4895 }, {
4896 .compatible = "logictechno,lttd800480070-l6wh-rt",
4897 .data = &logictechno_lttd800480070_l6wh_rt,
4898 }, {
4899 .compatible = "microtips,mf-101hiebcaf0",
4900 .data = µtips_mf_101hiebcaf0_c,
4901 }, {
4902 .compatible = "microtips,mf-103hieb0ga0",
4903 .data = µtips_mf_103hieb0ga0,
4904 }, {
4905 .compatible = "mitsubishi,aa070mc01-ca1",
4906 .data = &mitsubishi_aa070mc01,
4907 }, {
4908 .compatible = "mitsubishi,aa084xe01",
4909 .data = &mitsubishi_aa084xe01,
4910 }, {
4911 .compatible = "multi-inno,mi0700s4t-6",
4912 .data = &multi_inno_mi0700s4t_6,
4913 }, {
4914 .compatible = "multi-inno,mi0800ft-9",
4915 .data = &multi_inno_mi0800ft_9,
4916 }, {
4917 .compatible = "multi-inno,mi1010ait-1cp",
4918 .data = &multi_inno_mi1010ait_1cp,
4919 }, {
4920 .compatible = "nec,nl12880bc20-05",
4921 .data = &nec_nl12880bc20_05,
4922 }, {
4923 .compatible = "nec,nl4827hc19-05b",
4924 .data = &nec_nl4827hc19_05b,
4925 }, {
4926 .compatible = "netron-dy,e231732",
4927 .data = &netron_dy_e231732,
4928 }, {
4929 .compatible = "newhaven,nhd-4.3-480272ef-atxl",
4930 .data = &newhaven_nhd_43_480272ef_atxl,
4931 }, {
4932 .compatible = "nlt,nl192108ac18-02d",
4933 .data = &nlt_nl192108ac18_02d,
4934 }, {
4935 .compatible = "nvd,9128",
4936 .data = &nvd_9128,
4937 }, {
4938 .compatible = "okaya,rs800480t-7x0gp",
4939 .data = &okaya_rs800480t_7x0gp,
4940 }, {
4941 .compatible = "olimex,lcd-olinuxino-43-ts",
4942 .data = &olimex_lcd_olinuxino_43ts,
4943 }, {
4944 .compatible = "ontat,kd50g21-40nt-a1",
4945 .data = &ontat_kd50g21_40nt_a1,
4946 }, {
4947 .compatible = "ontat,yx700wv03",
4948 .data = &ontat_yx700wv03,
4949 }, {
4950 .compatible = "ortustech,com37h3m05dtc",
4951 .data = &ortustech_com37h3m,
4952 }, {
4953 .compatible = "ortustech,com37h3m99dtc",
4954 .data = &ortustech_com37h3m,
4955 }, {
4956 .compatible = "ortustech,com43h4m85ulc",
4957 .data = &ortustech_com43h4m85ulc,
4958 }, {
4959 .compatible = "osddisplays,osd070t1718-19ts",
4960 .data = &osddisplays_osd070t1718_19ts,
4961 }, {
4962 .compatible = "pda,91-00156-a0",
4963 .data = &pda_91_00156_a0,
4964 }, {
4965 .compatible = "powertip,ph128800t006-zhc01",
4966 .data = &powertip_ph128800t006_zhc01,
4967 }, {
4968 .compatible = "powertip,ph800480t013-idf02",
4969 .data = &powertip_ph800480t013_idf02,
4970 }, {
4971 .compatible = "primeview,pm070wl4",
4972 .data = &primeview_pm070wl4,
4973 }, {
4974 .compatible = "qiaodian,qd43003c0-40",
4975 .data = &qd43003c0_40,
4976 }, {
4977 .compatible = "qishenglong,gopher2b-lcd",
4978 .data = &qishenglong_gopher2b_lcd,
4979 }, {
4980 .compatible = "rocktech,rk043fn48h",
4981 .data = &rocktech_rk043fn48h,
4982 }, {
4983 .compatible = "rocktech,rk070er9427",
4984 .data = &rocktech_rk070er9427,
4985 }, {
4986 .compatible = "rocktech,rk101ii01d-ct",
4987 .data = &rocktech_rk101ii01d_ct,
4988 }, {
4989 .compatible = "samsung,ltl101al01",
4990 .data = &samsung_ltl101al01,
4991 }, {
4992 .compatible = "samsung,ltn101nt05",
4993 .data = &samsung_ltn101nt05,
4994 }, {
4995 .compatible = "satoz,sat050at40h12r2",
4996 .data = &satoz_sat050at40h12r2,
4997 }, {
4998 .compatible = "sharp,lq035q7db03",
4999 .data = &sharp_lq035q7db03,
5000 }, {
5001 .compatible = "sharp,lq070y3dg3b",
5002 .data = &sharp_lq070y3dg3b,
5003 }, {
5004 .compatible = "sharp,lq101k1ly04",
5005 .data = &sharp_lq101k1ly04,
5006 }, {
5007 .compatible = "sharp,ls020b1dd01d",
5008 .data = &sharp_ls020b1dd01d,
5009 }, {
5010 .compatible = "shelly,sca07010-bfn-lnn",
5011 .data = &shelly_sca07010_bfn_lnn,
5012 }, {
5013 .compatible = "starry,kr070pe2t",
5014 .data = &starry_kr070pe2t,
5015 }, {
5016 .compatible = "startek,kd070wvfpa",
5017 .data = &startek_kd070wvfpa,
5018 }, {
5019 .compatible = "team-source-display,tst043015cmhx",
5020 .data = &tsd_tst043015cmhx,
5021 }, {
5022 .compatible = "tfc,s9700rtwv43tr-01b",
5023 .data = &tfc_s9700rtwv43tr_01b,
5024 }, {
5025 .compatible = "tianma,tm070jdhg30",
5026 .data = &tianma_tm070jdhg30,
5027 }, {
5028 .compatible = "tianma,tm070jvhg33",
5029 .data = &tianma_tm070jvhg33,
5030 }, {
5031 .compatible = "tianma,tm070rvhg71",
5032 .data = &tianma_tm070rvhg71,
5033 }, {
5034 .compatible = "ti,nspire-cx-lcd-panel",
5035 .data = &ti_nspire_cx_lcd_panel,
5036 }, {
5037 .compatible = "ti,nspire-classic-lcd-panel",
5038 .data = &ti_nspire_classic_lcd_panel,
5039 }, {
5040 .compatible = "toshiba,lt089ac29000",
5041 .data = &toshiba_lt089ac29000,
5042 }, {
5043 .compatible = "tpk,f07a-0102",
5044 .data = &tpk_f07a_0102,
5045 }, {
5046 .compatible = "tpk,f10a-0102",
5047 .data = &tpk_f10a_0102,
5048 }, {
5049 .compatible = "urt,umsh-8596md-t",
5050 .data = &urt_umsh_8596md_parallel,
5051 }, {
5052 .compatible = "urt,umsh-8596md-1t",
5053 .data = &urt_umsh_8596md_parallel,
5054 }, {
5055 .compatible = "urt,umsh-8596md-7t",
5056 .data = &urt_umsh_8596md_parallel,
5057 }, {
5058 .compatible = "urt,umsh-8596md-11t",
5059 .data = &urt_umsh_8596md_lvds,
5060 }, {
5061 .compatible = "urt,umsh-8596md-19t",
5062 .data = &urt_umsh_8596md_lvds,
5063 }, {
5064 .compatible = "urt,umsh-8596md-20t",
5065 .data = &urt_umsh_8596md_parallel,
5066 }, {
5067 .compatible = "vivax,tpc9150-panel",
5068 .data = &vivax_tpc9150_panel,
5069 }, {
5070 .compatible = "vxt,vl050-8048nt-c01",
5071 .data = &vl050_8048nt_c01,
5072 }, {
5073 .compatible = "winstar,wf35ltiacd",
5074 .data = &winstar_wf35ltiacd,
5075 }, {
5076 .compatible = "yes-optoelectronics,ytc700tlag-05-201c",
5077 .data = &yes_optoelectronics_ytc700tlag_05_201c,
5078 }, {
5079 .compatible = "microchip,ac69t88a",
5080 .data = &mchp_ac69t88a,
5081 }, {
5082 /* Must be the last entry */
5083 .compatible = "panel-dpi",
5084 .data = &panel_dpi,
5085 }, {
5086 /* sentinel */
5087 }
5088 };
5089 MODULE_DEVICE_TABLE(of, platform_of_match);
5090
panel_simple_platform_probe(struct platform_device * pdev)5091 static int panel_simple_platform_probe(struct platform_device *pdev)
5092 {
5093 const struct panel_desc *desc;
5094
5095 desc = of_device_get_match_data(&pdev->dev);
5096 if (!desc)
5097 return -ENODEV;
5098
5099 return panel_simple_probe(&pdev->dev, desc);
5100 }
5101
panel_simple_platform_remove(struct platform_device * pdev)5102 static void panel_simple_platform_remove(struct platform_device *pdev)
5103 {
5104 panel_simple_remove(&pdev->dev);
5105 }
5106
panel_simple_platform_shutdown(struct platform_device * pdev)5107 static void panel_simple_platform_shutdown(struct platform_device *pdev)
5108 {
5109 panel_simple_shutdown(&pdev->dev);
5110 }
5111
5112 static const struct dev_pm_ops panel_simple_pm_ops = {
5113 SET_RUNTIME_PM_OPS(panel_simple_suspend, panel_simple_resume, NULL)
5114 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
5115 pm_runtime_force_resume)
5116 };
5117
5118 static struct platform_driver panel_simple_platform_driver = {
5119 .driver = {
5120 .name = "panel-simple",
5121 .of_match_table = platform_of_match,
5122 .pm = &panel_simple_pm_ops,
5123 },
5124 .probe = panel_simple_platform_probe,
5125 .remove_new = panel_simple_platform_remove,
5126 .shutdown = panel_simple_platform_shutdown,
5127 };
5128
5129 struct panel_desc_dsi {
5130 struct panel_desc desc;
5131
5132 unsigned long flags;
5133 enum mipi_dsi_pixel_format format;
5134 unsigned int lanes;
5135 };
5136
5137 static const struct drm_display_mode auo_b080uan01_mode = {
5138 .clock = 154500,
5139 .hdisplay = 1200,
5140 .hsync_start = 1200 + 62,
5141 .hsync_end = 1200 + 62 + 4,
5142 .htotal = 1200 + 62 + 4 + 62,
5143 .vdisplay = 1920,
5144 .vsync_start = 1920 + 9,
5145 .vsync_end = 1920 + 9 + 2,
5146 .vtotal = 1920 + 9 + 2 + 8,
5147 };
5148
5149 static const struct panel_desc_dsi auo_b080uan01 = {
5150 .desc = {
5151 .modes = &auo_b080uan01_mode,
5152 .num_modes = 1,
5153 .bpc = 8,
5154 .size = {
5155 .width = 108,
5156 .height = 272,
5157 },
5158 .connector_type = DRM_MODE_CONNECTOR_DSI,
5159 },
5160 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_CLOCK_NON_CONTINUOUS,
5161 .format = MIPI_DSI_FMT_RGB888,
5162 .lanes = 4,
5163 };
5164
5165 static const struct drm_display_mode boe_tv080wum_nl0_mode = {
5166 .clock = 160000,
5167 .hdisplay = 1200,
5168 .hsync_start = 1200 + 120,
5169 .hsync_end = 1200 + 120 + 20,
5170 .htotal = 1200 + 120 + 20 + 21,
5171 .vdisplay = 1920,
5172 .vsync_start = 1920 + 21,
5173 .vsync_end = 1920 + 21 + 3,
5174 .vtotal = 1920 + 21 + 3 + 18,
5175 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
5176 };
5177
5178 static const struct panel_desc_dsi boe_tv080wum_nl0 = {
5179 .desc = {
5180 .modes = &boe_tv080wum_nl0_mode,
5181 .num_modes = 1,
5182 .size = {
5183 .width = 107,
5184 .height = 172,
5185 },
5186 .connector_type = DRM_MODE_CONNECTOR_DSI,
5187 },
5188 .flags = MIPI_DSI_MODE_VIDEO |
5189 MIPI_DSI_MODE_VIDEO_BURST |
5190 MIPI_DSI_MODE_VIDEO_SYNC_PULSE,
5191 .format = MIPI_DSI_FMT_RGB888,
5192 .lanes = 4,
5193 };
5194
5195 static const struct drm_display_mode lg_ld070wx3_sl01_mode = {
5196 .clock = 71000,
5197 .hdisplay = 800,
5198 .hsync_start = 800 + 32,
5199 .hsync_end = 800 + 32 + 1,
5200 .htotal = 800 + 32 + 1 + 57,
5201 .vdisplay = 1280,
5202 .vsync_start = 1280 + 28,
5203 .vsync_end = 1280 + 28 + 1,
5204 .vtotal = 1280 + 28 + 1 + 14,
5205 };
5206
5207 static const struct panel_desc_dsi lg_ld070wx3_sl01 = {
5208 .desc = {
5209 .modes = &lg_ld070wx3_sl01_mode,
5210 .num_modes = 1,
5211 .bpc = 8,
5212 .size = {
5213 .width = 94,
5214 .height = 151,
5215 },
5216 .connector_type = DRM_MODE_CONNECTOR_DSI,
5217 },
5218 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_CLOCK_NON_CONTINUOUS,
5219 .format = MIPI_DSI_FMT_RGB888,
5220 .lanes = 4,
5221 };
5222
5223 static const struct drm_display_mode lg_lh500wx1_sd03_mode = {
5224 .clock = 67000,
5225 .hdisplay = 720,
5226 .hsync_start = 720 + 12,
5227 .hsync_end = 720 + 12 + 4,
5228 .htotal = 720 + 12 + 4 + 112,
5229 .vdisplay = 1280,
5230 .vsync_start = 1280 + 8,
5231 .vsync_end = 1280 + 8 + 4,
5232 .vtotal = 1280 + 8 + 4 + 12,
5233 };
5234
5235 static const struct panel_desc_dsi lg_lh500wx1_sd03 = {
5236 .desc = {
5237 .modes = &lg_lh500wx1_sd03_mode,
5238 .num_modes = 1,
5239 .bpc = 8,
5240 .size = {
5241 .width = 62,
5242 .height = 110,
5243 },
5244 .connector_type = DRM_MODE_CONNECTOR_DSI,
5245 },
5246 .flags = MIPI_DSI_MODE_VIDEO,
5247 .format = MIPI_DSI_FMT_RGB888,
5248 .lanes = 4,
5249 };
5250
5251 static const struct drm_display_mode panasonic_vvx10f004b00_mode = {
5252 .clock = 157200,
5253 .hdisplay = 1920,
5254 .hsync_start = 1920 + 154,
5255 .hsync_end = 1920 + 154 + 16,
5256 .htotal = 1920 + 154 + 16 + 32,
5257 .vdisplay = 1200,
5258 .vsync_start = 1200 + 17,
5259 .vsync_end = 1200 + 17 + 2,
5260 .vtotal = 1200 + 17 + 2 + 16,
5261 };
5262
5263 static const struct panel_desc_dsi panasonic_vvx10f004b00 = {
5264 .desc = {
5265 .modes = &panasonic_vvx10f004b00_mode,
5266 .num_modes = 1,
5267 .bpc = 8,
5268 .size = {
5269 .width = 217,
5270 .height = 136,
5271 },
5272 .connector_type = DRM_MODE_CONNECTOR_DSI,
5273 },
5274 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE |
5275 MIPI_DSI_CLOCK_NON_CONTINUOUS,
5276 .format = MIPI_DSI_FMT_RGB888,
5277 .lanes = 4,
5278 };
5279
5280 static const struct drm_display_mode lg_acx467akm_7_mode = {
5281 .clock = 150000,
5282 .hdisplay = 1080,
5283 .hsync_start = 1080 + 2,
5284 .hsync_end = 1080 + 2 + 2,
5285 .htotal = 1080 + 2 + 2 + 2,
5286 .vdisplay = 1920,
5287 .vsync_start = 1920 + 2,
5288 .vsync_end = 1920 + 2 + 2,
5289 .vtotal = 1920 + 2 + 2 + 2,
5290 };
5291
5292 static const struct panel_desc_dsi lg_acx467akm_7 = {
5293 .desc = {
5294 .modes = &lg_acx467akm_7_mode,
5295 .num_modes = 1,
5296 .bpc = 8,
5297 .size = {
5298 .width = 62,
5299 .height = 110,
5300 },
5301 .connector_type = DRM_MODE_CONNECTOR_DSI,
5302 },
5303 .flags = 0,
5304 .format = MIPI_DSI_FMT_RGB888,
5305 .lanes = 4,
5306 };
5307
5308 static const struct drm_display_mode osd101t2045_53ts_mode = {
5309 .clock = 154500,
5310 .hdisplay = 1920,
5311 .hsync_start = 1920 + 112,
5312 .hsync_end = 1920 + 112 + 16,
5313 .htotal = 1920 + 112 + 16 + 32,
5314 .vdisplay = 1200,
5315 .vsync_start = 1200 + 16,
5316 .vsync_end = 1200 + 16 + 2,
5317 .vtotal = 1200 + 16 + 2 + 16,
5318 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
5319 };
5320
5321 static const struct panel_desc_dsi osd101t2045_53ts = {
5322 .desc = {
5323 .modes = &osd101t2045_53ts_mode,
5324 .num_modes = 1,
5325 .bpc = 8,
5326 .size = {
5327 .width = 217,
5328 .height = 136,
5329 },
5330 .connector_type = DRM_MODE_CONNECTOR_DSI,
5331 },
5332 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST |
5333 MIPI_DSI_MODE_VIDEO_SYNC_PULSE |
5334 MIPI_DSI_MODE_NO_EOT_PACKET,
5335 .format = MIPI_DSI_FMT_RGB888,
5336 .lanes = 4,
5337 };
5338
5339 static const struct of_device_id dsi_of_match[] = {
5340 {
5341 .compatible = "auo,b080uan01",
5342 .data = &auo_b080uan01
5343 }, {
5344 .compatible = "boe,tv080wum-nl0",
5345 .data = &boe_tv080wum_nl0
5346 }, {
5347 .compatible = "lg,ld070wx3-sl01",
5348 .data = &lg_ld070wx3_sl01
5349 }, {
5350 .compatible = "lg,lh500wx1-sd03",
5351 .data = &lg_lh500wx1_sd03
5352 }, {
5353 .compatible = "panasonic,vvx10f004b00",
5354 .data = &panasonic_vvx10f004b00
5355 }, {
5356 .compatible = "lg,acx467akm-7",
5357 .data = &lg_acx467akm_7
5358 }, {
5359 .compatible = "osddisplays,osd101t2045-53ts",
5360 .data = &osd101t2045_53ts
5361 }, {
5362 /* sentinel */
5363 }
5364 };
5365 MODULE_DEVICE_TABLE(of, dsi_of_match);
5366
panel_simple_dsi_probe(struct mipi_dsi_device * dsi)5367 static int panel_simple_dsi_probe(struct mipi_dsi_device *dsi)
5368 {
5369 const struct panel_desc_dsi *desc;
5370 int err;
5371
5372 desc = of_device_get_match_data(&dsi->dev);
5373 if (!desc)
5374 return -ENODEV;
5375
5376 err = panel_simple_probe(&dsi->dev, &desc->desc);
5377 if (err < 0)
5378 return err;
5379
5380 dsi->mode_flags = desc->flags;
5381 dsi->format = desc->format;
5382 dsi->lanes = desc->lanes;
5383
5384 err = mipi_dsi_attach(dsi);
5385 if (err) {
5386 struct panel_simple *panel = mipi_dsi_get_drvdata(dsi);
5387
5388 drm_panel_remove(&panel->base);
5389 }
5390
5391 return err;
5392 }
5393
panel_simple_dsi_remove(struct mipi_dsi_device * dsi)5394 static void panel_simple_dsi_remove(struct mipi_dsi_device *dsi)
5395 {
5396 int err;
5397
5398 err = mipi_dsi_detach(dsi);
5399 if (err < 0)
5400 dev_err(&dsi->dev, "failed to detach from DSI host: %d\n", err);
5401
5402 panel_simple_remove(&dsi->dev);
5403 }
5404
panel_simple_dsi_shutdown(struct mipi_dsi_device * dsi)5405 static void panel_simple_dsi_shutdown(struct mipi_dsi_device *dsi)
5406 {
5407 panel_simple_shutdown(&dsi->dev);
5408 }
5409
5410 static struct mipi_dsi_driver panel_simple_dsi_driver = {
5411 .driver = {
5412 .name = "panel-simple-dsi",
5413 .of_match_table = dsi_of_match,
5414 .pm = &panel_simple_pm_ops,
5415 },
5416 .probe = panel_simple_dsi_probe,
5417 .remove = panel_simple_dsi_remove,
5418 .shutdown = panel_simple_dsi_shutdown,
5419 };
5420
panel_simple_init(void)5421 static int __init panel_simple_init(void)
5422 {
5423 int err;
5424
5425 err = platform_driver_register(&panel_simple_platform_driver);
5426 if (err < 0)
5427 return err;
5428
5429 if (IS_ENABLED(CONFIG_DRM_MIPI_DSI)) {
5430 err = mipi_dsi_driver_register(&panel_simple_dsi_driver);
5431 if (err < 0)
5432 goto err_did_platform_register;
5433 }
5434
5435 return 0;
5436
5437 err_did_platform_register:
5438 platform_driver_unregister(&panel_simple_platform_driver);
5439
5440 return err;
5441 }
5442 module_init(panel_simple_init);
5443
panel_simple_exit(void)5444 static void __exit panel_simple_exit(void)
5445 {
5446 if (IS_ENABLED(CONFIG_DRM_MIPI_DSI))
5447 mipi_dsi_driver_unregister(&panel_simple_dsi_driver);
5448
5449 platform_driver_unregister(&panel_simple_platform_driver);
5450 }
5451 module_exit(panel_simple_exit);
5452
5453 MODULE_AUTHOR("Thierry Reding <treding@nvidia.com>");
5454 MODULE_DESCRIPTION("DRM Driver for Simple Panels");
5455 MODULE_LICENSE("GPL and additional rights");
5456