1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd 4 * Author:Mark Yao <mark.yao@rock-chips.com> 5 */ 6 7 #ifndef _ROCKCHIP_DRM_VOP2_H 8 #define _ROCKCHIP_DRM_VOP2_H 9 10 #include <linux/regmap.h> 11 #include <drm/drm_modes.h> 12 #include "rockchip_drm_drv.h" 13 #include "rockchip_drm_vop.h" 14 15 #define VOP2_VP_FEATURE_OUTPUT_10BIT BIT(0) 16 17 #define VOP2_FEATURE_HAS_SYS_GRF BIT(0) 18 #define VOP2_FEATURE_HAS_VO0_GRF BIT(1) 19 #define VOP2_FEATURE_HAS_VO1_GRF BIT(2) 20 #define VOP2_FEATURE_HAS_VOP_GRF BIT(3) 21 #define VOP2_FEATURE_HAS_SYS_PMU BIT(4) 22 23 #define WIN_FEATURE_AFBDC BIT(0) 24 #define WIN_FEATURE_CLUSTER BIT(1) 25 26 #define HIWORD_UPDATE(v, h, l) ((GENMASK(h, l) << 16) | ((v) << (l))) 27 /* 28 * the delay number of a window in different mode. 29 */ 30 enum win_dly_mode { 31 VOP2_DLY_MODE_DEFAULT, /**< default mode */ 32 VOP2_DLY_MODE_HISO_S, /** HDR in SDR out mode, as a SDR window */ 33 VOP2_DLY_MODE_HIHO_H, /** HDR in HDR out mode, as a HDR window */ 34 VOP2_DLY_MODE_MAX, 35 }; 36 37 enum vop2_scale_up_mode { 38 VOP2_SCALE_UP_NRST_NBOR, 39 VOP2_SCALE_UP_BIL, 40 VOP2_SCALE_UP_BIC, 41 }; 42 43 enum vop2_scale_down_mode { 44 VOP2_SCALE_DOWN_NRST_NBOR, 45 VOP2_SCALE_DOWN_BIL, 46 VOP2_SCALE_DOWN_AVG, 47 }; 48 49 /* 50 * vop2 internal power domain id, 51 * should be all none zero, 0 will be treat as invalid; 52 */ 53 #define VOP2_PD_CLUSTER0 BIT(0) 54 #define VOP2_PD_CLUSTER1 BIT(1) 55 #define VOP2_PD_CLUSTER2 BIT(2) 56 #define VOP2_PD_CLUSTER3 BIT(3) 57 #define VOP2_PD_DSC_8K BIT(5) 58 #define VOP2_PD_DSC_4K BIT(6) 59 #define VOP2_PD_ESMART BIT(7) 60 61 enum vop2_win_regs { 62 VOP2_WIN_ENABLE, 63 VOP2_WIN_FORMAT, 64 VOP2_WIN_CSC_MODE, 65 VOP2_WIN_XMIRROR, 66 VOP2_WIN_YMIRROR, 67 VOP2_WIN_RB_SWAP, 68 VOP2_WIN_UV_SWAP, 69 VOP2_WIN_ACT_INFO, 70 VOP2_WIN_DSP_INFO, 71 VOP2_WIN_DSP_ST, 72 VOP2_WIN_YRGB_MST, 73 VOP2_WIN_UV_MST, 74 VOP2_WIN_YRGB_VIR, 75 VOP2_WIN_UV_VIR, 76 VOP2_WIN_YUV_CLIP, 77 VOP2_WIN_Y2R_EN, 78 VOP2_WIN_R2Y_EN, 79 VOP2_WIN_COLOR_KEY, 80 VOP2_WIN_COLOR_KEY_EN, 81 VOP2_WIN_DITHER_UP, 82 VOP2_WIN_AXI_BUS_ID, 83 VOP2_WIN_AXI_YRGB_R_ID, 84 VOP2_WIN_AXI_UV_R_ID, 85 86 /* scale regs */ 87 VOP2_WIN_SCALE_YRGB_X, 88 VOP2_WIN_SCALE_YRGB_Y, 89 VOP2_WIN_SCALE_CBCR_X, 90 VOP2_WIN_SCALE_CBCR_Y, 91 VOP2_WIN_YRGB_HOR_SCL_MODE, 92 VOP2_WIN_YRGB_HSCL_FILTER_MODE, 93 VOP2_WIN_YRGB_VER_SCL_MODE, 94 VOP2_WIN_YRGB_VSCL_FILTER_MODE, 95 VOP2_WIN_CBCR_VER_SCL_MODE, 96 VOP2_WIN_CBCR_HSCL_FILTER_MODE, 97 VOP2_WIN_CBCR_HOR_SCL_MODE, 98 VOP2_WIN_CBCR_VSCL_FILTER_MODE, 99 VOP2_WIN_VSD_CBCR_GT2, 100 VOP2_WIN_VSD_CBCR_GT4, 101 VOP2_WIN_VSD_YRGB_GT2, 102 VOP2_WIN_VSD_YRGB_GT4, 103 VOP2_WIN_BIC_COE_SEL, 104 105 /* cluster regs */ 106 VOP2_WIN_CLUSTER_ENABLE, 107 VOP2_WIN_AFBC_ENABLE, 108 VOP2_WIN_CLUSTER_LB_MODE, 109 110 /* afbc regs */ 111 VOP2_WIN_AFBC_FORMAT, 112 VOP2_WIN_AFBC_RB_SWAP, 113 VOP2_WIN_AFBC_UV_SWAP, 114 VOP2_WIN_AFBC_AUTO_GATING_EN, 115 VOP2_WIN_AFBC_BLOCK_SPLIT_EN, 116 VOP2_WIN_AFBC_PIC_VIR_WIDTH, 117 VOP2_WIN_AFBC_TILE_NUM, 118 VOP2_WIN_AFBC_PIC_OFFSET, 119 VOP2_WIN_AFBC_PIC_SIZE, 120 VOP2_WIN_AFBC_DSP_OFFSET, 121 VOP2_WIN_AFBC_TRANSFORM_OFFSET, 122 VOP2_WIN_AFBC_HDR_PTR, 123 VOP2_WIN_AFBC_HALF_BLOCK_EN, 124 VOP2_WIN_AFBC_ROTATE_270, 125 VOP2_WIN_AFBC_ROTATE_90, 126 VOP2_WIN_MAX_REG, 127 }; 128 129 struct vop2_win_data { 130 const char *name; 131 unsigned int phys_id; 132 133 u32 base; 134 enum drm_plane_type type; 135 136 u32 nformats; 137 const u32 *formats; 138 const uint64_t *format_modifiers; 139 const unsigned int supported_rotations; 140 141 /** 142 * @layer_sel_id: defined by register OVERLAY_LAYER_SEL of VOP2 143 */ 144 unsigned int layer_sel_id; 145 uint64_t feature; 146 147 uint8_t axi_bus_id; 148 uint8_t axi_yrgb_r_id; 149 uint8_t axi_uv_r_id; 150 151 unsigned int max_upscale_factor; 152 unsigned int max_downscale_factor; 153 const u8 dly[VOP2_DLY_MODE_MAX]; 154 }; 155 156 struct vop2_video_port_data { 157 unsigned int id; 158 u32 feature; 159 u16 gamma_lut_len; 160 u16 cubic_lut_len; 161 struct vop_rect max_output; 162 const u8 pre_scan_max_dly[4]; 163 unsigned int offset; 164 }; 165 166 struct vop2_data { 167 u8 nr_vps; 168 u64 feature; 169 const struct vop2_win_data *win; 170 const struct vop2_video_port_data *vp; 171 struct vop_rect max_input; 172 struct vop_rect max_output; 173 174 unsigned int win_size; 175 unsigned int soc_id; 176 }; 177 178 /* interrupt define */ 179 #define FS_NEW_INTR BIT(4) 180 #define ADDR_SAME_INTR BIT(5) 181 #define LINE_FLAG1_INTR BIT(6) 182 #define WIN0_EMPTY_INTR BIT(7) 183 #define WIN1_EMPTY_INTR BIT(8) 184 #define WIN2_EMPTY_INTR BIT(9) 185 #define WIN3_EMPTY_INTR BIT(10) 186 #define HWC_EMPTY_INTR BIT(11) 187 #define POST_BUF_EMPTY_INTR BIT(12) 188 #define PWM_GEN_INTR BIT(13) 189 #define DMA_FINISH_INTR BIT(14) 190 #define FS_FIELD_INTR BIT(15) 191 #define FE_INTR BIT(16) 192 #define WB_UV_FIFO_FULL_INTR BIT(17) 193 #define WB_YRGB_FIFO_FULL_INTR BIT(18) 194 #define WB_COMPLETE_INTR BIT(19) 195 196 197 enum vop_csc_format { 198 CSC_BT601L, 199 CSC_BT709L, 200 CSC_BT601F, 201 CSC_BT2020, 202 }; 203 204 enum src_factor_mode { 205 SRC_FAC_ALPHA_ZERO, 206 SRC_FAC_ALPHA_ONE, 207 SRC_FAC_ALPHA_DST, 208 SRC_FAC_ALPHA_DST_INVERSE, 209 SRC_FAC_ALPHA_SRC, 210 SRC_FAC_ALPHA_SRC_GLOBAL, 211 }; 212 213 enum dst_factor_mode { 214 DST_FAC_ALPHA_ZERO, 215 DST_FAC_ALPHA_ONE, 216 DST_FAC_ALPHA_SRC, 217 DST_FAC_ALPHA_SRC_INVERSE, 218 DST_FAC_ALPHA_DST, 219 DST_FAC_ALPHA_DST_GLOBAL, 220 }; 221 222 #define RK3568_GRF_VO_CON1 0x0364 223 224 #define RK3588_GRF_SOC_CON1 0x0304 225 #define RK3588_GRF_VOP_CON2 0x08 226 #define RK3588_GRF_VO1_CON0 0x00 227 228 /* System registers definition */ 229 #define RK3568_REG_CFG_DONE 0x000 230 #define RK3568_VERSION_INFO 0x004 231 #define RK3568_SYS_AUTO_GATING_CTRL 0x008 232 #define RK3568_SYS_AXI_LUT_CTRL 0x024 233 #define RK3568_DSP_IF_EN 0x028 234 #define RK3568_DSP_IF_CTRL 0x02c 235 #define RK3568_DSP_IF_POL 0x030 236 #define RK3588_SYS_PD_CTRL 0x034 237 #define RK3568_WB_CTRL 0x40 238 #define RK3568_WB_XSCAL_FACTOR 0x44 239 #define RK3568_WB_YRGB_MST 0x48 240 #define RK3568_WB_CBR_MST 0x4C 241 #define RK3568_OTP_WIN_EN 0x050 242 #define RK3568_LUT_PORT_SEL 0x058 243 #define RK3568_SYS_STATUS0 0x060 244 #define RK3568_VP_LINE_FLAG(vp) (0x70 + (vp) * 0x4) 245 #define RK3568_SYS0_INT_EN 0x80 246 #define RK3568_SYS0_INT_CLR 0x84 247 #define RK3568_SYS0_INT_STATUS 0x88 248 #define RK3568_SYS1_INT_EN 0x90 249 #define RK3568_SYS1_INT_CLR 0x94 250 #define RK3568_SYS1_INT_STATUS 0x98 251 #define RK3568_VP_INT_EN(vp) (0xA0 + (vp) * 0x10) 252 #define RK3568_VP_INT_CLR(vp) (0xA4 + (vp) * 0x10) 253 #define RK3568_VP_INT_STATUS(vp) (0xA8 + (vp) * 0x10) 254 #define RK3568_VP_INT_RAW_STATUS(vp) (0xAC + (vp) * 0x10) 255 256 /* Video Port registers definition */ 257 #define RK3568_VP0_CTRL_BASE 0x0C00 258 #define RK3568_VP1_CTRL_BASE 0x0D00 259 #define RK3568_VP2_CTRL_BASE 0x0E00 260 #define RK3588_VP3_CTRL_BASE 0x0F00 261 #define RK3568_VP_DSP_CTRL 0x00 262 #define RK3568_VP_MIPI_CTRL 0x04 263 #define RK3568_VP_COLOR_BAR_CTRL 0x08 264 #define RK3588_VP_CLK_CTRL 0x0C 265 #define RK3568_VP_3D_LUT_CTRL 0x10 266 #define RK3568_VP_3D_LUT_MST 0x20 267 #define RK3568_VP_DSP_BG 0x2C 268 #define RK3568_VP_PRE_SCAN_HTIMING 0x30 269 #define RK3568_VP_POST_DSP_HACT_INFO 0x34 270 #define RK3568_VP_POST_DSP_VACT_INFO 0x38 271 #define RK3568_VP_POST_SCL_FACTOR_YRGB 0x3C 272 #define RK3568_VP_POST_SCL_CTRL 0x40 273 #define RK3568_VP_POST_DSP_VACT_INFO_F1 0x44 274 #define RK3568_VP_DSP_HTOTAL_HS_END 0x48 275 #define RK3568_VP_DSP_HACT_ST_END 0x4C 276 #define RK3568_VP_DSP_VTOTAL_VS_END 0x50 277 #define RK3568_VP_DSP_VACT_ST_END 0x54 278 #define RK3568_VP_DSP_VS_ST_END_F1 0x58 279 #define RK3568_VP_DSP_VACT_ST_END_F1 0x5C 280 #define RK3568_VP_BCSH_CTRL 0x60 281 #define RK3568_VP_BCSH_BCS 0x64 282 #define RK3568_VP_BCSH_H 0x68 283 #define RK3568_VP_BCSH_COLOR_BAR 0x6C 284 285 /* Overlay registers definition */ 286 #define RK3568_OVL_CTRL 0x600 287 #define RK3568_OVL_LAYER_SEL 0x604 288 #define RK3568_OVL_PORT_SEL 0x608 289 #define RK3568_CLUSTER0_MIX_SRC_COLOR_CTRL 0x610 290 #define RK3568_CLUSTER0_MIX_DST_COLOR_CTRL 0x614 291 #define RK3568_CLUSTER0_MIX_SRC_ALPHA_CTRL 0x618 292 #define RK3568_CLUSTER0_MIX_DST_ALPHA_CTRL 0x61C 293 #define RK3568_MIX0_SRC_COLOR_CTRL 0x650 294 #define RK3568_MIX0_DST_COLOR_CTRL 0x654 295 #define RK3568_MIX0_SRC_ALPHA_CTRL 0x658 296 #define RK3568_MIX0_DST_ALPHA_CTRL 0x65C 297 #define RK3568_HDR0_SRC_COLOR_CTRL 0x6C0 298 #define RK3568_HDR0_DST_COLOR_CTRL 0x6C4 299 #define RK3568_HDR0_SRC_ALPHA_CTRL 0x6C8 300 #define RK3568_HDR0_DST_ALPHA_CTRL 0x6CC 301 #define RK3568_VP_BG_MIX_CTRL(vp) (0x6E0 + (vp) * 4) 302 #define RK3568_CLUSTER_DLY_NUM 0x6F0 303 #define RK3568_SMART_DLY_NUM 0x6F8 304 305 /* Cluster register definition, offset relative to window base */ 306 #define RK3568_CLUSTER0_CTRL_BASE 0x1000 307 #define RK3568_CLUSTER1_CTRL_BASE 0x1200 308 #define RK3588_CLUSTER2_CTRL_BASE 0x1400 309 #define RK3588_CLUSTER3_CTRL_BASE 0x1600 310 #define RK3568_ESMART0_CTRL_BASE 0x1800 311 #define RK3568_ESMART1_CTRL_BASE 0x1A00 312 #define RK3568_SMART0_CTRL_BASE 0x1C00 313 #define RK3568_SMART1_CTRL_BASE 0x1E00 314 #define RK3588_ESMART2_CTRL_BASE 0x1C00 315 #define RK3588_ESMART3_CTRL_BASE 0x1E00 316 317 #define RK3568_CLUSTER_WIN_CTRL0 0x00 318 #define RK3568_CLUSTER_WIN_CTRL1 0x04 319 #define RK3568_CLUSTER_WIN_CTRL2 0x08 320 #define RK3568_CLUSTER_WIN_YRGB_MST 0x10 321 #define RK3568_CLUSTER_WIN_CBR_MST 0x14 322 #define RK3568_CLUSTER_WIN_VIR 0x18 323 #define RK3568_CLUSTER_WIN_ACT_INFO 0x20 324 #define RK3568_CLUSTER_WIN_DSP_INFO 0x24 325 #define RK3568_CLUSTER_WIN_DSP_ST 0x28 326 #define RK3568_CLUSTER_WIN_SCL_FACTOR_YRGB 0x30 327 #define RK3568_CLUSTER_WIN_AFBCD_TRANSFORM_OFFSET 0x3C 328 #define RK3568_CLUSTER_WIN_AFBCD_OUTPUT_CTRL 0x50 329 #define RK3568_CLUSTER_WIN_AFBCD_ROTATE_MODE 0x54 330 #define RK3568_CLUSTER_WIN_AFBCD_HDR_PTR 0x58 331 #define RK3568_CLUSTER_WIN_AFBCD_VIR_WIDTH 0x5C 332 #define RK3568_CLUSTER_WIN_AFBCD_PIC_SIZE 0x60 333 #define RK3568_CLUSTER_WIN_AFBCD_PIC_OFFSET 0x64 334 #define RK3568_CLUSTER_WIN_AFBCD_DSP_OFFSET 0x68 335 #define RK3568_CLUSTER_WIN_AFBCD_CTRL 0x6C 336 337 #define RK3568_CLUSTER_CTRL 0x100 338 339 /* (E)smart register definition, offset relative to window base */ 340 #define RK3568_SMART_CTRL0 0x00 341 #define RK3568_SMART_CTRL1 0x04 342 #define RK3588_SMART_AXI_CTRL 0x08 343 #define RK3568_SMART_REGION0_CTRL 0x10 344 #define RK3568_SMART_REGION0_YRGB_MST 0x14 345 #define RK3568_SMART_REGION0_CBR_MST 0x18 346 #define RK3568_SMART_REGION0_VIR 0x1C 347 #define RK3568_SMART_REGION0_ACT_INFO 0x20 348 #define RK3568_SMART_REGION0_DSP_INFO 0x24 349 #define RK3568_SMART_REGION0_DSP_ST 0x28 350 #define RK3568_SMART_REGION0_SCL_CTRL 0x30 351 #define RK3568_SMART_REGION0_SCL_FACTOR_YRGB 0x34 352 #define RK3568_SMART_REGION0_SCL_FACTOR_CBR 0x38 353 #define RK3568_SMART_REGION0_SCL_OFFSET 0x3C 354 #define RK3568_SMART_REGION1_CTRL 0x40 355 #define RK3568_SMART_REGION1_YRGB_MST 0x44 356 #define RK3568_SMART_REGION1_CBR_MST 0x48 357 #define RK3568_SMART_REGION1_VIR 0x4C 358 #define RK3568_SMART_REGION1_ACT_INFO 0x50 359 #define RK3568_SMART_REGION1_DSP_INFO 0x54 360 #define RK3568_SMART_REGION1_DSP_ST 0x58 361 #define RK3568_SMART_REGION1_SCL_CTRL 0x60 362 #define RK3568_SMART_REGION1_SCL_FACTOR_YRGB 0x64 363 #define RK3568_SMART_REGION1_SCL_FACTOR_CBR 0x68 364 #define RK3568_SMART_REGION1_SCL_OFFSET 0x6C 365 #define RK3568_SMART_REGION2_CTRL 0x70 366 #define RK3568_SMART_REGION2_YRGB_MST 0x74 367 #define RK3568_SMART_REGION2_CBR_MST 0x78 368 #define RK3568_SMART_REGION2_VIR 0x7C 369 #define RK3568_SMART_REGION2_ACT_INFO 0x80 370 #define RK3568_SMART_REGION2_DSP_INFO 0x84 371 #define RK3568_SMART_REGION2_DSP_ST 0x88 372 #define RK3568_SMART_REGION2_SCL_CTRL 0x90 373 #define RK3568_SMART_REGION2_SCL_FACTOR_YRGB 0x94 374 #define RK3568_SMART_REGION2_SCL_FACTOR_CBR 0x98 375 #define RK3568_SMART_REGION2_SCL_OFFSET 0x9C 376 #define RK3568_SMART_REGION3_CTRL 0xA0 377 #define RK3568_SMART_REGION3_YRGB_MST 0xA4 378 #define RK3568_SMART_REGION3_CBR_MST 0xA8 379 #define RK3568_SMART_REGION3_VIR 0xAC 380 #define RK3568_SMART_REGION3_ACT_INFO 0xB0 381 #define RK3568_SMART_REGION3_DSP_INFO 0xB4 382 #define RK3568_SMART_REGION3_DSP_ST 0xB8 383 #define RK3568_SMART_REGION3_SCL_CTRL 0xC0 384 #define RK3568_SMART_REGION3_SCL_FACTOR_YRGB 0xC4 385 #define RK3568_SMART_REGION3_SCL_FACTOR_CBR 0xC8 386 #define RK3568_SMART_REGION3_SCL_OFFSET 0xCC 387 #define RK3568_SMART_COLOR_KEY_CTRL 0xD0 388 389 /* HDR register definition */ 390 #define RK3568_HDR_LUT_CTRL 0x2000 391 #define RK3568_HDR_LUT_MST 0x2004 392 #define RK3568_SDR2HDR_CTRL 0x2010 393 #define RK3568_HDR2SDR_CTRL 0x2020 394 #define RK3568_HDR2SDR_SRC_RANGE 0x2024 395 #define RK3568_HDR2SDR_NORMFACEETF 0x2028 396 #define RK3568_HDR2SDR_DST_RANGE 0x202C 397 #define RK3568_HDR2SDR_NORMFACCGAMMA 0x2030 398 #define RK3568_HDR_EETF_OETF_Y0 0x203C 399 #define RK3568_HDR_SAT_Y0 0x20C0 400 #define RK3568_HDR_EOTF_OETF_Y0 0x20F0 401 #define RK3568_HDR_OETF_DX_POW1 0x2200 402 #define RK3568_HDR_OETF_XN1 0x2300 403 404 #define RK3568_REG_CFG_DONE__GLB_CFG_DONE_EN BIT(15) 405 406 #define RK3568_VP_DSP_CTRL__STANDBY BIT(31) 407 #define RK3568_VP_DSP_CTRL__DITHER_DOWN_MODE BIT(20) 408 #define RK3568_VP_DSP_CTRL__DITHER_DOWN_SEL GENMASK(19, 18) 409 #define RK3568_VP_DSP_CTRL__DITHER_DOWN_EN BIT(17) 410 #define RK3568_VP_DSP_CTRL__PRE_DITHER_DOWN_EN BIT(16) 411 #define RK3568_VP_DSP_CTRL__POST_DSP_OUT_R2Y BIT(15) 412 #define RK3568_VP_DSP_CTRL__DSP_RG_SWAP BIT(10) 413 #define RK3568_VP_DSP_CTRL__DSP_RB_SWAP BIT(9) 414 #define RK3568_VP_DSP_CTRL__DSP_BG_SWAP BIT(8) 415 #define RK3568_VP_DSP_CTRL__DSP_INTERLACE BIT(7) 416 #define RK3568_VP_DSP_CTRL__DSP_FILED_POL BIT(6) 417 #define RK3568_VP_DSP_CTRL__P2I_EN BIT(5) 418 #define RK3568_VP_DSP_CTRL__CORE_DCLK_DIV BIT(4) 419 #define RK3568_VP_DSP_CTRL__OUT_MODE GENMASK(3, 0) 420 421 #define RK3588_VP_CLK_CTRL__DCLK_OUT_DIV GENMASK(3, 2) 422 #define RK3588_VP_CLK_CTRL__DCLK_CORE_DIV GENMASK(1, 0) 423 424 #define RK3568_VP_POST_SCL_CTRL__VSCALEDOWN BIT(1) 425 #define RK3568_VP_POST_SCL_CTRL__HSCALEDOWN BIT(0) 426 427 #define RK3568_SYS_DSP_INFACE_EN_LVDS1_MUX GENMASK(26, 25) 428 #define RK3568_SYS_DSP_INFACE_EN_LVDS1 BIT(24) 429 #define RK3568_SYS_DSP_INFACE_EN_MIPI1_MUX GENMASK(22, 21) 430 #define RK3568_SYS_DSP_INFACE_EN_MIPI1 BIT(20) 431 #define RK3568_SYS_DSP_INFACE_EN_LVDS0_MUX GENMASK(19, 18) 432 #define RK3568_SYS_DSP_INFACE_EN_MIPI0_MUX GENMASK(17, 16) 433 #define RK3568_SYS_DSP_INFACE_EN_EDP_MUX GENMASK(15, 14) 434 #define RK3568_SYS_DSP_INFACE_EN_HDMI_MUX GENMASK(11, 10) 435 #define RK3568_SYS_DSP_INFACE_EN_RGB_MUX GENMASK(9, 8) 436 #define RK3568_SYS_DSP_INFACE_EN_LVDS0 BIT(5) 437 #define RK3568_SYS_DSP_INFACE_EN_MIPI0 BIT(4) 438 #define RK3568_SYS_DSP_INFACE_EN_EDP BIT(3) 439 #define RK3568_SYS_DSP_INFACE_EN_HDMI BIT(1) 440 #define RK3568_SYS_DSP_INFACE_EN_RGB BIT(0) 441 442 #define RK3588_SYS_DSP_INFACE_EN_MIPI1_MUX GENMASK(22, 21) 443 #define RK3588_SYS_DSP_INFACE_EN_MIPI0_MUX GENMASK(20, 20) 444 #define RK3588_SYS_DSP_INFACE_EN_EDP_HDMI1_MUX GENMASK(19, 18) 445 #define RK3588_SYS_DSP_INFACE_EN_EDP_HDMI0_MUX GENMASK(17, 16) 446 #define RK3588_SYS_DSP_INFACE_EN_DP1_MUX GENMASK(15, 14) 447 #define RK3588_SYS_DSP_INFACE_EN_DP0_MUX GENMASK(13, 12) 448 #define RK3588_SYS_DSP_INFACE_EN_DPI GENMASK(9, 8) 449 #define RK3588_SYS_DSP_INFACE_EN_MIPI1 BIT(7) 450 #define RK3588_SYS_DSP_INFACE_EN_MIPI0 BIT(6) 451 #define RK3588_SYS_DSP_INFACE_EN_HDMI1 BIT(5) 452 #define RK3588_SYS_DSP_INFACE_EN_EDP1 BIT(4) 453 #define RK3588_SYS_DSP_INFACE_EN_HDMI0 BIT(3) 454 #define RK3588_SYS_DSP_INFACE_EN_EDP0 BIT(2) 455 #define RK3588_SYS_DSP_INFACE_EN_DP1 BIT(1) 456 #define RK3588_SYS_DSP_INFACE_EN_DP0 BIT(0) 457 458 #define RK3588_DSP_IF_MIPI1_PCLK_DIV GENMASK(27, 26) 459 #define RK3588_DSP_IF_MIPI0_PCLK_DIV GENMASK(25, 24) 460 #define RK3588_DSP_IF_EDP_HDMI1_PCLK_DIV GENMASK(22, 22) 461 #define RK3588_DSP_IF_EDP_HDMI1_DCLK_DIV GENMASK(21, 20) 462 #define RK3588_DSP_IF_EDP_HDMI0_PCLK_DIV GENMASK(18, 18) 463 #define RK3588_DSP_IF_EDP_HDMI0_DCLK_DIV GENMASK(17, 16) 464 465 #define RK3568_DSP_IF_POL__MIPI_PIN_POL GENMASK(19, 16) 466 #define RK3568_DSP_IF_POL__EDP_PIN_POL GENMASK(15, 12) 467 #define RK3568_DSP_IF_POL__HDMI_PIN_POL GENMASK(7, 4) 468 #define RK3568_DSP_IF_POL__RGB_LVDS_PIN_POL GENMASK(3, 0) 469 470 #define RK3588_DSP_IF_POL__DP1_PIN_POL GENMASK(14, 12) 471 #define RK3588_DSP_IF_POL__DP0_PIN_POL GENMASK(10, 8) 472 473 #define RK3568_VP0_MIPI_CTRL__DCLK_DIV2_PHASE_LOCK BIT(5) 474 #define RK3568_VP0_MIPI_CTRL__DCLK_DIV2 BIT(4) 475 476 #define RK3568_SYS_AUTO_GATING_CTRL__AUTO_GATING_EN BIT(31) 477 478 #define RK3568_DSP_IF_POL__CFG_DONE_IMD BIT(28) 479 480 #define VOP2_SYS_AXI_BUS_NUM 2 481 482 #define VOP2_CLUSTER_YUV444_10 0x12 483 484 #define VOP2_COLOR_KEY_MASK BIT(31) 485 486 #define RK3568_OVL_CTRL__LAYERSEL_REGDONE_IMD BIT(28) 487 #define RK3568_OVL_CTRL__YUV_MODE(vp) BIT(vp) 488 489 #define RK3568_VP_BG_MIX_CTRL__BG_DLY GENMASK(31, 24) 490 491 #define RK3568_OVL_PORT_SEL__SEL_PORT GENMASK(31, 16) 492 #define RK3568_OVL_PORT_SEL__SMART1 GENMASK(31, 30) 493 #define RK3568_OVL_PORT_SEL__SMART0 GENMASK(29, 28) 494 #define RK3588_OVL_PORT_SEL__ESMART3 GENMASK(31, 30) 495 #define RK3588_OVL_PORT_SEL__ESMART2 GENMASK(29, 28) 496 #define RK3568_OVL_PORT_SEL__ESMART1 GENMASK(27, 26) 497 #define RK3568_OVL_PORT_SEL__ESMART0 GENMASK(25, 24) 498 #define RK3588_OVL_PORT_SEL__CLUSTER3 GENMASK(23, 22) 499 #define RK3588_OVL_PORT_SEL__CLUSTER2 GENMASK(21, 20) 500 #define RK3568_OVL_PORT_SEL__CLUSTER1 GENMASK(19, 18) 501 #define RK3568_OVL_PORT_SEL__CLUSTER0 GENMASK(17, 16) 502 #define RK3568_OVL_PORT_SET__PORT2_MUX GENMASK(11, 8) 503 #define RK3568_OVL_PORT_SET__PORT1_MUX GENMASK(7, 4) 504 #define RK3568_OVL_PORT_SET__PORT0_MUX GENMASK(3, 0) 505 #define RK3568_OVL_LAYER_SEL__LAYER(layer, x) ((x) << ((layer) * 4)) 506 507 #define RK3568_CLUSTER_DLY_NUM__CLUSTER1_1 GENMASK(31, 24) 508 #define RK3568_CLUSTER_DLY_NUM__CLUSTER1_0 GENMASK(23, 16) 509 #define RK3568_CLUSTER_DLY_NUM__CLUSTER0_1 GENMASK(15, 8) 510 #define RK3568_CLUSTER_DLY_NUM__CLUSTER0_0 GENMASK(7, 0) 511 512 #define RK3568_CLUSTER_WIN_CTRL0__WIN0_EN BIT(0) 513 514 #define RK3568_SMART_REGION0_CTRL__WIN0_EN BIT(0) 515 516 #define RK3568_SMART_DLY_NUM__SMART1 GENMASK(31, 24) 517 #define RK3568_SMART_DLY_NUM__SMART0 GENMASK(23, 16) 518 #define RK3568_SMART_DLY_NUM__ESMART1 GENMASK(15, 8) 519 #define RK3568_SMART_DLY_NUM__ESMART0 GENMASK(7, 0) 520 521 #define VP_INT_DSP_HOLD_VALID BIT(6) 522 #define VP_INT_FS_FIELD BIT(5) 523 #define VP_INT_POST_BUF_EMPTY BIT(4) 524 #define VP_INT_LINE_FLAG1 BIT(3) 525 #define VP_INT_LINE_FLAG0 BIT(2) 526 #define VOP2_INT_BUS_ERRPR BIT(1) 527 #define VP_INT_FS BIT(0) 528 529 #define POLFLAG_DCLK_INV BIT(3) 530 531 enum vop2_layer_phy_id { 532 ROCKCHIP_VOP2_CLUSTER0 = 0, 533 ROCKCHIP_VOP2_CLUSTER1, 534 ROCKCHIP_VOP2_ESMART0, 535 ROCKCHIP_VOP2_ESMART1, 536 ROCKCHIP_VOP2_SMART0, 537 ROCKCHIP_VOP2_SMART1, 538 ROCKCHIP_VOP2_CLUSTER2, 539 ROCKCHIP_VOP2_CLUSTER3, 540 ROCKCHIP_VOP2_ESMART2, 541 ROCKCHIP_VOP2_ESMART3, 542 ROCKCHIP_VOP2_PHY_ID_INVALID = -1, 543 }; 544 545 extern const struct component_ops vop2_component_ops; 546 547 #endif /* _ROCKCHIP_DRM_VOP2_H */ 548