1 // SPDX-License-Identifier: GPL-2.0+
2 /* Copyright (C) 2017-2018 Broadcom */
3
4 /**
5 * DOC: Broadcom V3D MMU
6 *
7 * The V3D 3.x hardware (compared to VC4) now includes an MMU. It has
8 * a single level of page tables for the V3D's 4GB address space to
9 * map to AXI bus addresses, thus it could need up to 4MB of
10 * physically contiguous memory to store the PTEs.
11 *
12 * Because the 4MB of contiguous memory for page tables is precious,
13 * and switching between them is expensive, we load all BOs into the
14 * same 4GB address space.
15 *
16 * To protect clients from each other, we should use the GMP to
17 * quickly mask out (at 128kb granularity) what pages are available to
18 * each client. This is not yet implemented.
19 */
20
21 #include "v3d_drv.h"
22 #include "v3d_regs.h"
23
24 /* Note: All PTEs for the 1MB superpage must be filled with the
25 * superpage bit set.
26 */
27 #define V3D_PTE_SUPERPAGE BIT(31)
28 #define V3D_PTE_WRITEABLE BIT(29)
29 #define V3D_PTE_VALID BIT(28)
30
v3d_mmu_flush_all(struct v3d_dev * v3d)31 int v3d_mmu_flush_all(struct v3d_dev *v3d)
32 {
33 int ret;
34
35 V3D_WRITE(V3D_MMUC_CONTROL, V3D_MMUC_CONTROL_FLUSH |
36 V3D_MMUC_CONTROL_ENABLE);
37
38 ret = wait_for(!(V3D_READ(V3D_MMUC_CONTROL) &
39 V3D_MMUC_CONTROL_FLUSHING), 100);
40 if (ret) {
41 dev_err(v3d->drm.dev, "MMUC flush wait idle failed\n");
42 return ret;
43 }
44
45 V3D_WRITE(V3D_MMU_CTL, V3D_READ(V3D_MMU_CTL) |
46 V3D_MMU_CTL_TLB_CLEAR);
47
48 ret = wait_for(!(V3D_READ(V3D_MMU_CTL) &
49 V3D_MMU_CTL_TLB_CLEARING), 100);
50 if (ret)
51 dev_err(v3d->drm.dev, "MMU TLB clear wait idle failed\n");
52
53 return ret;
54 }
55
v3d_mmu_set_page_table(struct v3d_dev * v3d)56 int v3d_mmu_set_page_table(struct v3d_dev *v3d)
57 {
58 V3D_WRITE(V3D_MMU_PT_PA_BASE, v3d->pt_paddr >> V3D_MMU_PAGE_SHIFT);
59 V3D_WRITE(V3D_MMU_CTL,
60 V3D_MMU_CTL_ENABLE |
61 V3D_MMU_CTL_PT_INVALID_ENABLE |
62 V3D_MMU_CTL_PT_INVALID_ABORT |
63 V3D_MMU_CTL_PT_INVALID_INT |
64 V3D_MMU_CTL_WRITE_VIOLATION_ABORT |
65 V3D_MMU_CTL_WRITE_VIOLATION_INT |
66 V3D_MMU_CTL_CAP_EXCEEDED_ABORT |
67 V3D_MMU_CTL_CAP_EXCEEDED_INT);
68 V3D_WRITE(V3D_MMU_ILLEGAL_ADDR,
69 (v3d->mmu_scratch_paddr >> V3D_MMU_PAGE_SHIFT) |
70 V3D_MMU_ILLEGAL_ADDR_ENABLE);
71 V3D_WRITE(V3D_MMUC_CONTROL, V3D_MMUC_CONTROL_ENABLE);
72
73 return v3d_mmu_flush_all(v3d);
74 }
75
v3d_mmu_insert_ptes(struct v3d_bo * bo)76 void v3d_mmu_insert_ptes(struct v3d_bo *bo)
77 {
78 struct drm_gem_shmem_object *shmem_obj = &bo->base;
79 struct v3d_dev *v3d = to_v3d_dev(shmem_obj->base.dev);
80 u32 page = bo->node.start;
81 u32 page_prot = V3D_PTE_WRITEABLE | V3D_PTE_VALID;
82 struct sg_dma_page_iter dma_iter;
83
84 for_each_sgtable_dma_page(shmem_obj->sgt, &dma_iter, 0) {
85 dma_addr_t dma_addr = sg_page_iter_dma_address(&dma_iter);
86 u32 page_address = dma_addr >> V3D_MMU_PAGE_SHIFT;
87 u32 pte = page_prot | page_address;
88 u32 i;
89
90 BUG_ON(page_address + (PAGE_SIZE >> V3D_MMU_PAGE_SHIFT) >=
91 BIT(24));
92 for (i = 0; i < PAGE_SIZE >> V3D_MMU_PAGE_SHIFT; i++)
93 v3d->pt[page++] = pte + i;
94 }
95
96 WARN_ON_ONCE(page - bo->node.start !=
97 shmem_obj->base.size >> V3D_MMU_PAGE_SHIFT);
98
99 if (v3d_mmu_flush_all(v3d))
100 dev_err(v3d->drm.dev, "MMU flush timeout\n");
101 }
102
v3d_mmu_remove_ptes(struct v3d_bo * bo)103 void v3d_mmu_remove_ptes(struct v3d_bo *bo)
104 {
105 struct v3d_dev *v3d = to_v3d_dev(bo->base.base.dev);
106 u32 npages = bo->base.base.size >> V3D_MMU_PAGE_SHIFT;
107 u32 page;
108
109 for (page = bo->node.start; page < bo->node.start + npages; page++)
110 v3d->pt[page] = 0;
111
112 if (v3d_mmu_flush_all(v3d))
113 dev_err(v3d->drm.dev, "MMU flush timeout\n");
114 }
115