1 /*
2 * Copyright (C) 2015 Red Hat, Inc.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining
6 * a copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sublicense, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the
14 * next paragraph) shall be included in all copies or substantial
15 * portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
18 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
20 * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
21 * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
22 * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
23 * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
24 */
25
26 #include <drm/drm_atomic_helper.h>
27 #include <drm/drm_damage_helper.h>
28 #include <drm/drm_fourcc.h>
29
30 #include "virtgpu_drv.h"
31
32 static const uint32_t virtio_gpu_formats[] = {
33 DRM_FORMAT_XRGB8888,
34 DRM_FORMAT_ARGB8888,
35 DRM_FORMAT_BGRX8888,
36 DRM_FORMAT_BGRA8888,
37 DRM_FORMAT_RGBX8888,
38 DRM_FORMAT_RGBA8888,
39 DRM_FORMAT_XBGR8888,
40 DRM_FORMAT_ABGR8888,
41 };
42
43 static const uint32_t virtio_gpu_cursor_formats[] = {
44 DRM_FORMAT_HOST_ARGB8888,
45 };
46
virtio_gpu_translate_format(uint32_t drm_fourcc)47 uint32_t virtio_gpu_translate_format(uint32_t drm_fourcc)
48 {
49 uint32_t format;
50
51 switch (drm_fourcc) {
52 #ifdef __BIG_ENDIAN
53 case DRM_FORMAT_XRGB8888:
54 format = VIRTIO_GPU_FORMAT_X8R8G8B8_UNORM;
55 break;
56 case DRM_FORMAT_ARGB8888:
57 format = VIRTIO_GPU_FORMAT_A8R8G8B8_UNORM;
58 break;
59 case DRM_FORMAT_BGRX8888:
60 format = VIRTIO_GPU_FORMAT_B8G8R8X8_UNORM;
61 break;
62 case DRM_FORMAT_BGRA8888:
63 format = VIRTIO_GPU_FORMAT_B8G8R8A8_UNORM;
64 break;
65 case DRM_FORMAT_RGBX8888:
66 format = VIRTIO_GPU_FORMAT_R8G8B8X8_UNORM;
67 break;
68 case DRM_FORMAT_RGBA8888:
69 format = VIRTIO_GPU_FORMAT_R8G8B8A8_UNORM;
70 break;
71 case DRM_FORMAT_XBGR8888:
72 format = VIRTIO_GPU_FORMAT_X8B8G8R8_UNORM;
73 break;
74 case DRM_FORMAT_ABGR8888:
75 format = VIRTIO_GPU_FORMAT_A8B8G8R8_UNORM;
76 break;
77 #else
78 case DRM_FORMAT_XRGB8888:
79 format = VIRTIO_GPU_FORMAT_B8G8R8X8_UNORM;
80 break;
81 case DRM_FORMAT_ARGB8888:
82 format = VIRTIO_GPU_FORMAT_B8G8R8A8_UNORM;
83 break;
84 case DRM_FORMAT_BGRX8888:
85 format = VIRTIO_GPU_FORMAT_X8R8G8B8_UNORM;
86 break;
87 case DRM_FORMAT_BGRA8888:
88 format = VIRTIO_GPU_FORMAT_A8R8G8B8_UNORM;
89 break;
90 case DRM_FORMAT_RGBX8888:
91 format = VIRTIO_GPU_FORMAT_X8B8G8R8_UNORM;
92 break;
93 case DRM_FORMAT_RGBA8888:
94 format = VIRTIO_GPU_FORMAT_A8B8G8R8_UNORM;
95 break;
96 case DRM_FORMAT_XBGR8888:
97 format = VIRTIO_GPU_FORMAT_R8G8B8X8_UNORM;
98 break;
99 case DRM_FORMAT_ABGR8888:
100 format = VIRTIO_GPU_FORMAT_R8G8B8A8_UNORM;
101 break;
102 #endif
103 default:
104 /*
105 * This should not happen, we handle everything listed
106 * in virtio_gpu_formats[].
107 */
108 format = 0;
109 break;
110 }
111 WARN_ON(format == 0);
112 return format;
113 }
114
115 static struct
virtio_gpu_plane_duplicate_state(struct drm_plane * plane)116 drm_plane_state *virtio_gpu_plane_duplicate_state(struct drm_plane *plane)
117 {
118 struct virtio_gpu_plane_state *new;
119
120 if (WARN_ON(!plane->state))
121 return NULL;
122
123 new = kzalloc(sizeof(*new), GFP_KERNEL);
124 if (!new)
125 return NULL;
126
127 __drm_atomic_helper_plane_duplicate_state(plane, &new->base);
128
129 return &new->base;
130 }
131
132 static const struct drm_plane_funcs virtio_gpu_plane_funcs = {
133 .update_plane = drm_atomic_helper_update_plane,
134 .disable_plane = drm_atomic_helper_disable_plane,
135 .reset = drm_atomic_helper_plane_reset,
136 .atomic_duplicate_state = virtio_gpu_plane_duplicate_state,
137 .atomic_destroy_state = drm_atomic_helper_plane_destroy_state,
138 };
139
virtio_gpu_plane_atomic_check(struct drm_plane * plane,struct drm_atomic_state * state)140 static int virtio_gpu_plane_atomic_check(struct drm_plane *plane,
141 struct drm_atomic_state *state)
142 {
143 struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state,
144 plane);
145 struct drm_plane_state *old_plane_state = drm_atomic_get_old_plane_state(state,
146 plane);
147 bool is_cursor = plane->type == DRM_PLANE_TYPE_CURSOR;
148 struct drm_crtc_state *crtc_state;
149 int ret;
150
151 if (!new_plane_state->fb || WARN_ON(!new_plane_state->crtc))
152 return 0;
153
154 /*
155 * Ignore damage clips if the framebuffer attached to the plane's state
156 * has changed since the last plane update (page-flip). In this case, a
157 * full plane update should happen because uploads are done per-buffer.
158 */
159 if (old_plane_state->fb != new_plane_state->fb)
160 new_plane_state->ignore_damage_clips = true;
161
162 crtc_state = drm_atomic_get_crtc_state(state,
163 new_plane_state->crtc);
164 if (IS_ERR(crtc_state))
165 return PTR_ERR(crtc_state);
166
167 ret = drm_atomic_helper_check_plane_state(new_plane_state, crtc_state,
168 DRM_PLANE_NO_SCALING,
169 DRM_PLANE_NO_SCALING,
170 is_cursor, true);
171 return ret;
172 }
173
virtio_gpu_update_dumb_bo(struct virtio_gpu_device * vgdev,struct drm_plane_state * state,struct drm_rect * rect)174 static void virtio_gpu_update_dumb_bo(struct virtio_gpu_device *vgdev,
175 struct drm_plane_state *state,
176 struct drm_rect *rect)
177 {
178 struct virtio_gpu_object *bo =
179 gem_to_virtio_gpu_obj(state->fb->obj[0]);
180 struct virtio_gpu_object_array *objs;
181 uint32_t w = rect->x2 - rect->x1;
182 uint32_t h = rect->y2 - rect->y1;
183 uint32_t x = rect->x1;
184 uint32_t y = rect->y1;
185 uint32_t off = x * state->fb->format->cpp[0] +
186 y * state->fb->pitches[0];
187
188 objs = virtio_gpu_array_alloc(1);
189 if (!objs)
190 return;
191 virtio_gpu_array_add_obj(objs, &bo->base.base);
192
193 virtio_gpu_cmd_transfer_to_host_2d(vgdev, off, w, h, x, y,
194 objs, NULL);
195 }
196
virtio_gpu_resource_flush(struct drm_plane * plane,uint32_t x,uint32_t y,uint32_t width,uint32_t height)197 static void virtio_gpu_resource_flush(struct drm_plane *plane,
198 uint32_t x, uint32_t y,
199 uint32_t width, uint32_t height)
200 {
201 struct drm_device *dev = plane->dev;
202 struct virtio_gpu_device *vgdev = dev->dev_private;
203 struct virtio_gpu_framebuffer *vgfb;
204 struct virtio_gpu_plane_state *vgplane_st;
205 struct virtio_gpu_object *bo;
206
207 vgfb = to_virtio_gpu_framebuffer(plane->state->fb);
208 vgplane_st = to_virtio_gpu_plane_state(plane->state);
209 bo = gem_to_virtio_gpu_obj(vgfb->base.obj[0]);
210 if (vgplane_st->fence) {
211 struct virtio_gpu_object_array *objs;
212
213 objs = virtio_gpu_array_alloc(1);
214 if (!objs)
215 return;
216 virtio_gpu_array_add_obj(objs, vgfb->base.obj[0]);
217 virtio_gpu_array_lock_resv(objs);
218 virtio_gpu_cmd_resource_flush(vgdev, bo->hw_res_handle, x, y,
219 width, height, objs,
220 vgplane_st->fence);
221 virtio_gpu_notify(vgdev);
222 dma_fence_wait_timeout(&vgplane_st->fence->f, true,
223 msecs_to_jiffies(50));
224 } else {
225 virtio_gpu_cmd_resource_flush(vgdev, bo->hw_res_handle, x, y,
226 width, height, NULL, NULL);
227 virtio_gpu_notify(vgdev);
228 }
229 }
230
virtio_gpu_primary_plane_update(struct drm_plane * plane,struct drm_atomic_state * state)231 static void virtio_gpu_primary_plane_update(struct drm_plane *plane,
232 struct drm_atomic_state *state)
233 {
234 struct drm_plane_state *old_state = drm_atomic_get_old_plane_state(state,
235 plane);
236 struct drm_device *dev = plane->dev;
237 struct virtio_gpu_device *vgdev = dev->dev_private;
238 struct virtio_gpu_output *output = NULL;
239 struct virtio_gpu_object *bo;
240 struct drm_rect rect;
241
242 if (plane->state->crtc)
243 output = drm_crtc_to_virtio_gpu_output(plane->state->crtc);
244 if (old_state->crtc)
245 output = drm_crtc_to_virtio_gpu_output(old_state->crtc);
246 if (WARN_ON(!output))
247 return;
248
249 if (!plane->state->fb || !output->crtc.state->active) {
250 DRM_DEBUG("nofb\n");
251 virtio_gpu_cmd_set_scanout(vgdev, output->index, 0,
252 plane->state->src_w >> 16,
253 plane->state->src_h >> 16,
254 0, 0);
255 virtio_gpu_notify(vgdev);
256 return;
257 }
258
259 if (!drm_atomic_helper_damage_merged(old_state, plane->state, &rect))
260 return;
261
262 bo = gem_to_virtio_gpu_obj(plane->state->fb->obj[0]);
263 if (bo->dumb)
264 virtio_gpu_update_dumb_bo(vgdev, plane->state, &rect);
265
266 if (plane->state->fb != old_state->fb ||
267 plane->state->src_w != old_state->src_w ||
268 plane->state->src_h != old_state->src_h ||
269 plane->state->src_x != old_state->src_x ||
270 plane->state->src_y != old_state->src_y ||
271 output->needs_modeset) {
272 output->needs_modeset = false;
273 DRM_DEBUG("handle 0x%x, crtc %dx%d+%d+%d, src %dx%d+%d+%d\n",
274 bo->hw_res_handle,
275 plane->state->crtc_w, plane->state->crtc_h,
276 plane->state->crtc_x, plane->state->crtc_y,
277 plane->state->src_w >> 16,
278 plane->state->src_h >> 16,
279 plane->state->src_x >> 16,
280 plane->state->src_y >> 16);
281
282 if (bo->host3d_blob || bo->guest_blob) {
283 virtio_gpu_cmd_set_scanout_blob
284 (vgdev, output->index, bo,
285 plane->state->fb,
286 plane->state->src_w >> 16,
287 plane->state->src_h >> 16,
288 plane->state->src_x >> 16,
289 plane->state->src_y >> 16);
290 } else {
291 virtio_gpu_cmd_set_scanout(vgdev, output->index,
292 bo->hw_res_handle,
293 plane->state->src_w >> 16,
294 plane->state->src_h >> 16,
295 plane->state->src_x >> 16,
296 plane->state->src_y >> 16);
297 }
298 }
299
300 virtio_gpu_resource_flush(plane,
301 rect.x1,
302 rect.y1,
303 rect.x2 - rect.x1,
304 rect.y2 - rect.y1);
305 }
306
virtio_gpu_plane_prepare_fb(struct drm_plane * plane,struct drm_plane_state * new_state)307 static int virtio_gpu_plane_prepare_fb(struct drm_plane *plane,
308 struct drm_plane_state *new_state)
309 {
310 struct drm_device *dev = plane->dev;
311 struct virtio_gpu_device *vgdev = dev->dev_private;
312 struct virtio_gpu_framebuffer *vgfb;
313 struct virtio_gpu_plane_state *vgplane_st;
314 struct virtio_gpu_object *bo;
315
316 if (!new_state->fb)
317 return 0;
318
319 vgfb = to_virtio_gpu_framebuffer(new_state->fb);
320 vgplane_st = to_virtio_gpu_plane_state(new_state);
321 bo = gem_to_virtio_gpu_obj(vgfb->base.obj[0]);
322 if (!bo || (plane->type == DRM_PLANE_TYPE_PRIMARY && !bo->guest_blob))
323 return 0;
324
325 if (bo->dumb) {
326 vgplane_st->fence = virtio_gpu_fence_alloc(vgdev,
327 vgdev->fence_drv.context,
328 0);
329 if (!vgplane_st->fence)
330 return -ENOMEM;
331 }
332
333 return 0;
334 }
335
virtio_gpu_plane_cleanup_fb(struct drm_plane * plane,struct drm_plane_state * state)336 static void virtio_gpu_plane_cleanup_fb(struct drm_plane *plane,
337 struct drm_plane_state *state)
338 {
339 struct virtio_gpu_plane_state *vgplane_st;
340
341 if (!state->fb)
342 return;
343
344 vgplane_st = to_virtio_gpu_plane_state(state);
345 if (vgplane_st->fence) {
346 dma_fence_put(&vgplane_st->fence->f);
347 vgplane_st->fence = NULL;
348 }
349 }
350
virtio_gpu_cursor_plane_update(struct drm_plane * plane,struct drm_atomic_state * state)351 static void virtio_gpu_cursor_plane_update(struct drm_plane *plane,
352 struct drm_atomic_state *state)
353 {
354 struct drm_plane_state *old_state = drm_atomic_get_old_plane_state(state,
355 plane);
356 struct drm_device *dev = plane->dev;
357 struct virtio_gpu_device *vgdev = dev->dev_private;
358 struct virtio_gpu_output *output = NULL;
359 struct virtio_gpu_framebuffer *vgfb;
360 struct virtio_gpu_plane_state *vgplane_st;
361 struct virtio_gpu_object *bo = NULL;
362 uint32_t handle;
363
364 if (plane->state->crtc)
365 output = drm_crtc_to_virtio_gpu_output(plane->state->crtc);
366 if (old_state->crtc)
367 output = drm_crtc_to_virtio_gpu_output(old_state->crtc);
368 if (WARN_ON(!output))
369 return;
370
371 if (plane->state->fb) {
372 vgfb = to_virtio_gpu_framebuffer(plane->state->fb);
373 vgplane_st = to_virtio_gpu_plane_state(plane->state);
374 bo = gem_to_virtio_gpu_obj(vgfb->base.obj[0]);
375 handle = bo->hw_res_handle;
376 } else {
377 handle = 0;
378 }
379
380 if (bo && bo->dumb && (plane->state->fb != old_state->fb)) {
381 /* new cursor -- update & wait */
382 struct virtio_gpu_object_array *objs;
383
384 objs = virtio_gpu_array_alloc(1);
385 if (!objs)
386 return;
387 virtio_gpu_array_add_obj(objs, vgfb->base.obj[0]);
388 virtio_gpu_array_lock_resv(objs);
389 virtio_gpu_cmd_transfer_to_host_2d
390 (vgdev, 0,
391 plane->state->crtc_w,
392 plane->state->crtc_h,
393 0, 0, objs, vgplane_st->fence);
394 virtio_gpu_notify(vgdev);
395 dma_fence_wait(&vgplane_st->fence->f, true);
396 }
397
398 if (plane->state->fb != old_state->fb) {
399 DRM_DEBUG("update, handle %d, pos +%d+%d, hot %d,%d\n", handle,
400 plane->state->crtc_x,
401 plane->state->crtc_y,
402 plane->state->hotspot_x,
403 plane->state->hotspot_y);
404 output->cursor.hdr.type =
405 cpu_to_le32(VIRTIO_GPU_CMD_UPDATE_CURSOR);
406 output->cursor.resource_id = cpu_to_le32(handle);
407 if (plane->state->fb) {
408 output->cursor.hot_x =
409 cpu_to_le32(plane->state->hotspot_x);
410 output->cursor.hot_y =
411 cpu_to_le32(plane->state->hotspot_y);
412 } else {
413 output->cursor.hot_x = cpu_to_le32(0);
414 output->cursor.hot_y = cpu_to_le32(0);
415 }
416 } else {
417 DRM_DEBUG("move +%d+%d\n",
418 plane->state->crtc_x,
419 plane->state->crtc_y);
420 output->cursor.hdr.type =
421 cpu_to_le32(VIRTIO_GPU_CMD_MOVE_CURSOR);
422 }
423 output->cursor.pos.x = cpu_to_le32(plane->state->crtc_x);
424 output->cursor.pos.y = cpu_to_le32(plane->state->crtc_y);
425 virtio_gpu_cursor_ping(vgdev, output);
426 }
427
428 static const struct drm_plane_helper_funcs virtio_gpu_primary_helper_funcs = {
429 .prepare_fb = virtio_gpu_plane_prepare_fb,
430 .cleanup_fb = virtio_gpu_plane_cleanup_fb,
431 .atomic_check = virtio_gpu_plane_atomic_check,
432 .atomic_update = virtio_gpu_primary_plane_update,
433 };
434
435 static const struct drm_plane_helper_funcs virtio_gpu_cursor_helper_funcs = {
436 .prepare_fb = virtio_gpu_plane_prepare_fb,
437 .cleanup_fb = virtio_gpu_plane_cleanup_fb,
438 .atomic_check = virtio_gpu_plane_atomic_check,
439 .atomic_update = virtio_gpu_cursor_plane_update,
440 };
441
virtio_gpu_plane_init(struct virtio_gpu_device * vgdev,enum drm_plane_type type,int index)442 struct drm_plane *virtio_gpu_plane_init(struct virtio_gpu_device *vgdev,
443 enum drm_plane_type type,
444 int index)
445 {
446 struct drm_device *dev = vgdev->ddev;
447 const struct drm_plane_helper_funcs *funcs;
448 struct drm_plane *plane;
449 const uint32_t *formats;
450 int nformats;
451
452 if (type == DRM_PLANE_TYPE_CURSOR) {
453 formats = virtio_gpu_cursor_formats;
454 nformats = ARRAY_SIZE(virtio_gpu_cursor_formats);
455 funcs = &virtio_gpu_cursor_helper_funcs;
456 } else {
457 formats = virtio_gpu_formats;
458 nformats = ARRAY_SIZE(virtio_gpu_formats);
459 funcs = &virtio_gpu_primary_helper_funcs;
460 }
461
462 plane = drmm_universal_plane_alloc(dev, struct drm_plane, dev,
463 1 << index, &virtio_gpu_plane_funcs,
464 formats, nformats, NULL, type, NULL);
465 if (IS_ERR(plane))
466 return plane;
467
468 drm_plane_helper_add(plane, funcs);
469
470 if (type == DRM_PLANE_TYPE_PRIMARY)
471 drm_plane_enable_fb_damage_clips(plane);
472
473 return plane;
474 }
475