1 // SPDX-License-Identifier: MIT
2 /*
3 * Copyright 2023, Intel Corporation.
4 */
5
6 #include "i915_vma.h"
7 #include "intel_display_types.h"
8 #include "intel_dsb_buffer.h"
9 #include "xe_bo.h"
10 #include "xe_device.h"
11 #include "xe_device_types.h"
12
intel_dsb_buffer_ggtt_offset(struct intel_dsb_buffer * dsb_buf)13 u32 intel_dsb_buffer_ggtt_offset(struct intel_dsb_buffer *dsb_buf)
14 {
15 return xe_bo_ggtt_addr(dsb_buf->vma->bo);
16 }
17
intel_dsb_buffer_write(struct intel_dsb_buffer * dsb_buf,u32 idx,u32 val)18 void intel_dsb_buffer_write(struct intel_dsb_buffer *dsb_buf, u32 idx, u32 val)
19 {
20 iosys_map_wr(&dsb_buf->vma->bo->vmap, idx * 4, u32, val);
21 }
22
intel_dsb_buffer_read(struct intel_dsb_buffer * dsb_buf,u32 idx)23 u32 intel_dsb_buffer_read(struct intel_dsb_buffer *dsb_buf, u32 idx)
24 {
25 return iosys_map_rd(&dsb_buf->vma->bo->vmap, idx * 4, u32);
26 }
27
intel_dsb_buffer_memset(struct intel_dsb_buffer * dsb_buf,u32 idx,u32 val,size_t size)28 void intel_dsb_buffer_memset(struct intel_dsb_buffer *dsb_buf, u32 idx, u32 val, size_t size)
29 {
30 WARN_ON(idx > (dsb_buf->buf_size - size) / sizeof(*dsb_buf->cmd_buf));
31
32 iosys_map_memset(&dsb_buf->vma->bo->vmap, idx * 4, val, size);
33 }
34
intel_dsb_buffer_create(struct intel_crtc * crtc,struct intel_dsb_buffer * dsb_buf,size_t size)35 bool intel_dsb_buffer_create(struct intel_crtc *crtc, struct intel_dsb_buffer *dsb_buf, size_t size)
36 {
37 struct xe_device *xe = to_xe_device(crtc->base.dev);
38 struct xe_bo *obj;
39 struct i915_vma *vma;
40
41 vma = kzalloc(sizeof(*vma), GFP_KERNEL);
42 if (!vma)
43 return false;
44
45 /* Set scanout flag for WC mapping */
46 obj = xe_bo_create_pin_map(xe, xe_device_get_root_tile(xe),
47 NULL, PAGE_ALIGN(size),
48 ttm_bo_type_kernel,
49 XE_BO_FLAG_VRAM_IF_DGFX(xe_device_get_root_tile(xe)) |
50 XE_BO_FLAG_SCANOUT | XE_BO_FLAG_GGTT);
51 if (IS_ERR(obj)) {
52 kfree(vma);
53 return false;
54 }
55
56 vma->bo = obj;
57 dsb_buf->vma = vma;
58 dsb_buf->buf_size = size;
59
60 return true;
61 }
62
intel_dsb_buffer_cleanup(struct intel_dsb_buffer * dsb_buf)63 void intel_dsb_buffer_cleanup(struct intel_dsb_buffer *dsb_buf)
64 {
65 xe_bo_unpin_map_no_vm(dsb_buf->vma->bo);
66 kfree(dsb_buf->vma);
67 }
68
intel_dsb_buffer_flush_map(struct intel_dsb_buffer * dsb_buf)69 void intel_dsb_buffer_flush_map(struct intel_dsb_buffer *dsb_buf)
70 {
71 struct xe_device *xe = dsb_buf->vma->bo->tile->xe;
72
73 /*
74 * The memory barrier here is to ensure coherency of DSB vs MMIO,
75 * both for weak ordering archs and discrete cards.
76 */
77 xe_device_wmb(xe);
78 xe_device_l2_flush(xe);
79 }
80