1 // SPDX-License-Identifier: MIT
2 /*
3 * Copyright © 2021 Intel Corporation
4 */
5
6 #include <drm/ttm/ttm_bo.h>
7
8 #include "intel_display_types.h"
9 #include "intel_dpt.h"
10 #include "intel_fb.h"
11 #include "intel_fb_pin.h"
12 #include "xe_bo.h"
13 #include "xe_device.h"
14 #include "xe_ggtt.h"
15 #include "xe_pm.h"
16
17 static void
write_dpt_rotated(struct xe_bo * bo,struct iosys_map * map,u32 * dpt_ofs,u32 bo_ofs,u32 width,u32 height,u32 src_stride,u32 dst_stride)18 write_dpt_rotated(struct xe_bo *bo, struct iosys_map *map, u32 *dpt_ofs, u32 bo_ofs,
19 u32 width, u32 height, u32 src_stride, u32 dst_stride)
20 {
21 struct xe_device *xe = xe_bo_device(bo);
22 struct xe_ggtt *ggtt = xe_device_get_root_tile(xe)->mem.ggtt;
23 u32 column, row;
24
25 /* TODO: Maybe rewrite so we can traverse the bo addresses sequentially,
26 * by writing dpt/ggtt in a different order?
27 */
28
29 for (column = 0; column < width; column++) {
30 u32 src_idx = src_stride * (height - 1) + column + bo_ofs;
31
32 for (row = 0; row < height; row++) {
33 u64 pte = ggtt->pt_ops->pte_encode_bo(bo, src_idx * XE_PAGE_SIZE,
34 xe->pat.idx[XE_CACHE_NONE]);
35
36 iosys_map_wr(map, *dpt_ofs, u64, pte);
37 *dpt_ofs += 8;
38 src_idx -= src_stride;
39 }
40
41 /* The DE ignores the PTEs for the padding tiles */
42 *dpt_ofs += (dst_stride - height) * 8;
43 }
44
45 /* Align to next page */
46 *dpt_ofs = ALIGN(*dpt_ofs, 4096);
47 }
48
49 static void
write_dpt_remapped(struct xe_bo * bo,struct iosys_map * map,u32 * dpt_ofs,u32 bo_ofs,u32 width,u32 height,u32 src_stride,u32 dst_stride)50 write_dpt_remapped(struct xe_bo *bo, struct iosys_map *map, u32 *dpt_ofs,
51 u32 bo_ofs, u32 width, u32 height, u32 src_stride,
52 u32 dst_stride)
53 {
54 struct xe_device *xe = xe_bo_device(bo);
55 struct xe_ggtt *ggtt = xe_device_get_root_tile(xe)->mem.ggtt;
56 u64 (*pte_encode_bo)(struct xe_bo *bo, u64 bo_offset, u16 pat_index)
57 = ggtt->pt_ops->pte_encode_bo;
58 u32 column, row;
59
60 for (row = 0; row < height; row++) {
61 u32 src_idx = src_stride * row + bo_ofs;
62
63 for (column = 0; column < width; column++) {
64 iosys_map_wr(map, *dpt_ofs, u64,
65 pte_encode_bo(bo, src_idx * XE_PAGE_SIZE,
66 xe->pat.idx[XE_CACHE_NONE]));
67
68 *dpt_ofs += 8;
69 src_idx++;
70 }
71
72 /* The DE ignores the PTEs for the padding tiles */
73 *dpt_ofs += (dst_stride - width) * 8;
74 }
75
76 /* Align to next page */
77 *dpt_ofs = ALIGN(*dpt_ofs, 4096);
78 }
79
__xe_pin_fb_vma_dpt(const struct intel_framebuffer * fb,const struct i915_gtt_view * view,struct i915_vma * vma)80 static int __xe_pin_fb_vma_dpt(const struct intel_framebuffer *fb,
81 const struct i915_gtt_view *view,
82 struct i915_vma *vma)
83 {
84 struct xe_device *xe = to_xe_device(fb->base.dev);
85 struct xe_tile *tile0 = xe_device_get_root_tile(xe);
86 struct xe_ggtt *ggtt = tile0->mem.ggtt;
87 struct xe_bo *bo = intel_fb_obj(&fb->base), *dpt;
88 u32 dpt_size, size = bo->ttm.base.size;
89
90 if (view->type == I915_GTT_VIEW_NORMAL)
91 dpt_size = ALIGN(size / XE_PAGE_SIZE * 8, XE_PAGE_SIZE);
92 else if (view->type == I915_GTT_VIEW_REMAPPED)
93 dpt_size = ALIGN(intel_remapped_info_size(&fb->remapped_view.gtt.remapped) * 8,
94 XE_PAGE_SIZE);
95 else
96 /* display uses 4K tiles instead of bytes here, convert to entries.. */
97 dpt_size = ALIGN(intel_rotation_info_size(&view->rotated) * 8,
98 XE_PAGE_SIZE);
99
100 if (IS_DGFX(xe))
101 dpt = xe_bo_create_pin_map(xe, tile0, NULL, dpt_size,
102 ttm_bo_type_kernel,
103 XE_BO_FLAG_VRAM0 |
104 XE_BO_FLAG_GGTT |
105 XE_BO_FLAG_PAGETABLE);
106 else
107 dpt = xe_bo_create_pin_map(xe, tile0, NULL, dpt_size,
108 ttm_bo_type_kernel,
109 XE_BO_FLAG_STOLEN |
110 XE_BO_FLAG_GGTT |
111 XE_BO_FLAG_PAGETABLE);
112 if (IS_ERR(dpt))
113 dpt = xe_bo_create_pin_map(xe, tile0, NULL, dpt_size,
114 ttm_bo_type_kernel,
115 XE_BO_FLAG_SYSTEM |
116 XE_BO_FLAG_GGTT |
117 XE_BO_FLAG_PAGETABLE);
118 if (IS_ERR(dpt))
119 return PTR_ERR(dpt);
120
121 if (view->type == I915_GTT_VIEW_NORMAL) {
122 u32 x;
123
124 for (x = 0; x < size / XE_PAGE_SIZE; x++) {
125 u64 pte = ggtt->pt_ops->pte_encode_bo(bo, x * XE_PAGE_SIZE,
126 xe->pat.idx[XE_CACHE_NONE]);
127
128 iosys_map_wr(&dpt->vmap, x * 8, u64, pte);
129 }
130 } else if (view->type == I915_GTT_VIEW_REMAPPED) {
131 const struct intel_remapped_info *remap_info = &view->remapped;
132 u32 i, dpt_ofs = 0;
133
134 for (i = 0; i < ARRAY_SIZE(remap_info->plane); i++)
135 write_dpt_remapped(bo, &dpt->vmap, &dpt_ofs,
136 remap_info->plane[i].offset,
137 remap_info->plane[i].width,
138 remap_info->plane[i].height,
139 remap_info->plane[i].src_stride,
140 remap_info->plane[i].dst_stride);
141
142 } else {
143 const struct intel_rotation_info *rot_info = &view->rotated;
144 u32 i, dpt_ofs = 0;
145
146 for (i = 0; i < ARRAY_SIZE(rot_info->plane); i++)
147 write_dpt_rotated(bo, &dpt->vmap, &dpt_ofs,
148 rot_info->plane[i].offset,
149 rot_info->plane[i].width,
150 rot_info->plane[i].height,
151 rot_info->plane[i].src_stride,
152 rot_info->plane[i].dst_stride);
153 }
154
155 vma->dpt = dpt;
156 vma->node = dpt->ggtt_node[tile0->id];
157
158 /* Ensure DPT writes are flushed */
159 xe_device_l2_flush(xe);
160 return 0;
161 }
162
163 static void
write_ggtt_rotated(struct xe_bo * bo,struct xe_ggtt * ggtt,u32 * ggtt_ofs,u32 bo_ofs,u32 width,u32 height,u32 src_stride,u32 dst_stride)164 write_ggtt_rotated(struct xe_bo *bo, struct xe_ggtt *ggtt, u32 *ggtt_ofs, u32 bo_ofs,
165 u32 width, u32 height, u32 src_stride, u32 dst_stride)
166 {
167 struct xe_device *xe = xe_bo_device(bo);
168 u32 column, row;
169
170 for (column = 0; column < width; column++) {
171 u32 src_idx = src_stride * (height - 1) + column + bo_ofs;
172
173 for (row = 0; row < height; row++) {
174 u64 pte = ggtt->pt_ops->pte_encode_bo(bo, src_idx * XE_PAGE_SIZE,
175 xe->pat.idx[XE_CACHE_NONE]);
176
177 ggtt->pt_ops->ggtt_set_pte(ggtt, *ggtt_ofs, pte);
178 *ggtt_ofs += XE_PAGE_SIZE;
179 src_idx -= src_stride;
180 }
181
182 /* The DE ignores the PTEs for the padding tiles */
183 *ggtt_ofs += (dst_stride - height) * XE_PAGE_SIZE;
184 }
185 }
186
__xe_pin_fb_vma_ggtt(const struct intel_framebuffer * fb,const struct i915_gtt_view * view,struct i915_vma * vma)187 static int __xe_pin_fb_vma_ggtt(const struct intel_framebuffer *fb,
188 const struct i915_gtt_view *view,
189 struct i915_vma *vma)
190 {
191 struct xe_bo *bo = intel_fb_obj(&fb->base);
192 struct xe_device *xe = to_xe_device(fb->base.dev);
193 struct xe_ggtt *ggtt = xe_device_get_root_tile(xe)->mem.ggtt;
194 u32 align;
195 int ret;
196
197 /* TODO: Consider sharing framebuffer mapping?
198 * embed i915_vma inside intel_framebuffer
199 */
200 xe_pm_runtime_get_noresume(tile_to_xe(ggtt->tile));
201 ret = mutex_lock_interruptible(&ggtt->lock);
202 if (ret)
203 goto out;
204
205 align = XE_PAGE_SIZE;
206 if (xe_bo_is_vram(bo) && ggtt->flags & XE_GGTT_FLAGS_64K)
207 align = max_t(u32, align, SZ_64K);
208
209 if (bo->ggtt_node[ggtt->tile->id] && view->type == I915_GTT_VIEW_NORMAL) {
210 vma->node = bo->ggtt_node[ggtt->tile->id];
211 } else if (view->type == I915_GTT_VIEW_NORMAL) {
212 u32 x, size = bo->ttm.base.size;
213
214 vma->node = xe_ggtt_node_init(ggtt);
215 if (IS_ERR(vma->node)) {
216 ret = PTR_ERR(vma->node);
217 goto out_unlock;
218 }
219
220 ret = xe_ggtt_node_insert_locked(vma->node, size, align, 0);
221 if (ret) {
222 xe_ggtt_node_fini(vma->node);
223 goto out_unlock;
224 }
225
226 for (x = 0; x < size; x += XE_PAGE_SIZE) {
227 u64 pte = ggtt->pt_ops->pte_encode_bo(bo, x,
228 xe->pat.idx[XE_CACHE_NONE]);
229
230 ggtt->pt_ops->ggtt_set_pte(ggtt, vma->node->base.start + x, pte);
231 }
232 } else {
233 u32 i, ggtt_ofs;
234 const struct intel_rotation_info *rot_info = &view->rotated;
235
236 /* display seems to use tiles instead of bytes here, so convert it back.. */
237 u32 size = intel_rotation_info_size(rot_info) * XE_PAGE_SIZE;
238
239 vma->node = xe_ggtt_node_init(ggtt);
240 if (IS_ERR(vma->node)) {
241 ret = PTR_ERR(vma->node);
242 goto out_unlock;
243 }
244
245 ret = xe_ggtt_node_insert_locked(vma->node, size, align, 0);
246 if (ret) {
247 xe_ggtt_node_fini(vma->node);
248 goto out_unlock;
249 }
250
251 ggtt_ofs = vma->node->base.start;
252
253 for (i = 0; i < ARRAY_SIZE(rot_info->plane); i++)
254 write_ggtt_rotated(bo, ggtt, &ggtt_ofs,
255 rot_info->plane[i].offset,
256 rot_info->plane[i].width,
257 rot_info->plane[i].height,
258 rot_info->plane[i].src_stride,
259 rot_info->plane[i].dst_stride);
260 }
261
262 out_unlock:
263 mutex_unlock(&ggtt->lock);
264 out:
265 xe_pm_runtime_put(tile_to_xe(ggtt->tile));
266 return ret;
267 }
268
__xe_pin_fb_vma(const struct intel_framebuffer * fb,const struct i915_gtt_view * view)269 static struct i915_vma *__xe_pin_fb_vma(const struct intel_framebuffer *fb,
270 const struct i915_gtt_view *view)
271 {
272 struct drm_device *dev = fb->base.dev;
273 struct xe_device *xe = to_xe_device(dev);
274 struct i915_vma *vma = kzalloc(sizeof(*vma), GFP_KERNEL);
275 struct xe_bo *bo = intel_fb_obj(&fb->base);
276 int ret;
277
278 if (!vma)
279 return ERR_PTR(-ENODEV);
280
281 if (IS_DGFX(to_xe_device(bo->ttm.base.dev)) &&
282 intel_fb_rc_ccs_cc_plane(&fb->base) >= 0 &&
283 !(bo->flags & XE_BO_FLAG_NEEDS_CPU_ACCESS)) {
284 struct xe_tile *tile = xe_device_get_root_tile(xe);
285
286 /*
287 * If we need to able to access the clear-color value stored in
288 * the buffer, then we require that such buffers are also CPU
289 * accessible. This is important on small-bar systems where
290 * only some subset of VRAM is CPU accessible.
291 */
292 if (tile->mem.vram.io_size < tile->mem.vram.usable_size) {
293 ret = -EINVAL;
294 goto err;
295 }
296 }
297
298 /*
299 * Pin the framebuffer, we can't use xe_bo_(un)pin functions as the
300 * assumptions are incorrect for framebuffers
301 */
302 ret = ttm_bo_reserve(&bo->ttm, false, false, NULL);
303 if (ret)
304 goto err;
305
306 if (IS_DGFX(xe))
307 ret = xe_bo_migrate(bo, XE_PL_VRAM0);
308 else
309 ret = xe_bo_validate(bo, NULL, true);
310 if (!ret)
311 ttm_bo_pin(&bo->ttm);
312 ttm_bo_unreserve(&bo->ttm);
313 if (ret)
314 goto err;
315
316 vma->bo = bo;
317 if (intel_fb_uses_dpt(&fb->base))
318 ret = __xe_pin_fb_vma_dpt(fb, view, vma);
319 else
320 ret = __xe_pin_fb_vma_ggtt(fb, view, vma);
321 if (ret)
322 goto err_unpin;
323
324 return vma;
325
326 err_unpin:
327 ttm_bo_reserve(&bo->ttm, false, false, NULL);
328 ttm_bo_unpin(&bo->ttm);
329 ttm_bo_unreserve(&bo->ttm);
330 err:
331 kfree(vma);
332 return ERR_PTR(ret);
333 }
334
__xe_unpin_fb_vma(struct i915_vma * vma)335 static void __xe_unpin_fb_vma(struct i915_vma *vma)
336 {
337 u8 tile_id = vma->node->ggtt->tile->id;
338
339 if (vma->dpt)
340 xe_bo_unpin_map_no_vm(vma->dpt);
341 else if (!xe_ggtt_node_allocated(vma->bo->ggtt_node[tile_id]) ||
342 vma->bo->ggtt_node[tile_id]->base.start != vma->node->base.start)
343 xe_ggtt_node_remove(vma->node, false);
344
345 ttm_bo_reserve(&vma->bo->ttm, false, false, NULL);
346 ttm_bo_unpin(&vma->bo->ttm);
347 ttm_bo_unreserve(&vma->bo->ttm);
348 kfree(vma);
349 }
350
351 struct i915_vma *
intel_fb_pin_to_ggtt(const struct drm_framebuffer * fb,const struct i915_gtt_view * view,unsigned int alignment,unsigned int phys_alignment,bool uses_fence,unsigned long * out_flags)352 intel_fb_pin_to_ggtt(const struct drm_framebuffer *fb,
353 const struct i915_gtt_view *view,
354 unsigned int alignment,
355 unsigned int phys_alignment,
356 bool uses_fence,
357 unsigned long *out_flags)
358 {
359 *out_flags = 0;
360
361 return __xe_pin_fb_vma(to_intel_framebuffer(fb), view);
362 }
363
intel_fb_unpin_vma(struct i915_vma * vma,unsigned long flags)364 void intel_fb_unpin_vma(struct i915_vma *vma, unsigned long flags)
365 {
366 __xe_unpin_fb_vma(vma);
367 }
368
intel_plane_pin_fb(struct intel_plane_state * plane_state)369 int intel_plane_pin_fb(struct intel_plane_state *plane_state)
370 {
371 struct drm_framebuffer *fb = plane_state->hw.fb;
372 struct xe_bo *bo = intel_fb_obj(fb);
373 struct i915_vma *vma;
374
375 /* We reject creating !SCANOUT fb's, so this is weird.. */
376 drm_WARN_ON(bo->ttm.base.dev, !(bo->flags & XE_BO_FLAG_SCANOUT));
377
378 vma = __xe_pin_fb_vma(to_intel_framebuffer(fb), &plane_state->view.gtt);
379 if (IS_ERR(vma))
380 return PTR_ERR(vma);
381
382 plane_state->ggtt_vma = vma;
383 return 0;
384 }
385
intel_plane_unpin_fb(struct intel_plane_state * old_plane_state)386 void intel_plane_unpin_fb(struct intel_plane_state *old_plane_state)
387 {
388 __xe_unpin_fb_vma(old_plane_state->ggtt_vma);
389 old_plane_state->ggtt_vma = NULL;
390 }
391
392 /*
393 * For Xe introduce dummy intel_dpt_create which just return NULL,
394 * intel_dpt_destroy which does nothing, and fake intel_dpt_ofsset returning 0;
395 */
intel_dpt_create(struct intel_framebuffer * fb)396 struct i915_address_space *intel_dpt_create(struct intel_framebuffer *fb)
397 {
398 return NULL;
399 }
400
intel_dpt_destroy(struct i915_address_space * vm)401 void intel_dpt_destroy(struct i915_address_space *vm)
402 {
403 return;
404 }
405
intel_dpt_offset(struct i915_vma * dpt_vma)406 u64 intel_dpt_offset(struct i915_vma *dpt_vma)
407 {
408 return 0;
409 }
410