1 // SPDX-License-Identifier: MIT
2 /*
3 * Copyright © 2021 Intel Corporation
4 */
5
6 #include "xe_pci.h"
7
8 #include <kunit/static_stub.h>
9 #include <linux/device/driver.h>
10 #include <linux/module.h>
11 #include <linux/pci.h>
12 #include <linux/pm_runtime.h>
13
14 #include <drm/drm_color_mgmt.h>
15 #include <drm/drm_drv.h>
16 #include <drm/intel/xe_pciids.h>
17
18 #include "display/xe_display.h"
19 #include "regs/xe_gt_regs.h"
20 #include "xe_device.h"
21 #include "xe_drv.h"
22 #include "xe_gt.h"
23 #include "xe_gt_sriov_vf.h"
24 #include "xe_guc.h"
25 #include "xe_macros.h"
26 #include "xe_mmio.h"
27 #include "xe_module.h"
28 #include "xe_pci_sriov.h"
29 #include "xe_pci_types.h"
30 #include "xe_pm.h"
31 #include "xe_sriov.h"
32 #include "xe_step.h"
33 #include "xe_tile.h"
34
35 enum toggle_d3cold {
36 D3COLD_DISABLE,
37 D3COLD_ENABLE,
38 };
39
40 struct xe_subplatform_desc {
41 enum xe_subplatform subplatform;
42 const char *name;
43 const u16 *pciidlist;
44 };
45
46 struct xe_device_desc {
47 /* Should only ever be set for platforms without GMD_ID */
48 const struct xe_graphics_desc *graphics;
49 /* Should only ever be set for platforms without GMD_ID */
50 const struct xe_media_desc *media;
51
52 const char *platform_name;
53 const struct xe_subplatform_desc *subplatforms;
54
55 enum xe_platform platform;
56
57 u8 require_force_probe:1;
58 u8 is_dgfx:1;
59
60 u8 has_display:1;
61 u8 has_heci_gscfi:1;
62 u8 has_heci_cscfi:1;
63 u8 has_llc:1;
64 u8 has_mmio_ext:1;
65 u8 has_sriov:1;
66 u8 skip_guc_pc:1;
67 u8 skip_mtcfg:1;
68 u8 skip_pcode:1;
69 };
70
71 __diag_push();
72 __diag_ignore_all("-Woverride-init", "Allow field overrides in table");
73
74 #define PLATFORM(x) \
75 .platform = XE_##x, \
76 .platform_name = #x
77
78 #define NOP(x) x
79
80 static const struct xe_graphics_desc graphics_xelp = {
81 .name = "Xe_LP",
82 .ver = 12,
83 .rel = 0,
84
85 .hw_engine_mask = BIT(XE_HW_ENGINE_RCS0) | BIT(XE_HW_ENGINE_BCS0),
86
87 .dma_mask_size = 39,
88 .va_bits = 48,
89 .vm_max_level = 3,
90 };
91
92 static const struct xe_graphics_desc graphics_xelpp = {
93 .name = "Xe_LP+",
94 .ver = 12,
95 .rel = 10,
96
97 .hw_engine_mask = BIT(XE_HW_ENGINE_RCS0) | BIT(XE_HW_ENGINE_BCS0),
98
99 .dma_mask_size = 39,
100 .va_bits = 48,
101 .vm_max_level = 3,
102 };
103
104 #define XE_HP_FEATURES \
105 .has_range_tlb_invalidation = true, \
106 .has_flat_ccs = true, \
107 .dma_mask_size = 46, \
108 .va_bits = 48, \
109 .vm_max_level = 3
110
111 static const struct xe_graphics_desc graphics_xehpg = {
112 .name = "Xe_HPG",
113 .ver = 12,
114 .rel = 55,
115
116 .hw_engine_mask =
117 BIT(XE_HW_ENGINE_RCS0) | BIT(XE_HW_ENGINE_BCS0) |
118 BIT(XE_HW_ENGINE_CCS0) | BIT(XE_HW_ENGINE_CCS1) |
119 BIT(XE_HW_ENGINE_CCS2) | BIT(XE_HW_ENGINE_CCS3),
120
121 XE_HP_FEATURES,
122 .vram_flags = XE_VRAM_FLAGS_NEED64K,
123 };
124
125 static const struct xe_graphics_desc graphics_xehpc = {
126 .name = "Xe_HPC",
127 .ver = 12,
128 .rel = 60,
129
130 .hw_engine_mask =
131 BIT(XE_HW_ENGINE_BCS0) | BIT(XE_HW_ENGINE_BCS1) |
132 BIT(XE_HW_ENGINE_BCS2) | BIT(XE_HW_ENGINE_BCS3) |
133 BIT(XE_HW_ENGINE_BCS4) | BIT(XE_HW_ENGINE_BCS5) |
134 BIT(XE_HW_ENGINE_BCS6) | BIT(XE_HW_ENGINE_BCS7) |
135 BIT(XE_HW_ENGINE_BCS8) |
136 BIT(XE_HW_ENGINE_CCS0) | BIT(XE_HW_ENGINE_CCS1) |
137 BIT(XE_HW_ENGINE_CCS2) | BIT(XE_HW_ENGINE_CCS3),
138
139 XE_HP_FEATURES,
140 .dma_mask_size = 52,
141 .max_remote_tiles = 1,
142 .va_bits = 57,
143 .vm_max_level = 4,
144 .vram_flags = XE_VRAM_FLAGS_NEED64K,
145
146 .has_asid = 1,
147 .has_atomic_enable_pte_bit = 1,
148 .has_flat_ccs = 0,
149 .has_usm = 1,
150 };
151
152 static const struct xe_graphics_desc graphics_xelpg = {
153 .name = "Xe_LPG",
154 .hw_engine_mask =
155 BIT(XE_HW_ENGINE_RCS0) | BIT(XE_HW_ENGINE_BCS0) |
156 BIT(XE_HW_ENGINE_CCS0),
157
158 XE_HP_FEATURES,
159 .has_flat_ccs = 0,
160 };
161
162 #define XE2_GFX_FEATURES \
163 .dma_mask_size = 46, \
164 .has_asid = 1, \
165 .has_atomic_enable_pte_bit = 1, \
166 .has_flat_ccs = 1, \
167 .has_range_tlb_invalidation = 1, \
168 .has_usm = 1, \
169 .va_bits = 48, \
170 .vm_max_level = 4, \
171 .hw_engine_mask = \
172 BIT(XE_HW_ENGINE_RCS0) | \
173 BIT(XE_HW_ENGINE_BCS8) | BIT(XE_HW_ENGINE_BCS0) | \
174 GENMASK(XE_HW_ENGINE_CCS3, XE_HW_ENGINE_CCS0)
175
176 static const struct xe_graphics_desc graphics_xe2 = {
177 .name = "Xe2_LPG / Xe2_HPG",
178
179 XE2_GFX_FEATURES,
180 };
181
182 static const struct xe_media_desc media_xem = {
183 .name = "Xe_M",
184 .ver = 12,
185 .rel = 0,
186
187 .hw_engine_mask =
188 GENMASK(XE_HW_ENGINE_VCS7, XE_HW_ENGINE_VCS0) |
189 GENMASK(XE_HW_ENGINE_VECS3, XE_HW_ENGINE_VECS0),
190 };
191
192 static const struct xe_media_desc media_xehpm = {
193 .name = "Xe_HPM",
194 .ver = 12,
195 .rel = 55,
196
197 .hw_engine_mask =
198 GENMASK(XE_HW_ENGINE_VCS7, XE_HW_ENGINE_VCS0) |
199 GENMASK(XE_HW_ENGINE_VECS3, XE_HW_ENGINE_VECS0),
200 };
201
202 static const struct xe_media_desc media_xelpmp = {
203 .name = "Xe_LPM+",
204 .hw_engine_mask =
205 GENMASK(XE_HW_ENGINE_VCS7, XE_HW_ENGINE_VCS0) |
206 GENMASK(XE_HW_ENGINE_VECS3, XE_HW_ENGINE_VECS0) |
207 BIT(XE_HW_ENGINE_GSCCS0)
208 };
209
210 static const struct xe_media_desc media_xe2 = {
211 .name = "Xe2_LPM / Xe2_HPM",
212 .hw_engine_mask =
213 GENMASK(XE_HW_ENGINE_VCS7, XE_HW_ENGINE_VCS0) |
214 GENMASK(XE_HW_ENGINE_VECS3, XE_HW_ENGINE_VECS0) |
215 BIT(XE_HW_ENGINE_GSCCS0)
216 };
217
218 static const struct xe_device_desc tgl_desc = {
219 .graphics = &graphics_xelp,
220 .media = &media_xem,
221 PLATFORM(TIGERLAKE),
222 .has_display = true,
223 .has_llc = true,
224 .require_force_probe = true,
225 };
226
227 static const struct xe_device_desc rkl_desc = {
228 .graphics = &graphics_xelp,
229 .media = &media_xem,
230 PLATFORM(ROCKETLAKE),
231 .has_display = true,
232 .has_llc = true,
233 .require_force_probe = true,
234 };
235
236 static const u16 adls_rpls_ids[] = { XE_RPLS_IDS(NOP), 0 };
237
238 static const struct xe_device_desc adl_s_desc = {
239 .graphics = &graphics_xelp,
240 .media = &media_xem,
241 PLATFORM(ALDERLAKE_S),
242 .has_display = true,
243 .has_llc = true,
244 .require_force_probe = true,
245 .subplatforms = (const struct xe_subplatform_desc[]) {
246 { XE_SUBPLATFORM_ALDERLAKE_S_RPLS, "RPLS", adls_rpls_ids },
247 {},
248 },
249 };
250
251 static const u16 adlp_rplu_ids[] = { XE_RPLU_IDS(NOP), 0 };
252
253 static const struct xe_device_desc adl_p_desc = {
254 .graphics = &graphics_xelp,
255 .media = &media_xem,
256 PLATFORM(ALDERLAKE_P),
257 .has_display = true,
258 .has_llc = true,
259 .require_force_probe = true,
260 .subplatforms = (const struct xe_subplatform_desc[]) {
261 { XE_SUBPLATFORM_ALDERLAKE_P_RPLU, "RPLU", adlp_rplu_ids },
262 {},
263 },
264 };
265
266 static const struct xe_device_desc adl_n_desc = {
267 .graphics = &graphics_xelp,
268 .media = &media_xem,
269 PLATFORM(ALDERLAKE_N),
270 .has_display = true,
271 .has_llc = true,
272 .require_force_probe = true,
273 };
274
275 #define DGFX_FEATURES \
276 .is_dgfx = 1
277
278 static const struct xe_device_desc dg1_desc = {
279 .graphics = &graphics_xelpp,
280 .media = &media_xem,
281 DGFX_FEATURES,
282 PLATFORM(DG1),
283 .has_display = true,
284 .has_heci_gscfi = 1,
285 .require_force_probe = true,
286 };
287
288 static const u16 dg2_g10_ids[] = { XE_DG2_G10_IDS(NOP), XE_ATS_M150_IDS(NOP), 0 };
289 static const u16 dg2_g11_ids[] = { XE_DG2_G11_IDS(NOP), XE_ATS_M75_IDS(NOP), 0 };
290 static const u16 dg2_g12_ids[] = { XE_DG2_G12_IDS(NOP), 0 };
291
292 #define DG2_FEATURES \
293 DGFX_FEATURES, \
294 PLATFORM(DG2), \
295 .has_heci_gscfi = 1, \
296 .subplatforms = (const struct xe_subplatform_desc[]) { \
297 { XE_SUBPLATFORM_DG2_G10, "G10", dg2_g10_ids }, \
298 { XE_SUBPLATFORM_DG2_G11, "G11", dg2_g11_ids }, \
299 { XE_SUBPLATFORM_DG2_G12, "G12", dg2_g12_ids }, \
300 { } \
301 }
302
303 static const struct xe_device_desc ats_m_desc = {
304 .graphics = &graphics_xehpg,
305 .media = &media_xehpm,
306 .require_force_probe = true,
307
308 DG2_FEATURES,
309 .has_display = false,
310 };
311
312 static const struct xe_device_desc dg2_desc = {
313 .graphics = &graphics_xehpg,
314 .media = &media_xehpm,
315 .require_force_probe = true,
316
317 DG2_FEATURES,
318 .has_display = true,
319 };
320
321 static const __maybe_unused struct xe_device_desc pvc_desc = {
322 .graphics = &graphics_xehpc,
323 DGFX_FEATURES,
324 PLATFORM(PVC),
325 .has_display = false,
326 .has_heci_gscfi = 1,
327 .require_force_probe = true,
328 };
329
330 static const struct xe_device_desc mtl_desc = {
331 /* .graphics and .media determined via GMD_ID */
332 .require_force_probe = true,
333 PLATFORM(METEORLAKE),
334 .has_display = true,
335 };
336
337 static const struct xe_device_desc lnl_desc = {
338 PLATFORM(LUNARLAKE),
339 .has_display = true,
340 };
341
342 static const struct xe_device_desc bmg_desc = {
343 DGFX_FEATURES,
344 PLATFORM(BATTLEMAGE),
345 .has_display = true,
346 .has_heci_cscfi = 1,
347 };
348
349 #undef PLATFORM
350 __diag_pop();
351
352 /* Map of GMD_ID values to graphics IP */
353 static const struct gmdid_map graphics_ip_map[] = {
354 { 1270, &graphics_xelpg },
355 { 1271, &graphics_xelpg },
356 { 1274, &graphics_xelpg }, /* Xe_LPG+ */
357 { 2001, &graphics_xe2 },
358 { 2004, &graphics_xe2 },
359 };
360
361 /* Map of GMD_ID values to media IP */
362 static const struct gmdid_map media_ip_map[] = {
363 { 1300, &media_xelpmp },
364 { 1301, &media_xe2 },
365 { 2000, &media_xe2 },
366 };
367
368 #define INTEL_VGA_DEVICE(id, info) { \
369 PCI_DEVICE(PCI_VENDOR_ID_INTEL, id), \
370 PCI_BASE_CLASS_DISPLAY << 16, 0xff << 16, \
371 (unsigned long) info }
372
373 /*
374 * Make sure any device matches here are from most specific to most
375 * general. For example, since the Quanta match is based on the subsystem
376 * and subvendor IDs, we need it to come before the more general IVB
377 * PCI ID matches, otherwise we'll use the wrong info struct above.
378 */
379 static const struct pci_device_id pciidlist[] = {
380 XE_TGL_IDS(INTEL_VGA_DEVICE, &tgl_desc),
381 XE_RKL_IDS(INTEL_VGA_DEVICE, &rkl_desc),
382 XE_ADLS_IDS(INTEL_VGA_DEVICE, &adl_s_desc),
383 XE_ADLP_IDS(INTEL_VGA_DEVICE, &adl_p_desc),
384 XE_ADLN_IDS(INTEL_VGA_DEVICE, &adl_n_desc),
385 XE_RPLU_IDS(INTEL_VGA_DEVICE, &adl_p_desc),
386 XE_RPLP_IDS(INTEL_VGA_DEVICE, &adl_p_desc),
387 XE_RPLS_IDS(INTEL_VGA_DEVICE, &adl_s_desc),
388 XE_DG1_IDS(INTEL_VGA_DEVICE, &dg1_desc),
389 XE_ATS_M_IDS(INTEL_VGA_DEVICE, &ats_m_desc),
390 XE_ARL_IDS(INTEL_VGA_DEVICE, &mtl_desc),
391 XE_DG2_IDS(INTEL_VGA_DEVICE, &dg2_desc),
392 XE_MTL_IDS(INTEL_VGA_DEVICE, &mtl_desc),
393 XE_LNL_IDS(INTEL_VGA_DEVICE, &lnl_desc),
394 XE_BMG_IDS(INTEL_VGA_DEVICE, &bmg_desc),
395 { }
396 };
397 MODULE_DEVICE_TABLE(pci, pciidlist);
398
399 #undef INTEL_VGA_DEVICE
400
401 /* is device_id present in comma separated list of ids */
device_id_in_list(u16 device_id,const char * devices,bool negative)402 static bool device_id_in_list(u16 device_id, const char *devices, bool negative)
403 {
404 char *s, *p, *tok;
405 bool ret;
406
407 if (!devices || !*devices)
408 return false;
409
410 /* match everything */
411 if (negative && strcmp(devices, "!*") == 0)
412 return true;
413 if (!negative && strcmp(devices, "*") == 0)
414 return true;
415
416 s = kstrdup(devices, GFP_KERNEL);
417 if (!s)
418 return false;
419
420 for (p = s, ret = false; (tok = strsep(&p, ",")) != NULL; ) {
421 u16 val;
422
423 if (negative && tok[0] == '!')
424 tok++;
425 else if ((negative && tok[0] != '!') ||
426 (!negative && tok[0] == '!'))
427 continue;
428
429 if (kstrtou16(tok, 16, &val) == 0 && val == device_id) {
430 ret = true;
431 break;
432 }
433 }
434
435 kfree(s);
436
437 return ret;
438 }
439
id_forced(u16 device_id)440 static bool id_forced(u16 device_id)
441 {
442 return device_id_in_list(device_id, xe_modparam.force_probe, false);
443 }
444
id_blocked(u16 device_id)445 static bool id_blocked(u16 device_id)
446 {
447 return device_id_in_list(device_id, xe_modparam.force_probe, true);
448 }
449
450 static const struct xe_subplatform_desc *
find_subplatform(const struct xe_device * xe,const struct xe_device_desc * desc)451 find_subplatform(const struct xe_device *xe, const struct xe_device_desc *desc)
452 {
453 const struct xe_subplatform_desc *sp;
454 const u16 *id;
455
456 for (sp = desc->subplatforms; sp && sp->subplatform; sp++)
457 for (id = sp->pciidlist; *id; id++)
458 if (*id == xe->info.devid)
459 return sp;
460
461 return NULL;
462 }
463
464 enum xe_gmdid_type {
465 GMDID_GRAPHICS,
466 GMDID_MEDIA
467 };
468
read_gmdid(struct xe_device * xe,enum xe_gmdid_type type,u32 * ver,u32 * revid)469 static void read_gmdid(struct xe_device *xe, enum xe_gmdid_type type, u32 *ver, u32 *revid)
470 {
471 struct xe_gt *gt = xe_root_mmio_gt(xe);
472 struct xe_reg gmdid_reg = GMD_ID;
473 u32 val;
474
475 KUNIT_STATIC_STUB_REDIRECT(read_gmdid, xe, type, ver, revid);
476
477 if (IS_SRIOV_VF(xe)) {
478 /*
479 * To get the value of the GMDID register, VFs must obtain it
480 * from the GuC using MMIO communication.
481 *
482 * Note that at this point the xe_gt is not fully uninitialized
483 * and only basic access to MMIO registers is possible. To use
484 * our existing GuC communication functions we must perform at
485 * least basic xe_gt and xe_guc initialization.
486 *
487 * Since to obtain the value of GMDID_MEDIA we need to use the
488 * media GuC, temporarly tweak the gt type.
489 */
490 xe_gt_assert(gt, gt->info.type == XE_GT_TYPE_UNINITIALIZED);
491
492 if (type == GMDID_MEDIA) {
493 gt->info.id = 1;
494 gt->info.type = XE_GT_TYPE_MEDIA;
495 } else {
496 gt->info.id = 0;
497 gt->info.type = XE_GT_TYPE_MAIN;
498 }
499
500 xe_guc_comm_init_early(>->uc.guc);
501
502 /* Don't bother with GMDID if failed to negotiate the GuC ABI */
503 val = xe_gt_sriov_vf_bootstrap(gt) ? 0 : xe_gt_sriov_vf_gmdid(gt);
504
505 /*
506 * Only undo xe_gt.info here, the remaining changes made above
507 * will be overwritten as part of the regular initialization.
508 */
509 gt->info.id = 0;
510 gt->info.type = XE_GT_TYPE_UNINITIALIZED;
511 } else {
512 /*
513 * We need to apply the GSI offset explicitly here as at this
514 * point the xe_gt is not fully uninitialized and only basic
515 * access to MMIO registers is possible.
516 */
517 if (type == GMDID_MEDIA)
518 gmdid_reg.addr += MEDIA_GT_GSI_OFFSET;
519
520 val = xe_mmio_read32(gt, gmdid_reg);
521 }
522
523 *ver = REG_FIELD_GET(GMD_ID_ARCH_MASK, val) * 100 + REG_FIELD_GET(GMD_ID_RELEASE_MASK, val);
524 *revid = REG_FIELD_GET(GMD_ID_REVID, val);
525 }
526
527 /*
528 * Pre-GMD_ID platform: device descriptor already points to the appropriate
529 * graphics descriptor. Simply forward the description and calculate the version
530 * appropriately. "graphics" should be present in all such platforms, while
531 * media is optional.
532 */
handle_pre_gmdid(struct xe_device * xe,const struct xe_graphics_desc * graphics,const struct xe_media_desc * media)533 static void handle_pre_gmdid(struct xe_device *xe,
534 const struct xe_graphics_desc *graphics,
535 const struct xe_media_desc *media)
536 {
537 xe->info.graphics_verx100 = graphics->ver * 100 + graphics->rel;
538
539 if (media)
540 xe->info.media_verx100 = media->ver * 100 + media->rel;
541
542 }
543
544 /*
545 * GMD_ID platform: read IP version from hardware and select graphics descriptor
546 * based on the result.
547 */
handle_gmdid(struct xe_device * xe,const struct xe_graphics_desc ** graphics,const struct xe_media_desc ** media,u32 * graphics_revid,u32 * media_revid)548 static void handle_gmdid(struct xe_device *xe,
549 const struct xe_graphics_desc **graphics,
550 const struct xe_media_desc **media,
551 u32 *graphics_revid,
552 u32 *media_revid)
553 {
554 u32 ver;
555
556 read_gmdid(xe, GMDID_GRAPHICS, &ver, graphics_revid);
557
558 for (int i = 0; i < ARRAY_SIZE(graphics_ip_map); i++) {
559 if (ver == graphics_ip_map[i].ver) {
560 xe->info.graphics_verx100 = ver;
561 *graphics = graphics_ip_map[i].ip;
562
563 break;
564 }
565 }
566
567 if (!xe->info.graphics_verx100) {
568 drm_err(&xe->drm, "Hardware reports unknown graphics version %u.%02u\n",
569 ver / 100, ver % 100);
570 }
571
572 read_gmdid(xe, GMDID_MEDIA, &ver, media_revid);
573
574 /* Media may legitimately be fused off / not present */
575 if (ver == 0)
576 return;
577
578 for (int i = 0; i < ARRAY_SIZE(media_ip_map); i++) {
579 if (ver == media_ip_map[i].ver) {
580 xe->info.media_verx100 = ver;
581 *media = media_ip_map[i].ip;
582
583 break;
584 }
585 }
586
587 if (!xe->info.media_verx100) {
588 drm_err(&xe->drm, "Hardware reports unknown media version %u.%02u\n",
589 ver / 100, ver % 100);
590 }
591 }
592
593 /*
594 * Initialize device info content that only depends on static driver_data
595 * passed to the driver at probe time from PCI ID table.
596 */
xe_info_init_early(struct xe_device * xe,const struct xe_device_desc * desc,const struct xe_subplatform_desc * subplatform_desc)597 static int xe_info_init_early(struct xe_device *xe,
598 const struct xe_device_desc *desc,
599 const struct xe_subplatform_desc *subplatform_desc)
600 {
601 int err;
602
603 xe->info.platform_name = desc->platform_name;
604 xe->info.platform = desc->platform;
605 xe->info.subplatform = subplatform_desc ?
606 subplatform_desc->subplatform : XE_SUBPLATFORM_NONE;
607
608 xe->info.is_dgfx = desc->is_dgfx;
609 xe->info.has_heci_gscfi = desc->has_heci_gscfi;
610 xe->info.has_heci_cscfi = desc->has_heci_cscfi;
611 xe->info.has_llc = desc->has_llc;
612 xe->info.has_mmio_ext = desc->has_mmio_ext;
613 xe->info.has_sriov = desc->has_sriov;
614 xe->info.skip_guc_pc = desc->skip_guc_pc;
615 xe->info.skip_mtcfg = desc->skip_mtcfg;
616 xe->info.skip_pcode = desc->skip_pcode;
617
618 xe->info.probe_display = IS_ENABLED(CONFIG_DRM_XE_DISPLAY) &&
619 xe_modparam.probe_display &&
620 desc->has_display;
621
622 err = xe_tile_init_early(xe_device_get_root_tile(xe), xe, 0);
623 if (err)
624 return err;
625
626 return 0;
627 }
628
629 /*
630 * Initialize device info content that does require knowledge about
631 * graphics / media IP version.
632 * Make sure that GT / tile structures allocated by the driver match the data
633 * present in device info.
634 */
xe_info_init(struct xe_device * xe,const struct xe_graphics_desc * graphics_desc,const struct xe_media_desc * media_desc)635 static int xe_info_init(struct xe_device *xe,
636 const struct xe_graphics_desc *graphics_desc,
637 const struct xe_media_desc *media_desc)
638 {
639 u32 graphics_gmdid_revid = 0, media_gmdid_revid = 0;
640 struct xe_tile *tile;
641 struct xe_gt *gt;
642 u8 id;
643
644 /*
645 * If this platform supports GMD_ID, we'll detect the proper IP
646 * descriptor to use from hardware registers. desc->graphics will only
647 * ever be set at this point for platforms before GMD_ID. In that case
648 * the IP descriptions and versions are simply derived from that.
649 */
650 if (graphics_desc) {
651 handle_pre_gmdid(xe, graphics_desc, media_desc);
652 xe->info.step = xe_step_pre_gmdid_get(xe);
653 } else {
654 xe_assert(xe, !media_desc);
655 handle_gmdid(xe, &graphics_desc, &media_desc,
656 &graphics_gmdid_revid, &media_gmdid_revid);
657 xe->info.step = xe_step_gmdid_get(xe,
658 graphics_gmdid_revid,
659 media_gmdid_revid);
660 }
661
662 /*
663 * If we couldn't detect the graphics IP, that's considered a fatal
664 * error and we should abort driver load. Failing to detect media
665 * IP is non-fatal; we'll just proceed without enabling media support.
666 */
667 if (!graphics_desc)
668 return -ENODEV;
669
670 xe->info.graphics_name = graphics_desc->name;
671 xe->info.media_name = media_desc ? media_desc->name : "none";
672 xe->info.tile_mmio_ext_size = graphics_desc->tile_mmio_ext_size;
673
674 xe->info.dma_mask_size = graphics_desc->dma_mask_size;
675 xe->info.vram_flags = graphics_desc->vram_flags;
676 xe->info.va_bits = graphics_desc->va_bits;
677 xe->info.vm_max_level = graphics_desc->vm_max_level;
678 xe->info.has_asid = graphics_desc->has_asid;
679 xe->info.has_atomic_enable_pte_bit = graphics_desc->has_atomic_enable_pte_bit;
680 if (xe->info.platform != XE_PVC)
681 xe->info.has_device_atomics_on_smem = 1;
682 xe->info.has_flat_ccs = graphics_desc->has_flat_ccs;
683 xe->info.has_range_tlb_invalidation = graphics_desc->has_range_tlb_invalidation;
684 xe->info.has_usm = graphics_desc->has_usm;
685
686 /*
687 * All platforms have at least one primary GT. Any platform with media
688 * version 13 or higher has an additional dedicated media GT. And
689 * depending on the graphics IP there may be additional "remote tiles."
690 * All of these together determine the overall GT count.
691 *
692 * FIXME: 'tile_count' here is misnamed since the rest of the driver
693 * treats it as the number of GTs rather than just the number of tiles.
694 */
695 xe->info.tile_count = 1 + graphics_desc->max_remote_tiles;
696
697 for_each_remote_tile(tile, xe, id) {
698 int err;
699
700 err = xe_tile_init_early(tile, xe, id);
701 if (err)
702 return err;
703 }
704
705 for_each_tile(tile, xe, id) {
706 gt = tile->primary_gt;
707 gt->info.id = xe->info.gt_count++;
708 gt->info.type = XE_GT_TYPE_MAIN;
709 gt->info.has_indirect_ring_state = graphics_desc->has_indirect_ring_state;
710 gt->info.engine_mask = graphics_desc->hw_engine_mask;
711 if (MEDIA_VER(xe) < 13 && media_desc)
712 gt->info.engine_mask |= media_desc->hw_engine_mask;
713
714 if (MEDIA_VER(xe) < 13 || !media_desc)
715 continue;
716
717 /*
718 * Allocate and setup media GT for platforms with standalone
719 * media.
720 */
721 tile->media_gt = xe_gt_alloc(tile);
722 if (IS_ERR(tile->media_gt))
723 return PTR_ERR(tile->media_gt);
724
725 gt = tile->media_gt;
726 gt->info.type = XE_GT_TYPE_MEDIA;
727 gt->info.has_indirect_ring_state = media_desc->has_indirect_ring_state;
728 gt->info.engine_mask = media_desc->hw_engine_mask;
729 gt->mmio.adj_offset = MEDIA_GT_GSI_OFFSET;
730 gt->mmio.adj_limit = MEDIA_GT_GSI_LENGTH;
731
732 /*
733 * FIXME: At the moment multi-tile and standalone media are
734 * mutually exclusive on current platforms. We'll need to
735 * come up with a better way to number GTs if we ever wind
736 * up with platforms that support both together.
737 */
738 drm_WARN_ON(&xe->drm, id != 0);
739 gt->info.id = xe->info.gt_count++;
740 }
741
742 return 0;
743 }
744
xe_pci_remove(struct pci_dev * pdev)745 static void xe_pci_remove(struct pci_dev *pdev)
746 {
747 struct xe_device *xe;
748
749 xe = pdev_to_xe_device(pdev);
750 if (!xe) /* driver load aborted, nothing to cleanup */
751 return;
752
753 if (IS_SRIOV_PF(xe))
754 xe_pci_sriov_configure(pdev, 0);
755
756 xe_device_remove(xe);
757 xe_pm_runtime_fini(xe);
758 pci_set_drvdata(pdev, NULL);
759 }
760
xe_pci_probe(struct pci_dev * pdev,const struct pci_device_id * ent)761 static int xe_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
762 {
763 const struct xe_device_desc *desc = (const void *)ent->driver_data;
764 const struct xe_subplatform_desc *subplatform_desc;
765 struct xe_device *xe;
766 int err;
767
768 if (desc->require_force_probe && !id_forced(pdev->device)) {
769 dev_info(&pdev->dev,
770 "Your graphics device %04x is not officially supported\n"
771 "by xe driver in this kernel version. To force Xe probe,\n"
772 "use xe.force_probe='%04x' and i915.force_probe='!%04x'\n"
773 "module parameters or CONFIG_DRM_XE_FORCE_PROBE='%04x' and\n"
774 "CONFIG_DRM_I915_FORCE_PROBE='!%04x' configuration options.\n",
775 pdev->device, pdev->device, pdev->device,
776 pdev->device, pdev->device);
777 return -ENODEV;
778 }
779
780 if (id_blocked(pdev->device)) {
781 dev_info(&pdev->dev, "Probe blocked for device [%04x:%04x].\n",
782 pdev->vendor, pdev->device);
783 return -ENODEV;
784 }
785
786 if (xe_display_driver_probe_defer(pdev))
787 return -EPROBE_DEFER;
788
789 err = pcim_enable_device(pdev);
790 if (err)
791 return err;
792
793 xe = xe_device_create(pdev, ent);
794 if (IS_ERR(xe))
795 return PTR_ERR(xe);
796
797 pci_set_drvdata(pdev, &xe->drm);
798
799 xe_pm_assert_unbounded_bridge(xe);
800 subplatform_desc = find_subplatform(xe, desc);
801
802 pci_set_master(pdev);
803
804 err = xe_info_init_early(xe, desc, subplatform_desc);
805 if (err)
806 return err;
807
808 err = xe_device_probe_early(xe);
809 if (err)
810 return err;
811
812 err = xe_info_init(xe, desc->graphics, desc->media);
813 if (err)
814 return err;
815
816 err = xe_display_probe(xe);
817 if (err)
818 return err;
819
820 drm_dbg(&xe->drm, "%s %s %04x:%04x dgfx:%d gfx:%s (%d.%02d) media:%s (%d.%02d) display:%s dma_m_s:%d tc:%d gscfi:%d cscfi:%d",
821 desc->platform_name,
822 subplatform_desc ? subplatform_desc->name : "",
823 xe->info.devid, xe->info.revid,
824 xe->info.is_dgfx,
825 xe->info.graphics_name,
826 xe->info.graphics_verx100 / 100,
827 xe->info.graphics_verx100 % 100,
828 xe->info.media_name,
829 xe->info.media_verx100 / 100,
830 xe->info.media_verx100 % 100,
831 str_yes_no(xe->info.probe_display),
832 xe->info.dma_mask_size, xe->info.tile_count,
833 xe->info.has_heci_gscfi, xe->info.has_heci_cscfi);
834
835 drm_dbg(&xe->drm, "Stepping = (G:%s, M:%s, B:%s)\n",
836 xe_step_name(xe->info.step.graphics),
837 xe_step_name(xe->info.step.media),
838 xe_step_name(xe->info.step.basedie));
839
840 drm_dbg(&xe->drm, "SR-IOV support: %s (mode: %s)\n",
841 str_yes_no(xe_device_has_sriov(xe)),
842 xe_sriov_mode_to_string(xe_device_sriov_mode(xe)));
843
844 err = xe_pm_init_early(xe);
845 if (err)
846 return err;
847
848 err = xe_device_probe(xe);
849 if (err)
850 return err;
851
852 err = xe_pm_init(xe);
853 if (err)
854 goto err_driver_cleanup;
855
856 drm_dbg(&xe->drm, "d3cold: capable=%s\n",
857 str_yes_no(xe->d3cold.capable));
858
859 return 0;
860
861 err_driver_cleanup:
862 xe_pci_remove(pdev);
863 return err;
864 }
865
xe_pci_shutdown(struct pci_dev * pdev)866 static void xe_pci_shutdown(struct pci_dev *pdev)
867 {
868 xe_device_shutdown(pdev_to_xe_device(pdev));
869 }
870
871 #ifdef CONFIG_PM_SLEEP
d3cold_toggle(struct pci_dev * pdev,enum toggle_d3cold toggle)872 static void d3cold_toggle(struct pci_dev *pdev, enum toggle_d3cold toggle)
873 {
874 struct xe_device *xe = pdev_to_xe_device(pdev);
875 struct pci_dev *root_pdev;
876
877 if (!xe->d3cold.capable)
878 return;
879
880 root_pdev = pcie_find_root_port(pdev);
881 if (!root_pdev)
882 return;
883
884 switch (toggle) {
885 case D3COLD_DISABLE:
886 pci_d3cold_disable(root_pdev);
887 break;
888 case D3COLD_ENABLE:
889 pci_d3cold_enable(root_pdev);
890 break;
891 }
892 }
893
xe_pci_suspend(struct device * dev)894 static int xe_pci_suspend(struct device *dev)
895 {
896 struct pci_dev *pdev = to_pci_dev(dev);
897 int err;
898
899 err = xe_pm_suspend(pdev_to_xe_device(pdev));
900 if (err)
901 return err;
902
903 /*
904 * Enabling D3Cold is needed for S2Idle/S0ix.
905 * It is save to allow here since xe_pm_suspend has evicted
906 * the local memory and the direct complete optimization is disabled.
907 */
908 d3cold_toggle(pdev, D3COLD_ENABLE);
909
910 pci_save_state(pdev);
911 pci_disable_device(pdev);
912 pci_set_power_state(pdev, PCI_D3cold);
913
914 return 0;
915 }
916
xe_pci_resume(struct device * dev)917 static int xe_pci_resume(struct device *dev)
918 {
919 struct pci_dev *pdev = to_pci_dev(dev);
920 int err;
921
922 /* Give back the D3Cold decision to the runtime P M*/
923 d3cold_toggle(pdev, D3COLD_DISABLE);
924
925 err = pci_set_power_state(pdev, PCI_D0);
926 if (err)
927 return err;
928
929 pci_restore_state(pdev);
930
931 err = pci_enable_device(pdev);
932 if (err)
933 return err;
934
935 pci_set_master(pdev);
936
937 err = xe_pm_resume(pdev_to_xe_device(pdev));
938 if (err)
939 return err;
940
941 return 0;
942 }
943
xe_pci_runtime_suspend(struct device * dev)944 static int xe_pci_runtime_suspend(struct device *dev)
945 {
946 struct pci_dev *pdev = to_pci_dev(dev);
947 struct xe_device *xe = pdev_to_xe_device(pdev);
948 int err;
949
950 err = xe_pm_runtime_suspend(xe);
951 if (err)
952 return err;
953
954 pci_save_state(pdev);
955
956 if (xe->d3cold.allowed) {
957 d3cold_toggle(pdev, D3COLD_ENABLE);
958 pci_disable_device(pdev);
959 pci_ignore_hotplug(pdev);
960 pci_set_power_state(pdev, PCI_D3cold);
961 } else {
962 d3cold_toggle(pdev, D3COLD_DISABLE);
963 pci_set_power_state(pdev, PCI_D3hot);
964 }
965
966 return 0;
967 }
968
xe_pci_runtime_resume(struct device * dev)969 static int xe_pci_runtime_resume(struct device *dev)
970 {
971 struct pci_dev *pdev = to_pci_dev(dev);
972 struct xe_device *xe = pdev_to_xe_device(pdev);
973 int err;
974
975 err = pci_set_power_state(pdev, PCI_D0);
976 if (err)
977 return err;
978
979 pci_restore_state(pdev);
980
981 if (xe->d3cold.allowed) {
982 err = pci_enable_device(pdev);
983 if (err)
984 return err;
985
986 pci_set_master(pdev);
987 }
988
989 return xe_pm_runtime_resume(xe);
990 }
991
xe_pci_runtime_idle(struct device * dev)992 static int xe_pci_runtime_idle(struct device *dev)
993 {
994 struct pci_dev *pdev = to_pci_dev(dev);
995 struct xe_device *xe = pdev_to_xe_device(pdev);
996
997 xe_pm_d3cold_allowed_toggle(xe);
998
999 return 0;
1000 }
1001
1002 static const struct dev_pm_ops xe_pm_ops = {
1003 SET_SYSTEM_SLEEP_PM_OPS(xe_pci_suspend, xe_pci_resume)
1004 SET_RUNTIME_PM_OPS(xe_pci_runtime_suspend, xe_pci_runtime_resume, xe_pci_runtime_idle)
1005 };
1006 #endif
1007
1008 static struct pci_driver xe_pci_driver = {
1009 .name = DRIVER_NAME,
1010 .id_table = pciidlist,
1011 .probe = xe_pci_probe,
1012 .remove = xe_pci_remove,
1013 .shutdown = xe_pci_shutdown,
1014 .sriov_configure = xe_pci_sriov_configure,
1015 #ifdef CONFIG_PM_SLEEP
1016 .driver.pm = &xe_pm_ops,
1017 #endif
1018 };
1019
xe_register_pci_driver(void)1020 int xe_register_pci_driver(void)
1021 {
1022 return pci_register_driver(&xe_pci_driver);
1023 }
1024
xe_unregister_pci_driver(void)1025 void xe_unregister_pci_driver(void)
1026 {
1027 pci_unregister_driver(&xe_pci_driver);
1028 }
1029
1030 #if IS_ENABLED(CONFIG_DRM_XE_KUNIT_TEST)
1031 #include "tests/xe_pci.c"
1032 #endif
1033