1 // SPDX-License-Identifier: MIT
2 /*
3 * Copyright © 2022 Intel Corporation
4 */
5
6 #include "xe_wa.h"
7
8 #include <drm/drm_managed.h>
9 #include <kunit/visibility.h>
10 #include <linux/compiler_types.h>
11
12 #include <generated/xe_wa_oob.h>
13
14 #include "regs/xe_engine_regs.h"
15 #include "regs/xe_gt_regs.h"
16 #include "regs/xe_regs.h"
17 #include "xe_device_types.h"
18 #include "xe_force_wake.h"
19 #include "xe_gt.h"
20 #include "xe_hw_engine_types.h"
21 #include "xe_mmio.h"
22 #include "xe_platform_types.h"
23 #include "xe_rtp.h"
24 #include "xe_sriov.h"
25 #include "xe_step.h"
26
27 /**
28 * DOC: Hardware workarounds
29 *
30 * Hardware workarounds are register programming documented to be executed in
31 * the driver that fall outside of the normal programming sequences for a
32 * platform. There are some basic categories of workarounds, depending on
33 * how/when they are applied:
34 *
35 * - LRC workarounds: workarounds that touch registers that are
36 * saved/restored to/from the HW context image. The list is emitted (via Load
37 * Register Immediate commands) once when initializing the device and saved in
38 * the default context. That default context is then used on every context
39 * creation to have a "primed golden context", i.e. a context image that
40 * already contains the changes needed to all the registers.
41 *
42 * - Engine workarounds: the list of these WAs is applied whenever the specific
43 * engine is reset. It's also possible that a set of engine classes share a
44 * common power domain and they are reset together. This happens on some
45 * platforms with render and compute engines. In this case (at least) one of
46 * them need to keeep the workaround programming: the approach taken in the
47 * driver is to tie those workarounds to the first compute/render engine that
48 * is registered. When executing with GuC submission, engine resets are
49 * outside of kernel driver control, hence the list of registers involved in
50 * written once, on engine initialization, and then passed to GuC, that
51 * saves/restores their values before/after the reset takes place. See
52 * ``drivers/gpu/drm/xe/xe_guc_ads.c`` for reference.
53 *
54 * - GT workarounds: the list of these WAs is applied whenever these registers
55 * revert to their default values: on GPU reset, suspend/resume [1]_, etc.
56 *
57 * - Register whitelist: some workarounds need to be implemented in userspace,
58 * but need to touch privileged registers. The whitelist in the kernel
59 * instructs the hardware to allow the access to happen. From the kernel side,
60 * this is just a special case of a MMIO workaround (as we write the list of
61 * these to/be-whitelisted registers to some special HW registers).
62 *
63 * - Workaround batchbuffers: buffers that get executed automatically by the
64 * hardware on every HW context restore. These buffers are created and
65 * programmed in the default context so the hardware always go through those
66 * programming sequences when switching contexts. The support for workaround
67 * batchbuffers is enabled these hardware mechanisms:
68 *
69 * #. INDIRECT_CTX: A batchbuffer and an offset are provided in the default
70 * context, pointing the hardware to jump to that location when that offset
71 * is reached in the context restore. Workaround batchbuffer in the driver
72 * currently uses this mechanism for all platforms.
73 *
74 * #. BB_PER_CTX_PTR: A batchbuffer is provided in the default context,
75 * pointing the hardware to a buffer to continue executing after the
76 * engine registers are restored in a context restore sequence. This is
77 * currently not used in the driver.
78 *
79 * - Other/OOB: There are WAs that, due to their nature, cannot be applied from
80 * a central place. Those are peppered around the rest of the code, as needed.
81 * Workarounds related to the display IP are the main example.
82 *
83 * .. [1] Technically, some registers are powercontext saved & restored, so they
84 * survive a suspend/resume. In practice, writing them again is not too
85 * costly and simplifies things, so it's the approach taken in the driver.
86 *
87 * .. note::
88 * Hardware workarounds in xe work the same way as in i915, with the
89 * difference of how they are maintained in the code. In xe it uses the
90 * xe_rtp infrastructure so the workarounds can be kept in tables, following
91 * a more declarative approach rather than procedural.
92 */
93
94 #undef XE_REG_MCR
95 #define XE_REG_MCR(...) XE_REG(__VA_ARGS__, .mcr = 1)
96
97 __diag_push();
98 __diag_ignore_all("-Woverride-init", "Allow field overrides in table");
99
100 static const struct xe_rtp_entry_sr gt_was[] = {
101 { XE_RTP_NAME("14011060649"),
102 XE_RTP_RULES(MEDIA_VERSION_RANGE(1200, 1255),
103 ENGINE_CLASS(VIDEO_DECODE),
104 FUNC(xe_rtp_match_even_instance)),
105 XE_RTP_ACTIONS(SET(VDBOX_CGCTL3F10(0), IECPUNIT_CLKGATE_DIS)),
106 XE_RTP_ENTRY_FLAG(FOREACH_ENGINE),
107 },
108 { XE_RTP_NAME("14011059788"),
109 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1210)),
110 XE_RTP_ACTIONS(SET(DFR_RATIO_EN_AND_CHICKEN, DFR_DISABLE))
111 },
112 { XE_RTP_NAME("14015795083"),
113 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1260)),
114 XE_RTP_ACTIONS(CLR(MISCCPCTL, DOP_CLOCK_GATE_RENDER_ENABLE))
115 },
116
117 /* DG1 */
118
119 { XE_RTP_NAME("1409420604"),
120 XE_RTP_RULES(PLATFORM(DG1)),
121 XE_RTP_ACTIONS(SET(SUBSLICE_UNIT_LEVEL_CLKGATE2, CPSSUNIT_CLKGATE_DIS))
122 },
123 { XE_RTP_NAME("1408615072"),
124 XE_RTP_RULES(PLATFORM(DG1)),
125 XE_RTP_ACTIONS(SET(UNSLICE_UNIT_LEVEL_CLKGATE2, VSUNIT_CLKGATE2_DIS))
126 },
127
128 /* DG2 */
129
130 { XE_RTP_NAME("22010523718"),
131 XE_RTP_RULES(SUBPLATFORM(DG2, G10)),
132 XE_RTP_ACTIONS(SET(UNSLICE_UNIT_LEVEL_CLKGATE, CG3DDISCFEG_CLKGATE_DIS))
133 },
134 { XE_RTP_NAME("14011006942"),
135 XE_RTP_RULES(SUBPLATFORM(DG2, G10)),
136 XE_RTP_ACTIONS(SET(SUBSLICE_UNIT_LEVEL_CLKGATE, DSS_ROUTER_CLKGATE_DIS))
137 },
138 { XE_RTP_NAME("14014830051"),
139 XE_RTP_RULES(PLATFORM(DG2)),
140 XE_RTP_ACTIONS(CLR(SARB_CHICKEN1, COMP_CKN_IN))
141 },
142 { XE_RTP_NAME("18018781329"),
143 XE_RTP_RULES(PLATFORM(DG2)),
144 XE_RTP_ACTIONS(SET(RENDER_MOD_CTRL, FORCE_MISS_FTLB),
145 SET(COMP_MOD_CTRL, FORCE_MISS_FTLB),
146 SET(XEHP_VDBX_MOD_CTRL, FORCE_MISS_FTLB),
147 SET(XEHP_VEBX_MOD_CTRL, FORCE_MISS_FTLB))
148 },
149 { XE_RTP_NAME("1509235366"),
150 XE_RTP_RULES(PLATFORM(DG2)),
151 XE_RTP_ACTIONS(SET(XEHP_GAMCNTRL_CTRL,
152 INVALIDATION_BROADCAST_MODE_DIS |
153 GLOBAL_INVALIDATION_MODE))
154 },
155
156 /* PVC */
157
158 { XE_RTP_NAME("18018781329"),
159 XE_RTP_RULES(PLATFORM(PVC)),
160 XE_RTP_ACTIONS(SET(RENDER_MOD_CTRL, FORCE_MISS_FTLB),
161 SET(COMP_MOD_CTRL, FORCE_MISS_FTLB),
162 SET(XEHP_VDBX_MOD_CTRL, FORCE_MISS_FTLB),
163 SET(XEHP_VEBX_MOD_CTRL, FORCE_MISS_FTLB))
164 },
165 { XE_RTP_NAME("16016694945"),
166 XE_RTP_RULES(PLATFORM(PVC)),
167 XE_RTP_ACTIONS(SET(XEHPC_LNCFMISCCFGREG0, XEHPC_OVRLSCCC))
168 },
169
170 /* Xe_LPG */
171
172 { XE_RTP_NAME("14015795083"),
173 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1270, 1271), GRAPHICS_STEP(A0, B0)),
174 XE_RTP_ACTIONS(CLR(MISCCPCTL, DOP_CLOCK_GATE_RENDER_ENABLE))
175 },
176 { XE_RTP_NAME("14018575942"),
177 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1270, 1274)),
178 XE_RTP_ACTIONS(SET(COMP_MOD_CTRL, FORCE_MISS_FTLB))
179 },
180 { XE_RTP_NAME("22016670082"),
181 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1270, 1274)),
182 XE_RTP_ACTIONS(SET(SQCNT1, ENFORCE_RAR))
183 },
184
185 /* Xe_LPM+ */
186
187 { XE_RTP_NAME("16021867713"),
188 XE_RTP_RULES(MEDIA_VERSION(1300),
189 ENGINE_CLASS(VIDEO_DECODE)),
190 XE_RTP_ACTIONS(SET(VDBOX_CGCTL3F1C(0), MFXPIPE_CLKGATE_DIS)),
191 XE_RTP_ENTRY_FLAG(FOREACH_ENGINE),
192 },
193 { XE_RTP_NAME("22016670082"),
194 XE_RTP_RULES(MEDIA_VERSION(1300)),
195 XE_RTP_ACTIONS(SET(XELPMP_SQCNT1, ENFORCE_RAR))
196 },
197
198 /* Xe2_LPG */
199
200 { XE_RTP_NAME("16020975621"),
201 XE_RTP_RULES(GRAPHICS_VERSION(2004), GRAPHICS_STEP(A0, B0)),
202 XE_RTP_ACTIONS(SET(XEHP_SLICE_UNIT_LEVEL_CLKGATE, SBEUNIT_CLKGATE_DIS))
203 },
204 { XE_RTP_NAME("14018157293"),
205 XE_RTP_RULES(GRAPHICS_VERSION(2004), GRAPHICS_STEP(A0, B0)),
206 XE_RTP_ACTIONS(SET(XEHPC_L3CLOS_MASK(0), ~0),
207 SET(XEHPC_L3CLOS_MASK(1), ~0),
208 SET(XEHPC_L3CLOS_MASK(2), ~0),
209 SET(XEHPC_L3CLOS_MASK(3), ~0))
210 },
211
212 /* Xe2_LPM */
213
214 { XE_RTP_NAME("14017421178"),
215 XE_RTP_RULES(MEDIA_VERSION(2000),
216 ENGINE_CLASS(VIDEO_DECODE)),
217 XE_RTP_ACTIONS(SET(VDBOX_CGCTL3F10(0), IECPUNIT_CLKGATE_DIS)),
218 XE_RTP_ENTRY_FLAG(FOREACH_ENGINE),
219 },
220 { XE_RTP_NAME("16021867713"),
221 XE_RTP_RULES(MEDIA_VERSION(2000),
222 ENGINE_CLASS(VIDEO_DECODE)),
223 XE_RTP_ACTIONS(SET(VDBOX_CGCTL3F1C(0), MFXPIPE_CLKGATE_DIS)),
224 XE_RTP_ENTRY_FLAG(FOREACH_ENGINE),
225 },
226 { XE_RTP_NAME("14019449301"),
227 XE_RTP_RULES(MEDIA_VERSION(2000), ENGINE_CLASS(VIDEO_DECODE)),
228 XE_RTP_ACTIONS(SET(VDBOX_CGCTL3F08(0), CG3DDISHRS_CLKGATE_DIS)),
229 XE_RTP_ENTRY_FLAG(FOREACH_ENGINE),
230 },
231
232 /* Xe2_HPM */
233
234 { XE_RTP_NAME("16021867713"),
235 XE_RTP_RULES(MEDIA_VERSION(1301),
236 ENGINE_CLASS(VIDEO_DECODE)),
237 XE_RTP_ACTIONS(SET(VDBOX_CGCTL3F1C(0), MFXPIPE_CLKGATE_DIS)),
238 XE_RTP_ENTRY_FLAG(FOREACH_ENGINE),
239 },
240 { XE_RTP_NAME("14020316580"),
241 XE_RTP_RULES(MEDIA_VERSION(1301)),
242 XE_RTP_ACTIONS(CLR(POWERGATE_ENABLE,
243 VDN_HCP_POWERGATE_ENABLE(0) |
244 VDN_MFXVDENC_POWERGATE_ENABLE(0) |
245 VDN_HCP_POWERGATE_ENABLE(2) |
246 VDN_MFXVDENC_POWERGATE_ENABLE(2))),
247 },
248 { XE_RTP_NAME("14019449301"),
249 XE_RTP_RULES(MEDIA_VERSION(1301), ENGINE_CLASS(VIDEO_DECODE)),
250 XE_RTP_ACTIONS(SET(VDBOX_CGCTL3F08(0), CG3DDISHRS_CLKGATE_DIS)),
251 XE_RTP_ENTRY_FLAG(FOREACH_ENGINE),
252 },
253
254 /* Xe3_LPG */
255
256 { XE_RTP_NAME("14021871409"),
257 XE_RTP_RULES(GRAPHICS_VERSION(3000), GRAPHICS_STEP(A0, B0)),
258 XE_RTP_ACTIONS(SET(UNSLCGCTL9454, LSCFE_CLKGATE_DIS))
259 },
260
261 /* Xe3_LPM */
262
263 { XE_RTP_NAME("16021867713"),
264 XE_RTP_RULES(MEDIA_VERSION(3000),
265 ENGINE_CLASS(VIDEO_DECODE)),
266 XE_RTP_ACTIONS(SET(VDBOX_CGCTL3F1C(0), MFXPIPE_CLKGATE_DIS)),
267 XE_RTP_ENTRY_FLAG(FOREACH_ENGINE),
268 },
269 { XE_RTP_NAME("16021865536"),
270 XE_RTP_RULES(MEDIA_VERSION(3000),
271 ENGINE_CLASS(VIDEO_DECODE)),
272 XE_RTP_ACTIONS(SET(VDBOX_CGCTL3F10(0), IECPUNIT_CLKGATE_DIS)),
273 XE_RTP_ENTRY_FLAG(FOREACH_ENGINE),
274 },
275 { XE_RTP_NAME("14021486841"),
276 XE_RTP_RULES(MEDIA_VERSION(3000), MEDIA_STEP(A0, B0),
277 ENGINE_CLASS(VIDEO_DECODE)),
278 XE_RTP_ACTIONS(SET(VDBOX_CGCTL3F10(0), RAMDFTUNIT_CLKGATE_DIS)),
279 XE_RTP_ENTRY_FLAG(FOREACH_ENGINE),
280 },
281
282 {}
283 };
284
285 static const struct xe_rtp_entry_sr engine_was[] = {
286 { XE_RTP_NAME("22010931296, 18011464164, 14010919138"),
287 XE_RTP_RULES(GRAPHICS_VERSION(1200), ENGINE_CLASS(RENDER)),
288 XE_RTP_ACTIONS(SET(FF_THREAD_MODE(RENDER_RING_BASE),
289 FF_TESSELATION_DOP_GATE_DISABLE))
290 },
291 { XE_RTP_NAME("1409804808"),
292 XE_RTP_RULES(GRAPHICS_VERSION(1200),
293 ENGINE_CLASS(RENDER),
294 IS_INTEGRATED),
295 XE_RTP_ACTIONS(SET(ROW_CHICKEN2, PUSH_CONST_DEREF_HOLD_DIS))
296 },
297 { XE_RTP_NAME("14010229206, 1409085225"),
298 XE_RTP_RULES(GRAPHICS_VERSION(1200),
299 ENGINE_CLASS(RENDER),
300 IS_INTEGRATED),
301 XE_RTP_ACTIONS(SET(ROW_CHICKEN4, DISABLE_TDL_PUSH))
302 },
303 { XE_RTP_NAME("1606931601"),
304 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1210), ENGINE_CLASS(RENDER)),
305 XE_RTP_ACTIONS(SET(ROW_CHICKEN2, DISABLE_EARLY_READ))
306 },
307 { XE_RTP_NAME("14010826681, 1606700617, 22010271021, 18019627453"),
308 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1255), ENGINE_CLASS(RENDER)),
309 XE_RTP_ACTIONS(SET(CS_DEBUG_MODE1(RENDER_RING_BASE),
310 FF_DOP_CLOCK_GATE_DISABLE))
311 },
312 { XE_RTP_NAME("1406941453"),
313 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1210), ENGINE_CLASS(RENDER)),
314 XE_RTP_ACTIONS(SET(SAMPLER_MODE, ENABLE_SMALLPL))
315 },
316 { XE_RTP_NAME("FtrPerCtxtPreemptionGranularityControl"),
317 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1250), ENGINE_CLASS(RENDER)),
318 XE_RTP_ACTIONS(SET(FF_SLICE_CS_CHICKEN1(RENDER_RING_BASE),
319 FFSC_PERCTX_PREEMPT_CTRL))
320 },
321
322 /* TGL */
323
324 { XE_RTP_NAME("1607297627, 1607030317, 1607186500"),
325 XE_RTP_RULES(PLATFORM(TIGERLAKE), ENGINE_CLASS(RENDER)),
326 XE_RTP_ACTIONS(SET(RING_PSMI_CTL(RENDER_RING_BASE),
327 WAIT_FOR_EVENT_POWER_DOWN_DISABLE |
328 RC_SEMA_IDLE_MSG_DISABLE))
329 },
330
331 /* RKL */
332
333 { XE_RTP_NAME("1607297627, 1607030317, 1607186500"),
334 XE_RTP_RULES(PLATFORM(ROCKETLAKE), ENGINE_CLASS(RENDER)),
335 XE_RTP_ACTIONS(SET(RING_PSMI_CTL(RENDER_RING_BASE),
336 WAIT_FOR_EVENT_POWER_DOWN_DISABLE |
337 RC_SEMA_IDLE_MSG_DISABLE))
338 },
339
340 /* ADL-P */
341
342 { XE_RTP_NAME("1607297627, 1607030317, 1607186500"),
343 XE_RTP_RULES(PLATFORM(ALDERLAKE_P), ENGINE_CLASS(RENDER)),
344 XE_RTP_ACTIONS(SET(RING_PSMI_CTL(RENDER_RING_BASE),
345 WAIT_FOR_EVENT_POWER_DOWN_DISABLE |
346 RC_SEMA_IDLE_MSG_DISABLE))
347 },
348
349 /* DG2 */
350
351 { XE_RTP_NAME("22013037850"),
352 XE_RTP_RULES(PLATFORM(DG2), FUNC(xe_rtp_match_first_render_or_compute)),
353 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0_UDW,
354 DISABLE_128B_EVICTION_COMMAND_UDW))
355 },
356 { XE_RTP_NAME("22014226127"),
357 XE_RTP_RULES(PLATFORM(DG2), FUNC(xe_rtp_match_first_render_or_compute)),
358 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0, DISABLE_D8_D16_COASLESCE))
359 },
360 { XE_RTP_NAME("18017747507"),
361 XE_RTP_RULES(PLATFORM(DG2), FUNC(xe_rtp_match_first_render_or_compute)),
362 XE_RTP_ACTIONS(SET(VFG_PREEMPTION_CHICKEN,
363 POLYGON_TRIFAN_LINELOOP_DISABLE))
364 },
365 { XE_RTP_NAME("22012826095, 22013059131"),
366 XE_RTP_RULES(SUBPLATFORM(DG2, G11),
367 FUNC(xe_rtp_match_first_render_or_compute)),
368 XE_RTP_ACTIONS(FIELD_SET(LSC_CHICKEN_BIT_0_UDW,
369 MAXREQS_PER_BANK,
370 REG_FIELD_PREP(MAXREQS_PER_BANK, 2)))
371 },
372 { XE_RTP_NAME("22013059131"),
373 XE_RTP_RULES(SUBPLATFORM(DG2, G11),
374 FUNC(xe_rtp_match_first_render_or_compute)),
375 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0, FORCE_1_SUB_MESSAGE_PER_FRAGMENT))
376 },
377 { XE_RTP_NAME("14015227452"),
378 XE_RTP_RULES(PLATFORM(DG2),
379 FUNC(xe_rtp_match_first_render_or_compute)),
380 XE_RTP_ACTIONS(SET(ROW_CHICKEN4, XEHP_DIS_BBL_SYSPIPE))
381 },
382 { XE_RTP_NAME("18028616096"),
383 XE_RTP_RULES(PLATFORM(DG2),
384 FUNC(xe_rtp_match_first_render_or_compute)),
385 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0_UDW, UGM_FRAGMENT_THRESHOLD_TO_3))
386 },
387 { XE_RTP_NAME("22015475538"),
388 XE_RTP_RULES(PLATFORM(DG2),
389 FUNC(xe_rtp_match_first_render_or_compute)),
390 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0_UDW, DIS_CHAIN_2XSIMD8))
391 },
392 { XE_RTP_NAME("22012654132"),
393 XE_RTP_RULES(SUBPLATFORM(DG2, G11),
394 FUNC(xe_rtp_match_first_render_or_compute)),
395 XE_RTP_ACTIONS(SET(CACHE_MODE_SS, ENABLE_PREFETCH_INTO_IC,
396 /*
397 * Register can't be read back for verification on
398 * DG2 due to Wa_14012342262
399 */
400 .read_mask = 0))
401 },
402 { XE_RTP_NAME("1509727124"),
403 XE_RTP_RULES(PLATFORM(DG2), ENGINE_CLASS(RENDER)),
404 XE_RTP_ACTIONS(SET(SAMPLER_MODE, SC_DISABLE_POWER_OPTIMIZATION_EBB))
405 },
406 { XE_RTP_NAME("22012856258"),
407 XE_RTP_RULES(PLATFORM(DG2), ENGINE_CLASS(RENDER)),
408 XE_RTP_ACTIONS(SET(ROW_CHICKEN2, DISABLE_READ_SUPPRESSION))
409 },
410 { XE_RTP_NAME("22010960976, 14013347512"),
411 XE_RTP_RULES(PLATFORM(DG2), ENGINE_CLASS(RENDER)),
412 XE_RTP_ACTIONS(CLR(XEHP_HDC_CHICKEN0,
413 LSC_L1_FLUSH_CTL_3D_DATAPORT_FLUSH_EVENTS_MASK))
414 },
415 { XE_RTP_NAME("14015150844"),
416 XE_RTP_RULES(PLATFORM(DG2), FUNC(xe_rtp_match_first_render_or_compute)),
417 XE_RTP_ACTIONS(SET(XEHP_HDC_CHICKEN0, DIS_ATOMIC_CHAINING_TYPED_WRITES,
418 XE_RTP_NOCHECK))
419 },
420
421 /* PVC */
422
423 { XE_RTP_NAME("22014226127"),
424 XE_RTP_RULES(PLATFORM(PVC), FUNC(xe_rtp_match_first_render_or_compute)),
425 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0, DISABLE_D8_D16_COASLESCE))
426 },
427 { XE_RTP_NAME("14015227452"),
428 XE_RTP_RULES(PLATFORM(PVC), FUNC(xe_rtp_match_first_render_or_compute)),
429 XE_RTP_ACTIONS(SET(ROW_CHICKEN4, XEHP_DIS_BBL_SYSPIPE))
430 },
431 { XE_RTP_NAME("18020744125"),
432 XE_RTP_RULES(PLATFORM(PVC), FUNC(xe_rtp_match_first_render_or_compute),
433 ENGINE_CLASS(COMPUTE)),
434 XE_RTP_ACTIONS(SET(RING_HWSTAM(RENDER_RING_BASE), ~0))
435 },
436 { XE_RTP_NAME("14014999345"),
437 XE_RTP_RULES(PLATFORM(PVC), ENGINE_CLASS(COMPUTE),
438 GRAPHICS_STEP(B0, C0)),
439 XE_RTP_ACTIONS(SET(CACHE_MODE_SS, DISABLE_ECC))
440 },
441
442 /* Xe_LPG */
443
444 { XE_RTP_NAME("14017856879"),
445 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1270, 1274),
446 FUNC(xe_rtp_match_first_render_or_compute)),
447 XE_RTP_ACTIONS(SET(ROW_CHICKEN3, DIS_FIX_EOT1_FLUSH))
448 },
449 { XE_RTP_NAME("14015150844"),
450 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1270, 1271),
451 FUNC(xe_rtp_match_first_render_or_compute)),
452 XE_RTP_ACTIONS(SET(XEHP_HDC_CHICKEN0, DIS_ATOMIC_CHAINING_TYPED_WRITES,
453 XE_RTP_NOCHECK))
454 },
455 { XE_RTP_NAME("14020495402"),
456 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1270, 1274),
457 FUNC(xe_rtp_match_first_render_or_compute)),
458 XE_RTP_ACTIONS(SET(ROW_CHICKEN2, DISABLE_TDL_SVHS_GATING))
459 },
460
461 /* Xe2_LPG */
462
463 { XE_RTP_NAME("18032247524"),
464 XE_RTP_RULES(GRAPHICS_VERSION(2004),
465 FUNC(xe_rtp_match_first_render_or_compute)),
466 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0, SEQUENTIAL_ACCESS_UPGRADE_DISABLE))
467 },
468 { XE_RTP_NAME("16018712365"),
469 XE_RTP_RULES(GRAPHICS_VERSION(2004), FUNC(xe_rtp_match_first_render_or_compute)),
470 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0_UDW, XE2_ALLOC_DPA_STARVE_FIX_DIS))
471 },
472 { XE_RTP_NAME("14018957109"),
473 XE_RTP_RULES(GRAPHICS_VERSION(2004), GRAPHICS_STEP(A0, B0),
474 FUNC(xe_rtp_match_first_render_or_compute)),
475 XE_RTP_ACTIONS(SET(HALF_SLICE_CHICKEN5, DISABLE_SAMPLE_G_PERFORMANCE))
476 },
477 { XE_RTP_NAME("14020338487"),
478 XE_RTP_RULES(GRAPHICS_VERSION(2004), FUNC(xe_rtp_match_first_render_or_compute)),
479 XE_RTP_ACTIONS(SET(ROW_CHICKEN3, XE2_EUPEND_CHK_FLUSH_DIS))
480 },
481 { XE_RTP_NAME("18034896535, 16021540221"), /* 16021540221: GRAPHICS_STEP(A0, B0) */
482 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 2004),
483 FUNC(xe_rtp_match_first_render_or_compute)),
484 XE_RTP_ACTIONS(SET(ROW_CHICKEN4, DISABLE_TDL_PUSH))
485 },
486 { XE_RTP_NAME("14019322943"),
487 XE_RTP_RULES(GRAPHICS_VERSION(2004), GRAPHICS_STEP(A0, B0),
488 FUNC(xe_rtp_match_first_render_or_compute)),
489 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0, TGM_WRITE_EOM_FORCE))
490 },
491 { XE_RTP_NAME("14018471104"),
492 XE_RTP_RULES(GRAPHICS_VERSION(2004), FUNC(xe_rtp_match_first_render_or_compute)),
493 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0_UDW, ENABLE_SMP_LD_RENDER_SURFACE_CONTROL))
494 },
495 { XE_RTP_NAME("16018737384"),
496 XE_RTP_RULES(GRAPHICS_VERSION(2004), FUNC(xe_rtp_match_first_render_or_compute)),
497 XE_RTP_ACTIONS(SET(ROW_CHICKEN, EARLY_EOT_DIS))
498 },
499 /*
500 * These two workarounds are the same, just applying to different
501 * engines. Although Wa_18032095049 (for the RCS) isn't required on
502 * all steppings, disabling these reports has no impact for our
503 * driver or the GuC, so we go ahead and treat it the same as
504 * Wa_16021639441 which does apply to all steppings.
505 */
506 { XE_RTP_NAME("18032095049, 16021639441"),
507 XE_RTP_RULES(GRAPHICS_VERSION(2004)),
508 XE_RTP_ACTIONS(SET(CSFE_CHICKEN1(0),
509 GHWSP_CSB_REPORT_DIS |
510 PPHWSP_CSB_AND_TIMESTAMP_REPORT_DIS,
511 XE_RTP_ACTION_FLAG(ENGINE_BASE)))
512 },
513 { XE_RTP_NAME("16018610683"),
514 XE_RTP_RULES(GRAPHICS_VERSION(2004), FUNC(xe_rtp_match_first_render_or_compute)),
515 XE_RTP_ACTIONS(SET(TDL_TSL_CHICKEN, SLM_WMTP_RESTORE))
516 },
517 { XE_RTP_NAME("14021402888"),
518 XE_RTP_RULES(GRAPHICS_VERSION(2004), ENGINE_CLASS(RENDER)),
519 XE_RTP_ACTIONS(SET(HALF_SLICE_CHICKEN7, CLEAR_OPTIMIZATION_DISABLE))
520 },
521
522 /* Xe2_HPG */
523
524 { XE_RTP_NAME("16018712365"),
525 XE_RTP_RULES(GRAPHICS_VERSION(2001), FUNC(xe_rtp_match_first_render_or_compute)),
526 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0_UDW, XE2_ALLOC_DPA_STARVE_FIX_DIS))
527 },
528 { XE_RTP_NAME("16018737384"),
529 XE_RTP_RULES(GRAPHICS_VERSION(2001), FUNC(xe_rtp_match_first_render_or_compute)),
530 XE_RTP_ACTIONS(SET(ROW_CHICKEN, EARLY_EOT_DIS))
531 },
532 { XE_RTP_NAME("14019988906"),
533 XE_RTP_RULES(GRAPHICS_VERSION(2001), FUNC(xe_rtp_match_first_render_or_compute)),
534 XE_RTP_ACTIONS(SET(XEHP_PSS_CHICKEN, FLSH_IGNORES_PSD))
535 },
536 { XE_RTP_NAME("14019877138"),
537 XE_RTP_RULES(GRAPHICS_VERSION(2001), FUNC(xe_rtp_match_first_render_or_compute)),
538 XE_RTP_ACTIONS(SET(XEHP_PSS_CHICKEN, FD_END_COLLECT))
539 },
540 { XE_RTP_NAME("14020338487"),
541 XE_RTP_RULES(GRAPHICS_VERSION(2001), FUNC(xe_rtp_match_first_render_or_compute)),
542 XE_RTP_ACTIONS(SET(ROW_CHICKEN3, XE2_EUPEND_CHK_FLUSH_DIS))
543 },
544 { XE_RTP_NAME("18032247524"),
545 XE_RTP_RULES(GRAPHICS_VERSION(2001), FUNC(xe_rtp_match_first_render_or_compute)),
546 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0, SEQUENTIAL_ACCESS_UPGRADE_DISABLE))
547 },
548 { XE_RTP_NAME("14018471104"),
549 XE_RTP_RULES(GRAPHICS_VERSION(2001), FUNC(xe_rtp_match_first_render_or_compute)),
550 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0_UDW, ENABLE_SMP_LD_RENDER_SURFACE_CONTROL))
551 },
552 /*
553 * Although this workaround isn't required for the RCS, disabling these
554 * reports has no impact for our driver or the GuC, so we go ahead and
555 * apply this to all engines for simplicity.
556 */
557 { XE_RTP_NAME("16021639441"),
558 XE_RTP_RULES(GRAPHICS_VERSION(2001)),
559 XE_RTP_ACTIONS(SET(CSFE_CHICKEN1(0),
560 GHWSP_CSB_REPORT_DIS |
561 PPHWSP_CSB_AND_TIMESTAMP_REPORT_DIS,
562 XE_RTP_ACTION_FLAG(ENGINE_BASE)))
563 },
564 { XE_RTP_NAME("14019811474"),
565 XE_RTP_RULES(GRAPHICS_VERSION(2001),
566 FUNC(xe_rtp_match_first_render_or_compute)),
567 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0, WR_REQ_CHAINING_DIS))
568 },
569 { XE_RTP_NAME("14021402888"),
570 XE_RTP_RULES(GRAPHICS_VERSION(2001), ENGINE_CLASS(RENDER)),
571 XE_RTP_ACTIONS(SET(HALF_SLICE_CHICKEN7, CLEAR_OPTIMIZATION_DISABLE))
572 },
573 { XE_RTP_NAME("14021821874"),
574 XE_RTP_RULES(GRAPHICS_VERSION(2001), FUNC(xe_rtp_match_first_render_or_compute)),
575 XE_RTP_ACTIONS(SET(TDL_TSL_CHICKEN, STK_ID_RESTRICT))
576 },
577
578 /* Xe2_LPM */
579
580 { XE_RTP_NAME("16021639441"),
581 XE_RTP_RULES(MEDIA_VERSION(2000)),
582 XE_RTP_ACTIONS(SET(CSFE_CHICKEN1(0),
583 GHWSP_CSB_REPORT_DIS |
584 PPHWSP_CSB_AND_TIMESTAMP_REPORT_DIS,
585 XE_RTP_ACTION_FLAG(ENGINE_BASE)))
586 },
587
588 /* Xe2_HPM */
589
590 { XE_RTP_NAME("16021639441"),
591 XE_RTP_RULES(MEDIA_VERSION(1301)),
592 XE_RTP_ACTIONS(SET(CSFE_CHICKEN1(0),
593 GHWSP_CSB_REPORT_DIS |
594 PPHWSP_CSB_AND_TIMESTAMP_REPORT_DIS,
595 XE_RTP_ACTION_FLAG(ENGINE_BASE)))
596 },
597
598 /* Xe3_LPG */
599
600 { XE_RTP_NAME("14021402888"),
601 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(3000, 3001), FUNC(xe_rtp_match_first_render_or_compute)),
602 XE_RTP_ACTIONS(SET(HALF_SLICE_CHICKEN7, CLEAR_OPTIMIZATION_DISABLE))
603 },
604
605 {}
606 };
607
608 static const struct xe_rtp_entry_sr lrc_was[] = {
609 { XE_RTP_NAME("16011163337"),
610 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1210), ENGINE_CLASS(RENDER)),
611 /* read verification is ignored due to 1608008084. */
612 XE_RTP_ACTIONS(FIELD_SET_NO_READ_MASK(FF_MODE2,
613 FF_MODE2_GS_TIMER_MASK,
614 FF_MODE2_GS_TIMER_224))
615 },
616 { XE_RTP_NAME("1409342910, 14010698770, 14010443199, 1408979724, 1409178076, 1409207793, 1409217633, 1409252684, 1409347922, 1409142259"),
617 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1210)),
618 XE_RTP_ACTIONS(SET(COMMON_SLICE_CHICKEN3,
619 DISABLE_CPS_AWARE_COLOR_PIPE))
620 },
621 { XE_RTP_NAME("WaDisableGPGPUMidThreadPreemption"),
622 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1210)),
623 XE_RTP_ACTIONS(FIELD_SET(CS_CHICKEN1(RENDER_RING_BASE),
624 PREEMPT_GPGPU_LEVEL_MASK,
625 PREEMPT_GPGPU_THREAD_GROUP_LEVEL))
626 },
627 { XE_RTP_NAME("1806527549"),
628 XE_RTP_RULES(GRAPHICS_VERSION(1200)),
629 XE_RTP_ACTIONS(SET(HIZ_CHICKEN, HZ_DEPTH_TEST_LE_GE_OPT_DISABLE))
630 },
631 { XE_RTP_NAME("1606376872"),
632 XE_RTP_RULES(GRAPHICS_VERSION(1200)),
633 XE_RTP_ACTIONS(SET(COMMON_SLICE_CHICKEN4, DISABLE_TDC_LOAD_BALANCING_CALC))
634 },
635
636 /* DG1 */
637
638 { XE_RTP_NAME("1409044764"),
639 XE_RTP_RULES(PLATFORM(DG1)),
640 XE_RTP_ACTIONS(CLR(COMMON_SLICE_CHICKEN3,
641 DG1_FLOAT_POINT_BLEND_OPT_STRICT_MODE_EN))
642 },
643 { XE_RTP_NAME("22010493298"),
644 XE_RTP_RULES(PLATFORM(DG1)),
645 XE_RTP_ACTIONS(SET(HIZ_CHICKEN,
646 DG1_HZ_READ_SUPPRESSION_OPTIMIZATION_DISABLE))
647 },
648
649 /* DG2 */
650
651 { XE_RTP_NAME("16013271637"),
652 XE_RTP_RULES(PLATFORM(DG2)),
653 XE_RTP_ACTIONS(SET(XEHP_SLICE_COMMON_ECO_CHICKEN1,
654 MSC_MSAA_REODER_BUF_BYPASS_DISABLE))
655 },
656 { XE_RTP_NAME("14014947963"),
657 XE_RTP_RULES(PLATFORM(DG2)),
658 XE_RTP_ACTIONS(FIELD_SET(VF_PREEMPTION,
659 PREEMPTION_VERTEX_COUNT,
660 0x4000))
661 },
662 { XE_RTP_NAME("18018764978"),
663 XE_RTP_RULES(PLATFORM(DG2)),
664 XE_RTP_ACTIONS(SET(XEHP_PSS_MODE2,
665 SCOREBOARD_STALL_FLUSH_CONTROL))
666 },
667 { XE_RTP_NAME("18019271663"),
668 XE_RTP_RULES(PLATFORM(DG2)),
669 XE_RTP_ACTIONS(SET(CACHE_MODE_1, MSAA_OPTIMIZATION_REDUC_DISABLE))
670 },
671 { XE_RTP_NAME("14019877138"),
672 XE_RTP_RULES(PLATFORM(DG2)),
673 XE_RTP_ACTIONS(SET(XEHP_PSS_CHICKEN, FD_END_COLLECT))
674 },
675
676 /* PVC */
677
678 { XE_RTP_NAME("16017236439"),
679 XE_RTP_RULES(PLATFORM(PVC), ENGINE_CLASS(COPY),
680 FUNC(xe_rtp_match_even_instance)),
681 XE_RTP_ACTIONS(SET(BCS_SWCTRL(0),
682 BCS_SWCTRL_DISABLE_256B,
683 XE_RTP_ACTION_FLAG(ENGINE_BASE))),
684 },
685
686 /* Xe_LPG */
687
688 { XE_RTP_NAME("18019271663"),
689 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1270, 1274)),
690 XE_RTP_ACTIONS(SET(CACHE_MODE_1, MSAA_OPTIMIZATION_REDUC_DISABLE))
691 },
692 { XE_RTP_NAME("14019877138"),
693 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1270, 1274), ENGINE_CLASS(RENDER)),
694 XE_RTP_ACTIONS(SET(XEHP_PSS_CHICKEN, FD_END_COLLECT))
695 },
696
697 /* Xe2_LPG */
698
699 { XE_RTP_NAME("16020518922"),
700 XE_RTP_RULES(GRAPHICS_VERSION(2004), GRAPHICS_STEP(A0, B0),
701 ENGINE_CLASS(RENDER)),
702 XE_RTP_ACTIONS(SET(FF_MODE,
703 DIS_TE_AUTOSTRIP |
704 DIS_MESH_PARTIAL_AUTOSTRIP |
705 DIS_MESH_AUTOSTRIP),
706 SET(VFLSKPD,
707 DIS_PARTIAL_AUTOSTRIP |
708 DIS_AUTOSTRIP))
709 },
710 { XE_RTP_NAME("14019386621"),
711 XE_RTP_RULES(GRAPHICS_VERSION(2004), ENGINE_CLASS(RENDER)),
712 XE_RTP_ACTIONS(SET(VF_SCRATCHPAD, XE2_VFG_TED_CREDIT_INTERFACE_DISABLE))
713 },
714 { XE_RTP_NAME("14019877138"),
715 XE_RTP_RULES(GRAPHICS_VERSION(2004), ENGINE_CLASS(RENDER)),
716 XE_RTP_ACTIONS(SET(XEHP_PSS_CHICKEN, FD_END_COLLECT))
717 },
718 { XE_RTP_NAME("14020013138"),
719 XE_RTP_RULES(GRAPHICS_VERSION(2004), GRAPHICS_STEP(A0, B0),
720 ENGINE_CLASS(RENDER)),
721 XE_RTP_ACTIONS(SET(WM_CHICKEN3, HIZ_PLANE_COMPRESSION_DIS))
722 },
723 { XE_RTP_NAME("14019988906"),
724 XE_RTP_RULES(GRAPHICS_VERSION(2004), ENGINE_CLASS(RENDER)),
725 XE_RTP_ACTIONS(SET(XEHP_PSS_CHICKEN, FLSH_IGNORES_PSD))
726 },
727 { XE_RTP_NAME("16020183090"),
728 XE_RTP_RULES(GRAPHICS_VERSION(2004), GRAPHICS_STEP(A0, B0),
729 ENGINE_CLASS(RENDER)),
730 XE_RTP_ACTIONS(SET(INSTPM(RENDER_RING_BASE), ENABLE_SEMAPHORE_POLL_BIT))
731 },
732 { XE_RTP_NAME("18033852989"),
733 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 2004), ENGINE_CLASS(RENDER)),
734 XE_RTP_ACTIONS(SET(COMMON_SLICE_CHICKEN1, DISABLE_BOTTOM_CLIP_RECTANGLE_TEST))
735 },
736 { XE_RTP_NAME("14021567978"),
737 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, XE_RTP_END_VERSION_UNDEFINED),
738 ENGINE_CLASS(RENDER)),
739 XE_RTP_ACTIONS(SET(CHICKEN_RASTER_2, TBIMR_FAST_CLIP))
740 },
741 { XE_RTP_NAME("14020756599"),
742 XE_RTP_RULES(GRAPHICS_VERSION(2004), ENGINE_CLASS(RENDER), OR,
743 MEDIA_VERSION_ANY_GT(2000), ENGINE_CLASS(RENDER)),
744 XE_RTP_ACTIONS(SET(WM_CHICKEN3, HIZ_PLANE_COMPRESSION_DIS))
745 },
746 { XE_RTP_NAME("14021490052"),
747 XE_RTP_RULES(GRAPHICS_VERSION(2004), ENGINE_CLASS(RENDER)),
748 XE_RTP_ACTIONS(SET(FF_MODE,
749 DIS_MESH_PARTIAL_AUTOSTRIP |
750 DIS_MESH_AUTOSTRIP),
751 SET(VFLSKPD,
752 DIS_PARTIAL_AUTOSTRIP |
753 DIS_AUTOSTRIP))
754 },
755 { XE_RTP_NAME("15016589081"),
756 XE_RTP_RULES(GRAPHICS_VERSION(2004), ENGINE_CLASS(RENDER)),
757 XE_RTP_ACTIONS(SET(CHICKEN_RASTER_1, DIS_CLIP_NEGATIVE_BOUNDING_BOX))
758 },
759
760 /* Xe2_HPG */
761 { XE_RTP_NAME("15010599737"),
762 XE_RTP_RULES(GRAPHICS_VERSION(2001), ENGINE_CLASS(RENDER)),
763 XE_RTP_ACTIONS(SET(CHICKEN_RASTER_1, DIS_SF_ROUND_NEAREST_EVEN))
764 },
765 { XE_RTP_NAME("14019386621"),
766 XE_RTP_RULES(GRAPHICS_VERSION(2001), ENGINE_CLASS(RENDER)),
767 XE_RTP_ACTIONS(SET(VF_SCRATCHPAD, XE2_VFG_TED_CREDIT_INTERFACE_DISABLE))
768 },
769 { XE_RTP_NAME("14020756599"),
770 XE_RTP_RULES(GRAPHICS_VERSION(2001), ENGINE_CLASS(RENDER)),
771 XE_RTP_ACTIONS(SET(WM_CHICKEN3, HIZ_PLANE_COMPRESSION_DIS))
772 },
773 { XE_RTP_NAME("14021490052"),
774 XE_RTP_RULES(GRAPHICS_VERSION(2001), ENGINE_CLASS(RENDER)),
775 XE_RTP_ACTIONS(SET(FF_MODE,
776 DIS_MESH_PARTIAL_AUTOSTRIP |
777 DIS_MESH_AUTOSTRIP),
778 SET(VFLSKPD,
779 DIS_PARTIAL_AUTOSTRIP |
780 DIS_AUTOSTRIP))
781 },
782 { XE_RTP_NAME("15016589081"),
783 XE_RTP_RULES(GRAPHICS_VERSION(2001), ENGINE_CLASS(RENDER)),
784 XE_RTP_ACTIONS(SET(CHICKEN_RASTER_1, DIS_CLIP_NEGATIVE_BOUNDING_BOX))
785 },
786 { XE_RTP_NAME("22021007897"),
787 XE_RTP_RULES(GRAPHICS_VERSION(2001), ENGINE_CLASS(RENDER)),
788 XE_RTP_ACTIONS(SET(COMMON_SLICE_CHICKEN4, SBE_PUSH_CONSTANT_BEHIND_FIX_ENABLE))
789 },
790
791 /* Xe3_LPG */
792 { XE_RTP_NAME("14021490052"),
793 XE_RTP_RULES(GRAPHICS_VERSION(3000), GRAPHICS_STEP(A0, B0),
794 ENGINE_CLASS(RENDER)),
795 XE_RTP_ACTIONS(SET(FF_MODE,
796 DIS_MESH_PARTIAL_AUTOSTRIP |
797 DIS_MESH_AUTOSTRIP),
798 SET(VFLSKPD,
799 DIS_PARTIAL_AUTOSTRIP |
800 DIS_AUTOSTRIP))
801 },
802
803 {}
804 };
805
806 static __maybe_unused const struct xe_rtp_entry oob_was[] = {
807 #include <generated/xe_wa_oob.c>
808 {}
809 };
810
811 static_assert(ARRAY_SIZE(oob_was) - 1 == _XE_WA_OOB_COUNT);
812
813 __diag_pop();
814
815 /**
816 * xe_wa_process_oob - process OOB workaround table
817 * @gt: GT instance to process workarounds for
818 *
819 * Process OOB workaround table for this platform, marking in @gt the
820 * workarounds that are active.
821 */
xe_wa_process_oob(struct xe_gt * gt)822 void xe_wa_process_oob(struct xe_gt *gt)
823 {
824 struct xe_rtp_process_ctx ctx = XE_RTP_PROCESS_CTX_INITIALIZER(gt);
825
826 xe_rtp_process_ctx_enable_active_tracking(&ctx, gt->wa_active.oob,
827 ARRAY_SIZE(oob_was));
828 gt->wa_active.oob_initialized = true;
829 xe_rtp_process(&ctx, oob_was);
830 }
831
832 /**
833 * xe_wa_process_gt - process GT workaround table
834 * @gt: GT instance to process workarounds for
835 *
836 * Process GT workaround table for this platform, saving in @gt all the
837 * workarounds that need to be applied at the GT level.
838 */
xe_wa_process_gt(struct xe_gt * gt)839 void xe_wa_process_gt(struct xe_gt *gt)
840 {
841 struct xe_rtp_process_ctx ctx = XE_RTP_PROCESS_CTX_INITIALIZER(gt);
842
843 xe_rtp_process_ctx_enable_active_tracking(&ctx, gt->wa_active.gt,
844 ARRAY_SIZE(gt_was));
845 xe_rtp_process_to_sr(&ctx, gt_was, >->reg_sr);
846 }
847 EXPORT_SYMBOL_IF_KUNIT(xe_wa_process_gt);
848
849 /**
850 * xe_wa_process_engine - process engine workaround table
851 * @hwe: engine instance to process workarounds for
852 *
853 * Process engine workaround table for this platform, saving in @hwe all the
854 * workarounds that need to be applied at the engine level that match this
855 * engine.
856 */
xe_wa_process_engine(struct xe_hw_engine * hwe)857 void xe_wa_process_engine(struct xe_hw_engine *hwe)
858 {
859 struct xe_rtp_process_ctx ctx = XE_RTP_PROCESS_CTX_INITIALIZER(hwe);
860
861 xe_rtp_process_ctx_enable_active_tracking(&ctx, hwe->gt->wa_active.engine,
862 ARRAY_SIZE(engine_was));
863 xe_rtp_process_to_sr(&ctx, engine_was, &hwe->reg_sr);
864 }
865
866 /**
867 * xe_wa_process_lrc - process context workaround table
868 * @hwe: engine instance to process workarounds for
869 *
870 * Process context workaround table for this platform, saving in @hwe all the
871 * workarounds that need to be applied on context restore. These are workarounds
872 * touching registers that are part of the HW context image.
873 */
xe_wa_process_lrc(struct xe_hw_engine * hwe)874 void xe_wa_process_lrc(struct xe_hw_engine *hwe)
875 {
876 struct xe_rtp_process_ctx ctx = XE_RTP_PROCESS_CTX_INITIALIZER(hwe);
877
878 xe_rtp_process_ctx_enable_active_tracking(&ctx, hwe->gt->wa_active.lrc,
879 ARRAY_SIZE(lrc_was));
880 xe_rtp_process_to_sr(&ctx, lrc_was, &hwe->reg_lrc);
881 }
882
883 /**
884 * xe_wa_init - initialize gt with workaround bookkeeping
885 * @gt: GT instance to initialize
886 *
887 * Returns 0 for success, negative error code otherwise.
888 */
xe_wa_init(struct xe_gt * gt)889 int xe_wa_init(struct xe_gt *gt)
890 {
891 struct xe_device *xe = gt_to_xe(gt);
892 size_t n_oob, n_lrc, n_engine, n_gt, total;
893 unsigned long *p;
894
895 n_gt = BITS_TO_LONGS(ARRAY_SIZE(gt_was));
896 n_engine = BITS_TO_LONGS(ARRAY_SIZE(engine_was));
897 n_lrc = BITS_TO_LONGS(ARRAY_SIZE(lrc_was));
898 n_oob = BITS_TO_LONGS(ARRAY_SIZE(oob_was));
899 total = n_gt + n_engine + n_lrc + n_oob;
900
901 p = drmm_kzalloc(&xe->drm, sizeof(*p) * total, GFP_KERNEL);
902 if (!p)
903 return -ENOMEM;
904
905 gt->wa_active.gt = p;
906 p += n_gt;
907 gt->wa_active.engine = p;
908 p += n_engine;
909 gt->wa_active.lrc = p;
910 p += n_lrc;
911 gt->wa_active.oob = p;
912
913 return 0;
914 }
915
xe_wa_dump(struct xe_gt * gt,struct drm_printer * p)916 void xe_wa_dump(struct xe_gt *gt, struct drm_printer *p)
917 {
918 size_t idx;
919
920 drm_printf(p, "GT Workarounds\n");
921 for_each_set_bit(idx, gt->wa_active.gt, ARRAY_SIZE(gt_was))
922 drm_printf_indent(p, 1, "%s\n", gt_was[idx].name);
923
924 drm_printf(p, "\nEngine Workarounds\n");
925 for_each_set_bit(idx, gt->wa_active.engine, ARRAY_SIZE(engine_was))
926 drm_printf_indent(p, 1, "%s\n", engine_was[idx].name);
927
928 drm_printf(p, "\nLRC Workarounds\n");
929 for_each_set_bit(idx, gt->wa_active.lrc, ARRAY_SIZE(lrc_was))
930 drm_printf_indent(p, 1, "%s\n", lrc_was[idx].name);
931
932 drm_printf(p, "\nOOB Workarounds\n");
933 for_each_set_bit(idx, gt->wa_active.oob, ARRAY_SIZE(oob_was))
934 if (oob_was[idx].name)
935 drm_printf_indent(p, 1, "%s\n", oob_was[idx].name);
936 }
937
938 /*
939 * Apply tile (non-GT, non-display) workarounds. Think very carefully before
940 * adding anything to this function; most workarounds should be implemented
941 * elsewhere. The programming here is primarily for sgunit/soc workarounds,
942 * which are relatively rare. Since the registers these workarounds target are
943 * outside the GT, they should only need to be applied once at device
944 * probe/resume; they will not lose their values on any kind of GT or engine
945 * reset.
946 *
947 * TODO: We may want to move this over to xe_rtp in the future once we have
948 * enough workarounds to justify the work.
949 */
xe_wa_apply_tile_workarounds(struct xe_tile * tile)950 void xe_wa_apply_tile_workarounds(struct xe_tile *tile)
951 {
952 struct xe_gt *mmio = tile->primary_gt;
953
954 if (IS_SRIOV_VF(tile->xe))
955 return;
956
957 if (XE_WA(mmio, 22010954014))
958 xe_mmio_rmw32(mmio, XEHP_CLOCK_GATE_DIS, 0, SGSI_SIDECLK_DIS);
959 }
960