1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (c) 2014, The Linux Foundation. All rights reserved.
4 */
5
6 #include <linux/acpi.h>
7 #include <linux/bitops.h>
8 #include <linux/kernel.h>
9 #include <linux/moduleparam.h>
10 #include <linux/init.h>
11 #include <linux/types.h>
12 #include <linux/device.h>
13 #include <linux/io.h>
14 #include <linux/err.h>
15 #include <linux/fs.h>
16 #include <linux/slab.h>
17 #include <linux/delay.h>
18 #include <linux/smp.h>
19 #include <linux/sysfs.h>
20 #include <linux/stat.h>
21 #include <linux/clk.h>
22 #include <linux/cpu.h>
23 #include <linux/cpu_pm.h>
24 #include <linux/coresight.h>
25 #include <linux/coresight-pmu.h>
26 #include <linux/pm_wakeup.h>
27 #include <linux/amba/bus.h>
28 #include <linux/seq_file.h>
29 #include <linux/uaccess.h>
30 #include <linux/perf_event.h>
31 #include <linux/platform_device.h>
32 #include <linux/pm_runtime.h>
33 #include <linux/property.h>
34 #include <linux/clk/clk-conf.h>
35
36 #include <asm/barrier.h>
37 #include <asm/sections.h>
38 #include <asm/sysreg.h>
39 #include <asm/local.h>
40 #include <asm/virt.h>
41
42 #include "coresight-etm4x.h"
43 #include "coresight-etm-perf.h"
44 #include "coresight-etm4x-cfg.h"
45 #include "coresight-self-hosted-trace.h"
46 #include "coresight-syscfg.h"
47 #include "coresight-trace-id.h"
48
49 static int boot_enable;
50 module_param(boot_enable, int, 0444);
51 MODULE_PARM_DESC(boot_enable, "Enable tracing on boot");
52
53 #define PARAM_PM_SAVE_FIRMWARE 0 /* save self-hosted state as per firmware */
54 #define PARAM_PM_SAVE_NEVER 1 /* never save any state */
55 #define PARAM_PM_SAVE_SELF_HOSTED 2 /* save self-hosted state only */
56
57 static int pm_save_enable = PARAM_PM_SAVE_FIRMWARE;
58 module_param(pm_save_enable, int, 0444);
59 MODULE_PARM_DESC(pm_save_enable,
60 "Save/restore state on power down: 1 = never, 2 = self-hosted");
61
62 static struct etmv4_drvdata *etmdrvdata[NR_CPUS];
63 static void etm4_set_default_config(struct etmv4_config *config);
64 static int etm4_set_event_filters(struct etmv4_drvdata *drvdata,
65 struct perf_event *event);
66 static u64 etm4_get_access_type(struct etmv4_config *config);
67
68 static enum cpuhp_state hp_online;
69
70 struct etm4_init_arg {
71 struct device *dev;
72 struct csdev_access *csa;
73 };
74
75 static DEFINE_PER_CPU(struct etm4_init_arg *, delayed_probe);
76 static int etm4_probe_cpu(unsigned int cpu);
77
78 /*
79 * Check if TRCSSPCICRn(i) is implemented for a given instance.
80 *
81 * TRCSSPCICRn is implemented only if :
82 * TRCSSPCICR<n> is present only if all of the following are true:
83 * TRCIDR4.NUMSSCC > n.
84 * TRCIDR4.NUMPC > 0b0000 .
85 * TRCSSCSR<n>.PC == 0b1
86 */
etm4x_sspcicrn_present(struct etmv4_drvdata * drvdata,int n)87 static inline bool etm4x_sspcicrn_present(struct etmv4_drvdata *drvdata, int n)
88 {
89 return (n < drvdata->nr_ss_cmp) &&
90 drvdata->nr_pe &&
91 (drvdata->config.ss_status[n] & TRCSSCSRn_PC);
92 }
93
etm4x_sysreg_read(u32 offset,bool _relaxed,bool _64bit)94 u64 etm4x_sysreg_read(u32 offset, bool _relaxed, bool _64bit)
95 {
96 u64 res = 0;
97
98 switch (offset) {
99 ETM4x_READ_SYSREG_CASES(res)
100 default :
101 pr_warn_ratelimited("etm4x: trying to read unsupported register @%x\n",
102 offset);
103 }
104
105 if (!_relaxed)
106 __io_ar(res); /* Imitate the !relaxed I/O helpers */
107
108 return res;
109 }
110
etm4x_sysreg_write(u64 val,u32 offset,bool _relaxed,bool _64bit)111 void etm4x_sysreg_write(u64 val, u32 offset, bool _relaxed, bool _64bit)
112 {
113 if (!_relaxed)
114 __io_bw(); /* Imitate the !relaxed I/O helpers */
115 if (!_64bit)
116 val &= GENMASK(31, 0);
117
118 switch (offset) {
119 ETM4x_WRITE_SYSREG_CASES(val)
120 default :
121 pr_warn_ratelimited("etm4x: trying to write to unsupported register @%x\n",
122 offset);
123 }
124 }
125
ete_sysreg_read(u32 offset,bool _relaxed,bool _64bit)126 static u64 ete_sysreg_read(u32 offset, bool _relaxed, bool _64bit)
127 {
128 u64 res = 0;
129
130 switch (offset) {
131 ETE_READ_CASES(res)
132 default :
133 pr_warn_ratelimited("ete: trying to read unsupported register @%x\n",
134 offset);
135 }
136
137 if (!_relaxed)
138 __io_ar(res); /* Imitate the !relaxed I/O helpers */
139
140 return res;
141 }
142
ete_sysreg_write(u64 val,u32 offset,bool _relaxed,bool _64bit)143 static void ete_sysreg_write(u64 val, u32 offset, bool _relaxed, bool _64bit)
144 {
145 if (!_relaxed)
146 __io_bw(); /* Imitate the !relaxed I/O helpers */
147 if (!_64bit)
148 val &= GENMASK(31, 0);
149
150 switch (offset) {
151 ETE_WRITE_CASES(val)
152 default :
153 pr_warn_ratelimited("ete: trying to write to unsupported register @%x\n",
154 offset);
155 }
156 }
157
etm_detect_os_lock(struct etmv4_drvdata * drvdata,struct csdev_access * csa)158 static void etm_detect_os_lock(struct etmv4_drvdata *drvdata,
159 struct csdev_access *csa)
160 {
161 u32 oslsr = etm4x_relaxed_read32(csa, TRCOSLSR);
162
163 drvdata->os_lock_model = ETM_OSLSR_OSLM(oslsr);
164 }
165
etm_write_os_lock(struct etmv4_drvdata * drvdata,struct csdev_access * csa,u32 val)166 static void etm_write_os_lock(struct etmv4_drvdata *drvdata,
167 struct csdev_access *csa, u32 val)
168 {
169 val = !!val;
170
171 switch (drvdata->os_lock_model) {
172 case ETM_OSLOCK_PRESENT:
173 etm4x_relaxed_write32(csa, val, TRCOSLAR);
174 break;
175 case ETM_OSLOCK_PE:
176 write_sysreg_s(val, SYS_OSLAR_EL1);
177 break;
178 default:
179 pr_warn_once("CPU%d: Unsupported Trace OSLock model: %x\n",
180 smp_processor_id(), drvdata->os_lock_model);
181 fallthrough;
182 case ETM_OSLOCK_NI:
183 return;
184 }
185 isb();
186 }
187
etm4_os_unlock_csa(struct etmv4_drvdata * drvdata,struct csdev_access * csa)188 static inline void etm4_os_unlock_csa(struct etmv4_drvdata *drvdata,
189 struct csdev_access *csa)
190 {
191 WARN_ON(drvdata->cpu != smp_processor_id());
192
193 /* Writing 0 to OS Lock unlocks the trace unit registers */
194 etm_write_os_lock(drvdata, csa, 0x0);
195 drvdata->os_unlock = true;
196 }
197
etm4_os_unlock(struct etmv4_drvdata * drvdata)198 static void etm4_os_unlock(struct etmv4_drvdata *drvdata)
199 {
200 if (!WARN_ON(!drvdata->csdev))
201 etm4_os_unlock_csa(drvdata, &drvdata->csdev->access);
202 }
203
etm4_os_lock(struct etmv4_drvdata * drvdata)204 static void etm4_os_lock(struct etmv4_drvdata *drvdata)
205 {
206 if (WARN_ON(!drvdata->csdev))
207 return;
208 /* Writing 0x1 to OS Lock locks the trace registers */
209 etm_write_os_lock(drvdata, &drvdata->csdev->access, 0x1);
210 drvdata->os_unlock = false;
211 }
212
etm4_cs_lock(struct etmv4_drvdata * drvdata,struct csdev_access * csa)213 static void etm4_cs_lock(struct etmv4_drvdata *drvdata,
214 struct csdev_access *csa)
215 {
216 /* Software Lock is only accessible via memory mapped interface */
217 if (csa->io_mem)
218 CS_LOCK(csa->base);
219 }
220
etm4_cs_unlock(struct etmv4_drvdata * drvdata,struct csdev_access * csa)221 static void etm4_cs_unlock(struct etmv4_drvdata *drvdata,
222 struct csdev_access *csa)
223 {
224 if (csa->io_mem)
225 CS_UNLOCK(csa->base);
226 }
227
etm4_cpu_id(struct coresight_device * csdev)228 static int etm4_cpu_id(struct coresight_device *csdev)
229 {
230 struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
231
232 return drvdata->cpu;
233 }
234
etm4_read_alloc_trace_id(struct etmv4_drvdata * drvdata)235 int etm4_read_alloc_trace_id(struct etmv4_drvdata *drvdata)
236 {
237 int trace_id;
238
239 /*
240 * This will allocate a trace ID to the cpu,
241 * or return the one currently allocated.
242 * The trace id function has its own lock
243 */
244 trace_id = coresight_trace_id_get_cpu_id(drvdata->cpu);
245 if (IS_VALID_CS_TRACE_ID(trace_id))
246 drvdata->trcid = (u8)trace_id;
247 else
248 dev_err(&drvdata->csdev->dev,
249 "Failed to allocate trace ID for %s on CPU%d\n",
250 dev_name(&drvdata->csdev->dev), drvdata->cpu);
251 return trace_id;
252 }
253
etm4_release_trace_id(struct etmv4_drvdata * drvdata)254 void etm4_release_trace_id(struct etmv4_drvdata *drvdata)
255 {
256 coresight_trace_id_put_cpu_id(drvdata->cpu);
257 }
258
259 struct etm4_enable_arg {
260 struct etmv4_drvdata *drvdata;
261 int rc;
262 };
263
264 /*
265 * etm4x_prohibit_trace - Prohibit the CPU from tracing at all ELs.
266 * When the CPU supports FEAT_TRF, we could move the ETM to a trace
267 * prohibited state by filtering the Exception levels via TRFCR_EL1.
268 */
etm4x_prohibit_trace(struct etmv4_drvdata * drvdata)269 static void etm4x_prohibit_trace(struct etmv4_drvdata *drvdata)
270 {
271 /* If the CPU doesn't support FEAT_TRF, nothing to do */
272 if (!drvdata->trfcr)
273 return;
274 cpu_prohibit_trace();
275 }
276
277 /*
278 * etm4x_allow_trace - Allow CPU tracing in the respective ELs,
279 * as configured by the drvdata->config.mode for the current
280 * session. Even though we have TRCVICTLR bits to filter the
281 * trace in the ELs, it doesn't prevent the ETM from generating
282 * a packet (e.g, TraceInfo) that might contain the addresses from
283 * the excluded levels. Thus we use the additional controls provided
284 * via the Trace Filtering controls (FEAT_TRF) to make sure no trace
285 * is generated for the excluded ELs.
286 */
etm4x_allow_trace(struct etmv4_drvdata * drvdata)287 static void etm4x_allow_trace(struct etmv4_drvdata *drvdata)
288 {
289 u64 trfcr = drvdata->trfcr;
290
291 /* If the CPU doesn't support FEAT_TRF, nothing to do */
292 if (!trfcr)
293 return;
294
295 if (drvdata->config.mode & ETM_MODE_EXCL_KERN)
296 trfcr &= ~TRFCR_ELx_ExTRE;
297 if (drvdata->config.mode & ETM_MODE_EXCL_USER)
298 trfcr &= ~TRFCR_ELx_E0TRE;
299
300 write_trfcr(trfcr);
301 }
302
303 #ifdef CONFIG_ETM4X_IMPDEF_FEATURE
304
305 #define HISI_HIP08_AMBA_ID 0x000b6d01
306 #define ETM4_AMBA_MASK 0xfffff
307 #define HISI_HIP08_CORE_COMMIT_MASK 0x3000
308 #define HISI_HIP08_CORE_COMMIT_SHIFT 12
309 #define HISI_HIP08_CORE_COMMIT_FULL 0b00
310 #define HISI_HIP08_CORE_COMMIT_LVL_1 0b01
311 #define HISI_HIP08_CORE_COMMIT_REG sys_reg(3, 1, 15, 2, 5)
312
313 struct etm4_arch_features {
314 void (*arch_callback)(bool enable);
315 };
316
etm4_hisi_match_pid(unsigned int id)317 static bool etm4_hisi_match_pid(unsigned int id)
318 {
319 return (id & ETM4_AMBA_MASK) == HISI_HIP08_AMBA_ID;
320 }
321
etm4_hisi_config_core_commit(bool enable)322 static void etm4_hisi_config_core_commit(bool enable)
323 {
324 u8 commit = enable ? HISI_HIP08_CORE_COMMIT_LVL_1 :
325 HISI_HIP08_CORE_COMMIT_FULL;
326 u64 val;
327
328 /*
329 * bit 12 and 13 of HISI_HIP08_CORE_COMMIT_REG are used together
330 * to set core-commit, 2'b00 means cpu is at full speed, 2'b01,
331 * 2'b10, 2'b11 mean reduce pipeline speed, and 2'b01 means level-1
332 * speed(minimun value). So bit 12 and 13 should be cleared together.
333 */
334 val = read_sysreg_s(HISI_HIP08_CORE_COMMIT_REG);
335 val &= ~HISI_HIP08_CORE_COMMIT_MASK;
336 val |= commit << HISI_HIP08_CORE_COMMIT_SHIFT;
337 write_sysreg_s(val, HISI_HIP08_CORE_COMMIT_REG);
338 }
339
340 static struct etm4_arch_features etm4_features[] = {
341 [ETM4_IMPDEF_HISI_CORE_COMMIT] = {
342 .arch_callback = etm4_hisi_config_core_commit,
343 },
344 {},
345 };
346
etm4_enable_arch_specific(struct etmv4_drvdata * drvdata)347 static void etm4_enable_arch_specific(struct etmv4_drvdata *drvdata)
348 {
349 struct etm4_arch_features *ftr;
350 int bit;
351
352 for_each_set_bit(bit, drvdata->arch_features, ETM4_IMPDEF_FEATURE_MAX) {
353 ftr = &etm4_features[bit];
354
355 if (ftr->arch_callback)
356 ftr->arch_callback(true);
357 }
358 }
359
etm4_disable_arch_specific(struct etmv4_drvdata * drvdata)360 static void etm4_disable_arch_specific(struct etmv4_drvdata *drvdata)
361 {
362 struct etm4_arch_features *ftr;
363 int bit;
364
365 for_each_set_bit(bit, drvdata->arch_features, ETM4_IMPDEF_FEATURE_MAX) {
366 ftr = &etm4_features[bit];
367
368 if (ftr->arch_callback)
369 ftr->arch_callback(false);
370 }
371 }
372
etm4_check_arch_features(struct etmv4_drvdata * drvdata,struct csdev_access * csa)373 static void etm4_check_arch_features(struct etmv4_drvdata *drvdata,
374 struct csdev_access *csa)
375 {
376 /*
377 * TRCPIDR* registers are not required for ETMs with system
378 * instructions. They must be identified by the MIDR+REVIDRs.
379 * Skip the TRCPID checks for now.
380 */
381 if (!csa->io_mem)
382 return;
383
384 if (etm4_hisi_match_pid(coresight_get_pid(csa)))
385 set_bit(ETM4_IMPDEF_HISI_CORE_COMMIT, drvdata->arch_features);
386 }
387 #else
etm4_enable_arch_specific(struct etmv4_drvdata * drvdata)388 static void etm4_enable_arch_specific(struct etmv4_drvdata *drvdata)
389 {
390 }
391
etm4_disable_arch_specific(struct etmv4_drvdata * drvdata)392 static void etm4_disable_arch_specific(struct etmv4_drvdata *drvdata)
393 {
394 }
395
etm4_check_arch_features(struct etmv4_drvdata * drvdata,struct csdev_access * csa)396 static void etm4_check_arch_features(struct etmv4_drvdata *drvdata,
397 struct csdev_access *csa)
398 {
399 }
400 #endif /* CONFIG_ETM4X_IMPDEF_FEATURE */
401
etm4x_sys_ins_barrier(struct csdev_access * csa,u32 offset,int pos,int val)402 static void etm4x_sys_ins_barrier(struct csdev_access *csa, u32 offset, int pos, int val)
403 {
404 if (!csa->io_mem)
405 isb();
406 }
407
408 /*
409 * etm4x_wait_status: Poll for TRCSTATR.<pos> == <val>. While using system
410 * instruction to access the trace unit, each access must be separated by a
411 * synchronization barrier. See ARM IHI0064H.b section "4.3.7 Synchronization of
412 * register updates", for system instructions section, in "Notes":
413 *
414 * "In particular, whenever disabling or enabling the trace unit, a poll of
415 * TRCSTATR needs explicit synchronization between each read of TRCSTATR"
416 */
etm4x_wait_status(struct csdev_access * csa,int pos,int val)417 static int etm4x_wait_status(struct csdev_access *csa, int pos, int val)
418 {
419 if (!csa->io_mem)
420 return coresight_timeout_action(csa, TRCSTATR, pos, val,
421 etm4x_sys_ins_barrier);
422 return coresight_timeout(csa, TRCSTATR, pos, val);
423 }
424
etm4_enable_hw(struct etmv4_drvdata * drvdata)425 static int etm4_enable_hw(struct etmv4_drvdata *drvdata)
426 {
427 int i, rc;
428 struct etmv4_config *config = &drvdata->config;
429 struct coresight_device *csdev = drvdata->csdev;
430 struct device *etm_dev = &csdev->dev;
431 struct csdev_access *csa = &csdev->access;
432
433
434 etm4_cs_unlock(drvdata, csa);
435 etm4_enable_arch_specific(drvdata);
436
437 etm4_os_unlock(drvdata);
438
439 rc = coresight_claim_device_unlocked(csdev);
440 if (rc)
441 goto done;
442
443 /* Disable the trace unit before programming trace registers */
444 etm4x_relaxed_write32(csa, 0, TRCPRGCTLR);
445
446 /*
447 * If we use system instructions, we need to synchronize the
448 * write to the TRCPRGCTLR, before accessing the TRCSTATR.
449 * See ARM IHI0064F, section
450 * "4.3.7 Synchronization of register updates"
451 */
452 if (!csa->io_mem)
453 isb();
454
455 /* wait for TRCSTATR.IDLE to go up */
456 if (etm4x_wait_status(csa, TRCSTATR_IDLE_BIT, 1))
457 dev_err(etm_dev,
458 "timeout while waiting for Idle Trace Status\n");
459 if (drvdata->nr_pe)
460 etm4x_relaxed_write32(csa, config->pe_sel, TRCPROCSELR);
461 etm4x_relaxed_write32(csa, config->cfg, TRCCONFIGR);
462 /* nothing specific implemented */
463 etm4x_relaxed_write32(csa, 0x0, TRCAUXCTLR);
464 etm4x_relaxed_write32(csa, config->eventctrl0, TRCEVENTCTL0R);
465 etm4x_relaxed_write32(csa, config->eventctrl1, TRCEVENTCTL1R);
466 if (drvdata->stallctl)
467 etm4x_relaxed_write32(csa, config->stall_ctrl, TRCSTALLCTLR);
468 etm4x_relaxed_write32(csa, config->ts_ctrl, TRCTSCTLR);
469 etm4x_relaxed_write32(csa, config->syncfreq, TRCSYNCPR);
470 etm4x_relaxed_write32(csa, config->ccctlr, TRCCCCTLR);
471 etm4x_relaxed_write32(csa, config->bb_ctrl, TRCBBCTLR);
472 etm4x_relaxed_write32(csa, drvdata->trcid, TRCTRACEIDR);
473 etm4x_relaxed_write32(csa, config->vinst_ctrl, TRCVICTLR);
474 etm4x_relaxed_write32(csa, config->viiectlr, TRCVIIECTLR);
475 etm4x_relaxed_write32(csa, config->vissctlr, TRCVISSCTLR);
476 if (drvdata->nr_pe_cmp)
477 etm4x_relaxed_write32(csa, config->vipcssctlr, TRCVIPCSSCTLR);
478 for (i = 0; i < drvdata->nrseqstate - 1; i++)
479 etm4x_relaxed_write32(csa, config->seq_ctrl[i], TRCSEQEVRn(i));
480 if (drvdata->nrseqstate) {
481 etm4x_relaxed_write32(csa, config->seq_rst, TRCSEQRSTEVR);
482 etm4x_relaxed_write32(csa, config->seq_state, TRCSEQSTR);
483 }
484 etm4x_relaxed_write32(csa, config->ext_inp, TRCEXTINSELR);
485 for (i = 0; i < drvdata->nr_cntr; i++) {
486 etm4x_relaxed_write32(csa, config->cntrldvr[i], TRCCNTRLDVRn(i));
487 etm4x_relaxed_write32(csa, config->cntr_ctrl[i], TRCCNTCTLRn(i));
488 etm4x_relaxed_write32(csa, config->cntr_val[i], TRCCNTVRn(i));
489 }
490
491 /*
492 * Resource selector pair 0 is always implemented and reserved. As
493 * such start at 2.
494 */
495 for (i = 2; i < drvdata->nr_resource * 2; i++)
496 etm4x_relaxed_write32(csa, config->res_ctrl[i], TRCRSCTLRn(i));
497
498 for (i = 0; i < drvdata->nr_ss_cmp; i++) {
499 /* always clear status bit on restart if using single-shot */
500 if (config->ss_ctrl[i] || config->ss_pe_cmp[i])
501 config->ss_status[i] &= ~TRCSSCSRn_STATUS;
502 etm4x_relaxed_write32(csa, config->ss_ctrl[i], TRCSSCCRn(i));
503 etm4x_relaxed_write32(csa, config->ss_status[i], TRCSSCSRn(i));
504 if (etm4x_sspcicrn_present(drvdata, i))
505 etm4x_relaxed_write32(csa, config->ss_pe_cmp[i], TRCSSPCICRn(i));
506 }
507 for (i = 0; i < drvdata->nr_addr_cmp * 2; i++) {
508 etm4x_relaxed_write64(csa, config->addr_val[i], TRCACVRn(i));
509 etm4x_relaxed_write64(csa, config->addr_acc[i], TRCACATRn(i));
510 }
511 for (i = 0; i < drvdata->numcidc; i++)
512 etm4x_relaxed_write64(csa, config->ctxid_pid[i], TRCCIDCVRn(i));
513 etm4x_relaxed_write32(csa, config->ctxid_mask0, TRCCIDCCTLR0);
514 if (drvdata->numcidc > 4)
515 etm4x_relaxed_write32(csa, config->ctxid_mask1, TRCCIDCCTLR1);
516
517 for (i = 0; i < drvdata->numvmidc; i++)
518 etm4x_relaxed_write64(csa, config->vmid_val[i], TRCVMIDCVRn(i));
519 etm4x_relaxed_write32(csa, config->vmid_mask0, TRCVMIDCCTLR0);
520 if (drvdata->numvmidc > 4)
521 etm4x_relaxed_write32(csa, config->vmid_mask1, TRCVMIDCCTLR1);
522
523 if (!drvdata->skip_power_up) {
524 u32 trcpdcr = etm4x_relaxed_read32(csa, TRCPDCR);
525
526 /*
527 * Request to keep the trace unit powered and also
528 * emulation of powerdown
529 */
530 etm4x_relaxed_write32(csa, trcpdcr | TRCPDCR_PU, TRCPDCR);
531 }
532
533 /*
534 * ETE mandates that the TRCRSR is written to before
535 * enabling it.
536 */
537 if (etm4x_is_ete(drvdata))
538 etm4x_relaxed_write32(csa, TRCRSR_TA, TRCRSR);
539
540 etm4x_allow_trace(drvdata);
541 /* Enable the trace unit */
542 etm4x_relaxed_write32(csa, 1, TRCPRGCTLR);
543
544 /* Synchronize the register updates for sysreg access */
545 if (!csa->io_mem)
546 isb();
547
548 /* wait for TRCSTATR.IDLE to go back down to '0' */
549 if (etm4x_wait_status(csa, TRCSTATR_IDLE_BIT, 0))
550 dev_err(etm_dev,
551 "timeout while waiting for Idle Trace Status\n");
552
553 /*
554 * As recommended by section 4.3.7 ("Synchronization when using the
555 * memory-mapped interface") of ARM IHI 0064D
556 */
557 dsb(sy);
558 isb();
559
560 done:
561 etm4_cs_lock(drvdata, csa);
562
563 dev_dbg(etm_dev, "cpu: %d enable smp call done: %d\n",
564 drvdata->cpu, rc);
565 return rc;
566 }
567
etm4_enable_hw_smp_call(void * info)568 static void etm4_enable_hw_smp_call(void *info)
569 {
570 struct etm4_enable_arg *arg = info;
571
572 if (WARN_ON(!arg))
573 return;
574 arg->rc = etm4_enable_hw(arg->drvdata);
575 }
576
577 /*
578 * The goal of function etm4_config_timestamp_event() is to configure a
579 * counter that will tell the tracer to emit a timestamp packet when it
580 * reaches zero. This is done in order to get a more fine grained idea
581 * of when instructions are executed so that they can be correlated
582 * with execution on other CPUs.
583 *
584 * To do this the counter itself is configured to self reload and
585 * TRCRSCTLR1 (always true) used to get the counter to decrement. From
586 * there a resource selector is configured with the counter and the
587 * timestamp control register to use the resource selector to trigger the
588 * event that will insert a timestamp packet in the stream.
589 */
etm4_config_timestamp_event(struct etmv4_drvdata * drvdata)590 static int etm4_config_timestamp_event(struct etmv4_drvdata *drvdata)
591 {
592 int ctridx, ret = -EINVAL;
593 int counter, rselector;
594 u32 val = 0;
595 struct etmv4_config *config = &drvdata->config;
596
597 /* No point in trying if we don't have at least one counter */
598 if (!drvdata->nr_cntr)
599 goto out;
600
601 /* Find a counter that hasn't been initialised */
602 for (ctridx = 0; ctridx < drvdata->nr_cntr; ctridx++)
603 if (config->cntr_val[ctridx] == 0)
604 break;
605
606 /* All the counters have been configured already, bail out */
607 if (ctridx == drvdata->nr_cntr) {
608 pr_debug("%s: no available counter found\n", __func__);
609 ret = -ENOSPC;
610 goto out;
611 }
612
613 /*
614 * Searching for an available resource selector to use, starting at
615 * '2' since every implementation has at least 2 resource selector.
616 * ETMIDR4 gives the number of resource selector _pairs_,
617 * hence multiply by 2.
618 */
619 for (rselector = 2; rselector < drvdata->nr_resource * 2; rselector++)
620 if (!config->res_ctrl[rselector])
621 break;
622
623 if (rselector == drvdata->nr_resource * 2) {
624 pr_debug("%s: no available resource selector found\n",
625 __func__);
626 ret = -ENOSPC;
627 goto out;
628 }
629
630 /* Remember what counter we used */
631 counter = 1 << ctridx;
632
633 /*
634 * Initialise original and reload counter value to the smallest
635 * possible value in order to get as much precision as we can.
636 */
637 config->cntr_val[ctridx] = 1;
638 config->cntrldvr[ctridx] = 1;
639
640 /* Set the trace counter control register */
641 val = 0x1 << 16 | /* Bit 16, reload counter automatically */
642 0x0 << 7 | /* Select single resource selector */
643 0x1; /* Resource selector 1, i.e always true */
644
645 config->cntr_ctrl[ctridx] = val;
646
647 val = 0x2 << 16 | /* Group 0b0010 - Counter and sequencers */
648 counter << 0; /* Counter to use */
649
650 config->res_ctrl[rselector] = val;
651
652 val = 0x0 << 7 | /* Select single resource selector */
653 rselector; /* Resource selector */
654
655 config->ts_ctrl = val;
656
657 ret = 0;
658 out:
659 return ret;
660 }
661
etm4_parse_event_config(struct coresight_device * csdev,struct perf_event * event)662 static int etm4_parse_event_config(struct coresight_device *csdev,
663 struct perf_event *event)
664 {
665 int ret = 0;
666 struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
667 struct etmv4_config *config = &drvdata->config;
668 struct perf_event_attr *attr = &event->attr;
669 unsigned long cfg_hash;
670 int preset, cc_threshold;
671
672 /* Clear configuration from previous run */
673 memset(config, 0, sizeof(struct etmv4_config));
674
675 if (attr->exclude_kernel)
676 config->mode = ETM_MODE_EXCL_KERN;
677
678 if (attr->exclude_user)
679 config->mode = ETM_MODE_EXCL_USER;
680
681 /* Always start from the default config */
682 etm4_set_default_config(config);
683
684 /* Configure filters specified on the perf cmd line, if any. */
685 ret = etm4_set_event_filters(drvdata, event);
686 if (ret)
687 goto out;
688
689 /* Go from generic option to ETMv4 specifics */
690 if (attr->config & BIT(ETM_OPT_CYCACC)) {
691 config->cfg |= TRCCONFIGR_CCI;
692 /* TRM: Must program this for cycacc to work */
693 cc_threshold = attr->config3 & ETM_CYC_THRESHOLD_MASK;
694 if (!cc_threshold)
695 cc_threshold = ETM_CYC_THRESHOLD_DEFAULT;
696 if (cc_threshold < drvdata->ccitmin)
697 cc_threshold = drvdata->ccitmin;
698 config->ccctlr = cc_threshold;
699 }
700 if (attr->config & BIT(ETM_OPT_TS)) {
701 /*
702 * Configure timestamps to be emitted at regular intervals in
703 * order to correlate instructions executed on different CPUs
704 * (CPU-wide trace scenarios).
705 */
706 ret = etm4_config_timestamp_event(drvdata);
707
708 /*
709 * No need to go further if timestamp intervals can't
710 * be configured.
711 */
712 if (ret)
713 goto out;
714
715 /* bit[11], Global timestamp tracing bit */
716 config->cfg |= TRCCONFIGR_TS;
717 }
718
719 /* Only trace contextID when runs in root PID namespace */
720 if ((attr->config & BIT(ETM_OPT_CTXTID)) &&
721 task_is_in_init_pid_ns(current))
722 /* bit[6], Context ID tracing bit */
723 config->cfg |= TRCCONFIGR_CID;
724
725 /*
726 * If set bit ETM_OPT_CTXTID2 in perf config, this asks to trace VMID
727 * for recording CONTEXTIDR_EL2. Do not enable VMID tracing if the
728 * kernel is not running in EL2.
729 */
730 if (attr->config & BIT(ETM_OPT_CTXTID2)) {
731 if (!is_kernel_in_hyp_mode()) {
732 ret = -EINVAL;
733 goto out;
734 }
735 /* Only trace virtual contextID when runs in root PID namespace */
736 if (task_is_in_init_pid_ns(current))
737 config->cfg |= TRCCONFIGR_VMID | TRCCONFIGR_VMIDOPT;
738 }
739
740 /* return stack - enable if selected and supported */
741 if ((attr->config & BIT(ETM_OPT_RETSTK)) && drvdata->retstack)
742 /* bit[12], Return stack enable bit */
743 config->cfg |= TRCCONFIGR_RS;
744
745 /*
746 * Set any selected configuration and preset.
747 *
748 * This extracts the values of PMU_FORMAT_ATTR(configid) and PMU_FORMAT_ATTR(preset)
749 * in the perf attributes defined in coresight-etm-perf.c.
750 * configid uses bits 63:32 of attr->config2, preset uses bits 3:0 of attr->config.
751 * A zero configid means no configuration active, preset = 0 means no preset selected.
752 */
753 if (attr->config2 & GENMASK_ULL(63, 32)) {
754 cfg_hash = (u32)(attr->config2 >> 32);
755 preset = attr->config & 0xF;
756 ret = cscfg_csdev_enable_active_config(csdev, cfg_hash, preset);
757 }
758
759 /* branch broadcast - enable if selected and supported */
760 if (attr->config & BIT(ETM_OPT_BRANCH_BROADCAST)) {
761 if (!drvdata->trcbb) {
762 /*
763 * Missing BB support could cause silent decode errors
764 * so fail to open if it's not supported.
765 */
766 ret = -EINVAL;
767 goto out;
768 } else {
769 config->cfg |= BIT(ETM4_CFG_BIT_BB);
770 }
771 }
772
773 out:
774 return ret;
775 }
776
etm4_enable_perf(struct coresight_device * csdev,struct perf_event * event,struct coresight_trace_id_map * id_map)777 static int etm4_enable_perf(struct coresight_device *csdev,
778 struct perf_event *event,
779 struct coresight_trace_id_map *id_map)
780 {
781 int ret = 0, trace_id;
782 struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
783
784 if (WARN_ON_ONCE(drvdata->cpu != smp_processor_id())) {
785 ret = -EINVAL;
786 goto out;
787 }
788
789 /* Configure the tracer based on the session's specifics */
790 ret = etm4_parse_event_config(csdev, event);
791 if (ret)
792 goto out;
793
794 /*
795 * perf allocates cpu ids as part of _setup_aux() - device needs to use
796 * the allocated ID. This reads the current version without allocation.
797 *
798 * This does not use the trace id lock to prevent lock_dep issues
799 * with perf locks - we know the ID cannot change until perf shuts down
800 * the session
801 */
802 trace_id = coresight_trace_id_read_cpu_id_map(drvdata->cpu, id_map);
803 if (!IS_VALID_CS_TRACE_ID(trace_id)) {
804 dev_err(&drvdata->csdev->dev, "Failed to set trace ID for %s on CPU%d\n",
805 dev_name(&drvdata->csdev->dev), drvdata->cpu);
806 ret = -EINVAL;
807 goto out;
808 }
809 drvdata->trcid = (u8)trace_id;
810
811 /* And enable it */
812 ret = etm4_enable_hw(drvdata);
813
814 out:
815 return ret;
816 }
817
etm4_enable_sysfs(struct coresight_device * csdev)818 static int etm4_enable_sysfs(struct coresight_device *csdev)
819 {
820 struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
821 struct etm4_enable_arg arg = { };
822 unsigned long cfg_hash;
823 int ret, preset;
824
825 /* enable any config activated by configfs */
826 cscfg_config_sysfs_get_active_cfg(&cfg_hash, &preset);
827 if (cfg_hash) {
828 ret = cscfg_csdev_enable_active_config(csdev, cfg_hash, preset);
829 if (ret)
830 return ret;
831 }
832
833 spin_lock(&drvdata->spinlock);
834
835 /* sysfs needs to read and allocate a trace ID */
836 ret = etm4_read_alloc_trace_id(drvdata);
837 if (ret < 0)
838 goto unlock_sysfs_enable;
839
840 /*
841 * Executing etm4_enable_hw on the cpu whose ETM is being enabled
842 * ensures that register writes occur when cpu is powered.
843 */
844 arg.drvdata = drvdata;
845 ret = smp_call_function_single(drvdata->cpu,
846 etm4_enable_hw_smp_call, &arg, 1);
847 if (!ret)
848 ret = arg.rc;
849 if (!ret)
850 drvdata->sticky_enable = true;
851
852 if (ret)
853 etm4_release_trace_id(drvdata);
854
855 unlock_sysfs_enable:
856 spin_unlock(&drvdata->spinlock);
857
858 if (!ret)
859 dev_dbg(&csdev->dev, "ETM tracing enabled\n");
860 return ret;
861 }
862
etm4_enable(struct coresight_device * csdev,struct perf_event * event,enum cs_mode mode,struct coresight_trace_id_map * id_map)863 static int etm4_enable(struct coresight_device *csdev, struct perf_event *event,
864 enum cs_mode mode, struct coresight_trace_id_map *id_map)
865 {
866 int ret;
867
868 if (!coresight_take_mode(csdev, mode)) {
869 /* Someone is already using the tracer */
870 return -EBUSY;
871 }
872
873 switch (mode) {
874 case CS_MODE_SYSFS:
875 ret = etm4_enable_sysfs(csdev);
876 break;
877 case CS_MODE_PERF:
878 ret = etm4_enable_perf(csdev, event, id_map);
879 break;
880 default:
881 ret = -EINVAL;
882 }
883
884 /* The tracer didn't start */
885 if (ret)
886 coresight_set_mode(csdev, CS_MODE_DISABLED);
887
888 return ret;
889 }
890
etm4_disable_hw(void * info)891 static void etm4_disable_hw(void *info)
892 {
893 u32 control;
894 struct etmv4_drvdata *drvdata = info;
895 struct etmv4_config *config = &drvdata->config;
896 struct coresight_device *csdev = drvdata->csdev;
897 struct device *etm_dev = &csdev->dev;
898 struct csdev_access *csa = &csdev->access;
899 int i;
900
901 etm4_cs_unlock(drvdata, csa);
902 etm4_disable_arch_specific(drvdata);
903
904 if (!drvdata->skip_power_up) {
905 /* power can be removed from the trace unit now */
906 control = etm4x_relaxed_read32(csa, TRCPDCR);
907 control &= ~TRCPDCR_PU;
908 etm4x_relaxed_write32(csa, control, TRCPDCR);
909 }
910
911 control = etm4x_relaxed_read32(csa, TRCPRGCTLR);
912
913 /* EN, bit[0] Trace unit enable bit */
914 control &= ~0x1;
915
916 /*
917 * If the CPU supports v8.4 Trace filter Control,
918 * set the ETM to trace prohibited region.
919 */
920 etm4x_prohibit_trace(drvdata);
921 /*
922 * Make sure everything completes before disabling, as recommended
923 * by section 7.3.77 ("TRCVICTLR, ViewInst Main Control Register,
924 * SSTATUS") of ARM IHI 0064D
925 */
926 dsb(sy);
927 isb();
928 /* Trace synchronization barrier, is a nop if not supported */
929 tsb_csync();
930 etm4x_relaxed_write32(csa, control, TRCPRGCTLR);
931
932 /*
933 * As recommended by section 4.3.7 ("Synchronization when using system
934 * instructions to progrom the trace unit") of ARM IHI 0064H.b, the
935 * self-hosted trace analyzer must perform a Context synchronization
936 * event between writing to the TRCPRGCTLR and reading the TRCSTATR.
937 */
938 if (!csa->io_mem)
939 isb();
940
941 /* wait for TRCSTATR.PMSTABLE to go to '1' */
942 if (etm4x_wait_status(csa, TRCSTATR_PMSTABLE_BIT, 1))
943 dev_err(etm_dev,
944 "timeout while waiting for PM stable Trace Status\n");
945 /*
946 * As recommended by section 4.3.7 (Synchronization of register updates)
947 * of ARM IHI 0064H.b.
948 */
949 isb();
950
951 /* read the status of the single shot comparators */
952 for (i = 0; i < drvdata->nr_ss_cmp; i++) {
953 config->ss_status[i] =
954 etm4x_relaxed_read32(csa, TRCSSCSRn(i));
955 }
956
957 /* read back the current counter values */
958 for (i = 0; i < drvdata->nr_cntr; i++) {
959 config->cntr_val[i] =
960 etm4x_relaxed_read32(csa, TRCCNTVRn(i));
961 }
962
963 coresight_disclaim_device_unlocked(csdev);
964 etm4_cs_lock(drvdata, csa);
965
966 dev_dbg(&drvdata->csdev->dev,
967 "cpu: %d disable smp call done\n", drvdata->cpu);
968 }
969
etm4_disable_perf(struct coresight_device * csdev,struct perf_event * event)970 static int etm4_disable_perf(struct coresight_device *csdev,
971 struct perf_event *event)
972 {
973 u32 control;
974 struct etm_filters *filters = event->hw.addr_filters;
975 struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
976 struct perf_event_attr *attr = &event->attr;
977
978 if (WARN_ON_ONCE(drvdata->cpu != smp_processor_id()))
979 return -EINVAL;
980
981 etm4_disable_hw(drvdata);
982 /*
983 * The config_id occupies bits 63:32 of the config2 perf event attr
984 * field. If this is non-zero then we will have enabled a config.
985 */
986 if (attr->config2 & GENMASK_ULL(63, 32))
987 cscfg_csdev_disable_active_config(csdev);
988
989 /*
990 * Check if the start/stop logic was active when the unit was stopped.
991 * That way we can re-enable the start/stop logic when the process is
992 * scheduled again. Configuration of the start/stop logic happens in
993 * function etm4_set_event_filters().
994 */
995 control = etm4x_relaxed_read32(&csdev->access, TRCVICTLR);
996 /* TRCVICTLR::SSSTATUS, bit[9] */
997 filters->ssstatus = (control & BIT(9));
998
999 /*
1000 * perf will release trace ids when _free_aux() is
1001 * called at the end of the session.
1002 */
1003
1004 return 0;
1005 }
1006
etm4_disable_sysfs(struct coresight_device * csdev)1007 static void etm4_disable_sysfs(struct coresight_device *csdev)
1008 {
1009 struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
1010
1011 /*
1012 * Taking hotplug lock here protects from clocks getting disabled
1013 * with tracing being left on (crash scenario) if user disable occurs
1014 * after cpu online mask indicates the cpu is offline but before the
1015 * DYING hotplug callback is serviced by the ETM driver.
1016 */
1017 cpus_read_lock();
1018 spin_lock(&drvdata->spinlock);
1019
1020 /*
1021 * Executing etm4_disable_hw on the cpu whose ETM is being disabled
1022 * ensures that register writes occur when cpu is powered.
1023 */
1024 smp_call_function_single(drvdata->cpu, etm4_disable_hw, drvdata, 1);
1025
1026 spin_unlock(&drvdata->spinlock);
1027 cpus_read_unlock();
1028
1029 /*
1030 * we only release trace IDs when resetting sysfs.
1031 * This permits sysfs users to read the trace ID after the trace
1032 * session has completed. This maintains operational behaviour with
1033 * prior trace id allocation method
1034 */
1035
1036 dev_dbg(&csdev->dev, "ETM tracing disabled\n");
1037 }
1038
etm4_disable(struct coresight_device * csdev,struct perf_event * event)1039 static void etm4_disable(struct coresight_device *csdev,
1040 struct perf_event *event)
1041 {
1042 enum cs_mode mode;
1043
1044 /*
1045 * For as long as the tracer isn't disabled another entity can't
1046 * change its status. As such we can read the status here without
1047 * fearing it will change under us.
1048 */
1049 mode = coresight_get_mode(csdev);
1050
1051 switch (mode) {
1052 case CS_MODE_DISABLED:
1053 break;
1054 case CS_MODE_SYSFS:
1055 etm4_disable_sysfs(csdev);
1056 break;
1057 case CS_MODE_PERF:
1058 etm4_disable_perf(csdev, event);
1059 break;
1060 }
1061
1062 if (mode)
1063 coresight_set_mode(csdev, CS_MODE_DISABLED);
1064 }
1065
1066 static const struct coresight_ops_source etm4_source_ops = {
1067 .cpu_id = etm4_cpu_id,
1068 .enable = etm4_enable,
1069 .disable = etm4_disable,
1070 };
1071
1072 static const struct coresight_ops etm4_cs_ops = {
1073 .source_ops = &etm4_source_ops,
1074 };
1075
cpu_supports_sysreg_trace(void)1076 static inline bool cpu_supports_sysreg_trace(void)
1077 {
1078 u64 dfr0 = read_sysreg_s(SYS_ID_AA64DFR0_EL1);
1079
1080 return ((dfr0 >> ID_AA64DFR0_EL1_TraceVer_SHIFT) & 0xfUL) > 0;
1081 }
1082
etm4_init_sysreg_access(struct etmv4_drvdata * drvdata,struct csdev_access * csa)1083 static bool etm4_init_sysreg_access(struct etmv4_drvdata *drvdata,
1084 struct csdev_access *csa)
1085 {
1086 u32 devarch;
1087
1088 if (!cpu_supports_sysreg_trace())
1089 return false;
1090
1091 /*
1092 * ETMs implementing sysreg access must implement TRCDEVARCH.
1093 */
1094 devarch = read_etm4x_sysreg_const_offset(TRCDEVARCH);
1095 switch (devarch & ETM_DEVARCH_ID_MASK) {
1096 case ETM_DEVARCH_ETMv4x_ARCH:
1097 *csa = (struct csdev_access) {
1098 .io_mem = false,
1099 .read = etm4x_sysreg_read,
1100 .write = etm4x_sysreg_write,
1101 };
1102 break;
1103 case ETM_DEVARCH_ETE_ARCH:
1104 *csa = (struct csdev_access) {
1105 .io_mem = false,
1106 .read = ete_sysreg_read,
1107 .write = ete_sysreg_write,
1108 };
1109 break;
1110 default:
1111 return false;
1112 }
1113
1114 drvdata->arch = etm_devarch_to_arch(devarch);
1115 return true;
1116 }
1117
is_devtype_cpu_trace(void __iomem * base)1118 static bool is_devtype_cpu_trace(void __iomem *base)
1119 {
1120 u32 devtype = readl(base + TRCDEVTYPE);
1121
1122 return (devtype == CS_DEVTYPE_PE_TRACE);
1123 }
1124
etm4_init_iomem_access(struct etmv4_drvdata * drvdata,struct csdev_access * csa)1125 static bool etm4_init_iomem_access(struct etmv4_drvdata *drvdata,
1126 struct csdev_access *csa)
1127 {
1128 u32 devarch = readl_relaxed(drvdata->base + TRCDEVARCH);
1129
1130 if (!is_coresight_device(drvdata->base) || !is_devtype_cpu_trace(drvdata->base))
1131 return false;
1132
1133 /*
1134 * All ETMs must implement TRCDEVARCH to indicate that
1135 * the component is an ETMv4. Even though TRCIDR1 also
1136 * contains the information, it is part of the "Trace"
1137 * register and must be accessed with the OSLK cleared,
1138 * with MMIO. But we cannot touch the OSLK until we are
1139 * sure this is an ETM. So rely only on the TRCDEVARCH.
1140 */
1141 if ((devarch & ETM_DEVARCH_ID_MASK) != ETM_DEVARCH_ETMv4x_ARCH) {
1142 pr_warn_once("TRCDEVARCH doesn't match ETMv4 architecture\n");
1143 return false;
1144 }
1145
1146 drvdata->arch = etm_devarch_to_arch(devarch);
1147 *csa = CSDEV_ACCESS_IOMEM(drvdata->base);
1148 return true;
1149 }
1150
etm4_init_csdev_access(struct etmv4_drvdata * drvdata,struct csdev_access * csa)1151 static bool etm4_init_csdev_access(struct etmv4_drvdata *drvdata,
1152 struct csdev_access *csa)
1153 {
1154 /*
1155 * Always choose the memory mapped io, if there is
1156 * a memory map to prevent sysreg access on broken
1157 * systems.
1158 */
1159 if (drvdata->base)
1160 return etm4_init_iomem_access(drvdata, csa);
1161
1162 if (etm4_init_sysreg_access(drvdata, csa))
1163 return true;
1164
1165 return false;
1166 }
1167
cpu_detect_trace_filtering(struct etmv4_drvdata * drvdata)1168 static void cpu_detect_trace_filtering(struct etmv4_drvdata *drvdata)
1169 {
1170 u64 dfr0 = read_sysreg(id_aa64dfr0_el1);
1171 u64 trfcr;
1172
1173 drvdata->trfcr = 0;
1174 if (!cpuid_feature_extract_unsigned_field(dfr0, ID_AA64DFR0_EL1_TraceFilt_SHIFT))
1175 return;
1176
1177 /*
1178 * If the CPU supports v8.4 SelfHosted Tracing, enable
1179 * tracing at the kernel EL and EL0, forcing to use the
1180 * virtual time as the timestamp.
1181 */
1182 trfcr = (TRFCR_ELx_TS_VIRTUAL |
1183 TRFCR_ELx_ExTRE |
1184 TRFCR_ELx_E0TRE);
1185
1186 /* If we are running at EL2, allow tracing the CONTEXTIDR_EL2. */
1187 if (is_kernel_in_hyp_mode())
1188 trfcr |= TRFCR_EL2_CX;
1189
1190 drvdata->trfcr = trfcr;
1191 }
1192
1193 /*
1194 * The following errata on applicable cpu ranges, affect the CCITMIN filed
1195 * in TCRIDR3 register. Software read for the field returns 0x100 limiting
1196 * the cycle threshold granularity, whereas the right value should have
1197 * been 0x4, which is well supported in the hardware.
1198 */
1199 static struct midr_range etm_wrong_ccitmin_cpus[] = {
1200 /* Erratum #1490853 - Cortex-A76 */
1201 MIDR_RANGE(MIDR_CORTEX_A76, 0, 0, 4, 0),
1202 /* Erratum #1490853 - Neoverse-N1 */
1203 MIDR_RANGE(MIDR_NEOVERSE_N1, 0, 0, 4, 0),
1204 /* Erratum #1491015 - Cortex-A77 */
1205 MIDR_RANGE(MIDR_CORTEX_A77, 0, 0, 1, 0),
1206 /* Erratum #1502854 - Cortex-X1 */
1207 MIDR_REV(MIDR_CORTEX_X1, 0, 0),
1208 /* Erratum #1619801 - Neoverse-V1 */
1209 MIDR_REV(MIDR_NEOVERSE_V1, 0, 0),
1210 {},
1211 };
1212
etm4_fixup_wrong_ccitmin(struct etmv4_drvdata * drvdata)1213 static void etm4_fixup_wrong_ccitmin(struct etmv4_drvdata *drvdata)
1214 {
1215 /*
1216 * Erratum affected cpus will read 256 as the minimum
1217 * instruction trace cycle counting threshold whereas
1218 * the correct value should be 4 instead. Override the
1219 * recorded value for 'drvdata->ccitmin' to workaround
1220 * this problem.
1221 */
1222 if (is_midr_in_range_list(read_cpuid_id(), etm_wrong_ccitmin_cpus)) {
1223 if (drvdata->ccitmin == 256)
1224 drvdata->ccitmin = 4;
1225 }
1226 }
1227
etm4_init_arch_data(void * info)1228 static void etm4_init_arch_data(void *info)
1229 {
1230 u32 etmidr0;
1231 u32 etmidr2;
1232 u32 etmidr3;
1233 u32 etmidr4;
1234 u32 etmidr5;
1235 struct etm4_init_arg *init_arg = info;
1236 struct etmv4_drvdata *drvdata;
1237 struct csdev_access *csa;
1238 struct device *dev = init_arg->dev;
1239 int i;
1240
1241 drvdata = dev_get_drvdata(init_arg->dev);
1242 csa = init_arg->csa;
1243
1244 /*
1245 * If we are unable to detect the access mechanism,
1246 * or unable to detect the trace unit type, fail
1247 * early.
1248 */
1249 if (!etm4_init_csdev_access(drvdata, csa))
1250 return;
1251
1252 if (!csa->io_mem ||
1253 fwnode_property_present(dev_fwnode(dev), "qcom,skip-power-up"))
1254 drvdata->skip_power_up = true;
1255
1256 /* Detect the support for OS Lock before we actually use it */
1257 etm_detect_os_lock(drvdata, csa);
1258
1259 /* Make sure all registers are accessible */
1260 etm4_os_unlock_csa(drvdata, csa);
1261 etm4_cs_unlock(drvdata, csa);
1262
1263 etm4_check_arch_features(drvdata, csa);
1264
1265 /* find all capabilities of the tracing unit */
1266 etmidr0 = etm4x_relaxed_read32(csa, TRCIDR0);
1267
1268 /* INSTP0, bits[2:1] P0 tracing support field */
1269 drvdata->instrp0 = !!(FIELD_GET(TRCIDR0_INSTP0_MASK, etmidr0) == 0b11);
1270 /* TRCBB, bit[5] Branch broadcast tracing support bit */
1271 drvdata->trcbb = !!(etmidr0 & TRCIDR0_TRCBB);
1272 /* TRCCOND, bit[6] Conditional instruction tracing support bit */
1273 drvdata->trccond = !!(etmidr0 & TRCIDR0_TRCCOND);
1274 /* TRCCCI, bit[7] Cycle counting instruction bit */
1275 drvdata->trccci = !!(etmidr0 & TRCIDR0_TRCCCI);
1276 /* RETSTACK, bit[9] Return stack bit */
1277 drvdata->retstack = !!(etmidr0 & TRCIDR0_RETSTACK);
1278 /* NUMEVENT, bits[11:10] Number of events field */
1279 drvdata->nr_event = FIELD_GET(TRCIDR0_NUMEVENT_MASK, etmidr0);
1280 /* QSUPP, bits[16:15] Q element support field */
1281 drvdata->q_support = FIELD_GET(TRCIDR0_QSUPP_MASK, etmidr0);
1282 if (drvdata->q_support)
1283 drvdata->q_filt = !!(etmidr0 & TRCIDR0_QFILT);
1284 /* TSSIZE, bits[28:24] Global timestamp size field */
1285 drvdata->ts_size = FIELD_GET(TRCIDR0_TSSIZE_MASK, etmidr0);
1286
1287 /* maximum size of resources */
1288 etmidr2 = etm4x_relaxed_read32(csa, TRCIDR2);
1289 /* CIDSIZE, bits[9:5] Indicates the Context ID size */
1290 drvdata->ctxid_size = FIELD_GET(TRCIDR2_CIDSIZE_MASK, etmidr2);
1291 /* VMIDSIZE, bits[14:10] Indicates the VMID size */
1292 drvdata->vmid_size = FIELD_GET(TRCIDR2_VMIDSIZE_MASK, etmidr2);
1293 /* CCSIZE, bits[28:25] size of the cycle counter in bits minus 12 */
1294 drvdata->ccsize = FIELD_GET(TRCIDR2_CCSIZE_MASK, etmidr2);
1295
1296 etmidr3 = etm4x_relaxed_read32(csa, TRCIDR3);
1297 /* CCITMIN, bits[11:0] minimum threshold value that can be programmed */
1298 drvdata->ccitmin = FIELD_GET(TRCIDR3_CCITMIN_MASK, etmidr3);
1299 etm4_fixup_wrong_ccitmin(drvdata);
1300
1301 /* EXLEVEL_S, bits[19:16] Secure state instruction tracing */
1302 drvdata->s_ex_level = FIELD_GET(TRCIDR3_EXLEVEL_S_MASK, etmidr3);
1303 drvdata->config.s_ex_level = drvdata->s_ex_level;
1304 /* EXLEVEL_NS, bits[23:20] Non-secure state instruction tracing */
1305 drvdata->ns_ex_level = FIELD_GET(TRCIDR3_EXLEVEL_NS_MASK, etmidr3);
1306 /*
1307 * TRCERR, bit[24] whether a trace unit can trace a
1308 * system error exception.
1309 */
1310 drvdata->trc_error = !!(etmidr3 & TRCIDR3_TRCERR);
1311 /* SYNCPR, bit[25] implementation has a fixed synchronization period? */
1312 drvdata->syncpr = !!(etmidr3 & TRCIDR3_SYNCPR);
1313 /* STALLCTL, bit[26] is stall control implemented? */
1314 drvdata->stallctl = !!(etmidr3 & TRCIDR3_STALLCTL);
1315 /* SYSSTALL, bit[27] implementation can support stall control? */
1316 drvdata->sysstall = !!(etmidr3 & TRCIDR3_SYSSTALL);
1317 /*
1318 * NUMPROC - the number of PEs available for tracing, 5bits
1319 * = TRCIDR3.bits[13:12]bits[30:28]
1320 * bits[4:3] = TRCIDR3.bits[13:12] (since etm-v4.2, otherwise RES0)
1321 * bits[3:0] = TRCIDR3.bits[30:28]
1322 */
1323 drvdata->nr_pe = (FIELD_GET(TRCIDR3_NUMPROC_HI_MASK, etmidr3) << 3) |
1324 FIELD_GET(TRCIDR3_NUMPROC_LO_MASK, etmidr3);
1325 /* NOOVERFLOW, bit[31] is trace overflow prevention supported */
1326 drvdata->nooverflow = !!(etmidr3 & TRCIDR3_NOOVERFLOW);
1327
1328 /* number of resources trace unit supports */
1329 etmidr4 = etm4x_relaxed_read32(csa, TRCIDR4);
1330 /* NUMACPAIRS, bits[0:3] number of addr comparator pairs for tracing */
1331 drvdata->nr_addr_cmp = FIELD_GET(TRCIDR4_NUMACPAIRS_MASK, etmidr4);
1332 /* NUMPC, bits[15:12] number of PE comparator inputs for tracing */
1333 drvdata->nr_pe_cmp = FIELD_GET(TRCIDR4_NUMPC_MASK, etmidr4);
1334 /*
1335 * NUMRSPAIR, bits[19:16]
1336 * The number of resource pairs conveyed by the HW starts at 0, i.e a
1337 * value of 0x0 indicate 1 resource pair, 0x1 indicate two and so on.
1338 * As such add 1 to the value of NUMRSPAIR for a better representation.
1339 *
1340 * For ETM v4.3 and later, 0x0 means 0, and no pairs are available -
1341 * the default TRUE and FALSE resource selectors are omitted.
1342 * Otherwise for values 0x1 and above the number is N + 1 as per v4.2.
1343 */
1344 drvdata->nr_resource = FIELD_GET(TRCIDR4_NUMRSPAIR_MASK, etmidr4);
1345 if ((drvdata->arch < ETM_ARCH_V4_3) || (drvdata->nr_resource > 0))
1346 drvdata->nr_resource += 1;
1347 /*
1348 * NUMSSCC, bits[23:20] the number of single-shot
1349 * comparator control for tracing. Read any status regs as these
1350 * also contain RO capability data.
1351 */
1352 drvdata->nr_ss_cmp = FIELD_GET(TRCIDR4_NUMSSCC_MASK, etmidr4);
1353 for (i = 0; i < drvdata->nr_ss_cmp; i++) {
1354 drvdata->config.ss_status[i] =
1355 etm4x_relaxed_read32(csa, TRCSSCSRn(i));
1356 }
1357 /* NUMCIDC, bits[27:24] number of Context ID comparators for tracing */
1358 drvdata->numcidc = FIELD_GET(TRCIDR4_NUMCIDC_MASK, etmidr4);
1359 /* NUMVMIDC, bits[31:28] number of VMID comparators for tracing */
1360 drvdata->numvmidc = FIELD_GET(TRCIDR4_NUMVMIDC_MASK, etmidr4);
1361
1362 etmidr5 = etm4x_relaxed_read32(csa, TRCIDR5);
1363 /* NUMEXTIN, bits[8:0] number of external inputs implemented */
1364 drvdata->nr_ext_inp = FIELD_GET(TRCIDR5_NUMEXTIN_MASK, etmidr5);
1365 /* TRACEIDSIZE, bits[21:16] indicates the trace ID width */
1366 drvdata->trcid_size = FIELD_GET(TRCIDR5_TRACEIDSIZE_MASK, etmidr5);
1367 /* ATBTRIG, bit[22] implementation can support ATB triggers? */
1368 drvdata->atbtrig = !!(etmidr5 & TRCIDR5_ATBTRIG);
1369 /*
1370 * LPOVERRIDE, bit[23] implementation supports
1371 * low-power state override
1372 */
1373 drvdata->lpoverride = (etmidr5 & TRCIDR5_LPOVERRIDE) && (!drvdata->skip_power_up);
1374 /* NUMSEQSTATE, bits[27:25] number of sequencer states implemented */
1375 drvdata->nrseqstate = FIELD_GET(TRCIDR5_NUMSEQSTATE_MASK, etmidr5);
1376 /* NUMCNTR, bits[30:28] number of counters available for tracing */
1377 drvdata->nr_cntr = FIELD_GET(TRCIDR5_NUMCNTR_MASK, etmidr5);
1378 etm4_cs_lock(drvdata, csa);
1379 cpu_detect_trace_filtering(drvdata);
1380 }
1381
etm4_get_victlr_access_type(struct etmv4_config * config)1382 static inline u32 etm4_get_victlr_access_type(struct etmv4_config *config)
1383 {
1384 return etm4_get_access_type(config) << __bf_shf(TRCVICTLR_EXLEVEL_MASK);
1385 }
1386
1387 /* Set ELx trace filter access in the TRCVICTLR register */
etm4_set_victlr_access(struct etmv4_config * config)1388 static void etm4_set_victlr_access(struct etmv4_config *config)
1389 {
1390 config->vinst_ctrl &= ~TRCVICTLR_EXLEVEL_MASK;
1391 config->vinst_ctrl |= etm4_get_victlr_access_type(config);
1392 }
1393
etm4_set_default_config(struct etmv4_config * config)1394 static void etm4_set_default_config(struct etmv4_config *config)
1395 {
1396 /* disable all events tracing */
1397 config->eventctrl0 = 0x0;
1398 config->eventctrl1 = 0x0;
1399
1400 /* disable stalling */
1401 config->stall_ctrl = 0x0;
1402
1403 /* enable trace synchronization every 4096 bytes, if available */
1404 config->syncfreq = 0xC;
1405
1406 /* disable timestamp event */
1407 config->ts_ctrl = 0x0;
1408
1409 /* TRCVICTLR::EVENT = 0x01, select the always on logic */
1410 config->vinst_ctrl = FIELD_PREP(TRCVICTLR_EVENT_MASK, 0x01);
1411
1412 /* TRCVICTLR::EXLEVEL_NS:EXLEVELS: Set kernel / user filtering */
1413 etm4_set_victlr_access(config);
1414 }
1415
etm4_get_ns_access_type(struct etmv4_config * config)1416 static u64 etm4_get_ns_access_type(struct etmv4_config *config)
1417 {
1418 u64 access_type = 0;
1419
1420 /*
1421 * EXLEVEL_NS, for NonSecure Exception levels.
1422 * The mask here is a generic value and must be
1423 * shifted to the corresponding field for the registers
1424 */
1425 if (!is_kernel_in_hyp_mode()) {
1426 /* Stay away from hypervisor mode for non-VHE */
1427 access_type = ETM_EXLEVEL_NS_HYP;
1428 if (config->mode & ETM_MODE_EXCL_KERN)
1429 access_type |= ETM_EXLEVEL_NS_OS;
1430 } else if (config->mode & ETM_MODE_EXCL_KERN) {
1431 access_type = ETM_EXLEVEL_NS_HYP;
1432 }
1433
1434 if (config->mode & ETM_MODE_EXCL_USER)
1435 access_type |= ETM_EXLEVEL_NS_APP;
1436
1437 return access_type;
1438 }
1439
1440 /*
1441 * Construct the exception level masks for a given config.
1442 * This must be shifted to the corresponding register field
1443 * for usage.
1444 */
etm4_get_access_type(struct etmv4_config * config)1445 static u64 etm4_get_access_type(struct etmv4_config *config)
1446 {
1447 /* All Secure exception levels are excluded from the trace */
1448 return etm4_get_ns_access_type(config) | (u64)config->s_ex_level;
1449 }
1450
etm4_get_comparator_access_type(struct etmv4_config * config)1451 static u64 etm4_get_comparator_access_type(struct etmv4_config *config)
1452 {
1453 return etm4_get_access_type(config) << TRCACATR_EXLEVEL_SHIFT;
1454 }
1455
etm4_set_comparator_filter(struct etmv4_config * config,u64 start,u64 stop,int comparator)1456 static void etm4_set_comparator_filter(struct etmv4_config *config,
1457 u64 start, u64 stop, int comparator)
1458 {
1459 u64 access_type = etm4_get_comparator_access_type(config);
1460
1461 /* First half of default address comparator */
1462 config->addr_val[comparator] = start;
1463 config->addr_acc[comparator] = access_type;
1464 config->addr_type[comparator] = ETM_ADDR_TYPE_RANGE;
1465
1466 /* Second half of default address comparator */
1467 config->addr_val[comparator + 1] = stop;
1468 config->addr_acc[comparator + 1] = access_type;
1469 config->addr_type[comparator + 1] = ETM_ADDR_TYPE_RANGE;
1470
1471 /*
1472 * Configure the ViewInst function to include this address range
1473 * comparator.
1474 *
1475 * @comparator is divided by two since it is the index in the
1476 * etmv4_config::addr_val array but register TRCVIIECTLR deals with
1477 * address range comparator _pairs_.
1478 *
1479 * Therefore:
1480 * index 0 -> compatator pair 0
1481 * index 2 -> comparator pair 1
1482 * index 4 -> comparator pair 2
1483 * ...
1484 * index 14 -> comparator pair 7
1485 */
1486 config->viiectlr |= BIT(comparator / 2);
1487 }
1488
etm4_set_start_stop_filter(struct etmv4_config * config,u64 address,int comparator,enum etm_addr_type type)1489 static void etm4_set_start_stop_filter(struct etmv4_config *config,
1490 u64 address, int comparator,
1491 enum etm_addr_type type)
1492 {
1493 int shift;
1494 u64 access_type = etm4_get_comparator_access_type(config);
1495
1496 /* Configure the comparator */
1497 config->addr_val[comparator] = address;
1498 config->addr_acc[comparator] = access_type;
1499 config->addr_type[comparator] = type;
1500
1501 /*
1502 * Configure ViewInst Start-Stop control register.
1503 * Addresses configured to start tracing go from bit 0 to n-1,
1504 * while those configured to stop tracing from 16 to 16 + n-1.
1505 */
1506 shift = (type == ETM_ADDR_TYPE_START ? 0 : 16);
1507 config->vissctlr |= BIT(shift + comparator);
1508 }
1509
etm4_set_default_filter(struct etmv4_config * config)1510 static void etm4_set_default_filter(struct etmv4_config *config)
1511 {
1512 /* Trace everything 'default' filter achieved by no filtering */
1513 config->viiectlr = 0x0;
1514
1515 /*
1516 * TRCVICTLR::SSSTATUS == 1, the start-stop logic is
1517 * in the started state
1518 */
1519 config->vinst_ctrl |= TRCVICTLR_SSSTATUS;
1520 config->mode |= ETM_MODE_VIEWINST_STARTSTOP;
1521
1522 /* No start-stop filtering for ViewInst */
1523 config->vissctlr = 0x0;
1524 }
1525
etm4_set_default(struct etmv4_config * config)1526 static void etm4_set_default(struct etmv4_config *config)
1527 {
1528 if (WARN_ON_ONCE(!config))
1529 return;
1530
1531 /*
1532 * Make default initialisation trace everything
1533 *
1534 * This is done by a minimum default config sufficient to enable
1535 * full instruction trace - with a default filter for trace all
1536 * achieved by having no filtering.
1537 */
1538 etm4_set_default_config(config);
1539 etm4_set_default_filter(config);
1540 }
1541
etm4_get_next_comparator(struct etmv4_drvdata * drvdata,u32 type)1542 static int etm4_get_next_comparator(struct etmv4_drvdata *drvdata, u32 type)
1543 {
1544 int nr_comparator, index = 0;
1545 struct etmv4_config *config = &drvdata->config;
1546
1547 /*
1548 * nr_addr_cmp holds the number of comparator _pair_, so time 2
1549 * for the total number of comparators.
1550 */
1551 nr_comparator = drvdata->nr_addr_cmp * 2;
1552
1553 /* Go through the tally of comparators looking for a free one. */
1554 while (index < nr_comparator) {
1555 switch (type) {
1556 case ETM_ADDR_TYPE_RANGE:
1557 if (config->addr_type[index] == ETM_ADDR_TYPE_NONE &&
1558 config->addr_type[index + 1] == ETM_ADDR_TYPE_NONE)
1559 return index;
1560
1561 /* Address range comparators go in pairs */
1562 index += 2;
1563 break;
1564 case ETM_ADDR_TYPE_START:
1565 case ETM_ADDR_TYPE_STOP:
1566 if (config->addr_type[index] == ETM_ADDR_TYPE_NONE)
1567 return index;
1568
1569 /* Start/stop address can have odd indexes */
1570 index += 1;
1571 break;
1572 default:
1573 return -EINVAL;
1574 }
1575 }
1576
1577 /* If we are here all the comparators have been used. */
1578 return -ENOSPC;
1579 }
1580
etm4_set_event_filters(struct etmv4_drvdata * drvdata,struct perf_event * event)1581 static int etm4_set_event_filters(struct etmv4_drvdata *drvdata,
1582 struct perf_event *event)
1583 {
1584 int i, comparator, ret = 0;
1585 u64 address;
1586 struct etmv4_config *config = &drvdata->config;
1587 struct etm_filters *filters = event->hw.addr_filters;
1588
1589 if (!filters)
1590 goto default_filter;
1591
1592 /* Sync events with what Perf got */
1593 perf_event_addr_filters_sync(event);
1594
1595 /*
1596 * If there are no filters to deal with simply go ahead with
1597 * the default filter, i.e the entire address range.
1598 */
1599 if (!filters->nr_filters)
1600 goto default_filter;
1601
1602 for (i = 0; i < filters->nr_filters; i++) {
1603 struct etm_filter *filter = &filters->etm_filter[i];
1604 enum etm_addr_type type = filter->type;
1605
1606 /* See if a comparator is free. */
1607 comparator = etm4_get_next_comparator(drvdata, type);
1608 if (comparator < 0) {
1609 ret = comparator;
1610 goto out;
1611 }
1612
1613 switch (type) {
1614 case ETM_ADDR_TYPE_RANGE:
1615 etm4_set_comparator_filter(config,
1616 filter->start_addr,
1617 filter->stop_addr,
1618 comparator);
1619 /*
1620 * TRCVICTLR::SSSTATUS == 1, the start-stop logic is
1621 * in the started state
1622 */
1623 config->vinst_ctrl |= TRCVICTLR_SSSTATUS;
1624
1625 /* No start-stop filtering for ViewInst */
1626 config->vissctlr = 0x0;
1627 break;
1628 case ETM_ADDR_TYPE_START:
1629 case ETM_ADDR_TYPE_STOP:
1630 /* Get the right start or stop address */
1631 address = (type == ETM_ADDR_TYPE_START ?
1632 filter->start_addr :
1633 filter->stop_addr);
1634
1635 /* Configure comparator */
1636 etm4_set_start_stop_filter(config, address,
1637 comparator, type);
1638
1639 /*
1640 * If filters::ssstatus == 1, trace acquisition was
1641 * started but the process was yanked away before the
1642 * stop address was hit. As such the start/stop
1643 * logic needs to be re-started so that tracing can
1644 * resume where it left.
1645 *
1646 * The start/stop logic status when a process is
1647 * scheduled out is checked in function
1648 * etm4_disable_perf().
1649 */
1650 if (filters->ssstatus)
1651 config->vinst_ctrl |= TRCVICTLR_SSSTATUS;
1652
1653 /* No include/exclude filtering for ViewInst */
1654 config->viiectlr = 0x0;
1655 break;
1656 default:
1657 ret = -EINVAL;
1658 goto out;
1659 }
1660 }
1661
1662 goto out;
1663
1664
1665 default_filter:
1666 etm4_set_default_filter(config);
1667
1668 out:
1669 return ret;
1670 }
1671
etm4_config_trace_mode(struct etmv4_config * config)1672 void etm4_config_trace_mode(struct etmv4_config *config)
1673 {
1674 u32 mode;
1675
1676 mode = config->mode;
1677 mode &= (ETM_MODE_EXCL_KERN | ETM_MODE_EXCL_USER);
1678
1679 /* excluding kernel AND user space doesn't make sense */
1680 WARN_ON_ONCE(mode == (ETM_MODE_EXCL_KERN | ETM_MODE_EXCL_USER));
1681
1682 /* nothing to do if neither flags are set */
1683 if (!(mode & ETM_MODE_EXCL_KERN) && !(mode & ETM_MODE_EXCL_USER))
1684 return;
1685
1686 etm4_set_victlr_access(config);
1687 }
1688
etm4_online_cpu(unsigned int cpu)1689 static int etm4_online_cpu(unsigned int cpu)
1690 {
1691 if (!etmdrvdata[cpu])
1692 return etm4_probe_cpu(cpu);
1693
1694 if (etmdrvdata[cpu]->boot_enable && !etmdrvdata[cpu]->sticky_enable)
1695 coresight_enable_sysfs(etmdrvdata[cpu]->csdev);
1696 return 0;
1697 }
1698
etm4_starting_cpu(unsigned int cpu)1699 static int etm4_starting_cpu(unsigned int cpu)
1700 {
1701 if (!etmdrvdata[cpu])
1702 return 0;
1703
1704 spin_lock(&etmdrvdata[cpu]->spinlock);
1705 if (!etmdrvdata[cpu]->os_unlock)
1706 etm4_os_unlock(etmdrvdata[cpu]);
1707
1708 if (coresight_get_mode(etmdrvdata[cpu]->csdev))
1709 etm4_enable_hw(etmdrvdata[cpu]);
1710 spin_unlock(&etmdrvdata[cpu]->spinlock);
1711 return 0;
1712 }
1713
etm4_dying_cpu(unsigned int cpu)1714 static int etm4_dying_cpu(unsigned int cpu)
1715 {
1716 if (!etmdrvdata[cpu])
1717 return 0;
1718
1719 spin_lock(&etmdrvdata[cpu]->spinlock);
1720 if (coresight_get_mode(etmdrvdata[cpu]->csdev))
1721 etm4_disable_hw(etmdrvdata[cpu]);
1722 spin_unlock(&etmdrvdata[cpu]->spinlock);
1723 return 0;
1724 }
1725
__etm4_cpu_save(struct etmv4_drvdata * drvdata)1726 static int __etm4_cpu_save(struct etmv4_drvdata *drvdata)
1727 {
1728 int i, ret = 0;
1729 struct etmv4_save_state *state;
1730 struct coresight_device *csdev = drvdata->csdev;
1731 struct csdev_access *csa;
1732 struct device *etm_dev;
1733
1734 if (WARN_ON(!csdev))
1735 return -ENODEV;
1736
1737 etm_dev = &csdev->dev;
1738 csa = &csdev->access;
1739
1740 /*
1741 * As recommended by 3.4.1 ("The procedure when powering down the PE")
1742 * of ARM IHI 0064D
1743 */
1744 dsb(sy);
1745 isb();
1746
1747 etm4_cs_unlock(drvdata, csa);
1748 /* Lock the OS lock to disable trace and external debugger access */
1749 etm4_os_lock(drvdata);
1750
1751 /* wait for TRCSTATR.PMSTABLE to go up */
1752 if (etm4x_wait_status(csa, TRCSTATR_PMSTABLE_BIT, 1)) {
1753 dev_err(etm_dev,
1754 "timeout while waiting for PM Stable Status\n");
1755 etm4_os_unlock(drvdata);
1756 ret = -EBUSY;
1757 goto out;
1758 }
1759
1760 state = drvdata->save_state;
1761
1762 state->trcprgctlr = etm4x_read32(csa, TRCPRGCTLR);
1763 if (drvdata->nr_pe)
1764 state->trcprocselr = etm4x_read32(csa, TRCPROCSELR);
1765 state->trcconfigr = etm4x_read32(csa, TRCCONFIGR);
1766 state->trcauxctlr = etm4x_read32(csa, TRCAUXCTLR);
1767 state->trceventctl0r = etm4x_read32(csa, TRCEVENTCTL0R);
1768 state->trceventctl1r = etm4x_read32(csa, TRCEVENTCTL1R);
1769 if (drvdata->stallctl)
1770 state->trcstallctlr = etm4x_read32(csa, TRCSTALLCTLR);
1771 state->trctsctlr = etm4x_read32(csa, TRCTSCTLR);
1772 state->trcsyncpr = etm4x_read32(csa, TRCSYNCPR);
1773 state->trcccctlr = etm4x_read32(csa, TRCCCCTLR);
1774 state->trcbbctlr = etm4x_read32(csa, TRCBBCTLR);
1775 state->trctraceidr = etm4x_read32(csa, TRCTRACEIDR);
1776 if (drvdata->q_filt)
1777 state->trcqctlr = etm4x_read32(csa, TRCQCTLR);
1778
1779 state->trcvictlr = etm4x_read32(csa, TRCVICTLR);
1780 state->trcviiectlr = etm4x_read32(csa, TRCVIIECTLR);
1781 state->trcvissctlr = etm4x_read32(csa, TRCVISSCTLR);
1782 if (drvdata->nr_pe_cmp)
1783 state->trcvipcssctlr = etm4x_read32(csa, TRCVIPCSSCTLR);
1784
1785 for (i = 0; i < drvdata->nrseqstate - 1; i++)
1786 state->trcseqevr[i] = etm4x_read32(csa, TRCSEQEVRn(i));
1787
1788 if (drvdata->nrseqstate) {
1789 state->trcseqrstevr = etm4x_read32(csa, TRCSEQRSTEVR);
1790 state->trcseqstr = etm4x_read32(csa, TRCSEQSTR);
1791 }
1792 state->trcextinselr = etm4x_read32(csa, TRCEXTINSELR);
1793
1794 for (i = 0; i < drvdata->nr_cntr; i++) {
1795 state->trccntrldvr[i] = etm4x_read32(csa, TRCCNTRLDVRn(i));
1796 state->trccntctlr[i] = etm4x_read32(csa, TRCCNTCTLRn(i));
1797 state->trccntvr[i] = etm4x_read32(csa, TRCCNTVRn(i));
1798 }
1799
1800 /* Resource selector pair 0 is reserved */
1801 for (i = 2; i < drvdata->nr_resource * 2; i++)
1802 state->trcrsctlr[i] = etm4x_read32(csa, TRCRSCTLRn(i));
1803
1804 for (i = 0; i < drvdata->nr_ss_cmp; i++) {
1805 state->trcssccr[i] = etm4x_read32(csa, TRCSSCCRn(i));
1806 state->trcsscsr[i] = etm4x_read32(csa, TRCSSCSRn(i));
1807 if (etm4x_sspcicrn_present(drvdata, i))
1808 state->trcsspcicr[i] = etm4x_read32(csa, TRCSSPCICRn(i));
1809 }
1810
1811 for (i = 0; i < drvdata->nr_addr_cmp * 2; i++) {
1812 state->trcacvr[i] = etm4x_read64(csa, TRCACVRn(i));
1813 state->trcacatr[i] = etm4x_read64(csa, TRCACATRn(i));
1814 }
1815
1816 /*
1817 * Data trace stream is architecturally prohibited for A profile cores
1818 * so we don't save (or later restore) trcdvcvr and trcdvcmr - As per
1819 * section 1.3.4 ("Possible functional configurations of an ETMv4 trace
1820 * unit") of ARM IHI 0064D.
1821 */
1822
1823 for (i = 0; i < drvdata->numcidc; i++)
1824 state->trccidcvr[i] = etm4x_read64(csa, TRCCIDCVRn(i));
1825
1826 for (i = 0; i < drvdata->numvmidc; i++)
1827 state->trcvmidcvr[i] = etm4x_read64(csa, TRCVMIDCVRn(i));
1828
1829 state->trccidcctlr0 = etm4x_read32(csa, TRCCIDCCTLR0);
1830 if (drvdata->numcidc > 4)
1831 state->trccidcctlr1 = etm4x_read32(csa, TRCCIDCCTLR1);
1832
1833 state->trcvmidcctlr0 = etm4x_read32(csa, TRCVMIDCCTLR0);
1834 if (drvdata->numvmidc > 4)
1835 state->trcvmidcctlr0 = etm4x_read32(csa, TRCVMIDCCTLR1);
1836
1837 state->trcclaimset = etm4x_read32(csa, TRCCLAIMCLR);
1838
1839 if (!drvdata->skip_power_up)
1840 state->trcpdcr = etm4x_read32(csa, TRCPDCR);
1841
1842 /* wait for TRCSTATR.IDLE to go up */
1843 if (etm4x_wait_status(csa, TRCSTATR_PMSTABLE_BIT, 1)) {
1844 dev_err(etm_dev,
1845 "timeout while waiting for Idle Trace Status\n");
1846 etm4_os_unlock(drvdata);
1847 ret = -EBUSY;
1848 goto out;
1849 }
1850
1851 drvdata->state_needs_restore = true;
1852
1853 /*
1854 * Power can be removed from the trace unit now. We do this to
1855 * potentially save power on systems that respect the TRCPDCR_PU
1856 * despite requesting software to save/restore state.
1857 */
1858 if (!drvdata->skip_power_up)
1859 etm4x_relaxed_write32(csa, (state->trcpdcr & ~TRCPDCR_PU),
1860 TRCPDCR);
1861 out:
1862 etm4_cs_lock(drvdata, csa);
1863 return ret;
1864 }
1865
etm4_cpu_save(struct etmv4_drvdata * drvdata)1866 static int etm4_cpu_save(struct etmv4_drvdata *drvdata)
1867 {
1868 int ret = 0;
1869
1870 /* Save the TRFCR irrespective of whether the ETM is ON */
1871 if (drvdata->trfcr)
1872 drvdata->save_trfcr = read_trfcr();
1873 /*
1874 * Save and restore the ETM Trace registers only if
1875 * the ETM is active.
1876 */
1877 if (coresight_get_mode(drvdata->csdev) && drvdata->save_state)
1878 ret = __etm4_cpu_save(drvdata);
1879 return ret;
1880 }
1881
__etm4_cpu_restore(struct etmv4_drvdata * drvdata)1882 static void __etm4_cpu_restore(struct etmv4_drvdata *drvdata)
1883 {
1884 int i;
1885 struct etmv4_save_state *state = drvdata->save_state;
1886 struct csdev_access *csa = &drvdata->csdev->access;
1887
1888 if (WARN_ON(!drvdata->csdev))
1889 return;
1890
1891 etm4_cs_unlock(drvdata, csa);
1892 etm4x_relaxed_write32(csa, state->trcclaimset, TRCCLAIMSET);
1893
1894 etm4x_relaxed_write32(csa, state->trcprgctlr, TRCPRGCTLR);
1895 if (drvdata->nr_pe)
1896 etm4x_relaxed_write32(csa, state->trcprocselr, TRCPROCSELR);
1897 etm4x_relaxed_write32(csa, state->trcconfigr, TRCCONFIGR);
1898 etm4x_relaxed_write32(csa, state->trcauxctlr, TRCAUXCTLR);
1899 etm4x_relaxed_write32(csa, state->trceventctl0r, TRCEVENTCTL0R);
1900 etm4x_relaxed_write32(csa, state->trceventctl1r, TRCEVENTCTL1R);
1901 if (drvdata->stallctl)
1902 etm4x_relaxed_write32(csa, state->trcstallctlr, TRCSTALLCTLR);
1903 etm4x_relaxed_write32(csa, state->trctsctlr, TRCTSCTLR);
1904 etm4x_relaxed_write32(csa, state->trcsyncpr, TRCSYNCPR);
1905 etm4x_relaxed_write32(csa, state->trcccctlr, TRCCCCTLR);
1906 etm4x_relaxed_write32(csa, state->trcbbctlr, TRCBBCTLR);
1907 etm4x_relaxed_write32(csa, state->trctraceidr, TRCTRACEIDR);
1908 if (drvdata->q_filt)
1909 etm4x_relaxed_write32(csa, state->trcqctlr, TRCQCTLR);
1910
1911 etm4x_relaxed_write32(csa, state->trcvictlr, TRCVICTLR);
1912 etm4x_relaxed_write32(csa, state->trcviiectlr, TRCVIIECTLR);
1913 etm4x_relaxed_write32(csa, state->trcvissctlr, TRCVISSCTLR);
1914 if (drvdata->nr_pe_cmp)
1915 etm4x_relaxed_write32(csa, state->trcvipcssctlr, TRCVIPCSSCTLR);
1916
1917 for (i = 0; i < drvdata->nrseqstate - 1; i++)
1918 etm4x_relaxed_write32(csa, state->trcseqevr[i], TRCSEQEVRn(i));
1919
1920 if (drvdata->nrseqstate) {
1921 etm4x_relaxed_write32(csa, state->trcseqrstevr, TRCSEQRSTEVR);
1922 etm4x_relaxed_write32(csa, state->trcseqstr, TRCSEQSTR);
1923 }
1924 etm4x_relaxed_write32(csa, state->trcextinselr, TRCEXTINSELR);
1925
1926 for (i = 0; i < drvdata->nr_cntr; i++) {
1927 etm4x_relaxed_write32(csa, state->trccntrldvr[i], TRCCNTRLDVRn(i));
1928 etm4x_relaxed_write32(csa, state->trccntctlr[i], TRCCNTCTLRn(i));
1929 etm4x_relaxed_write32(csa, state->trccntvr[i], TRCCNTVRn(i));
1930 }
1931
1932 /* Resource selector pair 0 is reserved */
1933 for (i = 2; i < drvdata->nr_resource * 2; i++)
1934 etm4x_relaxed_write32(csa, state->trcrsctlr[i], TRCRSCTLRn(i));
1935
1936 for (i = 0; i < drvdata->nr_ss_cmp; i++) {
1937 etm4x_relaxed_write32(csa, state->trcssccr[i], TRCSSCCRn(i));
1938 etm4x_relaxed_write32(csa, state->trcsscsr[i], TRCSSCSRn(i));
1939 if (etm4x_sspcicrn_present(drvdata, i))
1940 etm4x_relaxed_write32(csa, state->trcsspcicr[i], TRCSSPCICRn(i));
1941 }
1942
1943 for (i = 0; i < drvdata->nr_addr_cmp * 2; i++) {
1944 etm4x_relaxed_write64(csa, state->trcacvr[i], TRCACVRn(i));
1945 etm4x_relaxed_write64(csa, state->trcacatr[i], TRCACATRn(i));
1946 }
1947
1948 for (i = 0; i < drvdata->numcidc; i++)
1949 etm4x_relaxed_write64(csa, state->trccidcvr[i], TRCCIDCVRn(i));
1950
1951 for (i = 0; i < drvdata->numvmidc; i++)
1952 etm4x_relaxed_write64(csa, state->trcvmidcvr[i], TRCVMIDCVRn(i));
1953
1954 etm4x_relaxed_write32(csa, state->trccidcctlr0, TRCCIDCCTLR0);
1955 if (drvdata->numcidc > 4)
1956 etm4x_relaxed_write32(csa, state->trccidcctlr1, TRCCIDCCTLR1);
1957
1958 etm4x_relaxed_write32(csa, state->trcvmidcctlr0, TRCVMIDCCTLR0);
1959 if (drvdata->numvmidc > 4)
1960 etm4x_relaxed_write32(csa, state->trcvmidcctlr0, TRCVMIDCCTLR1);
1961
1962 etm4x_relaxed_write32(csa, state->trcclaimset, TRCCLAIMSET);
1963
1964 if (!drvdata->skip_power_up)
1965 etm4x_relaxed_write32(csa, state->trcpdcr, TRCPDCR);
1966
1967 drvdata->state_needs_restore = false;
1968
1969 /*
1970 * As recommended by section 4.3.7 ("Synchronization when using the
1971 * memory-mapped interface") of ARM IHI 0064D
1972 */
1973 dsb(sy);
1974 isb();
1975
1976 /* Unlock the OS lock to re-enable trace and external debug access */
1977 etm4_os_unlock(drvdata);
1978 etm4_cs_lock(drvdata, csa);
1979 }
1980
etm4_cpu_restore(struct etmv4_drvdata * drvdata)1981 static void etm4_cpu_restore(struct etmv4_drvdata *drvdata)
1982 {
1983 if (drvdata->trfcr)
1984 write_trfcr(drvdata->save_trfcr);
1985 if (drvdata->state_needs_restore)
1986 __etm4_cpu_restore(drvdata);
1987 }
1988
etm4_cpu_pm_notify(struct notifier_block * nb,unsigned long cmd,void * v)1989 static int etm4_cpu_pm_notify(struct notifier_block *nb, unsigned long cmd,
1990 void *v)
1991 {
1992 struct etmv4_drvdata *drvdata;
1993 unsigned int cpu = smp_processor_id();
1994
1995 if (!etmdrvdata[cpu])
1996 return NOTIFY_OK;
1997
1998 drvdata = etmdrvdata[cpu];
1999
2000 if (WARN_ON_ONCE(drvdata->cpu != cpu))
2001 return NOTIFY_BAD;
2002
2003 switch (cmd) {
2004 case CPU_PM_ENTER:
2005 if (etm4_cpu_save(drvdata))
2006 return NOTIFY_BAD;
2007 break;
2008 case CPU_PM_EXIT:
2009 case CPU_PM_ENTER_FAILED:
2010 etm4_cpu_restore(drvdata);
2011 break;
2012 default:
2013 return NOTIFY_DONE;
2014 }
2015
2016 return NOTIFY_OK;
2017 }
2018
2019 static struct notifier_block etm4_cpu_pm_nb = {
2020 .notifier_call = etm4_cpu_pm_notify,
2021 };
2022
2023 /* Setup PM. Deals with error conditions and counts */
etm4_pm_setup(void)2024 static int __init etm4_pm_setup(void)
2025 {
2026 int ret;
2027
2028 ret = cpu_pm_register_notifier(&etm4_cpu_pm_nb);
2029 if (ret)
2030 return ret;
2031
2032 ret = cpuhp_setup_state_nocalls(CPUHP_AP_ARM_CORESIGHT_STARTING,
2033 "arm/coresight4:starting",
2034 etm4_starting_cpu, etm4_dying_cpu);
2035
2036 if (ret)
2037 goto unregister_notifier;
2038
2039 ret = cpuhp_setup_state_nocalls(CPUHP_AP_ONLINE_DYN,
2040 "arm/coresight4:online",
2041 etm4_online_cpu, NULL);
2042
2043 /* HP dyn state ID returned in ret on success */
2044 if (ret > 0) {
2045 hp_online = ret;
2046 return 0;
2047 }
2048
2049 /* failed dyn state - remove others */
2050 cpuhp_remove_state_nocalls(CPUHP_AP_ARM_CORESIGHT_STARTING);
2051
2052 unregister_notifier:
2053 cpu_pm_unregister_notifier(&etm4_cpu_pm_nb);
2054 return ret;
2055 }
2056
etm4_pm_clear(void)2057 static void etm4_pm_clear(void)
2058 {
2059 cpu_pm_unregister_notifier(&etm4_cpu_pm_nb);
2060 cpuhp_remove_state_nocalls(CPUHP_AP_ARM_CORESIGHT_STARTING);
2061 if (hp_online) {
2062 cpuhp_remove_state_nocalls(hp_online);
2063 hp_online = 0;
2064 }
2065 }
2066
etm4_add_coresight_dev(struct etm4_init_arg * init_arg)2067 static int etm4_add_coresight_dev(struct etm4_init_arg *init_arg)
2068 {
2069 int ret;
2070 struct coresight_platform_data *pdata = NULL;
2071 struct device *dev = init_arg->dev;
2072 struct etmv4_drvdata *drvdata = dev_get_drvdata(dev);
2073 struct coresight_desc desc = { 0 };
2074 u8 major, minor;
2075 char *type_name;
2076
2077 if (!drvdata)
2078 return -EINVAL;
2079
2080 desc.access = *init_arg->csa;
2081
2082 if (!drvdata->arch)
2083 return -EINVAL;
2084
2085 major = ETM_ARCH_MAJOR_VERSION(drvdata->arch);
2086 minor = ETM_ARCH_MINOR_VERSION(drvdata->arch);
2087
2088 if (etm4x_is_ete(drvdata)) {
2089 type_name = "ete";
2090 /* ETE v1 has major version == 0b101. Adjust this for logging.*/
2091 major -= 4;
2092 } else {
2093 type_name = "etm";
2094 }
2095
2096 desc.name = devm_kasprintf(dev, GFP_KERNEL,
2097 "%s%d", type_name, drvdata->cpu);
2098 if (!desc.name)
2099 return -ENOMEM;
2100
2101 etm4_set_default(&drvdata->config);
2102
2103 pdata = coresight_get_platform_data(dev);
2104 if (IS_ERR(pdata))
2105 return PTR_ERR(pdata);
2106
2107 dev->platform_data = pdata;
2108
2109 desc.type = CORESIGHT_DEV_TYPE_SOURCE;
2110 desc.subtype.source_subtype = CORESIGHT_DEV_SUBTYPE_SOURCE_PROC;
2111 desc.ops = &etm4_cs_ops;
2112 desc.pdata = pdata;
2113 desc.dev = dev;
2114 desc.groups = coresight_etmv4_groups;
2115 drvdata->csdev = coresight_register(&desc);
2116 if (IS_ERR(drvdata->csdev))
2117 return PTR_ERR(drvdata->csdev);
2118
2119 ret = etm_perf_symlink(drvdata->csdev, true);
2120 if (ret) {
2121 coresight_unregister(drvdata->csdev);
2122 return ret;
2123 }
2124
2125 /* register with config infrastructure & load any current features */
2126 ret = etm4_cscfg_register(drvdata->csdev);
2127 if (ret) {
2128 coresight_unregister(drvdata->csdev);
2129 return ret;
2130 }
2131
2132 etmdrvdata[drvdata->cpu] = drvdata;
2133
2134 dev_info(&drvdata->csdev->dev, "CPU%d: %s v%d.%d initialized\n",
2135 drvdata->cpu, type_name, major, minor);
2136
2137 if (boot_enable) {
2138 coresight_enable_sysfs(drvdata->csdev);
2139 drvdata->boot_enable = true;
2140 }
2141
2142 return 0;
2143 }
2144
etm4_probe(struct device * dev)2145 static int etm4_probe(struct device *dev)
2146 {
2147 struct etmv4_drvdata *drvdata = dev_get_drvdata(dev);
2148 struct csdev_access access = { 0 };
2149 struct etm4_init_arg init_arg = { 0 };
2150 struct etm4_init_arg *delayed;
2151
2152 if (WARN_ON(!drvdata))
2153 return -ENOMEM;
2154
2155 if (pm_save_enable == PARAM_PM_SAVE_FIRMWARE)
2156 pm_save_enable = coresight_loses_context_with_cpu(dev) ?
2157 PARAM_PM_SAVE_SELF_HOSTED : PARAM_PM_SAVE_NEVER;
2158
2159 if (pm_save_enable != PARAM_PM_SAVE_NEVER) {
2160 drvdata->save_state = devm_kmalloc(dev,
2161 sizeof(struct etmv4_save_state), GFP_KERNEL);
2162 if (!drvdata->save_state)
2163 return -ENOMEM;
2164 }
2165
2166 spin_lock_init(&drvdata->spinlock);
2167
2168 drvdata->cpu = coresight_get_cpu(dev);
2169 if (drvdata->cpu < 0)
2170 return drvdata->cpu;
2171
2172 init_arg.dev = dev;
2173 init_arg.csa = &access;
2174
2175 /*
2176 * Serialize against CPUHP callbacks to avoid race condition
2177 * between the smp call and saving the delayed probe.
2178 */
2179 cpus_read_lock();
2180 if (smp_call_function_single(drvdata->cpu,
2181 etm4_init_arch_data, &init_arg, 1)) {
2182 /* The CPU was offline, try again once it comes online. */
2183 delayed = devm_kmalloc(dev, sizeof(*delayed), GFP_KERNEL);
2184 if (!delayed) {
2185 cpus_read_unlock();
2186 return -ENOMEM;
2187 }
2188
2189 *delayed = init_arg;
2190
2191 per_cpu(delayed_probe, drvdata->cpu) = delayed;
2192
2193 cpus_read_unlock();
2194 return 0;
2195 }
2196 cpus_read_unlock();
2197
2198 return etm4_add_coresight_dev(&init_arg);
2199 }
2200
etm4_probe_amba(struct amba_device * adev,const struct amba_id * id)2201 static int etm4_probe_amba(struct amba_device *adev, const struct amba_id *id)
2202 {
2203 struct etmv4_drvdata *drvdata;
2204 void __iomem *base;
2205 struct device *dev = &adev->dev;
2206 struct resource *res = &adev->res;
2207 int ret;
2208
2209 /* Validity for the resource is already checked by the AMBA core */
2210 base = devm_ioremap_resource(dev, res);
2211 if (IS_ERR(base))
2212 return PTR_ERR(base);
2213
2214 drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL);
2215 if (!drvdata)
2216 return -ENOMEM;
2217
2218 drvdata->base = base;
2219 dev_set_drvdata(dev, drvdata);
2220 ret = etm4_probe(dev);
2221 if (!ret)
2222 pm_runtime_put(&adev->dev);
2223
2224 return ret;
2225 }
2226
etm4_probe_platform_dev(struct platform_device * pdev)2227 static int etm4_probe_platform_dev(struct platform_device *pdev)
2228 {
2229 struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2230 struct etmv4_drvdata *drvdata;
2231 int ret;
2232
2233 drvdata = devm_kzalloc(&pdev->dev, sizeof(*drvdata), GFP_KERNEL);
2234 if (!drvdata)
2235 return -ENOMEM;
2236
2237 drvdata->pclk = coresight_get_enable_apb_pclk(&pdev->dev);
2238 if (IS_ERR(drvdata->pclk))
2239 return -ENODEV;
2240
2241 if (res) {
2242 drvdata->base = devm_ioremap_resource(&pdev->dev, res);
2243 if (IS_ERR(drvdata->base)) {
2244 clk_put(drvdata->pclk);
2245 return PTR_ERR(drvdata->base);
2246 }
2247 }
2248
2249 dev_set_drvdata(&pdev->dev, drvdata);
2250 pm_runtime_get_noresume(&pdev->dev);
2251 pm_runtime_set_active(&pdev->dev);
2252 pm_runtime_enable(&pdev->dev);
2253
2254 ret = etm4_probe(&pdev->dev);
2255
2256 pm_runtime_put(&pdev->dev);
2257 if (ret)
2258 pm_runtime_disable(&pdev->dev);
2259
2260 return ret;
2261 }
2262
etm4_probe_cpu(unsigned int cpu)2263 static int etm4_probe_cpu(unsigned int cpu)
2264 {
2265 int ret;
2266 struct etm4_init_arg init_arg;
2267 struct csdev_access access = { 0 };
2268 struct etm4_init_arg *iap = *this_cpu_ptr(&delayed_probe);
2269
2270 if (!iap)
2271 return 0;
2272
2273 init_arg = *iap;
2274 devm_kfree(init_arg.dev, iap);
2275 *this_cpu_ptr(&delayed_probe) = NULL;
2276
2277 ret = pm_runtime_resume_and_get(init_arg.dev);
2278 if (ret < 0) {
2279 dev_err(init_arg.dev, "Failed to get PM runtime!\n");
2280 return 0;
2281 }
2282
2283 init_arg.csa = &access;
2284 etm4_init_arch_data(&init_arg);
2285
2286 etm4_add_coresight_dev(&init_arg);
2287
2288 pm_runtime_put(init_arg.dev);
2289 return 0;
2290 }
2291
2292 static struct amba_cs_uci_id uci_id_etm4[] = {
2293 {
2294 /* ETMv4 UCI data */
2295 .devarch = ETM_DEVARCH_ETMv4x_ARCH,
2296 .devarch_mask = ETM_DEVARCH_ID_MASK,
2297 .devtype = CS_DEVTYPE_PE_TRACE,
2298 }
2299 };
2300
clear_etmdrvdata(void * info)2301 static void clear_etmdrvdata(void *info)
2302 {
2303 int cpu = *(int *)info;
2304
2305 etmdrvdata[cpu] = NULL;
2306 per_cpu(delayed_probe, cpu) = NULL;
2307 }
2308
etm4_remove_dev(struct etmv4_drvdata * drvdata)2309 static void etm4_remove_dev(struct etmv4_drvdata *drvdata)
2310 {
2311 bool had_delayed_probe;
2312 /*
2313 * Taking hotplug lock here to avoid racing between etm4_remove_dev()
2314 * and CPU hotplug call backs.
2315 */
2316 cpus_read_lock();
2317
2318 had_delayed_probe = per_cpu(delayed_probe, drvdata->cpu);
2319
2320 /*
2321 * The readers for etmdrvdata[] are CPU hotplug call backs
2322 * and PM notification call backs. Change etmdrvdata[i] on
2323 * CPU i ensures these call backs has consistent view
2324 * inside one call back function.
2325 */
2326 if (smp_call_function_single(drvdata->cpu, clear_etmdrvdata, &drvdata->cpu, 1))
2327 clear_etmdrvdata(&drvdata->cpu);
2328
2329 cpus_read_unlock();
2330
2331 if (!had_delayed_probe) {
2332 etm_perf_symlink(drvdata->csdev, false);
2333 cscfg_unregister_csdev(drvdata->csdev);
2334 coresight_unregister(drvdata->csdev);
2335 }
2336 }
2337
etm4_remove_amba(struct amba_device * adev)2338 static void etm4_remove_amba(struct amba_device *adev)
2339 {
2340 struct etmv4_drvdata *drvdata = dev_get_drvdata(&adev->dev);
2341
2342 if (drvdata)
2343 etm4_remove_dev(drvdata);
2344 }
2345
etm4_remove_platform_dev(struct platform_device * pdev)2346 static void etm4_remove_platform_dev(struct platform_device *pdev)
2347 {
2348 struct etmv4_drvdata *drvdata = dev_get_drvdata(&pdev->dev);
2349
2350 if (drvdata)
2351 etm4_remove_dev(drvdata);
2352 pm_runtime_disable(&pdev->dev);
2353
2354 if (drvdata && !IS_ERR_OR_NULL(drvdata->pclk))
2355 clk_put(drvdata->pclk);
2356 }
2357
2358 static const struct amba_id etm4_ids[] = {
2359 CS_AMBA_ID(0x000bb95d), /* Cortex-A53 */
2360 CS_AMBA_ID(0x000bb95e), /* Cortex-A57 */
2361 CS_AMBA_ID(0x000bb95a), /* Cortex-A72 */
2362 CS_AMBA_ID(0x000bb959), /* Cortex-A73 */
2363 CS_AMBA_UCI_ID(0x000bb9da, uci_id_etm4),/* Cortex-A35 */
2364 CS_AMBA_UCI_ID(0x000bbd05, uci_id_etm4),/* Cortex-A55 */
2365 CS_AMBA_UCI_ID(0x000bbd0a, uci_id_etm4),/* Cortex-A75 */
2366 CS_AMBA_UCI_ID(0x000bbd0c, uci_id_etm4),/* Neoverse N1 */
2367 CS_AMBA_UCI_ID(0x000bbd41, uci_id_etm4),/* Cortex-A78 */
2368 CS_AMBA_UCI_ID(0x000f0205, uci_id_etm4),/* Qualcomm Kryo */
2369 CS_AMBA_UCI_ID(0x000f0211, uci_id_etm4),/* Qualcomm Kryo */
2370 CS_AMBA_UCI_ID(0x000bb802, uci_id_etm4),/* Qualcomm Kryo 385 Cortex-A55 */
2371 CS_AMBA_UCI_ID(0x000bb803, uci_id_etm4),/* Qualcomm Kryo 385 Cortex-A75 */
2372 CS_AMBA_UCI_ID(0x000bb805, uci_id_etm4),/* Qualcomm Kryo 4XX Cortex-A55 */
2373 CS_AMBA_UCI_ID(0x000bb804, uci_id_etm4),/* Qualcomm Kryo 4XX Cortex-A76 */
2374 CS_AMBA_UCI_ID(0x000bbd0d, uci_id_etm4),/* Qualcomm Kryo 5XX Cortex-A77 */
2375 CS_AMBA_UCI_ID(0x000cc0af, uci_id_etm4),/* Marvell ThunderX2 */
2376 CS_AMBA_UCI_ID(0x000b6d01, uci_id_etm4),/* HiSilicon-Hip08 */
2377 CS_AMBA_UCI_ID(0x000b6d02, uci_id_etm4),/* HiSilicon-Hip09 */
2378 /*
2379 * Match all PIDs with ETM4 DEVARCH. No need for adding any of the new
2380 * CPUs to the list here.
2381 */
2382 CS_AMBA_MATCH_ALL_UCI(uci_id_etm4),
2383 {},
2384 };
2385
2386 MODULE_DEVICE_TABLE(amba, etm4_ids);
2387
2388 static struct amba_driver etm4x_amba_driver = {
2389 .drv = {
2390 .name = "coresight-etm4x",
2391 .suppress_bind_attrs = true,
2392 },
2393 .probe = etm4_probe_amba,
2394 .remove = etm4_remove_amba,
2395 .id_table = etm4_ids,
2396 };
2397
2398 #ifdef CONFIG_PM
etm4_runtime_suspend(struct device * dev)2399 static int etm4_runtime_suspend(struct device *dev)
2400 {
2401 struct etmv4_drvdata *drvdata = dev_get_drvdata(dev);
2402
2403 if (drvdata->pclk && !IS_ERR(drvdata->pclk))
2404 clk_disable_unprepare(drvdata->pclk);
2405
2406 return 0;
2407 }
2408
etm4_runtime_resume(struct device * dev)2409 static int etm4_runtime_resume(struct device *dev)
2410 {
2411 struct etmv4_drvdata *drvdata = dev_get_drvdata(dev);
2412
2413 if (drvdata->pclk && !IS_ERR(drvdata->pclk))
2414 clk_prepare_enable(drvdata->pclk);
2415
2416 return 0;
2417 }
2418 #endif
2419
2420 static const struct dev_pm_ops etm4_dev_pm_ops = {
2421 SET_RUNTIME_PM_OPS(etm4_runtime_suspend, etm4_runtime_resume, NULL)
2422 };
2423
2424 static const struct of_device_id etm4_sysreg_match[] = {
2425 { .compatible = "arm,coresight-etm4x-sysreg" },
2426 { .compatible = "arm,embedded-trace-extension" },
2427 {}
2428 };
2429
2430 #ifdef CONFIG_ACPI
2431 static const struct acpi_device_id etm4x_acpi_ids[] = {
2432 {"ARMHC500", 0, 0, 0}, /* ARM CoreSight ETM4x */
2433 {}
2434 };
2435 MODULE_DEVICE_TABLE(acpi, etm4x_acpi_ids);
2436 #endif
2437
2438 static struct platform_driver etm4_platform_driver = {
2439 .probe = etm4_probe_platform_dev,
2440 .remove_new = etm4_remove_platform_dev,
2441 .driver = {
2442 .name = "coresight-etm4x",
2443 .of_match_table = etm4_sysreg_match,
2444 .acpi_match_table = ACPI_PTR(etm4x_acpi_ids),
2445 .suppress_bind_attrs = true,
2446 .pm = &etm4_dev_pm_ops,
2447 },
2448 };
2449
etm4x_init(void)2450 static int __init etm4x_init(void)
2451 {
2452 int ret;
2453
2454 ret = etm4_pm_setup();
2455
2456 /* etm4_pm_setup() does its own cleanup - exit on error */
2457 if (ret)
2458 return ret;
2459
2460 ret = amba_driver_register(&etm4x_amba_driver);
2461 if (ret) {
2462 pr_err("Error registering etm4x AMBA driver\n");
2463 goto clear_pm;
2464 }
2465
2466 ret = platform_driver_register(&etm4_platform_driver);
2467 if (!ret)
2468 return 0;
2469
2470 pr_err("Error registering etm4x platform driver\n");
2471 amba_driver_unregister(&etm4x_amba_driver);
2472
2473 clear_pm:
2474 etm4_pm_clear();
2475 return ret;
2476 }
2477
etm4x_exit(void)2478 static void __exit etm4x_exit(void)
2479 {
2480 amba_driver_unregister(&etm4x_amba_driver);
2481 platform_driver_unregister(&etm4_platform_driver);
2482 etm4_pm_clear();
2483 }
2484
2485 module_init(etm4x_init);
2486 module_exit(etm4x_exit);
2487
2488 MODULE_AUTHOR("Pratik Patel <pratikp@codeaurora.org>");
2489 MODULE_AUTHOR("Mathieu Poirier <mathieu.poirier@linaro.org>");
2490 MODULE_DESCRIPTION("Arm CoreSight Program Flow Trace v4.x driver");
2491 MODULE_LICENSE("GPL v2");
2492