1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2002 Motorola GSG-China
4 *
5 * Author:
6 * Darius Augulis, Teltonika Inc.
7 *
8 * Desc.:
9 * Implementation of I2C Adapter/Algorithm Driver
10 * for I2C Bus integrated in Freescale i.MX/MXC processors
11 *
12 * Derived from Motorola GSG China I2C example driver
13 *
14 * Copyright (C) 2005 Torsten Koschorrek <koschorrek at synertronixx.de
15 * Copyright (C) 2005 Matthias Blaschke <blaschke at synertronixx.de
16 * Copyright (C) 2007 RightHand Technologies, Inc.
17 * Copyright (C) 2008 Darius Augulis <darius.augulis at teltonika.lt>
18 *
19 * Copyright 2013 Freescale Semiconductor, Inc.
20 * Copyright 2020 NXP
21 *
22 */
23
24 #include <linux/acpi.h>
25 #include <linux/clk.h>
26 #include <linux/completion.h>
27 #include <linux/delay.h>
28 #include <linux/dma-mapping.h>
29 #include <linux/dmaengine.h>
30 #include <linux/dmapool.h>
31 #include <linux/err.h>
32 #include <linux/errno.h>
33 #include <linux/gpio/consumer.h>
34 #include <linux/i2c.h>
35 #include <linux/init.h>
36 #include <linux/interrupt.h>
37 #include <linux/io.h>
38 #include <linux/iopoll.h>
39 #include <linux/kernel.h>
40 #include <linux/spinlock.h>
41 #include <linux/hrtimer.h>
42 #include <linux/module.h>
43 #include <linux/of.h>
44 #include <linux/of_dma.h>
45 #include <linux/pinctrl/consumer.h>
46 #include <linux/platform_data/i2c-imx.h>
47 #include <linux/platform_device.h>
48 #include <linux/pm_runtime.h>
49 #include <linux/sched.h>
50 #include <linux/slab.h>
51
52 /* This will be the driver name the kernel reports */
53 #define DRIVER_NAME "imx-i2c"
54
55 #define I2C_IMX_CHECK_DELAY 30000 /* Time to check for bus idle, in NS */
56
57 /*
58 * Enable DMA if transfer byte size is bigger than this threshold.
59 * As the hardware request, it must bigger than 4 bytes.\
60 * I have set '16' here, maybe it's not the best but I think it's
61 * the appropriate.
62 */
63 #define DMA_THRESHOLD 16
64 #define DMA_TIMEOUT 1000
65
66 /* IMX I2C registers:
67 * the I2C register offset is different between SoCs,
68 * to provide support for all these chips, split the
69 * register offset into a fixed base address and a
70 * variable shift value, then the full register offset
71 * will be calculated by
72 * reg_off = ( reg_base_addr << reg_shift)
73 */
74 #define IMX_I2C_IADR 0x00 /* i2c slave address */
75 #define IMX_I2C_IFDR 0x01 /* i2c frequency divider */
76 #define IMX_I2C_I2CR 0x02 /* i2c control */
77 #define IMX_I2C_I2SR 0x03 /* i2c status */
78 #define IMX_I2C_I2DR 0x04 /* i2c transfer data */
79
80 /*
81 * All of the layerscape series SoCs support IBIC register.
82 */
83 #define IMX_I2C_IBIC 0x05 /* i2c bus interrupt config */
84
85 #define IMX_I2C_REGSHIFT 2
86 #define VF610_I2C_REGSHIFT 0
87
88 /* Bits of IMX I2C registers */
89 #define I2SR_RXAK 0x01
90 #define I2SR_IIF 0x02
91 #define I2SR_SRW 0x04
92 #define I2SR_IAL 0x10
93 #define I2SR_IBB 0x20
94 #define I2SR_IAAS 0x40
95 #define I2SR_ICF 0x80
96 #define I2CR_DMAEN 0x02
97 #define I2CR_RSTA 0x04
98 #define I2CR_TXAK 0x08
99 #define I2CR_MTX 0x10
100 #define I2CR_MSTA 0x20
101 #define I2CR_IIEN 0x40
102 #define I2CR_IEN 0x80
103 #define IBIC_BIIE 0x80 /* Bus idle interrupt enable */
104
105 /* register bits different operating codes definition:
106 * 1) I2SR: Interrupt flags clear operation differ between SoCs:
107 * - write zero to clear(w0c) INT flag on i.MX,
108 * - but write one to clear(w1c) INT flag on Vybrid.
109 * 2) I2CR: I2C module enable operation also differ between SoCs:
110 * - set I2CR_IEN bit enable the module on i.MX,
111 * - but clear I2CR_IEN bit enable the module on Vybrid.
112 */
113 #define I2SR_CLR_OPCODE_W0C 0x0
114 #define I2SR_CLR_OPCODE_W1C (I2SR_IAL | I2SR_IIF)
115 #define I2CR_IEN_OPCODE_0 0x0
116 #define I2CR_IEN_OPCODE_1 I2CR_IEN
117
118 #define I2C_PM_TIMEOUT 10 /* ms */
119
120 /*
121 * sorted list of clock divider, register value pairs
122 * taken from table 26-5, p.26-9, Freescale i.MX
123 * Integrated Portable System Processor Reference Manual
124 * Document Number: MC9328MXLRM, Rev. 5.1, 06/2007
125 *
126 * Duplicated divider values removed from list
127 */
128 struct imx_i2c_clk_pair {
129 u16 div;
130 u16 val;
131 };
132
133 static struct imx_i2c_clk_pair imx_i2c_clk_div[] = {
134 { 22, 0x20 }, { 24, 0x21 }, { 26, 0x22 }, { 28, 0x23 },
135 { 30, 0x00 }, { 32, 0x24 }, { 36, 0x25 }, { 40, 0x26 },
136 { 42, 0x03 }, { 44, 0x27 }, { 48, 0x28 }, { 52, 0x05 },
137 { 56, 0x29 }, { 60, 0x06 }, { 64, 0x2A }, { 72, 0x2B },
138 { 80, 0x2C }, { 88, 0x09 }, { 96, 0x2D }, { 104, 0x0A },
139 { 112, 0x2E }, { 128, 0x2F }, { 144, 0x0C }, { 160, 0x30 },
140 { 192, 0x31 }, { 224, 0x32 }, { 240, 0x0F }, { 256, 0x33 },
141 { 288, 0x10 }, { 320, 0x34 }, { 384, 0x35 }, { 448, 0x36 },
142 { 480, 0x13 }, { 512, 0x37 }, { 576, 0x14 }, { 640, 0x38 },
143 { 768, 0x39 }, { 896, 0x3A }, { 960, 0x17 }, { 1024, 0x3B },
144 { 1152, 0x18 }, { 1280, 0x3C }, { 1536, 0x3D }, { 1792, 0x3E },
145 { 1920, 0x1B }, { 2048, 0x3F }, { 2304, 0x1C }, { 2560, 0x1D },
146 { 3072, 0x1E }, { 3840, 0x1F }
147 };
148
149 /* Vybrid VF610 clock divider, register value pairs */
150 static struct imx_i2c_clk_pair vf610_i2c_clk_div[] = {
151 { 20, 0x00 }, { 22, 0x01 }, { 24, 0x02 }, { 26, 0x03 },
152 { 28, 0x04 }, { 30, 0x05 }, { 32, 0x09 }, { 34, 0x06 },
153 { 36, 0x0A }, { 40, 0x07 }, { 44, 0x0C }, { 48, 0x0D },
154 { 52, 0x43 }, { 56, 0x0E }, { 60, 0x45 }, { 64, 0x12 },
155 { 68, 0x0F }, { 72, 0x13 }, { 80, 0x14 }, { 88, 0x15 },
156 { 96, 0x19 }, { 104, 0x16 }, { 112, 0x1A }, { 128, 0x17 },
157 { 136, 0x4F }, { 144, 0x1C }, { 160, 0x1D }, { 176, 0x55 },
158 { 192, 0x1E }, { 208, 0x56 }, { 224, 0x22 }, { 228, 0x24 },
159 { 240, 0x1F }, { 256, 0x23 }, { 288, 0x5C }, { 320, 0x25 },
160 { 384, 0x26 }, { 448, 0x2A }, { 480, 0x27 }, { 512, 0x2B },
161 { 576, 0x2C }, { 640, 0x2D }, { 768, 0x31 }, { 896, 0x32 },
162 { 960, 0x2F }, { 1024, 0x33 }, { 1152, 0x34 }, { 1280, 0x35 },
163 { 1536, 0x36 }, { 1792, 0x3A }, { 1920, 0x37 }, { 2048, 0x3B },
164 { 2304, 0x3C }, { 2560, 0x3D }, { 3072, 0x3E }, { 3584, 0x7A },
165 { 3840, 0x3F }, { 4096, 0x7B }, { 5120, 0x7D }, { 6144, 0x7E },
166 };
167
168 enum imx_i2c_type {
169 IMX1_I2C,
170 IMX21_I2C,
171 VF610_I2C,
172 };
173
174 struct imx_i2c_hwdata {
175 enum imx_i2c_type devtype;
176 unsigned int regshift;
177 struct imx_i2c_clk_pair *clk_div;
178 unsigned int ndivs;
179 unsigned int i2sr_clr_opcode;
180 unsigned int i2cr_ien_opcode;
181 /*
182 * Errata ERR007805 or e7805:
183 * I2C: When the I2C clock speed is configured for 400 kHz,
184 * the SCL low period violates the I2C spec of 1.3 uS min.
185 */
186 bool has_err007805;
187 };
188
189 struct imx_i2c_dma {
190 struct dma_chan *chan_tx;
191 struct dma_chan *chan_rx;
192 struct dma_chan *chan_using;
193 struct completion cmd_complete;
194 dma_addr_t dma_buf;
195 unsigned int dma_len;
196 enum dma_transfer_direction dma_transfer_dir;
197 enum dma_data_direction dma_data_dir;
198 };
199
200 struct imx_i2c_struct {
201 struct i2c_adapter adapter;
202 struct clk *clk;
203 struct notifier_block clk_change_nb;
204 void __iomem *base;
205 wait_queue_head_t queue;
206 unsigned long i2csr;
207 unsigned int disable_delay;
208 int stopped;
209 unsigned int ifdr; /* IMX_I2C_IFDR */
210 unsigned int cur_clk;
211 unsigned int bitrate;
212 const struct imx_i2c_hwdata *hwdata;
213 struct i2c_bus_recovery_info rinfo;
214
215 struct imx_i2c_dma *dma;
216 struct i2c_client *slave;
217 enum i2c_slave_event last_slave_event;
218
219 /* For checking slave events. */
220 spinlock_t slave_lock;
221 struct hrtimer slave_timer;
222 };
223
224 static const struct imx_i2c_hwdata imx1_i2c_hwdata = {
225 .devtype = IMX1_I2C,
226 .regshift = IMX_I2C_REGSHIFT,
227 .clk_div = imx_i2c_clk_div,
228 .ndivs = ARRAY_SIZE(imx_i2c_clk_div),
229 .i2sr_clr_opcode = I2SR_CLR_OPCODE_W0C,
230 .i2cr_ien_opcode = I2CR_IEN_OPCODE_1,
231
232 };
233
234 static const struct imx_i2c_hwdata imx21_i2c_hwdata = {
235 .devtype = IMX21_I2C,
236 .regshift = IMX_I2C_REGSHIFT,
237 .clk_div = imx_i2c_clk_div,
238 .ndivs = ARRAY_SIZE(imx_i2c_clk_div),
239 .i2sr_clr_opcode = I2SR_CLR_OPCODE_W0C,
240 .i2cr_ien_opcode = I2CR_IEN_OPCODE_1,
241
242 };
243
244 static const struct imx_i2c_hwdata imx6_i2c_hwdata = {
245 .devtype = IMX21_I2C,
246 .regshift = IMX_I2C_REGSHIFT,
247 .clk_div = imx_i2c_clk_div,
248 .ndivs = ARRAY_SIZE(imx_i2c_clk_div),
249 .i2sr_clr_opcode = I2SR_CLR_OPCODE_W0C,
250 .i2cr_ien_opcode = I2CR_IEN_OPCODE_1,
251 .has_err007805 = true,
252 };
253
254 static struct imx_i2c_hwdata vf610_i2c_hwdata = {
255 .devtype = VF610_I2C,
256 .regshift = VF610_I2C_REGSHIFT,
257 .clk_div = vf610_i2c_clk_div,
258 .ndivs = ARRAY_SIZE(vf610_i2c_clk_div),
259 .i2sr_clr_opcode = I2SR_CLR_OPCODE_W1C,
260 .i2cr_ien_opcode = I2CR_IEN_OPCODE_0,
261
262 };
263
264 static const struct platform_device_id imx_i2c_devtype[] = {
265 {
266 .name = "imx1-i2c",
267 .driver_data = (kernel_ulong_t)&imx1_i2c_hwdata,
268 }, {
269 .name = "imx21-i2c",
270 .driver_data = (kernel_ulong_t)&imx21_i2c_hwdata,
271 }, {
272 /* sentinel */
273 }
274 };
275 MODULE_DEVICE_TABLE(platform, imx_i2c_devtype);
276
277 static const struct of_device_id i2c_imx_dt_ids[] = {
278 { .compatible = "fsl,imx1-i2c", .data = &imx1_i2c_hwdata, },
279 { .compatible = "fsl,imx21-i2c", .data = &imx21_i2c_hwdata, },
280 { .compatible = "fsl,imx6q-i2c", .data = &imx6_i2c_hwdata, },
281 { .compatible = "fsl,imx6sl-i2c", .data = &imx6_i2c_hwdata, },
282 { .compatible = "fsl,imx6sll-i2c", .data = &imx6_i2c_hwdata, },
283 { .compatible = "fsl,imx6sx-i2c", .data = &imx6_i2c_hwdata, },
284 { .compatible = "fsl,imx6ul-i2c", .data = &imx6_i2c_hwdata, },
285 { .compatible = "fsl,imx7d-i2c", .data = &imx6_i2c_hwdata, },
286 { .compatible = "fsl,imx7s-i2c", .data = &imx6_i2c_hwdata, },
287 { .compatible = "fsl,imx8mm-i2c", .data = &imx6_i2c_hwdata, },
288 { .compatible = "fsl,imx8mn-i2c", .data = &imx6_i2c_hwdata, },
289 { .compatible = "fsl,imx8mp-i2c", .data = &imx6_i2c_hwdata, },
290 { .compatible = "fsl,imx8mq-i2c", .data = &imx6_i2c_hwdata, },
291 { .compatible = "fsl,vf610-i2c", .data = &vf610_i2c_hwdata, },
292 { /* sentinel */ }
293 };
294 MODULE_DEVICE_TABLE(of, i2c_imx_dt_ids);
295
296 static const struct acpi_device_id i2c_imx_acpi_ids[] = {
297 {"NXP0001", .driver_data = (kernel_ulong_t)&vf610_i2c_hwdata},
298 { }
299 };
300 MODULE_DEVICE_TABLE(acpi, i2c_imx_acpi_ids);
301
is_imx1_i2c(struct imx_i2c_struct * i2c_imx)302 static inline int is_imx1_i2c(struct imx_i2c_struct *i2c_imx)
303 {
304 return i2c_imx->hwdata->devtype == IMX1_I2C;
305 }
306
is_vf610_i2c(struct imx_i2c_struct * i2c_imx)307 static inline int is_vf610_i2c(struct imx_i2c_struct *i2c_imx)
308 {
309 return i2c_imx->hwdata->devtype == VF610_I2C;
310 }
311
imx_i2c_write_reg(unsigned int val,struct imx_i2c_struct * i2c_imx,unsigned int reg)312 static inline void imx_i2c_write_reg(unsigned int val,
313 struct imx_i2c_struct *i2c_imx, unsigned int reg)
314 {
315 writeb(val, i2c_imx->base + (reg << i2c_imx->hwdata->regshift));
316 }
317
imx_i2c_read_reg(struct imx_i2c_struct * i2c_imx,unsigned int reg)318 static inline unsigned char imx_i2c_read_reg(struct imx_i2c_struct *i2c_imx,
319 unsigned int reg)
320 {
321 return readb(i2c_imx->base + (reg << i2c_imx->hwdata->regshift));
322 }
323
i2c_imx_clear_irq(struct imx_i2c_struct * i2c_imx,unsigned int bits)324 static void i2c_imx_clear_irq(struct imx_i2c_struct *i2c_imx, unsigned int bits)
325 {
326 unsigned int temp;
327
328 /*
329 * i2sr_clr_opcode is the value to clear all interrupts. Here we want to
330 * clear only <bits>, so we write ~i2sr_clr_opcode with just <bits>
331 * toggled. This is required because i.MX needs W0C and Vybrid uses W1C.
332 */
333 temp = ~i2c_imx->hwdata->i2sr_clr_opcode ^ bits;
334 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2SR);
335 }
336
337 /* Set up i2c controller register and i2c status register to default value. */
i2c_imx_reset_regs(struct imx_i2c_struct * i2c_imx)338 static void i2c_imx_reset_regs(struct imx_i2c_struct *i2c_imx)
339 {
340 imx_i2c_write_reg(i2c_imx->hwdata->i2cr_ien_opcode ^ I2CR_IEN,
341 i2c_imx, IMX_I2C_I2CR);
342 i2c_imx_clear_irq(i2c_imx, I2SR_IIF | I2SR_IAL);
343 }
344
345 /* Functions for DMA support */
i2c_imx_dma_request(struct imx_i2c_struct * i2c_imx,dma_addr_t phy_addr)346 static void i2c_imx_dma_request(struct imx_i2c_struct *i2c_imx,
347 dma_addr_t phy_addr)
348 {
349 struct imx_i2c_dma *dma;
350 struct dma_slave_config dma_sconfig;
351 struct device *dev = &i2c_imx->adapter.dev;
352 int ret;
353
354 dma = devm_kzalloc(dev, sizeof(*dma), GFP_KERNEL);
355 if (!dma)
356 return;
357
358 dma->chan_tx = dma_request_chan(dev, "tx");
359 if (IS_ERR(dma->chan_tx)) {
360 ret = PTR_ERR(dma->chan_tx);
361 if (ret != -ENODEV && ret != -EPROBE_DEFER)
362 dev_err(dev, "can't request DMA tx channel (%d)\n", ret);
363 goto fail_al;
364 }
365
366 dma_sconfig.dst_addr = phy_addr +
367 (IMX_I2C_I2DR << i2c_imx->hwdata->regshift);
368 dma_sconfig.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
369 dma_sconfig.dst_maxburst = 1;
370 dma_sconfig.direction = DMA_MEM_TO_DEV;
371 ret = dmaengine_slave_config(dma->chan_tx, &dma_sconfig);
372 if (ret < 0) {
373 dev_err(dev, "can't configure tx channel (%d)\n", ret);
374 goto fail_tx;
375 }
376
377 dma->chan_rx = dma_request_chan(dev, "rx");
378 if (IS_ERR(dma->chan_rx)) {
379 ret = PTR_ERR(dma->chan_rx);
380 if (ret != -ENODEV && ret != -EPROBE_DEFER)
381 dev_err(dev, "can't request DMA rx channel (%d)\n", ret);
382 goto fail_tx;
383 }
384
385 dma_sconfig.src_addr = phy_addr +
386 (IMX_I2C_I2DR << i2c_imx->hwdata->regshift);
387 dma_sconfig.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
388 dma_sconfig.src_maxburst = 1;
389 dma_sconfig.direction = DMA_DEV_TO_MEM;
390 ret = dmaengine_slave_config(dma->chan_rx, &dma_sconfig);
391 if (ret < 0) {
392 dev_err(dev, "can't configure rx channel (%d)\n", ret);
393 goto fail_rx;
394 }
395
396 i2c_imx->dma = dma;
397 init_completion(&dma->cmd_complete);
398 dev_info(dev, "using %s (tx) and %s (rx) for DMA transfers\n",
399 dma_chan_name(dma->chan_tx), dma_chan_name(dma->chan_rx));
400
401 return;
402
403 fail_rx:
404 dma_release_channel(dma->chan_rx);
405 fail_tx:
406 dma_release_channel(dma->chan_tx);
407 fail_al:
408 devm_kfree(dev, dma);
409 }
410
i2c_imx_dma_callback(void * arg)411 static void i2c_imx_dma_callback(void *arg)
412 {
413 struct imx_i2c_struct *i2c_imx = (struct imx_i2c_struct *)arg;
414 struct imx_i2c_dma *dma = i2c_imx->dma;
415
416 dma_unmap_single(dma->chan_using->device->dev, dma->dma_buf,
417 dma->dma_len, dma->dma_data_dir);
418 complete(&dma->cmd_complete);
419 }
420
i2c_imx_dma_xfer(struct imx_i2c_struct * i2c_imx,struct i2c_msg * msgs)421 static int i2c_imx_dma_xfer(struct imx_i2c_struct *i2c_imx,
422 struct i2c_msg *msgs)
423 {
424 struct imx_i2c_dma *dma = i2c_imx->dma;
425 struct dma_async_tx_descriptor *txdesc;
426 struct device *dev = &i2c_imx->adapter.dev;
427 struct device *chan_dev = dma->chan_using->device->dev;
428
429 dma->dma_buf = dma_map_single(chan_dev, msgs->buf,
430 dma->dma_len, dma->dma_data_dir);
431 if (dma_mapping_error(chan_dev, dma->dma_buf)) {
432 dev_err(dev, "DMA mapping failed\n");
433 goto err_map;
434 }
435
436 txdesc = dmaengine_prep_slave_single(dma->chan_using, dma->dma_buf,
437 dma->dma_len, dma->dma_transfer_dir,
438 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
439 if (!txdesc) {
440 dev_err(dev, "Not able to get desc for DMA xfer\n");
441 goto err_desc;
442 }
443
444 reinit_completion(&dma->cmd_complete);
445 txdesc->callback = i2c_imx_dma_callback;
446 txdesc->callback_param = i2c_imx;
447 if (dma_submit_error(dmaengine_submit(txdesc))) {
448 dev_err(dev, "DMA submit failed\n");
449 goto err_submit;
450 }
451
452 dma_async_issue_pending(dma->chan_using);
453 return 0;
454
455 err_submit:
456 dmaengine_terminate_sync(dma->chan_using);
457 err_desc:
458 dma_unmap_single(chan_dev, dma->dma_buf,
459 dma->dma_len, dma->dma_data_dir);
460 err_map:
461 return -EINVAL;
462 }
463
i2c_imx_dma_free(struct imx_i2c_struct * i2c_imx)464 static void i2c_imx_dma_free(struct imx_i2c_struct *i2c_imx)
465 {
466 struct imx_i2c_dma *dma = i2c_imx->dma;
467
468 dma->dma_buf = 0;
469 dma->dma_len = 0;
470
471 dma_release_channel(dma->chan_tx);
472 dma->chan_tx = NULL;
473
474 dma_release_channel(dma->chan_rx);
475 dma->chan_rx = NULL;
476
477 dma->chan_using = NULL;
478 }
479
i2c_imx_bus_busy(struct imx_i2c_struct * i2c_imx,int for_busy,bool atomic)480 static int i2c_imx_bus_busy(struct imx_i2c_struct *i2c_imx, int for_busy, bool atomic)
481 {
482 unsigned long orig_jiffies = jiffies;
483 unsigned int temp;
484
485 while (1) {
486 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR);
487
488 /* check for arbitration lost */
489 if (temp & I2SR_IAL) {
490 i2c_imx_clear_irq(i2c_imx, I2SR_IAL);
491 return -EAGAIN;
492 }
493
494 if (for_busy && (temp & I2SR_IBB)) {
495 i2c_imx->stopped = 0;
496 break;
497 }
498 if (!for_busy && !(temp & I2SR_IBB)) {
499 i2c_imx->stopped = 1;
500 break;
501 }
502 if (time_after(jiffies, orig_jiffies + msecs_to_jiffies(500))) {
503 dev_dbg(&i2c_imx->adapter.dev,
504 "<%s> I2C bus is busy\n", __func__);
505 return -ETIMEDOUT;
506 }
507 if (atomic)
508 udelay(100);
509 else
510 schedule();
511 }
512
513 return 0;
514 }
515
i2c_imx_trx_complete(struct imx_i2c_struct * i2c_imx,bool atomic)516 static int i2c_imx_trx_complete(struct imx_i2c_struct *i2c_imx, bool atomic)
517 {
518 if (atomic) {
519 void __iomem *addr = i2c_imx->base + (IMX_I2C_I2SR << i2c_imx->hwdata->regshift);
520 unsigned int regval;
521
522 /*
523 * The formula for the poll timeout is documented in the RM
524 * Rev.5 on page 1878:
525 * T_min = 10/F_scl
526 * Set the value hard as it is done for the non-atomic use-case.
527 * Use 10 kHz for the calculation since this is the minimum
528 * allowed SMBus frequency. Also add an offset of 100us since it
529 * turned out that the I2SR_IIF bit isn't set correctly within
530 * the minimum timeout in polling mode.
531 */
532 readb_poll_timeout_atomic(addr, regval, regval & I2SR_IIF, 5, 1000 + 100);
533 i2c_imx->i2csr = regval;
534 i2c_imx_clear_irq(i2c_imx, I2SR_IIF | I2SR_IAL);
535 } else {
536 wait_event_timeout(i2c_imx->queue, i2c_imx->i2csr & I2SR_IIF, HZ / 10);
537 }
538
539 if (unlikely(!(i2c_imx->i2csr & I2SR_IIF))) {
540 dev_dbg(&i2c_imx->adapter.dev, "<%s> Timeout\n", __func__);
541 return -ETIMEDOUT;
542 }
543
544 /* check for arbitration lost */
545 if (i2c_imx->i2csr & I2SR_IAL) {
546 dev_dbg(&i2c_imx->adapter.dev, "<%s> Arbitration lost\n", __func__);
547 i2c_imx_clear_irq(i2c_imx, I2SR_IAL);
548
549 i2c_imx->i2csr = 0;
550 return -EAGAIN;
551 }
552
553 dev_dbg(&i2c_imx->adapter.dev, "<%s> TRX complete\n", __func__);
554 i2c_imx->i2csr = 0;
555 return 0;
556 }
557
i2c_imx_acked(struct imx_i2c_struct * i2c_imx)558 static int i2c_imx_acked(struct imx_i2c_struct *i2c_imx)
559 {
560 if (imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR) & I2SR_RXAK) {
561 dev_dbg(&i2c_imx->adapter.dev, "<%s> No ACK\n", __func__);
562 return -ENXIO; /* No ACK */
563 }
564
565 dev_dbg(&i2c_imx->adapter.dev, "<%s> ACK received\n", __func__);
566 return 0;
567 }
568
i2c_imx_set_clk(struct imx_i2c_struct * i2c_imx,unsigned int i2c_clk_rate)569 static void i2c_imx_set_clk(struct imx_i2c_struct *i2c_imx,
570 unsigned int i2c_clk_rate)
571 {
572 struct imx_i2c_clk_pair *i2c_clk_div = i2c_imx->hwdata->clk_div;
573 unsigned int div;
574 int i;
575
576 if (i2c_imx->hwdata->has_err007805 && i2c_imx->bitrate > 384000) {
577 dev_dbg(&i2c_imx->adapter.dev,
578 "SoC errata ERR007805 or e7805 applies, bus frequency limited from %d Hz to 384000 Hz.\n",
579 i2c_imx->bitrate);
580 i2c_imx->bitrate = 384000;
581 }
582
583 /* Divider value calculation */
584 if (i2c_imx->cur_clk == i2c_clk_rate)
585 return;
586
587 i2c_imx->cur_clk = i2c_clk_rate;
588
589 div = DIV_ROUND_UP(i2c_clk_rate, i2c_imx->bitrate);
590 if (div < i2c_clk_div[0].div)
591 i = 0;
592 else if (div > i2c_clk_div[i2c_imx->hwdata->ndivs - 1].div)
593 i = i2c_imx->hwdata->ndivs - 1;
594 else
595 for (i = 0; i2c_clk_div[i].div < div; i++)
596 ;
597
598 /* Store divider value */
599 i2c_imx->ifdr = i2c_clk_div[i].val;
600
601 /*
602 * There dummy delay is calculated.
603 * It should be about one I2C clock period long.
604 * This delay is used in I2C bus disable function
605 * to fix chip hardware bug.
606 */
607 i2c_imx->disable_delay = DIV_ROUND_UP(500000U * i2c_clk_div[i].div,
608 i2c_clk_rate / 2);
609
610 #ifdef CONFIG_I2C_DEBUG_BUS
611 dev_dbg(&i2c_imx->adapter.dev, "I2C_CLK=%d, REQ DIV=%d\n",
612 i2c_clk_rate, div);
613 dev_dbg(&i2c_imx->adapter.dev, "IFDR[IC]=0x%x, REAL DIV=%d\n",
614 i2c_clk_div[i].val, i2c_clk_div[i].div);
615 #endif
616 }
617
i2c_imx_clk_notifier_call(struct notifier_block * nb,unsigned long action,void * data)618 static int i2c_imx_clk_notifier_call(struct notifier_block *nb,
619 unsigned long action, void *data)
620 {
621 struct clk_notifier_data *ndata = data;
622 struct imx_i2c_struct *i2c_imx = container_of(nb,
623 struct imx_i2c_struct,
624 clk_change_nb);
625
626 if (action & POST_RATE_CHANGE)
627 i2c_imx_set_clk(i2c_imx, ndata->new_rate);
628
629 return NOTIFY_OK;
630 }
631
i2c_imx_start(struct imx_i2c_struct * i2c_imx,bool atomic)632 static int i2c_imx_start(struct imx_i2c_struct *i2c_imx, bool atomic)
633 {
634 unsigned int temp = 0;
635 int result;
636
637 imx_i2c_write_reg(i2c_imx->ifdr, i2c_imx, IMX_I2C_IFDR);
638 /* Enable I2C controller */
639 imx_i2c_write_reg(i2c_imx->hwdata->i2sr_clr_opcode, i2c_imx, IMX_I2C_I2SR);
640 imx_i2c_write_reg(i2c_imx->hwdata->i2cr_ien_opcode, i2c_imx, IMX_I2C_I2CR);
641
642 /* Wait controller to be stable */
643 if (atomic)
644 udelay(50);
645 else
646 usleep_range(50, 150);
647
648 /* Start I2C transaction */
649 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
650 temp |= I2CR_MSTA;
651 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
652 result = i2c_imx_bus_busy(i2c_imx, 1, atomic);
653 if (result)
654 return result;
655
656 temp |= I2CR_IIEN | I2CR_MTX | I2CR_TXAK;
657 if (atomic)
658 temp &= ~I2CR_IIEN; /* Disable interrupt */
659
660 temp &= ~I2CR_DMAEN;
661 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
662 return result;
663 }
664
i2c_imx_stop(struct imx_i2c_struct * i2c_imx,bool atomic)665 static void i2c_imx_stop(struct imx_i2c_struct *i2c_imx, bool atomic)
666 {
667 unsigned int temp = 0;
668
669 if (!i2c_imx->stopped) {
670 /* Stop I2C transaction */
671 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
672 if (!(temp & I2CR_MSTA))
673 i2c_imx->stopped = 1;
674 temp &= ~(I2CR_MSTA | I2CR_MTX);
675 if (i2c_imx->dma)
676 temp &= ~I2CR_DMAEN;
677 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
678 }
679 if (is_imx1_i2c(i2c_imx)) {
680 /*
681 * This delay caused by an i.MXL hardware bug.
682 * If no (or too short) delay, no "STOP" bit will be generated.
683 */
684 udelay(i2c_imx->disable_delay);
685 }
686
687 if (!i2c_imx->stopped)
688 i2c_imx_bus_busy(i2c_imx, 0, atomic);
689
690 /* Disable I2C controller */
691 temp = i2c_imx->hwdata->i2cr_ien_opcode ^ I2CR_IEN;
692 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
693 }
694
695 /*
696 * Enable bus idle interrupts
697 * Note: IBIC register will be cleared after disabled i2c module.
698 * All of layerscape series SoCs support IBIC register.
699 */
i2c_imx_enable_bus_idle(struct imx_i2c_struct * i2c_imx)700 static void i2c_imx_enable_bus_idle(struct imx_i2c_struct *i2c_imx)
701 {
702 if (is_vf610_i2c(i2c_imx)) {
703 unsigned int temp;
704
705 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_IBIC);
706 temp |= IBIC_BIIE;
707 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_IBIC);
708 }
709 }
710
i2c_imx_slave_event(struct imx_i2c_struct * i2c_imx,enum i2c_slave_event event,u8 * val)711 static void i2c_imx_slave_event(struct imx_i2c_struct *i2c_imx,
712 enum i2c_slave_event event, u8 *val)
713 {
714 i2c_slave_event(i2c_imx->slave, event, val);
715 i2c_imx->last_slave_event = event;
716 }
717
i2c_imx_slave_finish_op(struct imx_i2c_struct * i2c_imx)718 static void i2c_imx_slave_finish_op(struct imx_i2c_struct *i2c_imx)
719 {
720 u8 val = 0;
721
722 while (i2c_imx->last_slave_event != I2C_SLAVE_STOP) {
723 switch (i2c_imx->last_slave_event) {
724 case I2C_SLAVE_READ_REQUESTED:
725 i2c_imx_slave_event(i2c_imx, I2C_SLAVE_READ_PROCESSED,
726 &val);
727 break;
728
729 case I2C_SLAVE_WRITE_REQUESTED:
730 case I2C_SLAVE_READ_PROCESSED:
731 case I2C_SLAVE_WRITE_RECEIVED:
732 i2c_imx_slave_event(i2c_imx, I2C_SLAVE_STOP, &val);
733 break;
734
735 case I2C_SLAVE_STOP:
736 break;
737 }
738 }
739 }
740
741 /* Returns true if the timer should be restarted, false if not. */
i2c_imx_slave_handle(struct imx_i2c_struct * i2c_imx,unsigned int status,unsigned int ctl)742 static irqreturn_t i2c_imx_slave_handle(struct imx_i2c_struct *i2c_imx,
743 unsigned int status, unsigned int ctl)
744 {
745 u8 value = 0;
746
747 if (status & I2SR_IAL) { /* Arbitration lost */
748 i2c_imx_clear_irq(i2c_imx, I2SR_IAL);
749 if (!(status & I2SR_IAAS))
750 return IRQ_HANDLED;
751 }
752
753 if (!(status & I2SR_IBB)) {
754 /* No master on the bus, that could mean a stop condition. */
755 i2c_imx_slave_finish_op(i2c_imx);
756 return IRQ_HANDLED;
757 }
758
759 if (!(status & I2SR_ICF))
760 /* Data transfer still in progress, ignore this. */
761 goto out;
762
763 if (status & I2SR_IAAS) { /* Addressed as a slave */
764 i2c_imx_slave_finish_op(i2c_imx);
765 if (status & I2SR_SRW) { /* Master wants to read from us*/
766 dev_dbg(&i2c_imx->adapter.dev, "read requested");
767 i2c_imx_slave_event(i2c_imx,
768 I2C_SLAVE_READ_REQUESTED, &value);
769
770 /* Slave transmit */
771 ctl |= I2CR_MTX;
772 imx_i2c_write_reg(ctl, i2c_imx, IMX_I2C_I2CR);
773
774 /* Send data */
775 imx_i2c_write_reg(value, i2c_imx, IMX_I2C_I2DR);
776 } else { /* Master wants to write to us */
777 dev_dbg(&i2c_imx->adapter.dev, "write requested");
778 i2c_imx_slave_event(i2c_imx,
779 I2C_SLAVE_WRITE_REQUESTED, &value);
780
781 /* Slave receive */
782 ctl &= ~I2CR_MTX;
783 imx_i2c_write_reg(ctl, i2c_imx, IMX_I2C_I2CR);
784 /* Dummy read */
785 imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR);
786 }
787 } else if (!(ctl & I2CR_MTX)) { /* Receive mode */
788 value = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR);
789 i2c_imx_slave_event(i2c_imx,
790 I2C_SLAVE_WRITE_RECEIVED, &value);
791 } else if (!(status & I2SR_RXAK)) { /* Transmit mode received ACK */
792 ctl |= I2CR_MTX;
793 imx_i2c_write_reg(ctl, i2c_imx, IMX_I2C_I2CR);
794
795 i2c_imx_slave_event(i2c_imx,
796 I2C_SLAVE_READ_PROCESSED, &value);
797
798 imx_i2c_write_reg(value, i2c_imx, IMX_I2C_I2DR);
799 } else { /* Transmit mode received NAK, operation is done */
800 ctl &= ~I2CR_MTX;
801 imx_i2c_write_reg(ctl, i2c_imx, IMX_I2C_I2CR);
802 imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR);
803
804 /* flag the last byte as processed */
805 i2c_imx_slave_event(i2c_imx,
806 I2C_SLAVE_READ_PROCESSED, &value);
807
808 i2c_imx_slave_finish_op(i2c_imx);
809 return IRQ_HANDLED;
810 }
811
812 out:
813 /*
814 * No need to check the return value here. If it returns 0 or
815 * 1, then everything is fine. If it returns -1, then the
816 * timer is running in the handler. This will still work,
817 * though it may be redone (or already have been done) by the
818 * timer function.
819 */
820 hrtimer_try_to_cancel(&i2c_imx->slave_timer);
821 hrtimer_forward_now(&i2c_imx->slave_timer, I2C_IMX_CHECK_DELAY);
822 hrtimer_restart(&i2c_imx->slave_timer);
823 return IRQ_HANDLED;
824 }
825
i2c_imx_slave_timeout(struct hrtimer * t)826 static enum hrtimer_restart i2c_imx_slave_timeout(struct hrtimer *t)
827 {
828 struct imx_i2c_struct *i2c_imx = container_of(t, struct imx_i2c_struct,
829 slave_timer);
830 unsigned int ctl, status;
831 unsigned long flags;
832
833 spin_lock_irqsave(&i2c_imx->slave_lock, flags);
834 status = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR);
835 ctl = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
836 i2c_imx_slave_handle(i2c_imx, status, ctl);
837 spin_unlock_irqrestore(&i2c_imx->slave_lock, flags);
838 return HRTIMER_NORESTART;
839 }
840
i2c_imx_slave_init(struct imx_i2c_struct * i2c_imx)841 static void i2c_imx_slave_init(struct imx_i2c_struct *i2c_imx)
842 {
843 int temp;
844
845 /* Set slave addr. */
846 imx_i2c_write_reg((i2c_imx->slave->addr << 1), i2c_imx, IMX_I2C_IADR);
847
848 i2c_imx_reset_regs(i2c_imx);
849
850 /* Enable module */
851 temp = i2c_imx->hwdata->i2cr_ien_opcode;
852 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
853
854 /* Enable interrupt from i2c module */
855 temp |= I2CR_IIEN;
856 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
857
858 i2c_imx_enable_bus_idle(i2c_imx);
859 }
860
i2c_imx_reg_slave(struct i2c_client * client)861 static int i2c_imx_reg_slave(struct i2c_client *client)
862 {
863 struct imx_i2c_struct *i2c_imx = i2c_get_adapdata(client->adapter);
864 int ret;
865
866 if (i2c_imx->slave)
867 return -EBUSY;
868
869 i2c_imx->slave = client;
870 i2c_imx->last_slave_event = I2C_SLAVE_STOP;
871
872 /* Resume */
873 ret = pm_runtime_resume_and_get(i2c_imx->adapter.dev.parent);
874 if (ret < 0) {
875 dev_err(&i2c_imx->adapter.dev, "failed to resume i2c controller");
876 return ret;
877 }
878
879 i2c_imx_slave_init(i2c_imx);
880
881 return 0;
882 }
883
i2c_imx_unreg_slave(struct i2c_client * client)884 static int i2c_imx_unreg_slave(struct i2c_client *client)
885 {
886 struct imx_i2c_struct *i2c_imx = i2c_get_adapdata(client->adapter);
887 int ret;
888
889 if (!i2c_imx->slave)
890 return -EINVAL;
891
892 /* Reset slave address. */
893 imx_i2c_write_reg(0, i2c_imx, IMX_I2C_IADR);
894
895 i2c_imx_reset_regs(i2c_imx);
896
897 i2c_imx->slave = NULL;
898
899 /* Suspend */
900 ret = pm_runtime_put_sync(i2c_imx->adapter.dev.parent);
901 if (ret < 0)
902 dev_err(&i2c_imx->adapter.dev, "failed to suspend i2c controller");
903
904 return ret;
905 }
906
i2c_imx_master_isr(struct imx_i2c_struct * i2c_imx,unsigned int status)907 static irqreturn_t i2c_imx_master_isr(struct imx_i2c_struct *i2c_imx, unsigned int status)
908 {
909 /* save status register */
910 i2c_imx->i2csr = status;
911 wake_up(&i2c_imx->queue);
912
913 return IRQ_HANDLED;
914 }
915
i2c_imx_isr(int irq,void * dev_id)916 static irqreturn_t i2c_imx_isr(int irq, void *dev_id)
917 {
918 struct imx_i2c_struct *i2c_imx = dev_id;
919 unsigned int ctl, status;
920 unsigned long flags;
921
922 spin_lock_irqsave(&i2c_imx->slave_lock, flags);
923 status = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR);
924 ctl = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
925
926 if (status & I2SR_IIF) {
927 i2c_imx_clear_irq(i2c_imx, I2SR_IIF);
928 if (i2c_imx->slave) {
929 if (!(ctl & I2CR_MSTA)) {
930 irqreturn_t ret;
931
932 ret = i2c_imx_slave_handle(i2c_imx,
933 status, ctl);
934 spin_unlock_irqrestore(&i2c_imx->slave_lock,
935 flags);
936 return ret;
937 }
938 i2c_imx_slave_finish_op(i2c_imx);
939 }
940 spin_unlock_irqrestore(&i2c_imx->slave_lock, flags);
941 return i2c_imx_master_isr(i2c_imx, status);
942 }
943 spin_unlock_irqrestore(&i2c_imx->slave_lock, flags);
944
945 return IRQ_NONE;
946 }
947
i2c_imx_dma_write(struct imx_i2c_struct * i2c_imx,struct i2c_msg * msgs)948 static int i2c_imx_dma_write(struct imx_i2c_struct *i2c_imx,
949 struct i2c_msg *msgs)
950 {
951 int result;
952 unsigned long time_left;
953 unsigned int temp = 0;
954 unsigned long orig_jiffies = jiffies;
955 struct imx_i2c_dma *dma = i2c_imx->dma;
956 struct device *dev = &i2c_imx->adapter.dev;
957
958 dma->chan_using = dma->chan_tx;
959 dma->dma_transfer_dir = DMA_MEM_TO_DEV;
960 dma->dma_data_dir = DMA_TO_DEVICE;
961 dma->dma_len = msgs->len - 1;
962 result = i2c_imx_dma_xfer(i2c_imx, msgs);
963 if (result)
964 return result;
965
966 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
967 temp |= I2CR_DMAEN;
968 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
969
970 /*
971 * Write slave address.
972 * The first byte must be transmitted by the CPU.
973 */
974 imx_i2c_write_reg(i2c_8bit_addr_from_msg(msgs), i2c_imx, IMX_I2C_I2DR);
975 time_left = wait_for_completion_timeout(
976 &i2c_imx->dma->cmd_complete,
977 msecs_to_jiffies(DMA_TIMEOUT));
978 if (time_left == 0) {
979 dmaengine_terminate_sync(dma->chan_using);
980 return -ETIMEDOUT;
981 }
982
983 /* Waiting for transfer complete. */
984 while (1) {
985 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR);
986 if (temp & I2SR_ICF)
987 break;
988 if (time_after(jiffies, orig_jiffies +
989 msecs_to_jiffies(DMA_TIMEOUT))) {
990 dev_dbg(dev, "<%s> Timeout\n", __func__);
991 return -ETIMEDOUT;
992 }
993 schedule();
994 }
995
996 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
997 temp &= ~I2CR_DMAEN;
998 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
999
1000 /* The last data byte must be transferred by the CPU. */
1001 imx_i2c_write_reg(msgs->buf[msgs->len-1],
1002 i2c_imx, IMX_I2C_I2DR);
1003 result = i2c_imx_trx_complete(i2c_imx, false);
1004 if (result)
1005 return result;
1006
1007 return i2c_imx_acked(i2c_imx);
1008 }
1009
i2c_imx_dma_read(struct imx_i2c_struct * i2c_imx,struct i2c_msg * msgs,bool is_lastmsg)1010 static int i2c_imx_dma_read(struct imx_i2c_struct *i2c_imx,
1011 struct i2c_msg *msgs, bool is_lastmsg)
1012 {
1013 int result;
1014 unsigned long time_left;
1015 unsigned int temp;
1016 unsigned long orig_jiffies = jiffies;
1017 struct imx_i2c_dma *dma = i2c_imx->dma;
1018 struct device *dev = &i2c_imx->adapter.dev;
1019
1020
1021 dma->chan_using = dma->chan_rx;
1022 dma->dma_transfer_dir = DMA_DEV_TO_MEM;
1023 dma->dma_data_dir = DMA_FROM_DEVICE;
1024 /* The last two data bytes must be transferred by the CPU. */
1025 dma->dma_len = msgs->len - 2;
1026 result = i2c_imx_dma_xfer(i2c_imx, msgs);
1027 if (result)
1028 return result;
1029
1030 time_left = wait_for_completion_timeout(
1031 &i2c_imx->dma->cmd_complete,
1032 msecs_to_jiffies(DMA_TIMEOUT));
1033 if (time_left == 0) {
1034 dmaengine_terminate_sync(dma->chan_using);
1035 return -ETIMEDOUT;
1036 }
1037
1038 /* waiting for transfer complete. */
1039 while (1) {
1040 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR);
1041 if (temp & I2SR_ICF)
1042 break;
1043 if (time_after(jiffies, orig_jiffies +
1044 msecs_to_jiffies(DMA_TIMEOUT))) {
1045 dev_dbg(dev, "<%s> Timeout\n", __func__);
1046 return -ETIMEDOUT;
1047 }
1048 schedule();
1049 }
1050
1051 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
1052 temp &= ~I2CR_DMAEN;
1053 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
1054
1055 /* read n-1 byte data */
1056 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
1057 temp |= I2CR_TXAK;
1058 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
1059
1060 msgs->buf[msgs->len-2] = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR);
1061 /* read n byte data */
1062 result = i2c_imx_trx_complete(i2c_imx, false);
1063 if (result)
1064 return result;
1065
1066 if (is_lastmsg) {
1067 /*
1068 * It must generate STOP before read I2DR to prevent
1069 * controller from generating another clock cycle
1070 */
1071 dev_dbg(dev, "<%s> clear MSTA\n", __func__);
1072 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
1073 if (!(temp & I2CR_MSTA))
1074 i2c_imx->stopped = 1;
1075 temp &= ~(I2CR_MSTA | I2CR_MTX);
1076 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
1077 if (!i2c_imx->stopped)
1078 i2c_imx_bus_busy(i2c_imx, 0, false);
1079 } else {
1080 /*
1081 * For i2c master receiver repeat restart operation like:
1082 * read -> repeat MSTA -> read/write
1083 * The controller must set MTX before read the last byte in
1084 * the first read operation, otherwise the first read cost
1085 * one extra clock cycle.
1086 */
1087 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
1088 temp |= I2CR_MTX;
1089 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
1090 }
1091 msgs->buf[msgs->len-1] = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR);
1092
1093 return 0;
1094 }
1095
i2c_imx_write(struct imx_i2c_struct * i2c_imx,struct i2c_msg * msgs,bool atomic)1096 static int i2c_imx_write(struct imx_i2c_struct *i2c_imx, struct i2c_msg *msgs,
1097 bool atomic)
1098 {
1099 int i, result;
1100
1101 dev_dbg(&i2c_imx->adapter.dev, "<%s> write slave address: addr=0x%x\n",
1102 __func__, i2c_8bit_addr_from_msg(msgs));
1103
1104 /* write slave address */
1105 imx_i2c_write_reg(i2c_8bit_addr_from_msg(msgs), i2c_imx, IMX_I2C_I2DR);
1106 result = i2c_imx_trx_complete(i2c_imx, atomic);
1107 if (result)
1108 return result;
1109 result = i2c_imx_acked(i2c_imx);
1110 if (result)
1111 return result;
1112 dev_dbg(&i2c_imx->adapter.dev, "<%s> write data\n", __func__);
1113
1114 /* write data */
1115 for (i = 0; i < msgs->len; i++) {
1116 dev_dbg(&i2c_imx->adapter.dev,
1117 "<%s> write byte: B%d=0x%X\n",
1118 __func__, i, msgs->buf[i]);
1119 imx_i2c_write_reg(msgs->buf[i], i2c_imx, IMX_I2C_I2DR);
1120 result = i2c_imx_trx_complete(i2c_imx, atomic);
1121 if (result)
1122 return result;
1123 result = i2c_imx_acked(i2c_imx);
1124 if (result)
1125 return result;
1126 }
1127 return 0;
1128 }
1129
i2c_imx_read(struct imx_i2c_struct * i2c_imx,struct i2c_msg * msgs,bool is_lastmsg,bool atomic)1130 static int i2c_imx_read(struct imx_i2c_struct *i2c_imx, struct i2c_msg *msgs,
1131 bool is_lastmsg, bool atomic)
1132 {
1133 int i, result;
1134 unsigned int temp;
1135 int block_data = msgs->flags & I2C_M_RECV_LEN;
1136 int use_dma = i2c_imx->dma && msgs->flags & I2C_M_DMA_SAFE &&
1137 msgs->len >= DMA_THRESHOLD && !block_data;
1138
1139 dev_dbg(&i2c_imx->adapter.dev,
1140 "<%s> write slave address: addr=0x%x\n",
1141 __func__, i2c_8bit_addr_from_msg(msgs));
1142
1143 /* write slave address */
1144 imx_i2c_write_reg(i2c_8bit_addr_from_msg(msgs), i2c_imx, IMX_I2C_I2DR);
1145 result = i2c_imx_trx_complete(i2c_imx, atomic);
1146 if (result)
1147 return result;
1148 result = i2c_imx_acked(i2c_imx);
1149 if (result)
1150 return result;
1151
1152 dev_dbg(&i2c_imx->adapter.dev, "<%s> setup bus\n", __func__);
1153
1154 /* setup bus to read data */
1155 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
1156 temp &= ~I2CR_MTX;
1157
1158 /*
1159 * Reset the I2CR_TXAK flag initially for SMBus block read since the
1160 * length is unknown
1161 */
1162 if ((msgs->len - 1) || block_data)
1163 temp &= ~I2CR_TXAK;
1164 if (use_dma)
1165 temp |= I2CR_DMAEN;
1166 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
1167 imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR); /* dummy read */
1168
1169 dev_dbg(&i2c_imx->adapter.dev, "<%s> read data\n", __func__);
1170
1171 if (use_dma)
1172 return i2c_imx_dma_read(i2c_imx, msgs, is_lastmsg);
1173
1174 /* read data */
1175 for (i = 0; i < msgs->len; i++) {
1176 u8 len = 0;
1177
1178 result = i2c_imx_trx_complete(i2c_imx, atomic);
1179 if (result)
1180 return result;
1181 /*
1182 * First byte is the length of remaining packet
1183 * in the SMBus block data read. Add it to
1184 * msgs->len.
1185 */
1186 if ((!i) && block_data) {
1187 len = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR);
1188 if ((len == 0) || (len > I2C_SMBUS_BLOCK_MAX))
1189 return -EPROTO;
1190 dev_dbg(&i2c_imx->adapter.dev,
1191 "<%s> read length: 0x%X\n",
1192 __func__, len);
1193 msgs->len += len;
1194 }
1195 if (i == (msgs->len - 1)) {
1196 if (is_lastmsg) {
1197 /*
1198 * It must generate STOP before read I2DR to prevent
1199 * controller from generating another clock cycle
1200 */
1201 dev_dbg(&i2c_imx->adapter.dev,
1202 "<%s> clear MSTA\n", __func__);
1203 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
1204 if (!(temp & I2CR_MSTA))
1205 i2c_imx->stopped = 1;
1206 temp &= ~(I2CR_MSTA | I2CR_MTX);
1207 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
1208 if (!i2c_imx->stopped)
1209 i2c_imx_bus_busy(i2c_imx, 0, atomic);
1210 } else {
1211 /*
1212 * For i2c master receiver repeat restart operation like:
1213 * read -> repeat MSTA -> read/write
1214 * The controller must set MTX before read the last byte in
1215 * the first read operation, otherwise the first read cost
1216 * one extra clock cycle.
1217 */
1218 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
1219 temp |= I2CR_MTX;
1220 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
1221 }
1222 } else if (i == (msgs->len - 2)) {
1223 dev_dbg(&i2c_imx->adapter.dev,
1224 "<%s> set TXAK\n", __func__);
1225 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
1226 temp |= I2CR_TXAK;
1227 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
1228 }
1229 if ((!i) && block_data)
1230 msgs->buf[0] = len;
1231 else
1232 msgs->buf[i] = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR);
1233 dev_dbg(&i2c_imx->adapter.dev,
1234 "<%s> read byte: B%d=0x%X\n",
1235 __func__, i, msgs->buf[i]);
1236 }
1237 return 0;
1238 }
1239
i2c_imx_xfer_common(struct i2c_adapter * adapter,struct i2c_msg * msgs,int num,bool atomic)1240 static int i2c_imx_xfer_common(struct i2c_adapter *adapter,
1241 struct i2c_msg *msgs, int num, bool atomic)
1242 {
1243 unsigned int i, temp;
1244 int result;
1245 bool is_lastmsg = false;
1246 struct imx_i2c_struct *i2c_imx = i2c_get_adapdata(adapter);
1247
1248 /* Start I2C transfer */
1249 result = i2c_imx_start(i2c_imx, atomic);
1250 if (result) {
1251 /*
1252 * Bus recovery uses gpiod_get_value_cansleep() which is not
1253 * allowed within atomic context.
1254 */
1255 if (!atomic && i2c_imx->adapter.bus_recovery_info) {
1256 i2c_recover_bus(&i2c_imx->adapter);
1257 result = i2c_imx_start(i2c_imx, atomic);
1258 }
1259 }
1260
1261 if (result)
1262 goto fail0;
1263
1264 /* read/write data */
1265 for (i = 0; i < num; i++) {
1266 if (i == num - 1)
1267 is_lastmsg = true;
1268
1269 if (i) {
1270 dev_dbg(&i2c_imx->adapter.dev,
1271 "<%s> repeated start\n", __func__);
1272 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
1273 temp |= I2CR_RSTA;
1274 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
1275 result = i2c_imx_bus_busy(i2c_imx, 1, atomic);
1276 if (result)
1277 goto fail0;
1278 }
1279 dev_dbg(&i2c_imx->adapter.dev,
1280 "<%s> transfer message: %d\n", __func__, i);
1281 /* write/read data */
1282 #ifdef CONFIG_I2C_DEBUG_BUS
1283 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
1284 dev_dbg(&i2c_imx->adapter.dev,
1285 "<%s> CONTROL: IEN=%d, IIEN=%d, MSTA=%d, MTX=%d, TXAK=%d, RSTA=%d\n",
1286 __func__,
1287 (temp & I2CR_IEN ? 1 : 0), (temp & I2CR_IIEN ? 1 : 0),
1288 (temp & I2CR_MSTA ? 1 : 0), (temp & I2CR_MTX ? 1 : 0),
1289 (temp & I2CR_TXAK ? 1 : 0), (temp & I2CR_RSTA ? 1 : 0));
1290 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR);
1291 dev_dbg(&i2c_imx->adapter.dev,
1292 "<%s> STATUS: ICF=%d, IAAS=%d, IBB=%d, IAL=%d, SRW=%d, IIF=%d, RXAK=%d\n",
1293 __func__,
1294 (temp & I2SR_ICF ? 1 : 0), (temp & I2SR_IAAS ? 1 : 0),
1295 (temp & I2SR_IBB ? 1 : 0), (temp & I2SR_IAL ? 1 : 0),
1296 (temp & I2SR_SRW ? 1 : 0), (temp & I2SR_IIF ? 1 : 0),
1297 (temp & I2SR_RXAK ? 1 : 0));
1298 #endif
1299 if (msgs[i].flags & I2C_M_RD) {
1300 result = i2c_imx_read(i2c_imx, &msgs[i], is_lastmsg, atomic);
1301 } else {
1302 if (!atomic &&
1303 i2c_imx->dma && msgs[i].len >= DMA_THRESHOLD &&
1304 msgs[i].flags & I2C_M_DMA_SAFE)
1305 result = i2c_imx_dma_write(i2c_imx, &msgs[i]);
1306 else
1307 result = i2c_imx_write(i2c_imx, &msgs[i], atomic);
1308 }
1309 if (result)
1310 goto fail0;
1311 }
1312
1313 fail0:
1314 /* Stop I2C transfer */
1315 i2c_imx_stop(i2c_imx, atomic);
1316
1317 dev_dbg(&i2c_imx->adapter.dev, "<%s> exit with: %s: %d\n", __func__,
1318 (result < 0) ? "error" : "success msg",
1319 (result < 0) ? result : num);
1320 /* After data is transferred, switch to slave mode(as a receiver) */
1321 if (i2c_imx->slave)
1322 i2c_imx_slave_init(i2c_imx);
1323
1324 return (result < 0) ? result : num;
1325 }
1326
i2c_imx_xfer(struct i2c_adapter * adapter,struct i2c_msg * msgs,int num)1327 static int i2c_imx_xfer(struct i2c_adapter *adapter,
1328 struct i2c_msg *msgs, int num)
1329 {
1330 struct imx_i2c_struct *i2c_imx = i2c_get_adapdata(adapter);
1331 int result;
1332
1333 result = pm_runtime_resume_and_get(i2c_imx->adapter.dev.parent);
1334 if (result < 0)
1335 return result;
1336
1337 result = i2c_imx_xfer_common(adapter, msgs, num, false);
1338
1339 pm_runtime_mark_last_busy(i2c_imx->adapter.dev.parent);
1340 pm_runtime_put_autosuspend(i2c_imx->adapter.dev.parent);
1341
1342 return result;
1343 }
1344
i2c_imx_xfer_atomic(struct i2c_adapter * adapter,struct i2c_msg * msgs,int num)1345 static int i2c_imx_xfer_atomic(struct i2c_adapter *adapter,
1346 struct i2c_msg *msgs, int num)
1347 {
1348 struct imx_i2c_struct *i2c_imx = i2c_get_adapdata(adapter);
1349 int result;
1350
1351 result = clk_enable(i2c_imx->clk);
1352 if (result)
1353 return result;
1354
1355 result = i2c_imx_xfer_common(adapter, msgs, num, true);
1356
1357 clk_disable(i2c_imx->clk);
1358
1359 return result;
1360 }
1361
1362 /*
1363 * We switch SCL and SDA to their GPIO function and do some bitbanging
1364 * for bus recovery. These alternative pinmux settings can be
1365 * described in the device tree by a separate pinctrl state "gpio". If
1366 * this is missing this is not a big problem, the only implication is
1367 * that we can't do bus recovery.
1368 */
i2c_imx_init_recovery_info(struct imx_i2c_struct * i2c_imx,struct platform_device * pdev)1369 static int i2c_imx_init_recovery_info(struct imx_i2c_struct *i2c_imx,
1370 struct platform_device *pdev)
1371 {
1372 struct i2c_bus_recovery_info *bri = &i2c_imx->rinfo;
1373
1374 bri->pinctrl = devm_pinctrl_get(&pdev->dev);
1375 if (IS_ERR(bri->pinctrl))
1376 return PTR_ERR(bri->pinctrl);
1377
1378 i2c_imx->adapter.bus_recovery_info = bri;
1379
1380 return 0;
1381 }
1382
i2c_imx_func(struct i2c_adapter * adapter)1383 static u32 i2c_imx_func(struct i2c_adapter *adapter)
1384 {
1385 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL
1386 | I2C_FUNC_SMBUS_READ_BLOCK_DATA;
1387 }
1388
1389 static const struct i2c_algorithm i2c_imx_algo = {
1390 .master_xfer = i2c_imx_xfer,
1391 .master_xfer_atomic = i2c_imx_xfer_atomic,
1392 .functionality = i2c_imx_func,
1393 .reg_slave = i2c_imx_reg_slave,
1394 .unreg_slave = i2c_imx_unreg_slave,
1395 };
1396
i2c_imx_probe(struct platform_device * pdev)1397 static int i2c_imx_probe(struct platform_device *pdev)
1398 {
1399 struct imx_i2c_struct *i2c_imx;
1400 struct resource *res;
1401 struct imxi2c_platform_data *pdata = dev_get_platdata(&pdev->dev);
1402 void __iomem *base;
1403 int irq, ret;
1404 dma_addr_t phy_addr;
1405 const struct imx_i2c_hwdata *match;
1406
1407 irq = platform_get_irq(pdev, 0);
1408 if (irq < 0)
1409 return irq;
1410
1411 base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
1412 if (IS_ERR(base))
1413 return PTR_ERR(base);
1414
1415 phy_addr = (dma_addr_t)res->start;
1416 i2c_imx = devm_kzalloc(&pdev->dev, sizeof(*i2c_imx), GFP_KERNEL);
1417 if (!i2c_imx)
1418 return -ENOMEM;
1419
1420 spin_lock_init(&i2c_imx->slave_lock);
1421 hrtimer_init(&i2c_imx->slave_timer, CLOCK_MONOTONIC, HRTIMER_MODE_ABS);
1422 i2c_imx->slave_timer.function = i2c_imx_slave_timeout;
1423
1424 match = device_get_match_data(&pdev->dev);
1425 if (match)
1426 i2c_imx->hwdata = match;
1427 else
1428 i2c_imx->hwdata = (struct imx_i2c_hwdata *)
1429 platform_get_device_id(pdev)->driver_data;
1430
1431 /* Setup i2c_imx driver structure */
1432 strscpy(i2c_imx->adapter.name, pdev->name, sizeof(i2c_imx->adapter.name));
1433 i2c_imx->adapter.owner = THIS_MODULE;
1434 i2c_imx->adapter.algo = &i2c_imx_algo;
1435 i2c_imx->adapter.dev.parent = &pdev->dev;
1436 i2c_imx->adapter.nr = pdev->id;
1437 i2c_imx->adapter.dev.of_node = pdev->dev.of_node;
1438 i2c_imx->base = base;
1439 ACPI_COMPANION_SET(&i2c_imx->adapter.dev, ACPI_COMPANION(&pdev->dev));
1440
1441 /* Get I2C clock */
1442 i2c_imx->clk = devm_clk_get_enabled(&pdev->dev, NULL);
1443 if (IS_ERR(i2c_imx->clk))
1444 return dev_err_probe(&pdev->dev, PTR_ERR(i2c_imx->clk),
1445 "can't get I2C clock\n");
1446
1447 /* Init queue */
1448 init_waitqueue_head(&i2c_imx->queue);
1449
1450 /* Set up adapter data */
1451 i2c_set_adapdata(&i2c_imx->adapter, i2c_imx);
1452
1453 /* Set up platform driver data */
1454 platform_set_drvdata(pdev, i2c_imx);
1455
1456 pm_runtime_set_autosuspend_delay(&pdev->dev, I2C_PM_TIMEOUT);
1457 pm_runtime_use_autosuspend(&pdev->dev);
1458 pm_runtime_set_active(&pdev->dev);
1459 pm_runtime_enable(&pdev->dev);
1460
1461 ret = pm_runtime_get_sync(&pdev->dev);
1462 if (ret < 0)
1463 goto rpm_disable;
1464
1465 /* Request IRQ */
1466 ret = request_irq(irq, i2c_imx_isr, IRQF_SHARED, pdev->name, i2c_imx);
1467 if (ret) {
1468 dev_err(&pdev->dev, "can't claim irq %d\n", irq);
1469 goto rpm_disable;
1470 }
1471
1472 /* Set up clock divider */
1473 i2c_imx->bitrate = I2C_MAX_STANDARD_MODE_FREQ;
1474 ret = of_property_read_u32(pdev->dev.of_node,
1475 "clock-frequency", &i2c_imx->bitrate);
1476 if (ret < 0 && pdata && pdata->bitrate)
1477 i2c_imx->bitrate = pdata->bitrate;
1478 i2c_imx->clk_change_nb.notifier_call = i2c_imx_clk_notifier_call;
1479 clk_notifier_register(i2c_imx->clk, &i2c_imx->clk_change_nb);
1480 i2c_imx_set_clk(i2c_imx, clk_get_rate(i2c_imx->clk));
1481
1482 i2c_imx_reset_regs(i2c_imx);
1483
1484 /* Init optional bus recovery function */
1485 ret = i2c_imx_init_recovery_info(i2c_imx, pdev);
1486 /* Give it another chance if pinctrl used is not ready yet */
1487 if (ret == -EPROBE_DEFER)
1488 goto clk_notifier_unregister;
1489
1490 /* Add I2C adapter */
1491 ret = i2c_add_numbered_adapter(&i2c_imx->adapter);
1492 if (ret < 0)
1493 goto clk_notifier_unregister;
1494
1495 pm_runtime_mark_last_busy(&pdev->dev);
1496 pm_runtime_put_autosuspend(&pdev->dev);
1497
1498 dev_dbg(&i2c_imx->adapter.dev, "claimed irq %d\n", irq);
1499 dev_dbg(&i2c_imx->adapter.dev, "device resources: %pR\n", res);
1500 dev_dbg(&i2c_imx->adapter.dev, "adapter name: \"%s\"\n",
1501 i2c_imx->adapter.name);
1502 dev_info(&i2c_imx->adapter.dev, "IMX I2C adapter registered\n");
1503
1504 /* Init DMA config if supported */
1505 i2c_imx_dma_request(i2c_imx, phy_addr);
1506
1507 return 0; /* Return OK */
1508
1509 clk_notifier_unregister:
1510 clk_notifier_unregister(i2c_imx->clk, &i2c_imx->clk_change_nb);
1511 free_irq(irq, i2c_imx);
1512 rpm_disable:
1513 pm_runtime_put_noidle(&pdev->dev);
1514 pm_runtime_disable(&pdev->dev);
1515 pm_runtime_set_suspended(&pdev->dev);
1516 pm_runtime_dont_use_autosuspend(&pdev->dev);
1517 return ret;
1518 }
1519
i2c_imx_remove(struct platform_device * pdev)1520 static void i2c_imx_remove(struct platform_device *pdev)
1521 {
1522 struct imx_i2c_struct *i2c_imx = platform_get_drvdata(pdev);
1523 int irq, ret;
1524
1525 ret = pm_runtime_get_sync(&pdev->dev);
1526
1527 hrtimer_cancel(&i2c_imx->slave_timer);
1528
1529 /* remove adapter */
1530 dev_dbg(&i2c_imx->adapter.dev, "adapter removed\n");
1531 i2c_del_adapter(&i2c_imx->adapter);
1532
1533 if (i2c_imx->dma)
1534 i2c_imx_dma_free(i2c_imx);
1535
1536 if (ret >= 0) {
1537 /* setup chip registers to defaults */
1538 imx_i2c_write_reg(0, i2c_imx, IMX_I2C_IADR);
1539 imx_i2c_write_reg(0, i2c_imx, IMX_I2C_IFDR);
1540 imx_i2c_write_reg(0, i2c_imx, IMX_I2C_I2CR);
1541 imx_i2c_write_reg(0, i2c_imx, IMX_I2C_I2SR);
1542 }
1543
1544 clk_notifier_unregister(i2c_imx->clk, &i2c_imx->clk_change_nb);
1545 irq = platform_get_irq(pdev, 0);
1546 if (irq >= 0)
1547 free_irq(irq, i2c_imx);
1548
1549 pm_runtime_put_noidle(&pdev->dev);
1550 pm_runtime_disable(&pdev->dev);
1551 }
1552
i2c_imx_runtime_suspend(struct device * dev)1553 static int i2c_imx_runtime_suspend(struct device *dev)
1554 {
1555 struct imx_i2c_struct *i2c_imx = dev_get_drvdata(dev);
1556
1557 clk_disable(i2c_imx->clk);
1558
1559 return 0;
1560 }
1561
i2c_imx_runtime_resume(struct device * dev)1562 static int i2c_imx_runtime_resume(struct device *dev)
1563 {
1564 struct imx_i2c_struct *i2c_imx = dev_get_drvdata(dev);
1565 int ret;
1566
1567 ret = clk_enable(i2c_imx->clk);
1568 if (ret)
1569 dev_err(dev, "can't enable I2C clock, ret=%d\n", ret);
1570
1571 return ret;
1572 }
1573
1574 static const struct dev_pm_ops i2c_imx_pm_ops = {
1575 RUNTIME_PM_OPS(i2c_imx_runtime_suspend, i2c_imx_runtime_resume, NULL)
1576 };
1577
1578 static struct platform_driver i2c_imx_driver = {
1579 .probe = i2c_imx_probe,
1580 .remove_new = i2c_imx_remove,
1581 .driver = {
1582 .name = DRIVER_NAME,
1583 .pm = pm_ptr(&i2c_imx_pm_ops),
1584 .of_match_table = i2c_imx_dt_ids,
1585 .acpi_match_table = i2c_imx_acpi_ids,
1586 },
1587 .id_table = imx_i2c_devtype,
1588 };
1589
i2c_adap_imx_init(void)1590 static int __init i2c_adap_imx_init(void)
1591 {
1592 return platform_driver_register(&i2c_imx_driver);
1593 }
1594 subsys_initcall(i2c_adap_imx_init);
1595
i2c_adap_imx_exit(void)1596 static void __exit i2c_adap_imx_exit(void)
1597 {
1598 platform_driver_unregister(&i2c_imx_driver);
1599 }
1600 module_exit(i2c_adap_imx_exit);
1601
1602 MODULE_LICENSE("GPL");
1603 MODULE_AUTHOR("Darius Augulis");
1604 MODULE_DESCRIPTION("I2C adapter driver for IMX I2C bus");
1605 MODULE_ALIAS("platform:" DRIVER_NAME);
1606