1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Silvaco dual-role I3C master driver
4 *
5 * Copyright (C) 2020 Silvaco
6 * Author: Miquel RAYNAL <miquel.raynal@bootlin.com>
7 * Based on a work from: Conor Culhane <conor.culhane@silvaco.com>
8 */
9
10 #include <linux/bitfield.h>
11 #include <linux/clk.h>
12 #include <linux/completion.h>
13 #include <linux/errno.h>
14 #include <linux/i3c/master.h>
15 #include <linux/interrupt.h>
16 #include <linux/iopoll.h>
17 #include <linux/list.h>
18 #include <linux/module.h>
19 #include <linux/of.h>
20 #include <linux/pinctrl/consumer.h>
21 #include <linux/platform_device.h>
22 #include <linux/pm_runtime.h>
23
24 /* Master Mode Registers */
25 #define SVC_I3C_MCONFIG 0x000
26 #define SVC_I3C_MCONFIG_MASTER_EN BIT(0)
27 #define SVC_I3C_MCONFIG_DISTO(x) FIELD_PREP(BIT(3), (x))
28 #define SVC_I3C_MCONFIG_HKEEP(x) FIELD_PREP(GENMASK(5, 4), (x))
29 #define SVC_I3C_MCONFIG_ODSTOP(x) FIELD_PREP(BIT(6), (x))
30 #define SVC_I3C_MCONFIG_PPBAUD(x) FIELD_PREP(GENMASK(11, 8), (x))
31 #define SVC_I3C_MCONFIG_PPLOW(x) FIELD_PREP(GENMASK(15, 12), (x))
32 #define SVC_I3C_MCONFIG_ODBAUD(x) FIELD_PREP(GENMASK(23, 16), (x))
33 #define SVC_I3C_MCONFIG_ODHPP(x) FIELD_PREP(BIT(24), (x))
34 #define SVC_I3C_MCONFIG_SKEW(x) FIELD_PREP(GENMASK(27, 25), (x))
35 #define SVC_I3C_MCONFIG_I2CBAUD(x) FIELD_PREP(GENMASK(31, 28), (x))
36
37 #define SVC_I3C_MCTRL 0x084
38 #define SVC_I3C_MCTRL_REQUEST_MASK GENMASK(2, 0)
39 #define SVC_I3C_MCTRL_REQUEST_NONE 0
40 #define SVC_I3C_MCTRL_REQUEST_START_ADDR 1
41 #define SVC_I3C_MCTRL_REQUEST_STOP 2
42 #define SVC_I3C_MCTRL_REQUEST_IBI_ACKNACK 3
43 #define SVC_I3C_MCTRL_REQUEST_PROC_DAA 4
44 #define SVC_I3C_MCTRL_REQUEST_AUTO_IBI 7
45 #define SVC_I3C_MCTRL_TYPE_I3C 0
46 #define SVC_I3C_MCTRL_TYPE_I2C BIT(4)
47 #define SVC_I3C_MCTRL_IBIRESP_AUTO 0
48 #define SVC_I3C_MCTRL_IBIRESP_ACK_WITHOUT_BYTE 0
49 #define SVC_I3C_MCTRL_IBIRESP_ACK_WITH_BYTE BIT(7)
50 #define SVC_I3C_MCTRL_IBIRESP_NACK BIT(6)
51 #define SVC_I3C_MCTRL_IBIRESP_MANUAL GENMASK(7, 6)
52 #define SVC_I3C_MCTRL_DIR(x) FIELD_PREP(BIT(8), (x))
53 #define SVC_I3C_MCTRL_DIR_WRITE 0
54 #define SVC_I3C_MCTRL_DIR_READ 1
55 #define SVC_I3C_MCTRL_ADDR(x) FIELD_PREP(GENMASK(15, 9), (x))
56 #define SVC_I3C_MCTRL_RDTERM(x) FIELD_PREP(GENMASK(23, 16), (x))
57
58 #define SVC_I3C_MSTATUS 0x088
59 #define SVC_I3C_MSTATUS_STATE(x) FIELD_GET(GENMASK(2, 0), (x))
60 #define SVC_I3C_MSTATUS_STATE_DAA(x) (SVC_I3C_MSTATUS_STATE(x) == 5)
61 #define SVC_I3C_MSTATUS_STATE_IDLE(x) (SVC_I3C_MSTATUS_STATE(x) == 0)
62 #define SVC_I3C_MSTATUS_BETWEEN(x) FIELD_GET(BIT(4), (x))
63 #define SVC_I3C_MSTATUS_NACKED(x) FIELD_GET(BIT(5), (x))
64 #define SVC_I3C_MSTATUS_IBITYPE(x) FIELD_GET(GENMASK(7, 6), (x))
65 #define SVC_I3C_MSTATUS_IBITYPE_IBI 1
66 #define SVC_I3C_MSTATUS_IBITYPE_MASTER_REQUEST 2
67 #define SVC_I3C_MSTATUS_IBITYPE_HOT_JOIN 3
68 #define SVC_I3C_MINT_SLVSTART BIT(8)
69 #define SVC_I3C_MINT_MCTRLDONE BIT(9)
70 #define SVC_I3C_MINT_COMPLETE BIT(10)
71 #define SVC_I3C_MINT_RXPEND BIT(11)
72 #define SVC_I3C_MINT_TXNOTFULL BIT(12)
73 #define SVC_I3C_MINT_IBIWON BIT(13)
74 #define SVC_I3C_MINT_ERRWARN BIT(15)
75 #define SVC_I3C_MSTATUS_SLVSTART(x) FIELD_GET(SVC_I3C_MINT_SLVSTART, (x))
76 #define SVC_I3C_MSTATUS_MCTRLDONE(x) FIELD_GET(SVC_I3C_MINT_MCTRLDONE, (x))
77 #define SVC_I3C_MSTATUS_COMPLETE(x) FIELD_GET(SVC_I3C_MINT_COMPLETE, (x))
78 #define SVC_I3C_MSTATUS_RXPEND(x) FIELD_GET(SVC_I3C_MINT_RXPEND, (x))
79 #define SVC_I3C_MSTATUS_TXNOTFULL(x) FIELD_GET(SVC_I3C_MINT_TXNOTFULL, (x))
80 #define SVC_I3C_MSTATUS_IBIWON(x) FIELD_GET(SVC_I3C_MINT_IBIWON, (x))
81 #define SVC_I3C_MSTATUS_ERRWARN(x) FIELD_GET(SVC_I3C_MINT_ERRWARN, (x))
82 #define SVC_I3C_MSTATUS_IBIADDR(x) FIELD_GET(GENMASK(30, 24), (x))
83
84 #define SVC_I3C_IBIRULES 0x08C
85 #define SVC_I3C_IBIRULES_ADDR(slot, addr) FIELD_PREP(GENMASK(29, 0), \
86 ((addr) & 0x3F) << ((slot) * 6))
87 #define SVC_I3C_IBIRULES_ADDRS 5
88 #define SVC_I3C_IBIRULES_MSB0 BIT(30)
89 #define SVC_I3C_IBIRULES_NOBYTE BIT(31)
90 #define SVC_I3C_IBIRULES_MANDBYTE 0
91 #define SVC_I3C_MINTSET 0x090
92 #define SVC_I3C_MINTCLR 0x094
93 #define SVC_I3C_MINTMASKED 0x098
94 #define SVC_I3C_MERRWARN 0x09C
95 #define SVC_I3C_MERRWARN_NACK BIT(2)
96 #define SVC_I3C_MERRWARN_TIMEOUT BIT(20)
97 #define SVC_I3C_MDMACTRL 0x0A0
98 #define SVC_I3C_MDATACTRL 0x0AC
99 #define SVC_I3C_MDATACTRL_FLUSHTB BIT(0)
100 #define SVC_I3C_MDATACTRL_FLUSHRB BIT(1)
101 #define SVC_I3C_MDATACTRL_UNLOCK_TRIG BIT(3)
102 #define SVC_I3C_MDATACTRL_TXTRIG_FIFO_NOT_FULL GENMASK(5, 4)
103 #define SVC_I3C_MDATACTRL_RXTRIG_FIFO_NOT_EMPTY 0
104 #define SVC_I3C_MDATACTRL_RXCOUNT(x) FIELD_GET(GENMASK(28, 24), (x))
105 #define SVC_I3C_MDATACTRL_TXFULL BIT(30)
106 #define SVC_I3C_MDATACTRL_RXEMPTY BIT(31)
107
108 #define SVC_I3C_MWDATAB 0x0B0
109 #define SVC_I3C_MWDATAB_END BIT(8)
110
111 #define SVC_I3C_MWDATABE 0x0B4
112 #define SVC_I3C_MWDATAH 0x0B8
113 #define SVC_I3C_MWDATAHE 0x0BC
114 #define SVC_I3C_MRDATAB 0x0C0
115 #define SVC_I3C_MRDATAH 0x0C8
116 #define SVC_I3C_MWMSG_SDR 0x0D0
117 #define SVC_I3C_MRMSG_SDR 0x0D4
118 #define SVC_I3C_MWMSG_DDR 0x0D8
119 #define SVC_I3C_MRMSG_DDR 0x0DC
120
121 #define SVC_I3C_MDYNADDR 0x0E4
122 #define SVC_MDYNADDR_VALID BIT(0)
123 #define SVC_MDYNADDR_ADDR(x) FIELD_PREP(GENMASK(7, 1), (x))
124
125 #define SVC_I3C_MAX_DEVS 32
126 #define SVC_I3C_PM_TIMEOUT_MS 1000
127
128 /* This parameter depends on the implementation and may be tuned */
129 #define SVC_I3C_FIFO_SIZE 16
130 #define SVC_I3C_PPBAUD_MAX 15
131 #define SVC_I3C_QUICK_I2C_CLK 4170000
132
133 #define SVC_I3C_EVENT_IBI GENMASK(7, 0)
134 #define SVC_I3C_EVENT_HOTJOIN BIT(31)
135
136 struct svc_i3c_cmd {
137 u8 addr;
138 bool rnw;
139 u8 *in;
140 const void *out;
141 unsigned int len;
142 unsigned int actual_len;
143 struct i3c_priv_xfer *xfer;
144 bool continued;
145 };
146
147 struct svc_i3c_xfer {
148 struct list_head node;
149 struct completion comp;
150 int ret;
151 unsigned int type;
152 unsigned int ncmds;
153 struct svc_i3c_cmd cmds[] __counted_by(ncmds);
154 };
155
156 struct svc_i3c_regs_save {
157 u32 mconfig;
158 u32 mdynaddr;
159 };
160
161 struct svc_i3c_drvdata {
162 u32 quirks;
163 };
164
165 /**
166 * struct svc_i3c_master - Silvaco I3C Master structure
167 * @base: I3C master controller
168 * @dev: Corresponding device
169 * @regs: Memory mapping
170 * @saved_regs: Volatile values for PM operations
171 * @free_slots: Bit array of available slots
172 * @addrs: Array containing the dynamic addresses of each attached device
173 * @descs: Array of descriptors, one per attached device
174 * @hj_work: Hot-join work
175 * @ibi_work: IBI work
176 * @irq: Main interrupt
177 * @pclk: System clock
178 * @fclk: Fast clock (bus)
179 * @sclk: Slow clock (other events)
180 * @xferqueue: Transfer queue structure
181 * @xferqueue.list: List member
182 * @xferqueue.cur: Current ongoing transfer
183 * @xferqueue.lock: Queue lock
184 * @ibi: IBI structure
185 * @ibi.num_slots: Number of slots available in @ibi.slots
186 * @ibi.slots: Available IBI slots
187 * @ibi.tbq_slot: To be queued IBI slot
188 * @ibi.lock: IBI lock
189 * @lock: Transfer lock, protect between IBI work thread and callbacks from master
190 * @drvdata: Driver data
191 * @enabled_events: Bit masks for enable events (IBI, HotJoin).
192 * @mctrl_config: Configuration value in SVC_I3C_MCTRL for setting speed back.
193 */
194 struct svc_i3c_master {
195 struct i3c_master_controller base;
196 struct device *dev;
197 void __iomem *regs;
198 struct svc_i3c_regs_save saved_regs;
199 u32 free_slots;
200 u8 addrs[SVC_I3C_MAX_DEVS];
201 struct i3c_dev_desc *descs[SVC_I3C_MAX_DEVS];
202 struct work_struct hj_work;
203 struct work_struct ibi_work;
204 int irq;
205 struct clk *pclk;
206 struct clk *fclk;
207 struct clk *sclk;
208 struct {
209 struct list_head list;
210 struct svc_i3c_xfer *cur;
211 /* Prevent races between transfers */
212 spinlock_t lock;
213 } xferqueue;
214 struct {
215 unsigned int num_slots;
216 struct i3c_dev_desc **slots;
217 struct i3c_ibi_slot *tbq_slot;
218 /* Prevent races within IBI handlers */
219 spinlock_t lock;
220 } ibi;
221 struct mutex lock;
222 const struct svc_i3c_drvdata *drvdata;
223 u32 enabled_events;
224 u32 mctrl_config;
225 };
226
227 /**
228 * struct svc_i3c_i2c_dev_data - Device specific data
229 * @index: Index in the master tables corresponding to this device
230 * @ibi: IBI slot index in the master structure
231 * @ibi_pool: IBI pool associated to this device
232 */
233 struct svc_i3c_i2c_dev_data {
234 u8 index;
235 int ibi;
236 struct i3c_generic_ibi_pool *ibi_pool;
237 };
238
is_events_enabled(struct svc_i3c_master * master,u32 mask)239 static inline bool is_events_enabled(struct svc_i3c_master *master, u32 mask)
240 {
241 return !!(master->enabled_events & mask);
242 }
243
svc_i3c_master_error(struct svc_i3c_master * master)244 static bool svc_i3c_master_error(struct svc_i3c_master *master)
245 {
246 u32 mstatus, merrwarn;
247
248 mstatus = readl(master->regs + SVC_I3C_MSTATUS);
249 if (SVC_I3C_MSTATUS_ERRWARN(mstatus)) {
250 merrwarn = readl(master->regs + SVC_I3C_MERRWARN);
251 writel(merrwarn, master->regs + SVC_I3C_MERRWARN);
252
253 /* Ignore timeout error */
254 if (merrwarn & SVC_I3C_MERRWARN_TIMEOUT) {
255 dev_dbg(master->dev, "Warning condition: MSTATUS 0x%08x, MERRWARN 0x%08x\n",
256 mstatus, merrwarn);
257 return false;
258 }
259
260 dev_err(master->dev,
261 "Error condition: MSTATUS 0x%08x, MERRWARN 0x%08x\n",
262 mstatus, merrwarn);
263
264 return true;
265 }
266
267 return false;
268 }
269
svc_i3c_master_enable_interrupts(struct svc_i3c_master * master,u32 mask)270 static void svc_i3c_master_enable_interrupts(struct svc_i3c_master *master, u32 mask)
271 {
272 writel(mask, master->regs + SVC_I3C_MINTSET);
273 }
274
svc_i3c_master_disable_interrupts(struct svc_i3c_master * master)275 static void svc_i3c_master_disable_interrupts(struct svc_i3c_master *master)
276 {
277 u32 mask = readl(master->regs + SVC_I3C_MINTSET);
278
279 writel(mask, master->regs + SVC_I3C_MINTCLR);
280 }
281
svc_i3c_master_clear_merrwarn(struct svc_i3c_master * master)282 static void svc_i3c_master_clear_merrwarn(struct svc_i3c_master *master)
283 {
284 /* Clear pending warnings */
285 writel(readl(master->regs + SVC_I3C_MERRWARN),
286 master->regs + SVC_I3C_MERRWARN);
287 }
288
svc_i3c_master_flush_fifo(struct svc_i3c_master * master)289 static void svc_i3c_master_flush_fifo(struct svc_i3c_master *master)
290 {
291 /* Flush FIFOs */
292 writel(SVC_I3C_MDATACTRL_FLUSHTB | SVC_I3C_MDATACTRL_FLUSHRB,
293 master->regs + SVC_I3C_MDATACTRL);
294 }
295
svc_i3c_master_reset_fifo_trigger(struct svc_i3c_master * master)296 static void svc_i3c_master_reset_fifo_trigger(struct svc_i3c_master *master)
297 {
298 u32 reg;
299
300 /* Set RX and TX tigger levels, flush FIFOs */
301 reg = SVC_I3C_MDATACTRL_FLUSHTB |
302 SVC_I3C_MDATACTRL_FLUSHRB |
303 SVC_I3C_MDATACTRL_UNLOCK_TRIG |
304 SVC_I3C_MDATACTRL_TXTRIG_FIFO_NOT_FULL |
305 SVC_I3C_MDATACTRL_RXTRIG_FIFO_NOT_EMPTY;
306 writel(reg, master->regs + SVC_I3C_MDATACTRL);
307 }
308
svc_i3c_master_reset(struct svc_i3c_master * master)309 static void svc_i3c_master_reset(struct svc_i3c_master *master)
310 {
311 svc_i3c_master_clear_merrwarn(master);
312 svc_i3c_master_reset_fifo_trigger(master);
313 svc_i3c_master_disable_interrupts(master);
314 }
315
316 static inline struct svc_i3c_master *
to_svc_i3c_master(struct i3c_master_controller * master)317 to_svc_i3c_master(struct i3c_master_controller *master)
318 {
319 return container_of(master, struct svc_i3c_master, base);
320 }
321
svc_i3c_master_hj_work(struct work_struct * work)322 static void svc_i3c_master_hj_work(struct work_struct *work)
323 {
324 struct svc_i3c_master *master;
325
326 master = container_of(work, struct svc_i3c_master, hj_work);
327 i3c_master_do_daa(&master->base);
328 }
329
330 static struct i3c_dev_desc *
svc_i3c_master_dev_from_addr(struct svc_i3c_master * master,unsigned int ibiaddr)331 svc_i3c_master_dev_from_addr(struct svc_i3c_master *master,
332 unsigned int ibiaddr)
333 {
334 int i;
335
336 for (i = 0; i < SVC_I3C_MAX_DEVS; i++)
337 if (master->addrs[i] == ibiaddr)
338 break;
339
340 if (i == SVC_I3C_MAX_DEVS)
341 return NULL;
342
343 return master->descs[i];
344 }
345
svc_i3c_master_emit_stop(struct svc_i3c_master * master)346 static void svc_i3c_master_emit_stop(struct svc_i3c_master *master)
347 {
348 writel(SVC_I3C_MCTRL_REQUEST_STOP, master->regs + SVC_I3C_MCTRL);
349
350 /*
351 * This delay is necessary after the emission of a stop, otherwise eg.
352 * repeating IBIs do not get detected. There is a note in the manual
353 * about it, stating that the stop condition might not be settled
354 * correctly if a start condition follows too rapidly.
355 */
356 udelay(1);
357 }
358
svc_i3c_master_handle_ibi(struct svc_i3c_master * master,struct i3c_dev_desc * dev)359 static int svc_i3c_master_handle_ibi(struct svc_i3c_master *master,
360 struct i3c_dev_desc *dev)
361 {
362 struct svc_i3c_i2c_dev_data *data = i3c_dev_get_master_data(dev);
363 struct i3c_ibi_slot *slot;
364 unsigned int count;
365 u32 mdatactrl;
366 int ret, val;
367 u8 *buf;
368
369 slot = i3c_generic_ibi_get_free_slot(data->ibi_pool);
370 if (!slot)
371 return -ENOSPC;
372
373 slot->len = 0;
374 buf = slot->data;
375
376 ret = readl_relaxed_poll_timeout(master->regs + SVC_I3C_MSTATUS, val,
377 SVC_I3C_MSTATUS_COMPLETE(val), 0, 1000);
378 if (ret) {
379 dev_err(master->dev, "Timeout when polling for COMPLETE\n");
380 return ret;
381 }
382
383 while (SVC_I3C_MSTATUS_RXPEND(readl(master->regs + SVC_I3C_MSTATUS)) &&
384 slot->len < SVC_I3C_FIFO_SIZE) {
385 mdatactrl = readl(master->regs + SVC_I3C_MDATACTRL);
386 count = SVC_I3C_MDATACTRL_RXCOUNT(mdatactrl);
387 readsb(master->regs + SVC_I3C_MRDATAB, buf, count);
388 slot->len += count;
389 buf += count;
390 }
391
392 master->ibi.tbq_slot = slot;
393
394 return 0;
395 }
396
svc_i3c_master_ack_ibi(struct svc_i3c_master * master,bool mandatory_byte)397 static void svc_i3c_master_ack_ibi(struct svc_i3c_master *master,
398 bool mandatory_byte)
399 {
400 unsigned int ibi_ack_nack;
401
402 ibi_ack_nack = SVC_I3C_MCTRL_REQUEST_IBI_ACKNACK;
403 if (mandatory_byte)
404 ibi_ack_nack |= SVC_I3C_MCTRL_IBIRESP_ACK_WITH_BYTE;
405 else
406 ibi_ack_nack |= SVC_I3C_MCTRL_IBIRESP_ACK_WITHOUT_BYTE;
407
408 writel(ibi_ack_nack, master->regs + SVC_I3C_MCTRL);
409 }
410
svc_i3c_master_nack_ibi(struct svc_i3c_master * master)411 static void svc_i3c_master_nack_ibi(struct svc_i3c_master *master)
412 {
413 writel(SVC_I3C_MCTRL_REQUEST_IBI_ACKNACK |
414 SVC_I3C_MCTRL_IBIRESP_NACK,
415 master->regs + SVC_I3C_MCTRL);
416 }
417
svc_i3c_master_ibi_work(struct work_struct * work)418 static void svc_i3c_master_ibi_work(struct work_struct *work)
419 {
420 struct svc_i3c_master *master = container_of(work, struct svc_i3c_master, ibi_work);
421 struct svc_i3c_i2c_dev_data *data;
422 unsigned int ibitype, ibiaddr;
423 struct i3c_dev_desc *dev;
424 u32 status, val;
425 int ret;
426
427 mutex_lock(&master->lock);
428 /*
429 * IBIWON may be set before SVC_I3C_MCTRL_REQUEST_AUTO_IBI, causing
430 * readl_relaxed_poll_timeout() to return immediately. Consequently,
431 * ibitype will be 0 since it was last updated only after the 8th SCL
432 * cycle, leading to missed client IBI handlers.
433 *
434 * A typical scenario is when IBIWON occurs and bus arbitration is lost
435 * at svc_i3c_master_priv_xfers().
436 *
437 * Clear SVC_I3C_MINT_IBIWON before sending SVC_I3C_MCTRL_REQUEST_AUTO_IBI.
438 */
439 writel(SVC_I3C_MINT_IBIWON, master->regs + SVC_I3C_MSTATUS);
440
441 /* Acknowledge the incoming interrupt with the AUTOIBI mechanism */
442 writel(SVC_I3C_MCTRL_REQUEST_AUTO_IBI |
443 SVC_I3C_MCTRL_IBIRESP_AUTO,
444 master->regs + SVC_I3C_MCTRL);
445
446 /* Wait for IBIWON, should take approximately 100us */
447 ret = readl_relaxed_poll_timeout(master->regs + SVC_I3C_MSTATUS, val,
448 SVC_I3C_MSTATUS_IBIWON(val), 0, 1000);
449 if (ret) {
450 dev_err(master->dev, "Timeout when polling for IBIWON\n");
451 svc_i3c_master_emit_stop(master);
452 goto reenable_ibis;
453 }
454
455 status = readl(master->regs + SVC_I3C_MSTATUS);
456 ibitype = SVC_I3C_MSTATUS_IBITYPE(status);
457 ibiaddr = SVC_I3C_MSTATUS_IBIADDR(status);
458
459 /* Handle the critical responses to IBI's */
460 switch (ibitype) {
461 case SVC_I3C_MSTATUS_IBITYPE_IBI:
462 dev = svc_i3c_master_dev_from_addr(master, ibiaddr);
463 if (!dev || !is_events_enabled(master, SVC_I3C_EVENT_IBI))
464 svc_i3c_master_nack_ibi(master);
465 else
466 svc_i3c_master_handle_ibi(master, dev);
467 break;
468 case SVC_I3C_MSTATUS_IBITYPE_HOT_JOIN:
469 if (is_events_enabled(master, SVC_I3C_EVENT_HOTJOIN))
470 svc_i3c_master_ack_ibi(master, false);
471 else
472 svc_i3c_master_nack_ibi(master);
473 break;
474 case SVC_I3C_MSTATUS_IBITYPE_MASTER_REQUEST:
475 svc_i3c_master_nack_ibi(master);
476 break;
477 default:
478 break;
479 }
480
481 /*
482 * If an error happened, we probably got interrupted and the exchange
483 * timedout. In this case we just drop everything, emit a stop and wait
484 * for the slave to interrupt again.
485 */
486 if (svc_i3c_master_error(master)) {
487 if (master->ibi.tbq_slot) {
488 data = i3c_dev_get_master_data(dev);
489 i3c_generic_ibi_recycle_slot(data->ibi_pool,
490 master->ibi.tbq_slot);
491 master->ibi.tbq_slot = NULL;
492 }
493
494 svc_i3c_master_emit_stop(master);
495
496 goto reenable_ibis;
497 }
498
499 /* Handle the non critical tasks */
500 switch (ibitype) {
501 case SVC_I3C_MSTATUS_IBITYPE_IBI:
502 if (dev) {
503 i3c_master_queue_ibi(dev, master->ibi.tbq_slot);
504 master->ibi.tbq_slot = NULL;
505 }
506 svc_i3c_master_emit_stop(master);
507 break;
508 case SVC_I3C_MSTATUS_IBITYPE_HOT_JOIN:
509 svc_i3c_master_emit_stop(master);
510 if (is_events_enabled(master, SVC_I3C_EVENT_HOTJOIN))
511 queue_work(master->base.wq, &master->hj_work);
512 break;
513 case SVC_I3C_MSTATUS_IBITYPE_MASTER_REQUEST:
514 svc_i3c_master_emit_stop(master);
515 break;
516 default:
517 break;
518 }
519
520 reenable_ibis:
521 svc_i3c_master_enable_interrupts(master, SVC_I3C_MINT_SLVSTART);
522 mutex_unlock(&master->lock);
523 }
524
svc_i3c_master_irq_handler(int irq,void * dev_id)525 static irqreturn_t svc_i3c_master_irq_handler(int irq, void *dev_id)
526 {
527 struct svc_i3c_master *master = (struct svc_i3c_master *)dev_id;
528 u32 active = readl(master->regs + SVC_I3C_MSTATUS);
529
530 if (!SVC_I3C_MSTATUS_SLVSTART(active))
531 return IRQ_NONE;
532
533 /* Clear the interrupt status */
534 writel(SVC_I3C_MINT_SLVSTART, master->regs + SVC_I3C_MSTATUS);
535
536 svc_i3c_master_disable_interrupts(master);
537
538 /* Handle the interrupt in a non atomic context */
539 queue_work(master->base.wq, &master->ibi_work);
540
541 return IRQ_HANDLED;
542 }
543
svc_i3c_master_set_speed(struct i3c_master_controller * m,enum i3c_open_drain_speed speed)544 static int svc_i3c_master_set_speed(struct i3c_master_controller *m,
545 enum i3c_open_drain_speed speed)
546 {
547 struct svc_i3c_master *master = to_svc_i3c_master(m);
548 struct i3c_bus *bus = i3c_master_get_bus(&master->base);
549 u32 ppbaud, odbaud, odhpp, mconfig;
550 unsigned long fclk_rate;
551 int ret;
552
553 ret = pm_runtime_resume_and_get(master->dev);
554 if (ret < 0) {
555 dev_err(master->dev, "<%s> Cannot get runtime PM.\n", __func__);
556 return ret;
557 }
558
559 switch (speed) {
560 case I3C_OPEN_DRAIN_SLOW_SPEED:
561 fclk_rate = clk_get_rate(master->fclk);
562 if (!fclk_rate) {
563 ret = -EINVAL;
564 goto rpm_out;
565 }
566 /*
567 * Set 50% duty-cycle I2C speed to I3C OPEN-DRAIN mode, so the first
568 * broadcast address is visible to all I2C/I3C devices on the I3C bus.
569 * I3C device working as a I2C device will turn off its 50ns Spike
570 * Filter to change to I3C mode.
571 */
572 mconfig = master->mctrl_config;
573 ppbaud = FIELD_GET(GENMASK(11, 8), mconfig);
574 odhpp = 0;
575 odbaud = DIV_ROUND_UP(fclk_rate, bus->scl_rate.i2c * (2 + 2 * ppbaud)) - 1;
576 mconfig &= ~GENMASK(24, 16);
577 mconfig |= SVC_I3C_MCONFIG_ODBAUD(odbaud) | SVC_I3C_MCONFIG_ODHPP(odhpp);
578 writel(mconfig, master->regs + SVC_I3C_MCONFIG);
579 break;
580 case I3C_OPEN_DRAIN_NORMAL_SPEED:
581 writel(master->mctrl_config, master->regs + SVC_I3C_MCONFIG);
582 break;
583 }
584
585 rpm_out:
586 pm_runtime_mark_last_busy(master->dev);
587 pm_runtime_put_autosuspend(master->dev);
588
589 return ret;
590 }
591
svc_i3c_master_bus_init(struct i3c_master_controller * m)592 static int svc_i3c_master_bus_init(struct i3c_master_controller *m)
593 {
594 struct svc_i3c_master *master = to_svc_i3c_master(m);
595 struct i3c_bus *bus = i3c_master_get_bus(m);
596 struct i3c_device_info info = {};
597 unsigned long fclk_rate, fclk_period_ns;
598 unsigned long i2c_period_ns, i2c_scl_rate, i3c_scl_rate;
599 unsigned int high_period_ns, od_low_period_ns;
600 u32 ppbaud, pplow, odhpp, odbaud, odstop, i2cbaud, reg;
601 int ret;
602
603 ret = pm_runtime_resume_and_get(master->dev);
604 if (ret < 0) {
605 dev_err(master->dev,
606 "<%s> cannot resume i3c bus master, err: %d\n",
607 __func__, ret);
608 return ret;
609 }
610
611 /* Timings derivation */
612 fclk_rate = clk_get_rate(master->fclk);
613 if (!fclk_rate) {
614 ret = -EINVAL;
615 goto rpm_out;
616 }
617
618 fclk_period_ns = DIV_ROUND_UP(1000000000, fclk_rate);
619 i2c_period_ns = DIV_ROUND_UP(1000000000, bus->scl_rate.i2c);
620 i2c_scl_rate = bus->scl_rate.i2c;
621 i3c_scl_rate = bus->scl_rate.i3c;
622
623 /*
624 * Using I3C Push-Pull mode, target is 12.5MHz/80ns period.
625 * Simplest configuration is using a 50% duty-cycle of 40ns.
626 */
627 ppbaud = DIV_ROUND_UP(fclk_rate / 2, i3c_scl_rate) - 1;
628 pplow = 0;
629
630 /*
631 * Using I3C Open-Drain mode, target is 4.17MHz/240ns with a
632 * duty-cycle tuned so that high levels are filetered out by
633 * the 50ns filter (target being 40ns).
634 */
635 odhpp = 1;
636 high_period_ns = (ppbaud + 1) * fclk_period_ns;
637 odbaud = DIV_ROUND_UP(fclk_rate, SVC_I3C_QUICK_I2C_CLK * (1 + ppbaud)) - 2;
638 od_low_period_ns = (odbaud + 1) * high_period_ns;
639
640 switch (bus->mode) {
641 case I3C_BUS_MODE_PURE:
642 i2cbaud = 0;
643 odstop = 0;
644 break;
645 case I3C_BUS_MODE_MIXED_FAST:
646 /*
647 * Using I2C Fm+ mode, target is 1MHz/1000ns, the difference
648 * between the high and low period does not really matter.
649 */
650 i2cbaud = DIV_ROUND_UP(i2c_period_ns, od_low_period_ns) - 2;
651 odstop = 1;
652 break;
653 case I3C_BUS_MODE_MIXED_LIMITED:
654 case I3C_BUS_MODE_MIXED_SLOW:
655 /* I3C PP + I3C OP + I2C OP both use i2c clk rate */
656 if (ppbaud > SVC_I3C_PPBAUD_MAX) {
657 ppbaud = SVC_I3C_PPBAUD_MAX;
658 pplow = DIV_ROUND_UP(fclk_rate, i3c_scl_rate) - (2 + 2 * ppbaud);
659 }
660
661 high_period_ns = (ppbaud + 1) * fclk_period_ns;
662 odhpp = 0;
663 odbaud = DIV_ROUND_UP(fclk_rate, i2c_scl_rate * (2 + 2 * ppbaud)) - 1;
664
665 od_low_period_ns = (odbaud + 1) * high_period_ns;
666 i2cbaud = DIV_ROUND_UP(i2c_period_ns, od_low_period_ns) - 2;
667 odstop = 1;
668 break;
669 default:
670 goto rpm_out;
671 }
672
673 reg = SVC_I3C_MCONFIG_MASTER_EN |
674 SVC_I3C_MCONFIG_DISTO(0) |
675 SVC_I3C_MCONFIG_HKEEP(0) |
676 SVC_I3C_MCONFIG_ODSTOP(odstop) |
677 SVC_I3C_MCONFIG_PPBAUD(ppbaud) |
678 SVC_I3C_MCONFIG_PPLOW(pplow) |
679 SVC_I3C_MCONFIG_ODBAUD(odbaud) |
680 SVC_I3C_MCONFIG_ODHPP(odhpp) |
681 SVC_I3C_MCONFIG_SKEW(0) |
682 SVC_I3C_MCONFIG_I2CBAUD(i2cbaud);
683 writel(reg, master->regs + SVC_I3C_MCONFIG);
684
685 master->mctrl_config = reg;
686 /* Master core's registration */
687 ret = i3c_master_get_free_addr(m, 0);
688 if (ret < 0)
689 goto rpm_out;
690
691 info.dyn_addr = ret;
692
693 writel(SVC_MDYNADDR_VALID | SVC_MDYNADDR_ADDR(info.dyn_addr),
694 master->regs + SVC_I3C_MDYNADDR);
695
696 ret = i3c_master_set_info(&master->base, &info);
697 if (ret)
698 goto rpm_out;
699
700 rpm_out:
701 pm_runtime_mark_last_busy(master->dev);
702 pm_runtime_put_autosuspend(master->dev);
703
704 return ret;
705 }
706
svc_i3c_master_bus_cleanup(struct i3c_master_controller * m)707 static void svc_i3c_master_bus_cleanup(struct i3c_master_controller *m)
708 {
709 struct svc_i3c_master *master = to_svc_i3c_master(m);
710 int ret;
711
712 ret = pm_runtime_resume_and_get(master->dev);
713 if (ret < 0) {
714 dev_err(master->dev, "<%s> Cannot get runtime PM.\n", __func__);
715 return;
716 }
717
718 svc_i3c_master_disable_interrupts(master);
719
720 /* Disable master */
721 writel(0, master->regs + SVC_I3C_MCONFIG);
722
723 pm_runtime_mark_last_busy(master->dev);
724 pm_runtime_put_autosuspend(master->dev);
725 }
726
svc_i3c_master_reserve_slot(struct svc_i3c_master * master)727 static int svc_i3c_master_reserve_slot(struct svc_i3c_master *master)
728 {
729 unsigned int slot;
730
731 if (!(master->free_slots & GENMASK(SVC_I3C_MAX_DEVS - 1, 0)))
732 return -ENOSPC;
733
734 slot = ffs(master->free_slots) - 1;
735
736 master->free_slots &= ~BIT(slot);
737
738 return slot;
739 }
740
svc_i3c_master_release_slot(struct svc_i3c_master * master,unsigned int slot)741 static void svc_i3c_master_release_slot(struct svc_i3c_master *master,
742 unsigned int slot)
743 {
744 master->free_slots |= BIT(slot);
745 }
746
svc_i3c_master_attach_i3c_dev(struct i3c_dev_desc * dev)747 static int svc_i3c_master_attach_i3c_dev(struct i3c_dev_desc *dev)
748 {
749 struct i3c_master_controller *m = i3c_dev_get_master(dev);
750 struct svc_i3c_master *master = to_svc_i3c_master(m);
751 struct svc_i3c_i2c_dev_data *data;
752 int slot;
753
754 slot = svc_i3c_master_reserve_slot(master);
755 if (slot < 0)
756 return slot;
757
758 data = kzalloc(sizeof(*data), GFP_KERNEL);
759 if (!data) {
760 svc_i3c_master_release_slot(master, slot);
761 return -ENOMEM;
762 }
763
764 data->ibi = -1;
765 data->index = slot;
766 master->addrs[slot] = dev->info.dyn_addr ? dev->info.dyn_addr :
767 dev->info.static_addr;
768 master->descs[slot] = dev;
769
770 i3c_dev_set_master_data(dev, data);
771
772 return 0;
773 }
774
svc_i3c_master_reattach_i3c_dev(struct i3c_dev_desc * dev,u8 old_dyn_addr)775 static int svc_i3c_master_reattach_i3c_dev(struct i3c_dev_desc *dev,
776 u8 old_dyn_addr)
777 {
778 struct i3c_master_controller *m = i3c_dev_get_master(dev);
779 struct svc_i3c_master *master = to_svc_i3c_master(m);
780 struct svc_i3c_i2c_dev_data *data = i3c_dev_get_master_data(dev);
781
782 master->addrs[data->index] = dev->info.dyn_addr ? dev->info.dyn_addr :
783 dev->info.static_addr;
784
785 return 0;
786 }
787
svc_i3c_master_detach_i3c_dev(struct i3c_dev_desc * dev)788 static void svc_i3c_master_detach_i3c_dev(struct i3c_dev_desc *dev)
789 {
790 struct svc_i3c_i2c_dev_data *data = i3c_dev_get_master_data(dev);
791 struct i3c_master_controller *m = i3c_dev_get_master(dev);
792 struct svc_i3c_master *master = to_svc_i3c_master(m);
793
794 master->addrs[data->index] = 0;
795 svc_i3c_master_release_slot(master, data->index);
796
797 kfree(data);
798 }
799
svc_i3c_master_attach_i2c_dev(struct i2c_dev_desc * dev)800 static int svc_i3c_master_attach_i2c_dev(struct i2c_dev_desc *dev)
801 {
802 struct i3c_master_controller *m = i2c_dev_get_master(dev);
803 struct svc_i3c_master *master = to_svc_i3c_master(m);
804 struct svc_i3c_i2c_dev_data *data;
805 int slot;
806
807 slot = svc_i3c_master_reserve_slot(master);
808 if (slot < 0)
809 return slot;
810
811 data = kzalloc(sizeof(*data), GFP_KERNEL);
812 if (!data) {
813 svc_i3c_master_release_slot(master, slot);
814 return -ENOMEM;
815 }
816
817 data->index = slot;
818 master->addrs[slot] = dev->addr;
819
820 i2c_dev_set_master_data(dev, data);
821
822 return 0;
823 }
824
svc_i3c_master_detach_i2c_dev(struct i2c_dev_desc * dev)825 static void svc_i3c_master_detach_i2c_dev(struct i2c_dev_desc *dev)
826 {
827 struct svc_i3c_i2c_dev_data *data = i2c_dev_get_master_data(dev);
828 struct i3c_master_controller *m = i2c_dev_get_master(dev);
829 struct svc_i3c_master *master = to_svc_i3c_master(m);
830
831 svc_i3c_master_release_slot(master, data->index);
832
833 kfree(data);
834 }
835
svc_i3c_master_readb(struct svc_i3c_master * master,u8 * dst,unsigned int len)836 static int svc_i3c_master_readb(struct svc_i3c_master *master, u8 *dst,
837 unsigned int len)
838 {
839 int ret, i;
840 u32 reg;
841
842 for (i = 0; i < len; i++) {
843 ret = readl_poll_timeout_atomic(master->regs + SVC_I3C_MSTATUS,
844 reg,
845 SVC_I3C_MSTATUS_RXPEND(reg),
846 0, 1000);
847 if (ret)
848 return ret;
849
850 dst[i] = readl(master->regs + SVC_I3C_MRDATAB);
851 }
852
853 return 0;
854 }
855
svc_i3c_master_do_daa_locked(struct svc_i3c_master * master,u8 * addrs,unsigned int * count)856 static int svc_i3c_master_do_daa_locked(struct svc_i3c_master *master,
857 u8 *addrs, unsigned int *count)
858 {
859 u64 prov_id[SVC_I3C_MAX_DEVS] = {}, nacking_prov_id = 0;
860 unsigned int dev_nb = 0, last_addr = 0;
861 u32 reg;
862 int ret, i;
863
864 svc_i3c_master_flush_fifo(master);
865
866 while (true) {
867 /* SVC_I3C_MCTRL_REQUEST_PROC_DAA have two mode, ENTER DAA or PROCESS DAA.
868 *
869 * ENTER DAA:
870 * 1 will issue START, 7E, ENTDAA, and then emits 7E/R to process first target.
871 * 2 Stops just before the new Dynamic Address (DA) is to be emitted.
872 *
873 * PROCESS DAA:
874 * 1 The DA is written using MWDATAB or ADDR bits 6:0.
875 * 2 ProcessDAA is requested again to write the new address, and then starts the
876 * next (START, 7E, ENTDAA) unless marked to STOP; an MSTATUS indicating NACK
877 * means DA was not accepted (e.g. parity error). If PROCESSDAA is NACKed on the
878 * 7E/R, which means no more Slaves need a DA, then a COMPLETE will be signaled
879 * (along with DONE), and a STOP issued automatically.
880 */
881 writel(SVC_I3C_MCTRL_REQUEST_PROC_DAA |
882 SVC_I3C_MCTRL_TYPE_I3C |
883 SVC_I3C_MCTRL_IBIRESP_NACK |
884 SVC_I3C_MCTRL_DIR(SVC_I3C_MCTRL_DIR_WRITE),
885 master->regs + SVC_I3C_MCTRL);
886
887 /*
888 * Either one slave will send its ID, or the assignment process
889 * is done.
890 */
891 ret = readl_poll_timeout_atomic(master->regs + SVC_I3C_MSTATUS,
892 reg,
893 SVC_I3C_MSTATUS_RXPEND(reg) |
894 SVC_I3C_MSTATUS_MCTRLDONE(reg),
895 1, 1000);
896 if (ret)
897 break;
898
899 if (SVC_I3C_MSTATUS_RXPEND(reg)) {
900 u8 data[6];
901
902 /*
903 * We only care about the 48-bit provisioned ID yet to
904 * be sure a device does not nack an address twice.
905 * Otherwise, we would just need to flush the RX FIFO.
906 */
907 ret = svc_i3c_master_readb(master, data, 6);
908 if (ret)
909 break;
910
911 for (i = 0; i < 6; i++)
912 prov_id[dev_nb] |= (u64)(data[i]) << (8 * (5 - i));
913
914 /* We do not care about the BCR and DCR yet */
915 ret = svc_i3c_master_readb(master, data, 2);
916 if (ret)
917 break;
918 } else if (SVC_I3C_MSTATUS_MCTRLDONE(reg)) {
919 if (SVC_I3C_MSTATUS_STATE_IDLE(reg) &&
920 SVC_I3C_MSTATUS_COMPLETE(reg)) {
921 /*
922 * All devices received and acked they dynamic
923 * address, this is the natural end of the DAA
924 * procedure.
925 *
926 * Hardware will auto emit STOP at this case.
927 */
928 *count = dev_nb;
929 return 0;
930
931 } else if (SVC_I3C_MSTATUS_NACKED(reg)) {
932 /* No I3C devices attached */
933 if (dev_nb == 0) {
934 /*
935 * Hardware can't treat first NACK for ENTAA as normal
936 * COMPLETE. So need manual emit STOP.
937 */
938 ret = 0;
939 *count = 0;
940 break;
941 }
942
943 /*
944 * A slave device nacked the address, this is
945 * allowed only once, DAA will be stopped and
946 * then resumed. The same device is supposed to
947 * answer again immediately and shall ack the
948 * address this time.
949 */
950 if (prov_id[dev_nb] == nacking_prov_id) {
951 ret = -EIO;
952 break;
953 }
954
955 dev_nb--;
956 nacking_prov_id = prov_id[dev_nb];
957 svc_i3c_master_emit_stop(master);
958
959 continue;
960 } else {
961 break;
962 }
963 }
964
965 /* Wait for the slave to be ready to receive its address */
966 ret = readl_poll_timeout_atomic(master->regs + SVC_I3C_MSTATUS,
967 reg,
968 SVC_I3C_MSTATUS_MCTRLDONE(reg) &&
969 SVC_I3C_MSTATUS_STATE_DAA(reg) &&
970 SVC_I3C_MSTATUS_BETWEEN(reg),
971 0, 1000);
972 if (ret)
973 break;
974
975 /* Give the slave device a suitable dynamic address */
976 ret = i3c_master_get_free_addr(&master->base, last_addr + 1);
977 if (ret < 0)
978 break;
979
980 addrs[dev_nb] = ret;
981 dev_dbg(master->dev, "DAA: device %d assigned to 0x%02x\n",
982 dev_nb, addrs[dev_nb]);
983
984 writel(addrs[dev_nb], master->regs + SVC_I3C_MWDATAB);
985 last_addr = addrs[dev_nb++];
986 }
987
988 /* Need manual issue STOP except for Complete condition */
989 svc_i3c_master_emit_stop(master);
990 return ret;
991 }
992
svc_i3c_update_ibirules(struct svc_i3c_master * master)993 static int svc_i3c_update_ibirules(struct svc_i3c_master *master)
994 {
995 struct i3c_dev_desc *dev;
996 u32 reg_mbyte = 0, reg_nobyte = SVC_I3C_IBIRULES_NOBYTE;
997 unsigned int mbyte_addr_ok = 0, mbyte_addr_ko = 0, nobyte_addr_ok = 0,
998 nobyte_addr_ko = 0;
999 bool list_mbyte = false, list_nobyte = false;
1000
1001 /* Create the IBIRULES register for both cases */
1002 i3c_bus_for_each_i3cdev(&master->base.bus, dev) {
1003 if (!(dev->info.bcr & I3C_BCR_IBI_REQ_CAP))
1004 continue;
1005
1006 if (dev->info.bcr & I3C_BCR_IBI_PAYLOAD) {
1007 reg_mbyte |= SVC_I3C_IBIRULES_ADDR(mbyte_addr_ok,
1008 dev->info.dyn_addr);
1009
1010 /* IBI rules cannot be applied to devices with MSb=1 */
1011 if (dev->info.dyn_addr & BIT(7))
1012 mbyte_addr_ko++;
1013 else
1014 mbyte_addr_ok++;
1015 } else {
1016 reg_nobyte |= SVC_I3C_IBIRULES_ADDR(nobyte_addr_ok,
1017 dev->info.dyn_addr);
1018
1019 /* IBI rules cannot be applied to devices with MSb=1 */
1020 if (dev->info.dyn_addr & BIT(7))
1021 nobyte_addr_ko++;
1022 else
1023 nobyte_addr_ok++;
1024 }
1025 }
1026
1027 /* Device list cannot be handled by hardware */
1028 if (!mbyte_addr_ko && mbyte_addr_ok <= SVC_I3C_IBIRULES_ADDRS)
1029 list_mbyte = true;
1030
1031 if (!nobyte_addr_ko && nobyte_addr_ok <= SVC_I3C_IBIRULES_ADDRS)
1032 list_nobyte = true;
1033
1034 /* No list can be properly handled, return an error */
1035 if (!list_mbyte && !list_nobyte)
1036 return -ERANGE;
1037
1038 /* Pick the first list that can be handled by hardware, randomly */
1039 if (list_mbyte)
1040 writel(reg_mbyte, master->regs + SVC_I3C_IBIRULES);
1041 else
1042 writel(reg_nobyte, master->regs + SVC_I3C_IBIRULES);
1043
1044 return 0;
1045 }
1046
svc_i3c_master_do_daa(struct i3c_master_controller * m)1047 static int svc_i3c_master_do_daa(struct i3c_master_controller *m)
1048 {
1049 struct svc_i3c_master *master = to_svc_i3c_master(m);
1050 u8 addrs[SVC_I3C_MAX_DEVS];
1051 unsigned long flags;
1052 unsigned int dev_nb;
1053 int ret, i;
1054
1055 ret = pm_runtime_resume_and_get(master->dev);
1056 if (ret < 0) {
1057 dev_err(master->dev, "<%s> Cannot get runtime PM.\n", __func__);
1058 return ret;
1059 }
1060
1061 spin_lock_irqsave(&master->xferqueue.lock, flags);
1062 ret = svc_i3c_master_do_daa_locked(master, addrs, &dev_nb);
1063 spin_unlock_irqrestore(&master->xferqueue.lock, flags);
1064
1065 svc_i3c_master_clear_merrwarn(master);
1066 if (ret)
1067 goto rpm_out;
1068
1069 /*
1070 * Register all devices who participated to the core
1071 *
1072 * If two devices (A and B) are detected in DAA and address 0xa is assigned to
1073 * device A and 0xb to device B, a failure in i3c_master_add_i3c_dev_locked()
1074 * for device A (addr: 0xa) could prevent device B (addr: 0xb) from being
1075 * registered on the bus. The I3C stack might still consider 0xb a free
1076 * address. If a subsequent Hotjoin occurs, 0xb might be assigned to Device A,
1077 * causing both devices A and B to use the same address 0xb, violating the I3C
1078 * specification.
1079 *
1080 * The return value for i3c_master_add_i3c_dev_locked() should not be checked
1081 * because subsequent steps will scan the entire I3C bus, independent of
1082 * whether i3c_master_add_i3c_dev_locked() returns success.
1083 *
1084 * If device A registration fails, there is still a chance to register device
1085 * B. i3c_master_add_i3c_dev_locked() can reset DAA if a failure occurs while
1086 * retrieving device information.
1087 */
1088 for (i = 0; i < dev_nb; i++)
1089 i3c_master_add_i3c_dev_locked(m, addrs[i]);
1090
1091 /* Configure IBI auto-rules */
1092 ret = svc_i3c_update_ibirules(master);
1093 if (ret)
1094 dev_err(master->dev, "Cannot handle such a list of devices");
1095
1096 rpm_out:
1097 pm_runtime_mark_last_busy(master->dev);
1098 pm_runtime_put_autosuspend(master->dev);
1099
1100 return ret;
1101 }
1102
svc_i3c_master_read(struct svc_i3c_master * master,u8 * in,unsigned int len)1103 static int svc_i3c_master_read(struct svc_i3c_master *master,
1104 u8 *in, unsigned int len)
1105 {
1106 int offset = 0, i;
1107 u32 mdctrl, mstatus;
1108 bool completed = false;
1109 unsigned int count;
1110 unsigned long start = jiffies;
1111
1112 while (!completed) {
1113 mstatus = readl(master->regs + SVC_I3C_MSTATUS);
1114 if (SVC_I3C_MSTATUS_COMPLETE(mstatus) != 0)
1115 completed = true;
1116
1117 if (time_after(jiffies, start + msecs_to_jiffies(1000))) {
1118 dev_dbg(master->dev, "I3C read timeout\n");
1119 return -ETIMEDOUT;
1120 }
1121
1122 mdctrl = readl(master->regs + SVC_I3C_MDATACTRL);
1123 count = SVC_I3C_MDATACTRL_RXCOUNT(mdctrl);
1124 if (offset + count > len) {
1125 dev_err(master->dev, "I3C receive length too long!\n");
1126 return -EINVAL;
1127 }
1128 for (i = 0; i < count; i++)
1129 in[offset + i] = readl(master->regs + SVC_I3C_MRDATAB);
1130
1131 offset += count;
1132 }
1133
1134 return offset;
1135 }
1136
svc_i3c_master_write(struct svc_i3c_master * master,const u8 * out,unsigned int len)1137 static int svc_i3c_master_write(struct svc_i3c_master *master,
1138 const u8 *out, unsigned int len)
1139 {
1140 int offset = 0, ret;
1141 u32 mdctrl;
1142
1143 while (offset < len) {
1144 ret = readl_poll_timeout(master->regs + SVC_I3C_MDATACTRL,
1145 mdctrl,
1146 !(mdctrl & SVC_I3C_MDATACTRL_TXFULL),
1147 0, 1000);
1148 if (ret)
1149 return ret;
1150
1151 /*
1152 * The last byte to be sent over the bus must either have the
1153 * "end" bit set or be written in MWDATABE.
1154 */
1155 if (likely(offset < (len - 1)))
1156 writel(out[offset++], master->regs + SVC_I3C_MWDATAB);
1157 else
1158 writel(out[offset++], master->regs + SVC_I3C_MWDATABE);
1159 }
1160
1161 return 0;
1162 }
1163
svc_i3c_master_xfer(struct svc_i3c_master * master,bool rnw,unsigned int xfer_type,u8 addr,u8 * in,const u8 * out,unsigned int xfer_len,unsigned int * actual_len,bool continued)1164 static int svc_i3c_master_xfer(struct svc_i3c_master *master,
1165 bool rnw, unsigned int xfer_type, u8 addr,
1166 u8 *in, const u8 *out, unsigned int xfer_len,
1167 unsigned int *actual_len, bool continued)
1168 {
1169 int retry = 2;
1170 u32 reg;
1171 int ret;
1172
1173 /* clean SVC_I3C_MINT_IBIWON w1c bits */
1174 writel(SVC_I3C_MINT_IBIWON, master->regs + SVC_I3C_MSTATUS);
1175
1176
1177 while (retry--) {
1178 writel(SVC_I3C_MCTRL_REQUEST_START_ADDR |
1179 xfer_type |
1180 SVC_I3C_MCTRL_IBIRESP_NACK |
1181 SVC_I3C_MCTRL_DIR(rnw) |
1182 SVC_I3C_MCTRL_ADDR(addr) |
1183 SVC_I3C_MCTRL_RDTERM(*actual_len),
1184 master->regs + SVC_I3C_MCTRL);
1185
1186 ret = readl_poll_timeout(master->regs + SVC_I3C_MSTATUS, reg,
1187 SVC_I3C_MSTATUS_MCTRLDONE(reg), 0, 1000);
1188 if (ret)
1189 goto emit_stop;
1190
1191 if (readl(master->regs + SVC_I3C_MERRWARN) & SVC_I3C_MERRWARN_NACK) {
1192 /*
1193 * According to I3C Spec 1.1.1, 11-Jun-2021, section: 5.1.2.2.3.
1194 * If the Controller chooses to start an I3C Message with an I3C Dynamic
1195 * Address, then special provisions shall be made because that same I3C
1196 * Target may be initiating an IBI or a Controller Role Request. So, one of
1197 * three things may happen: (skip 1, 2)
1198 *
1199 * 3. The Addresses match and the RnW bits also match, and so neither
1200 * Controller nor Target will ACK since both are expecting the other side to
1201 * provide ACK. As a result, each side might think it had "won" arbitration,
1202 * but neither side would continue, as each would subsequently see that the
1203 * other did not provide ACK.
1204 * ...
1205 * For either value of RnW: Due to the NACK, the Controller shall defer the
1206 * Private Write or Private Read, and should typically transmit the Target
1207 * Address again after a Repeated START (i.e., the next one or any one prior
1208 * to a STOP in the Frame). Since the Address Header following a Repeated
1209 * START is not arbitrated, the Controller will always win (see Section
1210 * 5.1.2.2.4).
1211 */
1212 if (retry && addr != 0x7e) {
1213 writel(SVC_I3C_MERRWARN_NACK, master->regs + SVC_I3C_MERRWARN);
1214 } else {
1215 ret = -ENXIO;
1216 *actual_len = 0;
1217 goto emit_stop;
1218 }
1219 } else {
1220 break;
1221 }
1222 }
1223
1224 /*
1225 * According to I3C spec ver 1.1.1, 5.1.2.2.3 Consequence of Controller Starting a Frame
1226 * with I3C Target Address.
1227 *
1228 * The I3C Controller normally should start a Frame, the Address may be arbitrated, and so
1229 * the Controller shall monitor to see whether an In-Band Interrupt request, a Controller
1230 * Role Request (i.e., Secondary Controller requests to become the Active Controller), or
1231 * a Hot-Join Request has been made.
1232 *
1233 * If missed IBIWON check, the wrong data will be return. When IBIWON happen, return failure
1234 * and yield the above events handler.
1235 */
1236 if (SVC_I3C_MSTATUS_IBIWON(reg)) {
1237 ret = -EAGAIN;
1238 *actual_len = 0;
1239 goto emit_stop;
1240 }
1241
1242 if (rnw)
1243 ret = svc_i3c_master_read(master, in, xfer_len);
1244 else
1245 ret = svc_i3c_master_write(master, out, xfer_len);
1246 if (ret < 0)
1247 goto emit_stop;
1248
1249 if (rnw)
1250 *actual_len = ret;
1251
1252 ret = readl_poll_timeout(master->regs + SVC_I3C_MSTATUS, reg,
1253 SVC_I3C_MSTATUS_COMPLETE(reg), 0, 1000);
1254 if (ret)
1255 goto emit_stop;
1256
1257 writel(SVC_I3C_MINT_COMPLETE, master->regs + SVC_I3C_MSTATUS);
1258
1259 if (!continued) {
1260 svc_i3c_master_emit_stop(master);
1261
1262 /* Wait idle if stop is sent. */
1263 readl_poll_timeout(master->regs + SVC_I3C_MSTATUS, reg,
1264 SVC_I3C_MSTATUS_STATE_IDLE(reg), 0, 1000);
1265 }
1266
1267 return 0;
1268
1269 emit_stop:
1270 svc_i3c_master_emit_stop(master);
1271 svc_i3c_master_clear_merrwarn(master);
1272
1273 return ret;
1274 }
1275
1276 static struct svc_i3c_xfer *
svc_i3c_master_alloc_xfer(struct svc_i3c_master * master,unsigned int ncmds)1277 svc_i3c_master_alloc_xfer(struct svc_i3c_master *master, unsigned int ncmds)
1278 {
1279 struct svc_i3c_xfer *xfer;
1280
1281 xfer = kzalloc(struct_size(xfer, cmds, ncmds), GFP_KERNEL);
1282 if (!xfer)
1283 return NULL;
1284
1285 INIT_LIST_HEAD(&xfer->node);
1286 xfer->ncmds = ncmds;
1287 xfer->ret = -ETIMEDOUT;
1288
1289 return xfer;
1290 }
1291
svc_i3c_master_free_xfer(struct svc_i3c_xfer * xfer)1292 static void svc_i3c_master_free_xfer(struct svc_i3c_xfer *xfer)
1293 {
1294 kfree(xfer);
1295 }
1296
svc_i3c_master_dequeue_xfer_locked(struct svc_i3c_master * master,struct svc_i3c_xfer * xfer)1297 static void svc_i3c_master_dequeue_xfer_locked(struct svc_i3c_master *master,
1298 struct svc_i3c_xfer *xfer)
1299 {
1300 if (master->xferqueue.cur == xfer)
1301 master->xferqueue.cur = NULL;
1302 else
1303 list_del_init(&xfer->node);
1304 }
1305
svc_i3c_master_dequeue_xfer(struct svc_i3c_master * master,struct svc_i3c_xfer * xfer)1306 static void svc_i3c_master_dequeue_xfer(struct svc_i3c_master *master,
1307 struct svc_i3c_xfer *xfer)
1308 {
1309 unsigned long flags;
1310
1311 spin_lock_irqsave(&master->xferqueue.lock, flags);
1312 svc_i3c_master_dequeue_xfer_locked(master, xfer);
1313 spin_unlock_irqrestore(&master->xferqueue.lock, flags);
1314 }
1315
svc_i3c_master_start_xfer_locked(struct svc_i3c_master * master)1316 static void svc_i3c_master_start_xfer_locked(struct svc_i3c_master *master)
1317 {
1318 struct svc_i3c_xfer *xfer = master->xferqueue.cur;
1319 int ret, i;
1320
1321 if (!xfer)
1322 return;
1323
1324 svc_i3c_master_clear_merrwarn(master);
1325 svc_i3c_master_flush_fifo(master);
1326
1327 for (i = 0; i < xfer->ncmds; i++) {
1328 struct svc_i3c_cmd *cmd = &xfer->cmds[i];
1329
1330 ret = svc_i3c_master_xfer(master, cmd->rnw, xfer->type,
1331 cmd->addr, cmd->in, cmd->out,
1332 cmd->len, &cmd->actual_len,
1333 cmd->continued);
1334 /* cmd->xfer is NULL if I2C or CCC transfer */
1335 if (cmd->xfer)
1336 cmd->xfer->actual_len = cmd->actual_len;
1337
1338 if (ret)
1339 break;
1340 }
1341
1342 xfer->ret = ret;
1343 complete(&xfer->comp);
1344
1345 if (ret < 0)
1346 svc_i3c_master_dequeue_xfer_locked(master, xfer);
1347
1348 xfer = list_first_entry_or_null(&master->xferqueue.list,
1349 struct svc_i3c_xfer,
1350 node);
1351 if (xfer)
1352 list_del_init(&xfer->node);
1353
1354 master->xferqueue.cur = xfer;
1355 svc_i3c_master_start_xfer_locked(master);
1356 }
1357
svc_i3c_master_enqueue_xfer(struct svc_i3c_master * master,struct svc_i3c_xfer * xfer)1358 static void svc_i3c_master_enqueue_xfer(struct svc_i3c_master *master,
1359 struct svc_i3c_xfer *xfer)
1360 {
1361 unsigned long flags;
1362 int ret;
1363
1364 ret = pm_runtime_resume_and_get(master->dev);
1365 if (ret < 0) {
1366 dev_err(master->dev, "<%s> Cannot get runtime PM.\n", __func__);
1367 return;
1368 }
1369
1370 init_completion(&xfer->comp);
1371 spin_lock_irqsave(&master->xferqueue.lock, flags);
1372 if (master->xferqueue.cur) {
1373 list_add_tail(&xfer->node, &master->xferqueue.list);
1374 } else {
1375 master->xferqueue.cur = xfer;
1376 svc_i3c_master_start_xfer_locked(master);
1377 }
1378 spin_unlock_irqrestore(&master->xferqueue.lock, flags);
1379
1380 pm_runtime_mark_last_busy(master->dev);
1381 pm_runtime_put_autosuspend(master->dev);
1382 }
1383
1384 static bool
svc_i3c_master_supports_ccc_cmd(struct i3c_master_controller * master,const struct i3c_ccc_cmd * cmd)1385 svc_i3c_master_supports_ccc_cmd(struct i3c_master_controller *master,
1386 const struct i3c_ccc_cmd *cmd)
1387 {
1388 /* No software support for CCC commands targeting more than one slave */
1389 return (cmd->ndests == 1);
1390 }
1391
svc_i3c_master_send_bdcast_ccc_cmd(struct svc_i3c_master * master,struct i3c_ccc_cmd * ccc)1392 static int svc_i3c_master_send_bdcast_ccc_cmd(struct svc_i3c_master *master,
1393 struct i3c_ccc_cmd *ccc)
1394 {
1395 unsigned int xfer_len = ccc->dests[0].payload.len + 1;
1396 struct svc_i3c_xfer *xfer;
1397 struct svc_i3c_cmd *cmd;
1398 u8 *buf;
1399 int ret;
1400
1401 xfer = svc_i3c_master_alloc_xfer(master, 1);
1402 if (!xfer)
1403 return -ENOMEM;
1404
1405 buf = kmalloc(xfer_len, GFP_KERNEL);
1406 if (!buf) {
1407 svc_i3c_master_free_xfer(xfer);
1408 return -ENOMEM;
1409 }
1410
1411 buf[0] = ccc->id;
1412 memcpy(&buf[1], ccc->dests[0].payload.data, ccc->dests[0].payload.len);
1413
1414 xfer->type = SVC_I3C_MCTRL_TYPE_I3C;
1415
1416 cmd = &xfer->cmds[0];
1417 cmd->addr = ccc->dests[0].addr;
1418 cmd->rnw = ccc->rnw;
1419 cmd->in = NULL;
1420 cmd->out = buf;
1421 cmd->len = xfer_len;
1422 cmd->actual_len = 0;
1423 cmd->continued = false;
1424
1425 mutex_lock(&master->lock);
1426 svc_i3c_master_enqueue_xfer(master, xfer);
1427 if (!wait_for_completion_timeout(&xfer->comp, msecs_to_jiffies(1000)))
1428 svc_i3c_master_dequeue_xfer(master, xfer);
1429 mutex_unlock(&master->lock);
1430
1431 ret = xfer->ret;
1432 kfree(buf);
1433 svc_i3c_master_free_xfer(xfer);
1434
1435 return ret;
1436 }
1437
svc_i3c_master_send_direct_ccc_cmd(struct svc_i3c_master * master,struct i3c_ccc_cmd * ccc)1438 static int svc_i3c_master_send_direct_ccc_cmd(struct svc_i3c_master *master,
1439 struct i3c_ccc_cmd *ccc)
1440 {
1441 unsigned int xfer_len = ccc->dests[0].payload.len;
1442 unsigned int actual_len = ccc->rnw ? xfer_len : 0;
1443 struct svc_i3c_xfer *xfer;
1444 struct svc_i3c_cmd *cmd;
1445 int ret;
1446
1447 xfer = svc_i3c_master_alloc_xfer(master, 2);
1448 if (!xfer)
1449 return -ENOMEM;
1450
1451 xfer->type = SVC_I3C_MCTRL_TYPE_I3C;
1452
1453 /* Broadcasted message */
1454 cmd = &xfer->cmds[0];
1455 cmd->addr = I3C_BROADCAST_ADDR;
1456 cmd->rnw = 0;
1457 cmd->in = NULL;
1458 cmd->out = &ccc->id;
1459 cmd->len = 1;
1460 cmd->actual_len = 0;
1461 cmd->continued = true;
1462
1463 /* Directed message */
1464 cmd = &xfer->cmds[1];
1465 cmd->addr = ccc->dests[0].addr;
1466 cmd->rnw = ccc->rnw;
1467 cmd->in = ccc->rnw ? ccc->dests[0].payload.data : NULL;
1468 cmd->out = ccc->rnw ? NULL : ccc->dests[0].payload.data;
1469 cmd->len = xfer_len;
1470 cmd->actual_len = actual_len;
1471 cmd->continued = false;
1472
1473 mutex_lock(&master->lock);
1474 svc_i3c_master_enqueue_xfer(master, xfer);
1475 if (!wait_for_completion_timeout(&xfer->comp, msecs_to_jiffies(1000)))
1476 svc_i3c_master_dequeue_xfer(master, xfer);
1477 mutex_unlock(&master->lock);
1478
1479 if (cmd->actual_len != xfer_len)
1480 ccc->dests[0].payload.len = cmd->actual_len;
1481
1482 ret = xfer->ret;
1483 svc_i3c_master_free_xfer(xfer);
1484
1485 return ret;
1486 }
1487
svc_i3c_master_send_ccc_cmd(struct i3c_master_controller * m,struct i3c_ccc_cmd * cmd)1488 static int svc_i3c_master_send_ccc_cmd(struct i3c_master_controller *m,
1489 struct i3c_ccc_cmd *cmd)
1490 {
1491 struct svc_i3c_master *master = to_svc_i3c_master(m);
1492 bool broadcast = cmd->id < 0x80;
1493 int ret;
1494
1495 if (broadcast)
1496 ret = svc_i3c_master_send_bdcast_ccc_cmd(master, cmd);
1497 else
1498 ret = svc_i3c_master_send_direct_ccc_cmd(master, cmd);
1499
1500 if (ret)
1501 cmd->err = I3C_ERROR_M2;
1502
1503 return ret;
1504 }
1505
svc_i3c_master_priv_xfers(struct i3c_dev_desc * dev,struct i3c_priv_xfer * xfers,int nxfers)1506 static int svc_i3c_master_priv_xfers(struct i3c_dev_desc *dev,
1507 struct i3c_priv_xfer *xfers,
1508 int nxfers)
1509 {
1510 struct i3c_master_controller *m = i3c_dev_get_master(dev);
1511 struct svc_i3c_master *master = to_svc_i3c_master(m);
1512 struct svc_i3c_i2c_dev_data *data = i3c_dev_get_master_data(dev);
1513 struct svc_i3c_xfer *xfer;
1514 int ret, i;
1515
1516 xfer = svc_i3c_master_alloc_xfer(master, nxfers);
1517 if (!xfer)
1518 return -ENOMEM;
1519
1520 xfer->type = SVC_I3C_MCTRL_TYPE_I3C;
1521
1522 for (i = 0; i < nxfers; i++) {
1523 struct svc_i3c_cmd *cmd = &xfer->cmds[i];
1524
1525 cmd->xfer = &xfers[i];
1526 cmd->addr = master->addrs[data->index];
1527 cmd->rnw = xfers[i].rnw;
1528 cmd->in = xfers[i].rnw ? xfers[i].data.in : NULL;
1529 cmd->out = xfers[i].rnw ? NULL : xfers[i].data.out;
1530 cmd->len = xfers[i].len;
1531 cmd->actual_len = xfers[i].rnw ? xfers[i].len : 0;
1532 cmd->continued = (i + 1) < nxfers;
1533 }
1534
1535 mutex_lock(&master->lock);
1536 svc_i3c_master_enqueue_xfer(master, xfer);
1537 if (!wait_for_completion_timeout(&xfer->comp, msecs_to_jiffies(1000)))
1538 svc_i3c_master_dequeue_xfer(master, xfer);
1539 mutex_unlock(&master->lock);
1540
1541 ret = xfer->ret;
1542 svc_i3c_master_free_xfer(xfer);
1543
1544 return ret;
1545 }
1546
svc_i3c_master_i2c_xfers(struct i2c_dev_desc * dev,const struct i2c_msg * xfers,int nxfers)1547 static int svc_i3c_master_i2c_xfers(struct i2c_dev_desc *dev,
1548 const struct i2c_msg *xfers,
1549 int nxfers)
1550 {
1551 struct i3c_master_controller *m = i2c_dev_get_master(dev);
1552 struct svc_i3c_master *master = to_svc_i3c_master(m);
1553 struct svc_i3c_i2c_dev_data *data = i2c_dev_get_master_data(dev);
1554 struct svc_i3c_xfer *xfer;
1555 int ret, i;
1556
1557 xfer = svc_i3c_master_alloc_xfer(master, nxfers);
1558 if (!xfer)
1559 return -ENOMEM;
1560
1561 xfer->type = SVC_I3C_MCTRL_TYPE_I2C;
1562
1563 for (i = 0; i < nxfers; i++) {
1564 struct svc_i3c_cmd *cmd = &xfer->cmds[i];
1565
1566 cmd->addr = master->addrs[data->index];
1567 cmd->rnw = xfers[i].flags & I2C_M_RD;
1568 cmd->in = cmd->rnw ? xfers[i].buf : NULL;
1569 cmd->out = cmd->rnw ? NULL : xfers[i].buf;
1570 cmd->len = xfers[i].len;
1571 cmd->actual_len = cmd->rnw ? xfers[i].len : 0;
1572 cmd->continued = (i + 1 < nxfers);
1573 }
1574
1575 mutex_lock(&master->lock);
1576 svc_i3c_master_enqueue_xfer(master, xfer);
1577 if (!wait_for_completion_timeout(&xfer->comp, msecs_to_jiffies(1000)))
1578 svc_i3c_master_dequeue_xfer(master, xfer);
1579 mutex_unlock(&master->lock);
1580
1581 ret = xfer->ret;
1582 svc_i3c_master_free_xfer(xfer);
1583
1584 return ret;
1585 }
1586
svc_i3c_master_request_ibi(struct i3c_dev_desc * dev,const struct i3c_ibi_setup * req)1587 static int svc_i3c_master_request_ibi(struct i3c_dev_desc *dev,
1588 const struct i3c_ibi_setup *req)
1589 {
1590 struct i3c_master_controller *m = i3c_dev_get_master(dev);
1591 struct svc_i3c_master *master = to_svc_i3c_master(m);
1592 struct svc_i3c_i2c_dev_data *data = i3c_dev_get_master_data(dev);
1593 unsigned long flags;
1594 unsigned int i;
1595
1596 if (dev->ibi->max_payload_len > SVC_I3C_FIFO_SIZE) {
1597 dev_err(master->dev, "IBI max payload %d should be < %d\n",
1598 dev->ibi->max_payload_len, SVC_I3C_FIFO_SIZE);
1599 return -ERANGE;
1600 }
1601
1602 data->ibi_pool = i3c_generic_ibi_alloc_pool(dev, req);
1603 if (IS_ERR(data->ibi_pool))
1604 return PTR_ERR(data->ibi_pool);
1605
1606 spin_lock_irqsave(&master->ibi.lock, flags);
1607 for (i = 0; i < master->ibi.num_slots; i++) {
1608 if (!master->ibi.slots[i]) {
1609 data->ibi = i;
1610 master->ibi.slots[i] = dev;
1611 break;
1612 }
1613 }
1614 spin_unlock_irqrestore(&master->ibi.lock, flags);
1615
1616 if (i < master->ibi.num_slots)
1617 return 0;
1618
1619 i3c_generic_ibi_free_pool(data->ibi_pool);
1620 data->ibi_pool = NULL;
1621
1622 return -ENOSPC;
1623 }
1624
svc_i3c_master_free_ibi(struct i3c_dev_desc * dev)1625 static void svc_i3c_master_free_ibi(struct i3c_dev_desc *dev)
1626 {
1627 struct i3c_master_controller *m = i3c_dev_get_master(dev);
1628 struct svc_i3c_master *master = to_svc_i3c_master(m);
1629 struct svc_i3c_i2c_dev_data *data = i3c_dev_get_master_data(dev);
1630 unsigned long flags;
1631
1632 spin_lock_irqsave(&master->ibi.lock, flags);
1633 master->ibi.slots[data->ibi] = NULL;
1634 data->ibi = -1;
1635 spin_unlock_irqrestore(&master->ibi.lock, flags);
1636
1637 i3c_generic_ibi_free_pool(data->ibi_pool);
1638 }
1639
svc_i3c_master_enable_ibi(struct i3c_dev_desc * dev)1640 static int svc_i3c_master_enable_ibi(struct i3c_dev_desc *dev)
1641 {
1642 struct i3c_master_controller *m = i3c_dev_get_master(dev);
1643 struct svc_i3c_master *master = to_svc_i3c_master(m);
1644 int ret;
1645
1646 ret = pm_runtime_resume_and_get(master->dev);
1647 if (ret < 0) {
1648 dev_err(master->dev, "<%s> Cannot get runtime PM.\n", __func__);
1649 return ret;
1650 }
1651
1652 master->enabled_events++;
1653 svc_i3c_master_enable_interrupts(master, SVC_I3C_MINT_SLVSTART);
1654
1655 return i3c_master_enec_locked(m, dev->info.dyn_addr, I3C_CCC_EVENT_SIR);
1656 }
1657
svc_i3c_master_disable_ibi(struct i3c_dev_desc * dev)1658 static int svc_i3c_master_disable_ibi(struct i3c_dev_desc *dev)
1659 {
1660 struct i3c_master_controller *m = i3c_dev_get_master(dev);
1661 struct svc_i3c_master *master = to_svc_i3c_master(m);
1662 int ret;
1663
1664 master->enabled_events--;
1665 if (!master->enabled_events)
1666 svc_i3c_master_disable_interrupts(master);
1667
1668 ret = i3c_master_disec_locked(m, dev->info.dyn_addr, I3C_CCC_EVENT_SIR);
1669
1670 pm_runtime_mark_last_busy(master->dev);
1671 pm_runtime_put_autosuspend(master->dev);
1672
1673 return ret;
1674 }
1675
svc_i3c_master_enable_hotjoin(struct i3c_master_controller * m)1676 static int svc_i3c_master_enable_hotjoin(struct i3c_master_controller *m)
1677 {
1678 struct svc_i3c_master *master = to_svc_i3c_master(m);
1679 int ret;
1680
1681 ret = pm_runtime_resume_and_get(master->dev);
1682 if (ret < 0) {
1683 dev_err(master->dev, "<%s> Cannot get runtime PM.\n", __func__);
1684 return ret;
1685 }
1686
1687 master->enabled_events |= SVC_I3C_EVENT_HOTJOIN;
1688
1689 svc_i3c_master_enable_interrupts(master, SVC_I3C_MINT_SLVSTART);
1690
1691 return 0;
1692 }
1693
svc_i3c_master_disable_hotjoin(struct i3c_master_controller * m)1694 static int svc_i3c_master_disable_hotjoin(struct i3c_master_controller *m)
1695 {
1696 struct svc_i3c_master *master = to_svc_i3c_master(m);
1697
1698 master->enabled_events &= ~SVC_I3C_EVENT_HOTJOIN;
1699
1700 if (!master->enabled_events)
1701 svc_i3c_master_disable_interrupts(master);
1702
1703 pm_runtime_mark_last_busy(master->dev);
1704 pm_runtime_put_autosuspend(master->dev);
1705
1706 return 0;
1707 }
1708
svc_i3c_master_recycle_ibi_slot(struct i3c_dev_desc * dev,struct i3c_ibi_slot * slot)1709 static void svc_i3c_master_recycle_ibi_slot(struct i3c_dev_desc *dev,
1710 struct i3c_ibi_slot *slot)
1711 {
1712 struct svc_i3c_i2c_dev_data *data = i3c_dev_get_master_data(dev);
1713
1714 i3c_generic_ibi_recycle_slot(data->ibi_pool, slot);
1715 }
1716
1717 static const struct i3c_master_controller_ops svc_i3c_master_ops = {
1718 .bus_init = svc_i3c_master_bus_init,
1719 .bus_cleanup = svc_i3c_master_bus_cleanup,
1720 .attach_i3c_dev = svc_i3c_master_attach_i3c_dev,
1721 .detach_i3c_dev = svc_i3c_master_detach_i3c_dev,
1722 .reattach_i3c_dev = svc_i3c_master_reattach_i3c_dev,
1723 .attach_i2c_dev = svc_i3c_master_attach_i2c_dev,
1724 .detach_i2c_dev = svc_i3c_master_detach_i2c_dev,
1725 .do_daa = svc_i3c_master_do_daa,
1726 .supports_ccc_cmd = svc_i3c_master_supports_ccc_cmd,
1727 .send_ccc_cmd = svc_i3c_master_send_ccc_cmd,
1728 .priv_xfers = svc_i3c_master_priv_xfers,
1729 .i2c_xfers = svc_i3c_master_i2c_xfers,
1730 .request_ibi = svc_i3c_master_request_ibi,
1731 .free_ibi = svc_i3c_master_free_ibi,
1732 .recycle_ibi_slot = svc_i3c_master_recycle_ibi_slot,
1733 .enable_ibi = svc_i3c_master_enable_ibi,
1734 .disable_ibi = svc_i3c_master_disable_ibi,
1735 .enable_hotjoin = svc_i3c_master_enable_hotjoin,
1736 .disable_hotjoin = svc_i3c_master_disable_hotjoin,
1737 .set_speed = svc_i3c_master_set_speed,
1738 };
1739
svc_i3c_master_prepare_clks(struct svc_i3c_master * master)1740 static int svc_i3c_master_prepare_clks(struct svc_i3c_master *master)
1741 {
1742 int ret = 0;
1743
1744 ret = clk_prepare_enable(master->pclk);
1745 if (ret)
1746 return ret;
1747
1748 ret = clk_prepare_enable(master->fclk);
1749 if (ret) {
1750 clk_disable_unprepare(master->pclk);
1751 return ret;
1752 }
1753
1754 ret = clk_prepare_enable(master->sclk);
1755 if (ret) {
1756 clk_disable_unprepare(master->pclk);
1757 clk_disable_unprepare(master->fclk);
1758 return ret;
1759 }
1760
1761 return 0;
1762 }
1763
svc_i3c_master_unprepare_clks(struct svc_i3c_master * master)1764 static void svc_i3c_master_unprepare_clks(struct svc_i3c_master *master)
1765 {
1766 clk_disable_unprepare(master->pclk);
1767 clk_disable_unprepare(master->fclk);
1768 clk_disable_unprepare(master->sclk);
1769 }
1770
svc_i3c_master_probe(struct platform_device * pdev)1771 static int svc_i3c_master_probe(struct platform_device *pdev)
1772 {
1773 struct device *dev = &pdev->dev;
1774 struct svc_i3c_master *master;
1775 int ret;
1776
1777 master = devm_kzalloc(dev, sizeof(*master), GFP_KERNEL);
1778 if (!master)
1779 return -ENOMEM;
1780
1781 master->drvdata = of_device_get_match_data(dev);
1782 if (!master->drvdata)
1783 return -EINVAL;
1784
1785 master->regs = devm_platform_ioremap_resource(pdev, 0);
1786 if (IS_ERR(master->regs))
1787 return PTR_ERR(master->regs);
1788
1789 master->pclk = devm_clk_get(dev, "pclk");
1790 if (IS_ERR(master->pclk))
1791 return PTR_ERR(master->pclk);
1792
1793 master->fclk = devm_clk_get(dev, "fast_clk");
1794 if (IS_ERR(master->fclk))
1795 return PTR_ERR(master->fclk);
1796
1797 master->sclk = devm_clk_get(dev, "slow_clk");
1798 if (IS_ERR(master->sclk))
1799 return PTR_ERR(master->sclk);
1800
1801 master->irq = platform_get_irq(pdev, 0);
1802 if (master->irq < 0)
1803 return master->irq;
1804
1805 master->dev = dev;
1806
1807 ret = svc_i3c_master_prepare_clks(master);
1808 if (ret)
1809 return ret;
1810
1811 INIT_WORK(&master->hj_work, svc_i3c_master_hj_work);
1812 INIT_WORK(&master->ibi_work, svc_i3c_master_ibi_work);
1813 mutex_init(&master->lock);
1814
1815 ret = devm_request_irq(dev, master->irq, svc_i3c_master_irq_handler,
1816 IRQF_NO_SUSPEND, "svc-i3c-irq", master);
1817 if (ret)
1818 goto err_disable_clks;
1819
1820 master->free_slots = GENMASK(SVC_I3C_MAX_DEVS - 1, 0);
1821
1822 spin_lock_init(&master->xferqueue.lock);
1823 INIT_LIST_HEAD(&master->xferqueue.list);
1824
1825 spin_lock_init(&master->ibi.lock);
1826 master->ibi.num_slots = SVC_I3C_MAX_DEVS;
1827 master->ibi.slots = devm_kcalloc(&pdev->dev, master->ibi.num_slots,
1828 sizeof(*master->ibi.slots),
1829 GFP_KERNEL);
1830 if (!master->ibi.slots) {
1831 ret = -ENOMEM;
1832 goto err_disable_clks;
1833 }
1834
1835 platform_set_drvdata(pdev, master);
1836
1837 pm_runtime_set_autosuspend_delay(&pdev->dev, SVC_I3C_PM_TIMEOUT_MS);
1838 pm_runtime_use_autosuspend(&pdev->dev);
1839 pm_runtime_get_noresume(&pdev->dev);
1840 pm_runtime_set_active(&pdev->dev);
1841 pm_runtime_enable(&pdev->dev);
1842
1843 svc_i3c_master_reset(master);
1844
1845 /* Register the master */
1846 ret = i3c_master_register(&master->base, &pdev->dev,
1847 &svc_i3c_master_ops, false);
1848 if (ret)
1849 goto rpm_disable;
1850
1851 pm_runtime_mark_last_busy(&pdev->dev);
1852 pm_runtime_put_autosuspend(&pdev->dev);
1853
1854 return 0;
1855
1856 rpm_disable:
1857 pm_runtime_dont_use_autosuspend(&pdev->dev);
1858 pm_runtime_put_noidle(&pdev->dev);
1859 pm_runtime_disable(&pdev->dev);
1860 pm_runtime_set_suspended(&pdev->dev);
1861
1862 err_disable_clks:
1863 svc_i3c_master_unprepare_clks(master);
1864
1865 return ret;
1866 }
1867
svc_i3c_master_remove(struct platform_device * pdev)1868 static void svc_i3c_master_remove(struct platform_device *pdev)
1869 {
1870 struct svc_i3c_master *master = platform_get_drvdata(pdev);
1871
1872 cancel_work_sync(&master->hj_work);
1873 i3c_master_unregister(&master->base);
1874
1875 pm_runtime_dont_use_autosuspend(&pdev->dev);
1876 pm_runtime_disable(&pdev->dev);
1877 }
1878
svc_i3c_save_regs(struct svc_i3c_master * master)1879 static void svc_i3c_save_regs(struct svc_i3c_master *master)
1880 {
1881 master->saved_regs.mconfig = readl(master->regs + SVC_I3C_MCONFIG);
1882 master->saved_regs.mdynaddr = readl(master->regs + SVC_I3C_MDYNADDR);
1883 }
1884
svc_i3c_restore_regs(struct svc_i3c_master * master)1885 static void svc_i3c_restore_regs(struct svc_i3c_master *master)
1886 {
1887 if (readl(master->regs + SVC_I3C_MDYNADDR) !=
1888 master->saved_regs.mdynaddr) {
1889 writel(master->saved_regs.mconfig,
1890 master->regs + SVC_I3C_MCONFIG);
1891 writel(master->saved_regs.mdynaddr,
1892 master->regs + SVC_I3C_MDYNADDR);
1893 }
1894 }
1895
svc_i3c_runtime_suspend(struct device * dev)1896 static int __maybe_unused svc_i3c_runtime_suspend(struct device *dev)
1897 {
1898 struct svc_i3c_master *master = dev_get_drvdata(dev);
1899
1900 svc_i3c_save_regs(master);
1901 svc_i3c_master_unprepare_clks(master);
1902 pinctrl_pm_select_sleep_state(dev);
1903
1904 return 0;
1905 }
1906
svc_i3c_runtime_resume(struct device * dev)1907 static int __maybe_unused svc_i3c_runtime_resume(struct device *dev)
1908 {
1909 struct svc_i3c_master *master = dev_get_drvdata(dev);
1910
1911 pinctrl_pm_select_default_state(dev);
1912 svc_i3c_master_prepare_clks(master);
1913
1914 svc_i3c_restore_regs(master);
1915
1916 return 0;
1917 }
1918
1919 static const struct dev_pm_ops svc_i3c_pm_ops = {
1920 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
1921 pm_runtime_force_resume)
1922 SET_RUNTIME_PM_OPS(svc_i3c_runtime_suspend,
1923 svc_i3c_runtime_resume, NULL)
1924 };
1925
1926 static const struct svc_i3c_drvdata npcm845_drvdata = {};
1927
1928 static const struct svc_i3c_drvdata svc_default_drvdata = {};
1929
1930 static const struct of_device_id svc_i3c_master_of_match_tbl[] = {
1931 { .compatible = "nuvoton,npcm845-i3c", .data = &npcm845_drvdata },
1932 { .compatible = "silvaco,i3c-master-v1", .data = &svc_default_drvdata },
1933 { /* sentinel */ },
1934 };
1935 MODULE_DEVICE_TABLE(of, svc_i3c_master_of_match_tbl);
1936
1937 static struct platform_driver svc_i3c_master = {
1938 .probe = svc_i3c_master_probe,
1939 .remove_new = svc_i3c_master_remove,
1940 .driver = {
1941 .name = "silvaco-i3c-master",
1942 .of_match_table = svc_i3c_master_of_match_tbl,
1943 .pm = &svc_i3c_pm_ops,
1944 },
1945 };
1946 module_platform_driver(svc_i3c_master);
1947
1948 MODULE_AUTHOR("Conor Culhane <conor.culhane@silvaco.com>");
1949 MODULE_AUTHOR("Miquel Raynal <miquel.raynal@bootlin.com>");
1950 MODULE_DESCRIPTION("Silvaco dual-role I3C master driver");
1951 MODULE_LICENSE("GPL v2");
1952