1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2021 Analog Devices, Inc.
4 * Author: Cosmin Tanislav <cosmin.tanislav@analog.com>
5 */
6
7 #include <linux/bitfield.h>
8 #include <linux/bitops.h>
9 #include <linux/iio/buffer.h>
10 #include <linux/iio/events.h>
11 #include <linux/iio/iio.h>
12 #include <linux/iio/kfifo_buf.h>
13 #include <linux/iio/sysfs.h>
14 #include <linux/interrupt.h>
15 #include <linux/irq.h>
16 #include <linux/mod_devicetable.h>
17 #include <linux/regmap.h>
18 #include <linux/regulator/consumer.h>
19 #include <linux/unaligned.h>
20
21 #include "adxl367.h"
22
23 #define ADXL367_REG_DEVID 0x00
24 #define ADXL367_DEVID_AD 0xAD
25
26 #define ADXL367_REG_STATUS 0x0B
27 #define ADXL367_STATUS_INACT_MASK BIT(5)
28 #define ADXL367_STATUS_ACT_MASK BIT(4)
29 #define ADXL367_STATUS_FIFO_FULL_MASK BIT(2)
30
31 #define ADXL367_FIFO_ENT_H_MASK GENMASK(1, 0)
32
33 #define ADXL367_REG_X_DATA_H 0x0E
34 #define ADXL367_REG_Y_DATA_H 0x10
35 #define ADXL367_REG_Z_DATA_H 0x12
36 #define ADXL367_REG_TEMP_DATA_H 0x14
37 #define ADXL367_REG_EX_ADC_DATA_H 0x16
38 #define ADXL367_DATA_MASK GENMASK(15, 2)
39
40 #define ADXL367_TEMP_25C 165
41 #define ADXL367_TEMP_PER_C 54
42
43 #define ADXL367_VOLTAGE_OFFSET 8192
44 #define ADXL367_VOLTAGE_MAX_MV 1000
45 #define ADXL367_VOLTAGE_MAX_RAW GENMASK(13, 0)
46
47 #define ADXL367_REG_RESET 0x1F
48 #define ADXL367_RESET_CODE 0x52
49
50 #define ADXL367_REG_THRESH_ACT_H 0x20
51 #define ADXL367_REG_THRESH_INACT_H 0x23
52 #define ADXL367_THRESH_MAX GENMASK(12, 0)
53 #define ADXL367_THRESH_VAL_H_MASK GENMASK(12, 6)
54 #define ADXL367_THRESH_H_MASK GENMASK(6, 0)
55 #define ADXL367_THRESH_VAL_L_MASK GENMASK(5, 0)
56 #define ADXL367_THRESH_L_MASK GENMASK(7, 2)
57
58 #define ADXL367_REG_TIME_ACT 0x22
59 #define ADXL367_REG_TIME_INACT_H 0x25
60 #define ADXL367_TIME_ACT_MAX GENMASK(7, 0)
61 #define ADXL367_TIME_INACT_MAX GENMASK(15, 0)
62 #define ADXL367_TIME_INACT_VAL_H_MASK GENMASK(15, 8)
63 #define ADXL367_TIME_INACT_H_MASK GENMASK(7, 0)
64 #define ADXL367_TIME_INACT_VAL_L_MASK GENMASK(7, 0)
65 #define ADXL367_TIME_INACT_L_MASK GENMASK(7, 0)
66
67 #define ADXL367_REG_ACT_INACT_CTL 0x27
68 #define ADXL367_ACT_EN_MASK GENMASK(1, 0)
69 #define ADXL367_ACT_LINKLOOP_MASK GENMASK(5, 4)
70
71 #define ADXL367_REG_FIFO_CTL 0x28
72 #define ADXL367_FIFO_CTL_FORMAT_MASK GENMASK(6, 3)
73 #define ADXL367_FIFO_CTL_MODE_MASK GENMASK(1, 0)
74
75 #define ADXL367_REG_FIFO_SAMPLES 0x29
76 #define ADXL367_FIFO_SIZE 512
77 #define ADXL367_FIFO_MAX_WATERMARK 511
78
79 #define ADXL367_SAMPLES_VAL_H_MASK BIT(8)
80 #define ADXL367_SAMPLES_H_MASK BIT(2)
81 #define ADXL367_SAMPLES_VAL_L_MASK GENMASK(7, 0)
82 #define ADXL367_SAMPLES_L_MASK GENMASK(7, 0)
83
84 #define ADXL367_REG_INT1_MAP 0x2A
85 #define ADXL367_INT_INACT_MASK BIT(5)
86 #define ADXL367_INT_ACT_MASK BIT(4)
87 #define ADXL367_INT_FIFO_WATERMARK_MASK BIT(2)
88
89 #define ADXL367_REG_FILTER_CTL 0x2C
90 #define ADXL367_FILTER_CTL_RANGE_MASK GENMASK(7, 6)
91 #define ADXL367_2G_RANGE_1G 4095
92 #define ADXL367_2G_RANGE_100MG 409
93 #define ADXL367_FILTER_CTL_ODR_MASK GENMASK(2, 0)
94
95 #define ADXL367_REG_POWER_CTL 0x2D
96 #define ADXL367_POWER_CTL_MODE_MASK GENMASK(1, 0)
97
98 #define ADXL367_REG_ADC_CTL 0x3C
99 #define ADXL367_REG_TEMP_CTL 0x3D
100 #define ADXL367_ADC_EN_MASK BIT(0)
101
102 enum adxl367_range {
103 ADXL367_2G_RANGE,
104 ADXL367_4G_RANGE,
105 ADXL367_8G_RANGE,
106 };
107
108 enum adxl367_fifo_mode {
109 ADXL367_FIFO_MODE_DISABLED = 0b00,
110 ADXL367_FIFO_MODE_STREAM = 0b10,
111 };
112
113 enum adxl367_fifo_format {
114 ADXL367_FIFO_FORMAT_XYZ,
115 ADXL367_FIFO_FORMAT_X,
116 ADXL367_FIFO_FORMAT_Y,
117 ADXL367_FIFO_FORMAT_Z,
118 ADXL367_FIFO_FORMAT_XYZT,
119 ADXL367_FIFO_FORMAT_XT,
120 ADXL367_FIFO_FORMAT_YT,
121 ADXL367_FIFO_FORMAT_ZT,
122 ADXL367_FIFO_FORMAT_XYZA,
123 ADXL367_FIFO_FORMAT_XA,
124 ADXL367_FIFO_FORMAT_YA,
125 ADXL367_FIFO_FORMAT_ZA,
126 };
127
128 enum adxl367_op_mode {
129 ADXL367_OP_STANDBY = 0b00,
130 ADXL367_OP_MEASURE = 0b10,
131 };
132
133 enum adxl367_act_proc_mode {
134 ADXL367_LOOPED = 0b11,
135 };
136
137 enum adxl367_act_en_mode {
138 ADXL367_ACT_DISABLED = 0b00,
139 ADCL367_ACT_REF_ENABLED = 0b11,
140 };
141
142 enum adxl367_activity_type {
143 ADXL367_ACTIVITY,
144 ADXL367_INACTIVITY,
145 };
146
147 enum adxl367_odr {
148 ADXL367_ODR_12P5HZ,
149 ADXL367_ODR_25HZ,
150 ADXL367_ODR_50HZ,
151 ADXL367_ODR_100HZ,
152 ADXL367_ODR_200HZ,
153 ADXL367_ODR_400HZ,
154 };
155
156 struct adxl367_state {
157 const struct adxl367_ops *ops;
158 void *context;
159
160 struct device *dev;
161 struct regmap *regmap;
162
163 /*
164 * Synchronize access to members of driver state, and ensure atomicity
165 * of consecutive regmap operations.
166 */
167 struct mutex lock;
168
169 enum adxl367_odr odr;
170 enum adxl367_range range;
171
172 unsigned int act_threshold;
173 unsigned int act_time_ms;
174 unsigned int inact_threshold;
175 unsigned int inact_time_ms;
176
177 unsigned int fifo_set_size;
178 unsigned int fifo_watermark;
179
180 __be16 fifo_buf[ADXL367_FIFO_SIZE] __aligned(IIO_DMA_MINALIGN);
181 __be16 sample_buf;
182 u8 act_threshold_buf[2];
183 u8 inact_time_buf[2];
184 u8 status_buf[3];
185 };
186
187 static const unsigned int adxl367_threshold_h_reg_tbl[] = {
188 [ADXL367_ACTIVITY] = ADXL367_REG_THRESH_ACT_H,
189 [ADXL367_INACTIVITY] = ADXL367_REG_THRESH_INACT_H,
190 };
191
192 static const unsigned int adxl367_act_en_shift_tbl[] = {
193 [ADXL367_ACTIVITY] = 0,
194 [ADXL367_INACTIVITY] = 2,
195 };
196
197 static const unsigned int adxl367_act_int_mask_tbl[] = {
198 [ADXL367_ACTIVITY] = ADXL367_INT_ACT_MASK,
199 [ADXL367_INACTIVITY] = ADXL367_INT_INACT_MASK,
200 };
201
202 static const int adxl367_samp_freq_tbl[][2] = {
203 [ADXL367_ODR_12P5HZ] = {12, 500000},
204 [ADXL367_ODR_25HZ] = {25, 0},
205 [ADXL367_ODR_50HZ] = {50, 0},
206 [ADXL367_ODR_100HZ] = {100, 0},
207 [ADXL367_ODR_200HZ] = {200, 0},
208 [ADXL367_ODR_400HZ] = {400, 0},
209 };
210
211 /* (g * 2) * 9.80665 * 1000000 / (2^14 - 1) */
212 static const int adxl367_range_scale_tbl[][2] = {
213 [ADXL367_2G_RANGE] = {0, 2394347},
214 [ADXL367_4G_RANGE] = {0, 4788695},
215 [ADXL367_8G_RANGE] = {0, 9577391},
216 };
217
218 static const int adxl367_range_scale_factor_tbl[] = {
219 [ADXL367_2G_RANGE] = 1,
220 [ADXL367_4G_RANGE] = 2,
221 [ADXL367_8G_RANGE] = 4,
222 };
223
224 enum {
225 ADXL367_X_CHANNEL_INDEX,
226 ADXL367_Y_CHANNEL_INDEX,
227 ADXL367_Z_CHANNEL_INDEX,
228 ADXL367_TEMP_CHANNEL_INDEX,
229 ADXL367_EX_ADC_CHANNEL_INDEX
230 };
231
232 #define ADXL367_X_CHANNEL_MASK BIT(ADXL367_X_CHANNEL_INDEX)
233 #define ADXL367_Y_CHANNEL_MASK BIT(ADXL367_Y_CHANNEL_INDEX)
234 #define ADXL367_Z_CHANNEL_MASK BIT(ADXL367_Z_CHANNEL_INDEX)
235 #define ADXL367_TEMP_CHANNEL_MASK BIT(ADXL367_TEMP_CHANNEL_INDEX)
236 #define ADXL367_EX_ADC_CHANNEL_MASK BIT(ADXL367_EX_ADC_CHANNEL_INDEX)
237
238 static const enum adxl367_fifo_format adxl367_fifo_formats[] = {
239 ADXL367_FIFO_FORMAT_X,
240 ADXL367_FIFO_FORMAT_Y,
241 ADXL367_FIFO_FORMAT_Z,
242 ADXL367_FIFO_FORMAT_XT,
243 ADXL367_FIFO_FORMAT_YT,
244 ADXL367_FIFO_FORMAT_ZT,
245 ADXL367_FIFO_FORMAT_XA,
246 ADXL367_FIFO_FORMAT_YA,
247 ADXL367_FIFO_FORMAT_ZA,
248 ADXL367_FIFO_FORMAT_XYZ,
249 ADXL367_FIFO_FORMAT_XYZT,
250 ADXL367_FIFO_FORMAT_XYZA,
251 };
252
253 static const unsigned long adxl367_channel_masks[] = {
254 ADXL367_X_CHANNEL_MASK,
255 ADXL367_Y_CHANNEL_MASK,
256 ADXL367_Z_CHANNEL_MASK,
257 ADXL367_X_CHANNEL_MASK | ADXL367_TEMP_CHANNEL_MASK,
258 ADXL367_Y_CHANNEL_MASK | ADXL367_TEMP_CHANNEL_MASK,
259 ADXL367_Z_CHANNEL_MASK | ADXL367_TEMP_CHANNEL_MASK,
260 ADXL367_X_CHANNEL_MASK | ADXL367_EX_ADC_CHANNEL_MASK,
261 ADXL367_Y_CHANNEL_MASK | ADXL367_EX_ADC_CHANNEL_MASK,
262 ADXL367_Z_CHANNEL_MASK | ADXL367_EX_ADC_CHANNEL_MASK,
263 ADXL367_X_CHANNEL_MASK | ADXL367_Y_CHANNEL_MASK | ADXL367_Z_CHANNEL_MASK,
264 ADXL367_X_CHANNEL_MASK | ADXL367_Y_CHANNEL_MASK | ADXL367_Z_CHANNEL_MASK |
265 ADXL367_TEMP_CHANNEL_MASK,
266 ADXL367_X_CHANNEL_MASK | ADXL367_Y_CHANNEL_MASK | ADXL367_Z_CHANNEL_MASK |
267 ADXL367_EX_ADC_CHANNEL_MASK,
268 0,
269 };
270
adxl367_set_measure_en(struct adxl367_state * st,bool en)271 static int adxl367_set_measure_en(struct adxl367_state *st, bool en)
272 {
273 enum adxl367_op_mode op_mode = en ? ADXL367_OP_MEASURE
274 : ADXL367_OP_STANDBY;
275 int ret;
276
277 ret = regmap_update_bits(st->regmap, ADXL367_REG_POWER_CTL,
278 ADXL367_POWER_CTL_MODE_MASK,
279 FIELD_PREP(ADXL367_POWER_CTL_MODE_MASK,
280 op_mode));
281 if (ret)
282 return ret;
283
284 /*
285 * Wait for acceleration output to settle after entering
286 * measure mode.
287 */
288 if (en)
289 msleep(100);
290
291 return 0;
292 }
293
adxl367_scale_act_thresholds(struct adxl367_state * st,enum adxl367_range old_range,enum adxl367_range new_range)294 static void adxl367_scale_act_thresholds(struct adxl367_state *st,
295 enum adxl367_range old_range,
296 enum adxl367_range new_range)
297 {
298 st->act_threshold = st->act_threshold
299 * adxl367_range_scale_factor_tbl[old_range]
300 / adxl367_range_scale_factor_tbl[new_range];
301 st->inact_threshold = st->inact_threshold
302 * adxl367_range_scale_factor_tbl[old_range]
303 / adxl367_range_scale_factor_tbl[new_range];
304 }
305
_adxl367_set_act_threshold(struct adxl367_state * st,enum adxl367_activity_type act,unsigned int threshold)306 static int _adxl367_set_act_threshold(struct adxl367_state *st,
307 enum adxl367_activity_type act,
308 unsigned int threshold)
309 {
310 u8 reg = adxl367_threshold_h_reg_tbl[act];
311 int ret;
312
313 if (threshold > ADXL367_THRESH_MAX)
314 return -EINVAL;
315
316 st->act_threshold_buf[0] = FIELD_PREP(ADXL367_THRESH_H_MASK,
317 FIELD_GET(ADXL367_THRESH_VAL_H_MASK,
318 threshold));
319 st->act_threshold_buf[1] = FIELD_PREP(ADXL367_THRESH_L_MASK,
320 FIELD_GET(ADXL367_THRESH_VAL_L_MASK,
321 threshold));
322
323 ret = regmap_bulk_write(st->regmap, reg, st->act_threshold_buf,
324 sizeof(st->act_threshold_buf));
325 if (ret)
326 return ret;
327
328 if (act == ADXL367_ACTIVITY)
329 st->act_threshold = threshold;
330 else
331 st->inact_threshold = threshold;
332
333 return 0;
334 }
335
adxl367_set_act_threshold(struct adxl367_state * st,enum adxl367_activity_type act,unsigned int threshold)336 static int adxl367_set_act_threshold(struct adxl367_state *st,
337 enum adxl367_activity_type act,
338 unsigned int threshold)
339 {
340 int ret;
341
342 guard(mutex)(&st->lock);
343
344 ret = adxl367_set_measure_en(st, false);
345 if (ret)
346 return ret;
347
348 ret = _adxl367_set_act_threshold(st, act, threshold);
349 if (ret)
350 return ret;
351
352 return adxl367_set_measure_en(st, true);
353 }
354
adxl367_set_act_proc_mode(struct adxl367_state * st,enum adxl367_act_proc_mode mode)355 static int adxl367_set_act_proc_mode(struct adxl367_state *st,
356 enum adxl367_act_proc_mode mode)
357 {
358 return regmap_update_bits(st->regmap, ADXL367_REG_ACT_INACT_CTL,
359 ADXL367_ACT_LINKLOOP_MASK,
360 FIELD_PREP(ADXL367_ACT_LINKLOOP_MASK,
361 mode));
362 }
363
adxl367_set_act_interrupt_en(struct adxl367_state * st,enum adxl367_activity_type act,bool en)364 static int adxl367_set_act_interrupt_en(struct adxl367_state *st,
365 enum adxl367_activity_type act,
366 bool en)
367 {
368 unsigned int mask = adxl367_act_int_mask_tbl[act];
369
370 return regmap_update_bits(st->regmap, ADXL367_REG_INT1_MAP,
371 mask, en ? mask : 0);
372 }
373
adxl367_get_act_interrupt_en(struct adxl367_state * st,enum adxl367_activity_type act,bool * en)374 static int adxl367_get_act_interrupt_en(struct adxl367_state *st,
375 enum adxl367_activity_type act,
376 bool *en)
377 {
378 unsigned int mask = adxl367_act_int_mask_tbl[act];
379 unsigned int val;
380 int ret;
381
382 ret = regmap_read(st->regmap, ADXL367_REG_INT1_MAP, &val);
383 if (ret)
384 return ret;
385
386 *en = !!(val & mask);
387
388 return 0;
389 }
390
adxl367_set_act_en(struct adxl367_state * st,enum adxl367_activity_type act,enum adxl367_act_en_mode en)391 static int adxl367_set_act_en(struct adxl367_state *st,
392 enum adxl367_activity_type act,
393 enum adxl367_act_en_mode en)
394 {
395 unsigned int ctl_shift = adxl367_act_en_shift_tbl[act];
396
397 return regmap_update_bits(st->regmap, ADXL367_REG_ACT_INACT_CTL,
398 ADXL367_ACT_EN_MASK << ctl_shift,
399 en << ctl_shift);
400 }
401
adxl367_set_fifo_watermark_interrupt_en(struct adxl367_state * st,bool en)402 static int adxl367_set_fifo_watermark_interrupt_en(struct adxl367_state *st,
403 bool en)
404 {
405 return regmap_update_bits(st->regmap, ADXL367_REG_INT1_MAP,
406 ADXL367_INT_FIFO_WATERMARK_MASK,
407 en ? ADXL367_INT_FIFO_WATERMARK_MASK : 0);
408 }
409
adxl367_get_fifo_mode(struct adxl367_state * st,enum adxl367_fifo_mode * fifo_mode)410 static int adxl367_get_fifo_mode(struct adxl367_state *st,
411 enum adxl367_fifo_mode *fifo_mode)
412 {
413 unsigned int val;
414 int ret;
415
416 ret = regmap_read(st->regmap, ADXL367_REG_FIFO_CTL, &val);
417 if (ret)
418 return ret;
419
420 *fifo_mode = FIELD_GET(ADXL367_FIFO_CTL_MODE_MASK, val);
421
422 return 0;
423 }
424
adxl367_set_fifo_mode(struct adxl367_state * st,enum adxl367_fifo_mode fifo_mode)425 static int adxl367_set_fifo_mode(struct adxl367_state *st,
426 enum adxl367_fifo_mode fifo_mode)
427 {
428 return regmap_update_bits(st->regmap, ADXL367_REG_FIFO_CTL,
429 ADXL367_FIFO_CTL_MODE_MASK,
430 FIELD_PREP(ADXL367_FIFO_CTL_MODE_MASK,
431 fifo_mode));
432 }
433
adxl367_set_fifo_format(struct adxl367_state * st,enum adxl367_fifo_format fifo_format)434 static int adxl367_set_fifo_format(struct adxl367_state *st,
435 enum adxl367_fifo_format fifo_format)
436 {
437 return regmap_update_bits(st->regmap, ADXL367_REG_FIFO_CTL,
438 ADXL367_FIFO_CTL_FORMAT_MASK,
439 FIELD_PREP(ADXL367_FIFO_CTL_FORMAT_MASK,
440 fifo_format));
441 }
442
adxl367_set_fifo_watermark(struct adxl367_state * st,unsigned int fifo_watermark)443 static int adxl367_set_fifo_watermark(struct adxl367_state *st,
444 unsigned int fifo_watermark)
445 {
446 unsigned int fifo_samples = fifo_watermark * st->fifo_set_size;
447 unsigned int fifo_samples_h, fifo_samples_l;
448 int ret;
449
450 if (fifo_samples > ADXL367_FIFO_MAX_WATERMARK)
451 fifo_samples = ADXL367_FIFO_MAX_WATERMARK;
452
453 fifo_samples /= st->fifo_set_size;
454
455 fifo_samples_h = FIELD_PREP(ADXL367_SAMPLES_H_MASK,
456 FIELD_GET(ADXL367_SAMPLES_VAL_H_MASK,
457 fifo_samples));
458 fifo_samples_l = FIELD_PREP(ADXL367_SAMPLES_L_MASK,
459 FIELD_GET(ADXL367_SAMPLES_VAL_L_MASK,
460 fifo_samples));
461
462 ret = regmap_update_bits(st->regmap, ADXL367_REG_FIFO_CTL,
463 ADXL367_SAMPLES_H_MASK, fifo_samples_h);
464 if (ret)
465 return ret;
466
467 ret = regmap_update_bits(st->regmap, ADXL367_REG_FIFO_SAMPLES,
468 ADXL367_SAMPLES_L_MASK, fifo_samples_l);
469 if (ret)
470 return ret;
471
472 st->fifo_watermark = fifo_watermark;
473
474 return 0;
475 }
476
adxl367_set_range(struct iio_dev * indio_dev,enum adxl367_range range)477 static int adxl367_set_range(struct iio_dev *indio_dev,
478 enum adxl367_range range)
479 {
480 iio_device_claim_direct_scoped(return -EBUSY, indio_dev) {
481 struct adxl367_state *st = iio_priv(indio_dev);
482 int ret;
483
484 guard(mutex)(&st->lock);
485
486 ret = adxl367_set_measure_en(st, false);
487 if (ret)
488 return ret;
489
490 ret = regmap_update_bits(st->regmap, ADXL367_REG_FILTER_CTL,
491 ADXL367_FILTER_CTL_RANGE_MASK,
492 FIELD_PREP(ADXL367_FILTER_CTL_RANGE_MASK,
493 range));
494 if (ret)
495 return ret;
496
497 adxl367_scale_act_thresholds(st, st->range, range);
498
499 /* Activity thresholds depend on range */
500 ret = _adxl367_set_act_threshold(st, ADXL367_ACTIVITY,
501 st->act_threshold);
502 if (ret)
503 return ret;
504
505 ret = _adxl367_set_act_threshold(st, ADXL367_INACTIVITY,
506 st->inact_threshold);
507 if (ret)
508 return ret;
509
510 ret = adxl367_set_measure_en(st, true);
511 if (ret)
512 return ret;
513
514 st->range = range;
515
516 return 0;
517 }
518 unreachable();
519 }
520
adxl367_time_ms_to_samples(struct adxl367_state * st,unsigned int ms)521 static int adxl367_time_ms_to_samples(struct adxl367_state *st, unsigned int ms)
522 {
523 int freq_hz = adxl367_samp_freq_tbl[st->odr][0];
524 int freq_microhz = adxl367_samp_freq_tbl[st->odr][1];
525 /* Scale to decihertz to prevent precision loss in 12.5Hz case. */
526 int freq_dhz = freq_hz * 10 + freq_microhz / 100000;
527
528 return DIV_ROUND_CLOSEST(ms * freq_dhz, 10000);
529 }
530
_adxl367_set_act_time_ms(struct adxl367_state * st,unsigned int ms)531 static int _adxl367_set_act_time_ms(struct adxl367_state *st, unsigned int ms)
532 {
533 unsigned int val = adxl367_time_ms_to_samples(st, ms);
534 int ret;
535
536 if (val > ADXL367_TIME_ACT_MAX)
537 val = ADXL367_TIME_ACT_MAX;
538
539 ret = regmap_write(st->regmap, ADXL367_REG_TIME_ACT, val);
540 if (ret)
541 return ret;
542
543 st->act_time_ms = ms;
544
545 return 0;
546 }
547
_adxl367_set_inact_time_ms(struct adxl367_state * st,unsigned int ms)548 static int _adxl367_set_inact_time_ms(struct adxl367_state *st, unsigned int ms)
549 {
550 unsigned int val = adxl367_time_ms_to_samples(st, ms);
551 int ret;
552
553 if (val > ADXL367_TIME_INACT_MAX)
554 val = ADXL367_TIME_INACT_MAX;
555
556 st->inact_time_buf[0] = FIELD_PREP(ADXL367_TIME_INACT_H_MASK,
557 FIELD_GET(ADXL367_TIME_INACT_VAL_H_MASK,
558 val));
559 st->inact_time_buf[1] = FIELD_PREP(ADXL367_TIME_INACT_L_MASK,
560 FIELD_GET(ADXL367_TIME_INACT_VAL_L_MASK,
561 val));
562
563 ret = regmap_bulk_write(st->regmap, ADXL367_REG_TIME_INACT_H,
564 st->inact_time_buf, sizeof(st->inact_time_buf));
565 if (ret)
566 return ret;
567
568 st->inact_time_ms = ms;
569
570 return 0;
571 }
572
adxl367_set_act_time_ms(struct adxl367_state * st,enum adxl367_activity_type act,unsigned int ms)573 static int adxl367_set_act_time_ms(struct adxl367_state *st,
574 enum adxl367_activity_type act,
575 unsigned int ms)
576 {
577 int ret;
578
579 guard(mutex)(&st->lock);
580
581 ret = adxl367_set_measure_en(st, false);
582 if (ret)
583 return ret;
584
585 if (act == ADXL367_ACTIVITY)
586 ret = _adxl367_set_act_time_ms(st, ms);
587 else
588 ret = _adxl367_set_inact_time_ms(st, ms);
589
590 if (ret)
591 return ret;
592
593 return adxl367_set_measure_en(st, true);
594 }
595
_adxl367_set_odr(struct adxl367_state * st,enum adxl367_odr odr)596 static int _adxl367_set_odr(struct adxl367_state *st, enum adxl367_odr odr)
597 {
598 int ret;
599
600 ret = regmap_update_bits(st->regmap, ADXL367_REG_FILTER_CTL,
601 ADXL367_FILTER_CTL_ODR_MASK,
602 FIELD_PREP(ADXL367_FILTER_CTL_ODR_MASK,
603 odr));
604 if (ret)
605 return ret;
606
607 st->odr = odr;
608
609 /* Activity timers depend on ODR */
610 ret = _adxl367_set_act_time_ms(st, st->act_time_ms);
611 if (ret)
612 return ret;
613
614 return _adxl367_set_inact_time_ms(st, st->inact_time_ms);
615 }
616
adxl367_set_odr(struct iio_dev * indio_dev,enum adxl367_odr odr)617 static int adxl367_set_odr(struct iio_dev *indio_dev, enum adxl367_odr odr)
618 {
619 iio_device_claim_direct_scoped(return -EBUSY, indio_dev) {
620 struct adxl367_state *st = iio_priv(indio_dev);
621 int ret;
622
623 guard(mutex)(&st->lock);
624
625 ret = adxl367_set_measure_en(st, false);
626 if (ret)
627 return ret;
628
629 ret = _adxl367_set_odr(st, odr);
630 if (ret)
631 return ret;
632
633 return adxl367_set_measure_en(st, true);
634 }
635 unreachable();
636 }
637
adxl367_set_temp_adc_en(struct adxl367_state * st,unsigned int reg,bool en)638 static int adxl367_set_temp_adc_en(struct adxl367_state *st, unsigned int reg,
639 bool en)
640 {
641 return regmap_update_bits(st->regmap, reg, ADXL367_ADC_EN_MASK,
642 en ? ADXL367_ADC_EN_MASK : 0);
643 }
644
adxl367_set_temp_adc_reg_en(struct adxl367_state * st,unsigned int reg,bool en)645 static int adxl367_set_temp_adc_reg_en(struct adxl367_state *st,
646 unsigned int reg, bool en)
647 {
648 int ret;
649
650 switch (reg) {
651 case ADXL367_REG_TEMP_DATA_H:
652 ret = adxl367_set_temp_adc_en(st, ADXL367_REG_TEMP_CTL, en);
653 break;
654 case ADXL367_REG_EX_ADC_DATA_H:
655 ret = adxl367_set_temp_adc_en(st, ADXL367_REG_ADC_CTL, en);
656 break;
657 default:
658 return 0;
659 }
660
661 if (ret)
662 return ret;
663
664 if (en)
665 msleep(100);
666
667 return 0;
668 }
669
adxl367_set_temp_adc_mask_en(struct adxl367_state * st,const unsigned long * active_scan_mask,bool en)670 static int adxl367_set_temp_adc_mask_en(struct adxl367_state *st,
671 const unsigned long *active_scan_mask,
672 bool en)
673 {
674 if (*active_scan_mask & ADXL367_TEMP_CHANNEL_MASK)
675 return adxl367_set_temp_adc_en(st, ADXL367_REG_TEMP_CTL, en);
676 else if (*active_scan_mask & ADXL367_EX_ADC_CHANNEL_MASK)
677 return adxl367_set_temp_adc_en(st, ADXL367_REG_ADC_CTL, en);
678
679 return 0;
680 }
681
adxl367_find_odr(struct adxl367_state * st,int val,int val2,enum adxl367_odr * odr)682 static int adxl367_find_odr(struct adxl367_state *st, int val, int val2,
683 enum adxl367_odr *odr)
684 {
685 size_t size = ARRAY_SIZE(adxl367_samp_freq_tbl);
686 int i;
687
688 for (i = 0; i < size; i++)
689 if (val == adxl367_samp_freq_tbl[i][0] &&
690 val2 == adxl367_samp_freq_tbl[i][1])
691 break;
692
693 if (i == size)
694 return -EINVAL;
695
696 *odr = i;
697
698 return 0;
699 }
700
adxl367_find_range(struct adxl367_state * st,int val,int val2,enum adxl367_range * range)701 static int adxl367_find_range(struct adxl367_state *st, int val, int val2,
702 enum adxl367_range *range)
703 {
704 size_t size = ARRAY_SIZE(adxl367_range_scale_tbl);
705 int i;
706
707 for (i = 0; i < size; i++)
708 if (val == adxl367_range_scale_tbl[i][0] &&
709 val2 == adxl367_range_scale_tbl[i][1])
710 break;
711
712 if (i == size)
713 return -EINVAL;
714
715 *range = i;
716
717 return 0;
718 }
719
adxl367_read_sample(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int * val)720 static int adxl367_read_sample(struct iio_dev *indio_dev,
721 struct iio_chan_spec const *chan,
722 int *val)
723 {
724 iio_device_claim_direct_scoped(return -EBUSY, indio_dev) {
725 struct adxl367_state *st = iio_priv(indio_dev);
726 u16 sample;
727 int ret;
728
729 guard(mutex)(&st->lock);
730
731 ret = adxl367_set_temp_adc_reg_en(st, chan->address, true);
732 if (ret)
733 return ret;
734
735 ret = regmap_bulk_read(st->regmap, chan->address, &st->sample_buf,
736 sizeof(st->sample_buf));
737 if (ret)
738 return ret;
739
740 sample = FIELD_GET(ADXL367_DATA_MASK, be16_to_cpu(st->sample_buf));
741 *val = sign_extend32(sample, chan->scan_type.realbits - 1);
742
743 ret = adxl367_set_temp_adc_reg_en(st, chan->address, false);
744 if (ret)
745 return ret;
746
747 return IIO_VAL_INT;
748 }
749 unreachable();
750 }
751
adxl367_get_status(struct adxl367_state * st,u8 * status,u16 * fifo_entries)752 static int adxl367_get_status(struct adxl367_state *st, u8 *status,
753 u16 *fifo_entries)
754 {
755 int ret;
756
757 /* Read STATUS, FIFO_ENT_L and FIFO_ENT_H */
758 ret = regmap_bulk_read(st->regmap, ADXL367_REG_STATUS,
759 st->status_buf, sizeof(st->status_buf));
760 if (ret)
761 return ret;
762
763 st->status_buf[2] &= ADXL367_FIFO_ENT_H_MASK;
764
765 *status = st->status_buf[0];
766 *fifo_entries = get_unaligned_le16(&st->status_buf[1]);
767
768 return 0;
769 }
770
adxl367_push_event(struct iio_dev * indio_dev,u8 status)771 static bool adxl367_push_event(struct iio_dev *indio_dev, u8 status)
772 {
773 unsigned int ev_dir;
774
775 if (FIELD_GET(ADXL367_STATUS_ACT_MASK, status))
776 ev_dir = IIO_EV_DIR_RISING;
777 else if (FIELD_GET(ADXL367_STATUS_INACT_MASK, status))
778 ev_dir = IIO_EV_DIR_FALLING;
779 else
780 return false;
781
782 iio_push_event(indio_dev,
783 IIO_MOD_EVENT_CODE(IIO_ACCEL, 0, IIO_MOD_X_OR_Y_OR_Z,
784 IIO_EV_TYPE_THRESH, ev_dir),
785 iio_get_time_ns(indio_dev));
786
787 return true;
788 }
789
adxl367_push_fifo_data(struct iio_dev * indio_dev,u8 status,u16 fifo_entries)790 static bool adxl367_push_fifo_data(struct iio_dev *indio_dev, u8 status,
791 u16 fifo_entries)
792 {
793 struct adxl367_state *st = iio_priv(indio_dev);
794 int ret;
795 int i;
796
797 if (!FIELD_GET(ADXL367_STATUS_FIFO_FULL_MASK, status))
798 return false;
799
800 fifo_entries -= fifo_entries % st->fifo_set_size;
801
802 ret = st->ops->read_fifo(st->context, st->fifo_buf, fifo_entries);
803 if (ret) {
804 dev_err(st->dev, "Failed to read FIFO: %d\n", ret);
805 return true;
806 }
807
808 for (i = 0; i < fifo_entries; i += st->fifo_set_size)
809 iio_push_to_buffers(indio_dev, &st->fifo_buf[i]);
810
811 return true;
812 }
813
adxl367_irq_handler(int irq,void * private)814 static irqreturn_t adxl367_irq_handler(int irq, void *private)
815 {
816 struct iio_dev *indio_dev = private;
817 struct adxl367_state *st = iio_priv(indio_dev);
818 u16 fifo_entries;
819 bool handled;
820 u8 status;
821 int ret;
822
823 ret = adxl367_get_status(st, &status, &fifo_entries);
824 if (ret)
825 return IRQ_NONE;
826
827 handled = adxl367_push_event(indio_dev, status);
828 handled |= adxl367_push_fifo_data(indio_dev, status, fifo_entries);
829
830 return handled ? IRQ_HANDLED : IRQ_NONE;
831 }
832
adxl367_reg_access(struct iio_dev * indio_dev,unsigned int reg,unsigned int writeval,unsigned int * readval)833 static int adxl367_reg_access(struct iio_dev *indio_dev,
834 unsigned int reg,
835 unsigned int writeval,
836 unsigned int *readval)
837 {
838 struct adxl367_state *st = iio_priv(indio_dev);
839
840 if (readval)
841 return regmap_read(st->regmap, reg, readval);
842 else
843 return regmap_write(st->regmap, reg, writeval);
844 }
845
adxl367_read_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int * val,int * val2,long info)846 static int adxl367_read_raw(struct iio_dev *indio_dev,
847 struct iio_chan_spec const *chan,
848 int *val, int *val2, long info)
849 {
850 struct adxl367_state *st = iio_priv(indio_dev);
851
852 switch (info) {
853 case IIO_CHAN_INFO_RAW:
854 return adxl367_read_sample(indio_dev, chan, val);
855 case IIO_CHAN_INFO_SCALE:
856 switch (chan->type) {
857 case IIO_ACCEL: {
858 guard(mutex)(&st->lock);
859 *val = adxl367_range_scale_tbl[st->range][0];
860 *val2 = adxl367_range_scale_tbl[st->range][1];
861 return IIO_VAL_INT_PLUS_NANO;
862 }
863 case IIO_TEMP:
864 *val = 1000;
865 *val2 = ADXL367_TEMP_PER_C;
866 return IIO_VAL_FRACTIONAL;
867 case IIO_VOLTAGE:
868 *val = ADXL367_VOLTAGE_MAX_MV;
869 *val2 = ADXL367_VOLTAGE_MAX_RAW;
870 return IIO_VAL_FRACTIONAL;
871 default:
872 return -EINVAL;
873 }
874 case IIO_CHAN_INFO_OFFSET:
875 switch (chan->type) {
876 case IIO_TEMP:
877 *val = 25 * ADXL367_TEMP_PER_C - ADXL367_TEMP_25C;
878 return IIO_VAL_INT;
879 case IIO_VOLTAGE:
880 *val = ADXL367_VOLTAGE_OFFSET;
881 return IIO_VAL_INT;
882 default:
883 return -EINVAL;
884 }
885 case IIO_CHAN_INFO_SAMP_FREQ: {
886 guard(mutex)(&st->lock);
887 *val = adxl367_samp_freq_tbl[st->odr][0];
888 *val2 = adxl367_samp_freq_tbl[st->odr][1];
889 return IIO_VAL_INT_PLUS_MICRO;
890 }
891 default:
892 return -EINVAL;
893 }
894 }
895
adxl367_write_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int val,int val2,long info)896 static int adxl367_write_raw(struct iio_dev *indio_dev,
897 struct iio_chan_spec const *chan,
898 int val, int val2, long info)
899 {
900 struct adxl367_state *st = iio_priv(indio_dev);
901 int ret;
902
903 switch (info) {
904 case IIO_CHAN_INFO_SAMP_FREQ: {
905 enum adxl367_odr odr;
906
907 ret = adxl367_find_odr(st, val, val2, &odr);
908 if (ret)
909 return ret;
910
911 return adxl367_set_odr(indio_dev, odr);
912 }
913 case IIO_CHAN_INFO_SCALE: {
914 enum adxl367_range range;
915
916 ret = adxl367_find_range(st, val, val2, &range);
917 if (ret)
918 return ret;
919
920 return adxl367_set_range(indio_dev, range);
921 }
922 default:
923 return -EINVAL;
924 }
925 }
926
adxl367_write_raw_get_fmt(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,long info)927 static int adxl367_write_raw_get_fmt(struct iio_dev *indio_dev,
928 struct iio_chan_spec const *chan,
929 long info)
930 {
931 switch (info) {
932 case IIO_CHAN_INFO_SCALE:
933 if (chan->type != IIO_ACCEL)
934 return -EINVAL;
935
936 return IIO_VAL_INT_PLUS_NANO;
937 default:
938 return IIO_VAL_INT_PLUS_MICRO;
939 }
940 }
941
adxl367_read_avail(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,const int ** vals,int * type,int * length,long info)942 static int adxl367_read_avail(struct iio_dev *indio_dev,
943 struct iio_chan_spec const *chan,
944 const int **vals, int *type, int *length,
945 long info)
946 {
947 switch (info) {
948 case IIO_CHAN_INFO_SCALE:
949 if (chan->type != IIO_ACCEL)
950 return -EINVAL;
951
952 *vals = (int *)adxl367_range_scale_tbl;
953 *type = IIO_VAL_INT_PLUS_NANO;
954 *length = ARRAY_SIZE(adxl367_range_scale_tbl) * 2;
955 return IIO_AVAIL_LIST;
956 case IIO_CHAN_INFO_SAMP_FREQ:
957 *vals = (int *)adxl367_samp_freq_tbl;
958 *type = IIO_VAL_INT_PLUS_MICRO;
959 *length = ARRAY_SIZE(adxl367_samp_freq_tbl) * 2;
960 return IIO_AVAIL_LIST;
961 default:
962 return -EINVAL;
963 }
964 }
965
adxl367_read_event_value(struct iio_dev * indio_dev,const struct iio_chan_spec * chan,enum iio_event_type type,enum iio_event_direction dir,enum iio_event_info info,int * val,int * val2)966 static int adxl367_read_event_value(struct iio_dev *indio_dev,
967 const struct iio_chan_spec *chan,
968 enum iio_event_type type,
969 enum iio_event_direction dir,
970 enum iio_event_info info,
971 int *val, int *val2)
972 {
973 struct adxl367_state *st = iio_priv(indio_dev);
974
975 guard(mutex)(&st->lock);
976 switch (info) {
977 case IIO_EV_INFO_VALUE: {
978 switch (dir) {
979 case IIO_EV_DIR_RISING:
980 *val = st->act_threshold;
981 return IIO_VAL_INT;
982 case IIO_EV_DIR_FALLING:
983 *val = st->inact_threshold;
984 return IIO_VAL_INT;
985 default:
986 return -EINVAL;
987 }
988 }
989 case IIO_EV_INFO_PERIOD:
990 switch (dir) {
991 case IIO_EV_DIR_RISING:
992 *val = st->act_time_ms;
993 *val2 = 1000;
994 return IIO_VAL_FRACTIONAL;
995 case IIO_EV_DIR_FALLING:
996 *val = st->inact_time_ms;
997 *val2 = 1000;
998 return IIO_VAL_FRACTIONAL;
999 default:
1000 return -EINVAL;
1001 }
1002 default:
1003 return -EINVAL;
1004 }
1005 }
1006
adxl367_write_event_value(struct iio_dev * indio_dev,const struct iio_chan_spec * chan,enum iio_event_type type,enum iio_event_direction dir,enum iio_event_info info,int val,int val2)1007 static int adxl367_write_event_value(struct iio_dev *indio_dev,
1008 const struct iio_chan_spec *chan,
1009 enum iio_event_type type,
1010 enum iio_event_direction dir,
1011 enum iio_event_info info,
1012 int val, int val2)
1013 {
1014 struct adxl367_state *st = iio_priv(indio_dev);
1015
1016 switch (info) {
1017 case IIO_EV_INFO_VALUE:
1018 if (val < 0)
1019 return -EINVAL;
1020
1021 switch (dir) {
1022 case IIO_EV_DIR_RISING:
1023 return adxl367_set_act_threshold(st, ADXL367_ACTIVITY, val);
1024 case IIO_EV_DIR_FALLING:
1025 return adxl367_set_act_threshold(st, ADXL367_INACTIVITY, val);
1026 default:
1027 return -EINVAL;
1028 }
1029 case IIO_EV_INFO_PERIOD:
1030 if (val < 0)
1031 return -EINVAL;
1032
1033 val = val * 1000 + DIV_ROUND_UP(val2, 1000);
1034 switch (dir) {
1035 case IIO_EV_DIR_RISING:
1036 return adxl367_set_act_time_ms(st, ADXL367_ACTIVITY, val);
1037 case IIO_EV_DIR_FALLING:
1038 return adxl367_set_act_time_ms(st, ADXL367_INACTIVITY, val);
1039 default:
1040 return -EINVAL;
1041 }
1042 default:
1043 return -EINVAL;
1044 }
1045 }
1046
adxl367_read_event_config(struct iio_dev * indio_dev,const struct iio_chan_spec * chan,enum iio_event_type type,enum iio_event_direction dir)1047 static int adxl367_read_event_config(struct iio_dev *indio_dev,
1048 const struct iio_chan_spec *chan,
1049 enum iio_event_type type,
1050 enum iio_event_direction dir)
1051 {
1052 struct adxl367_state *st = iio_priv(indio_dev);
1053 bool en;
1054 int ret;
1055
1056 switch (dir) {
1057 case IIO_EV_DIR_RISING:
1058 ret = adxl367_get_act_interrupt_en(st, ADXL367_ACTIVITY, &en);
1059 return ret ?: en;
1060 case IIO_EV_DIR_FALLING:
1061 ret = adxl367_get_act_interrupt_en(st, ADXL367_INACTIVITY, &en);
1062 return ret ?: en;
1063 default:
1064 return -EINVAL;
1065 }
1066 }
1067
adxl367_write_event_config(struct iio_dev * indio_dev,const struct iio_chan_spec * chan,enum iio_event_type type,enum iio_event_direction dir,int state)1068 static int adxl367_write_event_config(struct iio_dev *indio_dev,
1069 const struct iio_chan_spec *chan,
1070 enum iio_event_type type,
1071 enum iio_event_direction dir,
1072 int state)
1073 {
1074 enum adxl367_activity_type act;
1075
1076 switch (dir) {
1077 case IIO_EV_DIR_RISING:
1078 act = ADXL367_ACTIVITY;
1079 break;
1080 case IIO_EV_DIR_FALLING:
1081 act = ADXL367_INACTIVITY;
1082 break;
1083 default:
1084 return -EINVAL;
1085 }
1086
1087 iio_device_claim_direct_scoped(return -EBUSY, indio_dev) {
1088 struct adxl367_state *st = iio_priv(indio_dev);
1089 int ret;
1090
1091 guard(mutex)(&st->lock);
1092
1093 ret = adxl367_set_measure_en(st, false);
1094 if (ret)
1095 return ret;
1096
1097 ret = adxl367_set_act_interrupt_en(st, act, state);
1098 if (ret)
1099 return ret;
1100
1101 ret = adxl367_set_act_en(st, act, state ? ADCL367_ACT_REF_ENABLED
1102 : ADXL367_ACT_DISABLED);
1103 if (ret)
1104 return ret;
1105
1106 return adxl367_set_measure_en(st, true);
1107 }
1108 unreachable();
1109 }
1110
adxl367_get_fifo_enabled(struct device * dev,struct device_attribute * attr,char * buf)1111 static ssize_t adxl367_get_fifo_enabled(struct device *dev,
1112 struct device_attribute *attr,
1113 char *buf)
1114 {
1115 struct adxl367_state *st = iio_priv(dev_to_iio_dev(dev));
1116 enum adxl367_fifo_mode fifo_mode;
1117 int ret;
1118
1119 ret = adxl367_get_fifo_mode(st, &fifo_mode);
1120 if (ret)
1121 return ret;
1122
1123 return sysfs_emit(buf, "%d\n", fifo_mode != ADXL367_FIFO_MODE_DISABLED);
1124 }
1125
adxl367_get_fifo_watermark(struct device * dev,struct device_attribute * attr,char * buf)1126 static ssize_t adxl367_get_fifo_watermark(struct device *dev,
1127 struct device_attribute *attr,
1128 char *buf)
1129 {
1130 struct adxl367_state *st = iio_priv(dev_to_iio_dev(dev));
1131 unsigned int fifo_watermark;
1132
1133 guard(mutex)(&st->lock);
1134 fifo_watermark = st->fifo_watermark;
1135
1136 return sysfs_emit(buf, "%d\n", fifo_watermark);
1137 }
1138
1139 IIO_STATIC_CONST_DEVICE_ATTR(hwfifo_watermark_min, "1");
1140 IIO_STATIC_CONST_DEVICE_ATTR(hwfifo_watermark_max,
1141 __stringify(ADXL367_FIFO_MAX_WATERMARK));
1142 static IIO_DEVICE_ATTR(hwfifo_watermark, 0444,
1143 adxl367_get_fifo_watermark, NULL, 0);
1144 static IIO_DEVICE_ATTR(hwfifo_enabled, 0444,
1145 adxl367_get_fifo_enabled, NULL, 0);
1146
1147 static const struct iio_dev_attr *adxl367_fifo_attributes[] = {
1148 &iio_dev_attr_hwfifo_watermark_min,
1149 &iio_dev_attr_hwfifo_watermark_max,
1150 &iio_dev_attr_hwfifo_watermark,
1151 &iio_dev_attr_hwfifo_enabled,
1152 NULL,
1153 };
1154
adxl367_set_watermark(struct iio_dev * indio_dev,unsigned int val)1155 static int adxl367_set_watermark(struct iio_dev *indio_dev, unsigned int val)
1156 {
1157 struct adxl367_state *st = iio_priv(indio_dev);
1158 int ret;
1159
1160 if (val > ADXL367_FIFO_MAX_WATERMARK)
1161 return -EINVAL;
1162
1163 guard(mutex)(&st->lock);
1164
1165 ret = adxl367_set_measure_en(st, false);
1166 if (ret)
1167 return ret;
1168
1169 ret = adxl367_set_fifo_watermark(st, val);
1170 if (ret)
1171 return ret;
1172
1173 return adxl367_set_measure_en(st, true);
1174 }
1175
adxl367_find_mask_fifo_format(const unsigned long * scan_mask,enum adxl367_fifo_format * fifo_format)1176 static bool adxl367_find_mask_fifo_format(const unsigned long *scan_mask,
1177 enum adxl367_fifo_format *fifo_format)
1178 {
1179 size_t size = ARRAY_SIZE(adxl367_fifo_formats);
1180 int i;
1181
1182 for (i = 0; i < size; i++)
1183 if (*scan_mask == adxl367_channel_masks[i])
1184 break;
1185
1186 if (i == size)
1187 return false;
1188
1189 *fifo_format = adxl367_fifo_formats[i];
1190
1191 return true;
1192 }
1193
adxl367_update_scan_mode(struct iio_dev * indio_dev,const unsigned long * active_scan_mask)1194 static int adxl367_update_scan_mode(struct iio_dev *indio_dev,
1195 const unsigned long *active_scan_mask)
1196 {
1197 struct adxl367_state *st = iio_priv(indio_dev);
1198 enum adxl367_fifo_format fifo_format;
1199 int ret;
1200
1201 if (!adxl367_find_mask_fifo_format(active_scan_mask, &fifo_format))
1202 return -EINVAL;
1203
1204 guard(mutex)(&st->lock);
1205
1206 ret = adxl367_set_measure_en(st, false);
1207 if (ret)
1208 return ret;
1209
1210 ret = adxl367_set_fifo_format(st, fifo_format);
1211 if (ret)
1212 return ret;
1213
1214 ret = adxl367_set_measure_en(st, true);
1215 if (ret)
1216 return ret;
1217
1218 st->fifo_set_size = bitmap_weight(active_scan_mask,
1219 iio_get_masklength(indio_dev));
1220
1221 return 0;
1222 }
1223
adxl367_buffer_postenable(struct iio_dev * indio_dev)1224 static int adxl367_buffer_postenable(struct iio_dev *indio_dev)
1225 {
1226 struct adxl367_state *st = iio_priv(indio_dev);
1227 int ret;
1228
1229 guard(mutex)(&st->lock);
1230
1231 ret = adxl367_set_temp_adc_mask_en(st, indio_dev->active_scan_mask,
1232 true);
1233 if (ret)
1234 return ret;
1235
1236 ret = adxl367_set_measure_en(st, false);
1237 if (ret)
1238 return ret;
1239
1240 ret = adxl367_set_fifo_watermark_interrupt_en(st, true);
1241 if (ret)
1242 return ret;
1243
1244 ret = adxl367_set_fifo_mode(st, ADXL367_FIFO_MODE_STREAM);
1245 if (ret)
1246 return ret;
1247
1248 return adxl367_set_measure_en(st, true);
1249 }
1250
adxl367_buffer_predisable(struct iio_dev * indio_dev)1251 static int adxl367_buffer_predisable(struct iio_dev *indio_dev)
1252 {
1253 struct adxl367_state *st = iio_priv(indio_dev);
1254 int ret;
1255
1256 guard(mutex)(&st->lock);
1257
1258 ret = adxl367_set_measure_en(st, false);
1259 if (ret)
1260 return ret;
1261
1262 ret = adxl367_set_fifo_mode(st, ADXL367_FIFO_MODE_DISABLED);
1263 if (ret)
1264 return ret;
1265
1266 ret = adxl367_set_fifo_watermark_interrupt_en(st, false);
1267 if (ret)
1268 return ret;
1269
1270 ret = adxl367_set_measure_en(st, true);
1271 if (ret)
1272 return ret;
1273
1274 return adxl367_set_temp_adc_mask_en(st, indio_dev->active_scan_mask,
1275 false);
1276 }
1277
1278 static const struct iio_buffer_setup_ops adxl367_buffer_ops = {
1279 .postenable = adxl367_buffer_postenable,
1280 .predisable = adxl367_buffer_predisable,
1281 };
1282
1283 static const struct iio_info adxl367_info = {
1284 .read_raw = adxl367_read_raw,
1285 .write_raw = adxl367_write_raw,
1286 .write_raw_get_fmt = adxl367_write_raw_get_fmt,
1287 .read_avail = adxl367_read_avail,
1288 .read_event_config = adxl367_read_event_config,
1289 .write_event_config = adxl367_write_event_config,
1290 .read_event_value = adxl367_read_event_value,
1291 .write_event_value = adxl367_write_event_value,
1292 .debugfs_reg_access = adxl367_reg_access,
1293 .hwfifo_set_watermark = adxl367_set_watermark,
1294 .update_scan_mode = adxl367_update_scan_mode,
1295 };
1296
1297 static const struct iio_event_spec adxl367_events[] = {
1298 {
1299 .type = IIO_EV_TYPE_MAG_REFERENCED,
1300 .dir = IIO_EV_DIR_RISING,
1301 .mask_shared_by_type = BIT(IIO_EV_INFO_ENABLE) |
1302 BIT(IIO_EV_INFO_PERIOD) |
1303 BIT(IIO_EV_INFO_VALUE),
1304 },
1305 {
1306 .type = IIO_EV_TYPE_MAG_REFERENCED,
1307 .dir = IIO_EV_DIR_FALLING,
1308 .mask_shared_by_type = BIT(IIO_EV_INFO_ENABLE) |
1309 BIT(IIO_EV_INFO_PERIOD) |
1310 BIT(IIO_EV_INFO_VALUE),
1311 },
1312 };
1313
1314 #define ADXL367_ACCEL_CHANNEL(index, reg, axis) { \
1315 .type = IIO_ACCEL, \
1316 .address = (reg), \
1317 .modified = 1, \
1318 .channel2 = IIO_MOD_##axis, \
1319 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
1320 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \
1321 .info_mask_shared_by_type_available = BIT(IIO_CHAN_INFO_SCALE), \
1322 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ), \
1323 .info_mask_shared_by_all_available = \
1324 BIT(IIO_CHAN_INFO_SAMP_FREQ), \
1325 .event_spec = adxl367_events, \
1326 .num_event_specs = ARRAY_SIZE(adxl367_events), \
1327 .scan_index = (index), \
1328 .scan_type = { \
1329 .sign = 's', \
1330 .realbits = 14, \
1331 .storagebits = 16, \
1332 .endianness = IIO_BE, \
1333 }, \
1334 }
1335
1336 #define ADXL367_CHANNEL(index, reg, _type) { \
1337 .type = (_type), \
1338 .address = (reg), \
1339 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
1340 BIT(IIO_CHAN_INFO_OFFSET) | \
1341 BIT(IIO_CHAN_INFO_SCALE), \
1342 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ), \
1343 .scan_index = (index), \
1344 .scan_type = { \
1345 .sign = 's', \
1346 .realbits = 14, \
1347 .storagebits = 16, \
1348 .endianness = IIO_BE, \
1349 }, \
1350 }
1351
1352 static const struct iio_chan_spec adxl367_channels[] = {
1353 ADXL367_ACCEL_CHANNEL(ADXL367_X_CHANNEL_INDEX, ADXL367_REG_X_DATA_H, X),
1354 ADXL367_ACCEL_CHANNEL(ADXL367_Y_CHANNEL_INDEX, ADXL367_REG_Y_DATA_H, Y),
1355 ADXL367_ACCEL_CHANNEL(ADXL367_Z_CHANNEL_INDEX, ADXL367_REG_Z_DATA_H, Z),
1356 ADXL367_CHANNEL(ADXL367_TEMP_CHANNEL_INDEX, ADXL367_REG_TEMP_DATA_H,
1357 IIO_TEMP),
1358 ADXL367_CHANNEL(ADXL367_EX_ADC_CHANNEL_INDEX, ADXL367_REG_EX_ADC_DATA_H,
1359 IIO_VOLTAGE),
1360 };
1361
adxl367_verify_devid(struct adxl367_state * st)1362 static int adxl367_verify_devid(struct adxl367_state *st)
1363 {
1364 unsigned int val;
1365 int ret;
1366
1367 ret = regmap_read(st->regmap, ADXL367_REG_DEVID, &val);
1368 if (ret)
1369 return dev_err_probe(st->dev, ret, "Failed to read dev id\n");
1370
1371 if (val != ADXL367_DEVID_AD)
1372 return dev_err_probe(st->dev, -ENODEV,
1373 "Invalid dev id 0x%02X, expected 0x%02X\n",
1374 val, ADXL367_DEVID_AD);
1375
1376 return 0;
1377 }
1378
adxl367_setup(struct adxl367_state * st)1379 static int adxl367_setup(struct adxl367_state *st)
1380 {
1381 int ret;
1382
1383 ret = _adxl367_set_act_threshold(st, ADXL367_ACTIVITY,
1384 ADXL367_2G_RANGE_1G);
1385 if (ret)
1386 return ret;
1387
1388 ret = _adxl367_set_act_threshold(st, ADXL367_INACTIVITY,
1389 ADXL367_2G_RANGE_100MG);
1390 if (ret)
1391 return ret;
1392
1393 ret = adxl367_set_act_proc_mode(st, ADXL367_LOOPED);
1394 if (ret)
1395 return ret;
1396
1397 ret = _adxl367_set_odr(st, ADXL367_ODR_400HZ);
1398 if (ret)
1399 return ret;
1400
1401 ret = _adxl367_set_act_time_ms(st, 10);
1402 if (ret)
1403 return ret;
1404
1405 ret = _adxl367_set_inact_time_ms(st, 10000);
1406 if (ret)
1407 return ret;
1408
1409 return adxl367_set_measure_en(st, true);
1410 }
1411
adxl367_probe(struct device * dev,const struct adxl367_ops * ops,void * context,struct regmap * regmap,int irq)1412 int adxl367_probe(struct device *dev, const struct adxl367_ops *ops,
1413 void *context, struct regmap *regmap, int irq)
1414 {
1415 static const char * const regulator_names[] = { "vdd", "vddio" };
1416 struct iio_dev *indio_dev;
1417 struct adxl367_state *st;
1418 int ret;
1419
1420 indio_dev = devm_iio_device_alloc(dev, sizeof(*st));
1421 if (!indio_dev)
1422 return -ENOMEM;
1423
1424 st = iio_priv(indio_dev);
1425 st->dev = dev;
1426 st->regmap = regmap;
1427 st->context = context;
1428 st->ops = ops;
1429
1430 mutex_init(&st->lock);
1431
1432 indio_dev->channels = adxl367_channels;
1433 indio_dev->num_channels = ARRAY_SIZE(adxl367_channels);
1434 indio_dev->available_scan_masks = adxl367_channel_masks;
1435 indio_dev->name = "adxl367";
1436 indio_dev->info = &adxl367_info;
1437 indio_dev->modes = INDIO_DIRECT_MODE;
1438
1439 ret = devm_regulator_bulk_get_enable(st->dev,
1440 ARRAY_SIZE(regulator_names),
1441 regulator_names);
1442 if (ret)
1443 return dev_err_probe(st->dev, ret,
1444 "Failed to get regulators\n");
1445
1446 ret = regmap_write(st->regmap, ADXL367_REG_RESET, ADXL367_RESET_CODE);
1447 if (ret)
1448 return ret;
1449
1450 fsleep(15000);
1451
1452 ret = adxl367_verify_devid(st);
1453 if (ret)
1454 return ret;
1455
1456 ret = adxl367_setup(st);
1457 if (ret)
1458 return ret;
1459
1460 ret = devm_iio_kfifo_buffer_setup_ext(st->dev, indio_dev,
1461 &adxl367_buffer_ops,
1462 adxl367_fifo_attributes);
1463 if (ret)
1464 return ret;
1465
1466 ret = devm_request_threaded_irq(st->dev, irq, NULL,
1467 adxl367_irq_handler, IRQF_ONESHOT,
1468 indio_dev->name, indio_dev);
1469 if (ret)
1470 return dev_err_probe(st->dev, ret, "Failed to request irq\n");
1471
1472 return devm_iio_device_register(dev, indio_dev);
1473 }
1474 EXPORT_SYMBOL_NS_GPL(adxl367_probe, IIO_ADXL367);
1475
1476 MODULE_AUTHOR("Cosmin Tanislav <cosmin.tanislav@analog.com>");
1477 MODULE_DESCRIPTION("Analog Devices ADXL367 3-axis accelerometer driver");
1478 MODULE_LICENSE("GPL");
1479