1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * NXP FXLS8962AF/FXLS8964AF Accelerometer Core Driver
4 *
5 * Copyright 2021 Connected Cars A/S
6 *
7 * Datasheet:
8 * https://www.nxp.com/docs/en/data-sheet/FXLS8962AF.pdf
9 * https://www.nxp.com/docs/en/data-sheet/FXLS8964AF.pdf
10 *
11 * Errata:
12 * https://www.nxp.com/docs/en/errata/ES_FXLS8962AF.pdf
13 */
14
15 #include <linux/bits.h>
16 #include <linux/bitfield.h>
17 #include <linux/i2c.h>
18 #include <linux/irq.h>
19 #include <linux/module.h>
20 #include <linux/mod_devicetable.h>
21 #include <linux/pm_runtime.h>
22 #include <linux/property.h>
23 #include <linux/regulator/consumer.h>
24 #include <linux/regmap.h>
25 #include <linux/units.h>
26
27 #include <linux/iio/buffer.h>
28 #include <linux/iio/events.h>
29 #include <linux/iio/iio.h>
30 #include <linux/iio/kfifo_buf.h>
31 #include <linux/iio/sysfs.h>
32
33 #include "fxls8962af.h"
34
35 #define FXLS8962AF_INT_STATUS 0x00
36 #define FXLS8962AF_INT_STATUS_SRC_BOOT BIT(0)
37 #define FXLS8962AF_INT_STATUS_SRC_SDCD_OT BIT(4)
38 #define FXLS8962AF_INT_STATUS_SRC_BUF BIT(5)
39 #define FXLS8962AF_INT_STATUS_SRC_DRDY BIT(7)
40 #define FXLS8962AF_TEMP_OUT 0x01
41 #define FXLS8962AF_VECM_LSB 0x02
42 #define FXLS8962AF_OUT_X_LSB 0x04
43 #define FXLS8962AF_OUT_Y_LSB 0x06
44 #define FXLS8962AF_OUT_Z_LSB 0x08
45 #define FXLS8962AF_BUF_STATUS 0x0b
46 #define FXLS8962AF_BUF_STATUS_BUF_CNT GENMASK(5, 0)
47 #define FXLS8962AF_BUF_STATUS_BUF_OVF BIT(6)
48 #define FXLS8962AF_BUF_STATUS_BUF_WMRK BIT(7)
49 #define FXLS8962AF_BUF_X_LSB 0x0c
50 #define FXLS8962AF_BUF_Y_LSB 0x0e
51 #define FXLS8962AF_BUF_Z_LSB 0x10
52
53 #define FXLS8962AF_PROD_REV 0x12
54 #define FXLS8962AF_WHO_AM_I 0x13
55
56 #define FXLS8962AF_SYS_MODE 0x14
57 #define FXLS8962AF_SENS_CONFIG1 0x15
58 #define FXLS8962AF_SENS_CONFIG1_ACTIVE BIT(0)
59 #define FXLS8962AF_SENS_CONFIG1_RST BIT(7)
60 #define FXLS8962AF_SC1_FSR_MASK GENMASK(2, 1)
61 #define FXLS8962AF_SC1_FSR_PREP(x) FIELD_PREP(FXLS8962AF_SC1_FSR_MASK, (x))
62 #define FXLS8962AF_SC1_FSR_GET(x) FIELD_GET(FXLS8962AF_SC1_FSR_MASK, (x))
63
64 #define FXLS8962AF_SENS_CONFIG2 0x16
65 #define FXLS8962AF_SENS_CONFIG3 0x17
66 #define FXLS8962AF_SC3_WAKE_ODR_MASK GENMASK(7, 4)
67 #define FXLS8962AF_SC3_WAKE_ODR_PREP(x) FIELD_PREP(FXLS8962AF_SC3_WAKE_ODR_MASK, (x))
68 #define FXLS8962AF_SC3_WAKE_ODR_GET(x) FIELD_GET(FXLS8962AF_SC3_WAKE_ODR_MASK, (x))
69 #define FXLS8962AF_SENS_CONFIG4 0x18
70 #define FXLS8962AF_SC4_INT_PP_OD_MASK BIT(1)
71 #define FXLS8962AF_SC4_INT_PP_OD_PREP(x) FIELD_PREP(FXLS8962AF_SC4_INT_PP_OD_MASK, (x))
72 #define FXLS8962AF_SC4_INT_POL_MASK BIT(0)
73 #define FXLS8962AF_SC4_INT_POL_PREP(x) FIELD_PREP(FXLS8962AF_SC4_INT_POL_MASK, (x))
74 #define FXLS8962AF_SENS_CONFIG5 0x19
75
76 #define FXLS8962AF_WAKE_IDLE_LSB 0x1b
77 #define FXLS8962AF_SLEEP_IDLE_LSB 0x1c
78 #define FXLS8962AF_ASLP_COUNT_LSB 0x1e
79
80 #define FXLS8962AF_INT_EN 0x20
81 #define FXLS8962AF_INT_EN_SDCD_OT_EN BIT(5)
82 #define FXLS8962AF_INT_EN_BUF_EN BIT(6)
83 #define FXLS8962AF_INT_PIN_SEL 0x21
84 #define FXLS8962AF_INT_PIN_SEL_MASK GENMASK(7, 0)
85 #define FXLS8962AF_INT_PIN_SEL_INT1 0x00
86 #define FXLS8962AF_INT_PIN_SEL_INT2 GENMASK(7, 0)
87
88 #define FXLS8962AF_OFF_X 0x22
89 #define FXLS8962AF_OFF_Y 0x23
90 #define FXLS8962AF_OFF_Z 0x24
91
92 #define FXLS8962AF_BUF_CONFIG1 0x26
93 #define FXLS8962AF_BC1_BUF_MODE_MASK GENMASK(6, 5)
94 #define FXLS8962AF_BC1_BUF_MODE_PREP(x) FIELD_PREP(FXLS8962AF_BC1_BUF_MODE_MASK, (x))
95 #define FXLS8962AF_BUF_CONFIG2 0x27
96 #define FXLS8962AF_BUF_CONFIG2_BUF_WMRK GENMASK(5, 0)
97
98 #define FXLS8962AF_ORIENT_STATUS 0x28
99 #define FXLS8962AF_ORIENT_CONFIG 0x29
100 #define FXLS8962AF_ORIENT_DBCOUNT 0x2a
101 #define FXLS8962AF_ORIENT_BF_ZCOMP 0x2b
102 #define FXLS8962AF_ORIENT_THS_REG 0x2c
103
104 #define FXLS8962AF_SDCD_INT_SRC1 0x2d
105 #define FXLS8962AF_SDCD_INT_SRC1_X_OT BIT(5)
106 #define FXLS8962AF_SDCD_INT_SRC1_X_POL BIT(4)
107 #define FXLS8962AF_SDCD_INT_SRC1_Y_OT BIT(3)
108 #define FXLS8962AF_SDCD_INT_SRC1_Y_POL BIT(2)
109 #define FXLS8962AF_SDCD_INT_SRC1_Z_OT BIT(1)
110 #define FXLS8962AF_SDCD_INT_SRC1_Z_POL BIT(0)
111 #define FXLS8962AF_SDCD_INT_SRC2 0x2e
112 #define FXLS8962AF_SDCD_CONFIG1 0x2f
113 #define FXLS8962AF_SDCD_CONFIG1_Z_OT_EN BIT(3)
114 #define FXLS8962AF_SDCD_CONFIG1_Y_OT_EN BIT(4)
115 #define FXLS8962AF_SDCD_CONFIG1_X_OT_EN BIT(5)
116 #define FXLS8962AF_SDCD_CONFIG1_OT_ELE BIT(7)
117 #define FXLS8962AF_SDCD_CONFIG2 0x30
118 #define FXLS8962AF_SDCD_CONFIG2_SDCD_EN BIT(7)
119 #define FXLS8962AF_SC2_REF_UPDM_AC GENMASK(6, 5)
120 #define FXLS8962AF_SDCD_OT_DBCNT 0x31
121 #define FXLS8962AF_SDCD_WT_DBCNT 0x32
122 #define FXLS8962AF_SDCD_LTHS_LSB 0x33
123 #define FXLS8962AF_SDCD_UTHS_LSB 0x35
124
125 #define FXLS8962AF_SELF_TEST_CONFIG1 0x37
126 #define FXLS8962AF_SELF_TEST_CONFIG2 0x38
127
128 #define FXLS8962AF_MAX_REG 0x38
129
130 #define FXLS8962AF_DEVICE_ID 0x62
131 #define FXLS8964AF_DEVICE_ID 0x84
132
133 /* Raw temp channel offset */
134 #define FXLS8962AF_TEMP_CENTER_VAL 25
135
136 #define FXLS8962AF_AUTO_SUSPEND_DELAY_MS 2000
137
138 #define FXLS8962AF_FIFO_LENGTH 32
139 #define FXLS8962AF_SCALE_TABLE_LEN 4
140 #define FXLS8962AF_SAMP_FREQ_TABLE_LEN 13
141
142 static const int fxls8962af_scale_table[FXLS8962AF_SCALE_TABLE_LEN][2] = {
143 {0, IIO_G_TO_M_S_2(980000)},
144 {0, IIO_G_TO_M_S_2(1950000)},
145 {0, IIO_G_TO_M_S_2(3910000)},
146 {0, IIO_G_TO_M_S_2(7810000)},
147 };
148
149 static const int fxls8962af_samp_freq_table[FXLS8962AF_SAMP_FREQ_TABLE_LEN][2] = {
150 {3200, 0}, {1600, 0}, {800, 0}, {400, 0}, {200, 0}, {100, 0},
151 {50, 0}, {25, 0}, {12, 500000}, {6, 250000}, {3, 125000},
152 {1, 563000}, {0, 781000},
153 };
154
155 struct fxls8962af_chip_info {
156 const char *name;
157 const struct iio_chan_spec *channels;
158 int num_channels;
159 u8 chip_id;
160 };
161
162 struct fxls8962af_data {
163 struct regmap *regmap;
164 const struct fxls8962af_chip_info *chip_info;
165 struct {
166 __le16 channels[3];
167 s64 ts __aligned(8);
168 } scan;
169 int64_t timestamp, old_timestamp; /* Only used in hw fifo mode. */
170 struct iio_mount_matrix orientation;
171 int irq;
172 u8 watermark;
173 u8 enable_event;
174 u16 lower_thres;
175 u16 upper_thres;
176 };
177
178 const struct regmap_config fxls8962af_i2c_regmap_conf = {
179 .reg_bits = 8,
180 .val_bits = 8,
181 .max_register = FXLS8962AF_MAX_REG,
182 };
183 EXPORT_SYMBOL_NS_GPL(fxls8962af_i2c_regmap_conf, IIO_FXLS8962AF);
184
185 const struct regmap_config fxls8962af_spi_regmap_conf = {
186 .reg_bits = 8,
187 .pad_bits = 8,
188 .val_bits = 8,
189 .max_register = FXLS8962AF_MAX_REG,
190 };
191 EXPORT_SYMBOL_NS_GPL(fxls8962af_spi_regmap_conf, IIO_FXLS8962AF);
192
193 enum {
194 fxls8962af_idx_x,
195 fxls8962af_idx_y,
196 fxls8962af_idx_z,
197 fxls8962af_idx_ts,
198 };
199
200 enum fxls8962af_int_pin {
201 FXLS8962AF_PIN_INT1,
202 FXLS8962AF_PIN_INT2,
203 };
204
fxls8962af_power_on(struct fxls8962af_data * data)205 static int fxls8962af_power_on(struct fxls8962af_data *data)
206 {
207 struct device *dev = regmap_get_device(data->regmap);
208 int ret;
209
210 ret = pm_runtime_resume_and_get(dev);
211 if (ret)
212 dev_err(dev, "failed to power on\n");
213
214 return ret;
215 }
216
fxls8962af_power_off(struct fxls8962af_data * data)217 static int fxls8962af_power_off(struct fxls8962af_data *data)
218 {
219 struct device *dev = regmap_get_device(data->regmap);
220 int ret;
221
222 pm_runtime_mark_last_busy(dev);
223 ret = pm_runtime_put_autosuspend(dev);
224 if (ret)
225 dev_err(dev, "failed to power off\n");
226
227 return ret;
228 }
229
fxls8962af_standby(struct fxls8962af_data * data)230 static int fxls8962af_standby(struct fxls8962af_data *data)
231 {
232 return regmap_clear_bits(data->regmap, FXLS8962AF_SENS_CONFIG1,
233 FXLS8962AF_SENS_CONFIG1_ACTIVE);
234 }
235
fxls8962af_active(struct fxls8962af_data * data)236 static int fxls8962af_active(struct fxls8962af_data *data)
237 {
238 return regmap_update_bits(data->regmap, FXLS8962AF_SENS_CONFIG1,
239 FXLS8962AF_SENS_CONFIG1_ACTIVE, 1);
240 }
241
fxls8962af_is_active(struct fxls8962af_data * data)242 static int fxls8962af_is_active(struct fxls8962af_data *data)
243 {
244 unsigned int reg;
245 int ret;
246
247 ret = regmap_read(data->regmap, FXLS8962AF_SENS_CONFIG1, ®);
248 if (ret)
249 return ret;
250
251 return reg & FXLS8962AF_SENS_CONFIG1_ACTIVE;
252 }
253
fxls8962af_get_out(struct fxls8962af_data * data,struct iio_chan_spec const * chan,int * val)254 static int fxls8962af_get_out(struct fxls8962af_data *data,
255 struct iio_chan_spec const *chan, int *val)
256 {
257 struct device *dev = regmap_get_device(data->regmap);
258 __le16 raw_val;
259 int is_active;
260 int ret;
261
262 is_active = fxls8962af_is_active(data);
263 if (!is_active) {
264 ret = fxls8962af_power_on(data);
265 if (ret)
266 return ret;
267 }
268
269 ret = regmap_bulk_read(data->regmap, chan->address,
270 &raw_val, sizeof(data->lower_thres));
271
272 if (!is_active)
273 fxls8962af_power_off(data);
274
275 if (ret) {
276 dev_err(dev, "failed to get out reg 0x%lx\n", chan->address);
277 return ret;
278 }
279
280 *val = sign_extend32(le16_to_cpu(raw_val),
281 chan->scan_type.realbits - 1);
282
283 return IIO_VAL_INT;
284 }
285
fxls8962af_read_avail(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,const int ** vals,int * type,int * length,long mask)286 static int fxls8962af_read_avail(struct iio_dev *indio_dev,
287 struct iio_chan_spec const *chan,
288 const int **vals, int *type, int *length,
289 long mask)
290 {
291 switch (mask) {
292 case IIO_CHAN_INFO_SCALE:
293 *type = IIO_VAL_INT_PLUS_NANO;
294 *vals = (int *)fxls8962af_scale_table;
295 *length = ARRAY_SIZE(fxls8962af_scale_table) * 2;
296 return IIO_AVAIL_LIST;
297 case IIO_CHAN_INFO_SAMP_FREQ:
298 *type = IIO_VAL_INT_PLUS_MICRO;
299 *vals = (int *)fxls8962af_samp_freq_table;
300 *length = ARRAY_SIZE(fxls8962af_samp_freq_table) * 2;
301 return IIO_AVAIL_LIST;
302 default:
303 return -EINVAL;
304 }
305 }
306
fxls8962af_write_raw_get_fmt(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,long mask)307 static int fxls8962af_write_raw_get_fmt(struct iio_dev *indio_dev,
308 struct iio_chan_spec const *chan,
309 long mask)
310 {
311 switch (mask) {
312 case IIO_CHAN_INFO_SCALE:
313 return IIO_VAL_INT_PLUS_NANO;
314 case IIO_CHAN_INFO_SAMP_FREQ:
315 return IIO_VAL_INT_PLUS_MICRO;
316 default:
317 return IIO_VAL_INT_PLUS_NANO;
318 }
319 }
320
fxls8962af_update_config(struct fxls8962af_data * data,u8 reg,u8 mask,u8 val)321 static int fxls8962af_update_config(struct fxls8962af_data *data, u8 reg,
322 u8 mask, u8 val)
323 {
324 int ret;
325 int is_active;
326
327 is_active = fxls8962af_is_active(data);
328 if (is_active) {
329 ret = fxls8962af_standby(data);
330 if (ret)
331 return ret;
332 }
333
334 ret = regmap_update_bits(data->regmap, reg, mask, val);
335 if (ret)
336 return ret;
337
338 if (is_active) {
339 ret = fxls8962af_active(data);
340 if (ret)
341 return ret;
342 }
343
344 return 0;
345 }
346
fxls8962af_set_full_scale(struct fxls8962af_data * data,u32 scale)347 static int fxls8962af_set_full_scale(struct fxls8962af_data *data, u32 scale)
348 {
349 int i;
350
351 for (i = 0; i < ARRAY_SIZE(fxls8962af_scale_table); i++)
352 if (scale == fxls8962af_scale_table[i][1])
353 break;
354
355 if (i == ARRAY_SIZE(fxls8962af_scale_table))
356 return -EINVAL;
357
358 return fxls8962af_update_config(data, FXLS8962AF_SENS_CONFIG1,
359 FXLS8962AF_SC1_FSR_MASK,
360 FXLS8962AF_SC1_FSR_PREP(i));
361 }
362
fxls8962af_read_full_scale(struct fxls8962af_data * data,int * val)363 static unsigned int fxls8962af_read_full_scale(struct fxls8962af_data *data,
364 int *val)
365 {
366 int ret;
367 unsigned int reg;
368 u8 range_idx;
369
370 ret = regmap_read(data->regmap, FXLS8962AF_SENS_CONFIG1, ®);
371 if (ret)
372 return ret;
373
374 range_idx = FXLS8962AF_SC1_FSR_GET(reg);
375
376 *val = fxls8962af_scale_table[range_idx][1];
377
378 return IIO_VAL_INT_PLUS_NANO;
379 }
380
fxls8962af_set_samp_freq(struct fxls8962af_data * data,u32 val,u32 val2)381 static int fxls8962af_set_samp_freq(struct fxls8962af_data *data, u32 val,
382 u32 val2)
383 {
384 int i;
385
386 for (i = 0; i < ARRAY_SIZE(fxls8962af_samp_freq_table); i++)
387 if (val == fxls8962af_samp_freq_table[i][0] &&
388 val2 == fxls8962af_samp_freq_table[i][1])
389 break;
390
391 if (i == ARRAY_SIZE(fxls8962af_samp_freq_table))
392 return -EINVAL;
393
394 return fxls8962af_update_config(data, FXLS8962AF_SENS_CONFIG3,
395 FXLS8962AF_SC3_WAKE_ODR_MASK,
396 FXLS8962AF_SC3_WAKE_ODR_PREP(i));
397 }
398
fxls8962af_read_samp_freq(struct fxls8962af_data * data,int * val,int * val2)399 static unsigned int fxls8962af_read_samp_freq(struct fxls8962af_data *data,
400 int *val, int *val2)
401 {
402 int ret;
403 unsigned int reg;
404 u8 range_idx;
405
406 ret = regmap_read(data->regmap, FXLS8962AF_SENS_CONFIG3, ®);
407 if (ret)
408 return ret;
409
410 range_idx = FXLS8962AF_SC3_WAKE_ODR_GET(reg);
411
412 *val = fxls8962af_samp_freq_table[range_idx][0];
413 *val2 = fxls8962af_samp_freq_table[range_idx][1];
414
415 return IIO_VAL_INT_PLUS_MICRO;
416 }
417
fxls8962af_read_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int * val,int * val2,long mask)418 static int fxls8962af_read_raw(struct iio_dev *indio_dev,
419 struct iio_chan_spec const *chan,
420 int *val, int *val2, long mask)
421 {
422 struct fxls8962af_data *data = iio_priv(indio_dev);
423
424 switch (mask) {
425 case IIO_CHAN_INFO_RAW:
426 switch (chan->type) {
427 case IIO_TEMP:
428 case IIO_ACCEL:
429 return fxls8962af_get_out(data, chan, val);
430 default:
431 return -EINVAL;
432 }
433 case IIO_CHAN_INFO_OFFSET:
434 if (chan->type != IIO_TEMP)
435 return -EINVAL;
436
437 *val = FXLS8962AF_TEMP_CENTER_VAL;
438 return IIO_VAL_INT;
439 case IIO_CHAN_INFO_SCALE:
440 switch (chan->type) {
441 case IIO_TEMP:
442 *val = MILLIDEGREE_PER_DEGREE;
443 return IIO_VAL_INT;
444 case IIO_ACCEL:
445 *val = 0;
446 return fxls8962af_read_full_scale(data, val2);
447 default:
448 return -EINVAL;
449 }
450 case IIO_CHAN_INFO_SAMP_FREQ:
451 return fxls8962af_read_samp_freq(data, val, val2);
452 default:
453 return -EINVAL;
454 }
455 }
456
fxls8962af_write_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int val,int val2,long mask)457 static int fxls8962af_write_raw(struct iio_dev *indio_dev,
458 struct iio_chan_spec const *chan,
459 int val, int val2, long mask)
460 {
461 struct fxls8962af_data *data = iio_priv(indio_dev);
462 int ret;
463
464 switch (mask) {
465 case IIO_CHAN_INFO_SCALE:
466 if (val != 0)
467 return -EINVAL;
468
469 ret = iio_device_claim_direct_mode(indio_dev);
470 if (ret)
471 return ret;
472
473 ret = fxls8962af_set_full_scale(data, val2);
474
475 iio_device_release_direct_mode(indio_dev);
476 return ret;
477 case IIO_CHAN_INFO_SAMP_FREQ:
478 ret = iio_device_claim_direct_mode(indio_dev);
479 if (ret)
480 return ret;
481
482 ret = fxls8962af_set_samp_freq(data, val, val2);
483
484 iio_device_release_direct_mode(indio_dev);
485 return ret;
486 default:
487 return -EINVAL;
488 }
489 }
490
fxls8962af_event_setup(struct fxls8962af_data * data,int state)491 static int fxls8962af_event_setup(struct fxls8962af_data *data, int state)
492 {
493 /* Enable wakeup interrupt */
494 int mask = FXLS8962AF_INT_EN_SDCD_OT_EN;
495 int value = state ? mask : 0;
496
497 return regmap_update_bits(data->regmap, FXLS8962AF_INT_EN, mask, value);
498 }
499
fxls8962af_set_watermark(struct iio_dev * indio_dev,unsigned val)500 static int fxls8962af_set_watermark(struct iio_dev *indio_dev, unsigned val)
501 {
502 struct fxls8962af_data *data = iio_priv(indio_dev);
503
504 if (val > FXLS8962AF_FIFO_LENGTH)
505 val = FXLS8962AF_FIFO_LENGTH;
506
507 data->watermark = val;
508
509 return 0;
510 }
511
__fxls8962af_set_thresholds(struct fxls8962af_data * data,const struct iio_chan_spec * chan,enum iio_event_direction dir,int val)512 static int __fxls8962af_set_thresholds(struct fxls8962af_data *data,
513 const struct iio_chan_spec *chan,
514 enum iio_event_direction dir,
515 int val)
516 {
517 switch (dir) {
518 case IIO_EV_DIR_FALLING:
519 data->lower_thres = val;
520 return regmap_bulk_write(data->regmap, FXLS8962AF_SDCD_LTHS_LSB,
521 &data->lower_thres, sizeof(data->lower_thres));
522 case IIO_EV_DIR_RISING:
523 data->upper_thres = val;
524 return regmap_bulk_write(data->regmap, FXLS8962AF_SDCD_UTHS_LSB,
525 &data->upper_thres, sizeof(data->upper_thres));
526 default:
527 return -EINVAL;
528 }
529 }
530
fxls8962af_read_event(struct iio_dev * indio_dev,const struct iio_chan_spec * chan,enum iio_event_type type,enum iio_event_direction dir,enum iio_event_info info,int * val,int * val2)531 static int fxls8962af_read_event(struct iio_dev *indio_dev,
532 const struct iio_chan_spec *chan,
533 enum iio_event_type type,
534 enum iio_event_direction dir,
535 enum iio_event_info info,
536 int *val, int *val2)
537 {
538 struct fxls8962af_data *data = iio_priv(indio_dev);
539 int ret;
540
541 if (type != IIO_EV_TYPE_THRESH)
542 return -EINVAL;
543
544 switch (dir) {
545 case IIO_EV_DIR_FALLING:
546 ret = regmap_bulk_read(data->regmap, FXLS8962AF_SDCD_LTHS_LSB,
547 &data->lower_thres, sizeof(data->lower_thres));
548 if (ret)
549 return ret;
550
551 *val = sign_extend32(data->lower_thres, chan->scan_type.realbits - 1);
552 return IIO_VAL_INT;
553 case IIO_EV_DIR_RISING:
554 ret = regmap_bulk_read(data->regmap, FXLS8962AF_SDCD_UTHS_LSB,
555 &data->upper_thres, sizeof(data->upper_thres));
556 if (ret)
557 return ret;
558
559 *val = sign_extend32(data->upper_thres, chan->scan_type.realbits - 1);
560 return IIO_VAL_INT;
561 default:
562 return -EINVAL;
563 }
564 }
565
fxls8962af_write_event(struct iio_dev * indio_dev,const struct iio_chan_spec * chan,enum iio_event_type type,enum iio_event_direction dir,enum iio_event_info info,int val,int val2)566 static int fxls8962af_write_event(struct iio_dev *indio_dev,
567 const struct iio_chan_spec *chan,
568 enum iio_event_type type,
569 enum iio_event_direction dir,
570 enum iio_event_info info,
571 int val, int val2)
572 {
573 struct fxls8962af_data *data = iio_priv(indio_dev);
574 int ret, val_masked;
575
576 if (type != IIO_EV_TYPE_THRESH)
577 return -EINVAL;
578
579 if (val < -2048 || val > 2047)
580 return -EINVAL;
581
582 if (data->enable_event)
583 return -EBUSY;
584
585 val_masked = val & GENMASK(11, 0);
586 if (fxls8962af_is_active(data)) {
587 ret = fxls8962af_standby(data);
588 if (ret)
589 return ret;
590
591 ret = __fxls8962af_set_thresholds(data, chan, dir, val_masked);
592 if (ret)
593 return ret;
594
595 return fxls8962af_active(data);
596 } else {
597 return __fxls8962af_set_thresholds(data, chan, dir, val_masked);
598 }
599 }
600
601 static int
fxls8962af_read_event_config(struct iio_dev * indio_dev,const struct iio_chan_spec * chan,enum iio_event_type type,enum iio_event_direction dir)602 fxls8962af_read_event_config(struct iio_dev *indio_dev,
603 const struct iio_chan_spec *chan,
604 enum iio_event_type type,
605 enum iio_event_direction dir)
606 {
607 struct fxls8962af_data *data = iio_priv(indio_dev);
608
609 if (type != IIO_EV_TYPE_THRESH)
610 return -EINVAL;
611
612 switch (chan->channel2) {
613 case IIO_MOD_X:
614 return !!(FXLS8962AF_SDCD_CONFIG1_X_OT_EN & data->enable_event);
615 case IIO_MOD_Y:
616 return !!(FXLS8962AF_SDCD_CONFIG1_Y_OT_EN & data->enable_event);
617 case IIO_MOD_Z:
618 return !!(FXLS8962AF_SDCD_CONFIG1_Z_OT_EN & data->enable_event);
619 default:
620 return -EINVAL;
621 }
622 }
623
624 static int
fxls8962af_write_event_config(struct iio_dev * indio_dev,const struct iio_chan_spec * chan,enum iio_event_type type,enum iio_event_direction dir,int state)625 fxls8962af_write_event_config(struct iio_dev *indio_dev,
626 const struct iio_chan_spec *chan,
627 enum iio_event_type type,
628 enum iio_event_direction dir, int state)
629 {
630 struct fxls8962af_data *data = iio_priv(indio_dev);
631 u8 enable_event, enable_bits;
632 int ret, value;
633
634 if (type != IIO_EV_TYPE_THRESH)
635 return -EINVAL;
636
637 switch (chan->channel2) {
638 case IIO_MOD_X:
639 enable_bits = FXLS8962AF_SDCD_CONFIG1_X_OT_EN;
640 break;
641 case IIO_MOD_Y:
642 enable_bits = FXLS8962AF_SDCD_CONFIG1_Y_OT_EN;
643 break;
644 case IIO_MOD_Z:
645 enable_bits = FXLS8962AF_SDCD_CONFIG1_Z_OT_EN;
646 break;
647 default:
648 return -EINVAL;
649 }
650
651 if (state)
652 enable_event = data->enable_event | enable_bits;
653 else
654 enable_event = data->enable_event & ~enable_bits;
655
656 if (data->enable_event == enable_event)
657 return 0;
658
659 ret = fxls8962af_standby(data);
660 if (ret)
661 return ret;
662
663 /* Enable events */
664 value = enable_event | FXLS8962AF_SDCD_CONFIG1_OT_ELE;
665 ret = regmap_write(data->regmap, FXLS8962AF_SDCD_CONFIG1, value);
666 if (ret)
667 return ret;
668
669 /*
670 * Enable update of SDCD_REF_X/Y/Z values with the current decimated and
671 * trimmed X/Y/Z acceleration input data. This allows for acceleration
672 * slope detection with Data(n) to Data(n–1) always used as the input
673 * to the window comparator.
674 */
675 value = enable_event ?
676 FXLS8962AF_SDCD_CONFIG2_SDCD_EN | FXLS8962AF_SC2_REF_UPDM_AC :
677 0x00;
678 ret = regmap_write(data->regmap, FXLS8962AF_SDCD_CONFIG2, value);
679 if (ret)
680 return ret;
681
682 ret = fxls8962af_event_setup(data, state);
683 if (ret)
684 return ret;
685
686 data->enable_event = enable_event;
687
688 if (data->enable_event) {
689 fxls8962af_active(data);
690 ret = fxls8962af_power_on(data);
691 } else {
692 ret = iio_device_claim_direct_mode(indio_dev);
693 if (ret)
694 return ret;
695
696 /* Not in buffered mode so disable power */
697 ret = fxls8962af_power_off(data);
698
699 iio_device_release_direct_mode(indio_dev);
700 }
701
702 return ret;
703 }
704
705 static const struct iio_event_spec fxls8962af_event[] = {
706 {
707 .type = IIO_EV_TYPE_THRESH,
708 .dir = IIO_EV_DIR_EITHER,
709 .mask_separate = BIT(IIO_EV_INFO_ENABLE),
710 },
711 {
712 .type = IIO_EV_TYPE_THRESH,
713 .dir = IIO_EV_DIR_FALLING,
714 .mask_separate = BIT(IIO_EV_INFO_VALUE),
715 },
716 {
717 .type = IIO_EV_TYPE_THRESH,
718 .dir = IIO_EV_DIR_RISING,
719 .mask_separate = BIT(IIO_EV_INFO_VALUE),
720 },
721 };
722
723 #define FXLS8962AF_CHANNEL(axis, reg, idx) { \
724 .type = IIO_ACCEL, \
725 .address = reg, \
726 .modified = 1, \
727 .channel2 = IIO_MOD_##axis, \
728 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
729 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) | \
730 BIT(IIO_CHAN_INFO_SAMP_FREQ), \
731 .info_mask_shared_by_type_available = BIT(IIO_CHAN_INFO_SCALE) | \
732 BIT(IIO_CHAN_INFO_SAMP_FREQ), \
733 .scan_index = idx, \
734 .scan_type = { \
735 .sign = 's', \
736 .realbits = 12, \
737 .storagebits = 16, \
738 .endianness = IIO_LE, \
739 }, \
740 .event_spec = fxls8962af_event, \
741 .num_event_specs = ARRAY_SIZE(fxls8962af_event), \
742 }
743
744 #define FXLS8962AF_TEMP_CHANNEL { \
745 .type = IIO_TEMP, \
746 .address = FXLS8962AF_TEMP_OUT, \
747 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
748 BIT(IIO_CHAN_INFO_SCALE) | \
749 BIT(IIO_CHAN_INFO_OFFSET),\
750 .scan_index = -1, \
751 .scan_type = { \
752 .sign = 's', \
753 .realbits = 8, \
754 .storagebits = 8, \
755 }, \
756 }
757
758 static const struct iio_chan_spec fxls8962af_channels[] = {
759 FXLS8962AF_CHANNEL(X, FXLS8962AF_OUT_X_LSB, fxls8962af_idx_x),
760 FXLS8962AF_CHANNEL(Y, FXLS8962AF_OUT_Y_LSB, fxls8962af_idx_y),
761 FXLS8962AF_CHANNEL(Z, FXLS8962AF_OUT_Z_LSB, fxls8962af_idx_z),
762 IIO_CHAN_SOFT_TIMESTAMP(fxls8962af_idx_ts),
763 FXLS8962AF_TEMP_CHANNEL,
764 };
765
766 static const struct fxls8962af_chip_info fxls_chip_info_table[] = {
767 [fxls8962af] = {
768 .chip_id = FXLS8962AF_DEVICE_ID,
769 .name = "fxls8962af",
770 .channels = fxls8962af_channels,
771 .num_channels = ARRAY_SIZE(fxls8962af_channels),
772 },
773 [fxls8964af] = {
774 .chip_id = FXLS8964AF_DEVICE_ID,
775 .name = "fxls8964af",
776 .channels = fxls8962af_channels,
777 .num_channels = ARRAY_SIZE(fxls8962af_channels),
778 },
779 };
780
781 static const struct iio_info fxls8962af_info = {
782 .read_raw = &fxls8962af_read_raw,
783 .write_raw = &fxls8962af_write_raw,
784 .write_raw_get_fmt = fxls8962af_write_raw_get_fmt,
785 .read_event_value = fxls8962af_read_event,
786 .write_event_value = fxls8962af_write_event,
787 .read_event_config = fxls8962af_read_event_config,
788 .write_event_config = fxls8962af_write_event_config,
789 .read_avail = fxls8962af_read_avail,
790 .hwfifo_set_watermark = fxls8962af_set_watermark,
791 };
792
fxls8962af_reset(struct fxls8962af_data * data)793 static int fxls8962af_reset(struct fxls8962af_data *data)
794 {
795 struct device *dev = regmap_get_device(data->regmap);
796 unsigned int reg;
797 int ret;
798
799 ret = regmap_set_bits(data->regmap, FXLS8962AF_SENS_CONFIG1,
800 FXLS8962AF_SENS_CONFIG1_RST);
801 if (ret)
802 return ret;
803
804 /* TBOOT1, TBOOT2, specifies we have to wait between 1 - 17.7ms */
805 ret = regmap_read_poll_timeout(data->regmap, FXLS8962AF_INT_STATUS, reg,
806 (reg & FXLS8962AF_INT_STATUS_SRC_BOOT),
807 1000, 18000);
808 if (ret == -ETIMEDOUT)
809 dev_err(dev, "reset timeout, int_status = 0x%x\n", reg);
810
811 return ret;
812 }
813
__fxls8962af_fifo_set_mode(struct fxls8962af_data * data,bool onoff)814 static int __fxls8962af_fifo_set_mode(struct fxls8962af_data *data, bool onoff)
815 {
816 int ret;
817
818 /* Enable watermark at max fifo size */
819 ret = regmap_update_bits(data->regmap, FXLS8962AF_BUF_CONFIG2,
820 FXLS8962AF_BUF_CONFIG2_BUF_WMRK,
821 data->watermark);
822 if (ret)
823 return ret;
824
825 return regmap_update_bits(data->regmap, FXLS8962AF_BUF_CONFIG1,
826 FXLS8962AF_BC1_BUF_MODE_MASK,
827 FXLS8962AF_BC1_BUF_MODE_PREP(onoff));
828 }
829
fxls8962af_buffer_preenable(struct iio_dev * indio_dev)830 static int fxls8962af_buffer_preenable(struct iio_dev *indio_dev)
831 {
832 return fxls8962af_power_on(iio_priv(indio_dev));
833 }
834
fxls8962af_buffer_postenable(struct iio_dev * indio_dev)835 static int fxls8962af_buffer_postenable(struct iio_dev *indio_dev)
836 {
837 struct fxls8962af_data *data = iio_priv(indio_dev);
838 int ret;
839
840 fxls8962af_standby(data);
841
842 /* Enable buffer interrupt */
843 ret = regmap_set_bits(data->regmap, FXLS8962AF_INT_EN,
844 FXLS8962AF_INT_EN_BUF_EN);
845 if (ret)
846 return ret;
847
848 ret = __fxls8962af_fifo_set_mode(data, true);
849
850 fxls8962af_active(data);
851
852 return ret;
853 }
854
fxls8962af_buffer_predisable(struct iio_dev * indio_dev)855 static int fxls8962af_buffer_predisable(struct iio_dev *indio_dev)
856 {
857 struct fxls8962af_data *data = iio_priv(indio_dev);
858 int ret;
859
860 fxls8962af_standby(data);
861
862 /* Disable buffer interrupt */
863 ret = regmap_clear_bits(data->regmap, FXLS8962AF_INT_EN,
864 FXLS8962AF_INT_EN_BUF_EN);
865 if (ret)
866 return ret;
867
868 synchronize_irq(data->irq);
869
870 ret = __fxls8962af_fifo_set_mode(data, false);
871
872 if (data->enable_event)
873 fxls8962af_active(data);
874
875 return ret;
876 }
877
fxls8962af_buffer_postdisable(struct iio_dev * indio_dev)878 static int fxls8962af_buffer_postdisable(struct iio_dev *indio_dev)
879 {
880 struct fxls8962af_data *data = iio_priv(indio_dev);
881
882 if (!data->enable_event)
883 fxls8962af_power_off(data);
884
885 return 0;
886 }
887
888 static const struct iio_buffer_setup_ops fxls8962af_buffer_ops = {
889 .preenable = fxls8962af_buffer_preenable,
890 .postenable = fxls8962af_buffer_postenable,
891 .predisable = fxls8962af_buffer_predisable,
892 .postdisable = fxls8962af_buffer_postdisable,
893 };
894
fxls8962af_i2c_raw_read_errata3(struct fxls8962af_data * data,u16 * buffer,int samples,int sample_length)895 static int fxls8962af_i2c_raw_read_errata3(struct fxls8962af_data *data,
896 u16 *buffer, int samples,
897 int sample_length)
898 {
899 int i, ret;
900
901 for (i = 0; i < samples; i++) {
902 ret = regmap_raw_read(data->regmap, FXLS8962AF_BUF_X_LSB,
903 &buffer[i * 3], sample_length);
904 if (ret)
905 return ret;
906 }
907
908 return 0;
909 }
910
fxls8962af_fifo_transfer(struct fxls8962af_data * data,u16 * buffer,int samples)911 static int fxls8962af_fifo_transfer(struct fxls8962af_data *data,
912 u16 *buffer, int samples)
913 {
914 struct device *dev = regmap_get_device(data->regmap);
915 int sample_length = 3 * sizeof(*buffer);
916 int total_length = samples * sample_length;
917 int ret;
918
919 if (i2c_verify_client(dev) &&
920 data->chip_info->chip_id == FXLS8962AF_DEVICE_ID)
921 /*
922 * Due to errata bug (only applicable on fxls8962af):
923 * E3: FIFO burst read operation error using I2C interface
924 * We have to avoid burst reads on I2C..
925 */
926 ret = fxls8962af_i2c_raw_read_errata3(data, buffer, samples,
927 sample_length);
928 else
929 ret = regmap_raw_read(data->regmap, FXLS8962AF_BUF_X_LSB, buffer,
930 total_length);
931
932 if (ret)
933 dev_err(dev, "Error transferring data from fifo: %d\n", ret);
934
935 return ret;
936 }
937
fxls8962af_fifo_flush(struct iio_dev * indio_dev)938 static int fxls8962af_fifo_flush(struct iio_dev *indio_dev)
939 {
940 struct fxls8962af_data *data = iio_priv(indio_dev);
941 struct device *dev = regmap_get_device(data->regmap);
942 u16 buffer[FXLS8962AF_FIFO_LENGTH * 3];
943 uint64_t sample_period;
944 unsigned int reg;
945 int64_t tstamp;
946 int ret, i;
947 u8 count;
948
949 ret = regmap_read(data->regmap, FXLS8962AF_BUF_STATUS, ®);
950 if (ret)
951 return ret;
952
953 if (reg & FXLS8962AF_BUF_STATUS_BUF_OVF) {
954 dev_err(dev, "Buffer overflow");
955 return -EOVERFLOW;
956 }
957
958 count = reg & FXLS8962AF_BUF_STATUS_BUF_CNT;
959 if (!count)
960 return 0;
961
962 data->old_timestamp = data->timestamp;
963 data->timestamp = iio_get_time_ns(indio_dev);
964
965 /*
966 * Approximate timestamps for each of the sample based on the sampling,
967 * frequency, timestamp for last sample and number of samples.
968 */
969 sample_period = (data->timestamp - data->old_timestamp);
970 do_div(sample_period, count);
971 tstamp = data->timestamp - (count - 1) * sample_period;
972
973 ret = fxls8962af_fifo_transfer(data, buffer, count);
974 if (ret)
975 return ret;
976
977 /* Demux hw FIFO into kfifo. */
978 for (i = 0; i < count; i++) {
979 int j, bit;
980
981 j = 0;
982 iio_for_each_active_channel(indio_dev, bit) {
983 memcpy(&data->scan.channels[j++], &buffer[i * 3 + bit],
984 sizeof(data->scan.channels[0]));
985 }
986
987 iio_push_to_buffers_with_timestamp(indio_dev, &data->scan,
988 tstamp);
989
990 tstamp += sample_period;
991 }
992
993 return count;
994 }
995
fxls8962af_event_interrupt(struct iio_dev * indio_dev)996 static int fxls8962af_event_interrupt(struct iio_dev *indio_dev)
997 {
998 struct fxls8962af_data *data = iio_priv(indio_dev);
999 s64 ts = iio_get_time_ns(indio_dev);
1000 unsigned int reg;
1001 u64 ev_code;
1002 int ret;
1003
1004 ret = regmap_read(data->regmap, FXLS8962AF_SDCD_INT_SRC1, ®);
1005 if (ret)
1006 return ret;
1007
1008 if (reg & FXLS8962AF_SDCD_INT_SRC1_X_OT) {
1009 ev_code = reg & FXLS8962AF_SDCD_INT_SRC1_X_POL ?
1010 IIO_EV_DIR_RISING : IIO_EV_DIR_FALLING;
1011 iio_push_event(indio_dev,
1012 IIO_MOD_EVENT_CODE(IIO_ACCEL, 0, IIO_MOD_X,
1013 IIO_EV_TYPE_THRESH, ev_code), ts);
1014 }
1015
1016 if (reg & FXLS8962AF_SDCD_INT_SRC1_Y_OT) {
1017 ev_code = reg & FXLS8962AF_SDCD_INT_SRC1_Y_POL ?
1018 IIO_EV_DIR_RISING : IIO_EV_DIR_FALLING;
1019 iio_push_event(indio_dev,
1020 IIO_MOD_EVENT_CODE(IIO_ACCEL, 0, IIO_MOD_X,
1021 IIO_EV_TYPE_THRESH, ev_code), ts);
1022 }
1023
1024 if (reg & FXLS8962AF_SDCD_INT_SRC1_Z_OT) {
1025 ev_code = reg & FXLS8962AF_SDCD_INT_SRC1_Z_POL ?
1026 IIO_EV_DIR_RISING : IIO_EV_DIR_FALLING;
1027 iio_push_event(indio_dev,
1028 IIO_MOD_EVENT_CODE(IIO_ACCEL, 0, IIO_MOD_X,
1029 IIO_EV_TYPE_THRESH, ev_code), ts);
1030 }
1031
1032 return 0;
1033 }
1034
fxls8962af_interrupt(int irq,void * p)1035 static irqreturn_t fxls8962af_interrupt(int irq, void *p)
1036 {
1037 struct iio_dev *indio_dev = p;
1038 struct fxls8962af_data *data = iio_priv(indio_dev);
1039 unsigned int reg;
1040 int ret;
1041
1042 ret = regmap_read(data->regmap, FXLS8962AF_INT_STATUS, ®);
1043 if (ret)
1044 return IRQ_NONE;
1045
1046 if (reg & FXLS8962AF_INT_STATUS_SRC_BUF) {
1047 ret = fxls8962af_fifo_flush(indio_dev);
1048 if (ret < 0)
1049 return IRQ_NONE;
1050
1051 return IRQ_HANDLED;
1052 }
1053
1054 if (reg & FXLS8962AF_INT_STATUS_SRC_SDCD_OT) {
1055 ret = fxls8962af_event_interrupt(indio_dev);
1056 if (ret < 0)
1057 return IRQ_NONE;
1058
1059 return IRQ_HANDLED;
1060 }
1061
1062 return IRQ_NONE;
1063 }
1064
fxls8962af_pm_disable(void * dev_ptr)1065 static void fxls8962af_pm_disable(void *dev_ptr)
1066 {
1067 struct device *dev = dev_ptr;
1068 struct iio_dev *indio_dev = dev_get_drvdata(dev);
1069
1070 pm_runtime_disable(dev);
1071 pm_runtime_set_suspended(dev);
1072 pm_runtime_put_noidle(dev);
1073
1074 fxls8962af_standby(iio_priv(indio_dev));
1075 }
1076
fxls8962af_get_irq(struct device * dev,enum fxls8962af_int_pin * pin)1077 static void fxls8962af_get_irq(struct device *dev,
1078 enum fxls8962af_int_pin *pin)
1079 {
1080 int irq;
1081
1082 irq = fwnode_irq_get_byname(dev_fwnode(dev), "INT2");
1083 if (irq > 0) {
1084 *pin = FXLS8962AF_PIN_INT2;
1085 return;
1086 }
1087
1088 *pin = FXLS8962AF_PIN_INT1;
1089 }
1090
fxls8962af_irq_setup(struct iio_dev * indio_dev,int irq)1091 static int fxls8962af_irq_setup(struct iio_dev *indio_dev, int irq)
1092 {
1093 struct fxls8962af_data *data = iio_priv(indio_dev);
1094 struct device *dev = regmap_get_device(data->regmap);
1095 unsigned long irq_type;
1096 bool irq_active_high;
1097 enum fxls8962af_int_pin int_pin;
1098 u8 int_pin_sel;
1099 int ret;
1100
1101 fxls8962af_get_irq(dev, &int_pin);
1102 switch (int_pin) {
1103 case FXLS8962AF_PIN_INT1:
1104 int_pin_sel = FXLS8962AF_INT_PIN_SEL_INT1;
1105 break;
1106 case FXLS8962AF_PIN_INT2:
1107 int_pin_sel = FXLS8962AF_INT_PIN_SEL_INT2;
1108 break;
1109 default:
1110 dev_err(dev, "unsupported int pin selected\n");
1111 return -EINVAL;
1112 }
1113
1114 ret = regmap_update_bits(data->regmap, FXLS8962AF_INT_PIN_SEL,
1115 FXLS8962AF_INT_PIN_SEL_MASK, int_pin_sel);
1116 if (ret)
1117 return ret;
1118
1119 irq_type = irqd_get_trigger_type(irq_get_irq_data(irq));
1120
1121 switch (irq_type) {
1122 case IRQF_TRIGGER_HIGH:
1123 case IRQF_TRIGGER_RISING:
1124 irq_active_high = true;
1125 break;
1126 case IRQF_TRIGGER_LOW:
1127 case IRQF_TRIGGER_FALLING:
1128 irq_active_high = false;
1129 break;
1130 default:
1131 dev_info(dev, "mode %lx unsupported\n", irq_type);
1132 return -EINVAL;
1133 }
1134
1135 ret = regmap_update_bits(data->regmap, FXLS8962AF_SENS_CONFIG4,
1136 FXLS8962AF_SC4_INT_POL_MASK,
1137 FXLS8962AF_SC4_INT_POL_PREP(irq_active_high));
1138 if (ret)
1139 return ret;
1140
1141 if (device_property_read_bool(dev, "drive-open-drain")) {
1142 ret = regmap_update_bits(data->regmap, FXLS8962AF_SENS_CONFIG4,
1143 FXLS8962AF_SC4_INT_PP_OD_MASK,
1144 FXLS8962AF_SC4_INT_PP_OD_PREP(1));
1145 if (ret)
1146 return ret;
1147
1148 irq_type |= IRQF_SHARED;
1149 }
1150
1151 return devm_request_threaded_irq(dev,
1152 irq,
1153 NULL, fxls8962af_interrupt,
1154 irq_type | IRQF_ONESHOT,
1155 indio_dev->name, indio_dev);
1156 }
1157
fxls8962af_core_probe(struct device * dev,struct regmap * regmap,int irq)1158 int fxls8962af_core_probe(struct device *dev, struct regmap *regmap, int irq)
1159 {
1160 struct fxls8962af_data *data;
1161 struct iio_dev *indio_dev;
1162 unsigned int reg;
1163 int ret, i;
1164
1165 indio_dev = devm_iio_device_alloc(dev, sizeof(*data));
1166 if (!indio_dev)
1167 return -ENOMEM;
1168
1169 data = iio_priv(indio_dev);
1170 dev_set_drvdata(dev, indio_dev);
1171 data->regmap = regmap;
1172 data->irq = irq;
1173
1174 ret = iio_read_mount_matrix(dev, &data->orientation);
1175 if (ret)
1176 return ret;
1177
1178 ret = devm_regulator_get_enable(dev, "vdd");
1179 if (ret)
1180 return dev_err_probe(dev, ret,
1181 "Failed to get vdd regulator\n");
1182
1183 ret = regmap_read(data->regmap, FXLS8962AF_WHO_AM_I, ®);
1184 if (ret)
1185 return ret;
1186
1187 for (i = 0; i < ARRAY_SIZE(fxls_chip_info_table); i++) {
1188 if (fxls_chip_info_table[i].chip_id == reg) {
1189 data->chip_info = &fxls_chip_info_table[i];
1190 break;
1191 }
1192 }
1193 if (i == ARRAY_SIZE(fxls_chip_info_table)) {
1194 dev_err(dev, "failed to match device in table\n");
1195 return -ENXIO;
1196 }
1197
1198 indio_dev->channels = data->chip_info->channels;
1199 indio_dev->num_channels = data->chip_info->num_channels;
1200 indio_dev->name = data->chip_info->name;
1201 indio_dev->info = &fxls8962af_info;
1202 indio_dev->modes = INDIO_DIRECT_MODE;
1203
1204 ret = fxls8962af_reset(data);
1205 if (ret)
1206 return ret;
1207
1208 if (irq) {
1209 ret = fxls8962af_irq_setup(indio_dev, irq);
1210 if (ret)
1211 return ret;
1212
1213 ret = devm_iio_kfifo_buffer_setup(dev, indio_dev,
1214 &fxls8962af_buffer_ops);
1215 if (ret)
1216 return ret;
1217 }
1218
1219 ret = pm_runtime_set_active(dev);
1220 if (ret)
1221 return ret;
1222
1223 pm_runtime_enable(dev);
1224 pm_runtime_set_autosuspend_delay(dev, FXLS8962AF_AUTO_SUSPEND_DELAY_MS);
1225 pm_runtime_use_autosuspend(dev);
1226
1227 ret = devm_add_action_or_reset(dev, fxls8962af_pm_disable, dev);
1228 if (ret)
1229 return ret;
1230
1231 if (device_property_read_bool(dev, "wakeup-source"))
1232 device_init_wakeup(dev, true);
1233
1234 return devm_iio_device_register(dev, indio_dev);
1235 }
1236 EXPORT_SYMBOL_NS_GPL(fxls8962af_core_probe, IIO_FXLS8962AF);
1237
fxls8962af_runtime_suspend(struct device * dev)1238 static int fxls8962af_runtime_suspend(struct device *dev)
1239 {
1240 struct fxls8962af_data *data = iio_priv(dev_get_drvdata(dev));
1241 int ret;
1242
1243 ret = fxls8962af_standby(data);
1244 if (ret) {
1245 dev_err(dev, "powering off device failed\n");
1246 return ret;
1247 }
1248
1249 return 0;
1250 }
1251
fxls8962af_runtime_resume(struct device * dev)1252 static int fxls8962af_runtime_resume(struct device *dev)
1253 {
1254 struct fxls8962af_data *data = iio_priv(dev_get_drvdata(dev));
1255
1256 return fxls8962af_active(data);
1257 }
1258
fxls8962af_suspend(struct device * dev)1259 static int fxls8962af_suspend(struct device *dev)
1260 {
1261 struct iio_dev *indio_dev = dev_get_drvdata(dev);
1262 struct fxls8962af_data *data = iio_priv(indio_dev);
1263
1264 if (device_may_wakeup(dev) && data->enable_event) {
1265 enable_irq_wake(data->irq);
1266
1267 /*
1268 * Disable buffer, as the buffer is so small the device will wake
1269 * almost immediately.
1270 */
1271 if (iio_buffer_enabled(indio_dev))
1272 fxls8962af_buffer_predisable(indio_dev);
1273 } else {
1274 fxls8962af_runtime_suspend(dev);
1275 }
1276
1277 return 0;
1278 }
1279
fxls8962af_resume(struct device * dev)1280 static int fxls8962af_resume(struct device *dev)
1281 {
1282 struct iio_dev *indio_dev = dev_get_drvdata(dev);
1283 struct fxls8962af_data *data = iio_priv(indio_dev);
1284
1285 if (device_may_wakeup(dev) && data->enable_event) {
1286 disable_irq_wake(data->irq);
1287
1288 if (iio_buffer_enabled(indio_dev))
1289 fxls8962af_buffer_postenable(indio_dev);
1290 } else {
1291 fxls8962af_runtime_resume(dev);
1292 }
1293
1294 return 0;
1295 }
1296
1297 EXPORT_NS_GPL_DEV_PM_OPS(fxls8962af_pm_ops, IIO_FXLS8962AF) = {
1298 SYSTEM_SLEEP_PM_OPS(fxls8962af_suspend, fxls8962af_resume)
1299 RUNTIME_PM_OPS(fxls8962af_runtime_suspend, fxls8962af_runtime_resume, NULL)
1300 };
1301
1302 MODULE_AUTHOR("Sean Nyekjaer <sean@geanix.com>");
1303 MODULE_DESCRIPTION("NXP FXLS8962AF/FXLS8964AF accelerometer driver");
1304 MODULE_LICENSE("GPL v2");
1305