1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * AD7124 SPI ADC driver
4 *
5 * Copyright 2018 Analog Devices Inc.
6 */
7 #include <linux/bitfield.h>
8 #include <linux/bitops.h>
9 #include <linux/clk.h>
10 #include <linux/delay.h>
11 #include <linux/device.h>
12 #include <linux/err.h>
13 #include <linux/interrupt.h>
14 #include <linux/kernel.h>
15 #include <linux/kfifo.h>
16 #include <linux/module.h>
17 #include <linux/mod_devicetable.h>
18 #include <linux/property.h>
19 #include <linux/regulator/consumer.h>
20 #include <linux/spi/spi.h>
21
22 #include <linux/iio/iio.h>
23 #include <linux/iio/adc/ad_sigma_delta.h>
24 #include <linux/iio/sysfs.h>
25
26 /* AD7124 registers */
27 #define AD7124_COMMS 0x00
28 #define AD7124_STATUS 0x00
29 #define AD7124_ADC_CONTROL 0x01
30 #define AD7124_DATA 0x02
31 #define AD7124_IO_CONTROL_1 0x03
32 #define AD7124_IO_CONTROL_2 0x04
33 #define AD7124_ID 0x05
34 #define AD7124_ERROR 0x06
35 #define AD7124_ERROR_EN 0x07
36 #define AD7124_MCLK_COUNT 0x08
37 #define AD7124_CHANNEL(x) (0x09 + (x))
38 #define AD7124_CONFIG(x) (0x19 + (x))
39 #define AD7124_FILTER(x) (0x21 + (x))
40 #define AD7124_OFFSET(x) (0x29 + (x))
41 #define AD7124_GAIN(x) (0x31 + (x))
42
43 /* AD7124_STATUS */
44 #define AD7124_STATUS_POR_FLAG_MSK BIT(4)
45
46 /* AD7124_ADC_CONTROL */
47 #define AD7124_ADC_STATUS_EN_MSK BIT(10)
48 #define AD7124_ADC_STATUS_EN(x) FIELD_PREP(AD7124_ADC_STATUS_EN_MSK, x)
49 #define AD7124_ADC_CTRL_REF_EN_MSK BIT(8)
50 #define AD7124_ADC_CTRL_REF_EN(x) FIELD_PREP(AD7124_ADC_CTRL_REF_EN_MSK, x)
51 #define AD7124_ADC_CTRL_PWR_MSK GENMASK(7, 6)
52 #define AD7124_ADC_CTRL_PWR(x) FIELD_PREP(AD7124_ADC_CTRL_PWR_MSK, x)
53 #define AD7124_ADC_CTRL_MODE_MSK GENMASK(5, 2)
54 #define AD7124_ADC_CTRL_MODE(x) FIELD_PREP(AD7124_ADC_CTRL_MODE_MSK, x)
55
56 /* AD7124 ID */
57 #define AD7124_DEVICE_ID_MSK GENMASK(7, 4)
58 #define AD7124_DEVICE_ID_GET(x) FIELD_GET(AD7124_DEVICE_ID_MSK, x)
59 #define AD7124_SILICON_REV_MSK GENMASK(3, 0)
60 #define AD7124_SILICON_REV_GET(x) FIELD_GET(AD7124_SILICON_REV_MSK, x)
61
62 #define CHIPID_AD7124_4 0x0
63 #define CHIPID_AD7124_8 0x1
64
65 /* AD7124_CHANNEL_X */
66 #define AD7124_CHANNEL_EN_MSK BIT(15)
67 #define AD7124_CHANNEL_EN(x) FIELD_PREP(AD7124_CHANNEL_EN_MSK, x)
68 #define AD7124_CHANNEL_SETUP_MSK GENMASK(14, 12)
69 #define AD7124_CHANNEL_SETUP(x) FIELD_PREP(AD7124_CHANNEL_SETUP_MSK, x)
70 #define AD7124_CHANNEL_AINP_MSK GENMASK(9, 5)
71 #define AD7124_CHANNEL_AINP(x) FIELD_PREP(AD7124_CHANNEL_AINP_MSK, x)
72 #define AD7124_CHANNEL_AINM_MSK GENMASK(4, 0)
73 #define AD7124_CHANNEL_AINM(x) FIELD_PREP(AD7124_CHANNEL_AINM_MSK, x)
74
75 /* AD7124_CONFIG_X */
76 #define AD7124_CONFIG_BIPOLAR_MSK BIT(11)
77 #define AD7124_CONFIG_BIPOLAR(x) FIELD_PREP(AD7124_CONFIG_BIPOLAR_MSK, x)
78 #define AD7124_CONFIG_REF_SEL_MSK GENMASK(4, 3)
79 #define AD7124_CONFIG_REF_SEL(x) FIELD_PREP(AD7124_CONFIG_REF_SEL_MSK, x)
80 #define AD7124_CONFIG_PGA_MSK GENMASK(2, 0)
81 #define AD7124_CONFIG_PGA(x) FIELD_PREP(AD7124_CONFIG_PGA_MSK, x)
82 #define AD7124_CONFIG_IN_BUFF_MSK GENMASK(6, 5)
83 #define AD7124_CONFIG_IN_BUFF(x) FIELD_PREP(AD7124_CONFIG_IN_BUFF_MSK, x)
84
85 /* AD7124_FILTER_X */
86 #define AD7124_FILTER_FS_MSK GENMASK(10, 0)
87 #define AD7124_FILTER_FS(x) FIELD_PREP(AD7124_FILTER_FS_MSK, x)
88 #define AD7124_FILTER_TYPE_MSK GENMASK(23, 21)
89 #define AD7124_FILTER_TYPE_SEL(x) FIELD_PREP(AD7124_FILTER_TYPE_MSK, x)
90
91 #define AD7124_SINC3_FILTER 2
92 #define AD7124_SINC4_FILTER 0
93
94 #define AD7124_CONF_ADDR_OFFSET 20
95 #define AD7124_MAX_CONFIGS 8
96 #define AD7124_MAX_CHANNELS 16
97
98 enum ad7124_ids {
99 ID_AD7124_4,
100 ID_AD7124_8,
101 };
102
103 enum ad7124_ref_sel {
104 AD7124_REFIN1,
105 AD7124_REFIN2,
106 AD7124_INT_REF,
107 AD7124_AVDD_REF,
108 };
109
110 enum ad7124_power_mode {
111 AD7124_LOW_POWER,
112 AD7124_MID_POWER,
113 AD7124_FULL_POWER,
114 };
115
116 static const unsigned int ad7124_gain[8] = {
117 1, 2, 4, 8, 16, 32, 64, 128
118 };
119
120 static const unsigned int ad7124_reg_size[] = {
121 1, 2, 3, 3, 2, 1, 3, 3, 1, 2, 2, 2, 2,
122 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
123 2, 2, 2, 2, 2, 2, 2, 3, 3, 3, 3, 3, 3,
124 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
125 3, 3, 3, 3, 3
126 };
127
128 static const int ad7124_master_clk_freq_hz[3] = {
129 [AD7124_LOW_POWER] = 76800,
130 [AD7124_MID_POWER] = 153600,
131 [AD7124_FULL_POWER] = 614400,
132 };
133
134 static const char * const ad7124_ref_names[] = {
135 [AD7124_REFIN1] = "refin1",
136 [AD7124_REFIN2] = "refin2",
137 [AD7124_INT_REF] = "int",
138 [AD7124_AVDD_REF] = "avdd",
139 };
140
141 struct ad7124_chip_info {
142 const char *name;
143 unsigned int chip_id;
144 unsigned int num_inputs;
145 };
146
147 struct ad7124_channel_config {
148 bool live;
149 unsigned int cfg_slot;
150 /*
151 * Following fields are used to compare for equality. If you
152 * make adaptations in it, you most likely also have to adapt
153 * ad7124_find_similar_live_cfg(), too.
154 */
155 struct_group(config_props,
156 enum ad7124_ref_sel refsel;
157 bool bipolar;
158 bool buf_positive;
159 bool buf_negative;
160 unsigned int vref_mv;
161 unsigned int pga_bits;
162 unsigned int odr;
163 unsigned int odr_sel_bits;
164 unsigned int filter_type;
165 );
166 };
167
168 struct ad7124_channel {
169 unsigned int nr;
170 struct ad7124_channel_config cfg;
171 unsigned int ain;
172 unsigned int slot;
173 };
174
175 struct ad7124_state {
176 const struct ad7124_chip_info *chip_info;
177 struct ad_sigma_delta sd;
178 struct ad7124_channel *channels;
179 struct regulator *vref[4];
180 struct clk *mclk;
181 unsigned int adc_control;
182 unsigned int num_channels;
183 struct mutex cfgs_lock; /* lock for configs access */
184 unsigned long cfg_slots_status; /* bitmap with slot status (1 means it is used) */
185 DECLARE_KFIFO(live_cfgs_fifo, struct ad7124_channel_config *, AD7124_MAX_CONFIGS);
186 };
187
188 static const struct iio_chan_spec ad7124_channel_template = {
189 .type = IIO_VOLTAGE,
190 .indexed = 1,
191 .differential = 1,
192 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
193 BIT(IIO_CHAN_INFO_SCALE) |
194 BIT(IIO_CHAN_INFO_OFFSET) |
195 BIT(IIO_CHAN_INFO_SAMP_FREQ) |
196 BIT(IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY),
197 .scan_type = {
198 .sign = 'u',
199 .realbits = 24,
200 .storagebits = 32,
201 .endianness = IIO_BE,
202 },
203 };
204
205 static struct ad7124_chip_info ad7124_chip_info_tbl[] = {
206 [ID_AD7124_4] = {
207 .name = "ad7124-4",
208 .chip_id = CHIPID_AD7124_4,
209 .num_inputs = 8,
210 },
211 [ID_AD7124_8] = {
212 .name = "ad7124-8",
213 .chip_id = CHIPID_AD7124_8,
214 .num_inputs = 16,
215 },
216 };
217
ad7124_find_closest_match(const int * array,unsigned int size,int val)218 static int ad7124_find_closest_match(const int *array,
219 unsigned int size, int val)
220 {
221 int i, idx;
222 unsigned int diff_new, diff_old;
223
224 diff_old = U32_MAX;
225 idx = 0;
226
227 for (i = 0; i < size; i++) {
228 diff_new = abs(val - array[i]);
229 if (diff_new < diff_old) {
230 diff_old = diff_new;
231 idx = i;
232 }
233 }
234
235 return idx;
236 }
237
ad7124_spi_write_mask(struct ad7124_state * st,unsigned int addr,unsigned long mask,unsigned int val,unsigned int bytes)238 static int ad7124_spi_write_mask(struct ad7124_state *st,
239 unsigned int addr,
240 unsigned long mask,
241 unsigned int val,
242 unsigned int bytes)
243 {
244 unsigned int readval;
245 int ret;
246
247 ret = ad_sd_read_reg(&st->sd, addr, bytes, &readval);
248 if (ret < 0)
249 return ret;
250
251 readval &= ~mask;
252 readval |= val;
253
254 return ad_sd_write_reg(&st->sd, addr, bytes, readval);
255 }
256
ad7124_set_mode(struct ad_sigma_delta * sd,enum ad_sigma_delta_mode mode)257 static int ad7124_set_mode(struct ad_sigma_delta *sd,
258 enum ad_sigma_delta_mode mode)
259 {
260 struct ad7124_state *st = container_of(sd, struct ad7124_state, sd);
261
262 st->adc_control &= ~AD7124_ADC_CTRL_MODE_MSK;
263 st->adc_control |= AD7124_ADC_CTRL_MODE(mode);
264
265 return ad_sd_write_reg(&st->sd, AD7124_ADC_CONTROL, 2, st->adc_control);
266 }
267
ad7124_set_channel_odr(struct ad7124_state * st,unsigned int channel,unsigned int odr)268 static void ad7124_set_channel_odr(struct ad7124_state *st, unsigned int channel, unsigned int odr)
269 {
270 unsigned int fclk, odr_sel_bits;
271
272 fclk = clk_get_rate(st->mclk);
273 /*
274 * FS[10:0] = fCLK / (fADC x 32) where:
275 * fADC is the output data rate
276 * fCLK is the master clock frequency
277 * FS[10:0] are the bits in the filter register
278 * FS[10:0] can have a value from 1 to 2047
279 */
280 odr_sel_bits = DIV_ROUND_CLOSEST(fclk, odr * 32);
281 if (odr_sel_bits < 1)
282 odr_sel_bits = 1;
283 else if (odr_sel_bits > 2047)
284 odr_sel_bits = 2047;
285
286 if (odr_sel_bits != st->channels[channel].cfg.odr_sel_bits)
287 st->channels[channel].cfg.live = false;
288
289 /* fADC = fCLK / (FS[10:0] x 32) */
290 st->channels[channel].cfg.odr = DIV_ROUND_CLOSEST(fclk, odr_sel_bits * 32);
291 st->channels[channel].cfg.odr_sel_bits = odr_sel_bits;
292 }
293
ad7124_get_3db_filter_freq(struct ad7124_state * st,unsigned int channel)294 static int ad7124_get_3db_filter_freq(struct ad7124_state *st,
295 unsigned int channel)
296 {
297 unsigned int fadc;
298
299 fadc = st->channels[channel].cfg.odr;
300
301 switch (st->channels[channel].cfg.filter_type) {
302 case AD7124_SINC3_FILTER:
303 return DIV_ROUND_CLOSEST(fadc * 272, 1000);
304 case AD7124_SINC4_FILTER:
305 return DIV_ROUND_CLOSEST(fadc * 230, 1000);
306 default:
307 return -EINVAL;
308 }
309 }
310
ad7124_set_3db_filter_freq(struct ad7124_state * st,unsigned int channel,unsigned int freq)311 static void ad7124_set_3db_filter_freq(struct ad7124_state *st, unsigned int channel,
312 unsigned int freq)
313 {
314 unsigned int sinc4_3db_odr;
315 unsigned int sinc3_3db_odr;
316 unsigned int new_filter;
317 unsigned int new_odr;
318
319 sinc4_3db_odr = DIV_ROUND_CLOSEST(freq * 1000, 230);
320 sinc3_3db_odr = DIV_ROUND_CLOSEST(freq * 1000, 262);
321
322 if (sinc4_3db_odr > sinc3_3db_odr) {
323 new_filter = AD7124_SINC3_FILTER;
324 new_odr = sinc4_3db_odr;
325 } else {
326 new_filter = AD7124_SINC4_FILTER;
327 new_odr = sinc3_3db_odr;
328 }
329
330 if (new_odr != st->channels[channel].cfg.odr)
331 st->channels[channel].cfg.live = false;
332
333 st->channels[channel].cfg.filter_type = new_filter;
334 st->channels[channel].cfg.odr = new_odr;
335 }
336
ad7124_find_similar_live_cfg(struct ad7124_state * st,struct ad7124_channel_config * cfg)337 static struct ad7124_channel_config *ad7124_find_similar_live_cfg(struct ad7124_state *st,
338 struct ad7124_channel_config *cfg)
339 {
340 struct ad7124_channel_config *cfg_aux;
341 int i;
342
343 /*
344 * This is just to make sure that the comparison is adapted after
345 * struct ad7124_channel_config was changed.
346 */
347 static_assert(sizeof_field(struct ad7124_channel_config, config_props) ==
348 sizeof(struct {
349 enum ad7124_ref_sel refsel;
350 bool bipolar;
351 bool buf_positive;
352 bool buf_negative;
353 unsigned int vref_mv;
354 unsigned int pga_bits;
355 unsigned int odr;
356 unsigned int odr_sel_bits;
357 unsigned int filter_type;
358 }));
359
360 for (i = 0; i < st->num_channels; i++) {
361 cfg_aux = &st->channels[i].cfg;
362
363 if (cfg_aux->live &&
364 cfg->refsel == cfg_aux->refsel &&
365 cfg->bipolar == cfg_aux->bipolar &&
366 cfg->buf_positive == cfg_aux->buf_positive &&
367 cfg->buf_negative == cfg_aux->buf_negative &&
368 cfg->vref_mv == cfg_aux->vref_mv &&
369 cfg->pga_bits == cfg_aux->pga_bits &&
370 cfg->odr == cfg_aux->odr &&
371 cfg->odr_sel_bits == cfg_aux->odr_sel_bits &&
372 cfg->filter_type == cfg_aux->filter_type)
373 return cfg_aux;
374 }
375
376 return NULL;
377 }
378
ad7124_find_free_config_slot(struct ad7124_state * st)379 static int ad7124_find_free_config_slot(struct ad7124_state *st)
380 {
381 unsigned int free_cfg_slot;
382
383 free_cfg_slot = find_first_zero_bit(&st->cfg_slots_status, AD7124_MAX_CONFIGS);
384 if (free_cfg_slot == AD7124_MAX_CONFIGS)
385 return -1;
386
387 return free_cfg_slot;
388 }
389
ad7124_init_config_vref(struct ad7124_state * st,struct ad7124_channel_config * cfg)390 static int ad7124_init_config_vref(struct ad7124_state *st, struct ad7124_channel_config *cfg)
391 {
392 unsigned int refsel = cfg->refsel;
393
394 switch (refsel) {
395 case AD7124_REFIN1:
396 case AD7124_REFIN2:
397 case AD7124_AVDD_REF:
398 if (IS_ERR(st->vref[refsel])) {
399 dev_err(&st->sd.spi->dev,
400 "Error, trying to use external voltage reference without a %s regulator.\n",
401 ad7124_ref_names[refsel]);
402 return PTR_ERR(st->vref[refsel]);
403 }
404 cfg->vref_mv = regulator_get_voltage(st->vref[refsel]);
405 /* Conversion from uV to mV */
406 cfg->vref_mv /= 1000;
407 return 0;
408 case AD7124_INT_REF:
409 cfg->vref_mv = 2500;
410 st->adc_control &= ~AD7124_ADC_CTRL_REF_EN_MSK;
411 st->adc_control |= AD7124_ADC_CTRL_REF_EN(1);
412 return 0;
413 default:
414 dev_err(&st->sd.spi->dev, "Invalid reference %d\n", refsel);
415 return -EINVAL;
416 }
417 }
418
ad7124_write_config(struct ad7124_state * st,struct ad7124_channel_config * cfg,unsigned int cfg_slot)419 static int ad7124_write_config(struct ad7124_state *st, struct ad7124_channel_config *cfg,
420 unsigned int cfg_slot)
421 {
422 unsigned int tmp;
423 unsigned int val;
424 int ret;
425
426 cfg->cfg_slot = cfg_slot;
427
428 tmp = (cfg->buf_positive << 1) + cfg->buf_negative;
429 val = AD7124_CONFIG_BIPOLAR(cfg->bipolar) | AD7124_CONFIG_REF_SEL(cfg->refsel) |
430 AD7124_CONFIG_IN_BUFF(tmp) | AD7124_CONFIG_PGA(cfg->pga_bits);
431
432 ret = ad_sd_write_reg(&st->sd, AD7124_CONFIG(cfg->cfg_slot), 2, val);
433 if (ret < 0)
434 return ret;
435
436 tmp = AD7124_FILTER_TYPE_SEL(cfg->filter_type) |
437 AD7124_FILTER_FS(cfg->odr_sel_bits);
438 return ad7124_spi_write_mask(st, AD7124_FILTER(cfg->cfg_slot),
439 AD7124_FILTER_TYPE_MSK | AD7124_FILTER_FS_MSK,
440 tmp, 3);
441 }
442
ad7124_pop_config(struct ad7124_state * st)443 static struct ad7124_channel_config *ad7124_pop_config(struct ad7124_state *st)
444 {
445 struct ad7124_channel_config *lru_cfg;
446 struct ad7124_channel_config *cfg;
447 int ret;
448 int i;
449
450 /*
451 * Pop least recently used config from the fifo
452 * in order to make room for the new one
453 */
454 ret = kfifo_get(&st->live_cfgs_fifo, &lru_cfg);
455 if (ret <= 0)
456 return NULL;
457
458 lru_cfg->live = false;
459
460 /* mark slot as free */
461 assign_bit(lru_cfg->cfg_slot, &st->cfg_slots_status, 0);
462
463 /* invalidate all other configs that pointed to this one */
464 for (i = 0; i < st->num_channels; i++) {
465 cfg = &st->channels[i].cfg;
466
467 if (cfg->cfg_slot == lru_cfg->cfg_slot)
468 cfg->live = false;
469 }
470
471 return lru_cfg;
472 }
473
ad7124_push_config(struct ad7124_state * st,struct ad7124_channel_config * cfg)474 static int ad7124_push_config(struct ad7124_state *st, struct ad7124_channel_config *cfg)
475 {
476 struct ad7124_channel_config *lru_cfg;
477 int free_cfg_slot;
478
479 free_cfg_slot = ad7124_find_free_config_slot(st);
480 if (free_cfg_slot >= 0) {
481 /* push the new config in configs queue */
482 kfifo_put(&st->live_cfgs_fifo, cfg);
483 } else {
484 /* pop one config to make room for the new one */
485 lru_cfg = ad7124_pop_config(st);
486 if (!lru_cfg)
487 return -EINVAL;
488
489 /* push the new config in configs queue */
490 free_cfg_slot = lru_cfg->cfg_slot;
491 kfifo_put(&st->live_cfgs_fifo, cfg);
492 }
493
494 /* mark slot as used */
495 assign_bit(free_cfg_slot, &st->cfg_slots_status, 1);
496
497 return ad7124_write_config(st, cfg, free_cfg_slot);
498 }
499
ad7124_enable_channel(struct ad7124_state * st,struct ad7124_channel * ch)500 static int ad7124_enable_channel(struct ad7124_state *st, struct ad7124_channel *ch)
501 {
502 ch->cfg.live = true;
503 return ad_sd_write_reg(&st->sd, AD7124_CHANNEL(ch->nr), 2, ch->ain |
504 AD7124_CHANNEL_SETUP(ch->cfg.cfg_slot) | AD7124_CHANNEL_EN(1));
505 }
506
ad7124_prepare_read(struct ad7124_state * st,int address)507 static int ad7124_prepare_read(struct ad7124_state *st, int address)
508 {
509 struct ad7124_channel_config *cfg = &st->channels[address].cfg;
510 struct ad7124_channel_config *live_cfg;
511
512 /*
513 * Before doing any reads assign the channel a configuration.
514 * Check if channel's config is on the device
515 */
516 if (!cfg->live) {
517 /* check if config matches another one */
518 live_cfg = ad7124_find_similar_live_cfg(st, cfg);
519 if (!live_cfg)
520 ad7124_push_config(st, cfg);
521 else
522 cfg->cfg_slot = live_cfg->cfg_slot;
523 }
524
525 /* point channel to the config slot and enable */
526 return ad7124_enable_channel(st, &st->channels[address]);
527 }
528
__ad7124_set_channel(struct ad_sigma_delta * sd,unsigned int channel)529 static int __ad7124_set_channel(struct ad_sigma_delta *sd, unsigned int channel)
530 {
531 struct ad7124_state *st = container_of(sd, struct ad7124_state, sd);
532
533 return ad7124_prepare_read(st, channel);
534 }
535
ad7124_set_channel(struct ad_sigma_delta * sd,unsigned int channel)536 static int ad7124_set_channel(struct ad_sigma_delta *sd, unsigned int channel)
537 {
538 struct ad7124_state *st = container_of(sd, struct ad7124_state, sd);
539 int ret;
540
541 mutex_lock(&st->cfgs_lock);
542 ret = __ad7124_set_channel(sd, channel);
543 mutex_unlock(&st->cfgs_lock);
544
545 return ret;
546 }
547
ad7124_append_status(struct ad_sigma_delta * sd,bool append)548 static int ad7124_append_status(struct ad_sigma_delta *sd, bool append)
549 {
550 struct ad7124_state *st = container_of(sd, struct ad7124_state, sd);
551 unsigned int adc_control = st->adc_control;
552 int ret;
553
554 adc_control &= ~AD7124_ADC_STATUS_EN_MSK;
555 adc_control |= AD7124_ADC_STATUS_EN(append);
556
557 ret = ad_sd_write_reg(&st->sd, AD7124_ADC_CONTROL, 2, adc_control);
558 if (ret < 0)
559 return ret;
560
561 st->adc_control = adc_control;
562
563 return 0;
564 }
565
ad7124_disable_all(struct ad_sigma_delta * sd)566 static int ad7124_disable_all(struct ad_sigma_delta *sd)
567 {
568 struct ad7124_state *st = container_of(sd, struct ad7124_state, sd);
569 int ret;
570 int i;
571
572 for (i = 0; i < st->num_channels; i++) {
573 ret = ad7124_spi_write_mask(st, AD7124_CHANNEL(i), AD7124_CHANNEL_EN_MSK, 0, 2);
574 if (ret < 0)
575 return ret;
576 }
577
578 return 0;
579 }
580
ad7124_disable_one(struct ad_sigma_delta * sd,unsigned int chan)581 static int ad7124_disable_one(struct ad_sigma_delta *sd, unsigned int chan)
582 {
583 struct ad7124_state *st = container_of(sd, struct ad7124_state, sd);
584
585 return ad7124_spi_write_mask(st, AD7124_CHANNEL(chan), AD7124_CHANNEL_EN_MSK, 0, 2);
586 }
587
588 static const struct ad_sigma_delta_info ad7124_sigma_delta_info = {
589 .set_channel = ad7124_set_channel,
590 .append_status = ad7124_append_status,
591 .disable_all = ad7124_disable_all,
592 .disable_one = ad7124_disable_one,
593 .set_mode = ad7124_set_mode,
594 .has_registers = true,
595 .addr_shift = 0,
596 .read_mask = BIT(6),
597 .status_ch_mask = GENMASK(3, 0),
598 .data_reg = AD7124_DATA,
599 .num_slots = 8,
600 .irq_flags = IRQF_TRIGGER_FALLING,
601 };
602
ad7124_read_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int * val,int * val2,long info)603 static int ad7124_read_raw(struct iio_dev *indio_dev,
604 struct iio_chan_spec const *chan,
605 int *val, int *val2, long info)
606 {
607 struct ad7124_state *st = iio_priv(indio_dev);
608 int idx, ret;
609
610 switch (info) {
611 case IIO_CHAN_INFO_RAW:
612 ret = ad_sigma_delta_single_conversion(indio_dev, chan, val);
613 if (ret < 0)
614 return ret;
615
616 return IIO_VAL_INT;
617 case IIO_CHAN_INFO_SCALE:
618 mutex_lock(&st->cfgs_lock);
619
620 idx = st->channels[chan->address].cfg.pga_bits;
621 *val = st->channels[chan->address].cfg.vref_mv;
622 if (st->channels[chan->address].cfg.bipolar)
623 *val2 = chan->scan_type.realbits - 1 + idx;
624 else
625 *val2 = chan->scan_type.realbits + idx;
626
627 mutex_unlock(&st->cfgs_lock);
628 return IIO_VAL_FRACTIONAL_LOG2;
629 case IIO_CHAN_INFO_OFFSET:
630 mutex_lock(&st->cfgs_lock);
631 if (st->channels[chan->address].cfg.bipolar)
632 *val = -(1 << (chan->scan_type.realbits - 1));
633 else
634 *val = 0;
635
636 mutex_unlock(&st->cfgs_lock);
637 return IIO_VAL_INT;
638 case IIO_CHAN_INFO_SAMP_FREQ:
639 mutex_lock(&st->cfgs_lock);
640 *val = st->channels[chan->address].cfg.odr;
641 mutex_unlock(&st->cfgs_lock);
642
643 return IIO_VAL_INT;
644 case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY:
645 mutex_lock(&st->cfgs_lock);
646 *val = ad7124_get_3db_filter_freq(st, chan->scan_index);
647 mutex_unlock(&st->cfgs_lock);
648
649 return IIO_VAL_INT;
650 default:
651 return -EINVAL;
652 }
653 }
654
ad7124_write_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int val,int val2,long info)655 static int ad7124_write_raw(struct iio_dev *indio_dev,
656 struct iio_chan_spec const *chan,
657 int val, int val2, long info)
658 {
659 struct ad7124_state *st = iio_priv(indio_dev);
660 unsigned int res, gain, full_scale, vref;
661 int ret = 0;
662
663 mutex_lock(&st->cfgs_lock);
664
665 switch (info) {
666 case IIO_CHAN_INFO_SAMP_FREQ:
667 if (val2 != 0 || val == 0) {
668 ret = -EINVAL;
669 break;
670 }
671
672 ad7124_set_channel_odr(st, chan->address, val);
673 break;
674 case IIO_CHAN_INFO_SCALE:
675 if (val != 0) {
676 ret = -EINVAL;
677 break;
678 }
679
680 if (st->channels[chan->address].cfg.bipolar)
681 full_scale = 1 << (chan->scan_type.realbits - 1);
682 else
683 full_scale = 1 << chan->scan_type.realbits;
684
685 vref = st->channels[chan->address].cfg.vref_mv * 1000000LL;
686 res = DIV_ROUND_CLOSEST(vref, full_scale);
687 gain = DIV_ROUND_CLOSEST(res, val2);
688 res = ad7124_find_closest_match(ad7124_gain, ARRAY_SIZE(ad7124_gain), gain);
689
690 if (st->channels[chan->address].cfg.pga_bits != res)
691 st->channels[chan->address].cfg.live = false;
692
693 st->channels[chan->address].cfg.pga_bits = res;
694 break;
695 case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY:
696 if (val2 != 0) {
697 ret = -EINVAL;
698 break;
699 }
700
701 ad7124_set_3db_filter_freq(st, chan->address, val);
702 break;
703 default:
704 ret = -EINVAL;
705 }
706
707 mutex_unlock(&st->cfgs_lock);
708 return ret;
709 }
710
ad7124_reg_access(struct iio_dev * indio_dev,unsigned int reg,unsigned int writeval,unsigned int * readval)711 static int ad7124_reg_access(struct iio_dev *indio_dev,
712 unsigned int reg,
713 unsigned int writeval,
714 unsigned int *readval)
715 {
716 struct ad7124_state *st = iio_priv(indio_dev);
717 int ret;
718
719 if (reg >= ARRAY_SIZE(ad7124_reg_size))
720 return -EINVAL;
721
722 if (readval)
723 ret = ad_sd_read_reg(&st->sd, reg, ad7124_reg_size[reg],
724 readval);
725 else
726 ret = ad_sd_write_reg(&st->sd, reg, ad7124_reg_size[reg],
727 writeval);
728
729 return ret;
730 }
731
732 static IIO_CONST_ATTR(in_voltage_scale_available,
733 "0.000001164 0.000002328 0.000004656 0.000009313 0.000018626 0.000037252 0.000074505 0.000149011 0.000298023");
734
735 static struct attribute *ad7124_attributes[] = {
736 &iio_const_attr_in_voltage_scale_available.dev_attr.attr,
737 NULL,
738 };
739
740 static const struct attribute_group ad7124_attrs_group = {
741 .attrs = ad7124_attributes,
742 };
743
ad7124_update_scan_mode(struct iio_dev * indio_dev,const unsigned long * scan_mask)744 static int ad7124_update_scan_mode(struct iio_dev *indio_dev,
745 const unsigned long *scan_mask)
746 {
747 struct ad7124_state *st = iio_priv(indio_dev);
748 bool bit_set;
749 int ret;
750 int i;
751
752 mutex_lock(&st->cfgs_lock);
753 for (i = 0; i < st->num_channels; i++) {
754 bit_set = test_bit(i, scan_mask);
755 if (bit_set)
756 ret = __ad7124_set_channel(&st->sd, i);
757 else
758 ret = ad7124_spi_write_mask(st, AD7124_CHANNEL(i), AD7124_CHANNEL_EN_MSK,
759 0, 2);
760 if (ret < 0) {
761 mutex_unlock(&st->cfgs_lock);
762
763 return ret;
764 }
765 }
766
767 mutex_unlock(&st->cfgs_lock);
768
769 return 0;
770 }
771
772 static const struct iio_info ad7124_info = {
773 .read_raw = ad7124_read_raw,
774 .write_raw = ad7124_write_raw,
775 .debugfs_reg_access = &ad7124_reg_access,
776 .validate_trigger = ad_sd_validate_trigger,
777 .update_scan_mode = ad7124_update_scan_mode,
778 .attrs = &ad7124_attrs_group,
779 };
780
ad7124_soft_reset(struct ad7124_state * st)781 static int ad7124_soft_reset(struct ad7124_state *st)
782 {
783 unsigned int readval, timeout;
784 int ret;
785
786 ret = ad_sd_reset(&st->sd, 64);
787 if (ret < 0)
788 return ret;
789
790 fsleep(200);
791 timeout = 100;
792 do {
793 ret = ad_sd_read_reg(&st->sd, AD7124_STATUS, 1, &readval);
794 if (ret < 0)
795 return ret;
796
797 if (!(readval & AD7124_STATUS_POR_FLAG_MSK))
798 return 0;
799
800 /* The AD7124 requires typically 2ms to power up and settle */
801 usleep_range(100, 2000);
802 } while (--timeout);
803
804 dev_err(&st->sd.spi->dev, "Soft reset failed\n");
805
806 return -EIO;
807 }
808
ad7124_check_chip_id(struct ad7124_state * st)809 static int ad7124_check_chip_id(struct ad7124_state *st)
810 {
811 unsigned int readval, chip_id, silicon_rev;
812 int ret;
813
814 ret = ad_sd_read_reg(&st->sd, AD7124_ID, 1, &readval);
815 if (ret < 0)
816 return ret;
817
818 chip_id = AD7124_DEVICE_ID_GET(readval);
819 silicon_rev = AD7124_SILICON_REV_GET(readval);
820
821 if (chip_id != st->chip_info->chip_id) {
822 dev_err(&st->sd.spi->dev,
823 "Chip ID mismatch: expected %u, got %u\n",
824 st->chip_info->chip_id, chip_id);
825 return -ENODEV;
826 }
827
828 if (silicon_rev == 0) {
829 dev_err(&st->sd.spi->dev,
830 "Silicon revision empty. Chip may not be present\n");
831 return -ENODEV;
832 }
833
834 return 0;
835 }
836
ad7124_parse_channel_config(struct iio_dev * indio_dev,struct device * dev)837 static int ad7124_parse_channel_config(struct iio_dev *indio_dev,
838 struct device *dev)
839 {
840 struct ad7124_state *st = iio_priv(indio_dev);
841 struct ad7124_channel_config *cfg;
842 struct ad7124_channel *channels;
843 struct iio_chan_spec *chan;
844 unsigned int ain[2], channel = 0, tmp;
845 int ret;
846
847 st->num_channels = device_get_child_node_count(dev);
848 if (!st->num_channels)
849 return dev_err_probe(dev, -ENODEV, "no channel children\n");
850
851 chan = devm_kcalloc(indio_dev->dev.parent, st->num_channels,
852 sizeof(*chan), GFP_KERNEL);
853 if (!chan)
854 return -ENOMEM;
855
856 channels = devm_kcalloc(indio_dev->dev.parent, st->num_channels, sizeof(*channels),
857 GFP_KERNEL);
858 if (!channels)
859 return -ENOMEM;
860
861 indio_dev->channels = chan;
862 indio_dev->num_channels = st->num_channels;
863 st->channels = channels;
864
865 device_for_each_child_node_scoped(dev, child) {
866 ret = fwnode_property_read_u32(child, "reg", &channel);
867 if (ret)
868 return ret;
869
870 if (channel >= indio_dev->num_channels)
871 return dev_err_probe(dev, -EINVAL,
872 "Channel index >= number of channels\n");
873
874 ret = fwnode_property_read_u32_array(child, "diff-channels",
875 ain, 2);
876 if (ret)
877 return ret;
878
879 st->channels[channel].nr = channel;
880 st->channels[channel].ain = AD7124_CHANNEL_AINP(ain[0]) |
881 AD7124_CHANNEL_AINM(ain[1]);
882
883 cfg = &st->channels[channel].cfg;
884 cfg->bipolar = fwnode_property_read_bool(child, "bipolar");
885
886 ret = fwnode_property_read_u32(child, "adi,reference-select", &tmp);
887 if (ret)
888 cfg->refsel = AD7124_INT_REF;
889 else
890 cfg->refsel = tmp;
891
892 cfg->buf_positive =
893 fwnode_property_read_bool(child, "adi,buffered-positive");
894 cfg->buf_negative =
895 fwnode_property_read_bool(child, "adi,buffered-negative");
896
897 chan[channel] = ad7124_channel_template;
898 chan[channel].address = channel;
899 chan[channel].scan_index = channel;
900 chan[channel].channel = ain[0];
901 chan[channel].channel2 = ain[1];
902 }
903
904 return 0;
905 }
906
ad7124_setup(struct ad7124_state * st)907 static int ad7124_setup(struct ad7124_state *st)
908 {
909 unsigned int fclk, power_mode;
910 int i, ret;
911
912 fclk = clk_get_rate(st->mclk);
913 if (!fclk)
914 return -EINVAL;
915
916 /* The power mode changes the master clock frequency */
917 power_mode = ad7124_find_closest_match(ad7124_master_clk_freq_hz,
918 ARRAY_SIZE(ad7124_master_clk_freq_hz),
919 fclk);
920 if (fclk != ad7124_master_clk_freq_hz[power_mode]) {
921 ret = clk_set_rate(st->mclk, fclk);
922 if (ret)
923 return ret;
924 }
925
926 /* Set the power mode */
927 st->adc_control &= ~AD7124_ADC_CTRL_PWR_MSK;
928 st->adc_control |= AD7124_ADC_CTRL_PWR(power_mode);
929
930 st->adc_control &= ~AD7124_ADC_CTRL_MODE_MSK;
931 st->adc_control |= AD7124_ADC_CTRL_MODE(AD_SD_MODE_IDLE);
932
933 mutex_init(&st->cfgs_lock);
934 INIT_KFIFO(st->live_cfgs_fifo);
935 for (i = 0; i < st->num_channels; i++) {
936
937 ret = ad7124_init_config_vref(st, &st->channels[i].cfg);
938 if (ret < 0)
939 return ret;
940
941 /*
942 * 9.38 SPS is the minimum output data rate supported
943 * regardless of the selected power mode. Round it up to 10 and
944 * set all channels to this default value.
945 */
946 ad7124_set_channel_odr(st, i, 10);
947
948 /* Disable all channels to prevent unintended conversions. */
949 ad_sd_write_reg(&st->sd, AD7124_CHANNEL(i), 2, 0);
950 }
951
952 ret = ad_sd_write_reg(&st->sd, AD7124_ADC_CONTROL, 2, st->adc_control);
953 if (ret < 0)
954 return ret;
955
956 return ret;
957 }
958
ad7124_reg_disable(void * r)959 static void ad7124_reg_disable(void *r)
960 {
961 regulator_disable(r);
962 }
963
ad7124_probe(struct spi_device * spi)964 static int ad7124_probe(struct spi_device *spi)
965 {
966 const struct ad7124_chip_info *info;
967 struct ad7124_state *st;
968 struct iio_dev *indio_dev;
969 int i, ret;
970
971 info = spi_get_device_match_data(spi);
972 if (!info)
973 return -ENODEV;
974
975 indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));
976 if (!indio_dev)
977 return -ENOMEM;
978
979 st = iio_priv(indio_dev);
980
981 st->chip_info = info;
982
983 indio_dev->name = st->chip_info->name;
984 indio_dev->modes = INDIO_DIRECT_MODE;
985 indio_dev->info = &ad7124_info;
986
987 ret = ad_sd_init(&st->sd, indio_dev, spi, &ad7124_sigma_delta_info);
988 if (ret < 0)
989 return ret;
990
991 ret = ad7124_parse_channel_config(indio_dev, &spi->dev);
992 if (ret < 0)
993 return ret;
994
995 for (i = 0; i < ARRAY_SIZE(st->vref); i++) {
996 if (i == AD7124_INT_REF)
997 continue;
998
999 st->vref[i] = devm_regulator_get_optional(&spi->dev,
1000 ad7124_ref_names[i]);
1001 if (PTR_ERR(st->vref[i]) == -ENODEV)
1002 continue;
1003 else if (IS_ERR(st->vref[i]))
1004 return PTR_ERR(st->vref[i]);
1005
1006 ret = regulator_enable(st->vref[i]);
1007 if (ret)
1008 return ret;
1009
1010 ret = devm_add_action_or_reset(&spi->dev, ad7124_reg_disable,
1011 st->vref[i]);
1012 if (ret)
1013 return ret;
1014 }
1015
1016 st->mclk = devm_clk_get_enabled(&spi->dev, "mclk");
1017 if (IS_ERR(st->mclk))
1018 return PTR_ERR(st->mclk);
1019
1020 ret = ad7124_soft_reset(st);
1021 if (ret < 0)
1022 return ret;
1023
1024 ret = ad7124_check_chip_id(st);
1025 if (ret)
1026 return ret;
1027
1028 ret = ad7124_setup(st);
1029 if (ret < 0)
1030 return ret;
1031
1032 ret = devm_ad_sd_setup_buffer_and_trigger(&spi->dev, indio_dev);
1033 if (ret < 0)
1034 return ret;
1035
1036 return devm_iio_device_register(&spi->dev, indio_dev);
1037
1038 }
1039
1040 static const struct of_device_id ad7124_of_match[] = {
1041 { .compatible = "adi,ad7124-4",
1042 .data = &ad7124_chip_info_tbl[ID_AD7124_4], },
1043 { .compatible = "adi,ad7124-8",
1044 .data = &ad7124_chip_info_tbl[ID_AD7124_8], },
1045 { }
1046 };
1047 MODULE_DEVICE_TABLE(of, ad7124_of_match);
1048
1049 static const struct spi_device_id ad71124_ids[] = {
1050 { "ad7124-4", (kernel_ulong_t)&ad7124_chip_info_tbl[ID_AD7124_4] },
1051 { "ad7124-8", (kernel_ulong_t)&ad7124_chip_info_tbl[ID_AD7124_8] },
1052 { }
1053 };
1054 MODULE_DEVICE_TABLE(spi, ad71124_ids);
1055
1056 static struct spi_driver ad71124_driver = {
1057 .driver = {
1058 .name = "ad7124",
1059 .of_match_table = ad7124_of_match,
1060 },
1061 .probe = ad7124_probe,
1062 .id_table = ad71124_ids,
1063 };
1064 module_spi_driver(ad71124_driver);
1065
1066 MODULE_AUTHOR("Stefan Popa <stefan.popa@analog.com>");
1067 MODULE_DESCRIPTION("Analog Devices AD7124 SPI driver");
1068 MODULE_LICENSE("GPL");
1069 MODULE_IMPORT_NS(IIO_AD_SIGMA_DELTA);
1070