1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * AD717x and AD411x family SPI ADC driver
4 *
5 * Supported devices:
6 * AD4111/AD4112/AD4114/AD4115/AD4116
7 * AD7172-2/AD7172-4/AD7173-8/AD7175-2
8 * AD7175-8/AD7176-2/AD7177-2
9 *
10 * Copyright (C) 2015, 2024 Analog Devices, Inc.
11 */
12
13 #include <linux/array_size.h>
14 #include <linux/bitfield.h>
15 #include <linux/bitmap.h>
16 #include <linux/container_of.h>
17 #include <linux/clk.h>
18 #include <linux/clk-provider.h>
19 #include <linux/delay.h>
20 #include <linux/device.h>
21 #include <linux/err.h>
22 #include <linux/gpio/driver.h>
23 #include <linux/gpio/regmap.h>
24 #include <linux/idr.h>
25 #include <linux/interrupt.h>
26 #include <linux/math64.h>
27 #include <linux/module.h>
28 #include <linux/mod_devicetable.h>
29 #include <linux/property.h>
30 #include <linux/regmap.h>
31 #include <linux/regulator/consumer.h>
32 #include <linux/slab.h>
33 #include <linux/spi/spi.h>
34 #include <linux/types.h>
35 #include <linux/units.h>
36
37 #include <linux/iio/buffer.h>
38 #include <linux/iio/iio.h>
39 #include <linux/iio/trigger_consumer.h>
40 #include <linux/iio/triggered_buffer.h>
41
42 #include <linux/iio/adc/ad_sigma_delta.h>
43
44 #define AD7173_REG_COMMS 0x00
45 #define AD7173_REG_ADC_MODE 0x01
46 #define AD7173_REG_INTERFACE_MODE 0x02
47 #define AD7173_REG_CRC 0x03
48 #define AD7173_REG_DATA 0x04
49 #define AD7173_REG_GPIO 0x06
50 #define AD7173_REG_ID 0x07
51 #define AD7173_REG_CH(x) (0x10 + (x))
52 #define AD7173_REG_SETUP(x) (0x20 + (x))
53 #define AD7173_REG_FILTER(x) (0x28 + (x))
54 #define AD7173_REG_OFFSET(x) (0x30 + (x))
55 #define AD7173_REG_GAIN(x) (0x38 + (x))
56
57 #define AD7173_RESET_LENGTH BITS_TO_BYTES(64)
58
59 #define AD7173_CH_ENABLE BIT(15)
60 #define AD7173_CH_SETUP_SEL_MASK GENMASK(14, 12)
61 #define AD7173_CH_SETUP_AINPOS_MASK GENMASK(9, 5)
62 #define AD7173_CH_SETUP_AINNEG_MASK GENMASK(4, 0)
63
64 #define AD7173_NO_AINS_PER_CHANNEL 2
65 #define AD7173_CH_ADDRESS(pos, neg) \
66 (FIELD_PREP(AD7173_CH_SETUP_AINPOS_MASK, pos) | \
67 FIELD_PREP(AD7173_CH_SETUP_AINNEG_MASK, neg))
68 #define AD7173_AIN_TEMP_POS 17
69 #define AD7173_AIN_TEMP_NEG 18
70 #define AD7173_AIN_POW_MON_POS 19
71 #define AD7173_AIN_POW_MON_NEG 20
72 #define AD7173_AIN_REF_POS 21
73 #define AD7173_AIN_REF_NEG 22
74
75 #define AD7173_IS_REF_INPUT(x) ((x) == AD7173_AIN_REF_POS || \
76 (x) == AD7173_AIN_REF_NEG)
77
78 #define AD7172_2_ID 0x00d0
79 #define AD7175_ID 0x0cd0
80 #define AD7176_ID 0x0c90
81 #define AD7175_2_ID 0x0cd0
82 #define AD7172_4_ID 0x2050
83 #define AD7173_ID 0x30d0
84 #define AD4111_ID AD7173_ID
85 #define AD4112_ID AD7173_ID
86 #define AD4114_ID AD7173_ID
87 #define AD4116_ID 0x34d0
88 #define AD4115_ID 0x38d0
89 #define AD7175_8_ID 0x3cd0
90 #define AD7177_ID 0x4fd0
91 #define AD7173_ID_MASK GENMASK(15, 4)
92
93 #define AD7173_ADC_MODE_REF_EN BIT(15)
94 #define AD7173_ADC_MODE_SING_CYC BIT(13)
95 #define AD7173_ADC_MODE_MODE_MASK GENMASK(6, 4)
96 #define AD7173_ADC_MODE_CLOCKSEL_MASK GENMASK(3, 2)
97 #define AD7173_ADC_MODE_CLOCKSEL_INT 0x0
98 #define AD7173_ADC_MODE_CLOCKSEL_INT_OUTPUT 0x1
99 #define AD7173_ADC_MODE_CLOCKSEL_EXT 0x2
100 #define AD7173_ADC_MODE_CLOCKSEL_XTAL 0x3
101
102 #define AD7173_GPIO_PDSW BIT(14)
103 #define AD7173_GPIO_OP_EN2_3 BIT(13)
104 #define AD7173_GPIO_MUX_IO BIT(12)
105 #define AD7173_GPIO_SYNC_EN BIT(11)
106 #define AD7173_GPIO_ERR_EN BIT(10)
107 #define AD7173_GPIO_ERR_DAT BIT(9)
108 #define AD7173_GPIO_GP_DATA3 BIT(7)
109 #define AD7173_GPIO_GP_DATA2 BIT(6)
110 #define AD7173_GPIO_IP_EN1 BIT(5)
111 #define AD7173_GPIO_IP_EN0 BIT(4)
112 #define AD7173_GPIO_OP_EN1 BIT(3)
113 #define AD7173_GPIO_OP_EN0 BIT(2)
114 #define AD7173_GPIO_GP_DATA1 BIT(1)
115 #define AD7173_GPIO_GP_DATA0 BIT(0)
116
117 #define AD7173_GPO12_DATA(x) BIT((x) + 0)
118 #define AD7173_GPO23_DATA(x) BIT((x) + 4)
119 #define AD4111_GPO01_DATA(x) BIT((x) + 6)
120 #define AD7173_GPO_DATA(x) ((x) < 2 ? AD7173_GPO12_DATA(x) : AD7173_GPO23_DATA(x))
121
122 #define AD7173_INTERFACE_DATA_STAT BIT(6)
123 #define AD7173_INTERFACE_DATA_STAT_EN(x) \
124 FIELD_PREP(AD7173_INTERFACE_DATA_STAT, x)
125
126 #define AD7173_SETUP_BIPOLAR BIT(12)
127 #define AD7173_SETUP_AREF_BUF_MASK GENMASK(11, 10)
128 #define AD7173_SETUP_AIN_BUF_MASK GENMASK(9, 8)
129
130 #define AD7173_SETUP_REF_SEL_MASK GENMASK(5, 4)
131 #define AD7173_SETUP_REF_SEL_AVDD1_AVSS 0x3
132 #define AD7173_SETUP_REF_SEL_INT_REF 0x2
133 #define AD7173_SETUP_REF_SEL_EXT_REF2 0x1
134 #define AD7173_SETUP_REF_SEL_EXT_REF 0x0
135 #define AD7173_VOLTAGE_INT_REF_uV 2500000
136 #define AD7173_TEMP_SENSIIVITY_uV_per_C 477
137 #define AD7177_ODR_START_VALUE 0x07
138 #define AD4111_SHUNT_RESISTOR_OHM 50
139 #define AD4111_DIVIDER_RATIO 10
140 #define AD4111_CURRENT_CHAN_CUTOFF 16
141 #define AD4111_VINCOM_INPUT 0x10
142
143 /* pin < num_voltage_in is a normal voltage input */
144 /* pin >= num_voltage_in_div is a voltage input without a divider */
145 #define AD4111_IS_VINCOM_MISMATCH(pin1, pin2) ((pin1) == AD4111_VINCOM_INPUT && \
146 (pin2) < st->info->num_voltage_in && \
147 (pin2) >= st->info->num_voltage_in_div)
148
149 #define AD7173_FILTER_ODR0_MASK GENMASK(5, 0)
150 #define AD7173_MAX_CONFIGS 8
151
152 struct ad7173_device_info {
153 const unsigned int *sinc5_data_rates;
154 unsigned int num_sinc5_data_rates;
155 unsigned int odr_start_value;
156 /*
157 * AD4116 has both inputs with a voltage divider and without.
158 * These inputs cannot be mixed in the channel configuration.
159 * Does not include the VINCOM input.
160 */
161 unsigned int num_voltage_in_div;
162 unsigned int num_channels;
163 unsigned int num_configs;
164 unsigned int num_voltage_in;
165 unsigned int clock;
166 unsigned int id;
167 char *name;
168 bool has_current_inputs;
169 bool has_vincom_input;
170 bool has_temp;
171 /* ((AVDD1 − AVSS)/5) */
172 bool has_pow_supply_monitoring;
173 bool has_input_buf;
174 bool has_int_ref;
175 bool has_ref2;
176 bool higher_gpio_bits;
177 u8 num_gpios;
178 };
179
180 struct ad7173_channel_config {
181 u8 cfg_slot;
182 bool live;
183
184 /*
185 * Following fields are used to compare equality. If you
186 * make adaptations in it, you most likely also have to adapt
187 * ad7173_find_live_config(), too.
188 */
189 struct_group(config_props,
190 bool bipolar;
191 bool input_buf;
192 u8 odr;
193 u8 ref_sel;
194 );
195 };
196
197 struct ad7173_channel {
198 unsigned int chan_reg;
199 unsigned int ain;
200 struct ad7173_channel_config cfg;
201 };
202
203 struct ad7173_state {
204 struct ad_sigma_delta sd;
205 struct ad_sigma_delta_info sigma_delta_info;
206 const struct ad7173_device_info *info;
207 struct ad7173_channel *channels;
208 struct regulator_bulk_data regulators[3];
209 unsigned int adc_mode;
210 unsigned int interface_mode;
211 unsigned int num_channels;
212 struct ida cfg_slots_status;
213 unsigned long long config_usage_counter;
214 unsigned long long *config_cnts;
215 struct clk *ext_clk;
216 struct clk_hw int_clk_hw;
217 #if IS_ENABLED(CONFIG_GPIOLIB)
218 struct regmap *reg_gpiocon_regmap;
219 struct gpio_regmap *gpio_regmap;
220 #endif
221 };
222
223 static unsigned int ad4115_sinc5_data_rates[] = {
224 24845000, 24845000, 20725000, 20725000, /* 0-3 */
225 15564000, 13841000, 10390000, 10390000, /* 4-7 */
226 4994000, 2499000, 1000000, 500000, /* 8-11 */
227 395500, 200000, 100000, 59890, /* 12-15 */
228 49920, 20000, 16660, 10000, /* 16-19 */
229 5000, 2500, 2500, /* 20-22 */
230 };
231
232 static unsigned int ad4116_sinc5_data_rates[] = {
233 12422360, 12422360, 12422360, 12422360, /* 0-3 */
234 10362690, 10362690, 7782100, 6290530, /* 4-7 */
235 5194800, 2496900, 1007600, 499900, /* 8-11 */
236 390600, 200300, 100000, 59750, /* 12-15 */
237 49840, 20000, 16650, 10000, /* 16-19 */
238 5000, 2500, 1250, /* 20-22 */
239 };
240
241 static const unsigned int ad7173_sinc5_data_rates[] = {
242 6211000, 6211000, 6211000, 6211000, 6211000, 6211000, 5181000, 4444000, /* 0-7 */
243 3115000, 2597000, 1007000, 503800, 381000, 200300, 100500, 59520, /* 8-15 */
244 49680, 20010, 16333, 10000, 5000, 2500, 1250, /* 16-22 */
245 };
246
247 static const unsigned int ad7175_sinc5_data_rates[] = {
248 50000000, 41667000, 31250000, 27778000, /* 0-3 */
249 20833000, 17857000, 12500000, 10000000, /* 4-7 */
250 5000000, 2500000, 1000000, 500000, /* 8-11 */
251 397500, 200000, 100000, 59920, /* 12-15 */
252 49960, 20000, 16666, 10000, /* 16-19 */
253 5000, /* 20 */
254 };
255
256 static unsigned int ad4111_current_channel_config[] = {
257 /* Ain sel: pos neg */
258 0x1E8, /* 15:IIN0+ 8:IIN0− */
259 0x1C9, /* 14:IIN1+ 9:IIN1− */
260 0x1AA, /* 13:IIN2+ 10:IIN2− */
261 0x18B, /* 12:IIN3+ 11:IIN3− */
262 };
263
264 static const struct ad7173_device_info ad4111_device_info = {
265 .name = "ad4111",
266 .id = AD4111_ID,
267 .num_voltage_in_div = 8,
268 .num_channels = 16,
269 .num_configs = 8,
270 .num_voltage_in = 8,
271 .num_gpios = 2,
272 .higher_gpio_bits = true,
273 .has_temp = true,
274 .has_vincom_input = true,
275 .has_input_buf = true,
276 .has_current_inputs = true,
277 .has_int_ref = true,
278 .clock = 2 * HZ_PER_MHZ,
279 .sinc5_data_rates = ad7173_sinc5_data_rates,
280 .num_sinc5_data_rates = ARRAY_SIZE(ad7173_sinc5_data_rates),
281 };
282
283 static const struct ad7173_device_info ad4112_device_info = {
284 .name = "ad4112",
285 .id = AD4112_ID,
286 .num_voltage_in_div = 8,
287 .num_channels = 16,
288 .num_configs = 8,
289 .num_voltage_in = 8,
290 .num_gpios = 2,
291 .higher_gpio_bits = true,
292 .has_vincom_input = true,
293 .has_temp = true,
294 .has_input_buf = true,
295 .has_current_inputs = true,
296 .has_int_ref = true,
297 .clock = 2 * HZ_PER_MHZ,
298 .sinc5_data_rates = ad7173_sinc5_data_rates,
299 .num_sinc5_data_rates = ARRAY_SIZE(ad7173_sinc5_data_rates),
300 };
301
302 static const struct ad7173_device_info ad4114_device_info = {
303 .name = "ad4114",
304 .id = AD4114_ID,
305 .num_voltage_in_div = 16,
306 .num_channels = 16,
307 .num_configs = 8,
308 .num_voltage_in = 16,
309 .num_gpios = 4,
310 .has_vincom_input = true,
311 .has_temp = true,
312 .has_input_buf = true,
313 .has_int_ref = true,
314 .clock = 2 * HZ_PER_MHZ,
315 .sinc5_data_rates = ad7173_sinc5_data_rates,
316 .num_sinc5_data_rates = ARRAY_SIZE(ad7173_sinc5_data_rates),
317 };
318
319 static const struct ad7173_device_info ad4115_device_info = {
320 .name = "ad4115",
321 .id = AD4115_ID,
322 .num_voltage_in_div = 16,
323 .num_channels = 16,
324 .num_configs = 8,
325 .num_voltage_in = 16,
326 .num_gpios = 4,
327 .has_vincom_input = true,
328 .has_temp = true,
329 .has_input_buf = true,
330 .has_int_ref = true,
331 .clock = 8 * HZ_PER_MHZ,
332 .sinc5_data_rates = ad4115_sinc5_data_rates,
333 .num_sinc5_data_rates = ARRAY_SIZE(ad4115_sinc5_data_rates),
334 };
335
336 static const struct ad7173_device_info ad4116_device_info = {
337 .name = "ad4116",
338 .id = AD4116_ID,
339 .num_voltage_in_div = 11,
340 .num_channels = 16,
341 .num_configs = 8,
342 .num_voltage_in = 16,
343 .num_gpios = 4,
344 .has_vincom_input = true,
345 .has_temp = true,
346 .has_input_buf = true,
347 .has_int_ref = true,
348 .clock = 4 * HZ_PER_MHZ,
349 .sinc5_data_rates = ad4116_sinc5_data_rates,
350 .num_sinc5_data_rates = ARRAY_SIZE(ad4116_sinc5_data_rates),
351 };
352
353 static const struct ad7173_device_info ad7172_2_device_info = {
354 .name = "ad7172-2",
355 .id = AD7172_2_ID,
356 .num_voltage_in = 5,
357 .num_channels = 4,
358 .num_configs = 4,
359 .num_gpios = 2,
360 .has_temp = true,
361 .has_input_buf = true,
362 .has_int_ref = true,
363 .has_pow_supply_monitoring = true,
364 .clock = 2 * HZ_PER_MHZ,
365 .sinc5_data_rates = ad7173_sinc5_data_rates,
366 .num_sinc5_data_rates = ARRAY_SIZE(ad7173_sinc5_data_rates),
367 };
368
369 static const struct ad7173_device_info ad7172_4_device_info = {
370 .name = "ad7172-4",
371 .id = AD7172_4_ID,
372 .num_voltage_in = 9,
373 .num_channels = 8,
374 .num_configs = 8,
375 .num_gpios = 4,
376 .has_input_buf = true,
377 .has_ref2 = true,
378 .has_pow_supply_monitoring = true,
379 .clock = 2 * HZ_PER_MHZ,
380 .sinc5_data_rates = ad7173_sinc5_data_rates,
381 .num_sinc5_data_rates = ARRAY_SIZE(ad7173_sinc5_data_rates),
382 };
383
384 static const struct ad7173_device_info ad7173_8_device_info = {
385 .name = "ad7173-8",
386 .id = AD7173_ID,
387 .num_voltage_in = 17,
388 .num_channels = 16,
389 .num_configs = 8,
390 .num_gpios = 4,
391 .has_temp = true,
392 .has_input_buf = true,
393 .has_int_ref = true,
394 .has_ref2 = true,
395 .clock = 2 * HZ_PER_MHZ,
396 .sinc5_data_rates = ad7173_sinc5_data_rates,
397 .num_sinc5_data_rates = ARRAY_SIZE(ad7173_sinc5_data_rates),
398 };
399
400 static const struct ad7173_device_info ad7175_2_device_info = {
401 .name = "ad7175-2",
402 .id = AD7175_2_ID,
403 .num_voltage_in = 5,
404 .num_channels = 4,
405 .num_configs = 4,
406 .num_gpios = 2,
407 .has_temp = true,
408 .has_input_buf = true,
409 .has_int_ref = true,
410 .has_pow_supply_monitoring = true,
411 .clock = 16 * HZ_PER_MHZ,
412 .sinc5_data_rates = ad7175_sinc5_data_rates,
413 .num_sinc5_data_rates = ARRAY_SIZE(ad7175_sinc5_data_rates),
414 };
415
416 static const struct ad7173_device_info ad7175_8_device_info = {
417 .name = "ad7175-8",
418 .id = AD7175_8_ID,
419 .num_voltage_in = 17,
420 .num_channels = 16,
421 .num_configs = 8,
422 .num_gpios = 4,
423 .has_temp = true,
424 .has_input_buf = true,
425 .has_int_ref = true,
426 .has_ref2 = true,
427 .has_pow_supply_monitoring = true,
428 .clock = 16 * HZ_PER_MHZ,
429 .sinc5_data_rates = ad7175_sinc5_data_rates,
430 .num_sinc5_data_rates = ARRAY_SIZE(ad7175_sinc5_data_rates),
431 };
432
433 static const struct ad7173_device_info ad7176_2_device_info = {
434 .name = "ad7176-2",
435 .id = AD7176_ID,
436 .num_voltage_in = 5,
437 .num_channels = 4,
438 .num_configs = 4,
439 .num_gpios = 2,
440 .has_int_ref = true,
441 .clock = 16 * HZ_PER_MHZ,
442 .sinc5_data_rates = ad7175_sinc5_data_rates,
443 .num_sinc5_data_rates = ARRAY_SIZE(ad7175_sinc5_data_rates),
444 };
445
446 static const struct ad7173_device_info ad7177_2_device_info = {
447 .name = "ad7177-2",
448 .id = AD7177_ID,
449 .num_voltage_in = 5,
450 .num_channels = 4,
451 .num_configs = 4,
452 .num_gpios = 2,
453 .has_temp = true,
454 .has_input_buf = true,
455 .has_int_ref = true,
456 .has_pow_supply_monitoring = true,
457 .clock = 16 * HZ_PER_MHZ,
458 .odr_start_value = AD7177_ODR_START_VALUE,
459 .sinc5_data_rates = ad7175_sinc5_data_rates,
460 .num_sinc5_data_rates = ARRAY_SIZE(ad7175_sinc5_data_rates),
461 };
462
463 static const char *const ad7173_ref_sel_str[] = {
464 [AD7173_SETUP_REF_SEL_EXT_REF] = "vref",
465 [AD7173_SETUP_REF_SEL_EXT_REF2] = "vref2",
466 [AD7173_SETUP_REF_SEL_INT_REF] = "refout-avss",
467 [AD7173_SETUP_REF_SEL_AVDD1_AVSS] = "avdd",
468 };
469
470 static const char *const ad7173_clk_sel[] = {
471 "ext-clk", "xtal"
472 };
473
474 #if IS_ENABLED(CONFIG_GPIOLIB)
475
476 static const struct regmap_range ad7173_range_gpio[] = {
477 regmap_reg_range(AD7173_REG_GPIO, AD7173_REG_GPIO),
478 };
479
480 static const struct regmap_access_table ad7173_access_table = {
481 .yes_ranges = ad7173_range_gpio,
482 .n_yes_ranges = ARRAY_SIZE(ad7173_range_gpio),
483 };
484
485 static const struct regmap_config ad7173_regmap_config = {
486 .reg_bits = 8,
487 .val_bits = 16,
488 .rd_table = &ad7173_access_table,
489 .wr_table = &ad7173_access_table,
490 .read_flag_mask = BIT(6),
491 };
492
ad7173_mask_xlate(struct gpio_regmap * gpio,unsigned int base,unsigned int offset,unsigned int * reg,unsigned int * mask)493 static int ad7173_mask_xlate(struct gpio_regmap *gpio, unsigned int base,
494 unsigned int offset, unsigned int *reg,
495 unsigned int *mask)
496 {
497 *mask = AD7173_GPO_DATA(offset);
498 *reg = base;
499 return 0;
500 }
501
ad4111_mask_xlate(struct gpio_regmap * gpio,unsigned int base,unsigned int offset,unsigned int * reg,unsigned int * mask)502 static int ad4111_mask_xlate(struct gpio_regmap *gpio, unsigned int base,
503 unsigned int offset, unsigned int *reg,
504 unsigned int *mask)
505 {
506 *mask = AD4111_GPO01_DATA(offset);
507 *reg = base;
508 return 0;
509 }
510
ad7173_gpio_disable(void * data)511 static void ad7173_gpio_disable(void *data)
512 {
513 struct ad7173_state *st = data;
514 unsigned int mask;
515
516 mask = AD7173_GPIO_OP_EN0 | AD7173_GPIO_OP_EN1 | AD7173_GPIO_OP_EN2_3;
517 regmap_update_bits(st->reg_gpiocon_regmap, AD7173_REG_GPIO, mask, ~mask);
518 }
519
ad7173_gpio_init(struct ad7173_state * st)520 static int ad7173_gpio_init(struct ad7173_state *st)
521 {
522 struct gpio_regmap_config gpio_regmap = {};
523 struct device *dev = &st->sd.spi->dev;
524 unsigned int mask;
525 int ret;
526
527 st->reg_gpiocon_regmap = devm_regmap_init_spi(st->sd.spi, &ad7173_regmap_config);
528 ret = PTR_ERR_OR_ZERO(st->reg_gpiocon_regmap);
529 if (ret)
530 return dev_err_probe(dev, ret, "Unable to init regmap\n");
531
532 mask = AD7173_GPIO_OP_EN0 | AD7173_GPIO_OP_EN1 | AD7173_GPIO_OP_EN2_3;
533 regmap_update_bits(st->reg_gpiocon_regmap, AD7173_REG_GPIO, mask, mask);
534
535 ret = devm_add_action_or_reset(dev, ad7173_gpio_disable, st);
536 if (ret)
537 return ret;
538
539 gpio_regmap.parent = dev;
540 gpio_regmap.regmap = st->reg_gpiocon_regmap;
541 gpio_regmap.ngpio = st->info->num_gpios;
542 gpio_regmap.reg_set_base = AD7173_REG_GPIO;
543 if (st->info->higher_gpio_bits)
544 gpio_regmap.reg_mask_xlate = ad4111_mask_xlate;
545 else
546 gpio_regmap.reg_mask_xlate = ad7173_mask_xlate;
547
548 st->gpio_regmap = devm_gpio_regmap_register(dev, &gpio_regmap);
549 ret = PTR_ERR_OR_ZERO(st->gpio_regmap);
550 if (ret)
551 return dev_err_probe(dev, ret, "Unable to init gpio-regmap\n");
552
553 return 0;
554 }
555 #else
ad7173_gpio_init(struct ad7173_state * st)556 static int ad7173_gpio_init(struct ad7173_state *st)
557 {
558 return 0;
559 }
560 #endif /* CONFIG_GPIOLIB */
561
ad_sigma_delta_to_ad7173(struct ad_sigma_delta * sd)562 static struct ad7173_state *ad_sigma_delta_to_ad7173(struct ad_sigma_delta *sd)
563 {
564 return container_of(sd, struct ad7173_state, sd);
565 }
566
clk_hw_to_ad7173(struct clk_hw * hw)567 static struct ad7173_state *clk_hw_to_ad7173(struct clk_hw *hw)
568 {
569 return container_of(hw, struct ad7173_state, int_clk_hw);
570 }
571
ad7173_ida_destroy(void * data)572 static void ad7173_ida_destroy(void *data)
573 {
574 struct ad7173_state *st = data;
575
576 ida_destroy(&st->cfg_slots_status);
577 }
578
ad7173_reset_usage_cnts(struct ad7173_state * st)579 static void ad7173_reset_usage_cnts(struct ad7173_state *st)
580 {
581 memset64(st->config_cnts, 0, st->info->num_configs);
582 st->config_usage_counter = 0;
583 }
584
585 static struct ad7173_channel_config *
ad7173_find_live_config(struct ad7173_state * st,struct ad7173_channel_config * cfg)586 ad7173_find_live_config(struct ad7173_state *st, struct ad7173_channel_config *cfg)
587 {
588 struct ad7173_channel_config *cfg_aux;
589 int i;
590
591 /*
592 * This is just to make sure that the comparison is adapted after
593 * struct ad7173_channel_config was changed.
594 */
595 static_assert(sizeof_field(struct ad7173_channel_config, config_props) ==
596 sizeof(struct {
597 bool bipolar;
598 bool input_buf;
599 u8 odr;
600 u8 ref_sel;
601 }));
602
603 for (i = 0; i < st->num_channels; i++) {
604 cfg_aux = &st->channels[i].cfg;
605
606 if (cfg_aux->live &&
607 cfg->bipolar == cfg_aux->bipolar &&
608 cfg->input_buf == cfg_aux->input_buf &&
609 cfg->odr == cfg_aux->odr &&
610 cfg->ref_sel == cfg_aux->ref_sel)
611 return cfg_aux;
612 }
613 return NULL;
614 }
615
616 /* Could be replaced with a generic LRU implementation */
ad7173_free_config_slot_lru(struct ad7173_state * st)617 static int ad7173_free_config_slot_lru(struct ad7173_state *st)
618 {
619 int i, lru_position = 0;
620
621 for (i = 1; i < st->info->num_configs; i++)
622 if (st->config_cnts[i] < st->config_cnts[lru_position])
623 lru_position = i;
624
625 for (i = 0; i < st->num_channels; i++)
626 if (st->channels[i].cfg.cfg_slot == lru_position)
627 st->channels[i].cfg.live = false;
628
629 ida_free(&st->cfg_slots_status, lru_position);
630 return ida_alloc(&st->cfg_slots_status, GFP_KERNEL);
631 }
632
633 /* Could be replaced with a generic LRU implementation */
ad7173_load_config(struct ad7173_state * st,struct ad7173_channel_config * cfg)634 static int ad7173_load_config(struct ad7173_state *st,
635 struct ad7173_channel_config *cfg)
636 {
637 unsigned int config;
638 int free_cfg_slot, ret;
639
640 free_cfg_slot = ida_alloc_range(&st->cfg_slots_status, 0,
641 st->info->num_configs - 1, GFP_KERNEL);
642 if (free_cfg_slot < 0)
643 free_cfg_slot = ad7173_free_config_slot_lru(st);
644
645 cfg->cfg_slot = free_cfg_slot;
646 config = FIELD_PREP(AD7173_SETUP_REF_SEL_MASK, cfg->ref_sel);
647
648 if (cfg->bipolar)
649 config |= AD7173_SETUP_BIPOLAR;
650
651 if (cfg->input_buf)
652 config |= AD7173_SETUP_AIN_BUF_MASK;
653
654 ret = ad_sd_write_reg(&st->sd, AD7173_REG_SETUP(free_cfg_slot), 2, config);
655 if (ret)
656 return ret;
657
658 return ad_sd_write_reg(&st->sd, AD7173_REG_FILTER(free_cfg_slot), 2,
659 AD7173_FILTER_ODR0_MASK & cfg->odr);
660 }
661
ad7173_config_channel(struct ad7173_state * st,int addr)662 static int ad7173_config_channel(struct ad7173_state *st, int addr)
663 {
664 struct ad7173_channel_config *cfg = &st->channels[addr].cfg;
665 struct ad7173_channel_config *live_cfg;
666 int ret;
667
668 if (!cfg->live) {
669 live_cfg = ad7173_find_live_config(st, cfg);
670 if (live_cfg) {
671 cfg->cfg_slot = live_cfg->cfg_slot;
672 } else {
673 ret = ad7173_load_config(st, cfg);
674 if (ret)
675 return ret;
676 cfg->live = true;
677 }
678 }
679
680 if (st->config_usage_counter == U64_MAX)
681 ad7173_reset_usage_cnts(st);
682
683 st->config_usage_counter++;
684 st->config_cnts[cfg->cfg_slot] = st->config_usage_counter;
685
686 return 0;
687 }
688
ad7173_set_channel(struct ad_sigma_delta * sd,unsigned int channel)689 static int ad7173_set_channel(struct ad_sigma_delta *sd, unsigned int channel)
690 {
691 struct ad7173_state *st = ad_sigma_delta_to_ad7173(sd);
692 unsigned int val;
693 int ret;
694
695 ret = ad7173_config_channel(st, channel);
696 if (ret)
697 return ret;
698
699 val = AD7173_CH_ENABLE |
700 FIELD_PREP(AD7173_CH_SETUP_SEL_MASK, st->channels[channel].cfg.cfg_slot) |
701 st->channels[channel].ain;
702
703 return ad_sd_write_reg(&st->sd, AD7173_REG_CH(channel), 2, val);
704 }
705
ad7173_set_mode(struct ad_sigma_delta * sd,enum ad_sigma_delta_mode mode)706 static int ad7173_set_mode(struct ad_sigma_delta *sd,
707 enum ad_sigma_delta_mode mode)
708 {
709 struct ad7173_state *st = ad_sigma_delta_to_ad7173(sd);
710
711 st->adc_mode &= ~AD7173_ADC_MODE_MODE_MASK;
712 st->adc_mode |= FIELD_PREP(AD7173_ADC_MODE_MODE_MASK, mode);
713
714 return ad_sd_write_reg(&st->sd, AD7173_REG_ADC_MODE, 2, st->adc_mode);
715 }
716
ad7173_append_status(struct ad_sigma_delta * sd,bool append)717 static int ad7173_append_status(struct ad_sigma_delta *sd, bool append)
718 {
719 struct ad7173_state *st = ad_sigma_delta_to_ad7173(sd);
720 unsigned int interface_mode = st->interface_mode;
721 int ret;
722
723 interface_mode &= ~AD7173_INTERFACE_DATA_STAT;
724 interface_mode |= AD7173_INTERFACE_DATA_STAT_EN(append);
725 ret = ad_sd_write_reg(&st->sd, AD7173_REG_INTERFACE_MODE, 2, interface_mode);
726 if (ret)
727 return ret;
728
729 st->interface_mode = interface_mode;
730
731 return 0;
732 }
733
ad7173_disable_all(struct ad_sigma_delta * sd)734 static int ad7173_disable_all(struct ad_sigma_delta *sd)
735 {
736 struct ad7173_state *st = ad_sigma_delta_to_ad7173(sd);
737 int ret;
738 int i;
739
740 for (i = 0; i < st->num_channels; i++) {
741 ret = ad_sd_write_reg(sd, AD7173_REG_CH(i), 2, 0);
742 if (ret < 0)
743 return ret;
744 }
745
746 return 0;
747 }
748
ad7173_disable_one(struct ad_sigma_delta * sd,unsigned int chan)749 static int ad7173_disable_one(struct ad_sigma_delta *sd, unsigned int chan)
750 {
751 return ad_sd_write_reg(sd, AD7173_REG_CH(chan), 2, 0);
752 }
753
754 static const struct ad_sigma_delta_info ad7173_sigma_delta_info = {
755 .set_channel = ad7173_set_channel,
756 .append_status = ad7173_append_status,
757 .disable_all = ad7173_disable_all,
758 .disable_one = ad7173_disable_one,
759 .set_mode = ad7173_set_mode,
760 .has_registers = true,
761 .addr_shift = 0,
762 .read_mask = BIT(6),
763 .status_ch_mask = GENMASK(3, 0),
764 .data_reg = AD7173_REG_DATA,
765 };
766
ad7173_setup(struct iio_dev * indio_dev)767 static int ad7173_setup(struct iio_dev *indio_dev)
768 {
769 struct ad7173_state *st = iio_priv(indio_dev);
770 struct device *dev = &st->sd.spi->dev;
771 u8 buf[AD7173_RESET_LENGTH];
772 unsigned int id;
773 int ret;
774
775 /* reset the serial interface */
776 memset(buf, 0xff, AD7173_RESET_LENGTH);
777 ret = spi_write_then_read(st->sd.spi, buf, sizeof(buf), NULL, 0);
778 if (ret < 0)
779 return ret;
780
781 /* datasheet recommends a delay of at least 500us after reset */
782 fsleep(500);
783
784 ret = ad_sd_read_reg(&st->sd, AD7173_REG_ID, 2, &id);
785 if (ret)
786 return ret;
787
788 id &= AD7173_ID_MASK;
789 if (id != st->info->id)
790 dev_warn(dev, "Unexpected device id: 0x%04X, expected: 0x%04X\n",
791 id, st->info->id);
792
793 st->adc_mode |= AD7173_ADC_MODE_SING_CYC;
794 st->interface_mode = 0x0;
795
796 st->config_usage_counter = 0;
797 st->config_cnts = devm_kcalloc(dev, st->info->num_configs,
798 sizeof(*st->config_cnts), GFP_KERNEL);
799 if (!st->config_cnts)
800 return -ENOMEM;
801
802 /* All channels are enabled by default after a reset */
803 return ad7173_disable_all(&st->sd);
804 }
805
ad7173_get_ref_voltage_milli(struct ad7173_state * st,u8 reference_select)806 static unsigned int ad7173_get_ref_voltage_milli(struct ad7173_state *st,
807 u8 reference_select)
808 {
809 int vref;
810
811 switch (reference_select) {
812 case AD7173_SETUP_REF_SEL_EXT_REF:
813 vref = regulator_get_voltage(st->regulators[0].consumer);
814 break;
815
816 case AD7173_SETUP_REF_SEL_EXT_REF2:
817 vref = regulator_get_voltage(st->regulators[1].consumer);
818 break;
819
820 case AD7173_SETUP_REF_SEL_INT_REF:
821 vref = AD7173_VOLTAGE_INT_REF_uV;
822 break;
823
824 case AD7173_SETUP_REF_SEL_AVDD1_AVSS:
825 vref = regulator_get_voltage(st->regulators[2].consumer);
826 break;
827
828 default:
829 return -EINVAL;
830 }
831
832 if (vref < 0)
833 return vref;
834
835 return vref / (MICRO / MILLI);
836 }
837
ad7173_read_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int * val,int * val2,long info)838 static int ad7173_read_raw(struct iio_dev *indio_dev,
839 struct iio_chan_spec const *chan,
840 int *val, int *val2, long info)
841 {
842 struct ad7173_state *st = iio_priv(indio_dev);
843 struct ad7173_channel *ch = &st->channels[chan->address];
844 unsigned int reg;
845 u64 temp;
846 int ret;
847
848 switch (info) {
849 case IIO_CHAN_INFO_RAW:
850 ret = ad_sigma_delta_single_conversion(indio_dev, chan, val);
851 if (ret < 0)
852 return ret;
853
854 return IIO_VAL_INT;
855 case IIO_CHAN_INFO_SCALE:
856
857 switch (chan->type) {
858 case IIO_TEMP:
859 temp = AD7173_VOLTAGE_INT_REF_uV * MILLI;
860 temp /= AD7173_TEMP_SENSIIVITY_uV_per_C;
861 *val = temp;
862 *val2 = chan->scan_type.realbits;
863 return IIO_VAL_FRACTIONAL_LOG2;
864 case IIO_VOLTAGE:
865 *val = ad7173_get_ref_voltage_milli(st, ch->cfg.ref_sel);
866 *val2 = chan->scan_type.realbits - !!(ch->cfg.bipolar);
867
868 if (chan->channel < st->info->num_voltage_in_div)
869 *val *= AD4111_DIVIDER_RATIO;
870 return IIO_VAL_FRACTIONAL_LOG2;
871 case IIO_CURRENT:
872 *val = ad7173_get_ref_voltage_milli(st, ch->cfg.ref_sel);
873 *val /= AD4111_SHUNT_RESISTOR_OHM;
874 *val2 = chan->scan_type.realbits - ch->cfg.bipolar;
875 return IIO_VAL_FRACTIONAL_LOG2;
876 default:
877 return -EINVAL;
878 }
879 case IIO_CHAN_INFO_OFFSET:
880
881 switch (chan->type) {
882 case IIO_TEMP:
883 /* 0 Kelvin -> raw sample */
884 temp = -ABSOLUTE_ZERO_MILLICELSIUS;
885 temp *= AD7173_TEMP_SENSIIVITY_uV_per_C;
886 temp <<= chan->scan_type.realbits;
887 temp = DIV_U64_ROUND_CLOSEST(temp,
888 AD7173_VOLTAGE_INT_REF_uV *
889 MILLI);
890 *val = -temp;
891 return IIO_VAL_INT;
892 case IIO_VOLTAGE:
893 case IIO_CURRENT:
894 *val = -BIT(chan->scan_type.realbits - 1);
895 return IIO_VAL_INT;
896 default:
897 return -EINVAL;
898 }
899 case IIO_CHAN_INFO_SAMP_FREQ:
900 reg = st->channels[chan->address].cfg.odr;
901
902 *val = st->info->sinc5_data_rates[reg] / MILLI;
903 *val2 = (st->info->sinc5_data_rates[reg] % MILLI) * (MICRO / MILLI);
904
905 return IIO_VAL_INT_PLUS_MICRO;
906 default:
907 return -EINVAL;
908 }
909 }
910
ad7173_write_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int val,int val2,long info)911 static int ad7173_write_raw(struct iio_dev *indio_dev,
912 struct iio_chan_spec const *chan,
913 int val, int val2, long info)
914 {
915 struct ad7173_state *st = iio_priv(indio_dev);
916 struct ad7173_channel_config *cfg;
917 unsigned int freq, i;
918 int ret;
919
920 ret = iio_device_claim_direct_mode(indio_dev);
921 if (ret)
922 return ret;
923
924 switch (info) {
925 /*
926 * This attribute sets the sampling frequency for each channel individually.
927 * There are no issues for raw or buffered reads of an individual channel.
928 *
929 * When multiple channels are enabled in buffered mode, the effective
930 * sampling rate of a channel is lowered in correlation to the number
931 * of channels enabled and the sampling rate of the other channels.
932 *
933 * Example: 3 channels enabled with rates CH1:6211sps CH2,CH3:10sps
934 * While the reading of CH1 takes only 0.16ms, the reading of CH2 and CH3
935 * will take 100ms each.
936 *
937 * This will cause the reading of CH1 to be actually done once every
938 * 200.16ms, an effective rate of 4.99sps.
939 */
940 case IIO_CHAN_INFO_SAMP_FREQ:
941 freq = val * MILLI + val2 / MILLI;
942 for (i = st->info->odr_start_value; i < st->info->num_sinc5_data_rates - 1; i++)
943 if (freq >= st->info->sinc5_data_rates[i])
944 break;
945
946 cfg = &st->channels[chan->address].cfg;
947 cfg->odr = i;
948 cfg->live = false;
949 break;
950
951 default:
952 ret = -EINVAL;
953 break;
954 }
955
956 iio_device_release_direct_mode(indio_dev);
957 return ret;
958 }
959
ad7173_update_scan_mode(struct iio_dev * indio_dev,const unsigned long * scan_mask)960 static int ad7173_update_scan_mode(struct iio_dev *indio_dev,
961 const unsigned long *scan_mask)
962 {
963 struct ad7173_state *st = iio_priv(indio_dev);
964 int i, ret;
965
966 for (i = 0; i < indio_dev->num_channels; i++) {
967 if (test_bit(i, scan_mask))
968 ret = ad7173_set_channel(&st->sd, i);
969 else
970 ret = ad_sd_write_reg(&st->sd, AD7173_REG_CH(i), 2, 0);
971 if (ret < 0)
972 return ret;
973 }
974
975 return 0;
976 }
977
ad7173_debug_reg_access(struct iio_dev * indio_dev,unsigned int reg,unsigned int writeval,unsigned int * readval)978 static int ad7173_debug_reg_access(struct iio_dev *indio_dev, unsigned int reg,
979 unsigned int writeval, unsigned int *readval)
980 {
981 struct ad7173_state *st = iio_priv(indio_dev);
982 u8 reg_size;
983
984 if (reg == AD7173_REG_COMMS)
985 reg_size = 1;
986 else if (reg == AD7173_REG_CRC || reg == AD7173_REG_DATA ||
987 reg >= AD7173_REG_OFFSET(0))
988 reg_size = 3;
989 else
990 reg_size = 2;
991
992 if (readval)
993 return ad_sd_read_reg(&st->sd, reg, reg_size, readval);
994
995 return ad_sd_write_reg(&st->sd, reg, reg_size, writeval);
996 }
997
998 static const struct iio_info ad7173_info = {
999 .read_raw = &ad7173_read_raw,
1000 .write_raw = &ad7173_write_raw,
1001 .debugfs_reg_access = &ad7173_debug_reg_access,
1002 .validate_trigger = ad_sd_validate_trigger,
1003 .update_scan_mode = ad7173_update_scan_mode,
1004 };
1005
1006 static const struct iio_chan_spec ad7173_channel_template = {
1007 .type = IIO_VOLTAGE,
1008 .indexed = 1,
1009 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
1010 BIT(IIO_CHAN_INFO_SCALE) | BIT(IIO_CHAN_INFO_SAMP_FREQ),
1011 .scan_type = {
1012 .sign = 'u',
1013 .realbits = 24,
1014 .storagebits = 32,
1015 .endianness = IIO_BE,
1016 },
1017 };
1018
1019 static const struct iio_chan_spec ad7173_temp_iio_channel_template = {
1020 .type = IIO_TEMP,
1021 .channel = AD7173_AIN_TEMP_POS,
1022 .channel2 = AD7173_AIN_TEMP_NEG,
1023 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
1024 BIT(IIO_CHAN_INFO_SCALE) | BIT(IIO_CHAN_INFO_OFFSET) |
1025 BIT(IIO_CHAN_INFO_SAMP_FREQ),
1026 .scan_type = {
1027 .sign = 'u',
1028 .realbits = 24,
1029 .storagebits = 32,
1030 .endianness = IIO_BE,
1031 },
1032 };
1033
ad7173_disable_regulators(void * data)1034 static void ad7173_disable_regulators(void *data)
1035 {
1036 struct ad7173_state *st = data;
1037
1038 regulator_bulk_disable(ARRAY_SIZE(st->regulators), st->regulators);
1039 }
1040
ad7173_clk_disable_unprepare(void * clk)1041 static void ad7173_clk_disable_unprepare(void *clk)
1042 {
1043 clk_disable_unprepare(clk);
1044 }
1045
ad7173_sel_clk(struct ad7173_state * st,unsigned int clk_sel)1046 static unsigned long ad7173_sel_clk(struct ad7173_state *st,
1047 unsigned int clk_sel)
1048 {
1049 int ret;
1050
1051 st->adc_mode &= ~AD7173_ADC_MODE_CLOCKSEL_MASK;
1052 st->adc_mode |= FIELD_PREP(AD7173_ADC_MODE_CLOCKSEL_MASK, clk_sel);
1053 ret = ad_sd_write_reg(&st->sd, AD7173_REG_ADC_MODE, 0x2, st->adc_mode);
1054
1055 return ret;
1056 }
1057
ad7173_clk_recalc_rate(struct clk_hw * hw,unsigned long parent_rate)1058 static unsigned long ad7173_clk_recalc_rate(struct clk_hw *hw,
1059 unsigned long parent_rate)
1060 {
1061 struct ad7173_state *st = clk_hw_to_ad7173(hw);
1062
1063 return st->info->clock / HZ_PER_KHZ;
1064 }
1065
ad7173_clk_output_is_enabled(struct clk_hw * hw)1066 static int ad7173_clk_output_is_enabled(struct clk_hw *hw)
1067 {
1068 struct ad7173_state *st = clk_hw_to_ad7173(hw);
1069 u32 clk_sel;
1070
1071 clk_sel = FIELD_GET(AD7173_ADC_MODE_CLOCKSEL_MASK, st->adc_mode);
1072 return clk_sel == AD7173_ADC_MODE_CLOCKSEL_INT_OUTPUT;
1073 }
1074
ad7173_clk_output_prepare(struct clk_hw * hw)1075 static int ad7173_clk_output_prepare(struct clk_hw *hw)
1076 {
1077 struct ad7173_state *st = clk_hw_to_ad7173(hw);
1078
1079 return ad7173_sel_clk(st, AD7173_ADC_MODE_CLOCKSEL_INT_OUTPUT);
1080 }
1081
ad7173_clk_output_unprepare(struct clk_hw * hw)1082 static void ad7173_clk_output_unprepare(struct clk_hw *hw)
1083 {
1084 struct ad7173_state *st = clk_hw_to_ad7173(hw);
1085
1086 ad7173_sel_clk(st, AD7173_ADC_MODE_CLOCKSEL_INT);
1087 }
1088
1089 static const struct clk_ops ad7173_int_clk_ops = {
1090 .recalc_rate = ad7173_clk_recalc_rate,
1091 .is_enabled = ad7173_clk_output_is_enabled,
1092 .prepare = ad7173_clk_output_prepare,
1093 .unprepare = ad7173_clk_output_unprepare,
1094 };
1095
ad7173_register_clk_provider(struct iio_dev * indio_dev)1096 static int ad7173_register_clk_provider(struct iio_dev *indio_dev)
1097 {
1098 struct ad7173_state *st = iio_priv(indio_dev);
1099 struct device *dev = indio_dev->dev.parent;
1100 struct fwnode_handle *fwnode = dev_fwnode(dev);
1101 struct clk_init_data init = {};
1102 int ret;
1103
1104 if (!IS_ENABLED(CONFIG_COMMON_CLK))
1105 return 0;
1106
1107 init.name = fwnode_get_name(fwnode);
1108 init.ops = &ad7173_int_clk_ops;
1109
1110 st->int_clk_hw.init = &init;
1111 ret = devm_clk_hw_register(dev, &st->int_clk_hw);
1112 if (ret)
1113 return ret;
1114
1115 return devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get,
1116 &st->int_clk_hw);
1117 }
1118
ad4111_validate_current_ain(struct ad7173_state * st,const unsigned int ain[AD7173_NO_AINS_PER_CHANNEL])1119 static int ad4111_validate_current_ain(struct ad7173_state *st,
1120 const unsigned int ain[AD7173_NO_AINS_PER_CHANNEL])
1121 {
1122 struct device *dev = &st->sd.spi->dev;
1123
1124 if (!st->info->has_current_inputs)
1125 return dev_err_probe(dev, -EINVAL,
1126 "Model %s does not support current channels\n",
1127 st->info->name);
1128
1129 if (ain[0] >= ARRAY_SIZE(ad4111_current_channel_config))
1130 return dev_err_probe(dev, -EINVAL,
1131 "For current channels single-channel must be <[0-3]>\n");
1132
1133 return 0;
1134 }
1135
ad7173_validate_voltage_ain_inputs(struct ad7173_state * st,unsigned int ain0,unsigned int ain1)1136 static int ad7173_validate_voltage_ain_inputs(struct ad7173_state *st,
1137 unsigned int ain0, unsigned int ain1)
1138 {
1139 struct device *dev = &st->sd.spi->dev;
1140 bool special_input0, special_input1;
1141
1142 /* (AVDD1-AVSS)/5 power supply monitoring */
1143 if (ain0 == AD7173_AIN_POW_MON_POS && ain1 == AD7173_AIN_POW_MON_NEG &&
1144 st->info->has_pow_supply_monitoring)
1145 return 0;
1146
1147 special_input0 = AD7173_IS_REF_INPUT(ain0) ||
1148 (ain0 == AD4111_VINCOM_INPUT && st->info->has_vincom_input);
1149 special_input1 = AD7173_IS_REF_INPUT(ain1) ||
1150 (ain1 == AD4111_VINCOM_INPUT && st->info->has_vincom_input);
1151
1152 if ((ain0 >= st->info->num_voltage_in && !special_input0) ||
1153 (ain1 >= st->info->num_voltage_in && !special_input1)) {
1154 if (ain0 == AD4111_VINCOM_INPUT || ain1 == AD4111_VINCOM_INPUT)
1155 return dev_err_probe(dev, -EINVAL,
1156 "VINCOM not supported for %s\n", st->info->name);
1157
1158 return dev_err_probe(dev, -EINVAL,
1159 "Input pin number out of range for pair (%d %d).\n",
1160 ain0, ain1);
1161 }
1162
1163 if (AD4111_IS_VINCOM_MISMATCH(ain0, ain1) ||
1164 AD4111_IS_VINCOM_MISMATCH(ain1, ain0))
1165 return dev_err_probe(dev, -EINVAL,
1166 "VINCOM must be paired with inputs having divider.\n");
1167
1168 if (!special_input0 && !special_input1 &&
1169 ((ain0 >= st->info->num_voltage_in_div) !=
1170 (ain1 >= st->info->num_voltage_in_div)))
1171 return dev_err_probe(dev, -EINVAL,
1172 "Both inputs must either have a voltage divider or not have: (%d %d).\n",
1173 ain0, ain1);
1174
1175 return 0;
1176 }
1177
ad7173_validate_reference(struct ad7173_state * st,int ref_sel)1178 static int ad7173_validate_reference(struct ad7173_state *st, int ref_sel)
1179 {
1180 struct device *dev = &st->sd.spi->dev;
1181 int ret;
1182
1183 if (ref_sel == AD7173_SETUP_REF_SEL_INT_REF && !st->info->has_int_ref)
1184 return dev_err_probe(dev, -EINVAL,
1185 "Internal reference is not available on current model.\n");
1186
1187 if (ref_sel == AD7173_SETUP_REF_SEL_EXT_REF2 && !st->info->has_ref2)
1188 return dev_err_probe(dev, -EINVAL,
1189 "External reference 2 is not available on current model.\n");
1190
1191 ret = ad7173_get_ref_voltage_milli(st, ref_sel);
1192 if (ret < 0)
1193 return dev_err_probe(dev, ret, "Cannot use reference %u\n",
1194 ref_sel);
1195
1196 return 0;
1197 }
1198
ad7173_fw_parse_channel_config(struct iio_dev * indio_dev)1199 static int ad7173_fw_parse_channel_config(struct iio_dev *indio_dev)
1200 {
1201 struct ad7173_channel *chans_st_arr, *chan_st_priv;
1202 struct ad7173_state *st = iio_priv(indio_dev);
1203 struct device *dev = indio_dev->dev.parent;
1204 struct iio_chan_spec *chan_arr, *chan;
1205 unsigned int ain[AD7173_NO_AINS_PER_CHANNEL], chan_index = 0;
1206 int ref_sel, ret, num_channels;
1207
1208 num_channels = device_get_child_node_count(dev);
1209
1210 if (st->info->has_temp)
1211 num_channels++;
1212
1213 if (num_channels == 0)
1214 return dev_err_probe(dev, -ENODATA, "No channels specified\n");
1215
1216 if (num_channels > st->info->num_channels)
1217 return dev_err_probe(dev, -EINVAL,
1218 "Too many channels specified. Maximum is %d, not including temperature channel if supported.\n",
1219 st->info->num_channels);
1220
1221 indio_dev->num_channels = num_channels;
1222 st->num_channels = num_channels;
1223
1224 chan_arr = devm_kcalloc(dev, sizeof(*indio_dev->channels),
1225 st->num_channels, GFP_KERNEL);
1226 if (!chan_arr)
1227 return -ENOMEM;
1228
1229 chans_st_arr = devm_kcalloc(dev, st->num_channels, sizeof(*st->channels),
1230 GFP_KERNEL);
1231 if (!chans_st_arr)
1232 return -ENOMEM;
1233
1234 indio_dev->channels = chan_arr;
1235 st->channels = chans_st_arr;
1236
1237 if (st->info->has_temp) {
1238 chan_arr[chan_index] = ad7173_temp_iio_channel_template;
1239 chan_st_priv = &chans_st_arr[chan_index];
1240 chan_st_priv->ain =
1241 AD7173_CH_ADDRESS(chan_arr[chan_index].channel,
1242 chan_arr[chan_index].channel2);
1243 chan_st_priv->cfg.bipolar = false;
1244 chan_st_priv->cfg.input_buf = st->info->has_input_buf;
1245 chan_st_priv->cfg.ref_sel = AD7173_SETUP_REF_SEL_INT_REF;
1246 chan_st_priv->cfg.odr = st->info->odr_start_value;
1247 st->adc_mode |= AD7173_ADC_MODE_REF_EN;
1248
1249 chan_index++;
1250 }
1251
1252 device_for_each_child_node_scoped(dev, child) {
1253 bool is_current_chan = false;
1254
1255 chan = &chan_arr[chan_index];
1256 *chan = ad7173_channel_template;
1257 chan_st_priv = &chans_st_arr[chan_index];
1258 ret = fwnode_property_read_u32_array(child, "diff-channels",
1259 ain, ARRAY_SIZE(ain));
1260 if (ret) {
1261 ret = fwnode_property_read_u32(child, "single-channel",
1262 ain);
1263 if (ret)
1264 return dev_err_probe(dev, ret,
1265 "Channel must define one of diff-channels or single-channel.\n");
1266
1267 is_current_chan = fwnode_property_read_bool(child, "adi,current-channel");
1268 } else {
1269 chan->differential = true;
1270 }
1271
1272 if (is_current_chan) {
1273 ret = ad4111_validate_current_ain(st, ain);
1274 if (ret)
1275 return ret;
1276 } else {
1277 if (!chan->differential) {
1278 ret = fwnode_property_read_u32(child,
1279 "common-mode-channel", ain + 1);
1280 if (ret)
1281 return dev_err_probe(dev, ret,
1282 "common-mode-channel must be defined for single-ended channels.\n");
1283 }
1284 ret = ad7173_validate_voltage_ain_inputs(st, ain[0], ain[1]);
1285 if (ret)
1286 return ret;
1287 }
1288
1289 ret = fwnode_property_match_property_string(child,
1290 "adi,reference-select",
1291 ad7173_ref_sel_str,
1292 ARRAY_SIZE(ad7173_ref_sel_str));
1293 if (ret < 0)
1294 ref_sel = AD7173_SETUP_REF_SEL_INT_REF;
1295 else
1296 ref_sel = ret;
1297
1298 ret = ad7173_validate_reference(st, ref_sel);
1299 if (ret)
1300 return ret;
1301
1302 if (ref_sel == AD7173_SETUP_REF_SEL_INT_REF)
1303 st->adc_mode |= AD7173_ADC_MODE_REF_EN;
1304 chan_st_priv->cfg.ref_sel = ref_sel;
1305
1306 chan->address = chan_index;
1307 chan->scan_index = chan_index;
1308 chan->channel = ain[0];
1309 chan_st_priv->chan_reg = chan_index;
1310 chan_st_priv->cfg.input_buf = st->info->has_input_buf;
1311 chan_st_priv->cfg.odr = st->info->odr_start_value;
1312
1313 chan_st_priv->cfg.bipolar = fwnode_property_read_bool(child, "bipolar");
1314 if (chan_st_priv->cfg.bipolar)
1315 chan->info_mask_separate |= BIT(IIO_CHAN_INFO_OFFSET);
1316
1317 if (is_current_chan) {
1318 chan->type = IIO_CURRENT;
1319 chan->differential = false;
1320 chan->channel2 = 0;
1321 chan_st_priv->ain = ad4111_current_channel_config[ain[0]];
1322 } else {
1323 chan_st_priv->cfg.input_buf = st->info->has_input_buf;
1324 chan->channel2 = ain[1];
1325 chan_st_priv->ain = AD7173_CH_ADDRESS(ain[0], ain[1]);
1326 }
1327
1328 chan_index++;
1329 }
1330 return 0;
1331 }
1332
ad7173_fw_parse_device_config(struct iio_dev * indio_dev)1333 static int ad7173_fw_parse_device_config(struct iio_dev *indio_dev)
1334 {
1335 struct ad7173_state *st = iio_priv(indio_dev);
1336 struct device *dev = indio_dev->dev.parent;
1337 int ret;
1338
1339 st->regulators[0].supply = ad7173_ref_sel_str[AD7173_SETUP_REF_SEL_EXT_REF];
1340 st->regulators[1].supply = ad7173_ref_sel_str[AD7173_SETUP_REF_SEL_EXT_REF2];
1341 st->regulators[2].supply = ad7173_ref_sel_str[AD7173_SETUP_REF_SEL_AVDD1_AVSS];
1342
1343 /*
1344 * If a regulator is not available, it will be set to a dummy regulator.
1345 * Each channel reference is checked with regulator_get_voltage() before
1346 * setting attributes so if any channel uses a dummy supply the driver
1347 * probe will fail.
1348 */
1349 ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(st->regulators),
1350 st->regulators);
1351 if (ret)
1352 return dev_err_probe(dev, ret, "Failed to get regulators\n");
1353
1354 ret = regulator_bulk_enable(ARRAY_SIZE(st->regulators), st->regulators);
1355 if (ret)
1356 return dev_err_probe(dev, ret, "Failed to enable regulators\n");
1357
1358 ret = devm_add_action_or_reset(dev, ad7173_disable_regulators, st);
1359 if (ret)
1360 return dev_err_probe(dev, ret,
1361 "Failed to add regulators disable action\n");
1362
1363 ret = device_property_match_property_string(dev, "clock-names",
1364 ad7173_clk_sel,
1365 ARRAY_SIZE(ad7173_clk_sel));
1366 if (ret < 0) {
1367 st->adc_mode |= FIELD_PREP(AD7173_ADC_MODE_CLOCKSEL_MASK,
1368 AD7173_ADC_MODE_CLOCKSEL_INT);
1369 ad7173_register_clk_provider(indio_dev);
1370 } else {
1371 st->adc_mode |= FIELD_PREP(AD7173_ADC_MODE_CLOCKSEL_MASK,
1372 AD7173_ADC_MODE_CLOCKSEL_EXT + ret);
1373 st->ext_clk = devm_clk_get(dev, ad7173_clk_sel[ret]);
1374 if (IS_ERR(st->ext_clk))
1375 return dev_err_probe(dev, PTR_ERR(st->ext_clk),
1376 "Failed to get external clock\n");
1377
1378 ret = clk_prepare_enable(st->ext_clk);
1379 if (ret)
1380 return dev_err_probe(dev, ret,
1381 "Failed to enable external clock\n");
1382
1383 ret = devm_add_action_or_reset(dev, ad7173_clk_disable_unprepare,
1384 st->ext_clk);
1385 if (ret)
1386 return ret;
1387 }
1388
1389 ret = fwnode_irq_get_byname(dev_fwnode(dev), "rdy");
1390 if (ret < 0)
1391 return dev_err_probe(dev, ret, "Interrupt 'rdy' is required\n");
1392
1393 st->sigma_delta_info.irq_line = ret;
1394
1395 return ad7173_fw_parse_channel_config(indio_dev);
1396 }
1397
ad7173_probe(struct spi_device * spi)1398 static int ad7173_probe(struct spi_device *spi)
1399 {
1400 struct device *dev = &spi->dev;
1401 struct ad7173_state *st;
1402 struct iio_dev *indio_dev;
1403 int ret;
1404
1405 indio_dev = devm_iio_device_alloc(dev, sizeof(*st));
1406 if (!indio_dev)
1407 return -ENOMEM;
1408
1409 st = iio_priv(indio_dev);
1410 st->info = spi_get_device_match_data(spi);
1411 if (!st->info)
1412 return -ENODEV;
1413
1414 ida_init(&st->cfg_slots_status);
1415 ret = devm_add_action_or_reset(dev, ad7173_ida_destroy, st);
1416 if (ret)
1417 return ret;
1418
1419 indio_dev->name = st->info->name;
1420 indio_dev->modes = INDIO_DIRECT_MODE;
1421 indio_dev->info = &ad7173_info;
1422
1423 spi->mode = SPI_MODE_3;
1424 spi_setup(spi);
1425
1426 st->sigma_delta_info = ad7173_sigma_delta_info;
1427 st->sigma_delta_info.num_slots = st->info->num_configs;
1428 ret = ad_sd_init(&st->sd, indio_dev, spi, &st->sigma_delta_info);
1429 if (ret)
1430 return ret;
1431
1432 ret = ad7173_fw_parse_device_config(indio_dev);
1433 if (ret)
1434 return ret;
1435
1436 ret = devm_ad_sd_setup_buffer_and_trigger(dev, indio_dev);
1437 if (ret)
1438 return ret;
1439
1440 ret = ad7173_setup(indio_dev);
1441 if (ret)
1442 return ret;
1443
1444 ret = devm_iio_device_register(dev, indio_dev);
1445 if (ret)
1446 return ret;
1447
1448 if (IS_ENABLED(CONFIG_GPIOLIB))
1449 return ad7173_gpio_init(st);
1450
1451 return 0;
1452 }
1453
1454 static const struct of_device_id ad7173_of_match[] = {
1455 { .compatible = "adi,ad4111", .data = &ad4111_device_info },
1456 { .compatible = "adi,ad4112", .data = &ad4112_device_info },
1457 { .compatible = "adi,ad4114", .data = &ad4114_device_info },
1458 { .compatible = "adi,ad4115", .data = &ad4115_device_info },
1459 { .compatible = "adi,ad4116", .data = &ad4116_device_info },
1460 { .compatible = "adi,ad7172-2", .data = &ad7172_2_device_info },
1461 { .compatible = "adi,ad7172-4", .data = &ad7172_4_device_info },
1462 { .compatible = "adi,ad7173-8", .data = &ad7173_8_device_info },
1463 { .compatible = "adi,ad7175-2", .data = &ad7175_2_device_info },
1464 { .compatible = "adi,ad7175-8", .data = &ad7175_8_device_info },
1465 { .compatible = "adi,ad7176-2", .data = &ad7176_2_device_info },
1466 { .compatible = "adi,ad7177-2", .data = &ad7177_2_device_info },
1467 { }
1468 };
1469 MODULE_DEVICE_TABLE(of, ad7173_of_match);
1470
1471 static const struct spi_device_id ad7173_id_table[] = {
1472 { "ad4111", (kernel_ulong_t)&ad4111_device_info },
1473 { "ad4112", (kernel_ulong_t)&ad4112_device_info },
1474 { "ad4114", (kernel_ulong_t)&ad4114_device_info },
1475 { "ad4115", (kernel_ulong_t)&ad4115_device_info },
1476 { "ad4116", (kernel_ulong_t)&ad4116_device_info },
1477 { "ad7172-2", (kernel_ulong_t)&ad7172_2_device_info },
1478 { "ad7172-4", (kernel_ulong_t)&ad7172_4_device_info },
1479 { "ad7173-8", (kernel_ulong_t)&ad7173_8_device_info },
1480 { "ad7175-2", (kernel_ulong_t)&ad7175_2_device_info },
1481 { "ad7175-8", (kernel_ulong_t)&ad7175_8_device_info },
1482 { "ad7176-2", (kernel_ulong_t)&ad7176_2_device_info },
1483 { "ad7177-2", (kernel_ulong_t)&ad7177_2_device_info },
1484 { }
1485 };
1486 MODULE_DEVICE_TABLE(spi, ad7173_id_table);
1487
1488 static struct spi_driver ad7173_driver = {
1489 .driver = {
1490 .name = "ad7173",
1491 .of_match_table = ad7173_of_match,
1492 },
1493 .probe = ad7173_probe,
1494 .id_table = ad7173_id_table,
1495 };
1496 module_spi_driver(ad7173_driver);
1497
1498 MODULE_IMPORT_NS(IIO_AD_SIGMA_DELTA);
1499 MODULE_AUTHOR("Lars-Peter Clausen <lars@metafo.de>");
1500 MODULE_AUTHOR("Dumitru Ceclan <dumitru.ceclan@analog.com>");
1501 MODULE_DESCRIPTION("Analog Devices AD7173 and similar ADC driver");
1502 MODULE_LICENSE("GPL");
1503