1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Analog Devices AD7768-1 SPI ADC driver
4 *
5 * Copyright 2017 Analog Devices Inc.
6 */
7 #include <linux/bitfield.h>
8 #include <linux/clk.h>
9 #include <linux/delay.h>
10 #include <linux/device.h>
11 #include <linux/err.h>
12 #include <linux/gpio/consumer.h>
13 #include <linux/kernel.h>
14 #include <linux/module.h>
15 #include <linux/regulator/consumer.h>
16 #include <linux/sysfs.h>
17 #include <linux/spi/spi.h>
18
19 #include <linux/iio/buffer.h>
20 #include <linux/iio/iio.h>
21 #include <linux/iio/sysfs.h>
22 #include <linux/iio/trigger.h>
23 #include <linux/iio/triggered_buffer.h>
24 #include <linux/iio/trigger_consumer.h>
25
26 /* AD7768 registers definition */
27 #define AD7768_REG_CHIP_TYPE 0x3
28 #define AD7768_REG_PROD_ID_L 0x4
29 #define AD7768_REG_PROD_ID_H 0x5
30 #define AD7768_REG_CHIP_GRADE 0x6
31 #define AD7768_REG_SCRATCH_PAD 0x0A
32 #define AD7768_REG_VENDOR_L 0x0C
33 #define AD7768_REG_VENDOR_H 0x0D
34 #define AD7768_REG_INTERFACE_FORMAT 0x14
35 #define AD7768_REG_POWER_CLOCK 0x15
36 #define AD7768_REG_ANALOG 0x16
37 #define AD7768_REG_ANALOG2 0x17
38 #define AD7768_REG_CONVERSION 0x18
39 #define AD7768_REG_DIGITAL_FILTER 0x19
40 #define AD7768_REG_SINC3_DEC_RATE_MSB 0x1A
41 #define AD7768_REG_SINC3_DEC_RATE_LSB 0x1B
42 #define AD7768_REG_DUTY_CYCLE_RATIO 0x1C
43 #define AD7768_REG_SYNC_RESET 0x1D
44 #define AD7768_REG_GPIO_CONTROL 0x1E
45 #define AD7768_REG_GPIO_WRITE 0x1F
46 #define AD7768_REG_GPIO_READ 0x20
47 #define AD7768_REG_OFFSET_HI 0x21
48 #define AD7768_REG_OFFSET_MID 0x22
49 #define AD7768_REG_OFFSET_LO 0x23
50 #define AD7768_REG_GAIN_HI 0x24
51 #define AD7768_REG_GAIN_MID 0x25
52 #define AD7768_REG_GAIN_LO 0x26
53 #define AD7768_REG_SPI_DIAG_ENABLE 0x28
54 #define AD7768_REG_ADC_DIAG_ENABLE 0x29
55 #define AD7768_REG_DIG_DIAG_ENABLE 0x2A
56 #define AD7768_REG_ADC_DATA 0x2C
57 #define AD7768_REG_MASTER_STATUS 0x2D
58 #define AD7768_REG_SPI_DIAG_STATUS 0x2E
59 #define AD7768_REG_ADC_DIAG_STATUS 0x2F
60 #define AD7768_REG_DIG_DIAG_STATUS 0x30
61 #define AD7768_REG_MCLK_COUNTER 0x31
62
63 /* AD7768_REG_POWER_CLOCK */
64 #define AD7768_PWR_MCLK_DIV_MSK GENMASK(5, 4)
65 #define AD7768_PWR_MCLK_DIV(x) FIELD_PREP(AD7768_PWR_MCLK_DIV_MSK, x)
66 #define AD7768_PWR_PWRMODE_MSK GENMASK(1, 0)
67 #define AD7768_PWR_PWRMODE(x) FIELD_PREP(AD7768_PWR_PWRMODE_MSK, x)
68
69 /* AD7768_REG_DIGITAL_FILTER */
70 #define AD7768_DIG_FIL_FIL_MSK GENMASK(6, 4)
71 #define AD7768_DIG_FIL_FIL(x) FIELD_PREP(AD7768_DIG_FIL_FIL_MSK, x)
72 #define AD7768_DIG_FIL_DEC_MSK GENMASK(2, 0)
73 #define AD7768_DIG_FIL_DEC_RATE(x) FIELD_PREP(AD7768_DIG_FIL_DEC_MSK, x)
74
75 /* AD7768_REG_CONVERSION */
76 #define AD7768_CONV_MODE_MSK GENMASK(2, 0)
77 #define AD7768_CONV_MODE(x) FIELD_PREP(AD7768_CONV_MODE_MSK, x)
78
79 #define AD7768_RD_FLAG_MSK(x) (BIT(6) | ((x) & 0x3F))
80 #define AD7768_WR_FLAG_MSK(x) ((x) & 0x3F)
81
82 enum ad7768_conv_mode {
83 AD7768_CONTINUOUS,
84 AD7768_ONE_SHOT,
85 AD7768_SINGLE,
86 AD7768_PERIODIC,
87 AD7768_STANDBY
88 };
89
90 enum ad7768_pwrmode {
91 AD7768_ECO_MODE = 0,
92 AD7768_MED_MODE = 2,
93 AD7768_FAST_MODE = 3
94 };
95
96 enum ad7768_mclk_div {
97 AD7768_MCLK_DIV_16,
98 AD7768_MCLK_DIV_8,
99 AD7768_MCLK_DIV_4,
100 AD7768_MCLK_DIV_2
101 };
102
103 enum ad7768_dec_rate {
104 AD7768_DEC_RATE_32 = 0,
105 AD7768_DEC_RATE_64 = 1,
106 AD7768_DEC_RATE_128 = 2,
107 AD7768_DEC_RATE_256 = 3,
108 AD7768_DEC_RATE_512 = 4,
109 AD7768_DEC_RATE_1024 = 5,
110 AD7768_DEC_RATE_8 = 9,
111 AD7768_DEC_RATE_16 = 10
112 };
113
114 struct ad7768_clk_configuration {
115 enum ad7768_mclk_div mclk_div;
116 enum ad7768_dec_rate dec_rate;
117 unsigned int clk_div;
118 enum ad7768_pwrmode pwrmode;
119 };
120
121 static const struct ad7768_clk_configuration ad7768_clk_config[] = {
122 { AD7768_MCLK_DIV_2, AD7768_DEC_RATE_8, 16, AD7768_FAST_MODE },
123 { AD7768_MCLK_DIV_2, AD7768_DEC_RATE_16, 32, AD7768_FAST_MODE },
124 { AD7768_MCLK_DIV_2, AD7768_DEC_RATE_32, 64, AD7768_FAST_MODE },
125 { AD7768_MCLK_DIV_2, AD7768_DEC_RATE_64, 128, AD7768_FAST_MODE },
126 { AD7768_MCLK_DIV_2, AD7768_DEC_RATE_128, 256, AD7768_FAST_MODE },
127 { AD7768_MCLK_DIV_4, AD7768_DEC_RATE_128, 512, AD7768_MED_MODE },
128 { AD7768_MCLK_DIV_4, AD7768_DEC_RATE_256, 1024, AD7768_MED_MODE },
129 { AD7768_MCLK_DIV_4, AD7768_DEC_RATE_512, 2048, AD7768_MED_MODE },
130 { AD7768_MCLK_DIV_4, AD7768_DEC_RATE_1024, 4096, AD7768_MED_MODE },
131 { AD7768_MCLK_DIV_8, AD7768_DEC_RATE_1024, 8192, AD7768_MED_MODE },
132 { AD7768_MCLK_DIV_16, AD7768_DEC_RATE_1024, 16384, AD7768_ECO_MODE },
133 };
134
135 static const struct iio_chan_spec ad7768_channels[] = {
136 {
137 .type = IIO_VOLTAGE,
138 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW),
139 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE),
140 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ),
141 .indexed = 1,
142 .channel = 0,
143 .scan_index = 0,
144 .scan_type = {
145 .sign = 's',
146 .realbits = 24,
147 .storagebits = 32,
148 .shift = 8,
149 .endianness = IIO_BE,
150 },
151 },
152 };
153
154 struct ad7768_state {
155 struct spi_device *spi;
156 struct regulator *vref;
157 struct mutex lock;
158 struct clk *mclk;
159 unsigned int mclk_freq;
160 unsigned int samp_freq;
161 struct completion completion;
162 struct iio_trigger *trig;
163 struct gpio_desc *gpio_sync_in;
164 const char *labels[ARRAY_SIZE(ad7768_channels)];
165 /*
166 * DMA (thus cache coherency maintenance) may require the
167 * transfer buffers to live in their own cache lines.
168 */
169 union {
170 struct {
171 __be32 chan;
172 aligned_s64 timestamp;
173 } scan;
174 __be32 d32;
175 u8 d8[2];
176 } data __aligned(IIO_DMA_MINALIGN);
177 };
178
ad7768_spi_reg_read(struct ad7768_state * st,unsigned int addr,unsigned int len)179 static int ad7768_spi_reg_read(struct ad7768_state *st, unsigned int addr,
180 unsigned int len)
181 {
182 unsigned int shift;
183 int ret;
184
185 shift = 32 - (8 * len);
186 st->data.d8[0] = AD7768_RD_FLAG_MSK(addr);
187
188 ret = spi_write_then_read(st->spi, st->data.d8, 1,
189 &st->data.d32, len);
190 if (ret < 0)
191 return ret;
192
193 return (be32_to_cpu(st->data.d32) >> shift);
194 }
195
ad7768_spi_reg_write(struct ad7768_state * st,unsigned int addr,unsigned int val)196 static int ad7768_spi_reg_write(struct ad7768_state *st,
197 unsigned int addr,
198 unsigned int val)
199 {
200 st->data.d8[0] = AD7768_WR_FLAG_MSK(addr);
201 st->data.d8[1] = val & 0xFF;
202
203 return spi_write(st->spi, st->data.d8, 2);
204 }
205
ad7768_send_sync_pulse(struct ad7768_state * st)206 static int ad7768_send_sync_pulse(struct ad7768_state *st)
207 {
208 /*
209 * The datasheet specifies a minimum SYNC_IN pulse width of 1.5 × Tmclk,
210 * where Tmclk is the MCLK period. The supported MCLK frequencies range
211 * from 0.6 MHz to 17 MHz, which corresponds to a minimum SYNC_IN pulse
212 * width of approximately 2.5 µs in the worst-case scenario (0.6 MHz).
213 *
214 * Add a delay to ensure the pulse width is always sufficient to
215 * trigger synchronization.
216 */
217 gpiod_set_value_cansleep(st->gpio_sync_in, 1);
218 fsleep(3);
219 gpiod_set_value_cansleep(st->gpio_sync_in, 0);
220
221 return 0;
222 }
223
ad7768_set_mode(struct ad7768_state * st,enum ad7768_conv_mode mode)224 static int ad7768_set_mode(struct ad7768_state *st,
225 enum ad7768_conv_mode mode)
226 {
227 int regval;
228
229 regval = ad7768_spi_reg_read(st, AD7768_REG_CONVERSION, 1);
230 if (regval < 0)
231 return regval;
232
233 regval &= ~AD7768_CONV_MODE_MSK;
234 regval |= AD7768_CONV_MODE(mode);
235
236 return ad7768_spi_reg_write(st, AD7768_REG_CONVERSION, regval);
237 }
238
ad7768_scan_direct(struct iio_dev * indio_dev)239 static int ad7768_scan_direct(struct iio_dev *indio_dev)
240 {
241 struct ad7768_state *st = iio_priv(indio_dev);
242 int readval, ret;
243
244 reinit_completion(&st->completion);
245
246 ret = ad7768_set_mode(st, AD7768_ONE_SHOT);
247 if (ret < 0)
248 return ret;
249
250 ret = wait_for_completion_timeout(&st->completion,
251 msecs_to_jiffies(1000));
252 if (!ret)
253 return -ETIMEDOUT;
254
255 readval = ad7768_spi_reg_read(st, AD7768_REG_ADC_DATA, 3);
256 if (readval < 0)
257 return readval;
258 /*
259 * Any SPI configuration of the AD7768-1 can only be
260 * performed in continuous conversion mode.
261 */
262 ret = ad7768_set_mode(st, AD7768_CONTINUOUS);
263 if (ret < 0)
264 return ret;
265
266 return readval;
267 }
268
ad7768_reg_access(struct iio_dev * indio_dev,unsigned int reg,unsigned int writeval,unsigned int * readval)269 static int ad7768_reg_access(struct iio_dev *indio_dev,
270 unsigned int reg,
271 unsigned int writeval,
272 unsigned int *readval)
273 {
274 struct ad7768_state *st = iio_priv(indio_dev);
275 int ret;
276
277 mutex_lock(&st->lock);
278 if (readval) {
279 ret = ad7768_spi_reg_read(st, reg, 1);
280 if (ret < 0)
281 goto err_unlock;
282 *readval = ret;
283 ret = 0;
284 } else {
285 ret = ad7768_spi_reg_write(st, reg, writeval);
286 }
287 err_unlock:
288 mutex_unlock(&st->lock);
289
290 return ret;
291 }
292
ad7768_set_dig_fil(struct ad7768_state * st,enum ad7768_dec_rate dec_rate)293 static int ad7768_set_dig_fil(struct ad7768_state *st,
294 enum ad7768_dec_rate dec_rate)
295 {
296 unsigned int mode;
297 int ret;
298
299 if (dec_rate == AD7768_DEC_RATE_8 || dec_rate == AD7768_DEC_RATE_16)
300 mode = AD7768_DIG_FIL_FIL(dec_rate);
301 else
302 mode = AD7768_DIG_FIL_DEC_RATE(dec_rate);
303
304 ret = ad7768_spi_reg_write(st, AD7768_REG_DIGITAL_FILTER, mode);
305 if (ret < 0)
306 return ret;
307
308 /* A sync-in pulse is required every time the filter dec rate changes */
309 return ad7768_send_sync_pulse(st);
310 }
311
ad7768_set_freq(struct ad7768_state * st,unsigned int freq)312 static int ad7768_set_freq(struct ad7768_state *st,
313 unsigned int freq)
314 {
315 unsigned int diff_new, diff_old, pwr_mode, i, idx;
316 int res, ret;
317
318 diff_old = U32_MAX;
319 idx = 0;
320
321 res = DIV_ROUND_CLOSEST(st->mclk_freq, freq);
322
323 /* Find the closest match for the desired sampling frequency */
324 for (i = 0; i < ARRAY_SIZE(ad7768_clk_config); i++) {
325 diff_new = abs(res - ad7768_clk_config[i].clk_div);
326 if (diff_new < diff_old) {
327 diff_old = diff_new;
328 idx = i;
329 }
330 }
331
332 /*
333 * Set both the mclk_div and pwrmode with a single write to the
334 * POWER_CLOCK register
335 */
336 pwr_mode = AD7768_PWR_MCLK_DIV(ad7768_clk_config[idx].mclk_div) |
337 AD7768_PWR_PWRMODE(ad7768_clk_config[idx].pwrmode);
338 ret = ad7768_spi_reg_write(st, AD7768_REG_POWER_CLOCK, pwr_mode);
339 if (ret < 0)
340 return ret;
341
342 ret = ad7768_set_dig_fil(st, ad7768_clk_config[idx].dec_rate);
343 if (ret < 0)
344 return ret;
345
346 st->samp_freq = DIV_ROUND_CLOSEST(st->mclk_freq,
347 ad7768_clk_config[idx].clk_div);
348
349 return 0;
350 }
351
ad7768_sampling_freq_avail(struct device * dev,struct device_attribute * attr,char * buf)352 static ssize_t ad7768_sampling_freq_avail(struct device *dev,
353 struct device_attribute *attr,
354 char *buf)
355 {
356 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
357 struct ad7768_state *st = iio_priv(indio_dev);
358 unsigned int freq;
359 int i, len = 0;
360
361 for (i = 0; i < ARRAY_SIZE(ad7768_clk_config); i++) {
362 freq = DIV_ROUND_CLOSEST(st->mclk_freq,
363 ad7768_clk_config[i].clk_div);
364 len += scnprintf(buf + len, PAGE_SIZE - len, "%d ", freq);
365 }
366
367 buf[len - 1] = '\n';
368
369 return len;
370 }
371
372 static IIO_DEV_ATTR_SAMP_FREQ_AVAIL(ad7768_sampling_freq_avail);
373
ad7768_read_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int * val,int * val2,long info)374 static int ad7768_read_raw(struct iio_dev *indio_dev,
375 struct iio_chan_spec const *chan,
376 int *val, int *val2, long info)
377 {
378 struct ad7768_state *st = iio_priv(indio_dev);
379 int scale_uv, ret;
380
381 switch (info) {
382 case IIO_CHAN_INFO_RAW:
383 ret = iio_device_claim_direct_mode(indio_dev);
384 if (ret)
385 return ret;
386
387 ret = ad7768_scan_direct(indio_dev);
388
389 iio_device_release_direct_mode(indio_dev);
390 if (ret < 0)
391 return ret;
392 *val = sign_extend32(ret, chan->scan_type.realbits - 1);
393
394 return IIO_VAL_INT;
395
396 case IIO_CHAN_INFO_SCALE:
397 scale_uv = regulator_get_voltage(st->vref);
398 if (scale_uv < 0)
399 return scale_uv;
400
401 *val = (scale_uv * 2) / 1000;
402 *val2 = chan->scan_type.realbits;
403
404 return IIO_VAL_FRACTIONAL_LOG2;
405
406 case IIO_CHAN_INFO_SAMP_FREQ:
407 *val = st->samp_freq;
408
409 return IIO_VAL_INT;
410 }
411
412 return -EINVAL;
413 }
414
ad7768_write_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int val,int val2,long info)415 static int ad7768_write_raw(struct iio_dev *indio_dev,
416 struct iio_chan_spec const *chan,
417 int val, int val2, long info)
418 {
419 struct ad7768_state *st = iio_priv(indio_dev);
420
421 switch (info) {
422 case IIO_CHAN_INFO_SAMP_FREQ:
423 return ad7768_set_freq(st, val);
424 default:
425 return -EINVAL;
426 }
427 }
428
ad7768_read_label(struct iio_dev * indio_dev,const struct iio_chan_spec * chan,char * label)429 static int ad7768_read_label(struct iio_dev *indio_dev,
430 const struct iio_chan_spec *chan, char *label)
431 {
432 struct ad7768_state *st = iio_priv(indio_dev);
433
434 return sprintf(label, "%s\n", st->labels[chan->channel]);
435 }
436
437 static struct attribute *ad7768_attributes[] = {
438 &iio_dev_attr_sampling_frequency_available.dev_attr.attr,
439 NULL
440 };
441
442 static const struct attribute_group ad7768_group = {
443 .attrs = ad7768_attributes,
444 };
445
446 static const struct iio_info ad7768_info = {
447 .attrs = &ad7768_group,
448 .read_raw = &ad7768_read_raw,
449 .write_raw = &ad7768_write_raw,
450 .read_label = ad7768_read_label,
451 .debugfs_reg_access = &ad7768_reg_access,
452 };
453
ad7768_setup(struct ad7768_state * st)454 static int ad7768_setup(struct ad7768_state *st)
455 {
456 int ret;
457
458 /*
459 * Two writes to the SPI_RESET[1:0] bits are required to initiate
460 * a software reset. The bits must first be set to 11, and then
461 * to 10. When the sequence is detected, the reset occurs.
462 * See the datasheet, page 70.
463 */
464 ret = ad7768_spi_reg_write(st, AD7768_REG_SYNC_RESET, 0x3);
465 if (ret)
466 return ret;
467
468 ret = ad7768_spi_reg_write(st, AD7768_REG_SYNC_RESET, 0x2);
469 if (ret)
470 return ret;
471
472 st->gpio_sync_in = devm_gpiod_get(&st->spi->dev, "adi,sync-in",
473 GPIOD_OUT_LOW);
474 if (IS_ERR(st->gpio_sync_in))
475 return PTR_ERR(st->gpio_sync_in);
476
477 /* Set the default sampling frequency to 32000 kSPS */
478 return ad7768_set_freq(st, 32000);
479 }
480
ad7768_trigger_handler(int irq,void * p)481 static irqreturn_t ad7768_trigger_handler(int irq, void *p)
482 {
483 struct iio_poll_func *pf = p;
484 struct iio_dev *indio_dev = pf->indio_dev;
485 struct ad7768_state *st = iio_priv(indio_dev);
486 int ret;
487
488 mutex_lock(&st->lock);
489
490 ret = spi_read(st->spi, &st->data.scan.chan, 3);
491 if (ret < 0)
492 goto err_unlock;
493
494 iio_push_to_buffers_with_timestamp(indio_dev, &st->data.scan,
495 iio_get_time_ns(indio_dev));
496
497 err_unlock:
498 iio_trigger_notify_done(indio_dev->trig);
499 mutex_unlock(&st->lock);
500
501 return IRQ_HANDLED;
502 }
503
ad7768_interrupt(int irq,void * dev_id)504 static irqreturn_t ad7768_interrupt(int irq, void *dev_id)
505 {
506 struct iio_dev *indio_dev = dev_id;
507 struct ad7768_state *st = iio_priv(indio_dev);
508
509 if (iio_buffer_enabled(indio_dev))
510 iio_trigger_poll(st->trig);
511 else
512 complete(&st->completion);
513
514 return IRQ_HANDLED;
515 };
516
ad7768_buffer_postenable(struct iio_dev * indio_dev)517 static int ad7768_buffer_postenable(struct iio_dev *indio_dev)
518 {
519 struct ad7768_state *st = iio_priv(indio_dev);
520
521 /*
522 * Write a 1 to the LSB of the INTERFACE_FORMAT register to enter
523 * continuous read mode. Subsequent data reads do not require an
524 * initial 8-bit write to query the ADC_DATA register.
525 */
526 return ad7768_spi_reg_write(st, AD7768_REG_INTERFACE_FORMAT, 0x01);
527 }
528
ad7768_buffer_predisable(struct iio_dev * indio_dev)529 static int ad7768_buffer_predisable(struct iio_dev *indio_dev)
530 {
531 struct ad7768_state *st = iio_priv(indio_dev);
532
533 /*
534 * To exit continuous read mode, perform a single read of the ADC_DATA
535 * reg (0x2C), which allows further configuration of the device.
536 */
537 return ad7768_spi_reg_read(st, AD7768_REG_ADC_DATA, 3);
538 }
539
540 static const struct iio_buffer_setup_ops ad7768_buffer_ops = {
541 .postenable = &ad7768_buffer_postenable,
542 .predisable = &ad7768_buffer_predisable,
543 };
544
545 static const struct iio_trigger_ops ad7768_trigger_ops = {
546 .validate_device = iio_trigger_validate_own_device,
547 };
548
ad7768_regulator_disable(void * data)549 static void ad7768_regulator_disable(void *data)
550 {
551 struct ad7768_state *st = data;
552
553 regulator_disable(st->vref);
554 }
555
ad7768_set_channel_label(struct iio_dev * indio_dev,int num_channels)556 static int ad7768_set_channel_label(struct iio_dev *indio_dev,
557 int num_channels)
558 {
559 struct ad7768_state *st = iio_priv(indio_dev);
560 struct device *device = indio_dev->dev.parent;
561 const char *label;
562 int crt_ch = 0;
563
564 device_for_each_child_node_scoped(device, child) {
565 if (fwnode_property_read_u32(child, "reg", &crt_ch))
566 continue;
567
568 if (crt_ch >= num_channels)
569 continue;
570
571 if (fwnode_property_read_string(child, "label", &label))
572 continue;
573
574 st->labels[crt_ch] = label;
575 }
576
577 return 0;
578 }
579
ad7768_probe(struct spi_device * spi)580 static int ad7768_probe(struct spi_device *spi)
581 {
582 struct ad7768_state *st;
583 struct iio_dev *indio_dev;
584 int ret;
585
586 indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));
587 if (!indio_dev)
588 return -ENOMEM;
589
590 st = iio_priv(indio_dev);
591 /*
592 * Datasheet recommends SDI line to be kept high when data is not being
593 * clocked out of the controller and the spi clock is free running,
594 * to prevent accidental reset.
595 * Since many controllers do not support the SPI_MOSI_IDLE_HIGH flag
596 * yet, only request the MOSI idle state to enable if the controller
597 * supports it.
598 */
599 if (spi->controller->mode_bits & SPI_MOSI_IDLE_HIGH) {
600 spi->mode |= SPI_MOSI_IDLE_HIGH;
601 ret = spi_setup(spi);
602 if (ret < 0)
603 return ret;
604 }
605
606 st->spi = spi;
607
608 st->vref = devm_regulator_get(&spi->dev, "vref");
609 if (IS_ERR(st->vref))
610 return PTR_ERR(st->vref);
611
612 ret = regulator_enable(st->vref);
613 if (ret) {
614 dev_err(&spi->dev, "Failed to enable specified vref supply\n");
615 return ret;
616 }
617
618 ret = devm_add_action_or_reset(&spi->dev, ad7768_regulator_disable, st);
619 if (ret)
620 return ret;
621
622 st->mclk = devm_clk_get_enabled(&spi->dev, "mclk");
623 if (IS_ERR(st->mclk))
624 return PTR_ERR(st->mclk);
625
626 st->mclk_freq = clk_get_rate(st->mclk);
627
628 mutex_init(&st->lock);
629
630 indio_dev->channels = ad7768_channels;
631 indio_dev->num_channels = ARRAY_SIZE(ad7768_channels);
632 indio_dev->name = spi_get_device_id(spi)->name;
633 indio_dev->info = &ad7768_info;
634 indio_dev->modes = INDIO_DIRECT_MODE;
635
636 ret = ad7768_setup(st);
637 if (ret < 0) {
638 dev_err(&spi->dev, "AD7768 setup failed\n");
639 return ret;
640 }
641
642 st->trig = devm_iio_trigger_alloc(&spi->dev, "%s-dev%d",
643 indio_dev->name,
644 iio_device_id(indio_dev));
645 if (!st->trig)
646 return -ENOMEM;
647
648 st->trig->ops = &ad7768_trigger_ops;
649 iio_trigger_set_drvdata(st->trig, indio_dev);
650 ret = devm_iio_trigger_register(&spi->dev, st->trig);
651 if (ret)
652 return ret;
653
654 indio_dev->trig = iio_trigger_get(st->trig);
655
656 init_completion(&st->completion);
657
658 ret = ad7768_set_channel_label(indio_dev, ARRAY_SIZE(ad7768_channels));
659 if (ret)
660 return ret;
661
662 ret = devm_request_irq(&spi->dev, spi->irq,
663 &ad7768_interrupt,
664 IRQF_TRIGGER_RISING | IRQF_ONESHOT,
665 indio_dev->name, indio_dev);
666 if (ret)
667 return ret;
668
669 ret = devm_iio_triggered_buffer_setup(&spi->dev, indio_dev,
670 &iio_pollfunc_store_time,
671 &ad7768_trigger_handler,
672 &ad7768_buffer_ops);
673 if (ret)
674 return ret;
675
676 return devm_iio_device_register(&spi->dev, indio_dev);
677 }
678
679 static const struct spi_device_id ad7768_id_table[] = {
680 { "ad7768-1", 0 },
681 {}
682 };
683 MODULE_DEVICE_TABLE(spi, ad7768_id_table);
684
685 static const struct of_device_id ad7768_of_match[] = {
686 { .compatible = "adi,ad7768-1" },
687 { }
688 };
689 MODULE_DEVICE_TABLE(of, ad7768_of_match);
690
691 static struct spi_driver ad7768_driver = {
692 .driver = {
693 .name = "ad7768-1",
694 .of_match_table = ad7768_of_match,
695 },
696 .probe = ad7768_probe,
697 .id_table = ad7768_id_table,
698 };
699 module_spi_driver(ad7768_driver);
700
701 MODULE_AUTHOR("Stefan Popa <stefan.popa@analog.com>");
702 MODULE_DESCRIPTION("Analog Devices AD7768-1 ADC driver");
703 MODULE_LICENSE("GPL v2");
704