1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Analog Devices AD7944/85/86 PulSAR ADC family driver.
4 *
5 * Copyright 2024 Analog Devices, Inc.
6 * Copyright 2024 BayLibre, SAS
7 */
8
9 #include <linux/align.h>
10 #include <linux/bitfield.h>
11 #include <linux/bitops.h>
12 #include <linux/delay.h>
13 #include <linux/device.h>
14 #include <linux/err.h>
15 #include <linux/gpio/consumer.h>
16 #include <linux/module.h>
17 #include <linux/property.h>
18 #include <linux/regulator/consumer.h>
19 #include <linux/spi/spi.h>
20 #include <linux/string_helpers.h>
21
22 #include <linux/iio/iio.h>
23 #include <linux/iio/sysfs.h>
24 #include <linux/iio/trigger_consumer.h>
25 #include <linux/iio/triggered_buffer.h>
26
27 #define AD7944_INTERNAL_REF_MV 4096
28
29 struct ad7944_timing_spec {
30 /* Normal mode max conversion time (t_{CONV}). */
31 unsigned int conv_ns;
32 /* TURBO mode max conversion time (t_{CONV}). */
33 unsigned int turbo_conv_ns;
34 };
35
36 enum ad7944_spi_mode {
37 /* datasheet calls this "4-wire mode" */
38 AD7944_SPI_MODE_DEFAULT,
39 /* datasheet calls this "3-wire mode" (not related to SPI_3WIRE!) */
40 AD7944_SPI_MODE_SINGLE,
41 /* datasheet calls this "chain mode" */
42 AD7944_SPI_MODE_CHAIN,
43 };
44
45 /* maps adi,spi-mode property value to enum */
46 static const char * const ad7944_spi_modes[] = {
47 [AD7944_SPI_MODE_DEFAULT] = "",
48 [AD7944_SPI_MODE_SINGLE] = "single",
49 [AD7944_SPI_MODE_CHAIN] = "chain",
50 };
51
52 struct ad7944_adc {
53 struct spi_device *spi;
54 enum ad7944_spi_mode spi_mode;
55 struct spi_transfer xfers[3];
56 struct spi_message msg;
57 void *chain_mode_buf;
58 /* Chip-specific timing specifications. */
59 const struct ad7944_timing_spec *timing_spec;
60 /* GPIO connected to CNV pin. */
61 struct gpio_desc *cnv;
62 /* Optional GPIO to enable turbo mode. */
63 struct gpio_desc *turbo;
64 /* Indicates TURBO is hard-wired to be always enabled. */
65 bool always_turbo;
66 /* Reference voltage (millivolts). */
67 unsigned int ref_mv;
68
69 /*
70 * DMA (thus cache coherency maintenance) requires the
71 * transfer buffers to live in their own cache lines.
72 */
73 struct {
74 union {
75 u16 u16;
76 u32 u32;
77 } raw;
78 u64 timestamp __aligned(8);
79 } sample __aligned(IIO_DMA_MINALIGN);
80 };
81
82 /* quite time before CNV rising edge */
83 #define T_QUIET_NS 20
84
85 static const struct ad7944_timing_spec ad7944_timing_spec = {
86 .conv_ns = 420,
87 .turbo_conv_ns = 320,
88 };
89
90 static const struct ad7944_timing_spec ad7986_timing_spec = {
91 .conv_ns = 500,
92 .turbo_conv_ns = 400,
93 };
94
95 struct ad7944_chip_info {
96 const char *name;
97 const struct ad7944_timing_spec *timing_spec;
98 const struct iio_chan_spec channels[2];
99 };
100
101 /* get number of bytes for SPI xfer */
102 #define AD7944_SPI_BYTES(scan_type) ((scan_type).realbits > 16 ? 4 : 2)
103
104 /*
105 * AD7944_DEFINE_CHIP_INFO - Define a chip info structure for a specific chip
106 * @_name: The name of the chip
107 * @_ts: The timing specification for the chip
108 * @_bits: The number of bits in the conversion result
109 * @_diff: Whether the chip is true differential or not
110 */
111 #define AD7944_DEFINE_CHIP_INFO(_name, _ts, _bits, _diff) \
112 static const struct ad7944_chip_info _name##_chip_info = { \
113 .name = #_name, \
114 .timing_spec = &_ts##_timing_spec, \
115 .channels = { \
116 { \
117 .type = IIO_VOLTAGE, \
118 .indexed = 1, \
119 .differential = _diff, \
120 .channel = 0, \
121 .channel2 = _diff ? 1 : 0, \
122 .scan_index = 0, \
123 .scan_type.sign = _diff ? 's' : 'u', \
124 .scan_type.realbits = _bits, \
125 .scan_type.storagebits = _bits > 16 ? 32 : 16, \
126 .scan_type.endianness = IIO_CPU, \
127 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) \
128 | BIT(IIO_CHAN_INFO_SCALE), \
129 }, \
130 IIO_CHAN_SOFT_TIMESTAMP(1), \
131 }, \
132 }
133
134 /* pseudo-differential with ground sense */
135 AD7944_DEFINE_CHIP_INFO(ad7944, ad7944, 14, 0);
136 AD7944_DEFINE_CHIP_INFO(ad7985, ad7944, 16, 0);
137 /* fully differential */
138 AD7944_DEFINE_CHIP_INFO(ad7986, ad7986, 18, 1);
139
ad7944_3wire_cs_mode_init_msg(struct device * dev,struct ad7944_adc * adc,const struct iio_chan_spec * chan)140 static int ad7944_3wire_cs_mode_init_msg(struct device *dev, struct ad7944_adc *adc,
141 const struct iio_chan_spec *chan)
142 {
143 unsigned int t_conv_ns = adc->always_turbo ? adc->timing_spec->turbo_conv_ns
144 : adc->timing_spec->conv_ns;
145 struct spi_transfer *xfers = adc->xfers;
146
147 /*
148 * NB: can get better performance from some SPI controllers if we use
149 * the same bits_per_word in every transfer.
150 */
151 xfers[0].bits_per_word = chan->scan_type.realbits;
152 /*
153 * CS is tied to CNV and we need a low to high transition to start the
154 * conversion, so place CNV low for t_QUIET to prepare for this.
155 */
156 xfers[0].delay.value = T_QUIET_NS;
157 xfers[0].delay.unit = SPI_DELAY_UNIT_NSECS;
158
159 /*
160 * CS has to be high for full conversion time to avoid triggering the
161 * busy indication.
162 */
163 xfers[1].cs_off = 1;
164 xfers[1].delay.value = t_conv_ns;
165 xfers[1].delay.unit = SPI_DELAY_UNIT_NSECS;
166 xfers[1].bits_per_word = chan->scan_type.realbits;
167
168 /* Then we can read the data during the acquisition phase */
169 xfers[2].rx_buf = &adc->sample.raw;
170 xfers[2].len = AD7944_SPI_BYTES(chan->scan_type);
171 xfers[2].bits_per_word = chan->scan_type.realbits;
172
173 spi_message_init_with_transfers(&adc->msg, xfers, 3);
174
175 return devm_spi_optimize_message(dev, adc->spi, &adc->msg);
176 }
177
ad7944_4wire_mode_init_msg(struct device * dev,struct ad7944_adc * adc,const struct iio_chan_spec * chan)178 static int ad7944_4wire_mode_init_msg(struct device *dev, struct ad7944_adc *adc,
179 const struct iio_chan_spec *chan)
180 {
181 unsigned int t_conv_ns = adc->always_turbo ? adc->timing_spec->turbo_conv_ns
182 : adc->timing_spec->conv_ns;
183 struct spi_transfer *xfers = adc->xfers;
184
185 /*
186 * NB: can get better performance from some SPI controllers if we use
187 * the same bits_per_word in every transfer.
188 */
189 xfers[0].bits_per_word = chan->scan_type.realbits;
190 /*
191 * CS has to be high for full conversion time to avoid triggering the
192 * busy indication.
193 */
194 xfers[0].cs_off = 1;
195 xfers[0].delay.value = t_conv_ns;
196 xfers[0].delay.unit = SPI_DELAY_UNIT_NSECS;
197
198 xfers[1].rx_buf = &adc->sample.raw;
199 xfers[1].len = AD7944_SPI_BYTES(chan->scan_type);
200 xfers[1].bits_per_word = chan->scan_type.realbits;
201
202 spi_message_init_with_transfers(&adc->msg, xfers, 2);
203
204 return devm_spi_optimize_message(dev, adc->spi, &adc->msg);
205 }
206
ad7944_chain_mode_init_msg(struct device * dev,struct ad7944_adc * adc,const struct iio_chan_spec * chan,u32 n_chain_dev)207 static int ad7944_chain_mode_init_msg(struct device *dev, struct ad7944_adc *adc,
208 const struct iio_chan_spec *chan,
209 u32 n_chain_dev)
210 {
211 struct spi_transfer *xfers = adc->xfers;
212
213 /*
214 * NB: SCLK has to be low before we toggle CS to avoid triggering the
215 * busy indication.
216 */
217 if (adc->spi->mode & SPI_CPOL)
218 return dev_err_probe(dev, -EINVAL,
219 "chain mode requires ~SPI_CPOL\n");
220
221 /*
222 * We only support CNV connected to CS in chain mode and we need CNV
223 * to be high during the transfer to trigger the conversion.
224 */
225 if (!(adc->spi->mode & SPI_CS_HIGH))
226 return dev_err_probe(dev, -EINVAL,
227 "chain mode requires SPI_CS_HIGH\n");
228
229 /* CNV has to be high for full conversion time before reading data. */
230 xfers[0].delay.value = adc->timing_spec->conv_ns;
231 xfers[0].delay.unit = SPI_DELAY_UNIT_NSECS;
232
233 xfers[1].rx_buf = adc->chain_mode_buf;
234 xfers[1].len = AD7944_SPI_BYTES(chan->scan_type) * n_chain_dev;
235 xfers[1].bits_per_word = chan->scan_type.realbits;
236
237 spi_message_init_with_transfers(&adc->msg, xfers, 2);
238
239 return devm_spi_optimize_message(dev, adc->spi, &adc->msg);
240 }
241
242 /**
243 * ad7944_convert_and_acquire - Perform a single conversion and acquisition
244 * @adc: The ADC device structure
245 * Return: 0 on success, a negative error code on failure
246 *
247 * Perform a conversion and acquisition of a single sample using the
248 * pre-optimized adc->msg.
249 *
250 * Upon successful return adc->sample.raw will contain the conversion result
251 * (or adc->chain_mode_buf if the device is using chain mode).
252 */
ad7944_convert_and_acquire(struct ad7944_adc * adc)253 static int ad7944_convert_and_acquire(struct ad7944_adc *adc)
254 {
255 int ret;
256
257 /*
258 * In 4-wire mode, the CNV line is held high for the entire conversion
259 * and acquisition process. In other modes adc->cnv is NULL and is
260 * ignored (CS is wired to CNV in those cases).
261 */
262 gpiod_set_value_cansleep(adc->cnv, 1);
263 ret = spi_sync(adc->spi, &adc->msg);
264 gpiod_set_value_cansleep(adc->cnv, 0);
265
266 return ret;
267 }
268
ad7944_single_conversion(struct ad7944_adc * adc,const struct iio_chan_spec * chan,int * val)269 static int ad7944_single_conversion(struct ad7944_adc *adc,
270 const struct iio_chan_spec *chan,
271 int *val)
272 {
273 int ret;
274
275 ret = ad7944_convert_and_acquire(adc);
276 if (ret)
277 return ret;
278
279 if (adc->spi_mode == AD7944_SPI_MODE_CHAIN) {
280 if (chan->scan_type.realbits > 16)
281 *val = ((u32 *)adc->chain_mode_buf)[chan->scan_index];
282 else
283 *val = ((u16 *)adc->chain_mode_buf)[chan->scan_index];
284 } else {
285 if (chan->scan_type.realbits > 16)
286 *val = adc->sample.raw.u32;
287 else
288 *val = adc->sample.raw.u16;
289 }
290
291 if (chan->scan_type.sign == 's')
292 *val = sign_extend32(*val, chan->scan_type.realbits - 1);
293 else
294 *val &= GENMASK(chan->scan_type.realbits - 1, 0);
295
296 return IIO_VAL_INT;
297 }
298
ad7944_read_raw(struct iio_dev * indio_dev,const struct iio_chan_spec * chan,int * val,int * val2,long info)299 static int ad7944_read_raw(struct iio_dev *indio_dev,
300 const struct iio_chan_spec *chan,
301 int *val, int *val2, long info)
302 {
303 struct ad7944_adc *adc = iio_priv(indio_dev);
304 int ret;
305
306 switch (info) {
307 case IIO_CHAN_INFO_RAW:
308 ret = iio_device_claim_direct_mode(indio_dev);
309 if (ret)
310 return ret;
311
312 ret = ad7944_single_conversion(adc, chan, val);
313 iio_device_release_direct_mode(indio_dev);
314 return ret;
315
316 case IIO_CHAN_INFO_SCALE:
317 switch (chan->type) {
318 case IIO_VOLTAGE:
319 *val = adc->ref_mv;
320
321 if (chan->scan_type.sign == 's')
322 *val2 = chan->scan_type.realbits - 1;
323 else
324 *val2 = chan->scan_type.realbits;
325
326 return IIO_VAL_FRACTIONAL_LOG2;
327 default:
328 return -EINVAL;
329 }
330
331 default:
332 return -EINVAL;
333 }
334 }
335
336 static const struct iio_info ad7944_iio_info = {
337 .read_raw = &ad7944_read_raw,
338 };
339
ad7944_trigger_handler(int irq,void * p)340 static irqreturn_t ad7944_trigger_handler(int irq, void *p)
341 {
342 struct iio_poll_func *pf = p;
343 struct iio_dev *indio_dev = pf->indio_dev;
344 struct ad7944_adc *adc = iio_priv(indio_dev);
345 int ret;
346
347 ret = ad7944_convert_and_acquire(adc);
348 if (ret)
349 goto out;
350
351 if (adc->spi_mode == AD7944_SPI_MODE_CHAIN)
352 iio_push_to_buffers_with_timestamp(indio_dev, adc->chain_mode_buf,
353 pf->timestamp);
354 else
355 iio_push_to_buffers_with_timestamp(indio_dev, &adc->sample.raw,
356 pf->timestamp);
357
358 out:
359 iio_trigger_notify_done(indio_dev->trig);
360
361 return IRQ_HANDLED;
362 }
363
364 /**
365 * ad7944_chain_mode_alloc - allocate and initialize channel specs and buffers
366 * for daisy-chained devices
367 * @dev: The device for devm_ functions
368 * @chan_template: The channel template for the devices (array of 2 channels
369 * voltage and timestamp)
370 * @n_chain_dev: The number of devices in the chain
371 * @chain_chan: Pointer to receive the allocated channel specs
372 * @chain_mode_buf: Pointer to receive the allocated rx buffer
373 * @chain_scan_masks: Pointer to receive the allocated scan masks
374 * Return: 0 on success, a negative error code on failure
375 */
ad7944_chain_mode_alloc(struct device * dev,const struct iio_chan_spec * chan_template,u32 n_chain_dev,struct iio_chan_spec ** chain_chan,void ** chain_mode_buf,unsigned long ** chain_scan_masks)376 static int ad7944_chain_mode_alloc(struct device *dev,
377 const struct iio_chan_spec *chan_template,
378 u32 n_chain_dev,
379 struct iio_chan_spec **chain_chan,
380 void **chain_mode_buf,
381 unsigned long **chain_scan_masks)
382 {
383 struct iio_chan_spec *chan;
384 size_t chain_mode_buf_size;
385 unsigned long *scan_masks;
386 void *buf;
387 int i;
388
389 /* 1 channel for each device in chain plus 1 for soft timestamp */
390
391 chan = devm_kcalloc(dev, n_chain_dev + 1, sizeof(*chan), GFP_KERNEL);
392 if (!chan)
393 return -ENOMEM;
394
395 for (i = 0; i < n_chain_dev; i++) {
396 chan[i] = chan_template[0];
397
398 if (chan_template[0].differential) {
399 chan[i].channel = 2 * i;
400 chan[i].channel2 = 2 * i + 1;
401 } else {
402 chan[i].channel = i;
403 }
404
405 chan[i].scan_index = i;
406 }
407
408 /* soft timestamp */
409 chan[i] = chan_template[1];
410 chan[i].scan_index = i;
411
412 *chain_chan = chan;
413
414 /* 1 word for each voltage channel + aligned u64 for timestamp */
415
416 chain_mode_buf_size = ALIGN(n_chain_dev *
417 AD7944_SPI_BYTES(chan[0].scan_type), sizeof(u64)) + sizeof(u64);
418 buf = devm_kzalloc(dev, chain_mode_buf_size, GFP_KERNEL);
419 if (!buf)
420 return -ENOMEM;
421
422 *chain_mode_buf = buf;
423
424 /*
425 * Have to limit n_chain_dev due to current implementation of
426 * available_scan_masks.
427 */
428 if (n_chain_dev > BITS_PER_LONG)
429 return dev_err_probe(dev, -EINVAL,
430 "chain is limited to 32 devices\n");
431
432 scan_masks = devm_kcalloc(dev, 2, sizeof(*scan_masks), GFP_KERNEL);
433 if (!scan_masks)
434 return -ENOMEM;
435
436 /*
437 * Scan mask is needed since we always have to read all devices in the
438 * chain in one SPI transfer.
439 */
440 scan_masks[0] = GENMASK(n_chain_dev - 1, 0);
441
442 *chain_scan_masks = scan_masks;
443
444 return 0;
445 }
446
447 static const char * const ad7944_power_supplies[] = {
448 "avdd", "dvdd", "bvdd", "vio"
449 };
450
ad7944_probe(struct spi_device * spi)451 static int ad7944_probe(struct spi_device *spi)
452 {
453 const struct ad7944_chip_info *chip_info;
454 struct device *dev = &spi->dev;
455 struct iio_dev *indio_dev;
456 struct ad7944_adc *adc;
457 bool have_refin;
458 struct iio_chan_spec *chain_chan;
459 unsigned long *chain_scan_masks;
460 u32 n_chain_dev;
461 int ret, ref_mv;
462
463 indio_dev = devm_iio_device_alloc(dev, sizeof(*adc));
464 if (!indio_dev)
465 return -ENOMEM;
466
467 adc = iio_priv(indio_dev);
468 adc->spi = spi;
469
470 chip_info = spi_get_device_match_data(spi);
471 if (!chip_info)
472 return dev_err_probe(dev, -EINVAL, "no chip info\n");
473
474 adc->timing_spec = chip_info->timing_spec;
475
476 ret = device_property_match_property_string(dev, "adi,spi-mode",
477 ad7944_spi_modes,
478 ARRAY_SIZE(ad7944_spi_modes));
479 /* absence of adi,spi-mode property means default mode */
480 if (ret == -EINVAL)
481 adc->spi_mode = AD7944_SPI_MODE_DEFAULT;
482 else if (ret < 0)
483 return dev_err_probe(dev, ret,
484 "getting adi,spi-mode property failed\n");
485 else
486 adc->spi_mode = ret;
487
488 /*
489 * Some chips use unusual word sizes, so check now instead of waiting
490 * for the first xfer.
491 */
492 if (!spi_is_bpw_supported(spi, chip_info->channels[0].scan_type.realbits))
493 return dev_err_probe(dev, -EINVAL,
494 "SPI host does not support %d bits per word\n",
495 chip_info->channels[0].scan_type.realbits);
496
497 ret = devm_regulator_bulk_get_enable(dev,
498 ARRAY_SIZE(ad7944_power_supplies),
499 ad7944_power_supplies);
500 if (ret)
501 return dev_err_probe(dev, ret,
502 "failed to get and enable supplies\n");
503
504 /*
505 * Sort out what is being used for the reference voltage. Options are:
506 * - internal reference: neither REF or REFIN is connected
507 * - internal reference with external buffer: REF not connected, REFIN
508 * is connected
509 * - external reference: REF is connected, REFIN is not connected
510 */
511
512 ret = devm_regulator_get_enable_read_voltage(dev, "ref");
513 if (ret < 0 && ret != -ENODEV)
514 return dev_err_probe(dev, ret, "failed to get REF voltage\n");
515
516 ref_mv = ret == -ENODEV ? 0 : ret / 1000;
517
518 ret = devm_regulator_get_enable_optional(dev, "refin");
519 if (ret < 0 && ret != -ENODEV)
520 return dev_err_probe(dev, ret, "failed to get REFIN voltage\n");
521
522 have_refin = ret != -ENODEV;
523
524 if (have_refin && ref_mv)
525 return dev_err_probe(dev, -EINVAL,
526 "cannot have both refin and ref supplies\n");
527
528 adc->ref_mv = ref_mv ?: AD7944_INTERNAL_REF_MV;
529
530 adc->cnv = devm_gpiod_get_optional(dev, "cnv", GPIOD_OUT_LOW);
531 if (IS_ERR(adc->cnv))
532 return dev_err_probe(dev, PTR_ERR(adc->cnv),
533 "failed to get CNV GPIO\n");
534
535 if (!adc->cnv && adc->spi_mode == AD7944_SPI_MODE_DEFAULT)
536 return dev_err_probe(&spi->dev, -EINVAL, "CNV GPIO is required\n");
537 if (adc->cnv && adc->spi_mode != AD7944_SPI_MODE_DEFAULT)
538 return dev_err_probe(&spi->dev, -EINVAL,
539 "CNV GPIO in single and chain mode is not currently supported\n");
540
541 adc->turbo = devm_gpiod_get_optional(dev, "turbo", GPIOD_OUT_LOW);
542 if (IS_ERR(adc->turbo))
543 return dev_err_probe(dev, PTR_ERR(adc->turbo),
544 "failed to get TURBO GPIO\n");
545
546 adc->always_turbo = device_property_present(dev, "adi,always-turbo");
547
548 if (adc->turbo && adc->always_turbo)
549 return dev_err_probe(dev, -EINVAL,
550 "cannot have both turbo-gpios and adi,always-turbo\n");
551
552 if (adc->spi_mode == AD7944_SPI_MODE_CHAIN && adc->always_turbo)
553 return dev_err_probe(dev, -EINVAL,
554 "cannot have both chain mode and always turbo\n");
555
556 switch (adc->spi_mode) {
557 case AD7944_SPI_MODE_DEFAULT:
558 ret = ad7944_4wire_mode_init_msg(dev, adc, &chip_info->channels[0]);
559 if (ret)
560 return ret;
561
562 break;
563 case AD7944_SPI_MODE_SINGLE:
564 ret = ad7944_3wire_cs_mode_init_msg(dev, adc, &chip_info->channels[0]);
565 if (ret)
566 return ret;
567
568 break;
569 case AD7944_SPI_MODE_CHAIN:
570 ret = device_property_read_u32(dev, "#daisy-chained-devices",
571 &n_chain_dev);
572 if (ret)
573 return dev_err_probe(dev, ret,
574 "failed to get #daisy-chained-devices\n");
575
576 ret = ad7944_chain_mode_alloc(dev, chip_info->channels,
577 n_chain_dev, &chain_chan,
578 &adc->chain_mode_buf,
579 &chain_scan_masks);
580 if (ret)
581 return ret;
582
583 ret = ad7944_chain_mode_init_msg(dev, adc, &chain_chan[0],
584 n_chain_dev);
585 if (ret)
586 return ret;
587
588 break;
589 }
590
591 indio_dev->name = chip_info->name;
592 indio_dev->modes = INDIO_DIRECT_MODE;
593 indio_dev->info = &ad7944_iio_info;
594
595 if (adc->spi_mode == AD7944_SPI_MODE_CHAIN) {
596 indio_dev->available_scan_masks = chain_scan_masks;
597 indio_dev->channels = chain_chan;
598 indio_dev->num_channels = n_chain_dev + 1;
599 } else {
600 indio_dev->channels = chip_info->channels;
601 indio_dev->num_channels = ARRAY_SIZE(chip_info->channels);
602 }
603
604 ret = devm_iio_triggered_buffer_setup(dev, indio_dev,
605 iio_pollfunc_store_time,
606 ad7944_trigger_handler, NULL);
607 if (ret)
608 return ret;
609
610 return devm_iio_device_register(dev, indio_dev);
611 }
612
613 static const struct of_device_id ad7944_of_match[] = {
614 { .compatible = "adi,ad7944", .data = &ad7944_chip_info },
615 { .compatible = "adi,ad7985", .data = &ad7985_chip_info },
616 { .compatible = "adi,ad7986", .data = &ad7986_chip_info },
617 { }
618 };
619 MODULE_DEVICE_TABLE(of, ad7944_of_match);
620
621 static const struct spi_device_id ad7944_spi_id[] = {
622 { "ad7944", (kernel_ulong_t)&ad7944_chip_info },
623 { "ad7985", (kernel_ulong_t)&ad7985_chip_info },
624 { "ad7986", (kernel_ulong_t)&ad7986_chip_info },
625 { }
626
627 };
628 MODULE_DEVICE_TABLE(spi, ad7944_spi_id);
629
630 static struct spi_driver ad7944_driver = {
631 .driver = {
632 .name = "ad7944",
633 .of_match_table = ad7944_of_match,
634 },
635 .probe = ad7944_probe,
636 .id_table = ad7944_spi_id,
637 };
638 module_spi_driver(ad7944_driver);
639
640 MODULE_AUTHOR("David Lechner <dlechner@baylibre.com>");
641 MODULE_DESCRIPTION("Analog Devices AD7944 PulSAR ADC family driver");
642 MODULE_LICENSE("GPL");
643