1 // SPDX-License-Identifier: GPL-2.0-only
2 /* ADC driver for AXP20X and AXP22X PMICs
3 *
4 * Copyright (c) 2016 Free Electrons NextThing Co.
5 * Quentin Schulz <quentin.schulz@free-electrons.com>
6 */
7
8 #include <linux/unaligned.h>
9 #include <linux/bitfield.h>
10 #include <linux/completion.h>
11 #include <linux/interrupt.h>
12 #include <linux/io.h>
13 #include <linux/module.h>
14 #include <linux/mod_devicetable.h>
15 #include <linux/platform_device.h>
16 #include <linux/pm_runtime.h>
17 #include <linux/property.h>
18 #include <linux/regmap.h>
19 #include <linux/thermal.h>
20
21 #include <linux/iio/iio.h>
22 #include <linux/iio/driver.h>
23 #include <linux/iio/machine.h>
24 #include <linux/mfd/axp20x.h>
25
26 #define AXP192_ADC_EN1_MASK GENMASK(7, 0)
27 #define AXP192_ADC_EN2_MASK (GENMASK(3, 0) | BIT(7))
28
29 #define AXP20X_ADC_EN1_MASK GENMASK(7, 0)
30 #define AXP20X_ADC_EN2_MASK (GENMASK(3, 2) | BIT(7))
31
32 #define AXP22X_ADC_EN1_MASK (GENMASK(7, 5) | BIT(0))
33
34 #define AXP717_ADC_EN1_MASK GENMASK(7, 0)
35
36 #define AXP192_GPIO30_IN_RANGE_GPIO0 BIT(0)
37 #define AXP192_GPIO30_IN_RANGE_GPIO1 BIT(1)
38 #define AXP192_GPIO30_IN_RANGE_GPIO2 BIT(2)
39 #define AXP192_GPIO30_IN_RANGE_GPIO3 BIT(3)
40
41 #define AXP20X_GPIO10_IN_RANGE_GPIO0 BIT(0)
42 #define AXP20X_GPIO10_IN_RANGE_GPIO1 BIT(1)
43
44 #define AXP20X_ADC_RATE_MASK GENMASK(7, 6)
45 #define AXP20X_ADC_RATE_HZ(x) ((ilog2((x) / 25) << 6) & AXP20X_ADC_RATE_MASK)
46
47 #define AXP22X_ADC_RATE_HZ(x) ((ilog2((x) / 100) << 6) & AXP20X_ADC_RATE_MASK)
48
49 #define AXP717_ADC_DATA_TS 0x00
50 #define AXP717_ADC_DATA_TEMP 0x01
51 #define AXP717_ADC_DATA_VMID 0x02
52 #define AXP717_ADC_DATA_BKUP_BATT 0x03
53
54 #define AXP717_ADC_DATA_MASK GENMASK(13, 0)
55
56 #define AXP813_V_I_ADC_RATE_MASK GENMASK(5, 4)
57 #define AXP813_ADC_RATE_MASK (AXP20X_ADC_RATE_MASK | AXP813_V_I_ADC_RATE_MASK)
58 #define AXP813_TS_GPIO0_ADC_RATE_HZ(x) AXP20X_ADC_RATE_HZ(x)
59 #define AXP813_V_I_ADC_RATE_HZ(x) ((ilog2((x) / 100) << 4) & AXP813_V_I_ADC_RATE_MASK)
60 #define AXP813_ADC_RATE_HZ(x) (AXP20X_ADC_RATE_HZ(x) | AXP813_V_I_ADC_RATE_HZ(x))
61
62 #define AXP20X_ADC_CHANNEL(_channel, _name, _type, _reg) \
63 { \
64 .type = _type, \
65 .indexed = 1, \
66 .channel = _channel, \
67 .address = _reg, \
68 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
69 BIT(IIO_CHAN_INFO_SCALE), \
70 .datasheet_name = _name, \
71 }
72
73 #define AXP20X_ADC_CHANNEL_OFFSET(_channel, _name, _type, _reg) \
74 { \
75 .type = _type, \
76 .indexed = 1, \
77 .channel = _channel, \
78 .address = _reg, \
79 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
80 BIT(IIO_CHAN_INFO_SCALE) |\
81 BIT(IIO_CHAN_INFO_OFFSET),\
82 .datasheet_name = _name, \
83 }
84
85 struct axp_data;
86
87 struct axp20x_adc_iio {
88 struct regmap *regmap;
89 const struct axp_data *data;
90 };
91
92 enum axp192_adc_channel_v {
93 AXP192_ACIN_V = 0,
94 AXP192_VBUS_V,
95 AXP192_TS_IN,
96 AXP192_GPIO0_V,
97 AXP192_GPIO1_V,
98 AXP192_GPIO2_V,
99 AXP192_GPIO3_V,
100 AXP192_IPSOUT_V,
101 AXP192_BATT_V,
102 };
103
104 enum axp192_adc_channel_i {
105 AXP192_ACIN_I = 0,
106 AXP192_VBUS_I,
107 AXP192_BATT_CHRG_I,
108 AXP192_BATT_DISCHRG_I,
109 };
110
111 enum axp20x_adc_channel_v {
112 AXP20X_ACIN_V = 0,
113 AXP20X_VBUS_V,
114 AXP20X_TS_IN,
115 AXP20X_GPIO0_V,
116 AXP20X_GPIO1_V,
117 AXP20X_IPSOUT_V,
118 AXP20X_BATT_V,
119 };
120
121 enum axp20x_adc_channel_i {
122 AXP20X_ACIN_I = 0,
123 AXP20X_VBUS_I,
124 AXP20X_BATT_CHRG_I,
125 AXP20X_BATT_DISCHRG_I,
126 };
127
128 enum axp22x_adc_channel_v {
129 AXP22X_TS_IN = 0,
130 AXP22X_BATT_V,
131 };
132
133 enum axp22x_adc_channel_i {
134 AXP22X_BATT_CHRG_I = 1,
135 AXP22X_BATT_DISCHRG_I,
136 };
137
138 enum axp717_adc_channel_v {
139 AXP717_BATT_V = 0,
140 AXP717_TS_IN,
141 AXP717_VBUS_V,
142 AXP717_VSYS_V,
143 AXP717_DIE_TEMP_V,
144 AXP717_VMID_V = 6,
145 AXP717_BKUP_BATT_V,
146 };
147
148 enum axp717_adc_channel_i {
149 AXP717_BATT_CHRG_I = 5,
150 };
151
152 enum axp813_adc_channel_v {
153 AXP813_TS_IN = 0,
154 AXP813_GPIO0_V,
155 AXP813_BATT_V,
156 };
157
158 static struct iio_map axp20x_maps[] = {
159 {
160 .consumer_dev_name = "axp20x-usb-power-supply",
161 .consumer_channel = "vbus_v",
162 .adc_channel_label = "vbus_v",
163 }, {
164 .consumer_dev_name = "axp20x-usb-power-supply",
165 .consumer_channel = "vbus_i",
166 .adc_channel_label = "vbus_i",
167 }, {
168 .consumer_dev_name = "axp20x-ac-power-supply",
169 .consumer_channel = "acin_v",
170 .adc_channel_label = "acin_v",
171 }, {
172 .consumer_dev_name = "axp20x-ac-power-supply",
173 .consumer_channel = "acin_i",
174 .adc_channel_label = "acin_i",
175 }, {
176 .consumer_dev_name = "axp20x-battery-power-supply",
177 .consumer_channel = "batt_v",
178 .adc_channel_label = "batt_v",
179 }, {
180 .consumer_dev_name = "axp20x-battery-power-supply",
181 .consumer_channel = "batt_chrg_i",
182 .adc_channel_label = "batt_chrg_i",
183 }, {
184 .consumer_dev_name = "axp20x-battery-power-supply",
185 .consumer_channel = "batt_dischrg_i",
186 .adc_channel_label = "batt_dischrg_i",
187 }, { /* sentinel */ }
188 };
189
190 static struct iio_map axp22x_maps[] = {
191 {
192 .consumer_dev_name = "axp20x-battery-power-supply",
193 .consumer_channel = "batt_v",
194 .adc_channel_label = "batt_v",
195 }, {
196 .consumer_dev_name = "axp20x-battery-power-supply",
197 .consumer_channel = "batt_chrg_i",
198 .adc_channel_label = "batt_chrg_i",
199 }, {
200 .consumer_dev_name = "axp20x-battery-power-supply",
201 .consumer_channel = "batt_dischrg_i",
202 .adc_channel_label = "batt_dischrg_i",
203 }, { /* sentinel */ }
204 };
205
206 static struct iio_map axp717_maps[] = {
207 {
208 .consumer_dev_name = "axp20x-usb-power-supply",
209 .consumer_channel = "vbus_v",
210 .adc_channel_label = "vbus_v",
211 }, {
212 .consumer_dev_name = "axp20x-battery-power-supply",
213 .consumer_channel = "batt_v",
214 .adc_channel_label = "batt_v",
215 }, {
216 .consumer_dev_name = "axp20x-battery-power-supply",
217 .consumer_channel = "batt_chrg_i",
218 .adc_channel_label = "batt_chrg_i",
219 },
220 { }
221 };
222
223 /*
224 * Channels are mapped by physical system. Their channels share the same index.
225 * i.e. acin_i is in_current0_raw and acin_v is in_voltage0_raw.
226 * The only exception is for the battery. batt_v will be in_voltage6_raw and
227 * charge current in_current6_raw and discharge current will be in_current7_raw.
228 */
229 static const struct iio_chan_spec axp192_adc_channels[] = {
230 AXP20X_ADC_CHANNEL(AXP192_ACIN_V, "acin_v", IIO_VOLTAGE,
231 AXP20X_ACIN_V_ADC_H),
232 AXP20X_ADC_CHANNEL(AXP192_ACIN_I, "acin_i", IIO_CURRENT,
233 AXP20X_ACIN_I_ADC_H),
234 AXP20X_ADC_CHANNEL(AXP192_VBUS_V, "vbus_v", IIO_VOLTAGE,
235 AXP20X_VBUS_V_ADC_H),
236 AXP20X_ADC_CHANNEL(AXP192_VBUS_I, "vbus_i", IIO_CURRENT,
237 AXP20X_VBUS_I_ADC_H),
238 {
239 .type = IIO_TEMP,
240 .address = AXP20X_TEMP_ADC_H,
241 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
242 BIT(IIO_CHAN_INFO_SCALE) |
243 BIT(IIO_CHAN_INFO_OFFSET),
244 .datasheet_name = "pmic_temp",
245 },
246 AXP20X_ADC_CHANNEL_OFFSET(AXP192_GPIO0_V, "gpio0_v", IIO_VOLTAGE,
247 AXP20X_GPIO0_V_ADC_H),
248 AXP20X_ADC_CHANNEL_OFFSET(AXP192_GPIO1_V, "gpio1_v", IIO_VOLTAGE,
249 AXP20X_GPIO1_V_ADC_H),
250 AXP20X_ADC_CHANNEL_OFFSET(AXP192_GPIO2_V, "gpio2_v", IIO_VOLTAGE,
251 AXP192_GPIO2_V_ADC_H),
252 AXP20X_ADC_CHANNEL_OFFSET(AXP192_GPIO3_V, "gpio3_v", IIO_VOLTAGE,
253 AXP192_GPIO3_V_ADC_H),
254 AXP20X_ADC_CHANNEL(AXP192_IPSOUT_V, "ipsout_v", IIO_VOLTAGE,
255 AXP20X_IPSOUT_V_HIGH_H),
256 AXP20X_ADC_CHANNEL(AXP192_BATT_V, "batt_v", IIO_VOLTAGE,
257 AXP20X_BATT_V_H),
258 AXP20X_ADC_CHANNEL(AXP192_BATT_CHRG_I, "batt_chrg_i", IIO_CURRENT,
259 AXP20X_BATT_CHRG_I_H),
260 AXP20X_ADC_CHANNEL(AXP192_BATT_DISCHRG_I, "batt_dischrg_i", IIO_CURRENT,
261 AXP20X_BATT_DISCHRG_I_H),
262 AXP20X_ADC_CHANNEL(AXP192_TS_IN, "ts_v", IIO_VOLTAGE,
263 AXP20X_TS_IN_H),
264 };
265
266 static const struct iio_chan_spec axp20x_adc_channels[] = {
267 AXP20X_ADC_CHANNEL(AXP20X_ACIN_V, "acin_v", IIO_VOLTAGE,
268 AXP20X_ACIN_V_ADC_H),
269 AXP20X_ADC_CHANNEL(AXP20X_ACIN_I, "acin_i", IIO_CURRENT,
270 AXP20X_ACIN_I_ADC_H),
271 AXP20X_ADC_CHANNEL(AXP20X_VBUS_V, "vbus_v", IIO_VOLTAGE,
272 AXP20X_VBUS_V_ADC_H),
273 AXP20X_ADC_CHANNEL(AXP20X_VBUS_I, "vbus_i", IIO_CURRENT,
274 AXP20X_VBUS_I_ADC_H),
275 {
276 .type = IIO_TEMP,
277 .address = AXP20X_TEMP_ADC_H,
278 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
279 BIT(IIO_CHAN_INFO_SCALE) |
280 BIT(IIO_CHAN_INFO_OFFSET),
281 .datasheet_name = "pmic_temp",
282 },
283 AXP20X_ADC_CHANNEL_OFFSET(AXP20X_GPIO0_V, "gpio0_v", IIO_VOLTAGE,
284 AXP20X_GPIO0_V_ADC_H),
285 AXP20X_ADC_CHANNEL_OFFSET(AXP20X_GPIO1_V, "gpio1_v", IIO_VOLTAGE,
286 AXP20X_GPIO1_V_ADC_H),
287 AXP20X_ADC_CHANNEL(AXP20X_IPSOUT_V, "ipsout_v", IIO_VOLTAGE,
288 AXP20X_IPSOUT_V_HIGH_H),
289 AXP20X_ADC_CHANNEL(AXP20X_BATT_V, "batt_v", IIO_VOLTAGE,
290 AXP20X_BATT_V_H),
291 AXP20X_ADC_CHANNEL(AXP20X_BATT_CHRG_I, "batt_chrg_i", IIO_CURRENT,
292 AXP20X_BATT_CHRG_I_H),
293 AXP20X_ADC_CHANNEL(AXP20X_BATT_DISCHRG_I, "batt_dischrg_i", IIO_CURRENT,
294 AXP20X_BATT_DISCHRG_I_H),
295 AXP20X_ADC_CHANNEL(AXP20X_TS_IN, "ts_v", IIO_VOLTAGE,
296 AXP20X_TS_IN_H),
297 };
298
299 static const struct iio_chan_spec axp22x_adc_channels[] = {
300 {
301 .type = IIO_TEMP,
302 .address = AXP22X_PMIC_TEMP_H,
303 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
304 BIT(IIO_CHAN_INFO_SCALE) |
305 BIT(IIO_CHAN_INFO_OFFSET),
306 .datasheet_name = "pmic_temp",
307 },
308 AXP20X_ADC_CHANNEL(AXP22X_BATT_V, "batt_v", IIO_VOLTAGE,
309 AXP20X_BATT_V_H),
310 AXP20X_ADC_CHANNEL(AXP22X_BATT_CHRG_I, "batt_chrg_i", IIO_CURRENT,
311 AXP20X_BATT_CHRG_I_H),
312 AXP20X_ADC_CHANNEL(AXP22X_BATT_DISCHRG_I, "batt_dischrg_i", IIO_CURRENT,
313 AXP20X_BATT_DISCHRG_I_H),
314 AXP20X_ADC_CHANNEL(AXP22X_TS_IN, "ts_v", IIO_VOLTAGE,
315 AXP22X_TS_ADC_H),
316 };
317
318 /*
319 * Scale and offset is unknown for temp, ts, batt_chrg_i, vmid_v, and
320 * bkup_batt_v channels. Leaving scale and offset undefined for now.
321 */
322 static const struct iio_chan_spec axp717_adc_channels[] = {
323 AXP20X_ADC_CHANNEL(AXP717_BATT_V, "batt_v", IIO_VOLTAGE,
324 AXP717_BATT_V_H),
325 AXP20X_ADC_CHANNEL(AXP717_TS_IN, "ts_v", IIO_VOLTAGE,
326 AXP717_ADC_DATA_H),
327 AXP20X_ADC_CHANNEL(AXP717_VBUS_V, "vbus_v", IIO_VOLTAGE,
328 AXP717_VBUS_V_H),
329 AXP20X_ADC_CHANNEL(AXP717_VSYS_V, "vsys_v", IIO_VOLTAGE,
330 AXP717_VSYS_V_H),
331 AXP20X_ADC_CHANNEL(AXP717_DIE_TEMP_V, "pmic_temp", IIO_TEMP,
332 AXP717_ADC_DATA_H),
333 AXP20X_ADC_CHANNEL(AXP717_BATT_CHRG_I, "batt_chrg_i", IIO_CURRENT,
334 AXP717_BATT_CHRG_I_H),
335 AXP20X_ADC_CHANNEL(AXP717_VMID_V, "vmid_v", IIO_VOLTAGE,
336 AXP717_ADC_DATA_H),
337 AXP20X_ADC_CHANNEL(AXP717_BKUP_BATT_V, "bkup_batt_v", IIO_VOLTAGE,
338 AXP717_ADC_DATA_H),
339 };
340
341 static const struct iio_chan_spec axp813_adc_channels[] = {
342 {
343 .type = IIO_TEMP,
344 .address = AXP22X_PMIC_TEMP_H,
345 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
346 BIT(IIO_CHAN_INFO_SCALE) |
347 BIT(IIO_CHAN_INFO_OFFSET),
348 .datasheet_name = "pmic_temp",
349 },
350 AXP20X_ADC_CHANNEL(AXP813_GPIO0_V, "gpio0_v", IIO_VOLTAGE,
351 AXP288_GP_ADC_H),
352 AXP20X_ADC_CHANNEL(AXP813_BATT_V, "batt_v", IIO_VOLTAGE,
353 AXP20X_BATT_V_H),
354 AXP20X_ADC_CHANNEL(AXP22X_BATT_CHRG_I, "batt_chrg_i", IIO_CURRENT,
355 AXP20X_BATT_CHRG_I_H),
356 AXP20X_ADC_CHANNEL(AXP22X_BATT_DISCHRG_I, "batt_dischrg_i", IIO_CURRENT,
357 AXP20X_BATT_DISCHRG_I_H),
358 AXP20X_ADC_CHANNEL(AXP813_TS_IN, "ts_v", IIO_VOLTAGE,
359 AXP288_TS_ADC_H),
360 };
361
axp192_adc_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int * val)362 static int axp192_adc_raw(struct iio_dev *indio_dev,
363 struct iio_chan_spec const *chan, int *val)
364 {
365 struct axp20x_adc_iio *info = iio_priv(indio_dev);
366 int ret, size;
367
368 if (chan->type == IIO_CURRENT &&
369 (chan->channel == AXP192_BATT_CHRG_I ||
370 chan->channel == AXP192_BATT_DISCHRG_I))
371 size = 13;
372 else
373 size = 12;
374
375 ret = axp20x_read_variable_width(info->regmap, chan->address, size);
376 if (ret < 0)
377 return ret;
378
379 *val = ret;
380 return IIO_VAL_INT;
381 }
382
axp20x_adc_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int * val)383 static int axp20x_adc_raw(struct iio_dev *indio_dev,
384 struct iio_chan_spec const *chan, int *val)
385 {
386 struct axp20x_adc_iio *info = iio_priv(indio_dev);
387 int ret, size;
388
389 /*
390 * N.B.: Unlike the Chinese datasheets tell, the charging current is
391 * stored on 12 bits, not 13 bits. Only discharging current is on 13
392 * bits.
393 */
394 if (chan->type == IIO_CURRENT && chan->channel == AXP20X_BATT_DISCHRG_I)
395 size = 13;
396 else
397 size = 12;
398
399 ret = axp20x_read_variable_width(info->regmap, chan->address, size);
400 if (ret < 0)
401 return ret;
402
403 *val = ret;
404 return IIO_VAL_INT;
405 }
406
axp22x_adc_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int * val)407 static int axp22x_adc_raw(struct iio_dev *indio_dev,
408 struct iio_chan_spec const *chan, int *val)
409 {
410 struct axp20x_adc_iio *info = iio_priv(indio_dev);
411 int ret;
412
413 ret = axp20x_read_variable_width(info->regmap, chan->address, 12);
414 if (ret < 0)
415 return ret;
416
417 *val = ret;
418 return IIO_VAL_INT;
419 }
420
axp717_adc_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int * val)421 static int axp717_adc_raw(struct iio_dev *indio_dev,
422 struct iio_chan_spec const *chan, int *val)
423 {
424 struct axp20x_adc_iio *info = iio_priv(indio_dev);
425 u8 bulk_reg[2];
426 int ret;
427
428 /*
429 * A generic "ADC data" channel is used for TS, tdie, vmid,
430 * and vbackup. This channel must both first be enabled and
431 * also selected before it can be read.
432 */
433 switch (chan->channel) {
434 case AXP717_TS_IN:
435 regmap_write(info->regmap, AXP717_ADC_DATA_SEL,
436 AXP717_ADC_DATA_TS);
437 break;
438 case AXP717_DIE_TEMP_V:
439 regmap_write(info->regmap, AXP717_ADC_DATA_SEL,
440 AXP717_ADC_DATA_TEMP);
441 break;
442 case AXP717_VMID_V:
443 regmap_write(info->regmap, AXP717_ADC_DATA_SEL,
444 AXP717_ADC_DATA_VMID);
445 break;
446 case AXP717_BKUP_BATT_V:
447 regmap_write(info->regmap, AXP717_ADC_DATA_SEL,
448 AXP717_ADC_DATA_BKUP_BATT);
449 break;
450 default:
451 break;
452 }
453
454 /*
455 * All channels are 14 bits, with the first 2 bits on the high
456 * register reserved and the remaining bits as the ADC value.
457 */
458 ret = regmap_bulk_read(info->regmap, chan->address, bulk_reg, 2);
459 if (ret < 0)
460 return ret;
461
462 *val = FIELD_GET(AXP717_ADC_DATA_MASK, get_unaligned_be16(bulk_reg));
463 return IIO_VAL_INT;
464 }
465
axp813_adc_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int * val)466 static int axp813_adc_raw(struct iio_dev *indio_dev,
467 struct iio_chan_spec const *chan, int *val)
468 {
469 struct axp20x_adc_iio *info = iio_priv(indio_dev);
470 int ret;
471
472 ret = axp20x_read_variable_width(info->regmap, chan->address, 12);
473 if (ret < 0)
474 return ret;
475
476 *val = ret;
477 return IIO_VAL_INT;
478 }
479
axp192_adc_scale_voltage(int channel,int * val,int * val2)480 static int axp192_adc_scale_voltage(int channel, int *val, int *val2)
481 {
482 switch (channel) {
483 case AXP192_ACIN_V:
484 case AXP192_VBUS_V:
485 *val = 1;
486 *val2 = 700000;
487 return IIO_VAL_INT_PLUS_MICRO;
488
489 case AXP192_GPIO0_V:
490 case AXP192_GPIO1_V:
491 case AXP192_GPIO2_V:
492 case AXP192_GPIO3_V:
493 *val = 0;
494 *val2 = 500000;
495 return IIO_VAL_INT_PLUS_MICRO;
496
497 case AXP192_BATT_V:
498 *val = 1;
499 *val2 = 100000;
500 return IIO_VAL_INT_PLUS_MICRO;
501
502 case AXP192_IPSOUT_V:
503 *val = 1;
504 *val2 = 400000;
505 return IIO_VAL_INT_PLUS_MICRO;
506
507 case AXP192_TS_IN:
508 /* 0.8 mV per LSB */
509 *val = 0;
510 *val2 = 800000;
511 return IIO_VAL_INT_PLUS_MICRO;
512
513 default:
514 return -EINVAL;
515 }
516 }
517
axp20x_adc_scale_voltage(int channel,int * val,int * val2)518 static int axp20x_adc_scale_voltage(int channel, int *val, int *val2)
519 {
520 switch (channel) {
521 case AXP20X_ACIN_V:
522 case AXP20X_VBUS_V:
523 *val = 1;
524 *val2 = 700000;
525 return IIO_VAL_INT_PLUS_MICRO;
526
527 case AXP20X_GPIO0_V:
528 case AXP20X_GPIO1_V:
529 *val = 0;
530 *val2 = 500000;
531 return IIO_VAL_INT_PLUS_MICRO;
532
533 case AXP20X_BATT_V:
534 *val = 1;
535 *val2 = 100000;
536 return IIO_VAL_INT_PLUS_MICRO;
537
538 case AXP20X_IPSOUT_V:
539 *val = 1;
540 *val2 = 400000;
541 return IIO_VAL_INT_PLUS_MICRO;
542
543 case AXP20X_TS_IN:
544 /* 0.8 mV per LSB */
545 *val = 0;
546 *val2 = 800000;
547 return IIO_VAL_INT_PLUS_MICRO;
548
549 default:
550 return -EINVAL;
551 }
552 }
553
axp22x_adc_scale_voltage(int channel,int * val,int * val2)554 static int axp22x_adc_scale_voltage(int channel, int *val, int *val2)
555 {
556 switch (channel) {
557 case AXP22X_BATT_V:
558 /* 1.1 mV per LSB */
559 *val = 1;
560 *val2 = 100000;
561 return IIO_VAL_INT_PLUS_MICRO;
562
563 case AXP22X_TS_IN:
564 /* 0.8 mV per LSB */
565 *val = 0;
566 *val2 = 800000;
567 return IIO_VAL_INT_PLUS_MICRO;
568
569 default:
570 return -EINVAL;
571 }
572 }
axp813_adc_scale_voltage(int channel,int * val,int * val2)573 static int axp813_adc_scale_voltage(int channel, int *val, int *val2)
574 {
575 switch (channel) {
576 case AXP813_GPIO0_V:
577 *val = 0;
578 *val2 = 800000;
579 return IIO_VAL_INT_PLUS_MICRO;
580
581 case AXP813_BATT_V:
582 *val = 1;
583 *val2 = 100000;
584 return IIO_VAL_INT_PLUS_MICRO;
585
586 case AXP813_TS_IN:
587 /* 0.8 mV per LSB */
588 *val = 0;
589 *val2 = 800000;
590 return IIO_VAL_INT_PLUS_MICRO;
591
592 default:
593 return -EINVAL;
594 }
595 }
596
axp20x_adc_scale_current(int channel,int * val,int * val2)597 static int axp20x_adc_scale_current(int channel, int *val, int *val2)
598 {
599 switch (channel) {
600 case AXP20X_ACIN_I:
601 *val = 0;
602 *val2 = 625000;
603 return IIO_VAL_INT_PLUS_MICRO;
604
605 case AXP20X_VBUS_I:
606 *val = 0;
607 *val2 = 375000;
608 return IIO_VAL_INT_PLUS_MICRO;
609
610 case AXP20X_BATT_DISCHRG_I:
611 case AXP20X_BATT_CHRG_I:
612 *val = 0;
613 *val2 = 500000;
614 return IIO_VAL_INT_PLUS_MICRO;
615
616 default:
617 return -EINVAL;
618 }
619 }
620
axp192_adc_scale(struct iio_chan_spec const * chan,int * val,int * val2)621 static int axp192_adc_scale(struct iio_chan_spec const *chan, int *val,
622 int *val2)
623 {
624 switch (chan->type) {
625 case IIO_VOLTAGE:
626 return axp192_adc_scale_voltage(chan->channel, val, val2);
627
628 case IIO_CURRENT:
629 /*
630 * AXP192 current channels are identical to the AXP20x,
631 * therefore we can re-use the scaling function.
632 */
633 return axp20x_adc_scale_current(chan->channel, val, val2);
634
635 case IIO_TEMP:
636 *val = 100;
637 return IIO_VAL_INT;
638
639 default:
640 return -EINVAL;
641 }
642 }
643
axp20x_adc_scale(struct iio_chan_spec const * chan,int * val,int * val2)644 static int axp20x_adc_scale(struct iio_chan_spec const *chan, int *val,
645 int *val2)
646 {
647 switch (chan->type) {
648 case IIO_VOLTAGE:
649 return axp20x_adc_scale_voltage(chan->channel, val, val2);
650
651 case IIO_CURRENT:
652 return axp20x_adc_scale_current(chan->channel, val, val2);
653
654 case IIO_TEMP:
655 *val = 100;
656 return IIO_VAL_INT;
657
658 default:
659 return -EINVAL;
660 }
661 }
662
axp22x_adc_scale(struct iio_chan_spec const * chan,int * val,int * val2)663 static int axp22x_adc_scale(struct iio_chan_spec const *chan, int *val,
664 int *val2)
665 {
666 switch (chan->type) {
667 case IIO_VOLTAGE:
668 return axp22x_adc_scale_voltage(chan->channel, val, val2);
669
670 case IIO_CURRENT:
671 *val = 1;
672 return IIO_VAL_INT;
673
674 case IIO_TEMP:
675 *val = 100;
676 return IIO_VAL_INT;
677
678 default:
679 return -EINVAL;
680 }
681 }
682
axp717_adc_scale(struct iio_chan_spec const * chan,int * val,int * val2)683 static int axp717_adc_scale(struct iio_chan_spec const *chan, int *val,
684 int *val2)
685 {
686 switch (chan->type) {
687 case IIO_VOLTAGE:
688 *val = 1;
689 return IIO_VAL_INT;
690
691 case IIO_CURRENT:
692 *val = 1;
693 return IIO_VAL_INT;
694
695 case IIO_TEMP:
696 *val = 100;
697 return IIO_VAL_INT;
698
699 default:
700 return -EINVAL;
701 }
702 }
703
axp813_adc_scale(struct iio_chan_spec const * chan,int * val,int * val2)704 static int axp813_adc_scale(struct iio_chan_spec const *chan, int *val,
705 int *val2)
706 {
707 switch (chan->type) {
708 case IIO_VOLTAGE:
709 return axp813_adc_scale_voltage(chan->channel, val, val2);
710
711 case IIO_CURRENT:
712 *val = 1;
713 return IIO_VAL_INT;
714
715 case IIO_TEMP:
716 *val = 100;
717 return IIO_VAL_INT;
718
719 default:
720 return -EINVAL;
721 }
722 }
723
axp192_adc_offset_voltage(struct iio_dev * indio_dev,int channel,int * val)724 static int axp192_adc_offset_voltage(struct iio_dev *indio_dev, int channel,
725 int *val)
726 {
727 struct axp20x_adc_iio *info = iio_priv(indio_dev);
728 unsigned int regval;
729 int ret;
730
731 ret = regmap_read(info->regmap, AXP192_GPIO30_IN_RANGE, ®val);
732 if (ret < 0)
733 return ret;
734
735 switch (channel) {
736 case AXP192_GPIO0_V:
737 regval = FIELD_GET(AXP192_GPIO30_IN_RANGE_GPIO0, regval);
738 break;
739
740 case AXP192_GPIO1_V:
741 regval = FIELD_GET(AXP192_GPIO30_IN_RANGE_GPIO1, regval);
742 break;
743
744 case AXP192_GPIO2_V:
745 regval = FIELD_GET(AXP192_GPIO30_IN_RANGE_GPIO2, regval);
746 break;
747
748 case AXP192_GPIO3_V:
749 regval = FIELD_GET(AXP192_GPIO30_IN_RANGE_GPIO3, regval);
750 break;
751
752 default:
753 return -EINVAL;
754 }
755
756 *val = regval ? 700000 : 0;
757 return IIO_VAL_INT;
758 }
759
axp20x_adc_offset_voltage(struct iio_dev * indio_dev,int channel,int * val)760 static int axp20x_adc_offset_voltage(struct iio_dev *indio_dev, int channel,
761 int *val)
762 {
763 struct axp20x_adc_iio *info = iio_priv(indio_dev);
764 unsigned int regval;
765 int ret;
766
767 ret = regmap_read(info->regmap, AXP20X_GPIO10_IN_RANGE, ®val);
768 if (ret < 0)
769 return ret;
770
771 switch (channel) {
772 case AXP20X_GPIO0_V:
773 regval = FIELD_GET(AXP20X_GPIO10_IN_RANGE_GPIO0, regval);
774 break;
775
776 case AXP20X_GPIO1_V:
777 regval = FIELD_GET(AXP20X_GPIO10_IN_RANGE_GPIO1, regval);
778 break;
779
780 default:
781 return -EINVAL;
782 }
783
784 *val = regval ? 700000 : 0;
785 return IIO_VAL_INT;
786 }
787
axp192_adc_offset(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int * val)788 static int axp192_adc_offset(struct iio_dev *indio_dev,
789 struct iio_chan_spec const *chan, int *val)
790 {
791 switch (chan->type) {
792 case IIO_VOLTAGE:
793 return axp192_adc_offset_voltage(indio_dev, chan->channel, val);
794
795 case IIO_TEMP:
796 *val = -1447;
797 return IIO_VAL_INT;
798
799 default:
800 return -EINVAL;
801 }
802 }
803
axp20x_adc_offset(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int * val)804 static int axp20x_adc_offset(struct iio_dev *indio_dev,
805 struct iio_chan_spec const *chan, int *val)
806 {
807 switch (chan->type) {
808 case IIO_VOLTAGE:
809 return axp20x_adc_offset_voltage(indio_dev, chan->channel, val);
810
811 case IIO_TEMP:
812 *val = -1447;
813 return IIO_VAL_INT;
814
815 default:
816 return -EINVAL;
817 }
818 }
819
axp192_read_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int * val,int * val2,long mask)820 static int axp192_read_raw(struct iio_dev *indio_dev,
821 struct iio_chan_spec const *chan, int *val,
822 int *val2, long mask)
823 {
824 switch (mask) {
825 case IIO_CHAN_INFO_OFFSET:
826 return axp192_adc_offset(indio_dev, chan, val);
827
828 case IIO_CHAN_INFO_SCALE:
829 return axp192_adc_scale(chan, val, val2);
830
831 case IIO_CHAN_INFO_RAW:
832 return axp192_adc_raw(indio_dev, chan, val);
833
834 default:
835 return -EINVAL;
836 }
837 }
838
axp20x_read_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int * val,int * val2,long mask)839 static int axp20x_read_raw(struct iio_dev *indio_dev,
840 struct iio_chan_spec const *chan, int *val,
841 int *val2, long mask)
842 {
843 switch (mask) {
844 case IIO_CHAN_INFO_OFFSET:
845 return axp20x_adc_offset(indio_dev, chan, val);
846
847 case IIO_CHAN_INFO_SCALE:
848 return axp20x_adc_scale(chan, val, val2);
849
850 case IIO_CHAN_INFO_RAW:
851 return axp20x_adc_raw(indio_dev, chan, val);
852
853 default:
854 return -EINVAL;
855 }
856 }
857
axp22x_read_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int * val,int * val2,long mask)858 static int axp22x_read_raw(struct iio_dev *indio_dev,
859 struct iio_chan_spec const *chan, int *val,
860 int *val2, long mask)
861 {
862 switch (mask) {
863 case IIO_CHAN_INFO_OFFSET:
864 /* For PMIC temp only */
865 *val = -2677;
866 return IIO_VAL_INT;
867
868 case IIO_CHAN_INFO_SCALE:
869 return axp22x_adc_scale(chan, val, val2);
870
871 case IIO_CHAN_INFO_RAW:
872 return axp22x_adc_raw(indio_dev, chan, val);
873
874 default:
875 return -EINVAL;
876 }
877 }
878
axp717_read_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int * val,int * val2,long mask)879 static int axp717_read_raw(struct iio_dev *indio_dev,
880 struct iio_chan_spec const *chan, int *val,
881 int *val2, long mask)
882 {
883 switch (mask) {
884 case IIO_CHAN_INFO_SCALE:
885 return axp717_adc_scale(chan, val, val2);
886
887 case IIO_CHAN_INFO_RAW:
888 return axp717_adc_raw(indio_dev, chan, val);
889
890 default:
891 return -EINVAL;
892 }
893 }
894
axp813_read_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int * val,int * val2,long mask)895 static int axp813_read_raw(struct iio_dev *indio_dev,
896 struct iio_chan_spec const *chan, int *val,
897 int *val2, long mask)
898 {
899 switch (mask) {
900 case IIO_CHAN_INFO_OFFSET:
901 *val = -2667;
902 return IIO_VAL_INT;
903
904 case IIO_CHAN_INFO_SCALE:
905 return axp813_adc_scale(chan, val, val2);
906
907 case IIO_CHAN_INFO_RAW:
908 return axp813_adc_raw(indio_dev, chan, val);
909
910 default:
911 return -EINVAL;
912 }
913 }
914
axp192_write_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int val,int val2,long mask)915 static int axp192_write_raw(struct iio_dev *indio_dev,
916 struct iio_chan_spec const *chan, int val, int val2,
917 long mask)
918 {
919 struct axp20x_adc_iio *info = iio_priv(indio_dev);
920 unsigned int regmask, regval;
921
922 /*
923 * The AXP192 PMIC allows the user to choose between 0V and 0.7V offsets
924 * for (independently) GPIO0-3 when in ADC mode.
925 */
926 if (mask != IIO_CHAN_INFO_OFFSET)
927 return -EINVAL;
928
929 if (val != 0 && val != 700000)
930 return -EINVAL;
931
932 switch (chan->channel) {
933 case AXP192_GPIO0_V:
934 regmask = AXP192_GPIO30_IN_RANGE_GPIO0;
935 regval = FIELD_PREP(AXP192_GPIO30_IN_RANGE_GPIO0, !!val);
936 break;
937
938 case AXP192_GPIO1_V:
939 regmask = AXP192_GPIO30_IN_RANGE_GPIO1;
940 regval = FIELD_PREP(AXP192_GPIO30_IN_RANGE_GPIO1, !!val);
941 break;
942
943 case AXP192_GPIO2_V:
944 regmask = AXP192_GPIO30_IN_RANGE_GPIO2;
945 regval = FIELD_PREP(AXP192_GPIO30_IN_RANGE_GPIO2, !!val);
946 break;
947
948 case AXP192_GPIO3_V:
949 regmask = AXP192_GPIO30_IN_RANGE_GPIO3;
950 regval = FIELD_PREP(AXP192_GPIO30_IN_RANGE_GPIO3, !!val);
951 break;
952
953 default:
954 return -EINVAL;
955 }
956
957 return regmap_update_bits(info->regmap, AXP192_GPIO30_IN_RANGE, regmask, regval);
958 }
959
axp20x_write_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int val,int val2,long mask)960 static int axp20x_write_raw(struct iio_dev *indio_dev,
961 struct iio_chan_spec const *chan, int val, int val2,
962 long mask)
963 {
964 struct axp20x_adc_iio *info = iio_priv(indio_dev);
965 unsigned int regmask, regval;
966
967 /*
968 * The AXP20X PMIC allows the user to choose between 0V and 0.7V offsets
969 * for (independently) GPIO0 and GPIO1 when in ADC mode.
970 */
971 if (mask != IIO_CHAN_INFO_OFFSET)
972 return -EINVAL;
973
974 if (val != 0 && val != 700000)
975 return -EINVAL;
976
977 switch (chan->channel) {
978 case AXP20X_GPIO0_V:
979 regmask = AXP20X_GPIO10_IN_RANGE_GPIO0;
980 regval = FIELD_PREP(AXP20X_GPIO10_IN_RANGE_GPIO0, !!val);
981 break;
982
983 case AXP20X_GPIO1_V:
984 regmask = AXP20X_GPIO10_IN_RANGE_GPIO1;
985 regval = FIELD_PREP(AXP20X_GPIO10_IN_RANGE_GPIO1, !!val);
986 break;
987
988 default:
989 return -EINVAL;
990 }
991
992 return regmap_update_bits(info->regmap, AXP20X_GPIO10_IN_RANGE, regmask, regval);
993 }
994
995 static const struct iio_info axp192_adc_iio_info = {
996 .read_raw = axp192_read_raw,
997 .write_raw = axp192_write_raw,
998 };
999
1000 static const struct iio_info axp20x_adc_iio_info = {
1001 .read_raw = axp20x_read_raw,
1002 .write_raw = axp20x_write_raw,
1003 };
1004
1005 static const struct iio_info axp22x_adc_iio_info = {
1006 .read_raw = axp22x_read_raw,
1007 };
1008
1009 static const struct iio_info axp717_adc_iio_info = {
1010 .read_raw = axp717_read_raw,
1011 };
1012
1013 static const struct iio_info axp813_adc_iio_info = {
1014 .read_raw = axp813_read_raw,
1015 };
1016
axp20x_adc_rate(struct axp20x_adc_iio * info,int rate)1017 static int axp20x_adc_rate(struct axp20x_adc_iio *info, int rate)
1018 {
1019 return regmap_update_bits(info->regmap, AXP20X_ADC_RATE,
1020 AXP20X_ADC_RATE_MASK,
1021 AXP20X_ADC_RATE_HZ(rate));
1022 }
1023
axp22x_adc_rate(struct axp20x_adc_iio * info,int rate)1024 static int axp22x_adc_rate(struct axp20x_adc_iio *info, int rate)
1025 {
1026 return regmap_update_bits(info->regmap, AXP20X_ADC_RATE,
1027 AXP20X_ADC_RATE_MASK,
1028 AXP22X_ADC_RATE_HZ(rate));
1029 }
1030
axp813_adc_rate(struct axp20x_adc_iio * info,int rate)1031 static int axp813_adc_rate(struct axp20x_adc_iio *info, int rate)
1032 {
1033 return regmap_update_bits(info->regmap, AXP813_ADC_RATE,
1034 AXP813_ADC_RATE_MASK,
1035 AXP813_ADC_RATE_HZ(rate));
1036 }
1037
1038 struct axp_data {
1039 const struct iio_info *iio_info;
1040 int num_channels;
1041 struct iio_chan_spec const *channels;
1042 unsigned long adc_en1;
1043 unsigned long adc_en1_mask;
1044 unsigned long adc_en2;
1045 unsigned long adc_en2_mask;
1046 int (*adc_rate)(struct axp20x_adc_iio *info,
1047 int rate);
1048 struct iio_map *maps;
1049 };
1050
1051 static const struct axp_data axp192_data = {
1052 .iio_info = &axp192_adc_iio_info,
1053 .num_channels = ARRAY_SIZE(axp192_adc_channels),
1054 .channels = axp192_adc_channels,
1055 .adc_en1_mask = AXP192_ADC_EN1_MASK,
1056 .adc_en2_mask = AXP192_ADC_EN2_MASK,
1057 .adc_rate = axp20x_adc_rate,
1058 .maps = axp20x_maps,
1059 };
1060
1061 static const struct axp_data axp20x_data = {
1062 .iio_info = &axp20x_adc_iio_info,
1063 .num_channels = ARRAY_SIZE(axp20x_adc_channels),
1064 .channels = axp20x_adc_channels,
1065 .adc_en1 = AXP20X_ADC_EN1,
1066 .adc_en1_mask = AXP20X_ADC_EN1_MASK,
1067 .adc_en2 = AXP20X_ADC_EN2,
1068 .adc_en2_mask = AXP20X_ADC_EN2_MASK,
1069 .adc_rate = axp20x_adc_rate,
1070 .maps = axp20x_maps,
1071 };
1072
1073 static const struct axp_data axp22x_data = {
1074 .iio_info = &axp22x_adc_iio_info,
1075 .num_channels = ARRAY_SIZE(axp22x_adc_channels),
1076 .channels = axp22x_adc_channels,
1077 .adc_en1 = AXP20X_ADC_EN1,
1078 .adc_en1_mask = AXP22X_ADC_EN1_MASK,
1079 .adc_rate = axp22x_adc_rate,
1080 .maps = axp22x_maps,
1081 };
1082
1083 static const struct axp_data axp717_data = {
1084 .iio_info = &axp717_adc_iio_info,
1085 .num_channels = ARRAY_SIZE(axp717_adc_channels),
1086 .channels = axp717_adc_channels,
1087 .adc_en1 = AXP717_ADC_CH_EN_CONTROL,
1088 .adc_en1_mask = AXP717_ADC_EN1_MASK,
1089 .maps = axp717_maps,
1090 };
1091
1092 static const struct axp_data axp813_data = {
1093 .iio_info = &axp813_adc_iio_info,
1094 .num_channels = ARRAY_SIZE(axp813_adc_channels),
1095 .channels = axp813_adc_channels,
1096 .adc_en1 = AXP20X_ADC_EN1,
1097 .adc_en1_mask = AXP22X_ADC_EN1_MASK,
1098 .adc_rate = axp813_adc_rate,
1099 .maps = axp22x_maps,
1100 };
1101
1102 static const struct of_device_id axp20x_adc_of_match[] = {
1103 { .compatible = "x-powers,axp192-adc", .data = (void *)&axp192_data, },
1104 { .compatible = "x-powers,axp209-adc", .data = (void *)&axp20x_data, },
1105 { .compatible = "x-powers,axp221-adc", .data = (void *)&axp22x_data, },
1106 { .compatible = "x-powers,axp717-adc", .data = (void *)&axp717_data, },
1107 { .compatible = "x-powers,axp813-adc", .data = (void *)&axp813_data, },
1108 { /* sentinel */ }
1109 };
1110 MODULE_DEVICE_TABLE(of, axp20x_adc_of_match);
1111
1112 static const struct platform_device_id axp20x_adc_id_match[] = {
1113 { .name = "axp192-adc", .driver_data = (kernel_ulong_t)&axp192_data, },
1114 { .name = "axp20x-adc", .driver_data = (kernel_ulong_t)&axp20x_data, },
1115 { .name = "axp22x-adc", .driver_data = (kernel_ulong_t)&axp22x_data, },
1116 { .name = "axp717-adc", .driver_data = (kernel_ulong_t)&axp717_data, },
1117 { .name = "axp813-adc", .driver_data = (kernel_ulong_t)&axp813_data, },
1118 { /* sentinel */ },
1119 };
1120 MODULE_DEVICE_TABLE(platform, axp20x_adc_id_match);
1121
axp20x_probe(struct platform_device * pdev)1122 static int axp20x_probe(struct platform_device *pdev)
1123 {
1124 struct axp20x_adc_iio *info;
1125 struct iio_dev *indio_dev;
1126 struct axp20x_dev *axp20x_dev;
1127 int ret;
1128
1129 axp20x_dev = dev_get_drvdata(pdev->dev.parent);
1130
1131 indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(*info));
1132 if (!indio_dev)
1133 return -ENOMEM;
1134
1135 info = iio_priv(indio_dev);
1136 platform_set_drvdata(pdev, indio_dev);
1137
1138 info->regmap = axp20x_dev->regmap;
1139 indio_dev->modes = INDIO_DIRECT_MODE;
1140
1141 if (!dev_fwnode(&pdev->dev)) {
1142 const struct platform_device_id *id;
1143
1144 id = platform_get_device_id(pdev);
1145 info->data = (const struct axp_data *)id->driver_data;
1146 } else {
1147 struct device *dev = &pdev->dev;
1148
1149 info->data = device_get_match_data(dev);
1150 }
1151
1152 indio_dev->name = platform_get_device_id(pdev)->name;
1153 indio_dev->info = info->data->iio_info;
1154 indio_dev->num_channels = info->data->num_channels;
1155 indio_dev->channels = info->data->channels;
1156
1157 /* Enable the ADCs on IP */
1158 regmap_write(info->regmap, info->data->adc_en1,
1159 info->data->adc_en1_mask);
1160
1161 if (info->data->adc_en2_mask)
1162 regmap_set_bits(info->regmap, info->data->adc_en2,
1163 info->data->adc_en2_mask);
1164
1165 /* Configure ADCs rate */
1166 if (info->data->adc_rate)
1167 info->data->adc_rate(info, 100);
1168
1169 ret = iio_map_array_register(indio_dev, info->data->maps);
1170 if (ret < 0) {
1171 dev_err(&pdev->dev, "failed to register IIO maps: %d\n", ret);
1172 goto fail_map;
1173 }
1174
1175 ret = iio_device_register(indio_dev);
1176 if (ret < 0) {
1177 dev_err(&pdev->dev, "could not register the device\n");
1178 goto fail_register;
1179 }
1180
1181 return 0;
1182
1183 fail_register:
1184 iio_map_array_unregister(indio_dev);
1185
1186 fail_map:
1187 regmap_write(info->regmap, info->data->adc_en1, 0);
1188
1189 if (info->data->adc_en2_mask)
1190 regmap_write(info->regmap, info->data->adc_en2, 0);
1191
1192 return ret;
1193 }
1194
axp20x_remove(struct platform_device * pdev)1195 static void axp20x_remove(struct platform_device *pdev)
1196 {
1197 struct iio_dev *indio_dev = platform_get_drvdata(pdev);
1198 struct axp20x_adc_iio *info = iio_priv(indio_dev);
1199
1200 iio_device_unregister(indio_dev);
1201 iio_map_array_unregister(indio_dev);
1202
1203 regmap_write(info->regmap, info->data->adc_en1, 0);
1204
1205 if (info->data->adc_en2_mask)
1206 regmap_write(info->regmap, info->data->adc_en2, 0);
1207 }
1208
1209 static struct platform_driver axp20x_adc_driver = {
1210 .driver = {
1211 .name = "axp20x-adc",
1212 .of_match_table = axp20x_adc_of_match,
1213 },
1214 .id_table = axp20x_adc_id_match,
1215 .probe = axp20x_probe,
1216 .remove_new = axp20x_remove,
1217 };
1218
1219 module_platform_driver(axp20x_adc_driver);
1220
1221 MODULE_DESCRIPTION("ADC driver for AXP20X and AXP22X PMICs");
1222 MODULE_AUTHOR("Quentin Schulz <quentin.schulz@free-electrons.com>");
1223 MODULE_LICENSE("GPL");
1224