1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Driver for Microchip MCP3911, Two-channel Analog Front End
4 *
5 * Copyright (C) 2018 Marcus Folkesson <marcus.folkesson@gmail.com>
6 * Copyright (C) 2018 Kent Gustavsson <kent@minoris.se>
7 */
8 #include <linux/bitfield.h>
9 #include <linux/bitops.h>
10 #include <linux/cleanup.h>
11 #include <linux/clk.h>
12 #include <linux/delay.h>
13 #include <linux/err.h>
14 #include <linux/module.h>
15 #include <linux/mod_devicetable.h>
16 #include <linux/property.h>
17 #include <linux/regulator/consumer.h>
18 #include <linux/spi/spi.h>
19
20 #include <linux/iio/iio.h>
21 #include <linux/iio/buffer.h>
22 #include <linux/iio/triggered_buffer.h>
23 #include <linux/iio/trigger_consumer.h>
24 #include <linux/iio/trigger.h>
25
26 #include <linux/unaligned.h>
27
28 #define MCP3911_REG_CHANNEL0 0x00
29 #define MCP3911_REG_CHANNEL1 0x03
30 #define MCP3911_REG_MOD 0x06
31 #define MCP3911_REG_PHASE 0x07
32 #define MCP3911_REG_GAIN 0x09
33 #define MCP3911_GAIN_MASK(ch) (GENMASK(2, 0) << 3 * (ch))
34 #define MCP3911_GAIN_VAL(ch, val) ((val << 3 * (ch)) & MCP3911_GAIN_MASK(ch))
35
36 #define MCP3911_REG_STATUSCOM 0x0a
37 #define MCP3911_STATUSCOM_DRHIZ BIT(12)
38 #define MCP3911_STATUSCOM_READ GENMASK(7, 6)
39 #define MCP3911_STATUSCOM_CH1_24WIDTH BIT(4)
40 #define MCP3911_STATUSCOM_CH0_24WIDTH BIT(3)
41 #define MCP3911_STATUSCOM_EN_OFFCAL BIT(2)
42 #define MCP3911_STATUSCOM_EN_GAINCAL BIT(1)
43
44 #define MCP3911_REG_CONFIG 0x0c
45 #define MCP3911_CONFIG_CLKEXT BIT(1)
46 #define MCP3911_CONFIG_VREFEXT BIT(2)
47 #define MCP3911_CONFIG_OSR GENMASK(13, 11)
48
49 #define MCP3911_REG_OFFCAL_CH0 0x0e
50 #define MCP3911_REG_GAINCAL_CH0 0x11
51 #define MCP3911_REG_OFFCAL_CH1 0x14
52 #define MCP3911_REG_GAINCAL_CH1 0x17
53 #define MCP3911_REG_VREFCAL 0x1a
54
55 #define MCP3911_CHANNEL(ch) (MCP3911_REG_CHANNEL0 + (ch) * 3)
56 #define MCP3911_OFFCAL(ch) (MCP3911_REG_OFFCAL_CH0 + (ch) * 6)
57
58 /* Internal voltage reference in mV */
59 #define MCP3911_INT_VREF_MV 1200
60
61 #define MCP3911_REG_READ(reg, id) ((((reg) << 1) | ((id) << 6) | (1 << 0)) & 0xff)
62 #define MCP3911_REG_WRITE(reg, id) ((((reg) << 1) | ((id) << 6) | (0 << 0)) & 0xff)
63 #define MCP3911_REG_MASK GENMASK(4, 1)
64
65 #define MCP3911_NUM_SCALES 6
66
67 /* Registers compatible with MCP3910 */
68 #define MCP3910_REG_STATUSCOM 0x0c
69 #define MCP3910_STATUSCOM_READ GENMASK(23, 22)
70 #define MCP3910_STATUSCOM_DRHIZ BIT(20)
71
72 #define MCP3910_REG_GAIN 0x0b
73
74 #define MCP3910_REG_CONFIG0 0x0d
75 #define MCP3910_CONFIG0_EN_OFFCAL BIT(23)
76 #define MCP3910_CONFIG0_OSR GENMASK(15, 13)
77
78 #define MCP3910_REG_CONFIG1 0x0e
79 #define MCP3910_CONFIG1_CLKEXT BIT(6)
80 #define MCP3910_CONFIG1_VREFEXT BIT(7)
81
82 #define MCP3910_CHANNEL(ch) (MCP3911_REG_CHANNEL0 + (ch))
83
84 #define MCP3910_REG_OFFCAL_CH0 0x0f
85 #define MCP3910_OFFCAL(ch) (MCP3910_REG_OFFCAL_CH0 + (ch) * 6)
86
87 /* Maximal number of channels used by the MCP39XX family */
88 #define MCP39XX_MAX_NUM_CHANNELS 8
89
90 static const int mcp3911_osr_table[] = { 32, 64, 128, 256, 512, 1024, 2048, 4096 };
91 static u32 mcp3911_scale_table[MCP3911_NUM_SCALES][2];
92
93 enum mcp3911_id {
94 MCP3910,
95 MCP3911,
96 MCP3912,
97 MCP3913,
98 MCP3914,
99 MCP3918,
100 MCP3919,
101 };
102
103 struct mcp3911;
104 struct mcp3911_chip_info {
105 const struct iio_chan_spec *channels;
106 unsigned int num_channels;
107
108 int (*config)(struct mcp3911 *adc, bool external_vref);
109 int (*get_osr)(struct mcp3911 *adc, u32 *val);
110 int (*set_osr)(struct mcp3911 *adc, u32 val);
111 int (*enable_offset)(struct mcp3911 *adc, bool enable);
112 int (*get_offset)(struct mcp3911 *adc, int channel, int *val);
113 int (*set_offset)(struct mcp3911 *adc, int channel, int val);
114 int (*set_scale)(struct mcp3911 *adc, int channel, u32 val);
115 int (*get_raw)(struct mcp3911 *adc, int channel, int *val);
116 };
117
118 struct mcp3911 {
119 struct spi_device *spi;
120 struct mutex lock;
121 struct clk *clki;
122 u32 dev_addr;
123 struct iio_trigger *trig;
124 u32 gain[MCP39XX_MAX_NUM_CHANNELS];
125 const struct mcp3911_chip_info *chip;
126 struct {
127 u32 channels[MCP39XX_MAX_NUM_CHANNELS];
128 s64 ts __aligned(8);
129 } scan;
130
131 u8 tx_buf __aligned(IIO_DMA_MINALIGN);
132 u8 rx_buf[MCP39XX_MAX_NUM_CHANNELS * 3];
133 };
134
mcp3911_read(struct mcp3911 * adc,u8 reg,u32 * val,u8 len)135 static int mcp3911_read(struct mcp3911 *adc, u8 reg, u32 *val, u8 len)
136 {
137 int ret;
138
139 reg = MCP3911_REG_READ(reg, adc->dev_addr);
140 ret = spi_write_then_read(adc->spi, ®, 1, val, len);
141 if (ret < 0)
142 return ret;
143
144 be32_to_cpus(val);
145 *val >>= ((4 - len) * 8);
146 dev_dbg(&adc->spi->dev, "reading 0x%x from register 0x%lx\n", *val,
147 FIELD_GET(MCP3911_REG_MASK, reg));
148 return ret;
149 }
150
mcp3911_write(struct mcp3911 * adc,u8 reg,u32 val,u8 len)151 static int mcp3911_write(struct mcp3911 *adc, u8 reg, u32 val, u8 len)
152 {
153 dev_dbg(&adc->spi->dev, "writing 0x%x to register 0x%x\n", val, reg);
154
155 val <<= (3 - len) * 8;
156 cpu_to_be32s(&val);
157 val |= MCP3911_REG_WRITE(reg, adc->dev_addr);
158
159 return spi_write(adc->spi, &val, len + 1);
160 }
161
mcp3911_update(struct mcp3911 * adc,u8 reg,u32 mask,u32 val,u8 len)162 static int mcp3911_update(struct mcp3911 *adc, u8 reg, u32 mask, u32 val, u8 len)
163 {
164 u32 tmp;
165 int ret;
166
167 ret = mcp3911_read(adc, reg, &tmp, len);
168 if (ret)
169 return ret;
170
171 val &= mask;
172 val |= tmp & ~mask;
173 return mcp3911_write(adc, reg, val, len);
174 }
175
mcp3911_read_s24(struct mcp3911 * const adc,u8 const reg,s32 * const val)176 static int mcp3911_read_s24(struct mcp3911 *const adc, u8 const reg, s32 *const val)
177 {
178 u32 uval;
179 int const ret = mcp3911_read(adc, reg, &uval, 3);
180
181 if (ret)
182 return ret;
183
184 *val = sign_extend32(uval, 23);
185 return ret;
186 }
187
mcp3910_enable_offset(struct mcp3911 * adc,bool enable)188 static int mcp3910_enable_offset(struct mcp3911 *adc, bool enable)
189 {
190 unsigned int mask = MCP3910_CONFIG0_EN_OFFCAL;
191 unsigned int value = enable ? mask : 0;
192
193 return mcp3911_update(adc, MCP3910_REG_CONFIG0, mask, value, 3);
194 }
195
mcp3910_get_offset(struct mcp3911 * adc,int channel,int * val)196 static int mcp3910_get_offset(struct mcp3911 *adc, int channel, int *val)
197 {
198 return mcp3911_read(adc, MCP3910_OFFCAL(channel), val, 3);
199 }
200
mcp3910_set_offset(struct mcp3911 * adc,int channel,int val)201 static int mcp3910_set_offset(struct mcp3911 *adc, int channel, int val)
202 {
203 int ret;
204
205 ret = mcp3911_write(adc, MCP3910_OFFCAL(channel), val, 3);
206 if (ret)
207 return ret;
208
209 return adc->chip->enable_offset(adc, 1);
210 }
211
mcp3910_get_raw(struct mcp3911 * adc,int channel,s32 * val)212 static int mcp3910_get_raw(struct mcp3911 *adc, int channel, s32 *val)
213 {
214 return mcp3911_read_s24(adc, MCP3910_CHANNEL(channel), val);
215 }
216
mcp3911_enable_offset(struct mcp3911 * adc,bool enable)217 static int mcp3911_enable_offset(struct mcp3911 *adc, bool enable)
218 {
219 unsigned int mask = MCP3911_STATUSCOM_EN_OFFCAL;
220 unsigned int value = enable ? mask : 0;
221
222 return mcp3911_update(adc, MCP3911_REG_STATUSCOM, mask, value, 2);
223 }
224
mcp3911_get_offset(struct mcp3911 * adc,int channel,int * val)225 static int mcp3911_get_offset(struct mcp3911 *adc, int channel, int *val)
226 {
227 return mcp3911_read(adc, MCP3911_OFFCAL(channel), val, 3);
228 }
229
mcp3911_set_offset(struct mcp3911 * adc,int channel,int val)230 static int mcp3911_set_offset(struct mcp3911 *adc, int channel, int val)
231 {
232 int ret;
233
234 ret = mcp3911_write(adc, MCP3911_OFFCAL(channel), val, 3);
235 if (ret)
236 return ret;
237
238 return adc->chip->enable_offset(adc, 1);
239 }
240
mcp3911_get_raw(struct mcp3911 * adc,int channel,s32 * val)241 static int mcp3911_get_raw(struct mcp3911 *adc, int channel, s32 *val)
242 {
243 return mcp3911_read_s24(adc, MCP3911_CHANNEL(channel), val);
244 }
245
mcp3910_get_osr(struct mcp3911 * adc,u32 * val)246 static int mcp3910_get_osr(struct mcp3911 *adc, u32 *val)
247 {
248 int ret;
249 unsigned int osr;
250
251 ret = mcp3911_read(adc, MCP3910_REG_CONFIG0, val, 3);
252 if (ret)
253 return ret;
254
255 osr = FIELD_GET(MCP3910_CONFIG0_OSR, *val);
256 *val = 32 << osr;
257 return 0;
258 }
259
mcp3910_set_osr(struct mcp3911 * adc,u32 val)260 static int mcp3910_set_osr(struct mcp3911 *adc, u32 val)
261 {
262 unsigned int osr = FIELD_PREP(MCP3910_CONFIG0_OSR, val);
263 unsigned int mask = MCP3910_CONFIG0_OSR;
264
265 return mcp3911_update(adc, MCP3910_REG_CONFIG0, mask, osr, 3);
266 }
267
mcp3911_set_osr(struct mcp3911 * adc,u32 val)268 static int mcp3911_set_osr(struct mcp3911 *adc, u32 val)
269 {
270 unsigned int osr = FIELD_PREP(MCP3911_CONFIG_OSR, val);
271 unsigned int mask = MCP3911_CONFIG_OSR;
272
273 return mcp3911_update(adc, MCP3911_REG_CONFIG, mask, osr, 2);
274 }
275
mcp3911_get_osr(struct mcp3911 * adc,u32 * val)276 static int mcp3911_get_osr(struct mcp3911 *adc, u32 *val)
277 {
278 int ret;
279 unsigned int osr;
280
281 ret = mcp3911_read(adc, MCP3911_REG_CONFIG, val, 2);
282 if (ret)
283 return ret;
284
285 osr = FIELD_GET(MCP3911_CONFIG_OSR, *val);
286 *val = 32 << osr;
287 return ret;
288 }
289
mcp3910_set_scale(struct mcp3911 * adc,int channel,u32 val)290 static int mcp3910_set_scale(struct mcp3911 *adc, int channel, u32 val)
291 {
292 return mcp3911_update(adc, MCP3910_REG_GAIN,
293 MCP3911_GAIN_MASK(channel),
294 MCP3911_GAIN_VAL(channel, val), 3);
295 }
296
mcp3911_set_scale(struct mcp3911 * adc,int channel,u32 val)297 static int mcp3911_set_scale(struct mcp3911 *adc, int channel, u32 val)
298 {
299 return mcp3911_update(adc, MCP3911_REG_GAIN,
300 MCP3911_GAIN_MASK(channel),
301 MCP3911_GAIN_VAL(channel, val), 1);
302 }
303
mcp3911_write_raw_get_fmt(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,long mask)304 static int mcp3911_write_raw_get_fmt(struct iio_dev *indio_dev,
305 struct iio_chan_spec const *chan,
306 long mask)
307 {
308 switch (mask) {
309 case IIO_CHAN_INFO_SCALE:
310 return IIO_VAL_INT_PLUS_NANO;
311 case IIO_CHAN_INFO_OVERSAMPLING_RATIO:
312 return IIO_VAL_INT;
313 default:
314 return IIO_VAL_INT_PLUS_NANO;
315 }
316 }
317
mcp3911_read_avail(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,const int ** vals,int * type,int * length,long info)318 static int mcp3911_read_avail(struct iio_dev *indio_dev,
319 struct iio_chan_spec const *chan,
320 const int **vals, int *type, int *length,
321 long info)
322 {
323 switch (info) {
324 case IIO_CHAN_INFO_OVERSAMPLING_RATIO:
325 *type = IIO_VAL_INT;
326 *vals = mcp3911_osr_table;
327 *length = ARRAY_SIZE(mcp3911_osr_table);
328 return IIO_AVAIL_LIST;
329 case IIO_CHAN_INFO_SCALE:
330 *type = IIO_VAL_INT_PLUS_NANO;
331 *vals = (int *)mcp3911_scale_table;
332 *length = ARRAY_SIZE(mcp3911_scale_table) * 2;
333 return IIO_AVAIL_LIST;
334 default:
335 return -EINVAL;
336 }
337 }
338
mcp3911_read_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * channel,int * val,int * val2,long mask)339 static int mcp3911_read_raw(struct iio_dev *indio_dev,
340 struct iio_chan_spec const *channel, int *val,
341 int *val2, long mask)
342 {
343 struct mcp3911 *adc = iio_priv(indio_dev);
344 int ret;
345
346 guard(mutex)(&adc->lock);
347 switch (mask) {
348 case IIO_CHAN_INFO_RAW:
349 ret = adc->chip->get_raw(adc, channel->channel, val);
350 if (ret)
351 return ret;
352 return IIO_VAL_INT;
353 case IIO_CHAN_INFO_OFFSET:
354 ret = adc->chip->get_offset(adc, channel->channel, val);
355 if (ret)
356 return ret;
357
358 return IIO_VAL_INT;
359 case IIO_CHAN_INFO_OVERSAMPLING_RATIO:
360 ret = adc->chip->get_osr(adc, val);
361 if (ret)
362 return ret;
363
364 return IIO_VAL_INT;
365 case IIO_CHAN_INFO_SCALE:
366 *val = mcp3911_scale_table[ilog2(adc->gain[channel->channel])][0];
367 *val2 = mcp3911_scale_table[ilog2(adc->gain[channel->channel])][1];
368 return IIO_VAL_INT_PLUS_NANO;
369 default:
370 return -EINVAL;
371 }
372 }
373
mcp3911_write_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * channel,int val,int val2,long mask)374 static int mcp3911_write_raw(struct iio_dev *indio_dev,
375 struct iio_chan_spec const *channel, int val,
376 int val2, long mask)
377 {
378 struct mcp3911 *adc = iio_priv(indio_dev);
379
380 guard(mutex)(&adc->lock);
381 switch (mask) {
382 case IIO_CHAN_INFO_SCALE:
383 for (int i = 0; i < MCP3911_NUM_SCALES; i++) {
384 if (val == mcp3911_scale_table[i][0] &&
385 val2 == mcp3911_scale_table[i][1]) {
386
387 adc->gain[channel->channel] = BIT(i);
388 return adc->chip->set_scale(adc, channel->channel, i);
389 }
390 }
391 return -EINVAL;
392 case IIO_CHAN_INFO_OFFSET:
393 if (val2 != 0)
394 return -EINVAL;
395
396 return adc->chip->set_offset(adc, channel->channel, val);
397 case IIO_CHAN_INFO_OVERSAMPLING_RATIO:
398 for (int i = 0; i < ARRAY_SIZE(mcp3911_osr_table); i++) {
399 if (val == mcp3911_osr_table[i]) {
400 return adc->chip->set_osr(adc, i);
401 }
402 }
403 return -EINVAL;
404 default:
405 return -EINVAL;
406 }
407 }
408
mcp3911_calc_scale_table(u32 vref_mv)409 static int mcp3911_calc_scale_table(u32 vref_mv)
410 {
411 u32 div;
412 u64 tmp;
413
414 /*
415 * For 24-bit Conversion
416 * Raw = ((Voltage)/(Vref) * 2^23 * Gain * 1.5
417 * Voltage = Raw * (Vref)/(2^23 * Gain * 1.5)
418 *
419 * ref = Reference voltage
420 * div = (2^23 * 1.5 * gain) = 12582912 * gain
421 */
422 for (int i = 0; i < MCP3911_NUM_SCALES; i++) {
423 div = 12582912 * BIT(i);
424 tmp = div_s64((s64)vref_mv * 1000000000LL, div);
425
426 mcp3911_scale_table[i][0] = 0;
427 mcp3911_scale_table[i][1] = tmp;
428 }
429
430 return 0;
431 }
432
433 #define MCP3911_CHAN(idx) { \
434 .type = IIO_VOLTAGE, \
435 .indexed = 1, \
436 .channel = idx, \
437 .scan_index = idx, \
438 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \
439 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
440 BIT(IIO_CHAN_INFO_OFFSET) | \
441 BIT(IIO_CHAN_INFO_SCALE), \
442 .info_mask_shared_by_type_available = \
443 BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \
444 .info_mask_separate_available = \
445 BIT(IIO_CHAN_INFO_SCALE), \
446 .scan_type = { \
447 .sign = 's', \
448 .realbits = 24, \
449 .storagebits = 32, \
450 .endianness = IIO_BE, \
451 }, \
452 }
453
454 static const struct iio_chan_spec mcp3910_channels[] = {
455 MCP3911_CHAN(0),
456 MCP3911_CHAN(1),
457 IIO_CHAN_SOFT_TIMESTAMP(2),
458 };
459
460 static const struct iio_chan_spec mcp3911_channels[] = {
461 MCP3911_CHAN(0),
462 MCP3911_CHAN(1),
463 IIO_CHAN_SOFT_TIMESTAMP(2),
464 };
465
466 static const struct iio_chan_spec mcp3912_channels[] = {
467 MCP3911_CHAN(0),
468 MCP3911_CHAN(1),
469 MCP3911_CHAN(2),
470 MCP3911_CHAN(3),
471 IIO_CHAN_SOFT_TIMESTAMP(4),
472 };
473
474 static const struct iio_chan_spec mcp3913_channels[] = {
475 MCP3911_CHAN(0),
476 MCP3911_CHAN(1),
477 MCP3911_CHAN(2),
478 MCP3911_CHAN(3),
479 MCP3911_CHAN(4),
480 MCP3911_CHAN(5),
481 IIO_CHAN_SOFT_TIMESTAMP(6),
482 };
483
484 static const struct iio_chan_spec mcp3914_channels[] = {
485 MCP3911_CHAN(0),
486 MCP3911_CHAN(1),
487 MCP3911_CHAN(2),
488 MCP3911_CHAN(3),
489 MCP3911_CHAN(4),
490 MCP3911_CHAN(5),
491 MCP3911_CHAN(6),
492 MCP3911_CHAN(7),
493 IIO_CHAN_SOFT_TIMESTAMP(8),
494 };
495
496 static const struct iio_chan_spec mcp3918_channels[] = {
497 MCP3911_CHAN(0),
498 IIO_CHAN_SOFT_TIMESTAMP(1),
499 };
500
501 static const struct iio_chan_spec mcp3919_channels[] = {
502 MCP3911_CHAN(0),
503 MCP3911_CHAN(1),
504 MCP3911_CHAN(2),
505 IIO_CHAN_SOFT_TIMESTAMP(3),
506 };
507
mcp3911_trigger_handler(int irq,void * p)508 static irqreturn_t mcp3911_trigger_handler(int irq, void *p)
509 {
510 struct iio_poll_func *pf = p;
511 struct iio_dev *indio_dev = pf->indio_dev;
512 struct mcp3911 *adc = iio_priv(indio_dev);
513 struct device *dev = &adc->spi->dev;
514 struct spi_transfer xfer[] = {
515 {
516 .tx_buf = &adc->tx_buf,
517 .len = 1,
518 }, {
519 .rx_buf = adc->rx_buf,
520 .len = (adc->chip->num_channels - 1) * 3,
521 },
522 };
523 int scan_index;
524 int i = 0;
525 int ret;
526
527 guard(mutex)(&adc->lock);
528 adc->tx_buf = MCP3911_REG_READ(MCP3911_CHANNEL(0), adc->dev_addr);
529 ret = spi_sync_transfer(adc->spi, xfer, ARRAY_SIZE(xfer));
530 if (ret < 0) {
531 dev_warn(dev, "failed to get conversion data\n");
532 goto out;
533 }
534
535 iio_for_each_active_channel(indio_dev, scan_index) {
536 const struct iio_chan_spec *scan_chan = &indio_dev->channels[scan_index];
537
538 adc->scan.channels[i] = get_unaligned_be24(&adc->rx_buf[scan_chan->channel * 3]);
539 i++;
540 }
541 iio_push_to_buffers_with_timestamp(indio_dev, &adc->scan,
542 iio_get_time_ns(indio_dev));
543 out:
544 iio_trigger_notify_done(indio_dev->trig);
545
546 return IRQ_HANDLED;
547 }
548
549 static const struct iio_info mcp3911_info = {
550 .read_raw = mcp3911_read_raw,
551 .write_raw = mcp3911_write_raw,
552 .read_avail = mcp3911_read_avail,
553 .write_raw_get_fmt = mcp3911_write_raw_get_fmt,
554 };
555
mcp3911_config(struct mcp3911 * adc,bool external_vref)556 static int mcp3911_config(struct mcp3911 *adc, bool external_vref)
557 {
558 struct device *dev = &adc->spi->dev;
559 u32 regval;
560 int ret;
561
562 ret = mcp3911_read(adc, MCP3911_REG_CONFIG, ®val, 2);
563 if (ret)
564 return ret;
565
566 regval &= ~MCP3911_CONFIG_VREFEXT;
567 if (external_vref) {
568 dev_dbg(dev, "use external voltage reference\n");
569 regval |= FIELD_PREP(MCP3911_CONFIG_VREFEXT, 1);
570 } else {
571 dev_dbg(dev, "use internal voltage reference (1.2V)\n");
572 regval |= FIELD_PREP(MCP3911_CONFIG_VREFEXT, 0);
573 }
574
575 regval &= ~MCP3911_CONFIG_CLKEXT;
576 if (adc->clki) {
577 dev_dbg(dev, "use external clock as clocksource\n");
578 regval |= FIELD_PREP(MCP3911_CONFIG_CLKEXT, 1);
579 } else {
580 dev_dbg(dev, "use crystal oscillator as clocksource\n");
581 regval |= FIELD_PREP(MCP3911_CONFIG_CLKEXT, 0);
582 }
583
584 ret = mcp3911_write(adc, MCP3911_REG_CONFIG, regval, 2);
585 if (ret)
586 return ret;
587
588 ret = mcp3911_read(adc, MCP3911_REG_STATUSCOM, ®val, 2);
589 if (ret)
590 return ret;
591
592 /* Address counter incremented, cycle through register types */
593 regval &= ~MCP3911_STATUSCOM_READ;
594 regval |= FIELD_PREP(MCP3911_STATUSCOM_READ, 0x02);
595
596 regval &= ~MCP3911_STATUSCOM_DRHIZ;
597 if (device_property_read_bool(dev, "microchip,data-ready-hiz"))
598 regval |= FIELD_PREP(MCP3911_STATUSCOM_DRHIZ, 0);
599 else
600 regval |= FIELD_PREP(MCP3911_STATUSCOM_DRHIZ, 1);
601
602 /* Disable offset to ignore any old values in offset register */
603 regval &= ~MCP3911_STATUSCOM_EN_OFFCAL;
604
605 ret = mcp3911_write(adc, MCP3911_REG_STATUSCOM, regval, 2);
606 if (ret)
607 return ret;
608
609 /* Set gain to 1 for all channels */
610 ret = mcp3911_read(adc, MCP3911_REG_GAIN, ®val, 1);
611 if (ret)
612 return ret;
613
614 for (int i = 0; i < adc->chip->num_channels - 1; i++) {
615 adc->gain[i] = 1;
616 regval &= ~MCP3911_GAIN_MASK(i);
617 }
618
619 return mcp3911_write(adc, MCP3911_REG_GAIN, regval, 1);
620 }
621
mcp3910_config(struct mcp3911 * adc,bool external_vref)622 static int mcp3910_config(struct mcp3911 *adc, bool external_vref)
623 {
624 struct device *dev = &adc->spi->dev;
625 u32 regval;
626 int ret;
627
628 ret = mcp3911_read(adc, MCP3910_REG_CONFIG1, ®val, 3);
629 if (ret)
630 return ret;
631
632 regval &= ~MCP3910_CONFIG1_VREFEXT;
633 if (external_vref) {
634 dev_dbg(dev, "use external voltage reference\n");
635 regval |= FIELD_PREP(MCP3910_CONFIG1_VREFEXT, 1);
636 } else {
637 dev_dbg(dev, "use internal voltage reference (1.2V)\n");
638 regval |= FIELD_PREP(MCP3910_CONFIG1_VREFEXT, 0);
639 }
640
641 regval &= ~MCP3910_CONFIG1_CLKEXT;
642 if (adc->clki) {
643 dev_dbg(dev, "use external clock as clocksource\n");
644 regval |= FIELD_PREP(MCP3910_CONFIG1_CLKEXT, 1);
645 } else {
646 dev_dbg(dev, "use crystal oscillator as clocksource\n");
647 regval |= FIELD_PREP(MCP3910_CONFIG1_CLKEXT, 0);
648 }
649
650 ret = mcp3911_write(adc, MCP3910_REG_CONFIG1, regval, 3);
651 if (ret)
652 return ret;
653
654 ret = mcp3911_read(adc, MCP3910_REG_STATUSCOM, ®val, 3);
655 if (ret)
656 return ret;
657
658 /* Address counter incremented, cycle through register types */
659 regval &= ~MCP3910_STATUSCOM_READ;
660 regval |= FIELD_PREP(MCP3910_STATUSCOM_READ, 0x02);
661
662 regval &= ~MCP3910_STATUSCOM_DRHIZ;
663 if (device_property_read_bool(dev, "microchip,data-ready-hiz"))
664 regval |= FIELD_PREP(MCP3910_STATUSCOM_DRHIZ, 0);
665 else
666 regval |= FIELD_PREP(MCP3910_STATUSCOM_DRHIZ, 1);
667
668 ret = mcp3911_write(adc, MCP3910_REG_STATUSCOM, regval, 3);
669 if (ret)
670 return ret;
671
672 /* Set gain to 1 for all channels */
673 ret = mcp3911_read(adc, MCP3910_REG_GAIN, ®val, 3);
674 if (ret)
675 return ret;
676
677 for (int i = 0; i < adc->chip->num_channels - 1; i++) {
678 adc->gain[i] = 1;
679 regval &= ~MCP3911_GAIN_MASK(i);
680 }
681 ret = mcp3911_write(adc, MCP3910_REG_GAIN, regval, 3);
682 if (ret)
683 return ret;
684
685 /* Disable offset to ignore any old values in offset register */
686 return adc->chip->enable_offset(adc, 0);
687 }
688
mcp3911_set_trigger_state(struct iio_trigger * trig,bool enable)689 static int mcp3911_set_trigger_state(struct iio_trigger *trig, bool enable)
690 {
691 struct mcp3911 *adc = iio_trigger_get_drvdata(trig);
692
693 if (enable)
694 enable_irq(adc->spi->irq);
695 else
696 disable_irq(adc->spi->irq);
697
698 return 0;
699 }
700
701 static const struct iio_trigger_ops mcp3911_trigger_ops = {
702 .validate_device = iio_trigger_validate_own_device,
703 .set_trigger_state = mcp3911_set_trigger_state,
704 };
705
mcp3911_probe(struct spi_device * spi)706 static int mcp3911_probe(struct spi_device *spi)
707 {
708 struct device *dev = &spi->dev;
709 struct iio_dev *indio_dev;
710 struct mcp3911 *adc;
711 bool external_vref;
712 u32 vref_mv;
713 int ret;
714
715 indio_dev = devm_iio_device_alloc(dev, sizeof(*adc));
716 if (!indio_dev)
717 return -ENOMEM;
718
719 adc = iio_priv(indio_dev);
720 adc->spi = spi;
721 adc->chip = spi_get_device_match_data(spi);
722
723 ret = devm_regulator_get_enable_read_voltage(dev, "vref");
724 if (ret < 0 && ret != -ENODEV)
725 return dev_err_probe(dev, ret, "failed to get vref voltage\n");
726
727 external_vref = ret != -ENODEV;
728 vref_mv = external_vref ? ret / 1000 : MCP3911_INT_VREF_MV;
729
730 adc->clki = devm_clk_get_enabled(dev, NULL);
731 if (IS_ERR(adc->clki)) {
732 if (PTR_ERR(adc->clki) == -ENOENT) {
733 adc->clki = NULL;
734 } else {
735 return dev_err_probe(dev, PTR_ERR(adc->clki), "failed to get adc clk\n");
736 }
737 }
738
739 /*
740 * Fallback to "device-addr" due to historical mismatch between
741 * dt-bindings and implementation.
742 */
743 ret = device_property_read_u32(dev, "microchip,device-addr", &adc->dev_addr);
744 if (ret)
745 device_property_read_u32(dev, "device-addr", &adc->dev_addr);
746 if (adc->dev_addr > 3) {
747 return dev_err_probe(dev, -EINVAL,
748 "invalid device address (%i). Must be in range 0-3.\n",
749 adc->dev_addr);
750 }
751 dev_dbg(dev, "use device address %i\n", adc->dev_addr);
752
753 ret = adc->chip->config(adc, external_vref);
754 if (ret)
755 return ret;
756
757 ret = mcp3911_calc_scale_table(vref_mv);
758 if (ret)
759 return ret;
760
761 /* Set gain to 1 for all channels */
762 for (int i = 0; i < adc->chip->num_channels - 1; i++) {
763 adc->gain[i] = 1;
764 ret = mcp3911_update(adc, MCP3911_REG_GAIN,
765 MCP3911_GAIN_MASK(i),
766 MCP3911_GAIN_VAL(i, 0), 1);
767 if (ret)
768 return ret;
769 }
770
771 indio_dev->name = spi_get_device_id(spi)->name;
772 indio_dev->modes = INDIO_DIRECT_MODE;
773 indio_dev->info = &mcp3911_info;
774 spi_set_drvdata(spi, indio_dev);
775
776 indio_dev->channels = adc->chip->channels;
777 indio_dev->num_channels = adc->chip->num_channels;
778
779 mutex_init(&adc->lock);
780
781 if (spi->irq > 0) {
782 adc->trig = devm_iio_trigger_alloc(dev, "%s-dev%d", indio_dev->name,
783 iio_device_id(indio_dev));
784 if (!adc->trig)
785 return -ENOMEM;
786
787 adc->trig->ops = &mcp3911_trigger_ops;
788 iio_trigger_set_drvdata(adc->trig, adc);
789 ret = devm_iio_trigger_register(dev, adc->trig);
790 if (ret)
791 return ret;
792
793 /*
794 * The device generates interrupts as long as it is powered up.
795 * Some platforms might not allow the option to power it down so
796 * don't enable the interrupt to avoid extra load on the system.
797 */
798 ret = devm_request_irq(dev, spi->irq, &iio_trigger_generic_data_rdy_poll,
799 IRQF_NO_AUTOEN | IRQF_ONESHOT,
800 indio_dev->name, adc->trig);
801 if (ret)
802 return ret;
803 }
804
805 ret = devm_iio_triggered_buffer_setup(dev, indio_dev, NULL,
806 mcp3911_trigger_handler, NULL);
807 if (ret)
808 return ret;
809
810 return devm_iio_device_register(dev, indio_dev);
811 }
812
813 static const struct mcp3911_chip_info mcp3911_chip_info[] = {
814 [MCP3910] = {
815 .channels = mcp3910_channels,
816 .num_channels = ARRAY_SIZE(mcp3910_channels),
817 .config = mcp3910_config,
818 .get_osr = mcp3910_get_osr,
819 .set_osr = mcp3910_set_osr,
820 .enable_offset = mcp3910_enable_offset,
821 .get_offset = mcp3910_get_offset,
822 .set_offset = mcp3910_set_offset,
823 .set_scale = mcp3910_set_scale,
824 .get_raw = mcp3910_get_raw,
825 },
826 [MCP3911] = {
827 .channels = mcp3911_channels,
828 .num_channels = ARRAY_SIZE(mcp3911_channels),
829 .config = mcp3911_config,
830 .get_osr = mcp3911_get_osr,
831 .set_osr = mcp3911_set_osr,
832 .enable_offset = mcp3911_enable_offset,
833 .get_offset = mcp3911_get_offset,
834 .set_offset = mcp3911_set_offset,
835 .set_scale = mcp3911_set_scale,
836 .get_raw = mcp3911_get_raw,
837 },
838 [MCP3912] = {
839 .channels = mcp3912_channels,
840 .num_channels = ARRAY_SIZE(mcp3912_channels),
841 .config = mcp3910_config,
842 .get_osr = mcp3910_get_osr,
843 .set_osr = mcp3910_set_osr,
844 .enable_offset = mcp3910_enable_offset,
845 .get_offset = mcp3910_get_offset,
846 .set_offset = mcp3910_set_offset,
847 .set_scale = mcp3910_set_scale,
848 .get_raw = mcp3910_get_raw,
849 },
850 [MCP3913] = {
851 .channels = mcp3913_channels,
852 .num_channels = ARRAY_SIZE(mcp3913_channels),
853 .config = mcp3910_config,
854 .get_osr = mcp3910_get_osr,
855 .set_osr = mcp3910_set_osr,
856 .enable_offset = mcp3910_enable_offset,
857 .get_offset = mcp3910_get_offset,
858 .set_offset = mcp3910_set_offset,
859 .set_scale = mcp3910_set_scale,
860 .get_raw = mcp3910_get_raw,
861 },
862 [MCP3914] = {
863 .channels = mcp3914_channels,
864 .num_channels = ARRAY_SIZE(mcp3914_channels),
865 .config = mcp3910_config,
866 .get_osr = mcp3910_get_osr,
867 .set_osr = mcp3910_set_osr,
868 .enable_offset = mcp3910_enable_offset,
869 .get_offset = mcp3910_get_offset,
870 .set_offset = mcp3910_set_offset,
871 .set_scale = mcp3910_set_scale,
872 .get_raw = mcp3910_get_raw,
873 },
874 [MCP3918] = {
875 .channels = mcp3918_channels,
876 .num_channels = ARRAY_SIZE(mcp3918_channels),
877 .config = mcp3910_config,
878 .get_osr = mcp3910_get_osr,
879 .set_osr = mcp3910_set_osr,
880 .enable_offset = mcp3910_enable_offset,
881 .get_offset = mcp3910_get_offset,
882 .set_offset = mcp3910_set_offset,
883 .set_scale = mcp3910_set_scale,
884 .get_raw = mcp3910_get_raw,
885 },
886 [MCP3919] = {
887 .channels = mcp3919_channels,
888 .num_channels = ARRAY_SIZE(mcp3919_channels),
889 .config = mcp3910_config,
890 .get_osr = mcp3910_get_osr,
891 .set_osr = mcp3910_set_osr,
892 .enable_offset = mcp3910_enable_offset,
893 .get_offset = mcp3910_get_offset,
894 .set_offset = mcp3910_set_offset,
895 .set_scale = mcp3910_set_scale,
896 .get_raw = mcp3910_get_raw,
897 },
898 };
899 static const struct of_device_id mcp3911_dt_ids[] = {
900 { .compatible = "microchip,mcp3910", .data = &mcp3911_chip_info[MCP3910] },
901 { .compatible = "microchip,mcp3911", .data = &mcp3911_chip_info[MCP3911] },
902 { .compatible = "microchip,mcp3912", .data = &mcp3911_chip_info[MCP3912] },
903 { .compatible = "microchip,mcp3913", .data = &mcp3911_chip_info[MCP3913] },
904 { .compatible = "microchip,mcp3914", .data = &mcp3911_chip_info[MCP3914] },
905 { .compatible = "microchip,mcp3918", .data = &mcp3911_chip_info[MCP3918] },
906 { .compatible = "microchip,mcp3919", .data = &mcp3911_chip_info[MCP3919] },
907 { }
908 };
909 MODULE_DEVICE_TABLE(of, mcp3911_dt_ids);
910
911 static const struct spi_device_id mcp3911_id[] = {
912 { "mcp3910", (kernel_ulong_t)&mcp3911_chip_info[MCP3910] },
913 { "mcp3911", (kernel_ulong_t)&mcp3911_chip_info[MCP3911] },
914 { "mcp3912", (kernel_ulong_t)&mcp3911_chip_info[MCP3912] },
915 { "mcp3913", (kernel_ulong_t)&mcp3911_chip_info[MCP3913] },
916 { "mcp3914", (kernel_ulong_t)&mcp3911_chip_info[MCP3914] },
917 { "mcp3918", (kernel_ulong_t)&mcp3911_chip_info[MCP3918] },
918 { "mcp3919", (kernel_ulong_t)&mcp3911_chip_info[MCP3919] },
919 { }
920 };
921 MODULE_DEVICE_TABLE(spi, mcp3911_id);
922
923 static struct spi_driver mcp3911_driver = {
924 .driver = {
925 .name = "mcp3911",
926 .of_match_table = mcp3911_dt_ids,
927 },
928 .probe = mcp3911_probe,
929 .id_table = mcp3911_id,
930 };
931 module_spi_driver(mcp3911_driver);
932
933 MODULE_AUTHOR("Marcus Folkesson <marcus.folkesson@gmail.com>");
934 MODULE_AUTHOR("Kent Gustavsson <kent@minoris.se>");
935 MODULE_DESCRIPTION("Microchip Technology MCP3911");
936 MODULE_LICENSE("GPL v2");
937