1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * IIO driver for Bosch BNO055 IMU
4 *
5 * Copyright (C) 2021-2022 Istituto Italiano di Tecnologia
6 * Electronic Design Laboratory
7 * Written by Andrea Merello <andrea.merello@iit.it>
8 *
9 * Portions of this driver are taken from the BNO055 driver patch
10 * from Vlad Dogaru which is Copyright (c) 2016, Intel Corporation.
11 *
12 * This driver is also based on BMI160 driver, which is:
13 * Copyright (c) 2016, Intel Corporation.
14 * Copyright (c) 2019, Martin Kelly.
15 */
16
17 #include <linux/bitfield.h>
18 #include <linux/bitmap.h>
19 #include <linux/clk.h>
20 #include <linux/debugfs.h>
21 #include <linux/device.h>
22 #include <linux/firmware.h>
23 #include <linux/gpio/consumer.h>
24 #include <linux/module.h>
25 #include <linux/mutex.h>
26 #include <linux/regmap.h>
27 #include <linux/util_macros.h>
28
29 #include <linux/iio/buffer.h>
30 #include <linux/iio/iio.h>
31 #include <linux/iio/sysfs.h>
32 #include <linux/iio/trigger_consumer.h>
33 #include <linux/iio/triggered_buffer.h>
34
35 #include "bno055.h"
36
37 #define BNO055_FW_UID_FMT "bno055-caldata-%*phN.dat"
38 #define BNO055_FW_GENERIC_NAME "bno055-caldata.dat"
39
40 /* common registers */
41 #define BNO055_PAGESEL_REG 0x7
42
43 /* page 0 registers */
44 #define BNO055_CHIP_ID_REG 0x0
45 #define BNO055_CHIP_ID_MAGIC 0xA0
46 #define BNO055_SW_REV_LSB_REG 0x4
47 #define BNO055_SW_REV_MSB_REG 0x5
48 #define BNO055_ACC_DATA_X_LSB_REG 0x8
49 #define BNO055_ACC_DATA_Y_LSB_REG 0xA
50 #define BNO055_ACC_DATA_Z_LSB_REG 0xC
51 #define BNO055_MAG_DATA_X_LSB_REG 0xE
52 #define BNO055_MAG_DATA_Y_LSB_REG 0x10
53 #define BNO055_MAG_DATA_Z_LSB_REG 0x12
54 #define BNO055_GYR_DATA_X_LSB_REG 0x14
55 #define BNO055_GYR_DATA_Y_LSB_REG 0x16
56 #define BNO055_GYR_DATA_Z_LSB_REG 0x18
57 #define BNO055_EUL_DATA_X_LSB_REG 0x1A
58 #define BNO055_EUL_DATA_Y_LSB_REG 0x1C
59 #define BNO055_EUL_DATA_Z_LSB_REG 0x1E
60 #define BNO055_QUAT_DATA_W_LSB_REG 0x20
61 #define BNO055_LIA_DATA_X_LSB_REG 0x28
62 #define BNO055_LIA_DATA_Y_LSB_REG 0x2A
63 #define BNO055_LIA_DATA_Z_LSB_REG 0x2C
64 #define BNO055_GRAVITY_DATA_X_LSB_REG 0x2E
65 #define BNO055_GRAVITY_DATA_Y_LSB_REG 0x30
66 #define BNO055_GRAVITY_DATA_Z_LSB_REG 0x32
67 #define BNO055_SCAN_CH_COUNT ((BNO055_GRAVITY_DATA_Z_LSB_REG - BNO055_ACC_DATA_X_LSB_REG) / 2)
68 #define BNO055_TEMP_REG 0x34
69 #define BNO055_CALIB_STAT_REG 0x35
70 #define BNO055_CALIB_STAT_MAGN_SHIFT 0
71 #define BNO055_CALIB_STAT_ACCEL_SHIFT 2
72 #define BNO055_CALIB_STAT_GYRO_SHIFT 4
73 #define BNO055_CALIB_STAT_SYS_SHIFT 6
74 #define BNO055_SYS_ERR_REG 0x3A
75 #define BNO055_POWER_MODE_REG 0x3E
76 #define BNO055_POWER_MODE_NORMAL 0
77 #define BNO055_SYS_TRIGGER_REG 0x3F
78 #define BNO055_SYS_TRIGGER_RST_SYS BIT(5)
79 #define BNO055_SYS_TRIGGER_CLK_SEL BIT(7)
80 #define BNO055_OPR_MODE_REG 0x3D
81 #define BNO055_OPR_MODE_CONFIG 0x0
82 #define BNO055_OPR_MODE_AMG 0x7
83 #define BNO055_OPR_MODE_FUSION_FMC_OFF 0xB
84 #define BNO055_OPR_MODE_FUSION 0xC
85 #define BNO055_UNIT_SEL_REG 0x3B
86 /* Android orientation mode means: pitch value decreases turning clockwise */
87 #define BNO055_UNIT_SEL_ANDROID BIT(7)
88 #define BNO055_UNIT_SEL_GYR_RPS BIT(1)
89 #define BNO055_CALDATA_START 0x55
90 #define BNO055_CALDATA_END 0x6A
91 #define BNO055_CALDATA_LEN 22
92
93 /*
94 * The difference in address between the register that contains the
95 * value and the register that contains the offset. This applies for
96 * accel, gyro and magn channels.
97 */
98 #define BNO055_REG_OFFSET_ADDR 0x4D
99
100 /* page 1 registers */
101 #define BNO055_PG1(x) ((x) | 0x80)
102 #define BNO055_ACC_CONFIG_REG BNO055_PG1(0x8)
103 #define BNO055_ACC_CONFIG_LPF_MASK GENMASK(4, 2)
104 #define BNO055_ACC_CONFIG_RANGE_MASK GENMASK(1, 0)
105 #define BNO055_MAG_CONFIG_REG BNO055_PG1(0x9)
106 #define BNO055_MAG_CONFIG_HIGHACCURACY 0x18
107 #define BNO055_MAG_CONFIG_ODR_MASK GENMASK(2, 0)
108 #define BNO055_GYR_CONFIG_REG BNO055_PG1(0xA)
109 #define BNO055_GYR_CONFIG_RANGE_MASK GENMASK(2, 0)
110 #define BNO055_GYR_CONFIG_LPF_MASK GENMASK(5, 3)
111 #define BNO055_GYR_AM_SET_REG BNO055_PG1(0x1F)
112 #define BNO055_UID_LOWER_REG BNO055_PG1(0x50)
113 #define BNO055_UID_HIGHER_REG BNO055_PG1(0x5F)
114 #define BNO055_UID_LEN 16
115
116 struct bno055_sysfs_attr {
117 int *vals;
118 int len;
119 int *fusion_vals;
120 int *hw_xlate;
121 int hw_xlate_len;
122 int type;
123 };
124
125 static int bno055_acc_lpf_vals[] = {
126 7, 810000, 15, 630000, 31, 250000, 62, 500000,
127 125, 0, 250, 0, 500, 0, 1000, 0,
128 };
129
130 static struct bno055_sysfs_attr bno055_acc_lpf = {
131 .vals = bno055_acc_lpf_vals,
132 .len = ARRAY_SIZE(bno055_acc_lpf_vals),
133 .fusion_vals = (int[]){62, 500000},
134 .type = IIO_VAL_INT_PLUS_MICRO,
135 };
136
137 static int bno055_acc_range_vals[] = {
138 /* G: 2, 4, 8, 16 */
139 1962, 3924, 7848, 15696
140 };
141
142 static struct bno055_sysfs_attr bno055_acc_range = {
143 .vals = bno055_acc_range_vals,
144 .len = ARRAY_SIZE(bno055_acc_range_vals),
145 .fusion_vals = (int[]){3924}, /* 4G */
146 .type = IIO_VAL_INT,
147 };
148
149 /*
150 * Theoretically the IMU should return data in a given (i.e. fixed) unit
151 * regardless of the range setting. This happens for the accelerometer, but not
152 * for the gyroscope; the gyroscope range setting affects the scale.
153 * This is probably due to this[0] bug.
154 * For this reason we map the internal range setting onto the standard IIO scale
155 * attribute for gyro.
156 * Since the bug[0] may be fixed in future, we check for the IMU FW version and
157 * eventually warn the user.
158 * Currently we just don't care about "range" attributes for gyro.
159 *
160 * [0] https://community.bosch-sensortec.com/t5/MEMS-sensors-forum/BNO055-Wrong-sensitivity-resolution-in-datasheet/td-p/10266
161 */
162
163 /*
164 * dps = hwval * (dps_range/2^15)
165 * rps = hwval * (rps_range/2^15)
166 * = hwval * (dps_range/(2^15 * k))
167 * where k is rad-to-deg factor
168 */
169 static int bno055_gyr_scale_vals[] = {
170 125, 1877467, 250, 1877467, 500, 1877467,
171 1000, 1877467, 2000, 1877467,
172 };
173
174 static int bno055_gyr_scale_hw_xlate[] = {0, 1, 2, 3, 4};
175 static struct bno055_sysfs_attr bno055_gyr_scale = {
176 .vals = bno055_gyr_scale_vals,
177 .len = ARRAY_SIZE(bno055_gyr_scale_vals),
178 .fusion_vals = (int[]){1, 900},
179 .hw_xlate = bno055_gyr_scale_hw_xlate,
180 .hw_xlate_len = ARRAY_SIZE(bno055_gyr_scale_hw_xlate),
181 .type = IIO_VAL_FRACTIONAL,
182 };
183
184 static int bno055_gyr_lpf_vals[] = {12, 23, 32, 47, 64, 116, 230, 523};
185 static int bno055_gyr_lpf_hw_xlate[] = {5, 4, 7, 3, 6, 2, 1, 0};
186 static struct bno055_sysfs_attr bno055_gyr_lpf = {
187 .vals = bno055_gyr_lpf_vals,
188 .len = ARRAY_SIZE(bno055_gyr_lpf_vals),
189 .fusion_vals = (int[]){32},
190 .hw_xlate = bno055_gyr_lpf_hw_xlate,
191 .hw_xlate_len = ARRAY_SIZE(bno055_gyr_lpf_hw_xlate),
192 .type = IIO_VAL_INT,
193 };
194
195 static int bno055_mag_odr_vals[] = {2, 6, 8, 10, 15, 20, 25, 30};
196 static struct bno055_sysfs_attr bno055_mag_odr = {
197 .vals = bno055_mag_odr_vals,
198 .len = ARRAY_SIZE(bno055_mag_odr_vals),
199 .fusion_vals = (int[]){20},
200 .type = IIO_VAL_INT,
201 };
202
203 struct bno055_priv {
204 struct regmap *regmap;
205 struct device *dev;
206 struct clk *clk;
207 int operation_mode;
208 int xfer_burst_break_thr;
209 struct mutex lock;
210 u8 uid[BNO055_UID_LEN];
211 struct gpio_desc *reset_gpio;
212 bool sw_reset;
213 struct {
214 __le16 chans[BNO055_SCAN_CH_COUNT];
215 s64 timestamp __aligned(8);
216 } buf;
217 struct dentry *debugfs;
218 };
219
bno055_regmap_volatile(struct device * dev,unsigned int reg)220 static bool bno055_regmap_volatile(struct device *dev, unsigned int reg)
221 {
222 /* data and status registers */
223 if (reg >= BNO055_ACC_DATA_X_LSB_REG && reg <= BNO055_SYS_ERR_REG)
224 return true;
225
226 /* when in fusion mode, config is updated by chip */
227 if (reg == BNO055_MAG_CONFIG_REG ||
228 reg == BNO055_ACC_CONFIG_REG ||
229 reg == BNO055_GYR_CONFIG_REG)
230 return true;
231
232 /* calibration data may be updated by the IMU */
233 if (reg >= BNO055_CALDATA_START && reg <= BNO055_CALDATA_END)
234 return true;
235
236 return false;
237 }
238
bno055_regmap_readable(struct device * dev,unsigned int reg)239 static bool bno055_regmap_readable(struct device *dev, unsigned int reg)
240 {
241 /* unnamed PG0 reserved areas */
242 if ((reg < BNO055_PG1(0) && reg > BNO055_CALDATA_END) ||
243 reg == 0x3C)
244 return false;
245
246 /* unnamed PG1 reserved areas */
247 if (reg > BNO055_PG1(BNO055_UID_HIGHER_REG) ||
248 (reg < BNO055_PG1(BNO055_UID_LOWER_REG) && reg > BNO055_PG1(BNO055_GYR_AM_SET_REG)) ||
249 reg == BNO055_PG1(0xE) ||
250 (reg < BNO055_PG1(BNO055_PAGESEL_REG) && reg >= BNO055_PG1(0x0)))
251 return false;
252 return true;
253 }
254
bno055_regmap_writeable(struct device * dev,unsigned int reg)255 static bool bno055_regmap_writeable(struct device *dev, unsigned int reg)
256 {
257 /*
258 * Unreadable registers are indeed reserved; there are no WO regs
259 * (except for a single bit in SYS_TRIGGER register)
260 */
261 if (!bno055_regmap_readable(dev, reg))
262 return false;
263
264 /* data and status registers */
265 if (reg >= BNO055_ACC_DATA_X_LSB_REG && reg <= BNO055_SYS_ERR_REG)
266 return false;
267
268 /* ID areas */
269 if (reg < BNO055_PAGESEL_REG ||
270 (reg <= BNO055_UID_HIGHER_REG && reg >= BNO055_UID_LOWER_REG))
271 return false;
272
273 return true;
274 }
275
276 static const struct regmap_range_cfg bno055_regmap_ranges[] = {
277 {
278 .range_min = 0,
279 .range_max = 0x7f * 2,
280 .selector_reg = BNO055_PAGESEL_REG,
281 .selector_mask = GENMASK(7, 0),
282 .selector_shift = 0,
283 .window_start = 0,
284 .window_len = 0x80,
285 },
286 };
287
288 const struct regmap_config bno055_regmap_config = {
289 .name = "bno055",
290 .reg_bits = 8,
291 .val_bits = 8,
292 .ranges = bno055_regmap_ranges,
293 .num_ranges = 1,
294 .volatile_reg = bno055_regmap_volatile,
295 .max_register = 0x80 * 2,
296 .writeable_reg = bno055_regmap_writeable,
297 .readable_reg = bno055_regmap_readable,
298 .cache_type = REGCACHE_RBTREE,
299 };
300 EXPORT_SYMBOL_NS_GPL(bno055_regmap_config, IIO_BNO055);
301
302 /* must be called in configuration mode */
bno055_calibration_load(struct bno055_priv * priv,const u8 * data,int len)303 static int bno055_calibration_load(struct bno055_priv *priv, const u8 *data, int len)
304 {
305 if (len != BNO055_CALDATA_LEN) {
306 dev_dbg(priv->dev, "Invalid calibration file size %d (expected %d)",
307 len, BNO055_CALDATA_LEN);
308 return -EINVAL;
309 }
310
311 dev_dbg(priv->dev, "loading cal data: %*ph", BNO055_CALDATA_LEN, data);
312 return regmap_bulk_write(priv->regmap, BNO055_CALDATA_START,
313 data, BNO055_CALDATA_LEN);
314 }
315
bno055_operation_mode_do_set(struct bno055_priv * priv,int operation_mode)316 static int bno055_operation_mode_do_set(struct bno055_priv *priv,
317 int operation_mode)
318 {
319 int ret;
320
321 ret = regmap_write(priv->regmap, BNO055_OPR_MODE_REG,
322 operation_mode);
323 if (ret)
324 return ret;
325
326 /* Following datasheet specifications: sensor takes 7mS up to 19 mS to switch mode */
327 msleep(20);
328
329 return 0;
330 }
331
bno055_system_reset(struct bno055_priv * priv)332 static int bno055_system_reset(struct bno055_priv *priv)
333 {
334 int ret;
335
336 if (priv->reset_gpio) {
337 gpiod_set_value_cansleep(priv->reset_gpio, 0);
338 usleep_range(5000, 10000);
339 gpiod_set_value_cansleep(priv->reset_gpio, 1);
340 } else if (priv->sw_reset) {
341 ret = regmap_write(priv->regmap, BNO055_SYS_TRIGGER_REG,
342 BNO055_SYS_TRIGGER_RST_SYS);
343 if (ret)
344 return ret;
345 } else {
346 return 0;
347 }
348
349 regcache_drop_region(priv->regmap, 0x0, 0xff);
350 usleep_range(650000, 700000);
351
352 return 0;
353 }
354
bno055_init(struct bno055_priv * priv,const u8 * caldata,int len)355 static int bno055_init(struct bno055_priv *priv, const u8 *caldata, int len)
356 {
357 int ret;
358
359 ret = bno055_operation_mode_do_set(priv, BNO055_OPR_MODE_CONFIG);
360 if (ret)
361 return ret;
362
363 ret = regmap_write(priv->regmap, BNO055_POWER_MODE_REG,
364 BNO055_POWER_MODE_NORMAL);
365 if (ret)
366 return ret;
367
368 ret = regmap_write(priv->regmap, BNO055_SYS_TRIGGER_REG,
369 priv->clk ? BNO055_SYS_TRIGGER_CLK_SEL : 0);
370 if (ret)
371 return ret;
372
373 /* use standard SI units */
374 ret = regmap_write(priv->regmap, BNO055_UNIT_SEL_REG,
375 BNO055_UNIT_SEL_ANDROID | BNO055_UNIT_SEL_GYR_RPS);
376 if (ret)
377 return ret;
378
379 if (caldata) {
380 ret = bno055_calibration_load(priv, caldata, len);
381 if (ret)
382 dev_warn(priv->dev, "failed to load calibration data with error %d\n",
383 ret);
384 }
385
386 return 0;
387 }
388
bno055_operation_mode_set(struct bno055_priv * priv,int operation_mode)389 static ssize_t bno055_operation_mode_set(struct bno055_priv *priv,
390 int operation_mode)
391 {
392 u8 caldata[BNO055_CALDATA_LEN];
393 int ret;
394
395 mutex_lock(&priv->lock);
396
397 ret = bno055_operation_mode_do_set(priv, BNO055_OPR_MODE_CONFIG);
398 if (ret)
399 goto exit_unlock;
400
401 if (operation_mode == BNO055_OPR_MODE_FUSION ||
402 operation_mode == BNO055_OPR_MODE_FUSION_FMC_OFF) {
403 /* for entering fusion mode, reset the chip to clear the algo state */
404 ret = regmap_bulk_read(priv->regmap, BNO055_CALDATA_START, caldata,
405 BNO055_CALDATA_LEN);
406 if (ret)
407 goto exit_unlock;
408
409 ret = bno055_system_reset(priv);
410 if (ret)
411 goto exit_unlock;
412
413 ret = bno055_init(priv, caldata, BNO055_CALDATA_LEN);
414 if (ret)
415 goto exit_unlock;
416 }
417
418 ret = bno055_operation_mode_do_set(priv, operation_mode);
419 if (ret)
420 goto exit_unlock;
421
422 priv->operation_mode = operation_mode;
423
424 exit_unlock:
425 mutex_unlock(&priv->lock);
426 return ret;
427 }
428
bno055_uninit(void * arg)429 static void bno055_uninit(void *arg)
430 {
431 struct bno055_priv *priv = arg;
432
433 /* stop the IMU */
434 bno055_operation_mode_do_set(priv, BNO055_OPR_MODE_CONFIG);
435 }
436
437 #define BNO055_CHANNEL(_type, _axis, _index, _address, _sep, _sh, _avail) { \
438 .address = _address, \
439 .type = _type, \
440 .modified = 1, \
441 .channel2 = IIO_MOD_##_axis, \
442 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | (_sep), \
443 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) | (_sh), \
444 .info_mask_shared_by_type_available = _avail, \
445 .scan_index = _index, \
446 .scan_type = { \
447 .sign = 's', \
448 .realbits = 16, \
449 .storagebits = 16, \
450 .endianness = IIO_LE, \
451 .repeat = IIO_MOD_##_axis == IIO_MOD_QUATERNION ? 4 : 0, \
452 }, \
453 }
454
455 /* scan indexes follow DATA register order */
456 enum bno055_scan_axis {
457 BNO055_SCAN_ACCEL_X,
458 BNO055_SCAN_ACCEL_Y,
459 BNO055_SCAN_ACCEL_Z,
460 BNO055_SCAN_MAGN_X,
461 BNO055_SCAN_MAGN_Y,
462 BNO055_SCAN_MAGN_Z,
463 BNO055_SCAN_GYRO_X,
464 BNO055_SCAN_GYRO_Y,
465 BNO055_SCAN_GYRO_Z,
466 BNO055_SCAN_YAW,
467 BNO055_SCAN_ROLL,
468 BNO055_SCAN_PITCH,
469 BNO055_SCAN_QUATERNION,
470 BNO055_SCAN_LIA_X,
471 BNO055_SCAN_LIA_Y,
472 BNO055_SCAN_LIA_Z,
473 BNO055_SCAN_GRAVITY_X,
474 BNO055_SCAN_GRAVITY_Y,
475 BNO055_SCAN_GRAVITY_Z,
476 BNO055_SCAN_TIMESTAMP,
477 _BNO055_SCAN_MAX
478 };
479
480 static const struct iio_chan_spec bno055_channels[] = {
481 /* accelerometer */
482 BNO055_CHANNEL(IIO_ACCEL, X, BNO055_SCAN_ACCEL_X,
483 BNO055_ACC_DATA_X_LSB_REG, BIT(IIO_CHAN_INFO_OFFSET),
484 BIT(IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY),
485 BIT(IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY)),
486 BNO055_CHANNEL(IIO_ACCEL, Y, BNO055_SCAN_ACCEL_Y,
487 BNO055_ACC_DATA_Y_LSB_REG, BIT(IIO_CHAN_INFO_OFFSET),
488 BIT(IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY),
489 BIT(IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY)),
490 BNO055_CHANNEL(IIO_ACCEL, Z, BNO055_SCAN_ACCEL_Z,
491 BNO055_ACC_DATA_Z_LSB_REG, BIT(IIO_CHAN_INFO_OFFSET),
492 BIT(IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY),
493 BIT(IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY)),
494 /* gyroscope */
495 BNO055_CHANNEL(IIO_ANGL_VEL, X, BNO055_SCAN_GYRO_X,
496 BNO055_GYR_DATA_X_LSB_REG, BIT(IIO_CHAN_INFO_OFFSET),
497 BIT(IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY),
498 BIT(IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY) |
499 BIT(IIO_CHAN_INFO_SCALE)),
500 BNO055_CHANNEL(IIO_ANGL_VEL, Y, BNO055_SCAN_GYRO_Y,
501 BNO055_GYR_DATA_Y_LSB_REG, BIT(IIO_CHAN_INFO_OFFSET),
502 BIT(IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY),
503 BIT(IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY) |
504 BIT(IIO_CHAN_INFO_SCALE)),
505 BNO055_CHANNEL(IIO_ANGL_VEL, Z, BNO055_SCAN_GYRO_Z,
506 BNO055_GYR_DATA_Z_LSB_REG, BIT(IIO_CHAN_INFO_OFFSET),
507 BIT(IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY),
508 BIT(IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY) |
509 BIT(IIO_CHAN_INFO_SCALE)),
510 /* magnetometer */
511 BNO055_CHANNEL(IIO_MAGN, X, BNO055_SCAN_MAGN_X,
512 BNO055_MAG_DATA_X_LSB_REG, BIT(IIO_CHAN_INFO_OFFSET),
513 BIT(IIO_CHAN_INFO_SAMP_FREQ), BIT(IIO_CHAN_INFO_SAMP_FREQ)),
514 BNO055_CHANNEL(IIO_MAGN, Y, BNO055_SCAN_MAGN_Y,
515 BNO055_MAG_DATA_Y_LSB_REG, BIT(IIO_CHAN_INFO_OFFSET),
516 BIT(IIO_CHAN_INFO_SAMP_FREQ), BIT(IIO_CHAN_INFO_SAMP_FREQ)),
517 BNO055_CHANNEL(IIO_MAGN, Z, BNO055_SCAN_MAGN_Z,
518 BNO055_MAG_DATA_Z_LSB_REG, BIT(IIO_CHAN_INFO_OFFSET),
519 BIT(IIO_CHAN_INFO_SAMP_FREQ), BIT(IIO_CHAN_INFO_SAMP_FREQ)),
520 /* euler angle */
521 BNO055_CHANNEL(IIO_ROT, YAW, BNO055_SCAN_YAW,
522 BNO055_EUL_DATA_X_LSB_REG, 0, 0, 0),
523 BNO055_CHANNEL(IIO_ROT, ROLL, BNO055_SCAN_ROLL,
524 BNO055_EUL_DATA_Y_LSB_REG, 0, 0, 0),
525 BNO055_CHANNEL(IIO_ROT, PITCH, BNO055_SCAN_PITCH,
526 BNO055_EUL_DATA_Z_LSB_REG, 0, 0, 0),
527 /* quaternion */
528 BNO055_CHANNEL(IIO_ROT, QUATERNION, BNO055_SCAN_QUATERNION,
529 BNO055_QUAT_DATA_W_LSB_REG, 0, 0, 0),
530
531 /* linear acceleration */
532 BNO055_CHANNEL(IIO_ACCEL, LINEAR_X, BNO055_SCAN_LIA_X,
533 BNO055_LIA_DATA_X_LSB_REG, 0, 0, 0),
534 BNO055_CHANNEL(IIO_ACCEL, LINEAR_Y, BNO055_SCAN_LIA_Y,
535 BNO055_LIA_DATA_Y_LSB_REG, 0, 0, 0),
536 BNO055_CHANNEL(IIO_ACCEL, LINEAR_Z, BNO055_SCAN_LIA_Z,
537 BNO055_LIA_DATA_Z_LSB_REG, 0, 0, 0),
538
539 /* gravity vector */
540 BNO055_CHANNEL(IIO_GRAVITY, X, BNO055_SCAN_GRAVITY_X,
541 BNO055_GRAVITY_DATA_X_LSB_REG, 0, 0, 0),
542 BNO055_CHANNEL(IIO_GRAVITY, Y, BNO055_SCAN_GRAVITY_Y,
543 BNO055_GRAVITY_DATA_Y_LSB_REG, 0, 0, 0),
544 BNO055_CHANNEL(IIO_GRAVITY, Z, BNO055_SCAN_GRAVITY_Z,
545 BNO055_GRAVITY_DATA_Z_LSB_REG, 0, 0, 0),
546
547 {
548 .type = IIO_TEMP,
549 .info_mask_separate = BIT(IIO_CHAN_INFO_PROCESSED),
550 .scan_index = -1,
551 },
552 IIO_CHAN_SOFT_TIMESTAMP(BNO055_SCAN_TIMESTAMP),
553 };
554
bno055_get_regmask(struct bno055_priv * priv,int * val,int * val2,int reg,int mask,struct bno055_sysfs_attr * attr)555 static int bno055_get_regmask(struct bno055_priv *priv, int *val, int *val2,
556 int reg, int mask, struct bno055_sysfs_attr *attr)
557 {
558 const int shift = __ffs(mask);
559 int hwval, idx;
560 int ret;
561 int i;
562
563 ret = regmap_read(priv->regmap, reg, &hwval);
564 if (ret)
565 return ret;
566
567 idx = (hwval & mask) >> shift;
568 if (attr->hw_xlate)
569 for (i = 0; i < attr->hw_xlate_len; i++)
570 if (attr->hw_xlate[i] == idx) {
571 idx = i;
572 break;
573 }
574 if (attr->type == IIO_VAL_INT) {
575 *val = attr->vals[idx];
576 } else { /* IIO_VAL_INT_PLUS_MICRO or IIO_VAL_FRACTIONAL */
577 *val = attr->vals[idx * 2];
578 *val2 = attr->vals[idx * 2 + 1];
579 }
580
581 return attr->type;
582 }
583
bno055_set_regmask(struct bno055_priv * priv,int val,int val2,int reg,int mask,struct bno055_sysfs_attr * attr)584 static int bno055_set_regmask(struct bno055_priv *priv, int val, int val2,
585 int reg, int mask, struct bno055_sysfs_attr *attr)
586 {
587 const int shift = __ffs(mask);
588 int best_delta;
589 int req_val;
590 int tbl_val;
591 bool first;
592 int delta;
593 int hwval;
594 int ret;
595 int len;
596 int i;
597
598 /*
599 * The closest value the HW supports is only one in fusion mode,
600 * and it is autoselected, so don't do anything, just return OK,
601 * as the closest possible value has been (virtually) selected
602 */
603 if (priv->operation_mode != BNO055_OPR_MODE_AMG)
604 return 0;
605
606 len = attr->len;
607
608 /*
609 * We always get a request in INT_PLUS_MICRO, but we
610 * take care of the micro part only when we really have
611 * non-integer tables. This prevents 32-bit overflow with
612 * larger integers contained in integer tables.
613 */
614 req_val = val;
615 if (attr->type != IIO_VAL_INT) {
616 len /= 2;
617 req_val = min(val, 2147) * 1000000 + val2;
618 }
619
620 first = true;
621 for (i = 0; i < len; i++) {
622 switch (attr->type) {
623 case IIO_VAL_INT:
624 tbl_val = attr->vals[i];
625 break;
626 case IIO_VAL_INT_PLUS_MICRO:
627 WARN_ON(attr->vals[i * 2] > 2147);
628 tbl_val = attr->vals[i * 2] * 1000000 +
629 attr->vals[i * 2 + 1];
630 break;
631 case IIO_VAL_FRACTIONAL:
632 WARN_ON(attr->vals[i * 2] > 4294);
633 tbl_val = attr->vals[i * 2] * 1000000 /
634 attr->vals[i * 2 + 1];
635 break;
636 default:
637 return -EINVAL;
638 }
639 delta = abs(tbl_val - req_val);
640 if (first || delta < best_delta) {
641 best_delta = delta;
642 hwval = i;
643 first = false;
644 }
645 }
646
647 if (attr->hw_xlate)
648 hwval = attr->hw_xlate[hwval];
649
650 ret = bno055_operation_mode_do_set(priv, BNO055_OPR_MODE_CONFIG);
651 if (ret)
652 return ret;
653
654 ret = regmap_update_bits(priv->regmap, reg, mask, hwval << shift);
655 if (ret)
656 return ret;
657
658 return bno055_operation_mode_do_set(priv, BNO055_OPR_MODE_AMG);
659 }
660
bno055_read_simple_chan(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int * val,int * val2,long mask)661 static int bno055_read_simple_chan(struct iio_dev *indio_dev,
662 struct iio_chan_spec const *chan,
663 int *val, int *val2, long mask)
664 {
665 struct bno055_priv *priv = iio_priv(indio_dev);
666 __le16 raw_val;
667 int ret;
668
669 switch (mask) {
670 case IIO_CHAN_INFO_RAW:
671 ret = regmap_bulk_read(priv->regmap, chan->address,
672 &raw_val, sizeof(raw_val));
673 if (ret < 0)
674 return ret;
675 *val = sign_extend32(le16_to_cpu(raw_val), 15);
676 return IIO_VAL_INT;
677 case IIO_CHAN_INFO_OFFSET:
678 if (priv->operation_mode != BNO055_OPR_MODE_AMG) {
679 *val = 0;
680 } else {
681 ret = regmap_bulk_read(priv->regmap,
682 chan->address +
683 BNO055_REG_OFFSET_ADDR,
684 &raw_val, sizeof(raw_val));
685 if (ret < 0)
686 return ret;
687 /*
688 * IMU reports sensor offsets; IIO wants correction
689 * offsets, thus we need the 'minus' here.
690 */
691 *val = -sign_extend32(le16_to_cpu(raw_val), 15);
692 }
693 return IIO_VAL_INT;
694 case IIO_CHAN_INFO_SCALE:
695 *val = 1;
696 switch (chan->type) {
697 case IIO_GRAVITY:
698 /* Table 3-35: 1 m/s^2 = 100 LSB */
699 case IIO_ACCEL:
700 /* Table 3-17: 1 m/s^2 = 100 LSB */
701 *val2 = 100;
702 break;
703 case IIO_MAGN:
704 /*
705 * Table 3-19: 1 uT = 16 LSB. But we need
706 * Gauss: 1G = 0.1 uT.
707 */
708 *val2 = 160;
709 break;
710 case IIO_ANGL_VEL:
711 /*
712 * Table 3-22: 1 Rps = 900 LSB
713 * .. but this is not exactly true. See comment at the
714 * beginning of this file.
715 */
716 if (priv->operation_mode != BNO055_OPR_MODE_AMG) {
717 *val = bno055_gyr_scale.fusion_vals[0];
718 *val2 = bno055_gyr_scale.fusion_vals[1];
719 return IIO_VAL_FRACTIONAL;
720 }
721
722 return bno055_get_regmask(priv, val, val2,
723 BNO055_GYR_CONFIG_REG,
724 BNO055_GYR_CONFIG_RANGE_MASK,
725 &bno055_gyr_scale);
726 break;
727 case IIO_ROT:
728 /* Table 3-28: 1 degree = 16 LSB */
729 *val2 = 16;
730 break;
731 default:
732 return -EINVAL;
733 }
734 return IIO_VAL_FRACTIONAL;
735
736 case IIO_CHAN_INFO_SAMP_FREQ:
737 if (chan->type != IIO_MAGN)
738 return -EINVAL;
739
740 return bno055_get_regmask(priv, val, val2,
741 BNO055_MAG_CONFIG_REG,
742 BNO055_MAG_CONFIG_ODR_MASK,
743 &bno055_mag_odr);
744
745 case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY:
746 switch (chan->type) {
747 case IIO_ANGL_VEL:
748 return bno055_get_regmask(priv, val, val2,
749 BNO055_GYR_CONFIG_REG,
750 BNO055_GYR_CONFIG_LPF_MASK,
751 &bno055_gyr_lpf);
752 case IIO_ACCEL:
753 return bno055_get_regmask(priv, val, val2,
754 BNO055_ACC_CONFIG_REG,
755 BNO055_ACC_CONFIG_LPF_MASK,
756 &bno055_acc_lpf);
757 default:
758 return -EINVAL;
759 }
760
761 default:
762 return -EINVAL;
763 }
764 }
765
bno055_sysfs_attr_avail(struct bno055_priv * priv,struct bno055_sysfs_attr * attr,const int ** vals,int * length)766 static int bno055_sysfs_attr_avail(struct bno055_priv *priv, struct bno055_sysfs_attr *attr,
767 const int **vals, int *length)
768 {
769 if (priv->operation_mode != BNO055_OPR_MODE_AMG) {
770 /* locked when fusion enabled */
771 *vals = attr->fusion_vals;
772 if (attr->type == IIO_VAL_INT)
773 *length = 1;
774 else
775 *length = 2; /* IIO_VAL_INT_PLUS_MICRO or IIO_VAL_FRACTIONAL*/
776 } else {
777 *vals = attr->vals;
778 *length = attr->len;
779 }
780
781 return attr->type;
782 }
783
bno055_read_avail(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,const int ** vals,int * type,int * length,long mask)784 static int bno055_read_avail(struct iio_dev *indio_dev,
785 struct iio_chan_spec const *chan,
786 const int **vals, int *type, int *length,
787 long mask)
788 {
789 struct bno055_priv *priv = iio_priv(indio_dev);
790
791 switch (mask) {
792 case IIO_CHAN_INFO_SCALE:
793 switch (chan->type) {
794 case IIO_ANGL_VEL:
795 *type = bno055_sysfs_attr_avail(priv, &bno055_gyr_scale,
796 vals, length);
797 return IIO_AVAIL_LIST;
798 default:
799 return -EINVAL;
800 }
801 case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY:
802 switch (chan->type) {
803 case IIO_ANGL_VEL:
804 *type = bno055_sysfs_attr_avail(priv, &bno055_gyr_lpf,
805 vals, length);
806 return IIO_AVAIL_LIST;
807 case IIO_ACCEL:
808 *type = bno055_sysfs_attr_avail(priv, &bno055_acc_lpf,
809 vals, length);
810 return IIO_AVAIL_LIST;
811 default:
812 return -EINVAL;
813 }
814
815 break;
816 case IIO_CHAN_INFO_SAMP_FREQ:
817 switch (chan->type) {
818 case IIO_MAGN:
819 *type = bno055_sysfs_attr_avail(priv, &bno055_mag_odr,
820 vals, length);
821 return IIO_AVAIL_LIST;
822 default:
823 return -EINVAL;
824 }
825 default:
826 return -EINVAL;
827 }
828 }
829
bno055_read_temp_chan(struct iio_dev * indio_dev,int * val)830 static int bno055_read_temp_chan(struct iio_dev *indio_dev, int *val)
831 {
832 struct bno055_priv *priv = iio_priv(indio_dev);
833 unsigned int raw_val;
834 int ret;
835
836 ret = regmap_read(priv->regmap, BNO055_TEMP_REG, &raw_val);
837 if (ret < 0)
838 return ret;
839
840 /*
841 * Tables 3-36 and 3-37: one byte of priv, signed, 1 LSB = 1C.
842 * ABI wants milliC.
843 */
844 *val = raw_val * 1000;
845
846 return IIO_VAL_INT;
847 }
848
bno055_read_quaternion(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int size,int * vals,int * val_len,long mask)849 static int bno055_read_quaternion(struct iio_dev *indio_dev,
850 struct iio_chan_spec const *chan,
851 int size, int *vals, int *val_len,
852 long mask)
853 {
854 struct bno055_priv *priv = iio_priv(indio_dev);
855 __le16 raw_vals[4];
856 int i, ret;
857
858 switch (mask) {
859 case IIO_CHAN_INFO_RAW:
860 if (size < 4)
861 return -EINVAL;
862 ret = regmap_bulk_read(priv->regmap,
863 BNO055_QUAT_DATA_W_LSB_REG,
864 raw_vals, sizeof(raw_vals));
865 if (ret < 0)
866 return ret;
867 for (i = 0; i < 4; i++)
868 vals[i] = sign_extend32(le16_to_cpu(raw_vals[i]), 15);
869 *val_len = 4;
870 return IIO_VAL_INT_MULTIPLE;
871 case IIO_CHAN_INFO_SCALE:
872 /* Table 3-31: 1 quaternion = 2^14 LSB */
873 if (size < 2)
874 return -EINVAL;
875 vals[0] = 1;
876 vals[1] = 14;
877 return IIO_VAL_FRACTIONAL_LOG2;
878 default:
879 return -EINVAL;
880 }
881 }
882
bno055_is_chan_readable(struct iio_dev * indio_dev,struct iio_chan_spec const * chan)883 static bool bno055_is_chan_readable(struct iio_dev *indio_dev,
884 struct iio_chan_spec const *chan)
885 {
886 struct bno055_priv *priv = iio_priv(indio_dev);
887
888 if (priv->operation_mode != BNO055_OPR_MODE_AMG)
889 return true;
890
891 switch (chan->type) {
892 case IIO_GRAVITY:
893 case IIO_ROT:
894 return false;
895 case IIO_ACCEL:
896 if (chan->channel2 == IIO_MOD_LINEAR_X ||
897 chan->channel2 == IIO_MOD_LINEAR_Y ||
898 chan->channel2 == IIO_MOD_LINEAR_Z)
899 return false;
900 return true;
901 default:
902 return true;
903 }
904 }
905
_bno055_read_raw_multi(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int size,int * vals,int * val_len,long mask)906 static int _bno055_read_raw_multi(struct iio_dev *indio_dev,
907 struct iio_chan_spec const *chan,
908 int size, int *vals, int *val_len,
909 long mask)
910 {
911 if (!bno055_is_chan_readable(indio_dev, chan))
912 return -EBUSY;
913
914 switch (chan->type) {
915 case IIO_MAGN:
916 case IIO_ACCEL:
917 case IIO_ANGL_VEL:
918 case IIO_GRAVITY:
919 if (size < 2)
920 return -EINVAL;
921 *val_len = 2;
922 return bno055_read_simple_chan(indio_dev, chan,
923 &vals[0], &vals[1],
924 mask);
925 case IIO_TEMP:
926 *val_len = 1;
927 return bno055_read_temp_chan(indio_dev, &vals[0]);
928 case IIO_ROT:
929 /*
930 * Rotation is exposed as either a quaternion or three
931 * Euler angles.
932 */
933 if (chan->channel2 == IIO_MOD_QUATERNION)
934 return bno055_read_quaternion(indio_dev, chan,
935 size, vals,
936 val_len, mask);
937 if (size < 2)
938 return -EINVAL;
939 *val_len = 2;
940 return bno055_read_simple_chan(indio_dev, chan,
941 &vals[0], &vals[1],
942 mask);
943 default:
944 return -EINVAL;
945 }
946 }
947
bno055_read_raw_multi(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int size,int * vals,int * val_len,long mask)948 static int bno055_read_raw_multi(struct iio_dev *indio_dev,
949 struct iio_chan_spec const *chan,
950 int size, int *vals, int *val_len,
951 long mask)
952 {
953 struct bno055_priv *priv = iio_priv(indio_dev);
954 int ret;
955
956 mutex_lock(&priv->lock);
957 ret = _bno055_read_raw_multi(indio_dev, chan, size,
958 vals, val_len, mask);
959 mutex_unlock(&priv->lock);
960 return ret;
961 }
962
_bno055_write_raw(struct iio_dev * iio_dev,struct iio_chan_spec const * chan,int val,int val2,long mask)963 static int _bno055_write_raw(struct iio_dev *iio_dev,
964 struct iio_chan_spec const *chan,
965 int val, int val2, long mask)
966 {
967 struct bno055_priv *priv = iio_priv(iio_dev);
968
969 switch (chan->type) {
970 case IIO_MAGN:
971 switch (mask) {
972 case IIO_CHAN_INFO_SAMP_FREQ:
973 return bno055_set_regmask(priv, val, val2,
974 BNO055_MAG_CONFIG_REG,
975 BNO055_MAG_CONFIG_ODR_MASK,
976 &bno055_mag_odr);
977 default:
978 return -EINVAL;
979 }
980 case IIO_ACCEL:
981 switch (mask) {
982 case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY:
983 return bno055_set_regmask(priv, val, val2,
984 BNO055_ACC_CONFIG_REG,
985 BNO055_ACC_CONFIG_LPF_MASK,
986 &bno055_acc_lpf);
987
988 default:
989 return -EINVAL;
990 }
991 case IIO_ANGL_VEL:
992 switch (mask) {
993 case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY:
994 return bno055_set_regmask(priv, val, val2,
995 BNO055_GYR_CONFIG_REG,
996 BNO055_GYR_CONFIG_LPF_MASK,
997 &bno055_gyr_lpf);
998 case IIO_CHAN_INFO_SCALE:
999 return bno055_set_regmask(priv, val, val2,
1000 BNO055_GYR_CONFIG_REG,
1001 BNO055_GYR_CONFIG_RANGE_MASK,
1002 &bno055_gyr_scale);
1003 default:
1004 return -EINVAL;
1005 }
1006 default:
1007 return -EINVAL;
1008 }
1009 }
1010
bno055_write_raw(struct iio_dev * iio_dev,struct iio_chan_spec const * chan,int val,int val2,long mask)1011 static int bno055_write_raw(struct iio_dev *iio_dev,
1012 struct iio_chan_spec const *chan,
1013 int val, int val2, long mask)
1014 {
1015 struct bno055_priv *priv = iio_priv(iio_dev);
1016 int ret;
1017
1018 mutex_lock(&priv->lock);
1019 ret = _bno055_write_raw(iio_dev, chan, val, val2, mask);
1020 mutex_unlock(&priv->lock);
1021
1022 return ret;
1023 }
1024
in_accel_range_raw_available_show(struct device * dev,struct device_attribute * attr,char * buf)1025 static ssize_t in_accel_range_raw_available_show(struct device *dev,
1026 struct device_attribute *attr,
1027 char *buf)
1028 {
1029 struct bno055_priv *priv = iio_priv(dev_to_iio_dev(dev));
1030 int len = 0;
1031 int i;
1032
1033 if (priv->operation_mode != BNO055_OPR_MODE_AMG)
1034 return sysfs_emit(buf, "%d\n", bno055_acc_range.fusion_vals[0]);
1035
1036 for (i = 0; i < bno055_acc_range.len; i++)
1037 len += sysfs_emit_at(buf, len, "%d ", bno055_acc_range.vals[i]);
1038 buf[len - 1] = '\n';
1039
1040 return len;
1041 }
1042
fusion_enable_show(struct device * dev,struct device_attribute * attr,char * buf)1043 static ssize_t fusion_enable_show(struct device *dev,
1044 struct device_attribute *attr,
1045 char *buf)
1046 {
1047 struct bno055_priv *priv = iio_priv(dev_to_iio_dev(dev));
1048
1049 return sysfs_emit(buf, "%d\n",
1050 priv->operation_mode != BNO055_OPR_MODE_AMG);
1051 }
1052
fusion_enable_store(struct device * dev,struct device_attribute * attr,const char * buf,size_t len)1053 static ssize_t fusion_enable_store(struct device *dev,
1054 struct device_attribute *attr,
1055 const char *buf, size_t len)
1056 {
1057 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
1058 struct bno055_priv *priv = iio_priv(indio_dev);
1059 bool en;
1060 int ret;
1061
1062 if (indio_dev->active_scan_mask &&
1063 !bitmap_empty(indio_dev->active_scan_mask, _BNO055_SCAN_MAX))
1064 return -EBUSY;
1065
1066 ret = kstrtobool(buf, &en);
1067 if (ret)
1068 return -EINVAL;
1069
1070 if (!en)
1071 return bno055_operation_mode_set(priv, BNO055_OPR_MODE_AMG) ?: len;
1072
1073 /*
1074 * Coming from AMG means the FMC was off, just switch to fusion but
1075 * don't change anything that doesn't belong to us (i.e let FMC stay off).
1076 * Coming from any other fusion mode means we don't need to do anything.
1077 */
1078 if (priv->operation_mode == BNO055_OPR_MODE_AMG)
1079 return bno055_operation_mode_set(priv, BNO055_OPR_MODE_FUSION_FMC_OFF) ?: len;
1080
1081 return len;
1082 }
1083
in_magn_calibration_fast_enable_show(struct device * dev,struct device_attribute * attr,char * buf)1084 static ssize_t in_magn_calibration_fast_enable_show(struct device *dev,
1085 struct device_attribute *attr,
1086 char *buf)
1087 {
1088 struct bno055_priv *priv = iio_priv(dev_to_iio_dev(dev));
1089
1090 return sysfs_emit(buf, "%d\n",
1091 priv->operation_mode == BNO055_OPR_MODE_FUSION);
1092 }
1093
in_magn_calibration_fast_enable_store(struct device * dev,struct device_attribute * attr,const char * buf,size_t len)1094 static ssize_t in_magn_calibration_fast_enable_store(struct device *dev,
1095 struct device_attribute *attr,
1096 const char *buf, size_t len)
1097 {
1098 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
1099 struct bno055_priv *priv = iio_priv(indio_dev);
1100 int ret;
1101
1102 if (indio_dev->active_scan_mask &&
1103 !bitmap_empty(indio_dev->active_scan_mask, _BNO055_SCAN_MAX))
1104 return -EBUSY;
1105
1106 if (sysfs_streq(buf, "0")) {
1107 if (priv->operation_mode == BNO055_OPR_MODE_FUSION) {
1108 ret = bno055_operation_mode_set(priv, BNO055_OPR_MODE_FUSION_FMC_OFF);
1109 if (ret)
1110 return ret;
1111 }
1112 } else {
1113 if (priv->operation_mode == BNO055_OPR_MODE_AMG)
1114 return -EINVAL;
1115
1116 if (priv->operation_mode != BNO055_OPR_MODE_FUSION) {
1117 ret = bno055_operation_mode_set(priv, BNO055_OPR_MODE_FUSION);
1118 if (ret)
1119 return ret;
1120 }
1121 }
1122
1123 return len;
1124 }
1125
in_accel_range_raw_show(struct device * dev,struct device_attribute * attr,char * buf)1126 static ssize_t in_accel_range_raw_show(struct device *dev,
1127 struct device_attribute *attr,
1128 char *buf)
1129 {
1130 struct bno055_priv *priv = iio_priv(dev_to_iio_dev(dev));
1131 int val;
1132 int ret;
1133
1134 ret = bno055_get_regmask(priv, &val, NULL,
1135 BNO055_ACC_CONFIG_REG,
1136 BNO055_ACC_CONFIG_RANGE_MASK,
1137 &bno055_acc_range);
1138 if (ret < 0)
1139 return ret;
1140
1141 return sysfs_emit(buf, "%d\n", val);
1142 }
1143
in_accel_range_raw_store(struct device * dev,struct device_attribute * attr,const char * buf,size_t len)1144 static ssize_t in_accel_range_raw_store(struct device *dev,
1145 struct device_attribute *attr,
1146 const char *buf, size_t len)
1147 {
1148 struct bno055_priv *priv = iio_priv(dev_to_iio_dev(dev));
1149 unsigned long val;
1150 int ret;
1151
1152 ret = kstrtoul(buf, 10, &val);
1153 if (ret)
1154 return ret;
1155
1156 mutex_lock(&priv->lock);
1157 ret = bno055_set_regmask(priv, val, 0,
1158 BNO055_ACC_CONFIG_REG,
1159 BNO055_ACC_CONFIG_RANGE_MASK,
1160 &bno055_acc_range);
1161 mutex_unlock(&priv->lock);
1162
1163 return ret ?: len;
1164 }
1165
bno055_get_calib_status(struct device * dev,char * buf,int which)1166 static ssize_t bno055_get_calib_status(struct device *dev, char *buf, int which)
1167 {
1168 struct bno055_priv *priv = iio_priv(dev_to_iio_dev(dev));
1169 int calib;
1170 int ret;
1171 int val;
1172
1173 if (priv->operation_mode == BNO055_OPR_MODE_AMG ||
1174 (priv->operation_mode == BNO055_OPR_MODE_FUSION_FMC_OFF &&
1175 which == BNO055_CALIB_STAT_MAGN_SHIFT)) {
1176 calib = 0;
1177 } else {
1178 mutex_lock(&priv->lock);
1179 ret = regmap_read(priv->regmap, BNO055_CALIB_STAT_REG, &val);
1180 mutex_unlock(&priv->lock);
1181
1182 if (ret)
1183 return -EIO;
1184
1185 calib = ((val >> which) & GENMASK(1, 0)) + 1;
1186 }
1187
1188 return sysfs_emit(buf, "%d\n", calib);
1189 }
1190
serialnumber_show(struct device * dev,struct device_attribute * attr,char * buf)1191 static ssize_t serialnumber_show(struct device *dev,
1192 struct device_attribute *attr,
1193 char *buf)
1194 {
1195 struct bno055_priv *priv = iio_priv(dev_to_iio_dev(dev));
1196
1197 return sysfs_emit(buf, "%*ph\n", BNO055_UID_LEN, priv->uid);
1198 }
1199
calibration_data_read(struct file * filp,struct kobject * kobj,struct bin_attribute * bin_attr,char * buf,loff_t pos,size_t count)1200 static ssize_t calibration_data_read(struct file *filp, struct kobject *kobj,
1201 struct bin_attribute *bin_attr, char *buf,
1202 loff_t pos, size_t count)
1203 {
1204 struct bno055_priv *priv = iio_priv(dev_to_iio_dev(kobj_to_dev(kobj)));
1205 u8 data[BNO055_CALDATA_LEN];
1206 int ret;
1207
1208 /*
1209 * Calibration data is volatile; reading it in chunks will possibly
1210 * results in inconsistent data. We require the user to read the whole
1211 * blob in a single chunk
1212 */
1213 if (count < BNO055_CALDATA_LEN || pos)
1214 return -EINVAL;
1215
1216 mutex_lock(&priv->lock);
1217 ret = bno055_operation_mode_do_set(priv, BNO055_OPR_MODE_CONFIG);
1218 if (ret)
1219 goto exit_unlock;
1220
1221 ret = regmap_bulk_read(priv->regmap, BNO055_CALDATA_START, data,
1222 BNO055_CALDATA_LEN);
1223 if (ret)
1224 goto exit_unlock;
1225
1226 ret = bno055_operation_mode_do_set(priv, priv->operation_mode);
1227 if (ret)
1228 goto exit_unlock;
1229
1230 memcpy(buf, data, BNO055_CALDATA_LEN);
1231
1232 ret = BNO055_CALDATA_LEN;
1233 exit_unlock:
1234 mutex_unlock(&priv->lock);
1235 return ret;
1236 }
1237
sys_calibration_auto_status_show(struct device * dev,struct device_attribute * a,char * buf)1238 static ssize_t sys_calibration_auto_status_show(struct device *dev,
1239 struct device_attribute *a,
1240 char *buf)
1241 {
1242 return bno055_get_calib_status(dev, buf, BNO055_CALIB_STAT_SYS_SHIFT);
1243 }
1244
in_accel_calibration_auto_status_show(struct device * dev,struct device_attribute * a,char * buf)1245 static ssize_t in_accel_calibration_auto_status_show(struct device *dev,
1246 struct device_attribute *a,
1247 char *buf)
1248 {
1249 return bno055_get_calib_status(dev, buf, BNO055_CALIB_STAT_ACCEL_SHIFT);
1250 }
1251
in_gyro_calibration_auto_status_show(struct device * dev,struct device_attribute * a,char * buf)1252 static ssize_t in_gyro_calibration_auto_status_show(struct device *dev,
1253 struct device_attribute *a,
1254 char *buf)
1255 {
1256 return bno055_get_calib_status(dev, buf, BNO055_CALIB_STAT_GYRO_SHIFT);
1257 }
1258
in_magn_calibration_auto_status_show(struct device * dev,struct device_attribute * a,char * buf)1259 static ssize_t in_magn_calibration_auto_status_show(struct device *dev,
1260 struct device_attribute *a,
1261 char *buf)
1262 {
1263 return bno055_get_calib_status(dev, buf, BNO055_CALIB_STAT_MAGN_SHIFT);
1264 }
1265
bno055_debugfs_reg_access(struct iio_dev * iio_dev,unsigned int reg,unsigned int writeval,unsigned int * readval)1266 static int bno055_debugfs_reg_access(struct iio_dev *iio_dev, unsigned int reg,
1267 unsigned int writeval, unsigned int *readval)
1268 {
1269 struct bno055_priv *priv = iio_priv(iio_dev);
1270
1271 if (readval)
1272 return regmap_read(priv->regmap, reg, readval);
1273 else
1274 return regmap_write(priv->regmap, reg, writeval);
1275 }
1276
bno055_show_fw_version(struct file * file,char __user * userbuf,size_t count,loff_t * ppos)1277 static ssize_t bno055_show_fw_version(struct file *file, char __user *userbuf,
1278 size_t count, loff_t *ppos)
1279 {
1280 struct bno055_priv *priv = file->private_data;
1281 int rev, ver;
1282 char *buf;
1283 int ret;
1284
1285 ret = regmap_read(priv->regmap, BNO055_SW_REV_LSB_REG, &rev);
1286 if (ret)
1287 return ret;
1288
1289 ret = regmap_read(priv->regmap, BNO055_SW_REV_MSB_REG, &ver);
1290 if (ret)
1291 return ret;
1292
1293 buf = kasprintf(GFP_KERNEL, "ver: 0x%x, rev: 0x%x\n", ver, rev);
1294 if (!buf)
1295 return -ENOMEM;
1296
1297 ret = simple_read_from_buffer(userbuf, count, ppos, buf, strlen(buf));
1298 kfree(buf);
1299
1300 return ret;
1301 }
1302
1303 static const struct file_operations bno055_fw_version_ops = {
1304 .open = simple_open,
1305 .read = bno055_show_fw_version,
1306 .llseek = default_llseek,
1307 .owner = THIS_MODULE,
1308 };
1309
bno055_debugfs_remove(void * _priv)1310 static void bno055_debugfs_remove(void *_priv)
1311 {
1312 struct bno055_priv *priv = _priv;
1313
1314 debugfs_remove(priv->debugfs);
1315 priv->debugfs = NULL;
1316 }
1317
bno055_debugfs_init(struct iio_dev * iio_dev)1318 static void bno055_debugfs_init(struct iio_dev *iio_dev)
1319 {
1320 struct bno055_priv *priv = iio_priv(iio_dev);
1321
1322 priv->debugfs = debugfs_create_file("firmware_version", 0400,
1323 iio_get_debugfs_dentry(iio_dev),
1324 priv, &bno055_fw_version_ops);
1325 if (!IS_ERR(priv->debugfs))
1326 devm_add_action_or_reset(priv->dev, bno055_debugfs_remove,
1327 priv);
1328 if (IS_ERR_OR_NULL(priv->debugfs))
1329 dev_warn(priv->dev, "failed to setup debugfs");
1330 }
1331
1332 static IIO_DEVICE_ATTR_RW(fusion_enable, 0);
1333 static IIO_DEVICE_ATTR_RW(in_magn_calibration_fast_enable, 0);
1334 static IIO_DEVICE_ATTR_RW(in_accel_range_raw, 0);
1335
1336 static IIO_DEVICE_ATTR_RO(in_accel_range_raw_available, 0);
1337 static IIO_DEVICE_ATTR_RO(sys_calibration_auto_status, 0);
1338 static IIO_DEVICE_ATTR_RO(in_accel_calibration_auto_status, 0);
1339 static IIO_DEVICE_ATTR_RO(in_gyro_calibration_auto_status, 0);
1340 static IIO_DEVICE_ATTR_RO(in_magn_calibration_auto_status, 0);
1341 static IIO_DEVICE_ATTR_RO(serialnumber, 0);
1342
1343 static struct attribute *bno055_attrs[] = {
1344 &iio_dev_attr_in_accel_range_raw_available.dev_attr.attr,
1345 &iio_dev_attr_in_accel_range_raw.dev_attr.attr,
1346 &iio_dev_attr_fusion_enable.dev_attr.attr,
1347 &iio_dev_attr_in_magn_calibration_fast_enable.dev_attr.attr,
1348 &iio_dev_attr_sys_calibration_auto_status.dev_attr.attr,
1349 &iio_dev_attr_in_accel_calibration_auto_status.dev_attr.attr,
1350 &iio_dev_attr_in_gyro_calibration_auto_status.dev_attr.attr,
1351 &iio_dev_attr_in_magn_calibration_auto_status.dev_attr.attr,
1352 &iio_dev_attr_serialnumber.dev_attr.attr,
1353 NULL
1354 };
1355
1356 static BIN_ATTR_RO(calibration_data, BNO055_CALDATA_LEN);
1357
1358 static struct bin_attribute *bno055_bin_attrs[] = {
1359 &bin_attr_calibration_data,
1360 NULL
1361 };
1362
1363 static const struct attribute_group bno055_attrs_group = {
1364 .attrs = bno055_attrs,
1365 .bin_attrs = bno055_bin_attrs,
1366 };
1367
1368 static const struct iio_info bno055_info = {
1369 .read_raw_multi = bno055_read_raw_multi,
1370 .read_avail = bno055_read_avail,
1371 .write_raw = bno055_write_raw,
1372 .attrs = &bno055_attrs_group,
1373 .debugfs_reg_access = bno055_debugfs_reg_access,
1374 };
1375
1376 /*
1377 * Reads len samples from the HW, stores them in buf starting from buf_idx,
1378 * and applies mask to cull (skip) unneeded samples.
1379 * Updates buf_idx incrementing with the number of stored samples.
1380 * Samples from HW are transferred into buf, then in-place copy on buf is
1381 * performed in order to cull samples that need to be skipped.
1382 * This avoids copies of the first samples until we hit the 1st sample to skip,
1383 * and also avoids having an extra bounce buffer.
1384 * buf must be able to contain len elements in spite of how many samples we are
1385 * going to cull.
1386 */
bno055_scan_xfer(struct bno055_priv * priv,int start_ch,int len,unsigned long mask,__le16 * buf,int * buf_idx)1387 static int bno055_scan_xfer(struct bno055_priv *priv,
1388 int start_ch, int len, unsigned long mask,
1389 __le16 *buf, int *buf_idx)
1390 {
1391 const int base = BNO055_ACC_DATA_X_LSB_REG;
1392 bool quat_in_read = false;
1393 int buf_base = *buf_idx;
1394 __le16 *dst, *src;
1395 int offs_fixup = 0;
1396 int xfer_len = len;
1397 int ret;
1398 int i, n;
1399
1400 if (!mask)
1401 return 0;
1402
1403 /*
1404 * All channels are made up 1 16-bit sample, except for quaternion that
1405 * is made up 4 16-bit values.
1406 * For us the quaternion CH is just like 4 regular CHs.
1407 * If our read starts past the quaternion make sure to adjust the
1408 * starting offset; if the quaternion is contained in our scan then make
1409 * sure to adjust the read len.
1410 */
1411 if (start_ch > BNO055_SCAN_QUATERNION) {
1412 start_ch += 3;
1413 } else if ((start_ch <= BNO055_SCAN_QUATERNION) &&
1414 ((start_ch + len) > BNO055_SCAN_QUATERNION)) {
1415 quat_in_read = true;
1416 xfer_len += 3;
1417 }
1418
1419 ret = regmap_bulk_read(priv->regmap,
1420 base + start_ch * sizeof(__le16),
1421 buf + buf_base,
1422 xfer_len * sizeof(__le16));
1423 if (ret)
1424 return ret;
1425
1426 for_each_set_bit(i, &mask, len) {
1427 if (quat_in_read && ((start_ch + i) > BNO055_SCAN_QUATERNION))
1428 offs_fixup = 3;
1429
1430 dst = buf + *buf_idx;
1431 src = buf + buf_base + offs_fixup + i;
1432
1433 n = (start_ch + i == BNO055_SCAN_QUATERNION) ? 4 : 1;
1434
1435 if (dst != src)
1436 memcpy(dst, src, n * sizeof(__le16));
1437
1438 *buf_idx += n;
1439 }
1440 return 0;
1441 }
1442
bno055_trigger_handler(int irq,void * p)1443 static irqreturn_t bno055_trigger_handler(int irq, void *p)
1444 {
1445 struct iio_poll_func *pf = p;
1446 struct iio_dev *iio_dev = pf->indio_dev;
1447 struct bno055_priv *priv = iio_priv(iio_dev);
1448 int xfer_start, start, end, prev_end;
1449 unsigned long mask;
1450 int quat_extra_len;
1451 bool first = true;
1452 int buf_idx = 0;
1453 bool thr_hit;
1454 int ret;
1455
1456 mutex_lock(&priv->lock);
1457
1458 /*
1459 * Walk the bitmap and eventually perform several transfers.
1460 * Bitmap ones-fields that are separated by gaps <= xfer_burst_break_thr
1461 * will be included in same transfer.
1462 * Every time the bitmap contains a gap wider than xfer_burst_break_thr
1463 * then we split the transfer, skipping the gap.
1464 */
1465 for_each_set_bitrange(start, end, iio_dev->active_scan_mask,
1466 iio_get_masklength(iio_dev)) {
1467 /*
1468 * First transfer will start from the beginning of the first
1469 * ones-field in the bitmap
1470 */
1471 if (first) {
1472 xfer_start = start;
1473 } else {
1474 /*
1475 * We found the next ones-field; check whether to
1476 * include it in * the current transfer or not (i.e.
1477 * let's perform the current * transfer and prepare for
1478 * another one).
1479 */
1480
1481 /*
1482 * In case the zeros-gap contains the quaternion bit,
1483 * then its length is actually 4 words instead of 1
1484 * (i.e. +3 wrt other channels).
1485 */
1486 quat_extra_len = ((start > BNO055_SCAN_QUATERNION) &&
1487 (prev_end <= BNO055_SCAN_QUATERNION)) ? 3 : 0;
1488
1489 /* If the gap is wider than xfer_burst_break_thr then.. */
1490 thr_hit = (start - prev_end + quat_extra_len) >
1491 priv->xfer_burst_break_thr;
1492
1493 /*
1494 * .. transfer all the data up to the gap. Then set the
1495 * next transfer start index at right after the gap
1496 * (i.e. at the start of this ones-field).
1497 */
1498 if (thr_hit) {
1499 mask = *iio_dev->active_scan_mask >> xfer_start;
1500 ret = bno055_scan_xfer(priv, xfer_start,
1501 prev_end - xfer_start,
1502 mask, priv->buf.chans, &buf_idx);
1503 if (ret)
1504 goto done;
1505 xfer_start = start;
1506 }
1507 }
1508 first = false;
1509 prev_end = end;
1510 }
1511
1512 /*
1513 * We finished walking the bitmap; no more gaps to check for. Just
1514 * perform the current transfer.
1515 */
1516 mask = *iio_dev->active_scan_mask >> xfer_start;
1517 ret = bno055_scan_xfer(priv, xfer_start,
1518 prev_end - xfer_start,
1519 mask, priv->buf.chans, &buf_idx);
1520
1521 if (!ret)
1522 iio_push_to_buffers_with_timestamp(iio_dev,
1523 &priv->buf, pf->timestamp);
1524 done:
1525 mutex_unlock(&priv->lock);
1526 iio_trigger_notify_done(iio_dev->trig);
1527 return IRQ_HANDLED;
1528 }
1529
bno055_buffer_preenable(struct iio_dev * indio_dev)1530 static int bno055_buffer_preenable(struct iio_dev *indio_dev)
1531 {
1532 struct bno055_priv *priv = iio_priv(indio_dev);
1533 const unsigned long fusion_mask =
1534 BIT(BNO055_SCAN_YAW) |
1535 BIT(BNO055_SCAN_ROLL) |
1536 BIT(BNO055_SCAN_PITCH) |
1537 BIT(BNO055_SCAN_QUATERNION) |
1538 BIT(BNO055_SCAN_LIA_X) |
1539 BIT(BNO055_SCAN_LIA_Y) |
1540 BIT(BNO055_SCAN_LIA_Z) |
1541 BIT(BNO055_SCAN_GRAVITY_X) |
1542 BIT(BNO055_SCAN_GRAVITY_Y) |
1543 BIT(BNO055_SCAN_GRAVITY_Z);
1544
1545 if (priv->operation_mode == BNO055_OPR_MODE_AMG &&
1546 bitmap_intersects(indio_dev->active_scan_mask, &fusion_mask,
1547 _BNO055_SCAN_MAX))
1548 return -EBUSY;
1549 return 0;
1550 }
1551
1552 static const struct iio_buffer_setup_ops bno055_buffer_setup_ops = {
1553 .preenable = bno055_buffer_preenable,
1554 };
1555
bno055_probe(struct device * dev,struct regmap * regmap,int xfer_burst_break_thr,bool sw_reset)1556 int bno055_probe(struct device *dev, struct regmap *regmap,
1557 int xfer_burst_break_thr, bool sw_reset)
1558 {
1559 const struct firmware *caldata = NULL;
1560 struct bno055_priv *priv;
1561 struct iio_dev *iio_dev;
1562 char *fw_name_buf;
1563 unsigned int val;
1564 int rev, ver;
1565 int ret;
1566
1567 iio_dev = devm_iio_device_alloc(dev, sizeof(*priv));
1568 if (!iio_dev)
1569 return -ENOMEM;
1570
1571 iio_dev->name = "bno055";
1572 priv = iio_priv(iio_dev);
1573 mutex_init(&priv->lock);
1574 priv->regmap = regmap;
1575 priv->dev = dev;
1576 priv->xfer_burst_break_thr = xfer_burst_break_thr;
1577 priv->sw_reset = sw_reset;
1578
1579 priv->reset_gpio = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW);
1580 if (IS_ERR(priv->reset_gpio))
1581 return dev_err_probe(dev, PTR_ERR(priv->reset_gpio), "Failed to get reset GPIO\n");
1582
1583 priv->clk = devm_clk_get_optional_enabled(dev, "clk");
1584 if (IS_ERR(priv->clk))
1585 return dev_err_probe(dev, PTR_ERR(priv->clk), "Failed to get CLK\n");
1586
1587 if (priv->reset_gpio) {
1588 usleep_range(5000, 10000);
1589 gpiod_set_value_cansleep(priv->reset_gpio, 1);
1590 usleep_range(650000, 750000);
1591 } else if (!sw_reset) {
1592 dev_warn(dev, "No usable reset method; IMU may be unreliable\n");
1593 }
1594
1595 ret = regmap_read(priv->regmap, BNO055_CHIP_ID_REG, &val);
1596 if (ret)
1597 return ret;
1598
1599 if (val != BNO055_CHIP_ID_MAGIC)
1600 dev_warn(dev, "Unrecognized chip ID 0x%x\n", val);
1601
1602 /*
1603 * In case we haven't a HW reset pin, we can still reset the chip via
1604 * register write. This is probably nonsense in case we can't even
1605 * communicate with the chip or the chip isn't the one we expect (i.e.
1606 * we don't write to unknown chips), so we perform SW reset only after
1607 * chip magic ID check
1608 */
1609 if (!priv->reset_gpio) {
1610 ret = bno055_system_reset(priv);
1611 if (ret)
1612 return ret;
1613 }
1614
1615 ret = regmap_read(priv->regmap, BNO055_SW_REV_LSB_REG, &rev);
1616 if (ret)
1617 return ret;
1618
1619 ret = regmap_read(priv->regmap, BNO055_SW_REV_MSB_REG, &ver);
1620 if (ret)
1621 return ret;
1622
1623 /*
1624 * The stock FW version contains a bug (see comment at the beginning of
1625 * this file) that causes the anglvel scale to be changed depending on
1626 * the chip range setting. We workaround this, but we don't know what
1627 * other FW versions might do.
1628 */
1629 if (ver != 0x3 || rev != 0x11)
1630 dev_warn(dev, "Untested firmware version. Anglvel scale may not work as expected\n");
1631
1632 ret = regmap_bulk_read(priv->regmap, BNO055_UID_LOWER_REG,
1633 priv->uid, BNO055_UID_LEN);
1634 if (ret)
1635 return ret;
1636
1637 /* Sensor calibration data */
1638 fw_name_buf = kasprintf(GFP_KERNEL, BNO055_FW_UID_FMT,
1639 BNO055_UID_LEN, priv->uid);
1640 if (!fw_name_buf)
1641 return -ENOMEM;
1642
1643 ret = request_firmware(&caldata, fw_name_buf, dev);
1644 kfree(fw_name_buf);
1645 if (ret)
1646 ret = request_firmware(&caldata, BNO055_FW_GENERIC_NAME, dev);
1647 if (ret) {
1648 dev_notice(dev, "Calibration file load failed. See instruction in kernel Documentation/iio/bno055.rst\n");
1649 ret = bno055_init(priv, NULL, 0);
1650 } else {
1651 ret = bno055_init(priv, caldata->data, caldata->size);
1652 release_firmware(caldata);
1653 }
1654 if (ret)
1655 return ret;
1656
1657 priv->operation_mode = BNO055_OPR_MODE_FUSION;
1658 ret = bno055_operation_mode_do_set(priv, priv->operation_mode);
1659 if (ret)
1660 return ret;
1661
1662 ret = devm_add_action_or_reset(dev, bno055_uninit, priv);
1663 if (ret)
1664 return ret;
1665
1666 iio_dev->channels = bno055_channels;
1667 iio_dev->num_channels = ARRAY_SIZE(bno055_channels);
1668 iio_dev->info = &bno055_info;
1669 iio_dev->modes = INDIO_DIRECT_MODE;
1670
1671 ret = devm_iio_triggered_buffer_setup(dev, iio_dev,
1672 iio_pollfunc_store_time,
1673 bno055_trigger_handler,
1674 &bno055_buffer_setup_ops);
1675 if (ret)
1676 return ret;
1677
1678 ret = devm_iio_device_register(dev, iio_dev);
1679 if (ret)
1680 return ret;
1681
1682 bno055_debugfs_init(iio_dev);
1683
1684 return 0;
1685 }
1686 EXPORT_SYMBOL_NS_GPL(bno055_probe, IIO_BNO055);
1687
1688 MODULE_AUTHOR("Andrea Merello <andrea.merello@iit.it>");
1689 MODULE_DESCRIPTION("Bosch BNO055 driver");
1690 MODULE_LICENSE("GPL");
1691