1 /*
2 * Broadcom NetXtreme-E RoCE driver.
3 *
4 * Copyright (c) 2016 - 2017, Broadcom. All rights reserved. The term
5 * Broadcom refers to Broadcom Limited and/or its subsidiaries.
6 *
7 * This software is available to you under a choice of one of two
8 * licenses. You may choose to be licensed under the terms of the GNU
9 * General Public License (GPL) Version 2, available from the file
10 * COPYING in the main directory of this source tree, or the
11 * BSD license below:
12 *
13 * Redistribution and use in source and binary forms, with or without
14 * modification, are permitted provided that the following conditions
15 * are met:
16 *
17 * 1. Redistributions of source code must retain the above copyright
18 * notice, this list of conditions and the following disclaimer.
19 * 2. Redistributions in binary form must reproduce the above copyright
20 * notice, this list of conditions and the following disclaimer in
21 * the documentation and/or other materials provided with the
22 * distribution.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS''
25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
26 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS
28 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
31 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
32 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
33 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
34 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
35 *
36 * Description: Main component of the bnxt_re driver
37 */
38
39 #include <linux/module.h>
40 #include <linux/netdevice.h>
41 #include <linux/ethtool.h>
42 #include <linux/mutex.h>
43 #include <linux/list.h>
44 #include <linux/rculist.h>
45 #include <linux/spinlock.h>
46 #include <linux/pci.h>
47 #include <net/dcbnl.h>
48 #include <net/ipv6.h>
49 #include <net/addrconf.h>
50 #include <linux/if_ether.h>
51 #include <linux/auxiliary_bus.h>
52
53 #include <rdma/ib_verbs.h>
54 #include <rdma/ib_user_verbs.h>
55 #include <rdma/ib_umem.h>
56 #include <rdma/ib_addr.h>
57 #include <linux/hashtable.h>
58
59 #include "bnxt_ulp.h"
60 #include "roce_hsi.h"
61 #include "qplib_res.h"
62 #include "qplib_sp.h"
63 #include "qplib_fp.h"
64 #include "qplib_rcfw.h"
65 #include "bnxt_re.h"
66 #include "ib_verbs.h"
67 #include <rdma/bnxt_re-abi.h>
68 #include "bnxt.h"
69 #include "hw_counters.h"
70
71 static char version[] =
72 BNXT_RE_DESC "\n";
73
74 MODULE_AUTHOR("Eddie Wai <eddie.wai@broadcom.com>");
75 MODULE_DESCRIPTION(BNXT_RE_DESC);
76 MODULE_LICENSE("Dual BSD/GPL");
77
78 /* globals */
79 static DEFINE_MUTEX(bnxt_re_mutex);
80
81 static void bnxt_re_stop_irq(void *handle);
82 static void bnxt_re_dev_stop(struct bnxt_re_dev *rdev);
83 static int bnxt_re_netdev_event(struct notifier_block *notifier,
84 unsigned long event, void *ptr);
85 static struct bnxt_re_dev *bnxt_re_from_netdev(struct net_device *netdev);
86 static void bnxt_re_dev_uninit(struct bnxt_re_dev *rdev, u8 op_type);
87 static int bnxt_re_hwrm_qcaps(struct bnxt_re_dev *rdev);
88
89 static int bnxt_re_hwrm_qcfg(struct bnxt_re_dev *rdev, u32 *db_len,
90 u32 *offset);
91 static void bnxt_re_setup_cc(struct bnxt_re_dev *rdev, bool enable);
bnxt_re_set_db_offset(struct bnxt_re_dev * rdev)92 static void bnxt_re_set_db_offset(struct bnxt_re_dev *rdev)
93 {
94 struct bnxt_qplib_chip_ctx *cctx;
95 struct bnxt_en_dev *en_dev;
96 struct bnxt_qplib_res *res;
97 u32 l2db_len = 0;
98 u32 offset = 0;
99 u32 barlen;
100 int rc;
101
102 res = &rdev->qplib_res;
103 en_dev = rdev->en_dev;
104 cctx = rdev->chip_ctx;
105
106 /* Issue qcfg */
107 rc = bnxt_re_hwrm_qcfg(rdev, &l2db_len, &offset);
108 if (rc)
109 dev_info(rdev_to_dev(rdev),
110 "Couldn't get DB bar size, Low latency framework is disabled\n");
111 /* set register offsets for both UC and WC */
112 if (bnxt_qplib_is_chip_gen_p7(cctx)) {
113 res->dpi_tbl.ucreg.offset = offset;
114 res->dpi_tbl.wcreg.offset = en_dev->l2_db_size;
115 } else {
116 res->dpi_tbl.ucreg.offset = res->is_vf ? BNXT_QPLIB_DBR_VF_DB_OFFSET :
117 BNXT_QPLIB_DBR_PF_DB_OFFSET;
118 res->dpi_tbl.wcreg.offset = res->dpi_tbl.ucreg.offset;
119 }
120
121 /* If WC mapping is disabled by L2 driver then en_dev->l2_db_size
122 * is equal to the DB-Bar actual size. This indicates that L2
123 * is mapping entire bar as UC-. RoCE driver can't enable WC mapping
124 * in such cases and DB-push will be disabled.
125 */
126 barlen = pci_resource_len(res->pdev, RCFW_DBR_PCI_BAR_REGION);
127 if (cctx->modes.db_push && l2db_len && en_dev->l2_db_size != barlen) {
128 res->dpi_tbl.wcreg.offset = en_dev->l2_db_size;
129 dev_info(rdev_to_dev(rdev), "Low latency framework is enabled\n");
130 }
131 }
132
bnxt_re_set_drv_mode(struct bnxt_re_dev * rdev)133 static void bnxt_re_set_drv_mode(struct bnxt_re_dev *rdev)
134 {
135 struct bnxt_qplib_chip_ctx *cctx;
136
137 cctx = rdev->chip_ctx;
138 cctx->modes.wqe_mode = bnxt_qplib_is_chip_gen_p7(rdev->chip_ctx) ?
139 BNXT_QPLIB_WQE_MODE_VARIABLE : BNXT_QPLIB_WQE_MODE_STATIC;
140 if (bnxt_re_hwrm_qcaps(rdev))
141 dev_err(rdev_to_dev(rdev),
142 "Failed to query hwrm qcaps\n");
143 if (bnxt_qplib_is_chip_gen_p7(rdev->chip_ctx)) {
144 cctx->modes.toggle_bits |= BNXT_QPLIB_CQ_TOGGLE_BIT;
145 cctx->modes.toggle_bits |= BNXT_QPLIB_SRQ_TOGGLE_BIT;
146 }
147 }
148
bnxt_re_destroy_chip_ctx(struct bnxt_re_dev * rdev)149 static void bnxt_re_destroy_chip_ctx(struct bnxt_re_dev *rdev)
150 {
151 struct bnxt_qplib_chip_ctx *chip_ctx;
152
153 if (!rdev->chip_ctx)
154 return;
155
156 kfree(rdev->dev_attr);
157 rdev->dev_attr = NULL;
158
159 chip_ctx = rdev->chip_ctx;
160 rdev->chip_ctx = NULL;
161 rdev->rcfw.res = NULL;
162 rdev->qplib_res.cctx = NULL;
163 rdev->qplib_res.pdev = NULL;
164 rdev->qplib_res.netdev = NULL;
165 kfree(chip_ctx);
166 }
167
bnxt_re_setup_chip_ctx(struct bnxt_re_dev * rdev)168 static int bnxt_re_setup_chip_ctx(struct bnxt_re_dev *rdev)
169 {
170 struct bnxt_qplib_chip_ctx *chip_ctx;
171 struct bnxt_en_dev *en_dev;
172 int rc = -ENOMEM;
173
174 en_dev = rdev->en_dev;
175
176 rdev->qplib_res.pdev = en_dev->pdev;
177 chip_ctx = kzalloc(sizeof(*chip_ctx), GFP_KERNEL);
178 if (!chip_ctx)
179 return -ENOMEM;
180 chip_ctx->chip_num = en_dev->chip_num;
181 chip_ctx->hw_stats_size = en_dev->hw_ring_stats_size;
182
183 rdev->chip_ctx = chip_ctx;
184 /* rest members to follow eventually */
185
186 rdev->qplib_res.cctx = rdev->chip_ctx;
187 rdev->rcfw.res = &rdev->qplib_res;
188 rdev->dev_attr = kzalloc(sizeof(*rdev->dev_attr), GFP_KERNEL);
189 if (!rdev->dev_attr)
190 goto free_chip_ctx;
191 rdev->qplib_res.dattr = rdev->dev_attr;
192 rdev->qplib_res.is_vf = BNXT_EN_VF(en_dev);
193
194 bnxt_re_set_drv_mode(rdev);
195
196 bnxt_re_set_db_offset(rdev);
197 rc = bnxt_qplib_map_db_bar(&rdev->qplib_res);
198 if (rc)
199 goto free_dev_attr;
200
201 if (bnxt_qplib_determine_atomics(en_dev->pdev))
202 ibdev_info(&rdev->ibdev,
203 "platform doesn't support global atomics.");
204 return 0;
205 free_dev_attr:
206 kfree(rdev->dev_attr);
207 rdev->dev_attr = NULL;
208 free_chip_ctx:
209 kfree(rdev->chip_ctx);
210 rdev->chip_ctx = NULL;
211 return rc;
212 }
213
214 /* SR-IOV helper functions */
215
bnxt_re_get_sriov_func_type(struct bnxt_re_dev * rdev)216 static void bnxt_re_get_sriov_func_type(struct bnxt_re_dev *rdev)
217 {
218 if (BNXT_EN_VF(rdev->en_dev))
219 rdev->is_virtfn = 1;
220 }
221
222 /* Set the maximum number of each resource that the driver actually wants
223 * to allocate. This may be up to the maximum number the firmware has
224 * reserved for the function. The driver may choose to allocate fewer
225 * resources than the firmware maximum.
226 */
bnxt_re_limit_pf_res(struct bnxt_re_dev * rdev)227 static void bnxt_re_limit_pf_res(struct bnxt_re_dev *rdev)
228 {
229 struct bnxt_qplib_dev_attr *attr;
230 struct bnxt_qplib_ctx *ctx;
231 int i;
232
233 attr = rdev->dev_attr;
234 ctx = &rdev->qplib_ctx;
235
236 ctx->qpc_count = min_t(u32, BNXT_RE_MAX_QPC_COUNT,
237 attr->max_qp);
238 ctx->mrw_count = BNXT_RE_MAX_MRW_COUNT_256K;
239 /* Use max_mr from fw since max_mrw does not get set */
240 ctx->mrw_count = min_t(u32, ctx->mrw_count, attr->max_mr);
241 ctx->srqc_count = min_t(u32, BNXT_RE_MAX_SRQC_COUNT,
242 attr->max_srq);
243 ctx->cq_count = min_t(u32, BNXT_RE_MAX_CQ_COUNT, attr->max_cq);
244 if (!bnxt_qplib_is_chip_gen_p5_p7(rdev->chip_ctx))
245 for (i = 0; i < MAX_TQM_ALLOC_REQ; i++)
246 rdev->qplib_ctx.tqm_ctx.qcount[i] =
247 rdev->dev_attr->tqm_alloc_reqs[i];
248 }
249
bnxt_re_limit_vf_res(struct bnxt_qplib_ctx * qplib_ctx,u32 num_vf)250 static void bnxt_re_limit_vf_res(struct bnxt_qplib_ctx *qplib_ctx, u32 num_vf)
251 {
252 struct bnxt_qplib_vf_res *vf_res;
253 u32 mrws = 0;
254 u32 vf_pct;
255 u32 nvfs;
256
257 vf_res = &qplib_ctx->vf_res;
258 /*
259 * Reserve a set of resources for the PF. Divide the remaining
260 * resources among the VFs
261 */
262 vf_pct = 100 - BNXT_RE_PCT_RSVD_FOR_PF;
263 nvfs = num_vf;
264 num_vf = 100 * num_vf;
265 vf_res->max_qp_per_vf = (qplib_ctx->qpc_count * vf_pct) / num_vf;
266 vf_res->max_srq_per_vf = (qplib_ctx->srqc_count * vf_pct) / num_vf;
267 vf_res->max_cq_per_vf = (qplib_ctx->cq_count * vf_pct) / num_vf;
268 /*
269 * The driver allows many more MRs than other resources. If the
270 * firmware does also, then reserve a fixed amount for the PF and
271 * divide the rest among VFs. VFs may use many MRs for NFS
272 * mounts, ISER, NVME applications, etc. If the firmware severely
273 * restricts the number of MRs, then let PF have half and divide
274 * the rest among VFs, as for the other resource types.
275 */
276 if (qplib_ctx->mrw_count < BNXT_RE_MAX_MRW_COUNT_64K) {
277 mrws = qplib_ctx->mrw_count * vf_pct;
278 nvfs = num_vf;
279 } else {
280 mrws = qplib_ctx->mrw_count - BNXT_RE_RESVD_MR_FOR_PF;
281 }
282 vf_res->max_mrw_per_vf = (mrws / nvfs);
283 vf_res->max_gid_per_vf = BNXT_RE_MAX_GID_PER_VF;
284 }
285
bnxt_re_set_resource_limits(struct bnxt_re_dev * rdev)286 static void bnxt_re_set_resource_limits(struct bnxt_re_dev *rdev)
287 {
288 u32 num_vfs;
289
290 memset(&rdev->qplib_ctx.vf_res, 0, sizeof(struct bnxt_qplib_vf_res));
291 bnxt_re_limit_pf_res(rdev);
292
293 num_vfs = bnxt_qplib_is_chip_gen_p5_p7(rdev->chip_ctx) ?
294 BNXT_RE_GEN_P5_MAX_VF : rdev->num_vfs;
295 if (num_vfs)
296 bnxt_re_limit_vf_res(&rdev->qplib_ctx, num_vfs);
297 }
298
bnxt_re_vf_res_config(struct bnxt_re_dev * rdev)299 static void bnxt_re_vf_res_config(struct bnxt_re_dev *rdev)
300 {
301 rdev->num_vfs = pci_sriov_get_totalvfs(rdev->en_dev->pdev);
302 if (!bnxt_qplib_is_chip_gen_p5_p7(rdev->chip_ctx)) {
303 bnxt_re_set_resource_limits(rdev);
304 bnxt_qplib_set_func_resources(&rdev->qplib_res, &rdev->rcfw,
305 &rdev->qplib_ctx);
306 }
307 }
308
bnxt_re_shutdown(struct auxiliary_device * adev)309 static void bnxt_re_shutdown(struct auxiliary_device *adev)
310 {
311 struct bnxt_re_en_dev_info *en_info = auxiliary_get_drvdata(adev);
312 struct bnxt_re_dev *rdev;
313
314 rdev = en_info->rdev;
315 ib_unregister_device(&rdev->ibdev);
316 bnxt_re_dev_uninit(rdev, BNXT_RE_COMPLETE_REMOVE);
317 }
318
bnxt_re_stop_irq(void * handle)319 static void bnxt_re_stop_irq(void *handle)
320 {
321 struct bnxt_re_en_dev_info *en_info = auxiliary_get_drvdata(handle);
322 struct bnxt_qplib_rcfw *rcfw;
323 struct bnxt_re_dev *rdev;
324 struct bnxt_qplib_nq *nq;
325 int indx;
326
327 rdev = en_info->rdev;
328 if (!rdev)
329 return;
330 rcfw = &rdev->rcfw;
331
332 for (indx = BNXT_RE_NQ_IDX; indx < rdev->nqr->num_msix; indx++) {
333 nq = &rdev->nqr->nq[indx - 1];
334 bnxt_qplib_nq_stop_irq(nq, false);
335 }
336
337 bnxt_qplib_rcfw_stop_irq(rcfw, false);
338 }
339
bnxt_re_start_irq(void * handle,struct bnxt_msix_entry * ent)340 static void bnxt_re_start_irq(void *handle, struct bnxt_msix_entry *ent)
341 {
342 struct bnxt_re_en_dev_info *en_info = auxiliary_get_drvdata(handle);
343 struct bnxt_msix_entry *msix_ent;
344 struct bnxt_qplib_rcfw *rcfw;
345 struct bnxt_re_dev *rdev;
346 struct bnxt_qplib_nq *nq;
347 int indx, rc;
348
349 rdev = en_info->rdev;
350 if (!rdev)
351 return;
352 msix_ent = rdev->nqr->msix_entries;
353 rcfw = &rdev->rcfw;
354 if (!ent) {
355 /* Not setting the f/w timeout bit in rcfw.
356 * During the driver unload the first command
357 * to f/w will timeout and that will set the
358 * timeout bit.
359 */
360 ibdev_err(&rdev->ibdev, "Failed to re-start IRQs\n");
361 return;
362 }
363
364 /* Vectors may change after restart, so update with new vectors
365 * in device sctructure.
366 */
367 for (indx = 0; indx < rdev->nqr->num_msix; indx++)
368 rdev->nqr->msix_entries[indx].vector = ent[indx].vector;
369
370 rc = bnxt_qplib_rcfw_start_irq(rcfw, msix_ent[BNXT_RE_AEQ_IDX].vector,
371 false);
372 if (rc) {
373 ibdev_warn(&rdev->ibdev, "Failed to reinit CREQ\n");
374 return;
375 }
376 for (indx = BNXT_RE_NQ_IDX ; indx < rdev->nqr->num_msix; indx++) {
377 nq = &rdev->nqr->nq[indx - 1];
378 rc = bnxt_qplib_nq_start_irq(nq, indx - 1,
379 msix_ent[indx].vector, false);
380 if (rc) {
381 ibdev_warn(&rdev->ibdev, "Failed to reinit NQ index %d\n",
382 indx - 1);
383 return;
384 }
385 }
386 }
387
388 static struct bnxt_ulp_ops bnxt_re_ulp_ops = {
389 .ulp_irq_stop = bnxt_re_stop_irq,
390 .ulp_irq_restart = bnxt_re_start_irq
391 };
392
393 /* RoCE -> Net driver */
394
bnxt_re_register_netdev(struct bnxt_re_dev * rdev)395 static int bnxt_re_register_netdev(struct bnxt_re_dev *rdev)
396 {
397 struct bnxt_en_dev *en_dev;
398
399 en_dev = rdev->en_dev;
400 return bnxt_register_dev(en_dev, &bnxt_re_ulp_ops, rdev->adev);
401 }
402
bnxt_re_init_hwrm_hdr(struct input * hdr,u16 opcd)403 static void bnxt_re_init_hwrm_hdr(struct input *hdr, u16 opcd)
404 {
405 hdr->req_type = cpu_to_le16(opcd);
406 hdr->cmpl_ring = cpu_to_le16(-1);
407 hdr->target_id = cpu_to_le16(-1);
408 }
409
bnxt_re_fill_fw_msg(struct bnxt_fw_msg * fw_msg,void * msg,int msg_len,void * resp,int resp_max_len,int timeout)410 static void bnxt_re_fill_fw_msg(struct bnxt_fw_msg *fw_msg, void *msg,
411 int msg_len, void *resp, int resp_max_len,
412 int timeout)
413 {
414 fw_msg->msg = msg;
415 fw_msg->msg_len = msg_len;
416 fw_msg->resp = resp;
417 fw_msg->resp_max_len = resp_max_len;
418 fw_msg->timeout = timeout;
419 }
420
421 /* Query device config using common hwrm */
bnxt_re_hwrm_qcfg(struct bnxt_re_dev * rdev,u32 * db_len,u32 * offset)422 static int bnxt_re_hwrm_qcfg(struct bnxt_re_dev *rdev, u32 *db_len,
423 u32 *offset)
424 {
425 struct bnxt_en_dev *en_dev = rdev->en_dev;
426 struct hwrm_func_qcfg_output resp = {0};
427 struct hwrm_func_qcfg_input req = {0};
428 struct bnxt_fw_msg fw_msg = {};
429 int rc;
430
431 bnxt_re_init_hwrm_hdr((void *)&req, HWRM_FUNC_QCFG);
432 req.fid = cpu_to_le16(0xffff);
433 bnxt_re_fill_fw_msg(&fw_msg, (void *)&req, sizeof(req), (void *)&resp,
434 sizeof(resp), DFLT_HWRM_CMD_TIMEOUT);
435 rc = bnxt_send_msg(en_dev, &fw_msg);
436 if (!rc) {
437 *db_len = PAGE_ALIGN(le16_to_cpu(resp.l2_doorbell_bar_size_kb) * 1024);
438 *offset = PAGE_ALIGN(le16_to_cpu(resp.legacy_l2_db_size_kb) * 1024);
439 }
440 return rc;
441 }
442
443 /* Query function capabilities using common hwrm */
bnxt_re_hwrm_qcaps(struct bnxt_re_dev * rdev)444 int bnxt_re_hwrm_qcaps(struct bnxt_re_dev *rdev)
445 {
446 struct bnxt_en_dev *en_dev = rdev->en_dev;
447 struct hwrm_func_qcaps_output resp = {};
448 struct hwrm_func_qcaps_input req = {};
449 struct bnxt_qplib_chip_ctx *cctx;
450 struct bnxt_fw_msg fw_msg = {};
451 u32 flags_ext2;
452 int rc;
453
454 cctx = rdev->chip_ctx;
455 bnxt_re_init_hwrm_hdr((void *)&req, HWRM_FUNC_QCAPS);
456 req.fid = cpu_to_le16(0xffff);
457 bnxt_re_fill_fw_msg(&fw_msg, (void *)&req, sizeof(req), (void *)&resp,
458 sizeof(resp), DFLT_HWRM_CMD_TIMEOUT);
459
460 rc = bnxt_send_msg(en_dev, &fw_msg);
461 if (rc)
462 return rc;
463 cctx->modes.db_push = le32_to_cpu(resp.flags) & FUNC_QCAPS_RESP_FLAGS_WCB_PUSH_MODE;
464
465 flags_ext2 = le32_to_cpu(resp.flags_ext2);
466 cctx->modes.dbr_pacing = flags_ext2 & FUNC_QCAPS_RESP_FLAGS_EXT2_DBR_PACING_EXT_SUPPORTED ||
467 flags_ext2 & FUNC_QCAPS_RESP_FLAGS_EXT2_DBR_PACING_V0_SUPPORTED;
468 return 0;
469 }
470
bnxt_re_hwrm_dbr_pacing_qcfg(struct bnxt_re_dev * rdev)471 static int bnxt_re_hwrm_dbr_pacing_qcfg(struct bnxt_re_dev *rdev)
472 {
473 struct bnxt_qplib_db_pacing_data *pacing_data = rdev->qplib_res.pacing_data;
474 struct hwrm_func_dbr_pacing_qcfg_output resp = {};
475 struct hwrm_func_dbr_pacing_qcfg_input req = {};
476 struct bnxt_en_dev *en_dev = rdev->en_dev;
477 struct bnxt_qplib_chip_ctx *cctx;
478 struct bnxt_fw_msg fw_msg = {};
479 int rc;
480
481 cctx = rdev->chip_ctx;
482 bnxt_re_init_hwrm_hdr((void *)&req, HWRM_FUNC_DBR_PACING_QCFG);
483 bnxt_re_fill_fw_msg(&fw_msg, (void *)&req, sizeof(req), (void *)&resp,
484 sizeof(resp), DFLT_HWRM_CMD_TIMEOUT);
485 rc = bnxt_send_msg(en_dev, &fw_msg);
486 if (rc)
487 return rc;
488
489 if ((le32_to_cpu(resp.dbr_stat_db_fifo_reg) &
490 FUNC_DBR_PACING_QCFG_RESP_DBR_STAT_DB_FIFO_REG_ADDR_SPACE_MASK) ==
491 FUNC_DBR_PACING_QCFG_RESP_DBR_STAT_DB_FIFO_REG_ADDR_SPACE_GRC)
492 cctx->dbr_stat_db_fifo =
493 le32_to_cpu(resp.dbr_stat_db_fifo_reg) &
494 ~FUNC_DBR_PACING_QCFG_RESP_DBR_STAT_DB_FIFO_REG_ADDR_SPACE_MASK;
495
496 pacing_data->fifo_max_depth = le32_to_cpu(resp.dbr_stat_db_max_fifo_depth);
497 if (!pacing_data->fifo_max_depth)
498 pacing_data->fifo_max_depth = BNXT_RE_MAX_FIFO_DEPTH(cctx);
499 pacing_data->fifo_room_mask = le32_to_cpu(resp.dbr_stat_db_fifo_reg_fifo_room_mask);
500 pacing_data->fifo_room_shift = resp.dbr_stat_db_fifo_reg_fifo_room_shift;
501
502 return 0;
503 }
504
505 /* Update the pacing tunable parameters to the default values */
bnxt_re_set_default_pacing_data(struct bnxt_re_dev * rdev)506 static void bnxt_re_set_default_pacing_data(struct bnxt_re_dev *rdev)
507 {
508 struct bnxt_qplib_db_pacing_data *pacing_data = rdev->qplib_res.pacing_data;
509
510 pacing_data->do_pacing = rdev->pacing.dbr_def_do_pacing;
511 pacing_data->pacing_th = rdev->pacing.pacing_algo_th;
512 pacing_data->alarm_th =
513 pacing_data->pacing_th * BNXT_RE_PACING_ALARM_TH_MULTIPLE;
514 }
515
__get_fifo_occupancy(struct bnxt_re_dev * rdev)516 static u32 __get_fifo_occupancy(struct bnxt_re_dev *rdev)
517 {
518 struct bnxt_qplib_db_pacing_data *pacing_data = rdev->qplib_res.pacing_data;
519 u32 read_val, fifo_occup;
520
521 read_val = readl(rdev->en_dev->bar0 + rdev->pacing.dbr_db_fifo_reg_off);
522 fifo_occup = pacing_data->fifo_max_depth -
523 ((read_val & pacing_data->fifo_room_mask) >>
524 pacing_data->fifo_room_shift);
525 return fifo_occup;
526 }
527
is_dbr_fifo_full(struct bnxt_re_dev * rdev)528 static bool is_dbr_fifo_full(struct bnxt_re_dev *rdev)
529 {
530 u32 max_occup, fifo_occup;
531
532 fifo_occup = __get_fifo_occupancy(rdev);
533 max_occup = BNXT_RE_MAX_FIFO_DEPTH(rdev->chip_ctx) - 1;
534 if (fifo_occup == max_occup)
535 return true;
536
537 return false;
538 }
539
__wait_for_fifo_occupancy_below_th(struct bnxt_re_dev * rdev)540 static void __wait_for_fifo_occupancy_below_th(struct bnxt_re_dev *rdev)
541 {
542 struct bnxt_qplib_db_pacing_data *pacing_data = rdev->qplib_res.pacing_data;
543 u32 retry_fifo_check = 1000;
544 u32 fifo_occup;
545
546 /* loop shouldn't run infintely as the occupancy usually goes
547 * below pacing algo threshold as soon as pacing kicks in.
548 */
549 while (1) {
550 fifo_occup = __get_fifo_occupancy(rdev);
551 /* Fifo occupancy cannot be greater the MAX FIFO depth */
552 if (fifo_occup > pacing_data->fifo_max_depth)
553 break;
554
555 if (fifo_occup < pacing_data->pacing_th)
556 break;
557 if (!retry_fifo_check--) {
558 dev_info_once(rdev_to_dev(rdev),
559 "%s: fifo_occup = 0x%xfifo_max_depth = 0x%x pacing_th = 0x%x\n",
560 __func__, fifo_occup, pacing_data->fifo_max_depth,
561 pacing_data->pacing_th);
562 break;
563 }
564
565 }
566 }
567
bnxt_re_db_fifo_check(struct work_struct * work)568 static void bnxt_re_db_fifo_check(struct work_struct *work)
569 {
570 struct bnxt_re_dev *rdev = container_of(work, struct bnxt_re_dev,
571 dbq_fifo_check_work);
572 struct bnxt_qplib_db_pacing_data *pacing_data;
573 u32 pacing_save;
574
575 if (!mutex_trylock(&rdev->pacing.dbq_lock))
576 return;
577 pacing_data = rdev->qplib_res.pacing_data;
578 pacing_save = rdev->pacing.do_pacing_save;
579 __wait_for_fifo_occupancy_below_th(rdev);
580 cancel_delayed_work_sync(&rdev->dbq_pacing_work);
581 if (pacing_save > rdev->pacing.dbr_def_do_pacing) {
582 /* Double the do_pacing value during the congestion */
583 pacing_save = pacing_save << 1;
584 } else {
585 /*
586 * when a new congestion is detected increase the do_pacing
587 * by 8 times. And also increase the pacing_th by 4 times. The
588 * reason to increase pacing_th is to give more space for the
589 * queue to oscillate down without getting empty, but also more
590 * room for the queue to increase without causing another alarm.
591 */
592 pacing_save = pacing_save << 3;
593 pacing_data->pacing_th = rdev->pacing.pacing_algo_th * 4;
594 }
595
596 if (pacing_save > BNXT_RE_MAX_DBR_DO_PACING)
597 pacing_save = BNXT_RE_MAX_DBR_DO_PACING;
598
599 pacing_data->do_pacing = pacing_save;
600 rdev->pacing.do_pacing_save = pacing_data->do_pacing;
601 pacing_data->alarm_th =
602 pacing_data->pacing_th * BNXT_RE_PACING_ALARM_TH_MULTIPLE;
603 schedule_delayed_work(&rdev->dbq_pacing_work,
604 msecs_to_jiffies(rdev->pacing.dbq_pacing_time));
605 rdev->stats.pacing.alerts++;
606 mutex_unlock(&rdev->pacing.dbq_lock);
607 }
608
bnxt_re_pacing_timer_exp(struct work_struct * work)609 static void bnxt_re_pacing_timer_exp(struct work_struct *work)
610 {
611 struct bnxt_re_dev *rdev = container_of(work, struct bnxt_re_dev,
612 dbq_pacing_work.work);
613 struct bnxt_qplib_db_pacing_data *pacing_data;
614 u32 fifo_occup;
615
616 if (!mutex_trylock(&rdev->pacing.dbq_lock))
617 return;
618
619 pacing_data = rdev->qplib_res.pacing_data;
620 fifo_occup = __get_fifo_occupancy(rdev);
621
622 if (fifo_occup > pacing_data->pacing_th)
623 goto restart_timer;
624
625 /*
626 * Instead of immediately going back to the default do_pacing
627 * reduce it by 1/8 times and restart the timer.
628 */
629 pacing_data->do_pacing = pacing_data->do_pacing - (pacing_data->do_pacing >> 3);
630 pacing_data->do_pacing = max_t(u32, rdev->pacing.dbr_def_do_pacing, pacing_data->do_pacing);
631 if (pacing_data->do_pacing <= rdev->pacing.dbr_def_do_pacing) {
632 bnxt_re_set_default_pacing_data(rdev);
633 rdev->stats.pacing.complete++;
634 goto dbq_unlock;
635 }
636
637 restart_timer:
638 schedule_delayed_work(&rdev->dbq_pacing_work,
639 msecs_to_jiffies(rdev->pacing.dbq_pacing_time));
640 rdev->stats.pacing.resched++;
641 dbq_unlock:
642 rdev->pacing.do_pacing_save = pacing_data->do_pacing;
643 mutex_unlock(&rdev->pacing.dbq_lock);
644 }
645
bnxt_re_pacing_alert(struct bnxt_re_dev * rdev)646 void bnxt_re_pacing_alert(struct bnxt_re_dev *rdev)
647 {
648 struct bnxt_qplib_db_pacing_data *pacing_data;
649
650 if (!rdev->pacing.dbr_pacing)
651 return;
652 mutex_lock(&rdev->pacing.dbq_lock);
653 pacing_data = rdev->qplib_res.pacing_data;
654
655 /*
656 * Increase the alarm_th to max so that other user lib instances do not
657 * keep alerting the driver.
658 */
659 pacing_data->alarm_th = pacing_data->fifo_max_depth;
660 pacing_data->do_pacing = BNXT_RE_MAX_DBR_DO_PACING;
661 cancel_work_sync(&rdev->dbq_fifo_check_work);
662 schedule_work(&rdev->dbq_fifo_check_work);
663 mutex_unlock(&rdev->pacing.dbq_lock);
664 }
665
bnxt_re_initialize_dbr_pacing(struct bnxt_re_dev * rdev)666 static int bnxt_re_initialize_dbr_pacing(struct bnxt_re_dev *rdev)
667 {
668 /* Allocate a page for app use */
669 rdev->pacing.dbr_page = (void *)__get_free_page(GFP_KERNEL);
670 if (!rdev->pacing.dbr_page)
671 return -ENOMEM;
672
673 memset((u8 *)rdev->pacing.dbr_page, 0, PAGE_SIZE);
674 rdev->qplib_res.pacing_data = (struct bnxt_qplib_db_pacing_data *)rdev->pacing.dbr_page;
675
676 if (bnxt_re_hwrm_dbr_pacing_qcfg(rdev)) {
677 free_page((u64)rdev->pacing.dbr_page);
678 rdev->pacing.dbr_page = NULL;
679 return -EIO;
680 }
681
682 /* MAP HW window 2 for reading db fifo depth */
683 writel(rdev->chip_ctx->dbr_stat_db_fifo & BNXT_GRC_BASE_MASK,
684 rdev->en_dev->bar0 + BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
685 rdev->pacing.dbr_db_fifo_reg_off =
686 (rdev->chip_ctx->dbr_stat_db_fifo & BNXT_GRC_OFFSET_MASK) +
687 BNXT_RE_GRC_FIFO_REG_BASE;
688 rdev->pacing.dbr_bar_addr =
689 pci_resource_start(rdev->qplib_res.pdev, 0) + rdev->pacing.dbr_db_fifo_reg_off;
690
691 if (is_dbr_fifo_full(rdev)) {
692 free_page((u64)rdev->pacing.dbr_page);
693 rdev->pacing.dbr_page = NULL;
694 return -EIO;
695 }
696
697 rdev->pacing.pacing_algo_th = BNXT_RE_PACING_ALGO_THRESHOLD;
698 rdev->pacing.dbq_pacing_time = BNXT_RE_DBR_PACING_TIME;
699 rdev->pacing.dbr_def_do_pacing = BNXT_RE_DBR_DO_PACING_NO_CONGESTION;
700 rdev->pacing.do_pacing_save = rdev->pacing.dbr_def_do_pacing;
701 rdev->qplib_res.pacing_data->grc_reg_offset = rdev->pacing.dbr_db_fifo_reg_off;
702 bnxt_re_set_default_pacing_data(rdev);
703 /* Initialize worker for DBR Pacing */
704 INIT_WORK(&rdev->dbq_fifo_check_work, bnxt_re_db_fifo_check);
705 INIT_DELAYED_WORK(&rdev->dbq_pacing_work, bnxt_re_pacing_timer_exp);
706 return 0;
707 }
708
bnxt_re_deinitialize_dbr_pacing(struct bnxt_re_dev * rdev)709 static void bnxt_re_deinitialize_dbr_pacing(struct bnxt_re_dev *rdev)
710 {
711 cancel_work_sync(&rdev->dbq_fifo_check_work);
712 cancel_delayed_work_sync(&rdev->dbq_pacing_work);
713 if (rdev->pacing.dbr_page)
714 free_page((u64)rdev->pacing.dbr_page);
715
716 rdev->pacing.dbr_page = NULL;
717 rdev->pacing.dbr_pacing = false;
718 }
719
bnxt_re_net_ring_free(struct bnxt_re_dev * rdev,u16 fw_ring_id,int type)720 static int bnxt_re_net_ring_free(struct bnxt_re_dev *rdev,
721 u16 fw_ring_id, int type)
722 {
723 struct bnxt_en_dev *en_dev;
724 struct hwrm_ring_free_input req = {};
725 struct hwrm_ring_free_output resp;
726 struct bnxt_fw_msg fw_msg = {};
727 int rc = -EINVAL;
728
729 if (!rdev)
730 return rc;
731
732 en_dev = rdev->en_dev;
733
734 if (!en_dev)
735 return rc;
736
737 if (test_bit(BNXT_RE_FLAG_ERR_DEVICE_DETACHED, &rdev->flags))
738 return 0;
739
740 bnxt_re_init_hwrm_hdr((void *)&req, HWRM_RING_FREE);
741 req.ring_type = type;
742 req.ring_id = cpu_to_le16(fw_ring_id);
743 bnxt_re_fill_fw_msg(&fw_msg, (void *)&req, sizeof(req), (void *)&resp,
744 sizeof(resp), DFLT_HWRM_CMD_TIMEOUT);
745 rc = bnxt_send_msg(en_dev, &fw_msg);
746 if (rc)
747 ibdev_err(&rdev->ibdev, "Failed to free HW ring:%d :%#x",
748 req.ring_id, rc);
749 return rc;
750 }
751
bnxt_re_net_ring_alloc(struct bnxt_re_dev * rdev,struct bnxt_re_ring_attr * ring_attr,u16 * fw_ring_id)752 static int bnxt_re_net_ring_alloc(struct bnxt_re_dev *rdev,
753 struct bnxt_re_ring_attr *ring_attr,
754 u16 *fw_ring_id)
755 {
756 struct bnxt_en_dev *en_dev = rdev->en_dev;
757 struct hwrm_ring_alloc_input req = {};
758 struct hwrm_ring_alloc_output resp;
759 struct bnxt_fw_msg fw_msg = {};
760 int rc = -EINVAL;
761
762 if (!en_dev)
763 return rc;
764
765 bnxt_re_init_hwrm_hdr((void *)&req, HWRM_RING_ALLOC);
766 req.enables = 0;
767 req.page_tbl_addr = cpu_to_le64(ring_attr->dma_arr[0]);
768 if (ring_attr->pages > 1) {
769 /* Page size is in log2 units */
770 req.page_size = BNXT_PAGE_SHIFT;
771 req.page_tbl_depth = 1;
772 }
773 req.fbo = 0;
774 /* Association of ring index with doorbell index and MSIX number */
775 req.logical_id = cpu_to_le16(ring_attr->lrid);
776 req.length = cpu_to_le32(ring_attr->depth + 1);
777 req.ring_type = ring_attr->type;
778 req.int_mode = ring_attr->mode;
779 bnxt_re_fill_fw_msg(&fw_msg, (void *)&req, sizeof(req), (void *)&resp,
780 sizeof(resp), DFLT_HWRM_CMD_TIMEOUT);
781 rc = bnxt_send_msg(en_dev, &fw_msg);
782 if (!rc)
783 *fw_ring_id = le16_to_cpu(resp.ring_id);
784
785 return rc;
786 }
787
bnxt_re_net_stats_ctx_free(struct bnxt_re_dev * rdev,u32 fw_stats_ctx_id)788 static int bnxt_re_net_stats_ctx_free(struct bnxt_re_dev *rdev,
789 u32 fw_stats_ctx_id)
790 {
791 struct bnxt_en_dev *en_dev = rdev->en_dev;
792 struct hwrm_stat_ctx_free_input req = {};
793 struct hwrm_stat_ctx_free_output resp = {};
794 struct bnxt_fw_msg fw_msg = {};
795 int rc = -EINVAL;
796
797 if (!en_dev)
798 return rc;
799
800 if (test_bit(BNXT_RE_FLAG_ERR_DEVICE_DETACHED, &rdev->flags))
801 return 0;
802
803 bnxt_re_init_hwrm_hdr((void *)&req, HWRM_STAT_CTX_FREE);
804 req.stat_ctx_id = cpu_to_le32(fw_stats_ctx_id);
805 bnxt_re_fill_fw_msg(&fw_msg, (void *)&req, sizeof(req), (void *)&resp,
806 sizeof(resp), DFLT_HWRM_CMD_TIMEOUT);
807 rc = bnxt_send_msg(en_dev, &fw_msg);
808 if (rc)
809 ibdev_err(&rdev->ibdev, "Failed to free HW stats context %#x",
810 rc);
811
812 return rc;
813 }
814
bnxt_re_net_stats_ctx_alloc(struct bnxt_re_dev * rdev,dma_addr_t dma_map,u32 * fw_stats_ctx_id)815 static int bnxt_re_net_stats_ctx_alloc(struct bnxt_re_dev *rdev,
816 dma_addr_t dma_map,
817 u32 *fw_stats_ctx_id)
818 {
819 struct bnxt_qplib_chip_ctx *chip_ctx = rdev->chip_ctx;
820 struct hwrm_stat_ctx_alloc_output resp = {};
821 struct hwrm_stat_ctx_alloc_input req = {};
822 struct bnxt_en_dev *en_dev = rdev->en_dev;
823 struct bnxt_fw_msg fw_msg = {};
824 int rc = -EINVAL;
825
826 *fw_stats_ctx_id = INVALID_STATS_CTX_ID;
827
828 if (!en_dev)
829 return rc;
830
831 bnxt_re_init_hwrm_hdr((void *)&req, HWRM_STAT_CTX_ALLOC);
832 req.update_period_ms = cpu_to_le32(1000);
833 req.stats_dma_addr = cpu_to_le64(dma_map);
834 req.stats_dma_length = cpu_to_le16(chip_ctx->hw_stats_size);
835 req.stat_ctx_flags = STAT_CTX_ALLOC_REQ_STAT_CTX_FLAGS_ROCE;
836 bnxt_re_fill_fw_msg(&fw_msg, (void *)&req, sizeof(req), (void *)&resp,
837 sizeof(resp), DFLT_HWRM_CMD_TIMEOUT);
838 rc = bnxt_send_msg(en_dev, &fw_msg);
839 if (!rc)
840 *fw_stats_ctx_id = le32_to_cpu(resp.stat_ctx_id);
841
842 return rc;
843 }
844
bnxt_re_disassociate_ucontext(struct ib_ucontext * ibcontext)845 static void bnxt_re_disassociate_ucontext(struct ib_ucontext *ibcontext)
846 {
847 }
848
849 /* Device */
850
bnxt_re_from_netdev(struct net_device * netdev)851 static struct bnxt_re_dev *bnxt_re_from_netdev(struct net_device *netdev)
852 {
853 struct ib_device *ibdev =
854 ib_device_get_by_netdev(netdev, RDMA_DRIVER_BNXT_RE);
855 if (!ibdev)
856 return NULL;
857
858 return container_of(ibdev, struct bnxt_re_dev, ibdev);
859 }
860
hw_rev_show(struct device * device,struct device_attribute * attr,char * buf)861 static ssize_t hw_rev_show(struct device *device, struct device_attribute *attr,
862 char *buf)
863 {
864 struct bnxt_re_dev *rdev =
865 rdma_device_to_drv_device(device, struct bnxt_re_dev, ibdev);
866
867 return sysfs_emit(buf, "0x%x\n", rdev->en_dev->pdev->vendor);
868 }
869 static DEVICE_ATTR_RO(hw_rev);
870
hca_type_show(struct device * device,struct device_attribute * attr,char * buf)871 static ssize_t hca_type_show(struct device *device,
872 struct device_attribute *attr, char *buf)
873 {
874 struct bnxt_re_dev *rdev =
875 rdma_device_to_drv_device(device, struct bnxt_re_dev, ibdev);
876
877 return sysfs_emit(buf, "%s\n", rdev->ibdev.node_desc);
878 }
879 static DEVICE_ATTR_RO(hca_type);
880
881 static struct attribute *bnxt_re_attributes[] = {
882 &dev_attr_hw_rev.attr,
883 &dev_attr_hca_type.attr,
884 NULL
885 };
886
887 static const struct attribute_group bnxt_re_dev_attr_group = {
888 .attrs = bnxt_re_attributes,
889 };
890
891 static const struct ib_device_ops bnxt_re_dev_ops = {
892 .owner = THIS_MODULE,
893 .driver_id = RDMA_DRIVER_BNXT_RE,
894 .uverbs_abi_ver = BNXT_RE_ABI_VERSION,
895
896 .add_gid = bnxt_re_add_gid,
897 .alloc_hw_port_stats = bnxt_re_ib_alloc_hw_port_stats,
898 .alloc_mr = bnxt_re_alloc_mr,
899 .alloc_pd = bnxt_re_alloc_pd,
900 .alloc_ucontext = bnxt_re_alloc_ucontext,
901 .create_ah = bnxt_re_create_ah,
902 .create_cq = bnxt_re_create_cq,
903 .create_qp = bnxt_re_create_qp,
904 .create_srq = bnxt_re_create_srq,
905 .create_user_ah = bnxt_re_create_ah,
906 .dealloc_pd = bnxt_re_dealloc_pd,
907 .dealloc_ucontext = bnxt_re_dealloc_ucontext,
908 .del_gid = bnxt_re_del_gid,
909 .dereg_mr = bnxt_re_dereg_mr,
910 .destroy_ah = bnxt_re_destroy_ah,
911 .destroy_cq = bnxt_re_destroy_cq,
912 .destroy_qp = bnxt_re_destroy_qp,
913 .destroy_srq = bnxt_re_destroy_srq,
914 .device_group = &bnxt_re_dev_attr_group,
915 .disassociate_ucontext = bnxt_re_disassociate_ucontext,
916 .get_dev_fw_str = bnxt_re_query_fw_str,
917 .get_dma_mr = bnxt_re_get_dma_mr,
918 .get_hw_stats = bnxt_re_ib_get_hw_stats,
919 .get_link_layer = bnxt_re_get_link_layer,
920 .get_port_immutable = bnxt_re_get_port_immutable,
921 .map_mr_sg = bnxt_re_map_mr_sg,
922 .mmap = bnxt_re_mmap,
923 .mmap_free = bnxt_re_mmap_free,
924 .modify_qp = bnxt_re_modify_qp,
925 .modify_srq = bnxt_re_modify_srq,
926 .poll_cq = bnxt_re_poll_cq,
927 .post_recv = bnxt_re_post_recv,
928 .post_send = bnxt_re_post_send,
929 .post_srq_recv = bnxt_re_post_srq_recv,
930 .query_ah = bnxt_re_query_ah,
931 .query_device = bnxt_re_query_device,
932 .query_pkey = bnxt_re_query_pkey,
933 .query_port = bnxt_re_query_port,
934 .query_qp = bnxt_re_query_qp,
935 .query_srq = bnxt_re_query_srq,
936 .reg_user_mr = bnxt_re_reg_user_mr,
937 .reg_user_mr_dmabuf = bnxt_re_reg_user_mr_dmabuf,
938 .req_notify_cq = bnxt_re_req_notify_cq,
939 .resize_cq = bnxt_re_resize_cq,
940 INIT_RDMA_OBJ_SIZE(ib_ah, bnxt_re_ah, ib_ah),
941 INIT_RDMA_OBJ_SIZE(ib_cq, bnxt_re_cq, ib_cq),
942 INIT_RDMA_OBJ_SIZE(ib_pd, bnxt_re_pd, ib_pd),
943 INIT_RDMA_OBJ_SIZE(ib_qp, bnxt_re_qp, ib_qp),
944 INIT_RDMA_OBJ_SIZE(ib_srq, bnxt_re_srq, ib_srq),
945 INIT_RDMA_OBJ_SIZE(ib_ucontext, bnxt_re_ucontext, ib_uctx),
946 };
947
bnxt_re_register_ib(struct bnxt_re_dev * rdev)948 static int bnxt_re_register_ib(struct bnxt_re_dev *rdev)
949 {
950 struct ib_device *ibdev = &rdev->ibdev;
951 int ret;
952
953 /* ib device init */
954 ibdev->node_type = RDMA_NODE_IB_CA;
955 strscpy(ibdev->node_desc, BNXT_RE_DESC " HCA",
956 strlen(BNXT_RE_DESC) + 5);
957 ibdev->phys_port_cnt = 1;
958
959 addrconf_addr_eui48((u8 *)&ibdev->node_guid, rdev->netdev->dev_addr);
960
961 ibdev->num_comp_vectors = rdev->nqr->num_msix - 1;
962 ibdev->dev.parent = &rdev->en_dev->pdev->dev;
963 ibdev->local_dma_lkey = BNXT_QPLIB_RSVD_LKEY;
964
965 if (IS_ENABLED(CONFIG_INFINIBAND_USER_ACCESS))
966 ibdev->driver_def = bnxt_re_uapi_defs;
967
968 ib_set_device_ops(ibdev, &bnxt_re_dev_ops);
969 ret = ib_device_set_netdev(&rdev->ibdev, rdev->netdev, 1);
970 if (ret)
971 return ret;
972
973 dma_set_max_seg_size(&rdev->en_dev->pdev->dev, UINT_MAX);
974 ibdev->uverbs_cmd_mask |= BIT_ULL(IB_USER_VERBS_CMD_POLL_CQ);
975 return ib_register_device(ibdev, "bnxt_re%d", &rdev->en_dev->pdev->dev);
976 }
977
bnxt_re_dev_add(struct auxiliary_device * adev,struct bnxt_en_dev * en_dev)978 static struct bnxt_re_dev *bnxt_re_dev_add(struct auxiliary_device *adev,
979 struct bnxt_en_dev *en_dev)
980 {
981 struct bnxt_re_dev *rdev;
982
983 /* Allocate bnxt_re_dev instance here */
984 rdev = ib_alloc_device(bnxt_re_dev, ibdev);
985 if (!rdev) {
986 ibdev_err(NULL, "%s: bnxt_re_dev allocation failure!",
987 ROCE_DRV_MODULE_NAME);
988 return NULL;
989 }
990 /* Default values */
991 rdev->nb.notifier_call = NULL;
992 rdev->netdev = en_dev->net;
993 rdev->en_dev = en_dev;
994 rdev->adev = adev;
995 rdev->id = rdev->en_dev->pdev->devfn;
996 INIT_LIST_HEAD(&rdev->qp_list);
997 mutex_init(&rdev->qp_lock);
998 mutex_init(&rdev->pacing.dbq_lock);
999 atomic_set(&rdev->stats.res.qp_count, 0);
1000 atomic_set(&rdev->stats.res.cq_count, 0);
1001 atomic_set(&rdev->stats.res.srq_count, 0);
1002 atomic_set(&rdev->stats.res.mr_count, 0);
1003 atomic_set(&rdev->stats.res.mw_count, 0);
1004 atomic_set(&rdev->stats.res.ah_count, 0);
1005 atomic_set(&rdev->stats.res.pd_count, 0);
1006 rdev->cosq[0] = 0xFFFF;
1007 rdev->cosq[1] = 0xFFFF;
1008
1009 return rdev;
1010 }
1011
bnxt_re_handle_unaffi_async_event(struct creq_func_event * unaffi_async)1012 static int bnxt_re_handle_unaffi_async_event(struct creq_func_event
1013 *unaffi_async)
1014 {
1015 switch (unaffi_async->event) {
1016 case CREQ_FUNC_EVENT_EVENT_TX_WQE_ERROR:
1017 break;
1018 case CREQ_FUNC_EVENT_EVENT_TX_DATA_ERROR:
1019 break;
1020 case CREQ_FUNC_EVENT_EVENT_RX_WQE_ERROR:
1021 break;
1022 case CREQ_FUNC_EVENT_EVENT_RX_DATA_ERROR:
1023 break;
1024 case CREQ_FUNC_EVENT_EVENT_CQ_ERROR:
1025 break;
1026 case CREQ_FUNC_EVENT_EVENT_TQM_ERROR:
1027 break;
1028 case CREQ_FUNC_EVENT_EVENT_CFCQ_ERROR:
1029 break;
1030 case CREQ_FUNC_EVENT_EVENT_CFCS_ERROR:
1031 break;
1032 case CREQ_FUNC_EVENT_EVENT_CFCC_ERROR:
1033 break;
1034 case CREQ_FUNC_EVENT_EVENT_CFCM_ERROR:
1035 break;
1036 case CREQ_FUNC_EVENT_EVENT_TIM_ERROR:
1037 break;
1038 default:
1039 return -EINVAL;
1040 }
1041 return 0;
1042 }
1043
bnxt_re_handle_qp_async_event(struct creq_qp_event * qp_event,struct bnxt_re_qp * qp)1044 static int bnxt_re_handle_qp_async_event(struct creq_qp_event *qp_event,
1045 struct bnxt_re_qp *qp)
1046 {
1047 struct creq_qp_error_notification *err_event;
1048 struct bnxt_re_srq *srq = NULL;
1049 struct ib_event event = {};
1050 unsigned int flags;
1051
1052 if (qp->qplib_qp.srq)
1053 srq = container_of(qp->qplib_qp.srq, struct bnxt_re_srq,
1054 qplib_srq);
1055
1056 if (qp->qplib_qp.state == CMDQ_MODIFY_QP_NEW_STATE_ERR &&
1057 rdma_is_kernel_res(&qp->ib_qp.res)) {
1058 flags = bnxt_re_lock_cqs(qp);
1059 bnxt_qplib_add_flush_qp(&qp->qplib_qp);
1060 bnxt_re_unlock_cqs(qp, flags);
1061 }
1062
1063 event.device = &qp->rdev->ibdev;
1064 event.element.qp = &qp->ib_qp;
1065 event.event = IB_EVENT_QP_FATAL;
1066
1067 err_event = (struct creq_qp_error_notification *)qp_event;
1068
1069 switch (err_event->req_err_state_reason) {
1070 case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_OPCODE_ERROR:
1071 case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_TIMEOUT_RETRY_LIMIT:
1072 case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_RNR_TIMEOUT_RETRY_LIMIT:
1073 case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_NAK_ARRIVAL_2:
1074 case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_NAK_ARRIVAL_3:
1075 case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_INVALID_READ_RESP:
1076 case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_ILLEGAL_BIND:
1077 case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_ILLEGAL_FAST_REG:
1078 case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_ILLEGAL_INVALIDATE:
1079 case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_RETRAN_LOCAL_ERROR:
1080 case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_AV_DOMAIN_ERROR:
1081 case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_PROD_WQE_MSMTCH_ERROR:
1082 case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_PSN_RANGE_CHECK_ERROR:
1083 event.event = IB_EVENT_QP_ACCESS_ERR;
1084 break;
1085 case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_NAK_ARRIVAL_1:
1086 case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_NAK_ARRIVAL_4:
1087 case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_READ_RESP_LENGTH:
1088 case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_WQE_FORMAT_ERROR:
1089 case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_ORRQ_FORMAT_ERROR:
1090 case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_INVALID_AVID_ERROR:
1091 case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_SERV_TYPE_ERROR:
1092 case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_INVALID_OP_ERROR:
1093 event.event = IB_EVENT_QP_REQ_ERR;
1094 break;
1095 case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_RX_MEMORY_ERROR:
1096 case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_TX_MEMORY_ERROR:
1097 case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_CMP_ERROR:
1098 case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_CQ_LOAD_ERROR:
1099 case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_TX_PCI_ERROR:
1100 case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_RX_PCI_ERROR:
1101 case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_RETX_SETUP_ERROR:
1102 event.event = IB_EVENT_QP_FATAL;
1103 break;
1104
1105 default:
1106 break;
1107 }
1108
1109 switch (err_event->res_err_state_reason) {
1110 case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_EXCEED_MAX:
1111 case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_PAYLOAD_LENGTH_MISMATCH:
1112 case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_PSN_SEQ_ERROR_RETRY_LIMIT:
1113 case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_RX_INVALID_R_KEY:
1114 case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_RX_DOMAIN_ERROR:
1115 case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_RX_NO_PERMISSION:
1116 case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_RX_RANGE_ERROR:
1117 case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_TX_INVALID_R_KEY:
1118 case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_TX_DOMAIN_ERROR:
1119 case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_TX_NO_PERMISSION:
1120 case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_TX_RANGE_ERROR:
1121 case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_UNALIGN_ATOMIC:
1122 case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_PSN_NOT_FOUND:
1123 case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_INVALID_DUP_RKEY:
1124 case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_IRRQ_FORMAT_ERROR:
1125 event.event = IB_EVENT_QP_ACCESS_ERR;
1126 break;
1127 case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_EXCEEDS_WQE:
1128 case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_WQE_FORMAT_ERROR:
1129 case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_UNSUPPORTED_OPCODE:
1130 case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_REM_INVALIDATE:
1131 case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_OPCODE_ERROR:
1132 event.event = IB_EVENT_QP_REQ_ERR;
1133 break;
1134 case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_IRRQ_OFLOW:
1135 case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_CMP_ERROR:
1136 case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_CQ_LOAD_ERROR:
1137 case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_TX_PCI_ERROR:
1138 case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_RX_PCI_ERROR:
1139 case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_MEMORY_ERROR:
1140 event.event = IB_EVENT_QP_FATAL;
1141 break;
1142 case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_SRQ_LOAD_ERROR:
1143 case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_SRQ_ERROR:
1144 if (srq)
1145 event.event = IB_EVENT_SRQ_ERR;
1146 break;
1147 default:
1148 break;
1149 }
1150
1151 if (err_event->res_err_state_reason || err_event->req_err_state_reason) {
1152 ibdev_dbg(&qp->rdev->ibdev,
1153 "%s %s qp_id: %d cons (%d %d) req (%d %d) res (%d %d)\n",
1154 __func__, rdma_is_kernel_res(&qp->ib_qp.res) ? "kernel" : "user",
1155 qp->qplib_qp.id,
1156 err_event->sq_cons_idx,
1157 err_event->rq_cons_idx,
1158 err_event->req_slow_path_state,
1159 err_event->req_err_state_reason,
1160 err_event->res_slow_path_state,
1161 err_event->res_err_state_reason);
1162 } else {
1163 if (srq)
1164 event.event = IB_EVENT_QP_LAST_WQE_REACHED;
1165 }
1166
1167 if (event.event == IB_EVENT_SRQ_ERR && srq->ib_srq.event_handler) {
1168 (*srq->ib_srq.event_handler)(&event,
1169 srq->ib_srq.srq_context);
1170 } else if (event.device && qp->ib_qp.event_handler) {
1171 qp->ib_qp.event_handler(&event, qp->ib_qp.qp_context);
1172 }
1173
1174 return 0;
1175 }
1176
bnxt_re_handle_cq_async_error(void * event,struct bnxt_re_cq * cq)1177 static int bnxt_re_handle_cq_async_error(void *event, struct bnxt_re_cq *cq)
1178 {
1179 struct creq_cq_error_notification *cqerr;
1180 struct ib_event ibevent = {};
1181
1182 cqerr = event;
1183 switch (cqerr->cq_err_reason) {
1184 case CREQ_CQ_ERROR_NOTIFICATION_CQ_ERR_REASON_REQ_CQ_INVALID_ERROR:
1185 case CREQ_CQ_ERROR_NOTIFICATION_CQ_ERR_REASON_REQ_CQ_OVERFLOW_ERROR:
1186 case CREQ_CQ_ERROR_NOTIFICATION_CQ_ERR_REASON_REQ_CQ_LOAD_ERROR:
1187 case CREQ_CQ_ERROR_NOTIFICATION_CQ_ERR_REASON_RES_CQ_INVALID_ERROR:
1188 case CREQ_CQ_ERROR_NOTIFICATION_CQ_ERR_REASON_RES_CQ_OVERFLOW_ERROR:
1189 case CREQ_CQ_ERROR_NOTIFICATION_CQ_ERR_REASON_RES_CQ_LOAD_ERROR:
1190 ibevent.event = IB_EVENT_CQ_ERR;
1191 break;
1192 default:
1193 break;
1194 }
1195
1196 if (ibevent.event == IB_EVENT_CQ_ERR && cq->ib_cq.event_handler) {
1197 ibevent.element.cq = &cq->ib_cq;
1198 ibevent.device = &cq->rdev->ibdev;
1199
1200 ibdev_dbg(&cq->rdev->ibdev,
1201 "%s err reason %d\n", __func__, cqerr->cq_err_reason);
1202 cq->ib_cq.event_handler(&ibevent, cq->ib_cq.cq_context);
1203 }
1204
1205 return 0;
1206 }
1207
bnxt_re_handle_affi_async_event(struct creq_qp_event * affi_async,void * obj)1208 static int bnxt_re_handle_affi_async_event(struct creq_qp_event *affi_async,
1209 void *obj)
1210 {
1211 struct bnxt_qplib_qp *lib_qp;
1212 struct bnxt_qplib_cq *lib_cq;
1213 struct bnxt_re_qp *qp;
1214 struct bnxt_re_cq *cq;
1215 int rc = 0;
1216 u8 event;
1217
1218 if (!obj)
1219 return rc; /* QP was already dead, still return success */
1220
1221 event = affi_async->event;
1222 switch (event) {
1223 case CREQ_QP_EVENT_EVENT_QP_ERROR_NOTIFICATION:
1224 lib_qp = obj;
1225 qp = container_of(lib_qp, struct bnxt_re_qp, qplib_qp);
1226 rc = bnxt_re_handle_qp_async_event(affi_async, qp);
1227 break;
1228 case CREQ_QP_EVENT_EVENT_CQ_ERROR_NOTIFICATION:
1229 lib_cq = obj;
1230 cq = container_of(lib_cq, struct bnxt_re_cq, qplib_cq);
1231 rc = bnxt_re_handle_cq_async_error(affi_async, cq);
1232 break;
1233 default:
1234 rc = -EINVAL;
1235 }
1236 return rc;
1237 }
1238
bnxt_re_aeq_handler(struct bnxt_qplib_rcfw * rcfw,void * aeqe,void * obj)1239 static int bnxt_re_aeq_handler(struct bnxt_qplib_rcfw *rcfw,
1240 void *aeqe, void *obj)
1241 {
1242 struct creq_qp_event *affi_async;
1243 struct creq_func_event *unaffi_async;
1244 u8 type;
1245 int rc;
1246
1247 type = ((struct creq_base *)aeqe)->type;
1248 if (type == CREQ_BASE_TYPE_FUNC_EVENT) {
1249 unaffi_async = aeqe;
1250 rc = bnxt_re_handle_unaffi_async_event(unaffi_async);
1251 } else {
1252 affi_async = aeqe;
1253 rc = bnxt_re_handle_affi_async_event(affi_async, obj);
1254 }
1255
1256 return rc;
1257 }
1258
bnxt_re_srqn_handler(struct bnxt_qplib_nq * nq,struct bnxt_qplib_srq * handle,u8 event)1259 static int bnxt_re_srqn_handler(struct bnxt_qplib_nq *nq,
1260 struct bnxt_qplib_srq *handle, u8 event)
1261 {
1262 struct bnxt_re_srq *srq = container_of(handle, struct bnxt_re_srq,
1263 qplib_srq);
1264 struct ib_event ib_event;
1265
1266 ib_event.device = &srq->rdev->ibdev;
1267 ib_event.element.srq = &srq->ib_srq;
1268
1269 if (srq->ib_srq.event_handler) {
1270 if (event == NQ_SRQ_EVENT_EVENT_SRQ_THRESHOLD_EVENT)
1271 ib_event.event = IB_EVENT_SRQ_LIMIT_REACHED;
1272 (*srq->ib_srq.event_handler)(&ib_event,
1273 srq->ib_srq.srq_context);
1274 }
1275 return 0;
1276 }
1277
bnxt_re_cqn_handler(struct bnxt_qplib_nq * nq,struct bnxt_qplib_cq * handle)1278 static int bnxt_re_cqn_handler(struct bnxt_qplib_nq *nq,
1279 struct bnxt_qplib_cq *handle)
1280 {
1281 struct bnxt_re_cq *cq = container_of(handle, struct bnxt_re_cq,
1282 qplib_cq);
1283
1284 if (cq->ib_cq.comp_handler)
1285 (*cq->ib_cq.comp_handler)(&cq->ib_cq, cq->ib_cq.cq_context);
1286
1287 return 0;
1288 }
1289
bnxt_re_cleanup_res(struct bnxt_re_dev * rdev)1290 static void bnxt_re_cleanup_res(struct bnxt_re_dev *rdev)
1291 {
1292 int i;
1293
1294 for (i = 1; i < rdev->nqr->num_msix; i++)
1295 bnxt_qplib_disable_nq(&rdev->nqr->nq[i - 1]);
1296
1297 if (rdev->qplib_res.rcfw)
1298 bnxt_qplib_cleanup_res(&rdev->qplib_res);
1299 }
1300
bnxt_re_init_res(struct bnxt_re_dev * rdev)1301 static int bnxt_re_init_res(struct bnxt_re_dev *rdev)
1302 {
1303 int num_vec_enabled = 0;
1304 int rc = 0, i;
1305 u32 db_offt;
1306
1307 bnxt_qplib_init_res(&rdev->qplib_res);
1308
1309 for (i = 1; i < rdev->nqr->num_msix ; i++) {
1310 db_offt = rdev->nqr->msix_entries[i].db_offset;
1311 rc = bnxt_qplib_enable_nq(rdev->en_dev->pdev, &rdev->nqr->nq[i - 1],
1312 i - 1, rdev->nqr->msix_entries[i].vector,
1313 db_offt, &bnxt_re_cqn_handler,
1314 &bnxt_re_srqn_handler);
1315 if (rc) {
1316 ibdev_err(&rdev->ibdev,
1317 "Failed to enable NQ with rc = 0x%x", rc);
1318 goto fail;
1319 }
1320 num_vec_enabled++;
1321 }
1322 return 0;
1323 fail:
1324 for (i = num_vec_enabled; i >= 0; i--)
1325 bnxt_qplib_disable_nq(&rdev->nqr->nq[i]);
1326 return rc;
1327 }
1328
bnxt_re_free_nq_res(struct bnxt_re_dev * rdev)1329 static void bnxt_re_free_nq_res(struct bnxt_re_dev *rdev)
1330 {
1331 struct bnxt_qplib_nq *nq;
1332 u8 type;
1333 int i;
1334
1335 for (i = 0; i < rdev->nqr->num_msix - 1; i++) {
1336 type = bnxt_qplib_get_ring_type(rdev->chip_ctx);
1337 nq = &rdev->nqr->nq[i];
1338 bnxt_re_net_ring_free(rdev, nq->ring_id, type);
1339 bnxt_qplib_free_nq(nq);
1340 nq->res = NULL;
1341 }
1342 }
1343
bnxt_re_free_res(struct bnxt_re_dev * rdev)1344 static void bnxt_re_free_res(struct bnxt_re_dev *rdev)
1345 {
1346 bnxt_re_free_nq_res(rdev);
1347
1348 if (rdev->qplib_res.dpi_tbl.max) {
1349 bnxt_qplib_dealloc_dpi(&rdev->qplib_res,
1350 &rdev->dpi_privileged);
1351 }
1352 if (rdev->qplib_res.rcfw) {
1353 bnxt_qplib_free_res(&rdev->qplib_res);
1354 rdev->qplib_res.rcfw = NULL;
1355 }
1356 }
1357
bnxt_re_alloc_res(struct bnxt_re_dev * rdev)1358 static int bnxt_re_alloc_res(struct bnxt_re_dev *rdev)
1359 {
1360 struct bnxt_re_ring_attr rattr = {};
1361 int num_vec_created = 0;
1362 int rc, i;
1363 u8 type;
1364
1365 /* Configure and allocate resources for qplib */
1366 rdev->qplib_res.rcfw = &rdev->rcfw;
1367 rc = bnxt_qplib_get_dev_attr(&rdev->rcfw);
1368 if (rc)
1369 goto fail;
1370
1371 rc = bnxt_qplib_alloc_res(&rdev->qplib_res, rdev->netdev);
1372 if (rc)
1373 goto fail;
1374
1375 rc = bnxt_qplib_alloc_dpi(&rdev->qplib_res,
1376 &rdev->dpi_privileged,
1377 rdev, BNXT_QPLIB_DPI_TYPE_KERNEL);
1378 if (rc)
1379 goto dealloc_res;
1380
1381 for (i = 0; i < rdev->nqr->num_msix - 1; i++) {
1382 struct bnxt_qplib_nq *nq;
1383
1384 nq = &rdev->nqr->nq[i];
1385 nq->hwq.max_elements = BNXT_QPLIB_NQE_MAX_CNT;
1386 rc = bnxt_qplib_alloc_nq(&rdev->qplib_res, nq);
1387 if (rc) {
1388 ibdev_err(&rdev->ibdev, "Alloc Failed NQ%d rc:%#x",
1389 i, rc);
1390 goto free_nq;
1391 }
1392 type = bnxt_qplib_get_ring_type(rdev->chip_ctx);
1393 rattr.dma_arr = nq->hwq.pbl[PBL_LVL_0].pg_map_arr;
1394 rattr.pages = nq->hwq.pbl[rdev->nqr->nq[i].hwq.level].pg_count;
1395 rattr.type = type;
1396 rattr.mode = RING_ALLOC_REQ_INT_MODE_MSIX;
1397 rattr.depth = BNXT_QPLIB_NQE_MAX_CNT - 1;
1398 rattr.lrid = rdev->nqr->msix_entries[i + 1].ring_idx;
1399 rc = bnxt_re_net_ring_alloc(rdev, &rattr, &nq->ring_id);
1400 if (rc) {
1401 ibdev_err(&rdev->ibdev,
1402 "Failed to allocate NQ fw id with rc = 0x%x",
1403 rc);
1404 bnxt_qplib_free_nq(nq);
1405 goto free_nq;
1406 }
1407 num_vec_created++;
1408 }
1409 return 0;
1410 free_nq:
1411 for (i = num_vec_created - 1; i >= 0; i--) {
1412 type = bnxt_qplib_get_ring_type(rdev->chip_ctx);
1413 bnxt_re_net_ring_free(rdev, rdev->nqr->nq[i].ring_id, type);
1414 bnxt_qplib_free_nq(&rdev->nqr->nq[i]);
1415 }
1416 bnxt_qplib_dealloc_dpi(&rdev->qplib_res,
1417 &rdev->dpi_privileged);
1418 dealloc_res:
1419 bnxt_qplib_free_res(&rdev->qplib_res);
1420
1421 fail:
1422 rdev->qplib_res.rcfw = NULL;
1423 return rc;
1424 }
1425
bnxt_re_dispatch_event(struct ib_device * ibdev,struct ib_qp * qp,u8 port_num,enum ib_event_type event)1426 static void bnxt_re_dispatch_event(struct ib_device *ibdev, struct ib_qp *qp,
1427 u8 port_num, enum ib_event_type event)
1428 {
1429 struct ib_event ib_event;
1430
1431 ib_event.device = ibdev;
1432 if (qp) {
1433 ib_event.element.qp = qp;
1434 ib_event.event = event;
1435 if (qp->event_handler)
1436 qp->event_handler(&ib_event, qp->qp_context);
1437
1438 } else {
1439 ib_event.element.port_num = port_num;
1440 ib_event.event = event;
1441 ib_dispatch_event(&ib_event);
1442 }
1443 }
1444
bnxt_re_is_qp1_or_shadow_qp(struct bnxt_re_dev * rdev,struct bnxt_re_qp * qp)1445 static bool bnxt_re_is_qp1_or_shadow_qp(struct bnxt_re_dev *rdev,
1446 struct bnxt_re_qp *qp)
1447 {
1448 return (qp->ib_qp.qp_type == IB_QPT_GSI) ||
1449 (qp == rdev->gsi_ctx.gsi_sqp);
1450 }
1451
bnxt_re_dev_stop(struct bnxt_re_dev * rdev)1452 static void bnxt_re_dev_stop(struct bnxt_re_dev *rdev)
1453 {
1454 struct bnxt_re_qp *qp;
1455
1456 mutex_lock(&rdev->qp_lock);
1457 list_for_each_entry(qp, &rdev->qp_list, list) {
1458 /* Modify the state of all QPs except QP1/Shadow QP */
1459 if (!bnxt_re_is_qp1_or_shadow_qp(rdev, qp)) {
1460 if (qp->qplib_qp.state !=
1461 CMDQ_MODIFY_QP_NEW_STATE_RESET &&
1462 qp->qplib_qp.state !=
1463 CMDQ_MODIFY_QP_NEW_STATE_ERR)
1464 bnxt_re_dispatch_event(&rdev->ibdev, &qp->ib_qp,
1465 1, IB_EVENT_QP_FATAL);
1466 }
1467 }
1468 mutex_unlock(&rdev->qp_lock);
1469 }
1470
bnxt_re_update_gid(struct bnxt_re_dev * rdev)1471 static int bnxt_re_update_gid(struct bnxt_re_dev *rdev)
1472 {
1473 struct bnxt_qplib_sgid_tbl *sgid_tbl = &rdev->qplib_res.sgid_tbl;
1474 struct bnxt_qplib_gid gid;
1475 u16 gid_idx, index;
1476 int rc = 0;
1477
1478 if (!ib_device_try_get(&rdev->ibdev))
1479 return 0;
1480
1481 for (index = 0; index < sgid_tbl->active; index++) {
1482 gid_idx = sgid_tbl->hw_id[index];
1483
1484 if (!memcmp(&sgid_tbl->tbl[index], &bnxt_qplib_gid_zero,
1485 sizeof(bnxt_qplib_gid_zero)))
1486 continue;
1487 /* need to modify the VLAN enable setting of non VLAN GID only
1488 * as setting is done for VLAN GID while adding GID
1489 */
1490 if (sgid_tbl->vlan[index])
1491 continue;
1492
1493 memcpy(&gid, &sgid_tbl->tbl[index], sizeof(gid));
1494
1495 rc = bnxt_qplib_update_sgid(sgid_tbl, &gid, gid_idx,
1496 rdev->qplib_res.netdev->dev_addr);
1497 }
1498
1499 ib_device_put(&rdev->ibdev);
1500 return rc;
1501 }
1502
bnxt_re_get_priority_mask(struct bnxt_re_dev * rdev)1503 static u32 bnxt_re_get_priority_mask(struct bnxt_re_dev *rdev)
1504 {
1505 u32 prio_map = 0, tmp_map = 0;
1506 struct net_device *netdev;
1507 struct dcb_app app = {};
1508
1509 netdev = rdev->netdev;
1510
1511 app.selector = IEEE_8021QAZ_APP_SEL_ETHERTYPE;
1512 app.protocol = ETH_P_IBOE;
1513 tmp_map = dcb_ieee_getapp_mask(netdev, &app);
1514 prio_map = tmp_map;
1515
1516 app.selector = IEEE_8021QAZ_APP_SEL_DGRAM;
1517 app.protocol = ROCE_V2_UDP_DPORT;
1518 tmp_map = dcb_ieee_getapp_mask(netdev, &app);
1519 prio_map |= tmp_map;
1520
1521 return prio_map;
1522 }
1523
bnxt_re_setup_qos(struct bnxt_re_dev * rdev)1524 static int bnxt_re_setup_qos(struct bnxt_re_dev *rdev)
1525 {
1526 u8 prio_map = 0;
1527
1528 /* Get priority for roce */
1529 prio_map = bnxt_re_get_priority_mask(rdev);
1530
1531 if (prio_map == rdev->cur_prio_map)
1532 return 0;
1533 rdev->cur_prio_map = prio_map;
1534 /* Actual priorities are not programmed as they are already
1535 * done by L2 driver; just enable or disable priority vlan tagging
1536 */
1537 if ((prio_map == 0 && rdev->qplib_res.prio) ||
1538 (prio_map != 0 && !rdev->qplib_res.prio)) {
1539 rdev->qplib_res.prio = prio_map;
1540 bnxt_re_update_gid(rdev);
1541 }
1542
1543 return 0;
1544 }
1545
bnxt_re_query_hwrm_intf_version(struct bnxt_re_dev * rdev)1546 static void bnxt_re_query_hwrm_intf_version(struct bnxt_re_dev *rdev)
1547 {
1548 struct bnxt_en_dev *en_dev = rdev->en_dev;
1549 struct hwrm_ver_get_output resp = {};
1550 struct hwrm_ver_get_input req = {};
1551 struct bnxt_qplib_chip_ctx *cctx;
1552 struct bnxt_fw_msg fw_msg = {};
1553 int rc;
1554
1555 bnxt_re_init_hwrm_hdr((void *)&req, HWRM_VER_GET);
1556 req.hwrm_intf_maj = HWRM_VERSION_MAJOR;
1557 req.hwrm_intf_min = HWRM_VERSION_MINOR;
1558 req.hwrm_intf_upd = HWRM_VERSION_UPDATE;
1559 bnxt_re_fill_fw_msg(&fw_msg, (void *)&req, sizeof(req), (void *)&resp,
1560 sizeof(resp), DFLT_HWRM_CMD_TIMEOUT);
1561 rc = bnxt_send_msg(en_dev, &fw_msg);
1562 if (rc) {
1563 ibdev_err(&rdev->ibdev, "Failed to query HW version, rc = 0x%x",
1564 rc);
1565 return;
1566 }
1567
1568 cctx = rdev->chip_ctx;
1569 cctx->hwrm_intf_ver =
1570 (u64)le16_to_cpu(resp.hwrm_intf_major) << 48 |
1571 (u64)le16_to_cpu(resp.hwrm_intf_minor) << 32 |
1572 (u64)le16_to_cpu(resp.hwrm_intf_build) << 16 |
1573 le16_to_cpu(resp.hwrm_intf_patch);
1574
1575 cctx->hwrm_cmd_max_timeout = le16_to_cpu(resp.max_req_timeout);
1576
1577 if (!cctx->hwrm_cmd_max_timeout)
1578 cctx->hwrm_cmd_max_timeout = RCFW_FW_STALL_MAX_TIMEOUT;
1579 }
1580
bnxt_re_ib_init(struct bnxt_re_dev * rdev)1581 static int bnxt_re_ib_init(struct bnxt_re_dev *rdev)
1582 {
1583 int rc;
1584 u32 event;
1585
1586 /* Register ib dev */
1587 rc = bnxt_re_register_ib(rdev);
1588 if (rc) {
1589 pr_err("Failed to register with IB: %#x\n", rc);
1590 return rc;
1591 }
1592 dev_info(rdev_to_dev(rdev), "Device registered with IB successfully");
1593 set_bit(BNXT_RE_FLAG_ISSUE_ROCE_STATS, &rdev->flags);
1594
1595 event = netif_running(rdev->netdev) && netif_carrier_ok(rdev->netdev) ?
1596 IB_EVENT_PORT_ACTIVE : IB_EVENT_PORT_ERR;
1597
1598 bnxt_re_dispatch_event(&rdev->ibdev, NULL, 1, event);
1599
1600 return rc;
1601 }
1602
bnxt_re_alloc_nqr_mem(struct bnxt_re_dev * rdev)1603 static int bnxt_re_alloc_nqr_mem(struct bnxt_re_dev *rdev)
1604 {
1605 rdev->nqr = kzalloc(sizeof(*rdev->nqr), GFP_KERNEL);
1606 if (!rdev->nqr)
1607 return -ENOMEM;
1608
1609 return 0;
1610 }
1611
bnxt_re_free_nqr_mem(struct bnxt_re_dev * rdev)1612 static void bnxt_re_free_nqr_mem(struct bnxt_re_dev *rdev)
1613 {
1614 kfree(rdev->nqr);
1615 rdev->nqr = NULL;
1616 }
1617
1618 /* When DEL_GID fails, driver is not freeing GID ctx memory.
1619 * To avoid the memory leak, free the memory during unload
1620 */
bnxt_re_free_gid_ctx(struct bnxt_re_dev * rdev)1621 static void bnxt_re_free_gid_ctx(struct bnxt_re_dev *rdev)
1622 {
1623 struct bnxt_qplib_sgid_tbl *sgid_tbl = &rdev->qplib_res.sgid_tbl;
1624 struct bnxt_re_gid_ctx *ctx, **ctx_tbl;
1625 int i;
1626
1627 if (!sgid_tbl->active)
1628 return;
1629
1630 ctx_tbl = sgid_tbl->ctx;
1631 for (i = 0; i < sgid_tbl->max; i++) {
1632 if (sgid_tbl->hw_id[i] == 0xFFFF)
1633 continue;
1634
1635 ctx = ctx_tbl[i];
1636 kfree(ctx);
1637 }
1638 }
1639
bnxt_re_dev_uninit(struct bnxt_re_dev * rdev,u8 op_type)1640 static void bnxt_re_dev_uninit(struct bnxt_re_dev *rdev, u8 op_type)
1641 {
1642 u8 type;
1643 int rc;
1644
1645 if (test_and_clear_bit(BNXT_RE_FLAG_QOS_WORK_REG, &rdev->flags))
1646 cancel_delayed_work_sync(&rdev->worker);
1647
1648 bnxt_re_free_gid_ctx(rdev);
1649 if (test_and_clear_bit(BNXT_RE_FLAG_RESOURCES_INITIALIZED,
1650 &rdev->flags))
1651 bnxt_re_cleanup_res(rdev);
1652 if (test_and_clear_bit(BNXT_RE_FLAG_RESOURCES_ALLOCATED, &rdev->flags))
1653 bnxt_re_free_res(rdev);
1654
1655 if (test_and_clear_bit(BNXT_RE_FLAG_RCFW_CHANNEL_EN, &rdev->flags)) {
1656 rc = bnxt_qplib_deinit_rcfw(&rdev->rcfw);
1657 if (rc)
1658 ibdev_warn(&rdev->ibdev,
1659 "Failed to deinitialize RCFW: %#x", rc);
1660 bnxt_re_net_stats_ctx_free(rdev, rdev->qplib_ctx.stats.fw_id);
1661 bnxt_qplib_free_ctx(&rdev->qplib_res, &rdev->qplib_ctx);
1662 bnxt_qplib_disable_rcfw_channel(&rdev->rcfw);
1663 type = bnxt_qplib_get_ring_type(rdev->chip_ctx);
1664 bnxt_re_net_ring_free(rdev, rdev->rcfw.creq.ring_id, type);
1665 bnxt_qplib_free_rcfw_channel(&rdev->rcfw);
1666 }
1667
1668 rdev->nqr->num_msix = 0;
1669
1670 if (rdev->pacing.dbr_pacing)
1671 bnxt_re_deinitialize_dbr_pacing(rdev);
1672
1673 bnxt_re_free_nqr_mem(rdev);
1674 bnxt_re_destroy_chip_ctx(rdev);
1675 if (op_type == BNXT_RE_COMPLETE_REMOVE) {
1676 if (test_and_clear_bit(BNXT_RE_FLAG_NETDEV_REGISTERED, &rdev->flags))
1677 bnxt_unregister_dev(rdev->en_dev);
1678 }
1679 }
1680
1681 /* worker thread for polling periodic events. Now used for QoS programming*/
bnxt_re_worker(struct work_struct * work)1682 static void bnxt_re_worker(struct work_struct *work)
1683 {
1684 struct bnxt_re_dev *rdev = container_of(work, struct bnxt_re_dev,
1685 worker.work);
1686
1687 bnxt_re_setup_qos(rdev);
1688 schedule_delayed_work(&rdev->worker, msecs_to_jiffies(30000));
1689 }
1690
bnxt_re_dev_init(struct bnxt_re_dev * rdev,u8 op_type)1691 static int bnxt_re_dev_init(struct bnxt_re_dev *rdev, u8 op_type)
1692 {
1693 struct bnxt_re_ring_attr rattr = {};
1694 struct bnxt_qplib_creq_ctx *creq;
1695 u32 db_offt;
1696 int vid;
1697 u8 type;
1698 int rc;
1699
1700 if (op_type == BNXT_RE_COMPLETE_INIT) {
1701 /* Registered a new RoCE device instance to netdev */
1702 rc = bnxt_re_register_netdev(rdev);
1703 if (rc) {
1704 ibdev_err(&rdev->ibdev,
1705 "Failed to register with netedev: %#x\n", rc);
1706 return -EINVAL;
1707 }
1708 }
1709 set_bit(BNXT_RE_FLAG_NETDEV_REGISTERED, &rdev->flags);
1710
1711 if (rdev->en_dev->ulp_tbl->msix_requested < BNXT_RE_MIN_MSIX) {
1712 ibdev_err(&rdev->ibdev,
1713 "RoCE requires minimum 2 MSI-X vectors, but only %d reserved\n",
1714 rdev->en_dev->ulp_tbl->msix_requested);
1715 bnxt_unregister_dev(rdev->en_dev);
1716 clear_bit(BNXT_RE_FLAG_NETDEV_REGISTERED, &rdev->flags);
1717 return -EINVAL;
1718 }
1719 ibdev_dbg(&rdev->ibdev, "Got %d MSI-X vectors\n",
1720 rdev->en_dev->ulp_tbl->msix_requested);
1721
1722 rc = bnxt_re_setup_chip_ctx(rdev);
1723 if (rc) {
1724 bnxt_unregister_dev(rdev->en_dev);
1725 clear_bit(BNXT_RE_FLAG_NETDEV_REGISTERED, &rdev->flags);
1726 ibdev_err(&rdev->ibdev, "Failed to get chip context\n");
1727 return -EINVAL;
1728 }
1729
1730 rc = bnxt_re_alloc_nqr_mem(rdev);
1731 if (rc) {
1732 bnxt_re_destroy_chip_ctx(rdev);
1733 bnxt_unregister_dev(rdev->en_dev);
1734 clear_bit(BNXT_RE_FLAG_NETDEV_REGISTERED, &rdev->flags);
1735 return rc;
1736 }
1737 rdev->nqr->num_msix = rdev->en_dev->ulp_tbl->msix_requested;
1738 memcpy(rdev->nqr->msix_entries, rdev->en_dev->msix_entries,
1739 sizeof(struct bnxt_msix_entry) * rdev->nqr->num_msix);
1740
1741 /* Check whether VF or PF */
1742 bnxt_re_get_sriov_func_type(rdev);
1743
1744 bnxt_re_query_hwrm_intf_version(rdev);
1745
1746 /* Establish RCFW Communication Channel to initialize the context
1747 * memory for the function and all child VFs
1748 */
1749 rc = bnxt_qplib_alloc_rcfw_channel(&rdev->qplib_res, &rdev->rcfw,
1750 &rdev->qplib_ctx,
1751 BNXT_RE_MAX_QPC_COUNT);
1752 if (rc) {
1753 ibdev_err(&rdev->ibdev,
1754 "Failed to allocate RCFW Channel: %#x\n", rc);
1755 goto fail;
1756 }
1757
1758 type = bnxt_qplib_get_ring_type(rdev->chip_ctx);
1759 creq = &rdev->rcfw.creq;
1760 rattr.dma_arr = creq->hwq.pbl[PBL_LVL_0].pg_map_arr;
1761 rattr.pages = creq->hwq.pbl[creq->hwq.level].pg_count;
1762 rattr.type = type;
1763 rattr.mode = RING_ALLOC_REQ_INT_MODE_MSIX;
1764 rattr.depth = BNXT_QPLIB_CREQE_MAX_CNT - 1;
1765 rattr.lrid = rdev->nqr->msix_entries[BNXT_RE_AEQ_IDX].ring_idx;
1766 rc = bnxt_re_net_ring_alloc(rdev, &rattr, &creq->ring_id);
1767 if (rc) {
1768 ibdev_err(&rdev->ibdev, "Failed to allocate CREQ: %#x\n", rc);
1769 goto free_rcfw;
1770 }
1771 db_offt = rdev->nqr->msix_entries[BNXT_RE_AEQ_IDX].db_offset;
1772 vid = rdev->nqr->msix_entries[BNXT_RE_AEQ_IDX].vector;
1773 rc = bnxt_qplib_enable_rcfw_channel(&rdev->rcfw,
1774 vid, db_offt,
1775 &bnxt_re_aeq_handler);
1776 if (rc) {
1777 ibdev_err(&rdev->ibdev, "Failed to enable RCFW channel: %#x\n",
1778 rc);
1779 goto free_ring;
1780 }
1781
1782 if (bnxt_qplib_dbr_pacing_en(rdev->chip_ctx)) {
1783 rc = bnxt_re_initialize_dbr_pacing(rdev);
1784 if (!rc) {
1785 rdev->pacing.dbr_pacing = true;
1786 } else {
1787 ibdev_err(&rdev->ibdev,
1788 "DBR pacing disabled with error : %d\n", rc);
1789 rdev->pacing.dbr_pacing = false;
1790 }
1791 }
1792 rc = bnxt_qplib_get_dev_attr(&rdev->rcfw);
1793 if (rc)
1794 goto disable_rcfw;
1795
1796 bnxt_re_set_resource_limits(rdev);
1797
1798 rc = bnxt_qplib_alloc_ctx(&rdev->qplib_res, &rdev->qplib_ctx, 0,
1799 bnxt_qplib_is_chip_gen_p5_p7(rdev->chip_ctx));
1800 if (rc) {
1801 ibdev_err(&rdev->ibdev,
1802 "Failed to allocate QPLIB context: %#x\n", rc);
1803 goto disable_rcfw;
1804 }
1805 rc = bnxt_re_net_stats_ctx_alloc(rdev,
1806 rdev->qplib_ctx.stats.dma_map,
1807 &rdev->qplib_ctx.stats.fw_id);
1808 if (rc) {
1809 ibdev_err(&rdev->ibdev,
1810 "Failed to allocate stats context: %#x\n", rc);
1811 goto free_ctx;
1812 }
1813
1814 rc = bnxt_qplib_init_rcfw(&rdev->rcfw, &rdev->qplib_ctx,
1815 rdev->is_virtfn);
1816 if (rc) {
1817 ibdev_err(&rdev->ibdev,
1818 "Failed to initialize RCFW: %#x\n", rc);
1819 goto free_sctx;
1820 }
1821 set_bit(BNXT_RE_FLAG_RCFW_CHANNEL_EN, &rdev->flags);
1822
1823 /* Resources based on the 'new' device caps */
1824 rc = bnxt_re_alloc_res(rdev);
1825 if (rc) {
1826 ibdev_err(&rdev->ibdev,
1827 "Failed to allocate resources: %#x\n", rc);
1828 goto fail;
1829 }
1830 set_bit(BNXT_RE_FLAG_RESOURCES_ALLOCATED, &rdev->flags);
1831 rc = bnxt_re_init_res(rdev);
1832 if (rc) {
1833 ibdev_err(&rdev->ibdev,
1834 "Failed to initialize resources: %#x\n", rc);
1835 goto fail;
1836 }
1837
1838 set_bit(BNXT_RE_FLAG_RESOURCES_INITIALIZED, &rdev->flags);
1839
1840 if (!rdev->is_virtfn) {
1841 rc = bnxt_re_setup_qos(rdev);
1842 if (rc)
1843 ibdev_info(&rdev->ibdev,
1844 "RoCE priority not yet configured\n");
1845
1846 INIT_DELAYED_WORK(&rdev->worker, bnxt_re_worker);
1847 set_bit(BNXT_RE_FLAG_QOS_WORK_REG, &rdev->flags);
1848 schedule_delayed_work(&rdev->worker, msecs_to_jiffies(30000));
1849 /*
1850 * Use the total VF count since the actual VF count may not be
1851 * available at this point.
1852 */
1853 bnxt_re_vf_res_config(rdev);
1854 }
1855 hash_init(rdev->cq_hash);
1856 if (rdev->chip_ctx->modes.toggle_bits & BNXT_QPLIB_SRQ_TOGGLE_BIT)
1857 hash_init(rdev->srq_hash);
1858
1859 return 0;
1860 free_sctx:
1861 bnxt_re_net_stats_ctx_free(rdev, rdev->qplib_ctx.stats.fw_id);
1862 free_ctx:
1863 bnxt_qplib_free_ctx(&rdev->qplib_res, &rdev->qplib_ctx);
1864 disable_rcfw:
1865 bnxt_qplib_disable_rcfw_channel(&rdev->rcfw);
1866 free_ring:
1867 type = bnxt_qplib_get_ring_type(rdev->chip_ctx);
1868 bnxt_re_net_ring_free(rdev, rdev->rcfw.creq.ring_id, type);
1869 free_rcfw:
1870 bnxt_qplib_free_rcfw_channel(&rdev->rcfw);
1871 fail:
1872 bnxt_re_dev_uninit(rdev, BNXT_RE_COMPLETE_REMOVE);
1873
1874 return rc;
1875 }
1876
bnxt_re_update_en_info_rdev(struct bnxt_re_dev * rdev,struct bnxt_re_en_dev_info * en_info,struct auxiliary_device * adev)1877 static void bnxt_re_update_en_info_rdev(struct bnxt_re_dev *rdev,
1878 struct bnxt_re_en_dev_info *en_info,
1879 struct auxiliary_device *adev)
1880 {
1881 /* Before updating the rdev pointer in bnxt_re_en_dev_info structure,
1882 * take the rtnl lock to avoid accessing invalid rdev pointer from
1883 * L2 ULP callbacks. This is applicable in all the places where rdev
1884 * pointer is updated in bnxt_re_en_dev_info.
1885 */
1886 rtnl_lock();
1887 en_info->rdev = rdev;
1888 rtnl_unlock();
1889 }
1890
bnxt_re_add_device(struct auxiliary_device * adev,u8 op_type)1891 static int bnxt_re_add_device(struct auxiliary_device *adev, u8 op_type)
1892 {
1893 struct bnxt_aux_priv *aux_priv =
1894 container_of(adev, struct bnxt_aux_priv, aux_dev);
1895 struct bnxt_re_en_dev_info *en_info;
1896 struct bnxt_en_dev *en_dev;
1897 struct bnxt_re_dev *rdev;
1898 int rc;
1899
1900 en_info = auxiliary_get_drvdata(adev);
1901 en_dev = en_info->en_dev;
1902
1903
1904 rdev = bnxt_re_dev_add(adev, en_dev);
1905 if (!rdev || !rdev_to_dev(rdev)) {
1906 rc = -ENOMEM;
1907 goto exit;
1908 }
1909
1910 bnxt_re_update_en_info_rdev(rdev, en_info, adev);
1911
1912 rc = bnxt_re_dev_init(rdev, op_type);
1913 if (rc)
1914 goto re_dev_dealloc;
1915
1916 rc = bnxt_re_ib_init(rdev);
1917 if (rc) {
1918 pr_err("Failed to register with IB: %s",
1919 aux_priv->aux_dev.name);
1920 goto re_dev_uninit;
1921 }
1922
1923 rdev->nb.notifier_call = bnxt_re_netdev_event;
1924 rc = register_netdevice_notifier(&rdev->nb);
1925 if (rc) {
1926 rdev->nb.notifier_call = NULL;
1927 pr_err("%s: Cannot register to netdevice_notifier",
1928 ROCE_DRV_MODULE_NAME);
1929 goto re_dev_unreg;
1930 }
1931 bnxt_re_setup_cc(rdev, true);
1932
1933 return 0;
1934
1935 re_dev_unreg:
1936 ib_unregister_device(&rdev->ibdev);
1937 re_dev_uninit:
1938 bnxt_re_update_en_info_rdev(NULL, en_info, adev);
1939 bnxt_re_dev_uninit(rdev, BNXT_RE_COMPLETE_REMOVE);
1940 re_dev_dealloc:
1941 ib_dealloc_device(&rdev->ibdev);
1942 exit:
1943 return rc;
1944 }
1945
bnxt_re_setup_cc(struct bnxt_re_dev * rdev,bool enable)1946 static void bnxt_re_setup_cc(struct bnxt_re_dev *rdev, bool enable)
1947 {
1948 struct bnxt_qplib_cc_param cc_param = {};
1949
1950 /* Do not enable congestion control on VFs */
1951 if (rdev->is_virtfn)
1952 return;
1953
1954 /* Currently enabling only for GenP5 adapters */
1955 if (!bnxt_qplib_is_chip_gen_p5_p7(rdev->chip_ctx))
1956 return;
1957
1958 if (enable) {
1959 cc_param.enable = 1;
1960 cc_param.cc_mode = CMDQ_MODIFY_ROCE_CC_CC_MODE_PROBABILISTIC_CC_MODE;
1961 }
1962
1963 cc_param.mask = (CMDQ_MODIFY_ROCE_CC_MODIFY_MASK_CC_MODE |
1964 CMDQ_MODIFY_ROCE_CC_MODIFY_MASK_ENABLE_CC |
1965 CMDQ_MODIFY_ROCE_CC_MODIFY_MASK_TOS_ECN);
1966
1967 if (bnxt_qplib_modify_cc(&rdev->qplib_res, &cc_param))
1968 ibdev_err(&rdev->ibdev, "Failed to setup CC enable = %d\n", enable);
1969 }
1970
1971 /*
1972 * "Notifier chain callback can be invoked for the same chain from
1973 * different CPUs at the same time".
1974 *
1975 * For cases when the netdev is already present, our call to the
1976 * register_netdevice_notifier() will actually get the rtnl_lock()
1977 * before sending NETDEV_REGISTER and (if up) NETDEV_UP
1978 * events.
1979 *
1980 * But for cases when the netdev is not already present, the notifier
1981 * chain is subjected to be invoked from different CPUs simultaneously.
1982 *
1983 * This is protected by the netdev_mutex.
1984 */
bnxt_re_netdev_event(struct notifier_block * notifier,unsigned long event,void * ptr)1985 static int bnxt_re_netdev_event(struct notifier_block *notifier,
1986 unsigned long event, void *ptr)
1987 {
1988 struct net_device *real_dev, *netdev = netdev_notifier_info_to_dev(ptr);
1989 struct bnxt_re_dev *rdev;
1990
1991 real_dev = rdma_vlan_dev_real_dev(netdev);
1992 if (!real_dev)
1993 real_dev = netdev;
1994
1995 if (real_dev != netdev)
1996 goto exit;
1997
1998 rdev = bnxt_re_from_netdev(real_dev);
1999 if (!rdev)
2000 return NOTIFY_DONE;
2001
2002
2003 switch (event) {
2004 case NETDEV_UP:
2005 case NETDEV_DOWN:
2006 case NETDEV_CHANGE:
2007 bnxt_re_dispatch_event(&rdev->ibdev, NULL, 1,
2008 netif_carrier_ok(real_dev) ?
2009 IB_EVENT_PORT_ACTIVE :
2010 IB_EVENT_PORT_ERR);
2011 break;
2012 default:
2013 break;
2014 }
2015 ib_device_put(&rdev->ibdev);
2016 exit:
2017 return NOTIFY_DONE;
2018 }
2019
2020 #define BNXT_ADEV_NAME "bnxt_en"
2021
bnxt_re_remove_device(struct bnxt_re_dev * rdev,u8 op_type,struct auxiliary_device * aux_dev)2022 static void bnxt_re_remove_device(struct bnxt_re_dev *rdev, u8 op_type,
2023 struct auxiliary_device *aux_dev)
2024 {
2025 if (rdev->nb.notifier_call) {
2026 unregister_netdevice_notifier(&rdev->nb);
2027 rdev->nb.notifier_call = NULL;
2028 } else {
2029 /* If notifier is null, we should have already done a
2030 * clean up before coming here.
2031 */
2032 return;
2033 }
2034 bnxt_re_setup_cc(rdev, false);
2035 ib_unregister_device(&rdev->ibdev);
2036 bnxt_re_dev_uninit(rdev, op_type);
2037 ib_dealloc_device(&rdev->ibdev);
2038 }
2039
bnxt_re_remove(struct auxiliary_device * adev)2040 static void bnxt_re_remove(struct auxiliary_device *adev)
2041 {
2042 struct bnxt_re_en_dev_info *en_info = auxiliary_get_drvdata(adev);
2043 struct bnxt_re_dev *rdev;
2044
2045 mutex_lock(&bnxt_re_mutex);
2046 rdev = en_info->rdev;
2047
2048 if (rdev)
2049 bnxt_re_remove_device(rdev, BNXT_RE_COMPLETE_REMOVE, adev);
2050 kfree(en_info);
2051 mutex_unlock(&bnxt_re_mutex);
2052 }
2053
bnxt_re_probe(struct auxiliary_device * adev,const struct auxiliary_device_id * id)2054 static int bnxt_re_probe(struct auxiliary_device *adev,
2055 const struct auxiliary_device_id *id)
2056 {
2057 struct bnxt_aux_priv *aux_priv =
2058 container_of(adev, struct bnxt_aux_priv, aux_dev);
2059 struct bnxt_re_en_dev_info *en_info;
2060 struct bnxt_en_dev *en_dev;
2061 int rc;
2062
2063 en_dev = aux_priv->edev;
2064
2065 mutex_lock(&bnxt_re_mutex);
2066 en_info = kzalloc(sizeof(*en_info), GFP_KERNEL);
2067 if (!en_info) {
2068 mutex_unlock(&bnxt_re_mutex);
2069 return -ENOMEM;
2070 }
2071 en_info->en_dev = en_dev;
2072
2073 auxiliary_set_drvdata(adev, en_info);
2074
2075 rc = bnxt_re_add_device(adev, BNXT_RE_COMPLETE_INIT);
2076 if (rc)
2077 goto err;
2078 mutex_unlock(&bnxt_re_mutex);
2079 return 0;
2080
2081 err:
2082 mutex_unlock(&bnxt_re_mutex);
2083 kfree(en_info);
2084
2085 return rc;
2086 }
2087
bnxt_re_suspend(struct auxiliary_device * adev,pm_message_t state)2088 static int bnxt_re_suspend(struct auxiliary_device *adev, pm_message_t state)
2089 {
2090 struct bnxt_re_en_dev_info *en_info = auxiliary_get_drvdata(adev);
2091 struct bnxt_en_dev *en_dev;
2092 struct bnxt_re_dev *rdev;
2093
2094 rdev = en_info->rdev;
2095 en_dev = en_info->en_dev;
2096 mutex_lock(&bnxt_re_mutex);
2097
2098 ibdev_info(&rdev->ibdev, "Handle device suspend call");
2099 /* Check the current device state from bnxt_en_dev and move the
2100 * device to detached state if FW_FATAL_COND is set.
2101 * This prevents more commands to HW during clean-up,
2102 * in case the device is already in error.
2103 */
2104 if (test_bit(BNXT_STATE_FW_FATAL_COND, &rdev->en_dev->en_state)) {
2105 set_bit(ERR_DEVICE_DETACHED, &rdev->rcfw.cmdq.flags);
2106 set_bit(BNXT_RE_FLAG_ERR_DEVICE_DETACHED, &rdev->flags);
2107 wake_up_all(&rdev->rcfw.cmdq.waitq);
2108 bnxt_re_dev_stop(rdev);
2109 }
2110
2111 if (rdev->pacing.dbr_pacing)
2112 bnxt_re_set_pacing_dev_state(rdev);
2113
2114 ibdev_info(&rdev->ibdev, "%s: L2 driver notified to stop en_state 0x%lx",
2115 __func__, en_dev->en_state);
2116 bnxt_re_remove_device(rdev, BNXT_RE_PRE_RECOVERY_REMOVE, adev);
2117 bnxt_re_update_en_info_rdev(NULL, en_info, adev);
2118 mutex_unlock(&bnxt_re_mutex);
2119
2120 return 0;
2121 }
2122
bnxt_re_resume(struct auxiliary_device * adev)2123 static int bnxt_re_resume(struct auxiliary_device *adev)
2124 {
2125 struct bnxt_re_en_dev_info *en_info = auxiliary_get_drvdata(adev);
2126 struct bnxt_re_dev *rdev;
2127
2128 mutex_lock(&bnxt_re_mutex);
2129 bnxt_re_add_device(adev, BNXT_RE_POST_RECOVERY_INIT);
2130 rdev = en_info->rdev;
2131 ibdev_info(&rdev->ibdev, "Device resume completed");
2132 mutex_unlock(&bnxt_re_mutex);
2133
2134 return 0;
2135 }
2136
2137 static const struct auxiliary_device_id bnxt_re_id_table[] = {
2138 { .name = BNXT_ADEV_NAME ".rdma", },
2139 {},
2140 };
2141
2142 MODULE_DEVICE_TABLE(auxiliary, bnxt_re_id_table);
2143
2144 static struct auxiliary_driver bnxt_re_driver = {
2145 .name = "rdma",
2146 .probe = bnxt_re_probe,
2147 .remove = bnxt_re_remove,
2148 .shutdown = bnxt_re_shutdown,
2149 .suspend = bnxt_re_suspend,
2150 .resume = bnxt_re_resume,
2151 .id_table = bnxt_re_id_table,
2152 };
2153
bnxt_re_mod_init(void)2154 static int __init bnxt_re_mod_init(void)
2155 {
2156 int rc;
2157
2158 pr_info("%s: %s", ROCE_DRV_MODULE_NAME, version);
2159 rc = auxiliary_driver_register(&bnxt_re_driver);
2160 if (rc) {
2161 pr_err("%s: Failed to register auxiliary driver\n",
2162 ROCE_DRV_MODULE_NAME);
2163 return rc;
2164 }
2165 return 0;
2166 }
2167
bnxt_re_mod_exit(void)2168 static void __exit bnxt_re_mod_exit(void)
2169 {
2170 auxiliary_driver_unregister(&bnxt_re_driver);
2171 }
2172
2173 module_init(bnxt_re_mod_init);
2174 module_exit(bnxt_re_mod_exit);
2175