1 /*
2 * Copyright (c) 2016-2017 Hisilicon Limited.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33 #include <linux/acpi.h>
34 #include <linux/etherdevice.h>
35 #include <linux/interrupt.h>
36 #include <linux/iopoll.h>
37 #include <linux/kernel.h>
38 #include <linux/types.h>
39 #include <linux/workqueue.h>
40 #include <net/addrconf.h>
41 #include <rdma/ib_addr.h>
42 #include <rdma/ib_cache.h>
43 #include <rdma/ib_umem.h>
44 #include <rdma/uverbs_ioctl.h>
45
46 #include "hns_roce_common.h"
47 #include "hns_roce_device.h"
48 #include "hns_roce_cmd.h"
49 #include "hns_roce_hem.h"
50 #include "hns_roce_hw_v2.h"
51
52 enum {
53 CMD_RST_PRC_OTHERS,
54 CMD_RST_PRC_SUCCESS,
55 CMD_RST_PRC_EBUSY,
56 };
57
58 enum ecc_resource_type {
59 ECC_RESOURCE_QPC,
60 ECC_RESOURCE_CQC,
61 ECC_RESOURCE_MPT,
62 ECC_RESOURCE_SRQC,
63 ECC_RESOURCE_GMV,
64 ECC_RESOURCE_QPC_TIMER,
65 ECC_RESOURCE_CQC_TIMER,
66 ECC_RESOURCE_SCCC,
67 ECC_RESOURCE_COUNT,
68 };
69
70 static const struct {
71 const char *name;
72 u8 read_bt0_op;
73 u8 write_bt0_op;
74 } fmea_ram_res[] = {
75 { "ECC_RESOURCE_QPC",
76 HNS_ROCE_CMD_READ_QPC_BT0, HNS_ROCE_CMD_WRITE_QPC_BT0 },
77 { "ECC_RESOURCE_CQC",
78 HNS_ROCE_CMD_READ_CQC_BT0, HNS_ROCE_CMD_WRITE_CQC_BT0 },
79 { "ECC_RESOURCE_MPT",
80 HNS_ROCE_CMD_READ_MPT_BT0, HNS_ROCE_CMD_WRITE_MPT_BT0 },
81 { "ECC_RESOURCE_SRQC",
82 HNS_ROCE_CMD_READ_SRQC_BT0, HNS_ROCE_CMD_WRITE_SRQC_BT0 },
83 /* ECC_RESOURCE_GMV is handled by cmdq, not mailbox */
84 { "ECC_RESOURCE_GMV",
85 0, 0 },
86 { "ECC_RESOURCE_QPC_TIMER",
87 HNS_ROCE_CMD_READ_QPC_TIMER_BT0, HNS_ROCE_CMD_WRITE_QPC_TIMER_BT0 },
88 { "ECC_RESOURCE_CQC_TIMER",
89 HNS_ROCE_CMD_READ_CQC_TIMER_BT0, HNS_ROCE_CMD_WRITE_CQC_TIMER_BT0 },
90 { "ECC_RESOURCE_SCCC",
91 HNS_ROCE_CMD_READ_SCCC_BT0, HNS_ROCE_CMD_WRITE_SCCC_BT0 },
92 };
93
set_data_seg_v2(struct hns_roce_v2_wqe_data_seg * dseg,struct ib_sge * sg)94 static inline void set_data_seg_v2(struct hns_roce_v2_wqe_data_seg *dseg,
95 struct ib_sge *sg)
96 {
97 dseg->lkey = cpu_to_le32(sg->lkey);
98 dseg->addr = cpu_to_le64(sg->addr);
99 dseg->len = cpu_to_le32(sg->length);
100 }
101
102 /*
103 * mapped-value = 1 + real-value
104 * The hns wr opcode real value is start from 0, In order to distinguish between
105 * initialized and uninitialized map values, we plus 1 to the actual value when
106 * defining the mapping, so that the validity can be identified by checking the
107 * mapped value is greater than 0.
108 */
109 #define HR_OPC_MAP(ib_key, hr_key) \
110 [IB_WR_ ## ib_key] = 1 + HNS_ROCE_V2_WQE_OP_ ## hr_key
111
112 static const u32 hns_roce_op_code[] = {
113 HR_OPC_MAP(RDMA_WRITE, RDMA_WRITE),
114 HR_OPC_MAP(RDMA_WRITE_WITH_IMM, RDMA_WRITE_WITH_IMM),
115 HR_OPC_MAP(SEND, SEND),
116 HR_OPC_MAP(SEND_WITH_IMM, SEND_WITH_IMM),
117 HR_OPC_MAP(RDMA_READ, RDMA_READ),
118 HR_OPC_MAP(ATOMIC_CMP_AND_SWP, ATOM_CMP_AND_SWAP),
119 HR_OPC_MAP(ATOMIC_FETCH_AND_ADD, ATOM_FETCH_AND_ADD),
120 HR_OPC_MAP(SEND_WITH_INV, SEND_WITH_INV),
121 HR_OPC_MAP(MASKED_ATOMIC_CMP_AND_SWP, ATOM_MSK_CMP_AND_SWAP),
122 HR_OPC_MAP(MASKED_ATOMIC_FETCH_AND_ADD, ATOM_MSK_FETCH_AND_ADD),
123 HR_OPC_MAP(REG_MR, FAST_REG_PMR),
124 };
125
to_hr_opcode(u32 ib_opcode)126 static u32 to_hr_opcode(u32 ib_opcode)
127 {
128 if (ib_opcode >= ARRAY_SIZE(hns_roce_op_code))
129 return HNS_ROCE_V2_WQE_OP_MASK;
130
131 return hns_roce_op_code[ib_opcode] ? hns_roce_op_code[ib_opcode] - 1 :
132 HNS_ROCE_V2_WQE_OP_MASK;
133 }
134
set_frmr_seg(struct hns_roce_v2_rc_send_wqe * rc_sq_wqe,const struct ib_reg_wr * wr)135 static void set_frmr_seg(struct hns_roce_v2_rc_send_wqe *rc_sq_wqe,
136 const struct ib_reg_wr *wr)
137 {
138 struct hns_roce_wqe_frmr_seg *fseg =
139 (void *)rc_sq_wqe + sizeof(struct hns_roce_v2_rc_send_wqe);
140 struct hns_roce_mr *mr = to_hr_mr(wr->mr);
141 u64 pbl_ba;
142
143 /* use ib_access_flags */
144 hr_reg_write_bool(fseg, FRMR_BIND_EN, wr->access & IB_ACCESS_MW_BIND);
145 hr_reg_write_bool(fseg, FRMR_ATOMIC,
146 wr->access & IB_ACCESS_REMOTE_ATOMIC);
147 hr_reg_write_bool(fseg, FRMR_RR, wr->access & IB_ACCESS_REMOTE_READ);
148 hr_reg_write_bool(fseg, FRMR_RW, wr->access & IB_ACCESS_REMOTE_WRITE);
149 hr_reg_write_bool(fseg, FRMR_LW, wr->access & IB_ACCESS_LOCAL_WRITE);
150
151 /* Data structure reuse may lead to confusion */
152 pbl_ba = mr->pbl_mtr.hem_cfg.root_ba;
153 rc_sq_wqe->msg_len = cpu_to_le32(lower_32_bits(pbl_ba));
154 rc_sq_wqe->inv_key = cpu_to_le32(upper_32_bits(pbl_ba));
155
156 rc_sq_wqe->byte_16 = cpu_to_le32(wr->mr->length & 0xffffffff);
157 rc_sq_wqe->byte_20 = cpu_to_le32(wr->mr->length >> 32);
158 rc_sq_wqe->rkey = cpu_to_le32(wr->key);
159 rc_sq_wqe->va = cpu_to_le64(wr->mr->iova);
160
161 hr_reg_write(fseg, FRMR_PBL_SIZE, mr->npages);
162 hr_reg_write(fseg, FRMR_PBL_BUF_PG_SZ,
163 to_hr_hw_page_shift(mr->pbl_mtr.hem_cfg.buf_pg_shift));
164 hr_reg_clear(fseg, FRMR_BLK_MODE);
165 }
166
set_atomic_seg(const struct ib_send_wr * wr,struct hns_roce_v2_rc_send_wqe * rc_sq_wqe,unsigned int valid_num_sge)167 static void set_atomic_seg(const struct ib_send_wr *wr,
168 struct hns_roce_v2_rc_send_wqe *rc_sq_wqe,
169 unsigned int valid_num_sge)
170 {
171 struct hns_roce_v2_wqe_data_seg *dseg =
172 (void *)rc_sq_wqe + sizeof(struct hns_roce_v2_rc_send_wqe);
173 struct hns_roce_wqe_atomic_seg *aseg =
174 (void *)dseg + sizeof(struct hns_roce_v2_wqe_data_seg);
175
176 set_data_seg_v2(dseg, wr->sg_list);
177
178 if (wr->opcode == IB_WR_ATOMIC_CMP_AND_SWP) {
179 aseg->fetchadd_swap_data = cpu_to_le64(atomic_wr(wr)->swap);
180 aseg->cmp_data = cpu_to_le64(atomic_wr(wr)->compare_add);
181 } else {
182 aseg->fetchadd_swap_data =
183 cpu_to_le64(atomic_wr(wr)->compare_add);
184 aseg->cmp_data = 0;
185 }
186
187 hr_reg_write(rc_sq_wqe, RC_SEND_WQE_SGE_NUM, valid_num_sge);
188 }
189
fill_ext_sge_inl_data(struct hns_roce_qp * qp,const struct ib_send_wr * wr,unsigned int * sge_idx,u32 msg_len)190 static int fill_ext_sge_inl_data(struct hns_roce_qp *qp,
191 const struct ib_send_wr *wr,
192 unsigned int *sge_idx, u32 msg_len)
193 {
194 struct ib_device *ibdev = &(to_hr_dev(qp->ibqp.device))->ib_dev;
195 unsigned int left_len_in_pg;
196 unsigned int idx = *sge_idx;
197 unsigned int i = 0;
198 unsigned int len;
199 void *addr;
200 void *dseg;
201
202 if (msg_len > qp->sq.ext_sge_cnt * HNS_ROCE_SGE_SIZE) {
203 ibdev_err(ibdev,
204 "no enough extended sge space for inline data.\n");
205 return -EINVAL;
206 }
207
208 dseg = hns_roce_get_extend_sge(qp, idx & (qp->sge.sge_cnt - 1));
209 left_len_in_pg = hr_hw_page_align((uintptr_t)dseg) - (uintptr_t)dseg;
210 len = wr->sg_list[0].length;
211 addr = (void *)(unsigned long)(wr->sg_list[0].addr);
212
213 /* When copying data to extended sge space, the left length in page may
214 * not long enough for current user's sge. So the data should be
215 * splited into several parts, one in the first page, and the others in
216 * the subsequent pages.
217 */
218 while (1) {
219 if (len <= left_len_in_pg) {
220 memcpy(dseg, addr, len);
221
222 idx += len / HNS_ROCE_SGE_SIZE;
223
224 i++;
225 if (i >= wr->num_sge)
226 break;
227
228 left_len_in_pg -= len;
229 len = wr->sg_list[i].length;
230 addr = (void *)(unsigned long)(wr->sg_list[i].addr);
231 dseg += len;
232 } else {
233 memcpy(dseg, addr, left_len_in_pg);
234
235 len -= left_len_in_pg;
236 addr += left_len_in_pg;
237 idx += left_len_in_pg / HNS_ROCE_SGE_SIZE;
238 dseg = hns_roce_get_extend_sge(qp,
239 idx & (qp->sge.sge_cnt - 1));
240 left_len_in_pg = 1 << HNS_HW_PAGE_SHIFT;
241 }
242 }
243
244 *sge_idx = idx;
245
246 return 0;
247 }
248
set_extend_sge(struct hns_roce_qp * qp,struct ib_sge * sge,unsigned int * sge_ind,unsigned int cnt)249 static void set_extend_sge(struct hns_roce_qp *qp, struct ib_sge *sge,
250 unsigned int *sge_ind, unsigned int cnt)
251 {
252 struct hns_roce_v2_wqe_data_seg *dseg;
253 unsigned int idx = *sge_ind;
254
255 while (cnt > 0) {
256 dseg = hns_roce_get_extend_sge(qp, idx & (qp->sge.sge_cnt - 1));
257 if (likely(sge->length)) {
258 set_data_seg_v2(dseg, sge);
259 idx++;
260 cnt--;
261 }
262 sge++;
263 }
264
265 *sge_ind = idx;
266 }
267
check_inl_data_len(struct hns_roce_qp * qp,unsigned int len)268 static bool check_inl_data_len(struct hns_roce_qp *qp, unsigned int len)
269 {
270 struct hns_roce_dev *hr_dev = to_hr_dev(qp->ibqp.device);
271 int mtu = ib_mtu_enum_to_int(qp->path_mtu);
272
273 if (mtu < 0 || len > qp->max_inline_data || len > mtu) {
274 ibdev_err(&hr_dev->ib_dev,
275 "invalid length of data, data len = %u, max inline len = %u, path mtu = %d.\n",
276 len, qp->max_inline_data, mtu);
277 return false;
278 }
279
280 return true;
281 }
282
set_rc_inl(struct hns_roce_qp * qp,const struct ib_send_wr * wr,struct hns_roce_v2_rc_send_wqe * rc_sq_wqe,unsigned int * sge_idx)283 static int set_rc_inl(struct hns_roce_qp *qp, const struct ib_send_wr *wr,
284 struct hns_roce_v2_rc_send_wqe *rc_sq_wqe,
285 unsigned int *sge_idx)
286 {
287 struct hns_roce_dev *hr_dev = to_hr_dev(qp->ibqp.device);
288 u32 msg_len = le32_to_cpu(rc_sq_wqe->msg_len);
289 struct ib_device *ibdev = &hr_dev->ib_dev;
290 unsigned int curr_idx = *sge_idx;
291 void *dseg = rc_sq_wqe;
292 unsigned int i;
293 int ret;
294
295 if (unlikely(wr->opcode == IB_WR_RDMA_READ)) {
296 ibdev_err(ibdev, "invalid inline parameters!\n");
297 return -EINVAL;
298 }
299
300 if (!check_inl_data_len(qp, msg_len))
301 return -EINVAL;
302
303 dseg += sizeof(struct hns_roce_v2_rc_send_wqe);
304
305 if (msg_len <= HNS_ROCE_V2_MAX_RC_INL_INN_SZ) {
306 hr_reg_clear(rc_sq_wqe, RC_SEND_WQE_INL_TYPE);
307
308 for (i = 0; i < wr->num_sge; i++) {
309 memcpy(dseg, ((void *)wr->sg_list[i].addr),
310 wr->sg_list[i].length);
311 dseg += wr->sg_list[i].length;
312 }
313 } else {
314 hr_reg_enable(rc_sq_wqe, RC_SEND_WQE_INL_TYPE);
315
316 ret = fill_ext_sge_inl_data(qp, wr, &curr_idx, msg_len);
317 if (ret)
318 return ret;
319
320 hr_reg_write(rc_sq_wqe, RC_SEND_WQE_SGE_NUM, curr_idx - *sge_idx);
321 }
322
323 *sge_idx = curr_idx;
324
325 return 0;
326 }
327
set_rwqe_data_seg(struct ib_qp * ibqp,const struct ib_send_wr * wr,struct hns_roce_v2_rc_send_wqe * rc_sq_wqe,unsigned int * sge_ind,unsigned int valid_num_sge)328 static int set_rwqe_data_seg(struct ib_qp *ibqp, const struct ib_send_wr *wr,
329 struct hns_roce_v2_rc_send_wqe *rc_sq_wqe,
330 unsigned int *sge_ind,
331 unsigned int valid_num_sge)
332 {
333 struct hns_roce_v2_wqe_data_seg *dseg =
334 (void *)rc_sq_wqe + sizeof(struct hns_roce_v2_rc_send_wqe);
335 struct hns_roce_qp *qp = to_hr_qp(ibqp);
336 int j = 0;
337 int i;
338
339 hr_reg_write(rc_sq_wqe, RC_SEND_WQE_MSG_START_SGE_IDX,
340 (*sge_ind) & (qp->sge.sge_cnt - 1));
341
342 hr_reg_write(rc_sq_wqe, RC_SEND_WQE_INLINE,
343 !!(wr->send_flags & IB_SEND_INLINE));
344 if (wr->send_flags & IB_SEND_INLINE)
345 return set_rc_inl(qp, wr, rc_sq_wqe, sge_ind);
346
347 if (valid_num_sge <= HNS_ROCE_SGE_IN_WQE) {
348 for (i = 0; i < wr->num_sge; i++) {
349 if (likely(wr->sg_list[i].length)) {
350 set_data_seg_v2(dseg, wr->sg_list + i);
351 dseg++;
352 }
353 }
354 } else {
355 for (i = 0; i < wr->num_sge && j < HNS_ROCE_SGE_IN_WQE; i++) {
356 if (likely(wr->sg_list[i].length)) {
357 set_data_seg_v2(dseg, wr->sg_list + i);
358 dseg++;
359 j++;
360 }
361 }
362
363 set_extend_sge(qp, wr->sg_list + i, sge_ind,
364 valid_num_sge - HNS_ROCE_SGE_IN_WQE);
365 }
366
367 hr_reg_write(rc_sq_wqe, RC_SEND_WQE_SGE_NUM, valid_num_sge);
368
369 return 0;
370 }
371
check_send_valid(struct hns_roce_dev * hr_dev,struct hns_roce_qp * hr_qp)372 static int check_send_valid(struct hns_roce_dev *hr_dev,
373 struct hns_roce_qp *hr_qp)
374 {
375 if (unlikely(hr_qp->state == IB_QPS_RESET ||
376 hr_qp->state == IB_QPS_INIT ||
377 hr_qp->state == IB_QPS_RTR))
378 return -EINVAL;
379 else if (unlikely(hr_dev->state >= HNS_ROCE_DEVICE_STATE_RST_DOWN))
380 return -EIO;
381
382 return 0;
383 }
384
calc_wr_sge_num(const struct ib_send_wr * wr,unsigned int * sge_len)385 static unsigned int calc_wr_sge_num(const struct ib_send_wr *wr,
386 unsigned int *sge_len)
387 {
388 unsigned int valid_num = 0;
389 unsigned int len = 0;
390 int i;
391
392 for (i = 0; i < wr->num_sge; i++) {
393 if (likely(wr->sg_list[i].length)) {
394 len += wr->sg_list[i].length;
395 valid_num++;
396 }
397 }
398
399 *sge_len = len;
400 return valid_num;
401 }
402
get_immtdata(const struct ib_send_wr * wr)403 static __le32 get_immtdata(const struct ib_send_wr *wr)
404 {
405 switch (wr->opcode) {
406 case IB_WR_SEND_WITH_IMM:
407 case IB_WR_RDMA_WRITE_WITH_IMM:
408 return cpu_to_le32(be32_to_cpu(wr->ex.imm_data));
409 default:
410 return 0;
411 }
412 }
413
set_ud_opcode(struct hns_roce_v2_ud_send_wqe * ud_sq_wqe,const struct ib_send_wr * wr)414 static int set_ud_opcode(struct hns_roce_v2_ud_send_wqe *ud_sq_wqe,
415 const struct ib_send_wr *wr)
416 {
417 u32 ib_op = wr->opcode;
418
419 if (ib_op != IB_WR_SEND && ib_op != IB_WR_SEND_WITH_IMM)
420 return -EINVAL;
421
422 ud_sq_wqe->immtdata = get_immtdata(wr);
423
424 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_OPCODE, to_hr_opcode(ib_op));
425
426 return 0;
427 }
428
fill_ud_av(struct hns_roce_v2_ud_send_wqe * ud_sq_wqe,struct hns_roce_ah * ah)429 static int fill_ud_av(struct hns_roce_v2_ud_send_wqe *ud_sq_wqe,
430 struct hns_roce_ah *ah)
431 {
432 struct ib_device *ib_dev = ah->ibah.device;
433 struct hns_roce_dev *hr_dev = to_hr_dev(ib_dev);
434
435 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_UDPSPN, ah->av.udp_sport);
436 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_HOPLIMIT, ah->av.hop_limit);
437 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_TCLASS, ah->av.tclass);
438 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_FLOW_LABEL, ah->av.flowlabel);
439 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_SL, ah->av.sl);
440
441 ud_sq_wqe->sgid_index = ah->av.gid_index;
442
443 memcpy(ud_sq_wqe->dmac, ah->av.mac, ETH_ALEN);
444 memcpy(ud_sq_wqe->dgid, ah->av.dgid, GID_LEN_V2);
445
446 if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09)
447 return 0;
448
449 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_VLAN_EN, ah->av.vlan_en);
450 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_VLAN, ah->av.vlan_id);
451
452 return 0;
453 }
454
set_ud_wqe(struct hns_roce_qp * qp,const struct ib_send_wr * wr,void * wqe,unsigned int * sge_idx,unsigned int owner_bit)455 static inline int set_ud_wqe(struct hns_roce_qp *qp,
456 const struct ib_send_wr *wr,
457 void *wqe, unsigned int *sge_idx,
458 unsigned int owner_bit)
459 {
460 struct hns_roce_ah *ah = to_hr_ah(ud_wr(wr)->ah);
461 struct hns_roce_v2_ud_send_wqe *ud_sq_wqe = wqe;
462 unsigned int curr_idx = *sge_idx;
463 unsigned int valid_num_sge;
464 u32 msg_len = 0;
465 int ret;
466
467 valid_num_sge = calc_wr_sge_num(wr, &msg_len);
468
469 ret = set_ud_opcode(ud_sq_wqe, wr);
470 if (WARN_ON_ONCE(ret))
471 return ret;
472
473 ud_sq_wqe->msg_len = cpu_to_le32(msg_len);
474
475 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_CQE,
476 !!(wr->send_flags & IB_SEND_SIGNALED));
477 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_SE,
478 !!(wr->send_flags & IB_SEND_SOLICITED));
479
480 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_PD, to_hr_pd(qp->ibqp.pd)->pdn);
481 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_SGE_NUM, valid_num_sge);
482 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_MSG_START_SGE_IDX,
483 curr_idx & (qp->sge.sge_cnt - 1));
484
485 ud_sq_wqe->qkey = cpu_to_le32(ud_wr(wr)->remote_qkey & 0x80000000 ?
486 qp->qkey : ud_wr(wr)->remote_qkey);
487 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_DQPN, ud_wr(wr)->remote_qpn);
488
489 ret = fill_ud_av(ud_sq_wqe, ah);
490 if (ret)
491 return ret;
492
493 qp->sl = to_hr_ah(ud_wr(wr)->ah)->av.sl;
494
495 set_extend_sge(qp, wr->sg_list, &curr_idx, valid_num_sge);
496
497 /*
498 * The pipeline can sequentially post all valid WQEs into WQ buffer,
499 * including new WQEs waiting for the doorbell to update the PI again.
500 * Therefore, the owner bit of WQE MUST be updated after all fields
501 * and extSGEs have been written into DDR instead of cache.
502 */
503 if (qp->en_flags & HNS_ROCE_QP_CAP_OWNER_DB)
504 dma_wmb();
505
506 *sge_idx = curr_idx;
507 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_OWNER, owner_bit);
508
509 return 0;
510 }
511
set_rc_opcode(struct hns_roce_dev * hr_dev,struct hns_roce_v2_rc_send_wqe * rc_sq_wqe,const struct ib_send_wr * wr)512 static int set_rc_opcode(struct hns_roce_dev *hr_dev,
513 struct hns_roce_v2_rc_send_wqe *rc_sq_wqe,
514 const struct ib_send_wr *wr)
515 {
516 u32 ib_op = wr->opcode;
517 int ret = 0;
518
519 rc_sq_wqe->immtdata = get_immtdata(wr);
520
521 switch (ib_op) {
522 case IB_WR_RDMA_READ:
523 case IB_WR_RDMA_WRITE:
524 case IB_WR_RDMA_WRITE_WITH_IMM:
525 rc_sq_wqe->rkey = cpu_to_le32(rdma_wr(wr)->rkey);
526 rc_sq_wqe->va = cpu_to_le64(rdma_wr(wr)->remote_addr);
527 break;
528 case IB_WR_SEND:
529 case IB_WR_SEND_WITH_IMM:
530 break;
531 case IB_WR_ATOMIC_CMP_AND_SWP:
532 case IB_WR_ATOMIC_FETCH_AND_ADD:
533 rc_sq_wqe->rkey = cpu_to_le32(atomic_wr(wr)->rkey);
534 rc_sq_wqe->va = cpu_to_le64(atomic_wr(wr)->remote_addr);
535 break;
536 case IB_WR_REG_MR:
537 if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09)
538 set_frmr_seg(rc_sq_wqe, reg_wr(wr));
539 else
540 ret = -EOPNOTSUPP;
541 break;
542 case IB_WR_SEND_WITH_INV:
543 rc_sq_wqe->inv_key = cpu_to_le32(wr->ex.invalidate_rkey);
544 break;
545 default:
546 ret = -EINVAL;
547 }
548
549 if (unlikely(ret))
550 return ret;
551
552 hr_reg_write(rc_sq_wqe, RC_SEND_WQE_OPCODE, to_hr_opcode(ib_op));
553
554 return ret;
555 }
556
set_rc_wqe(struct hns_roce_qp * qp,const struct ib_send_wr * wr,void * wqe,unsigned int * sge_idx,unsigned int owner_bit)557 static inline int set_rc_wqe(struct hns_roce_qp *qp,
558 const struct ib_send_wr *wr,
559 void *wqe, unsigned int *sge_idx,
560 unsigned int owner_bit)
561 {
562 struct hns_roce_dev *hr_dev = to_hr_dev(qp->ibqp.device);
563 struct hns_roce_v2_rc_send_wqe *rc_sq_wqe = wqe;
564 unsigned int curr_idx = *sge_idx;
565 unsigned int valid_num_sge;
566 u32 msg_len = 0;
567 int ret;
568
569 valid_num_sge = calc_wr_sge_num(wr, &msg_len);
570
571 rc_sq_wqe->msg_len = cpu_to_le32(msg_len);
572
573 ret = set_rc_opcode(hr_dev, rc_sq_wqe, wr);
574 if (WARN_ON_ONCE(ret))
575 return ret;
576
577 hr_reg_write(rc_sq_wqe, RC_SEND_WQE_SO,
578 (wr->send_flags & IB_SEND_FENCE) ? 1 : 0);
579
580 hr_reg_write(rc_sq_wqe, RC_SEND_WQE_SE,
581 (wr->send_flags & IB_SEND_SOLICITED) ? 1 : 0);
582
583 hr_reg_write(rc_sq_wqe, RC_SEND_WQE_CQE,
584 (wr->send_flags & IB_SEND_SIGNALED) ? 1 : 0);
585
586 if (wr->opcode == IB_WR_ATOMIC_CMP_AND_SWP ||
587 wr->opcode == IB_WR_ATOMIC_FETCH_AND_ADD) {
588 if (msg_len != ATOMIC_WR_LEN)
589 return -EINVAL;
590 set_atomic_seg(wr, rc_sq_wqe, valid_num_sge);
591 } else if (wr->opcode != IB_WR_REG_MR) {
592 ret = set_rwqe_data_seg(&qp->ibqp, wr, rc_sq_wqe,
593 &curr_idx, valid_num_sge);
594 if (ret)
595 return ret;
596 }
597
598 /*
599 * The pipeline can sequentially post all valid WQEs into WQ buffer,
600 * including new WQEs waiting for the doorbell to update the PI again.
601 * Therefore, the owner bit of WQE MUST be updated after all fields
602 * and extSGEs have been written into DDR instead of cache.
603 */
604 if (qp->en_flags & HNS_ROCE_QP_CAP_OWNER_DB)
605 dma_wmb();
606
607 *sge_idx = curr_idx;
608 hr_reg_write(rc_sq_wqe, RC_SEND_WQE_OWNER, owner_bit);
609
610 return ret;
611 }
612
update_sq_db(struct hns_roce_dev * hr_dev,struct hns_roce_qp * qp)613 static inline void update_sq_db(struct hns_roce_dev *hr_dev,
614 struct hns_roce_qp *qp)
615 {
616 if (unlikely(qp->state == IB_QPS_ERR)) {
617 flush_cqe(hr_dev, qp);
618 } else {
619 struct hns_roce_v2_db sq_db = {};
620
621 hr_reg_write(&sq_db, DB_TAG, qp->qpn);
622 hr_reg_write(&sq_db, DB_CMD, HNS_ROCE_V2_SQ_DB);
623 hr_reg_write(&sq_db, DB_PI, qp->sq.head);
624 hr_reg_write(&sq_db, DB_SL, qp->sl);
625
626 hns_roce_write64(hr_dev, (__le32 *)&sq_db, qp->sq.db_reg);
627 }
628 }
629
update_rq_db(struct hns_roce_dev * hr_dev,struct hns_roce_qp * qp)630 static inline void update_rq_db(struct hns_roce_dev *hr_dev,
631 struct hns_roce_qp *qp)
632 {
633 if (unlikely(qp->state == IB_QPS_ERR)) {
634 flush_cqe(hr_dev, qp);
635 } else {
636 if (likely(qp->en_flags & HNS_ROCE_QP_CAP_RQ_RECORD_DB)) {
637 *qp->rdb.db_record =
638 qp->rq.head & V2_DB_PRODUCER_IDX_M;
639 } else {
640 struct hns_roce_v2_db rq_db = {};
641
642 hr_reg_write(&rq_db, DB_TAG, qp->qpn);
643 hr_reg_write(&rq_db, DB_CMD, HNS_ROCE_V2_RQ_DB);
644 hr_reg_write(&rq_db, DB_PI, qp->rq.head);
645
646 hns_roce_write64(hr_dev, (__le32 *)&rq_db,
647 qp->rq.db_reg);
648 }
649 }
650 }
651
hns_roce_write512(struct hns_roce_dev * hr_dev,u64 * val,u64 __iomem * dest)652 static void hns_roce_write512(struct hns_roce_dev *hr_dev, u64 *val,
653 u64 __iomem *dest)
654 {
655 #define HNS_ROCE_WRITE_TIMES 8
656 struct hns_roce_v2_priv *priv = (struct hns_roce_v2_priv *)hr_dev->priv;
657 struct hnae3_handle *handle = priv->handle;
658 const struct hnae3_ae_ops *ops = handle->ae_algo->ops;
659 int i;
660
661 if (!hr_dev->dis_db && !ops->get_hw_reset_stat(handle))
662 for (i = 0; i < HNS_ROCE_WRITE_TIMES; i++)
663 writeq_relaxed(*(val + i), dest + i);
664 }
665
write_dwqe(struct hns_roce_dev * hr_dev,struct hns_roce_qp * qp,void * wqe)666 static void write_dwqe(struct hns_roce_dev *hr_dev, struct hns_roce_qp *qp,
667 void *wqe)
668 {
669 #define HNS_ROCE_SL_SHIFT 2
670 struct hns_roce_v2_rc_send_wqe *rc_sq_wqe = wqe;
671
672 if (unlikely(qp->state == IB_QPS_ERR)) {
673 flush_cqe(hr_dev, qp);
674 return;
675 }
676 /* All kinds of DirectWQE have the same header field layout */
677 hr_reg_enable(rc_sq_wqe, RC_SEND_WQE_FLAG);
678 hr_reg_write(rc_sq_wqe, RC_SEND_WQE_DB_SL_L, qp->sl);
679 hr_reg_write(rc_sq_wqe, RC_SEND_WQE_DB_SL_H,
680 qp->sl >> HNS_ROCE_SL_SHIFT);
681 hr_reg_write(rc_sq_wqe, RC_SEND_WQE_WQE_INDEX, qp->sq.head);
682
683 hns_roce_write512(hr_dev, wqe, qp->sq.db_reg);
684 }
685
hns_roce_v2_post_send(struct ib_qp * ibqp,const struct ib_send_wr * wr,const struct ib_send_wr ** bad_wr)686 static int hns_roce_v2_post_send(struct ib_qp *ibqp,
687 const struct ib_send_wr *wr,
688 const struct ib_send_wr **bad_wr)
689 {
690 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
691 struct ib_device *ibdev = &hr_dev->ib_dev;
692 struct hns_roce_qp *qp = to_hr_qp(ibqp);
693 unsigned long flags = 0;
694 unsigned int owner_bit;
695 unsigned int sge_idx;
696 unsigned int wqe_idx;
697 void *wqe = NULL;
698 u32 nreq;
699 int ret;
700
701 spin_lock_irqsave(&qp->sq.lock, flags);
702
703 ret = check_send_valid(hr_dev, qp);
704 if (unlikely(ret)) {
705 *bad_wr = wr;
706 nreq = 0;
707 goto out;
708 }
709
710 sge_idx = qp->next_sge;
711
712 for (nreq = 0; wr; ++nreq, wr = wr->next) {
713 if (hns_roce_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq)) {
714 ret = -ENOMEM;
715 *bad_wr = wr;
716 goto out;
717 }
718
719 wqe_idx = (qp->sq.head + nreq) & (qp->sq.wqe_cnt - 1);
720
721 if (unlikely(wr->num_sge > qp->sq.max_gs)) {
722 ibdev_err(ibdev, "num_sge = %d > qp->sq.max_gs = %u.\n",
723 wr->num_sge, qp->sq.max_gs);
724 ret = -EINVAL;
725 *bad_wr = wr;
726 goto out;
727 }
728
729 wqe = hns_roce_get_send_wqe(qp, wqe_idx);
730 qp->sq.wrid[wqe_idx] = wr->wr_id;
731 owner_bit =
732 ~(((qp->sq.head + nreq) >> ilog2(qp->sq.wqe_cnt)) & 0x1);
733
734 /* Corresponding to the QP type, wqe process separately */
735 if (ibqp->qp_type == IB_QPT_RC)
736 ret = set_rc_wqe(qp, wr, wqe, &sge_idx, owner_bit);
737 else
738 ret = set_ud_wqe(qp, wr, wqe, &sge_idx, owner_bit);
739
740 if (unlikely(ret)) {
741 *bad_wr = wr;
742 goto out;
743 }
744 }
745
746 out:
747 if (likely(nreq)) {
748 qp->sq.head += nreq;
749 qp->next_sge = sge_idx;
750
751 if (nreq == 1 && !ret &&
752 (qp->en_flags & HNS_ROCE_QP_CAP_DIRECT_WQE))
753 write_dwqe(hr_dev, qp, wqe);
754 else
755 update_sq_db(hr_dev, qp);
756 }
757
758 spin_unlock_irqrestore(&qp->sq.lock, flags);
759
760 return ret;
761 }
762
check_recv_valid(struct hns_roce_dev * hr_dev,struct hns_roce_qp * hr_qp)763 static int check_recv_valid(struct hns_roce_dev *hr_dev,
764 struct hns_roce_qp *hr_qp)
765 {
766 if (unlikely(hr_dev->state >= HNS_ROCE_DEVICE_STATE_RST_DOWN))
767 return -EIO;
768
769 if (hr_qp->state == IB_QPS_RESET)
770 return -EINVAL;
771
772 return 0;
773 }
774
fill_recv_sge_to_wqe(const struct ib_recv_wr * wr,void * wqe,u32 max_sge,bool rsv)775 static void fill_recv_sge_to_wqe(const struct ib_recv_wr *wr, void *wqe,
776 u32 max_sge, bool rsv)
777 {
778 struct hns_roce_v2_wqe_data_seg *dseg = wqe;
779 u32 i, cnt;
780
781 for (i = 0, cnt = 0; i < wr->num_sge; i++) {
782 /* Skip zero-length sge */
783 if (!wr->sg_list[i].length)
784 continue;
785 set_data_seg_v2(dseg + cnt, wr->sg_list + i);
786 cnt++;
787 }
788
789 /* Fill a reserved sge to make hw stop reading remaining segments */
790 if (rsv) {
791 dseg[cnt].lkey = cpu_to_le32(HNS_ROCE_INVALID_LKEY);
792 dseg[cnt].addr = 0;
793 dseg[cnt].len = cpu_to_le32(HNS_ROCE_INVALID_SGE_LENGTH);
794 } else {
795 /* Clear remaining segments to make ROCEE ignore sges */
796 if (cnt < max_sge)
797 memset(dseg + cnt, 0,
798 (max_sge - cnt) * HNS_ROCE_SGE_SIZE);
799 }
800 }
801
fill_rq_wqe(struct hns_roce_qp * hr_qp,const struct ib_recv_wr * wr,u32 wqe_idx,u32 max_sge)802 static void fill_rq_wqe(struct hns_roce_qp *hr_qp, const struct ib_recv_wr *wr,
803 u32 wqe_idx, u32 max_sge)
804 {
805 void *wqe = NULL;
806
807 wqe = hns_roce_get_recv_wqe(hr_qp, wqe_idx);
808 fill_recv_sge_to_wqe(wr, wqe, max_sge, hr_qp->rq.rsv_sge);
809 }
810
hns_roce_v2_post_recv(struct ib_qp * ibqp,const struct ib_recv_wr * wr,const struct ib_recv_wr ** bad_wr)811 static int hns_roce_v2_post_recv(struct ib_qp *ibqp,
812 const struct ib_recv_wr *wr,
813 const struct ib_recv_wr **bad_wr)
814 {
815 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
816 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
817 struct ib_device *ibdev = &hr_dev->ib_dev;
818 u32 wqe_idx, nreq, max_sge;
819 unsigned long flags;
820 int ret;
821
822 spin_lock_irqsave(&hr_qp->rq.lock, flags);
823
824 ret = check_recv_valid(hr_dev, hr_qp);
825 if (unlikely(ret)) {
826 *bad_wr = wr;
827 nreq = 0;
828 goto out;
829 }
830
831 max_sge = hr_qp->rq.max_gs - hr_qp->rq.rsv_sge;
832 for (nreq = 0; wr; ++nreq, wr = wr->next) {
833 if (unlikely(hns_roce_wq_overflow(&hr_qp->rq, nreq,
834 hr_qp->ibqp.recv_cq))) {
835 ret = -ENOMEM;
836 *bad_wr = wr;
837 goto out;
838 }
839
840 if (unlikely(wr->num_sge > max_sge)) {
841 ibdev_err(ibdev, "num_sge = %d >= max_sge = %u.\n",
842 wr->num_sge, max_sge);
843 ret = -EINVAL;
844 *bad_wr = wr;
845 goto out;
846 }
847
848 wqe_idx = (hr_qp->rq.head + nreq) & (hr_qp->rq.wqe_cnt - 1);
849 fill_rq_wqe(hr_qp, wr, wqe_idx, max_sge);
850 hr_qp->rq.wrid[wqe_idx] = wr->wr_id;
851 }
852
853 out:
854 if (likely(nreq)) {
855 hr_qp->rq.head += nreq;
856
857 update_rq_db(hr_dev, hr_qp);
858 }
859 spin_unlock_irqrestore(&hr_qp->rq.lock, flags);
860
861 return ret;
862 }
863
get_srq_wqe_buf(struct hns_roce_srq * srq,u32 n)864 static void *get_srq_wqe_buf(struct hns_roce_srq *srq, u32 n)
865 {
866 return hns_roce_buf_offset(srq->buf_mtr.kmem, n << srq->wqe_shift);
867 }
868
get_idx_buf(struct hns_roce_idx_que * idx_que,u32 n)869 static void *get_idx_buf(struct hns_roce_idx_que *idx_que, u32 n)
870 {
871 return hns_roce_buf_offset(idx_que->mtr.kmem,
872 n << idx_que->entry_shift);
873 }
874
hns_roce_free_srq_wqe(struct hns_roce_srq * srq,u32 wqe_index)875 static void hns_roce_free_srq_wqe(struct hns_roce_srq *srq, u32 wqe_index)
876 {
877 /* always called with interrupts disabled. */
878 spin_lock(&srq->lock);
879
880 bitmap_clear(srq->idx_que.bitmap, wqe_index, 1);
881 srq->idx_que.tail++;
882
883 spin_unlock(&srq->lock);
884 }
885
hns_roce_srqwq_overflow(struct hns_roce_srq * srq)886 static int hns_roce_srqwq_overflow(struct hns_roce_srq *srq)
887 {
888 struct hns_roce_idx_que *idx_que = &srq->idx_que;
889
890 return idx_que->head - idx_que->tail >= srq->wqe_cnt;
891 }
892
check_post_srq_valid(struct hns_roce_srq * srq,u32 max_sge,const struct ib_recv_wr * wr)893 static int check_post_srq_valid(struct hns_roce_srq *srq, u32 max_sge,
894 const struct ib_recv_wr *wr)
895 {
896 struct ib_device *ib_dev = srq->ibsrq.device;
897
898 if (unlikely(wr->num_sge > max_sge)) {
899 ibdev_err(ib_dev,
900 "failed to check sge, wr->num_sge = %d, max_sge = %u.\n",
901 wr->num_sge, max_sge);
902 return -EINVAL;
903 }
904
905 if (unlikely(hns_roce_srqwq_overflow(srq))) {
906 ibdev_err(ib_dev,
907 "failed to check srqwq status, srqwq is full.\n");
908 return -ENOMEM;
909 }
910
911 return 0;
912 }
913
get_srq_wqe_idx(struct hns_roce_srq * srq,u32 * wqe_idx)914 static int get_srq_wqe_idx(struct hns_roce_srq *srq, u32 *wqe_idx)
915 {
916 struct hns_roce_idx_que *idx_que = &srq->idx_que;
917 u32 pos;
918
919 pos = find_first_zero_bit(idx_que->bitmap, srq->wqe_cnt);
920 if (unlikely(pos == srq->wqe_cnt))
921 return -ENOSPC;
922
923 bitmap_set(idx_que->bitmap, pos, 1);
924 *wqe_idx = pos;
925 return 0;
926 }
927
fill_wqe_idx(struct hns_roce_srq * srq,unsigned int wqe_idx)928 static void fill_wqe_idx(struct hns_roce_srq *srq, unsigned int wqe_idx)
929 {
930 struct hns_roce_idx_que *idx_que = &srq->idx_que;
931 unsigned int head;
932 __le32 *buf;
933
934 head = idx_que->head & (srq->wqe_cnt - 1);
935
936 buf = get_idx_buf(idx_que, head);
937 *buf = cpu_to_le32(wqe_idx);
938
939 idx_que->head++;
940 }
941
update_srq_db(struct hns_roce_srq * srq)942 static void update_srq_db(struct hns_roce_srq *srq)
943 {
944 struct hns_roce_dev *hr_dev = to_hr_dev(srq->ibsrq.device);
945 struct hns_roce_v2_db db = {};
946
947 hr_reg_write(&db, DB_TAG, srq->srqn);
948 hr_reg_write(&db, DB_CMD, HNS_ROCE_V2_SRQ_DB);
949 hr_reg_write(&db, DB_PI, srq->idx_que.head);
950
951 hns_roce_write64(hr_dev, (__le32 *)&db, srq->db_reg);
952 }
953
hns_roce_v2_post_srq_recv(struct ib_srq * ibsrq,const struct ib_recv_wr * wr,const struct ib_recv_wr ** bad_wr)954 static int hns_roce_v2_post_srq_recv(struct ib_srq *ibsrq,
955 const struct ib_recv_wr *wr,
956 const struct ib_recv_wr **bad_wr)
957 {
958 struct hns_roce_srq *srq = to_hr_srq(ibsrq);
959 unsigned long flags;
960 int ret = 0;
961 u32 max_sge;
962 u32 wqe_idx;
963 void *wqe;
964 u32 nreq;
965
966 spin_lock_irqsave(&srq->lock, flags);
967
968 max_sge = srq->max_gs - srq->rsv_sge;
969 for (nreq = 0; wr; ++nreq, wr = wr->next) {
970 ret = check_post_srq_valid(srq, max_sge, wr);
971 if (ret) {
972 *bad_wr = wr;
973 break;
974 }
975
976 ret = get_srq_wqe_idx(srq, &wqe_idx);
977 if (unlikely(ret)) {
978 *bad_wr = wr;
979 break;
980 }
981
982 wqe = get_srq_wqe_buf(srq, wqe_idx);
983 fill_recv_sge_to_wqe(wr, wqe, max_sge, srq->rsv_sge);
984 fill_wqe_idx(srq, wqe_idx);
985 srq->wrid[wqe_idx] = wr->wr_id;
986 }
987
988 if (likely(nreq)) {
989 if (srq->cap_flags & HNS_ROCE_SRQ_CAP_RECORD_DB)
990 *srq->rdb.db_record = srq->idx_que.head &
991 V2_DB_PRODUCER_IDX_M;
992 else
993 update_srq_db(srq);
994 }
995
996 spin_unlock_irqrestore(&srq->lock, flags);
997
998 return ret;
999 }
1000
hns_roce_v2_cmd_hw_reseted(struct hns_roce_dev * hr_dev,unsigned long instance_stage,unsigned long reset_stage)1001 static u32 hns_roce_v2_cmd_hw_reseted(struct hns_roce_dev *hr_dev,
1002 unsigned long instance_stage,
1003 unsigned long reset_stage)
1004 {
1005 /* When hardware reset has been completed once or more, we should stop
1006 * sending mailbox&cmq&doorbell to hardware. If now in .init_instance()
1007 * function, we should exit with error. If now at HNAE3_INIT_CLIENT
1008 * stage of soft reset process, we should exit with error, and then
1009 * HNAE3_INIT_CLIENT related process can rollback the operation like
1010 * notifing hardware to free resources, HNAE3_INIT_CLIENT related
1011 * process will exit with error to notify NIC driver to reschedule soft
1012 * reset process once again.
1013 */
1014 hr_dev->is_reset = true;
1015 hr_dev->dis_db = true;
1016
1017 if (reset_stage == HNS_ROCE_STATE_RST_INIT ||
1018 instance_stage == HNS_ROCE_STATE_INIT)
1019 return CMD_RST_PRC_EBUSY;
1020
1021 return CMD_RST_PRC_SUCCESS;
1022 }
1023
hns_roce_v2_cmd_hw_resetting(struct hns_roce_dev * hr_dev,unsigned long instance_stage,unsigned long reset_stage)1024 static u32 hns_roce_v2_cmd_hw_resetting(struct hns_roce_dev *hr_dev,
1025 unsigned long instance_stage,
1026 unsigned long reset_stage)
1027 {
1028 #define HW_RESET_TIMEOUT_US 1000000
1029 #define HW_RESET_SLEEP_US 1000
1030
1031 struct hns_roce_v2_priv *priv = hr_dev->priv;
1032 struct hnae3_handle *handle = priv->handle;
1033 const struct hnae3_ae_ops *ops = handle->ae_algo->ops;
1034 unsigned long val;
1035 int ret;
1036
1037 /* When hardware reset is detected, we should stop sending mailbox&cmq&
1038 * doorbell to hardware. If now in .init_instance() function, we should
1039 * exit with error. If now at HNAE3_INIT_CLIENT stage of soft reset
1040 * process, we should exit with error, and then HNAE3_INIT_CLIENT
1041 * related process can rollback the operation like notifing hardware to
1042 * free resources, HNAE3_INIT_CLIENT related process will exit with
1043 * error to notify NIC driver to reschedule soft reset process once
1044 * again.
1045 */
1046 hr_dev->dis_db = true;
1047
1048 ret = read_poll_timeout(ops->ae_dev_reset_cnt, val,
1049 val > hr_dev->reset_cnt, HW_RESET_SLEEP_US,
1050 HW_RESET_TIMEOUT_US, false, handle);
1051 if (!ret)
1052 hr_dev->is_reset = true;
1053
1054 if (!hr_dev->is_reset || reset_stage == HNS_ROCE_STATE_RST_INIT ||
1055 instance_stage == HNS_ROCE_STATE_INIT)
1056 return CMD_RST_PRC_EBUSY;
1057
1058 return CMD_RST_PRC_SUCCESS;
1059 }
1060
hns_roce_v2_cmd_sw_resetting(struct hns_roce_dev * hr_dev)1061 static u32 hns_roce_v2_cmd_sw_resetting(struct hns_roce_dev *hr_dev)
1062 {
1063 struct hns_roce_v2_priv *priv = hr_dev->priv;
1064 struct hnae3_handle *handle = priv->handle;
1065 const struct hnae3_ae_ops *ops = handle->ae_algo->ops;
1066
1067 /* When software reset is detected at .init_instance() function, we
1068 * should stop sending mailbox&cmq&doorbell to hardware, and exit
1069 * with error.
1070 */
1071 hr_dev->dis_db = true;
1072 if (ops->ae_dev_reset_cnt(handle) != hr_dev->reset_cnt)
1073 hr_dev->is_reset = true;
1074
1075 return CMD_RST_PRC_EBUSY;
1076 }
1077
check_aedev_reset_status(struct hns_roce_dev * hr_dev,struct hnae3_handle * handle)1078 static u32 check_aedev_reset_status(struct hns_roce_dev *hr_dev,
1079 struct hnae3_handle *handle)
1080 {
1081 const struct hnae3_ae_ops *ops = handle->ae_algo->ops;
1082 unsigned long instance_stage; /* the current instance stage */
1083 unsigned long reset_stage; /* the current reset stage */
1084 unsigned long reset_cnt;
1085 bool sw_resetting;
1086 bool hw_resetting;
1087
1088 /* Get information about reset from NIC driver or RoCE driver itself,
1089 * the meaning of the following variables from NIC driver are described
1090 * as below:
1091 * reset_cnt -- The count value of completed hardware reset.
1092 * hw_resetting -- Whether hardware device is resetting now.
1093 * sw_resetting -- Whether NIC's software reset process is running now.
1094 */
1095 instance_stage = handle->rinfo.instance_state;
1096 reset_stage = handle->rinfo.reset_state;
1097 reset_cnt = ops->ae_dev_reset_cnt(handle);
1098 if (reset_cnt != hr_dev->reset_cnt)
1099 return hns_roce_v2_cmd_hw_reseted(hr_dev, instance_stage,
1100 reset_stage);
1101
1102 hw_resetting = ops->get_cmdq_stat(handle);
1103 if (hw_resetting)
1104 return hns_roce_v2_cmd_hw_resetting(hr_dev, instance_stage,
1105 reset_stage);
1106
1107 sw_resetting = ops->ae_dev_resetting(handle);
1108 if (sw_resetting && instance_stage == HNS_ROCE_STATE_INIT)
1109 return hns_roce_v2_cmd_sw_resetting(hr_dev);
1110
1111 return CMD_RST_PRC_OTHERS;
1112 }
1113
check_device_is_in_reset(struct hns_roce_dev * hr_dev)1114 static bool check_device_is_in_reset(struct hns_roce_dev *hr_dev)
1115 {
1116 struct hns_roce_v2_priv *priv = hr_dev->priv;
1117 struct hnae3_handle *handle = priv->handle;
1118 const struct hnae3_ae_ops *ops = handle->ae_algo->ops;
1119
1120 if (hr_dev->reset_cnt != ops->ae_dev_reset_cnt(handle))
1121 return true;
1122
1123 if (ops->get_hw_reset_stat(handle))
1124 return true;
1125
1126 if (ops->ae_dev_resetting(handle))
1127 return true;
1128
1129 return false;
1130 }
1131
v2_chk_mbox_is_avail(struct hns_roce_dev * hr_dev,bool * busy)1132 static bool v2_chk_mbox_is_avail(struct hns_roce_dev *hr_dev, bool *busy)
1133 {
1134 struct hns_roce_v2_priv *priv = hr_dev->priv;
1135 u32 status;
1136
1137 if (hr_dev->is_reset)
1138 status = CMD_RST_PRC_SUCCESS;
1139 else
1140 status = check_aedev_reset_status(hr_dev, priv->handle);
1141
1142 *busy = (status == CMD_RST_PRC_EBUSY);
1143
1144 return status == CMD_RST_PRC_OTHERS;
1145 }
1146
hns_roce_alloc_cmq_desc(struct hns_roce_dev * hr_dev,struct hns_roce_v2_cmq_ring * ring)1147 static int hns_roce_alloc_cmq_desc(struct hns_roce_dev *hr_dev,
1148 struct hns_roce_v2_cmq_ring *ring)
1149 {
1150 int size = ring->desc_num * sizeof(struct hns_roce_cmq_desc);
1151
1152 ring->desc = dma_alloc_coherent(hr_dev->dev, size,
1153 &ring->desc_dma_addr, GFP_KERNEL);
1154 if (!ring->desc)
1155 return -ENOMEM;
1156
1157 return 0;
1158 }
1159
hns_roce_free_cmq_desc(struct hns_roce_dev * hr_dev,struct hns_roce_v2_cmq_ring * ring)1160 static void hns_roce_free_cmq_desc(struct hns_roce_dev *hr_dev,
1161 struct hns_roce_v2_cmq_ring *ring)
1162 {
1163 dma_free_coherent(hr_dev->dev,
1164 ring->desc_num * sizeof(struct hns_roce_cmq_desc),
1165 ring->desc, ring->desc_dma_addr);
1166
1167 ring->desc_dma_addr = 0;
1168 }
1169
init_csq(struct hns_roce_dev * hr_dev,struct hns_roce_v2_cmq_ring * csq)1170 static int init_csq(struct hns_roce_dev *hr_dev,
1171 struct hns_roce_v2_cmq_ring *csq)
1172 {
1173 dma_addr_t dma;
1174 int ret;
1175
1176 csq->desc_num = CMD_CSQ_DESC_NUM;
1177 spin_lock_init(&csq->lock);
1178 csq->flag = TYPE_CSQ;
1179 csq->head = 0;
1180
1181 ret = hns_roce_alloc_cmq_desc(hr_dev, csq);
1182 if (ret)
1183 return ret;
1184
1185 dma = csq->desc_dma_addr;
1186 roce_write(hr_dev, ROCEE_TX_CMQ_BASEADDR_L_REG, lower_32_bits(dma));
1187 roce_write(hr_dev, ROCEE_TX_CMQ_BASEADDR_H_REG, upper_32_bits(dma));
1188 roce_write(hr_dev, ROCEE_TX_CMQ_DEPTH_REG,
1189 (u32)csq->desc_num >> HNS_ROCE_CMQ_DESC_NUM_S);
1190
1191 /* Make sure to write CI first and then PI */
1192 roce_write(hr_dev, ROCEE_TX_CMQ_CI_REG, 0);
1193 roce_write(hr_dev, ROCEE_TX_CMQ_PI_REG, 0);
1194
1195 return 0;
1196 }
1197
hns_roce_v2_cmq_init(struct hns_roce_dev * hr_dev)1198 static int hns_roce_v2_cmq_init(struct hns_roce_dev *hr_dev)
1199 {
1200 struct hns_roce_v2_priv *priv = hr_dev->priv;
1201 int ret;
1202
1203 priv->cmq.tx_timeout = HNS_ROCE_CMQ_TX_TIMEOUT;
1204
1205 ret = init_csq(hr_dev, &priv->cmq.csq);
1206 if (ret)
1207 dev_err(hr_dev->dev, "failed to init CSQ, ret = %d.\n", ret);
1208
1209 return ret;
1210 }
1211
hns_roce_v2_cmq_exit(struct hns_roce_dev * hr_dev)1212 static void hns_roce_v2_cmq_exit(struct hns_roce_dev *hr_dev)
1213 {
1214 struct hns_roce_v2_priv *priv = hr_dev->priv;
1215
1216 hns_roce_free_cmq_desc(hr_dev, &priv->cmq.csq);
1217 }
1218
hns_roce_cmq_setup_basic_desc(struct hns_roce_cmq_desc * desc,enum hns_roce_opcode_type opcode,bool is_read)1219 static void hns_roce_cmq_setup_basic_desc(struct hns_roce_cmq_desc *desc,
1220 enum hns_roce_opcode_type opcode,
1221 bool is_read)
1222 {
1223 memset((void *)desc, 0, sizeof(struct hns_roce_cmq_desc));
1224 desc->opcode = cpu_to_le16(opcode);
1225 desc->flag = cpu_to_le16(HNS_ROCE_CMD_FLAG_IN);
1226 if (is_read)
1227 desc->flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_WR);
1228 else
1229 desc->flag &= cpu_to_le16(~HNS_ROCE_CMD_FLAG_WR);
1230 }
1231
hns_roce_cmq_csq_done(struct hns_roce_dev * hr_dev)1232 static int hns_roce_cmq_csq_done(struct hns_roce_dev *hr_dev)
1233 {
1234 u32 tail = roce_read(hr_dev, ROCEE_TX_CMQ_CI_REG);
1235 struct hns_roce_v2_priv *priv = hr_dev->priv;
1236
1237 return tail == priv->cmq.csq.head;
1238 }
1239
update_cmdq_status(struct hns_roce_dev * hr_dev)1240 static void update_cmdq_status(struct hns_roce_dev *hr_dev)
1241 {
1242 struct hns_roce_v2_priv *priv = hr_dev->priv;
1243 struct hnae3_handle *handle = priv->handle;
1244
1245 if (handle->rinfo.reset_state == HNS_ROCE_STATE_RST_INIT ||
1246 handle->rinfo.instance_state == HNS_ROCE_STATE_INIT)
1247 hr_dev->cmd.state = HNS_ROCE_CMDQ_STATE_FATAL_ERR;
1248 }
1249
hns_roce_cmd_err_convert_errno(u16 desc_ret)1250 static int hns_roce_cmd_err_convert_errno(u16 desc_ret)
1251 {
1252 struct hns_roce_cmd_errcode errcode_table[] = {
1253 {CMD_EXEC_SUCCESS, 0},
1254 {CMD_NO_AUTH, -EPERM},
1255 {CMD_NOT_EXIST, -EOPNOTSUPP},
1256 {CMD_CRQ_FULL, -EXFULL},
1257 {CMD_NEXT_ERR, -ENOSR},
1258 {CMD_NOT_EXEC, -ENOTBLK},
1259 {CMD_PARA_ERR, -EINVAL},
1260 {CMD_RESULT_ERR, -ERANGE},
1261 {CMD_TIMEOUT, -ETIME},
1262 {CMD_HILINK_ERR, -ENOLINK},
1263 {CMD_INFO_ILLEGAL, -ENXIO},
1264 {CMD_INVALID, -EBADR},
1265 };
1266 u16 i;
1267
1268 for (i = 0; i < ARRAY_SIZE(errcode_table); i++)
1269 if (desc_ret == errcode_table[i].return_status)
1270 return errcode_table[i].errno;
1271 return -EIO;
1272 }
1273
hns_roce_cmdq_tx_timeout(u16 opcode,u32 tx_timeout)1274 static u32 hns_roce_cmdq_tx_timeout(u16 opcode, u32 tx_timeout)
1275 {
1276 static const struct hns_roce_cmdq_tx_timeout_map cmdq_tx_timeout[] = {
1277 {HNS_ROCE_OPC_POST_MB, HNS_ROCE_OPC_POST_MB_TIMEOUT},
1278 };
1279 int i;
1280
1281 for (i = 0; i < ARRAY_SIZE(cmdq_tx_timeout); i++)
1282 if (cmdq_tx_timeout[i].opcode == opcode)
1283 return cmdq_tx_timeout[i].tx_timeout;
1284
1285 return tx_timeout;
1286 }
1287
hns_roce_wait_csq_done(struct hns_roce_dev * hr_dev,u32 tx_timeout)1288 static void hns_roce_wait_csq_done(struct hns_roce_dev *hr_dev, u32 tx_timeout)
1289 {
1290 u32 timeout = 0;
1291
1292 do {
1293 if (hns_roce_cmq_csq_done(hr_dev))
1294 break;
1295 udelay(1);
1296 } while (++timeout < tx_timeout);
1297 }
1298
__hns_roce_cmq_send_one(struct hns_roce_dev * hr_dev,struct hns_roce_cmq_desc * desc,int num,u32 tx_timeout)1299 static int __hns_roce_cmq_send_one(struct hns_roce_dev *hr_dev,
1300 struct hns_roce_cmq_desc *desc,
1301 int num, u32 tx_timeout)
1302 {
1303 struct hns_roce_v2_priv *priv = hr_dev->priv;
1304 struct hns_roce_v2_cmq_ring *csq = &priv->cmq.csq;
1305 u16 desc_ret;
1306 u32 tail;
1307 int ret;
1308 int i;
1309
1310 tail = csq->head;
1311
1312 for (i = 0; i < num; i++) {
1313 csq->desc[csq->head++] = desc[i];
1314 if (csq->head == csq->desc_num)
1315 csq->head = 0;
1316 }
1317
1318 /* Write to hardware */
1319 roce_write(hr_dev, ROCEE_TX_CMQ_PI_REG, csq->head);
1320
1321 atomic64_inc(&hr_dev->dfx_cnt[HNS_ROCE_DFX_CMDS_CNT]);
1322
1323 hns_roce_wait_csq_done(hr_dev, tx_timeout);
1324 if (hns_roce_cmq_csq_done(hr_dev)) {
1325 ret = 0;
1326 for (i = 0; i < num; i++) {
1327 /* check the result of hardware write back */
1328 desc_ret = le16_to_cpu(csq->desc[tail++].retval);
1329 if (tail == csq->desc_num)
1330 tail = 0;
1331 if (likely(desc_ret == CMD_EXEC_SUCCESS))
1332 continue;
1333
1334 ret = hns_roce_cmd_err_convert_errno(desc_ret);
1335 }
1336 } else {
1337 /* FW/HW reset or incorrect number of desc */
1338 tail = roce_read(hr_dev, ROCEE_TX_CMQ_CI_REG);
1339 dev_warn(hr_dev->dev, "CMDQ move tail from %u to %u.\n",
1340 csq->head, tail);
1341 csq->head = tail;
1342
1343 update_cmdq_status(hr_dev);
1344
1345 ret = -EAGAIN;
1346 }
1347
1348 if (ret)
1349 atomic64_inc(&hr_dev->dfx_cnt[HNS_ROCE_DFX_CMDS_ERR_CNT]);
1350
1351 return ret;
1352 }
1353
__hns_roce_cmq_send(struct hns_roce_dev * hr_dev,struct hns_roce_cmq_desc * desc,int num)1354 static int __hns_roce_cmq_send(struct hns_roce_dev *hr_dev,
1355 struct hns_roce_cmq_desc *desc, int num)
1356 {
1357 struct hns_roce_v2_priv *priv = hr_dev->priv;
1358 struct hns_roce_v2_cmq_ring *csq = &priv->cmq.csq;
1359 u16 opcode = le16_to_cpu(desc->opcode);
1360 u32 tx_timeout = hns_roce_cmdq_tx_timeout(opcode, priv->cmq.tx_timeout);
1361 u8 try_cnt = HNS_ROCE_OPC_POST_MB_TRY_CNT;
1362 u32 rsv_tail;
1363 int ret;
1364 int i;
1365
1366 while (try_cnt) {
1367 try_cnt--;
1368
1369 spin_lock_bh(&csq->lock);
1370 rsv_tail = csq->head;
1371 ret = __hns_roce_cmq_send_one(hr_dev, desc, num, tx_timeout);
1372 if (opcode == HNS_ROCE_OPC_POST_MB && ret == -ETIME &&
1373 try_cnt) {
1374 spin_unlock_bh(&csq->lock);
1375 mdelay(HNS_ROCE_OPC_POST_MB_RETRY_GAP_MSEC);
1376 continue;
1377 }
1378
1379 for (i = 0; i < num; i++) {
1380 desc[i] = csq->desc[rsv_tail++];
1381 if (rsv_tail == csq->desc_num)
1382 rsv_tail = 0;
1383 }
1384 spin_unlock_bh(&csq->lock);
1385 break;
1386 }
1387
1388 if (ret)
1389 dev_err_ratelimited(hr_dev->dev,
1390 "Cmdq IO error, opcode = 0x%x, return = %d.\n",
1391 opcode, ret);
1392
1393 return ret;
1394 }
1395
hns_roce_cmq_send(struct hns_roce_dev * hr_dev,struct hns_roce_cmq_desc * desc,int num)1396 static int hns_roce_cmq_send(struct hns_roce_dev *hr_dev,
1397 struct hns_roce_cmq_desc *desc, int num)
1398 {
1399 bool busy;
1400 int ret;
1401
1402 if (hr_dev->cmd.state == HNS_ROCE_CMDQ_STATE_FATAL_ERR)
1403 return -EIO;
1404
1405 if (!v2_chk_mbox_is_avail(hr_dev, &busy))
1406 return busy ? -EBUSY : 0;
1407
1408 ret = __hns_roce_cmq_send(hr_dev, desc, num);
1409 if (ret) {
1410 if (!v2_chk_mbox_is_avail(hr_dev, &busy))
1411 return busy ? -EBUSY : 0;
1412 }
1413
1414 return ret;
1415 }
1416
config_hem_ba_to_hw(struct hns_roce_dev * hr_dev,dma_addr_t base_addr,u8 cmd,unsigned long tag)1417 static int config_hem_ba_to_hw(struct hns_roce_dev *hr_dev,
1418 dma_addr_t base_addr, u8 cmd, unsigned long tag)
1419 {
1420 struct hns_roce_cmd_mailbox *mbox;
1421 int ret;
1422
1423 mbox = hns_roce_alloc_cmd_mailbox(hr_dev);
1424 if (IS_ERR(mbox))
1425 return PTR_ERR(mbox);
1426
1427 ret = hns_roce_cmd_mbox(hr_dev, base_addr, mbox->dma, cmd, tag);
1428 hns_roce_free_cmd_mailbox(hr_dev, mbox);
1429 return ret;
1430 }
1431
hns_roce_cmq_query_hw_info(struct hns_roce_dev * hr_dev)1432 static int hns_roce_cmq_query_hw_info(struct hns_roce_dev *hr_dev)
1433 {
1434 struct hns_roce_query_version *resp;
1435 struct hns_roce_cmq_desc desc;
1436 int ret;
1437
1438 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_QUERY_HW_VER, true);
1439 ret = hns_roce_cmq_send(hr_dev, &desc, 1);
1440 if (ret)
1441 return ret;
1442
1443 resp = (struct hns_roce_query_version *)desc.data;
1444 hr_dev->hw_rev = le16_to_cpu(resp->rocee_hw_version);
1445 hr_dev->vendor_id = hr_dev->pci_dev->vendor;
1446
1447 return 0;
1448 }
1449
func_clr_hw_resetting_state(struct hns_roce_dev * hr_dev,struct hnae3_handle * handle)1450 static void func_clr_hw_resetting_state(struct hns_roce_dev *hr_dev,
1451 struct hnae3_handle *handle)
1452 {
1453 const struct hnae3_ae_ops *ops = handle->ae_algo->ops;
1454 unsigned long end;
1455
1456 hr_dev->dis_db = true;
1457
1458 dev_warn(hr_dev->dev,
1459 "func clear is pending, device in resetting state.\n");
1460 end = HNS_ROCE_V2_HW_RST_TIMEOUT;
1461 while (end) {
1462 if (!ops->get_hw_reset_stat(handle)) {
1463 hr_dev->is_reset = true;
1464 dev_info(hr_dev->dev,
1465 "func clear success after reset.\n");
1466 return;
1467 }
1468 msleep(HNS_ROCE_V2_HW_RST_COMPLETION_WAIT);
1469 end -= HNS_ROCE_V2_HW_RST_COMPLETION_WAIT;
1470 }
1471
1472 dev_warn(hr_dev->dev, "func clear failed.\n");
1473 }
1474
func_clr_sw_resetting_state(struct hns_roce_dev * hr_dev,struct hnae3_handle * handle)1475 static void func_clr_sw_resetting_state(struct hns_roce_dev *hr_dev,
1476 struct hnae3_handle *handle)
1477 {
1478 const struct hnae3_ae_ops *ops = handle->ae_algo->ops;
1479 unsigned long end;
1480
1481 hr_dev->dis_db = true;
1482
1483 dev_warn(hr_dev->dev,
1484 "func clear is pending, device in resetting state.\n");
1485 end = HNS_ROCE_V2_HW_RST_TIMEOUT;
1486 while (end) {
1487 if (ops->ae_dev_reset_cnt(handle) !=
1488 hr_dev->reset_cnt) {
1489 hr_dev->is_reset = true;
1490 dev_info(hr_dev->dev,
1491 "func clear success after sw reset\n");
1492 return;
1493 }
1494 msleep(HNS_ROCE_V2_HW_RST_COMPLETION_WAIT);
1495 end -= HNS_ROCE_V2_HW_RST_COMPLETION_WAIT;
1496 }
1497
1498 dev_warn(hr_dev->dev, "func clear failed because of unfinished sw reset\n");
1499 }
1500
hns_roce_func_clr_rst_proc(struct hns_roce_dev * hr_dev,int retval,int flag)1501 static void hns_roce_func_clr_rst_proc(struct hns_roce_dev *hr_dev, int retval,
1502 int flag)
1503 {
1504 struct hns_roce_v2_priv *priv = hr_dev->priv;
1505 struct hnae3_handle *handle = priv->handle;
1506 const struct hnae3_ae_ops *ops = handle->ae_algo->ops;
1507
1508 if (ops->ae_dev_reset_cnt(handle) != hr_dev->reset_cnt) {
1509 hr_dev->dis_db = true;
1510 hr_dev->is_reset = true;
1511 dev_info(hr_dev->dev, "func clear success after reset.\n");
1512 return;
1513 }
1514
1515 if (ops->get_hw_reset_stat(handle)) {
1516 func_clr_hw_resetting_state(hr_dev, handle);
1517 return;
1518 }
1519
1520 if (ops->ae_dev_resetting(handle) &&
1521 handle->rinfo.instance_state == HNS_ROCE_STATE_INIT) {
1522 func_clr_sw_resetting_state(hr_dev, handle);
1523 return;
1524 }
1525
1526 if (retval && !flag)
1527 dev_warn(hr_dev->dev,
1528 "func clear read failed, ret = %d.\n", retval);
1529
1530 dev_warn(hr_dev->dev, "func clear failed.\n");
1531 }
1532
__hns_roce_function_clear(struct hns_roce_dev * hr_dev,int vf_id)1533 static void __hns_roce_function_clear(struct hns_roce_dev *hr_dev, int vf_id)
1534 {
1535 bool fclr_write_fail_flag = false;
1536 struct hns_roce_func_clear *resp;
1537 struct hns_roce_cmq_desc desc;
1538 unsigned long end;
1539 int ret = 0;
1540
1541 if (check_device_is_in_reset(hr_dev))
1542 goto out;
1543
1544 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_FUNC_CLEAR, false);
1545 resp = (struct hns_roce_func_clear *)desc.data;
1546 resp->rst_funcid_en = cpu_to_le32(vf_id);
1547
1548 ret = hns_roce_cmq_send(hr_dev, &desc, 1);
1549 if (ret) {
1550 fclr_write_fail_flag = true;
1551 dev_err(hr_dev->dev, "func clear write failed, ret = %d.\n",
1552 ret);
1553 goto out;
1554 }
1555
1556 msleep(HNS_ROCE_V2_READ_FUNC_CLEAR_FLAG_INTERVAL);
1557 end = HNS_ROCE_V2_FUNC_CLEAR_TIMEOUT_MSECS;
1558 while (end) {
1559 if (check_device_is_in_reset(hr_dev))
1560 goto out;
1561 msleep(HNS_ROCE_V2_READ_FUNC_CLEAR_FLAG_FAIL_WAIT);
1562 end -= HNS_ROCE_V2_READ_FUNC_CLEAR_FLAG_FAIL_WAIT;
1563
1564 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_FUNC_CLEAR,
1565 true);
1566
1567 resp->rst_funcid_en = cpu_to_le32(vf_id);
1568 ret = hns_roce_cmq_send(hr_dev, &desc, 1);
1569 if (ret)
1570 continue;
1571
1572 if (hr_reg_read(resp, FUNC_CLEAR_RST_FUN_DONE)) {
1573 if (vf_id == 0)
1574 hr_dev->is_reset = true;
1575 return;
1576 }
1577 }
1578
1579 out:
1580 hns_roce_func_clr_rst_proc(hr_dev, ret, fclr_write_fail_flag);
1581 }
1582
hns_roce_free_vf_resource(struct hns_roce_dev * hr_dev,int vf_id)1583 static int hns_roce_free_vf_resource(struct hns_roce_dev *hr_dev, int vf_id)
1584 {
1585 enum hns_roce_opcode_type opcode = HNS_ROCE_OPC_ALLOC_VF_RES;
1586 struct hns_roce_cmq_desc desc[2];
1587 struct hns_roce_cmq_req *req_a;
1588
1589 req_a = (struct hns_roce_cmq_req *)desc[0].data;
1590 hns_roce_cmq_setup_basic_desc(&desc[0], opcode, false);
1591 desc[0].flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT);
1592 hns_roce_cmq_setup_basic_desc(&desc[1], opcode, false);
1593 hr_reg_write(req_a, FUNC_RES_A_VF_ID, vf_id);
1594
1595 return hns_roce_cmq_send(hr_dev, desc, 2);
1596 }
1597
hns_roce_function_clear(struct hns_roce_dev * hr_dev)1598 static void hns_roce_function_clear(struct hns_roce_dev *hr_dev)
1599 {
1600 int ret;
1601 int i;
1602
1603 if (hr_dev->cmd.state == HNS_ROCE_CMDQ_STATE_FATAL_ERR)
1604 return;
1605
1606 for (i = hr_dev->func_num - 1; i >= 0; i--) {
1607 __hns_roce_function_clear(hr_dev, i);
1608
1609 if (i == 0)
1610 continue;
1611
1612 ret = hns_roce_free_vf_resource(hr_dev, i);
1613 if (ret)
1614 ibdev_err(&hr_dev->ib_dev,
1615 "failed to free vf resource, vf_id = %d, ret = %d.\n",
1616 i, ret);
1617 }
1618 }
1619
hns_roce_clear_extdb_list_info(struct hns_roce_dev * hr_dev)1620 static int hns_roce_clear_extdb_list_info(struct hns_roce_dev *hr_dev)
1621 {
1622 struct hns_roce_cmq_desc desc;
1623 int ret;
1624
1625 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CLEAR_EXTDB_LIST_INFO,
1626 false);
1627 ret = hns_roce_cmq_send(hr_dev, &desc, 1);
1628 if (ret)
1629 ibdev_err(&hr_dev->ib_dev,
1630 "failed to clear extended doorbell info, ret = %d.\n",
1631 ret);
1632
1633 return ret;
1634 }
1635
hns_roce_query_fw_ver(struct hns_roce_dev * hr_dev)1636 static int hns_roce_query_fw_ver(struct hns_roce_dev *hr_dev)
1637 {
1638 struct hns_roce_query_fw_info *resp;
1639 struct hns_roce_cmq_desc desc;
1640 int ret;
1641
1642 hns_roce_cmq_setup_basic_desc(&desc, HNS_QUERY_FW_VER, true);
1643 ret = hns_roce_cmq_send(hr_dev, &desc, 1);
1644 if (ret)
1645 return ret;
1646
1647 resp = (struct hns_roce_query_fw_info *)desc.data;
1648 hr_dev->caps.fw_ver = (u64)(le32_to_cpu(resp->fw_ver));
1649
1650 return 0;
1651 }
1652
hns_roce_query_func_info(struct hns_roce_dev * hr_dev)1653 static int hns_roce_query_func_info(struct hns_roce_dev *hr_dev)
1654 {
1655 struct hns_roce_cmq_desc desc;
1656 int ret;
1657
1658 if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08) {
1659 hr_dev->func_num = 1;
1660 return 0;
1661 }
1662
1663 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_QUERY_FUNC_INFO,
1664 true);
1665 ret = hns_roce_cmq_send(hr_dev, &desc, 1);
1666 if (ret) {
1667 hr_dev->func_num = 1;
1668 return ret;
1669 }
1670
1671 hr_dev->func_num = le32_to_cpu(desc.func_info.own_func_num);
1672 hr_dev->cong_algo_tmpl_id = le32_to_cpu(desc.func_info.own_mac_id);
1673
1674 return 0;
1675 }
1676
hns_roce_hw_v2_query_counter(struct hns_roce_dev * hr_dev,u64 * stats,u32 port,int * num_counters)1677 static int hns_roce_hw_v2_query_counter(struct hns_roce_dev *hr_dev,
1678 u64 *stats, u32 port, int *num_counters)
1679 {
1680 #define CNT_PER_DESC 3
1681 struct hns_roce_cmq_desc *desc;
1682 int bd_idx, cnt_idx;
1683 __le64 *cnt_data;
1684 int desc_num;
1685 int ret;
1686 int i;
1687
1688 if (port > hr_dev->caps.num_ports)
1689 return -EINVAL;
1690
1691 desc_num = DIV_ROUND_UP(HNS_ROCE_HW_CNT_TOTAL, CNT_PER_DESC);
1692 desc = kcalloc(desc_num, sizeof(*desc), GFP_KERNEL);
1693 if (!desc)
1694 return -ENOMEM;
1695
1696 for (i = 0; i < desc_num; i++) {
1697 hns_roce_cmq_setup_basic_desc(&desc[i],
1698 HNS_ROCE_OPC_QUERY_COUNTER, true);
1699 if (i != desc_num - 1)
1700 desc[i].flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT);
1701 }
1702
1703 ret = hns_roce_cmq_send(hr_dev, desc, desc_num);
1704 if (ret) {
1705 ibdev_err(&hr_dev->ib_dev,
1706 "failed to get counter, ret = %d.\n", ret);
1707 goto err_out;
1708 }
1709
1710 for (i = 0; i < HNS_ROCE_HW_CNT_TOTAL && i < *num_counters; i++) {
1711 bd_idx = i / CNT_PER_DESC;
1712 if (bd_idx != HNS_ROCE_HW_CNT_TOTAL / CNT_PER_DESC &&
1713 !(desc[bd_idx].flag & cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT)))
1714 break;
1715
1716 cnt_data = (__le64 *)&desc[bd_idx].data[0];
1717 cnt_idx = i % CNT_PER_DESC;
1718 stats[i] = le64_to_cpu(cnt_data[cnt_idx]);
1719 }
1720 *num_counters = i;
1721
1722 err_out:
1723 kfree(desc);
1724 return ret;
1725 }
1726
hns_roce_config_global_param(struct hns_roce_dev * hr_dev)1727 static int hns_roce_config_global_param(struct hns_roce_dev *hr_dev)
1728 {
1729 struct hns_roce_cmq_desc desc;
1730 struct hns_roce_cmq_req *req = (struct hns_roce_cmq_req *)desc.data;
1731 u32 clock_cycles_of_1us;
1732
1733 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CFG_GLOBAL_PARAM,
1734 false);
1735
1736 if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08)
1737 clock_cycles_of_1us = HNS_ROCE_1NS_CFG;
1738 else
1739 clock_cycles_of_1us = HNS_ROCE_1US_CFG;
1740
1741 hr_reg_write(req, CFG_GLOBAL_PARAM_1US_CYCLES, clock_cycles_of_1us);
1742 hr_reg_write(req, CFG_GLOBAL_PARAM_UDP_PORT, ROCE_V2_UDP_DPORT);
1743
1744 return hns_roce_cmq_send(hr_dev, &desc, 1);
1745 }
1746
load_func_res_caps(struct hns_roce_dev * hr_dev,bool is_vf)1747 static int load_func_res_caps(struct hns_roce_dev *hr_dev, bool is_vf)
1748 {
1749 struct hns_roce_cmq_desc desc[2];
1750 struct hns_roce_cmq_req *r_a = (struct hns_roce_cmq_req *)desc[0].data;
1751 struct hns_roce_cmq_req *r_b = (struct hns_roce_cmq_req *)desc[1].data;
1752 struct hns_roce_caps *caps = &hr_dev->caps;
1753 enum hns_roce_opcode_type opcode;
1754 u32 func_num;
1755 int ret;
1756
1757 if (is_vf) {
1758 opcode = HNS_ROCE_OPC_QUERY_VF_RES;
1759 func_num = 1;
1760 } else {
1761 opcode = HNS_ROCE_OPC_QUERY_PF_RES;
1762 func_num = hr_dev->func_num;
1763 }
1764
1765 hns_roce_cmq_setup_basic_desc(&desc[0], opcode, true);
1766 desc[0].flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT);
1767 hns_roce_cmq_setup_basic_desc(&desc[1], opcode, true);
1768
1769 ret = hns_roce_cmq_send(hr_dev, desc, 2);
1770 if (ret)
1771 return ret;
1772
1773 caps->qpc_bt_num = hr_reg_read(r_a, FUNC_RES_A_QPC_BT_NUM) / func_num;
1774 caps->srqc_bt_num = hr_reg_read(r_a, FUNC_RES_A_SRQC_BT_NUM) / func_num;
1775 caps->cqc_bt_num = hr_reg_read(r_a, FUNC_RES_A_CQC_BT_NUM) / func_num;
1776 caps->mpt_bt_num = hr_reg_read(r_a, FUNC_RES_A_MPT_BT_NUM) / func_num;
1777 caps->eqc_bt_num = hr_reg_read(r_a, FUNC_RES_A_EQC_BT_NUM) / func_num;
1778 caps->smac_bt_num = hr_reg_read(r_b, FUNC_RES_B_SMAC_NUM) / func_num;
1779 caps->sgid_bt_num = hr_reg_read(r_b, FUNC_RES_B_SGID_NUM) / func_num;
1780 caps->sccc_bt_num = hr_reg_read(r_b, FUNC_RES_B_SCCC_BT_NUM) / func_num;
1781
1782 if (is_vf) {
1783 caps->sl_num = hr_reg_read(r_b, FUNC_RES_V_QID_NUM) / func_num;
1784 caps->gmv_bt_num = hr_reg_read(r_b, FUNC_RES_V_GMV_BT_NUM) /
1785 func_num;
1786 } else {
1787 caps->sl_num = hr_reg_read(r_b, FUNC_RES_B_QID_NUM) / func_num;
1788 caps->gmv_bt_num = hr_reg_read(r_b, FUNC_RES_B_GMV_BT_NUM) /
1789 func_num;
1790 }
1791
1792 return 0;
1793 }
1794
load_pf_timer_res_caps(struct hns_roce_dev * hr_dev)1795 static int load_pf_timer_res_caps(struct hns_roce_dev *hr_dev)
1796 {
1797 struct hns_roce_cmq_desc desc;
1798 struct hns_roce_cmq_req *req = (struct hns_roce_cmq_req *)desc.data;
1799 struct hns_roce_caps *caps = &hr_dev->caps;
1800 int ret;
1801
1802 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_QUERY_PF_TIMER_RES,
1803 true);
1804
1805 ret = hns_roce_cmq_send(hr_dev, &desc, 1);
1806 if (ret)
1807 return ret;
1808
1809 caps->qpc_timer_bt_num = hr_reg_read(req, PF_TIMER_RES_QPC_ITEM_NUM);
1810 caps->cqc_timer_bt_num = hr_reg_read(req, PF_TIMER_RES_CQC_ITEM_NUM);
1811
1812 return 0;
1813 }
1814
hns_roce_query_pf_resource(struct hns_roce_dev * hr_dev)1815 static int hns_roce_query_pf_resource(struct hns_roce_dev *hr_dev)
1816 {
1817 struct device *dev = hr_dev->dev;
1818 int ret;
1819
1820 ret = load_func_res_caps(hr_dev, false);
1821 if (ret) {
1822 dev_err(dev, "failed to load pf res caps, ret = %d.\n", ret);
1823 return ret;
1824 }
1825
1826 ret = load_pf_timer_res_caps(hr_dev);
1827 if (ret)
1828 dev_err(dev, "failed to load pf timer resource, ret = %d.\n",
1829 ret);
1830
1831 return ret;
1832 }
1833
hns_roce_query_vf_resource(struct hns_roce_dev * hr_dev)1834 static int hns_roce_query_vf_resource(struct hns_roce_dev *hr_dev)
1835 {
1836 struct device *dev = hr_dev->dev;
1837 int ret;
1838
1839 ret = load_func_res_caps(hr_dev, true);
1840 if (ret)
1841 dev_err(dev, "failed to load vf res caps, ret = %d.\n", ret);
1842
1843 return ret;
1844 }
1845
__hns_roce_set_vf_switch_param(struct hns_roce_dev * hr_dev,u32 vf_id)1846 static int __hns_roce_set_vf_switch_param(struct hns_roce_dev *hr_dev,
1847 u32 vf_id)
1848 {
1849 struct hns_roce_vf_switch *swt;
1850 struct hns_roce_cmq_desc desc;
1851 int ret;
1852
1853 swt = (struct hns_roce_vf_switch *)desc.data;
1854 hns_roce_cmq_setup_basic_desc(&desc, HNS_SWITCH_PARAMETER_CFG, true);
1855 swt->rocee_sel |= cpu_to_le32(HNS_ICL_SWITCH_CMD_ROCEE_SEL);
1856 hr_reg_write(swt, VF_SWITCH_VF_ID, vf_id);
1857 ret = hns_roce_cmq_send(hr_dev, &desc, 1);
1858 if (ret)
1859 return ret;
1860
1861 desc.flag = cpu_to_le16(HNS_ROCE_CMD_FLAG_IN);
1862 desc.flag &= cpu_to_le16(~HNS_ROCE_CMD_FLAG_WR);
1863 hr_reg_enable(swt, VF_SWITCH_ALW_LPBK);
1864 hr_reg_clear(swt, VF_SWITCH_ALW_LCL_LPBK);
1865 hr_reg_enable(swt, VF_SWITCH_ALW_DST_OVRD);
1866
1867 return hns_roce_cmq_send(hr_dev, &desc, 1);
1868 }
1869
hns_roce_set_vf_switch_param(struct hns_roce_dev * hr_dev)1870 static int hns_roce_set_vf_switch_param(struct hns_roce_dev *hr_dev)
1871 {
1872 u32 vf_id;
1873 int ret;
1874
1875 for (vf_id = 0; vf_id < hr_dev->func_num; vf_id++) {
1876 ret = __hns_roce_set_vf_switch_param(hr_dev, vf_id);
1877 if (ret)
1878 return ret;
1879 }
1880 return 0;
1881 }
1882
config_vf_hem_resource(struct hns_roce_dev * hr_dev,int vf_id)1883 static int config_vf_hem_resource(struct hns_roce_dev *hr_dev, int vf_id)
1884 {
1885 struct hns_roce_cmq_desc desc[2];
1886 struct hns_roce_cmq_req *r_a = (struct hns_roce_cmq_req *)desc[0].data;
1887 struct hns_roce_cmq_req *r_b = (struct hns_roce_cmq_req *)desc[1].data;
1888 enum hns_roce_opcode_type opcode = HNS_ROCE_OPC_ALLOC_VF_RES;
1889 struct hns_roce_caps *caps = &hr_dev->caps;
1890
1891 hns_roce_cmq_setup_basic_desc(&desc[0], opcode, false);
1892 desc[0].flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT);
1893 hns_roce_cmq_setup_basic_desc(&desc[1], opcode, false);
1894
1895 hr_reg_write(r_a, FUNC_RES_A_VF_ID, vf_id);
1896
1897 hr_reg_write(r_a, FUNC_RES_A_QPC_BT_NUM, caps->qpc_bt_num);
1898 hr_reg_write(r_a, FUNC_RES_A_QPC_BT_IDX, vf_id * caps->qpc_bt_num);
1899 hr_reg_write(r_a, FUNC_RES_A_SRQC_BT_NUM, caps->srqc_bt_num);
1900 hr_reg_write(r_a, FUNC_RES_A_SRQC_BT_IDX, vf_id * caps->srqc_bt_num);
1901 hr_reg_write(r_a, FUNC_RES_A_CQC_BT_NUM, caps->cqc_bt_num);
1902 hr_reg_write(r_a, FUNC_RES_A_CQC_BT_IDX, vf_id * caps->cqc_bt_num);
1903 hr_reg_write(r_a, FUNC_RES_A_MPT_BT_NUM, caps->mpt_bt_num);
1904 hr_reg_write(r_a, FUNC_RES_A_MPT_BT_IDX, vf_id * caps->mpt_bt_num);
1905 hr_reg_write(r_a, FUNC_RES_A_EQC_BT_NUM, caps->eqc_bt_num);
1906 hr_reg_write(r_a, FUNC_RES_A_EQC_BT_IDX, vf_id * caps->eqc_bt_num);
1907 hr_reg_write(r_b, FUNC_RES_V_QID_NUM, caps->sl_num);
1908 hr_reg_write(r_b, FUNC_RES_B_QID_IDX, vf_id * caps->sl_num);
1909 hr_reg_write(r_b, FUNC_RES_B_SCCC_BT_NUM, caps->sccc_bt_num);
1910 hr_reg_write(r_b, FUNC_RES_B_SCCC_BT_IDX, vf_id * caps->sccc_bt_num);
1911
1912 if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09) {
1913 hr_reg_write(r_b, FUNC_RES_V_GMV_BT_NUM, caps->gmv_bt_num);
1914 hr_reg_write(r_b, FUNC_RES_B_GMV_BT_IDX,
1915 vf_id * caps->gmv_bt_num);
1916 } else {
1917 hr_reg_write(r_b, FUNC_RES_B_SGID_NUM, caps->sgid_bt_num);
1918 hr_reg_write(r_b, FUNC_RES_B_SGID_IDX,
1919 vf_id * caps->sgid_bt_num);
1920 hr_reg_write(r_b, FUNC_RES_B_SMAC_NUM, caps->smac_bt_num);
1921 hr_reg_write(r_b, FUNC_RES_B_SMAC_IDX,
1922 vf_id * caps->smac_bt_num);
1923 }
1924
1925 return hns_roce_cmq_send(hr_dev, desc, 2);
1926 }
1927
hns_roce_alloc_vf_resource(struct hns_roce_dev * hr_dev)1928 static int hns_roce_alloc_vf_resource(struct hns_roce_dev *hr_dev)
1929 {
1930 u32 func_num = max_t(u32, 1, hr_dev->func_num);
1931 u32 vf_id;
1932 int ret;
1933
1934 for (vf_id = 0; vf_id < func_num; vf_id++) {
1935 ret = config_vf_hem_resource(hr_dev, vf_id);
1936 if (ret) {
1937 dev_err(hr_dev->dev,
1938 "failed to config vf-%u hem res, ret = %d.\n",
1939 vf_id, ret);
1940 return ret;
1941 }
1942 }
1943
1944 return 0;
1945 }
1946
hns_roce_v2_set_bt(struct hns_roce_dev * hr_dev)1947 static int hns_roce_v2_set_bt(struct hns_roce_dev *hr_dev)
1948 {
1949 struct hns_roce_cmq_desc desc;
1950 struct hns_roce_cmq_req *req = (struct hns_roce_cmq_req *)desc.data;
1951 struct hns_roce_caps *caps = &hr_dev->caps;
1952
1953 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CFG_BT_ATTR, false);
1954
1955 hr_reg_write(req, CFG_BT_ATTR_QPC_BA_PGSZ,
1956 caps->qpc_ba_pg_sz + PG_SHIFT_OFFSET);
1957 hr_reg_write(req, CFG_BT_ATTR_QPC_BUF_PGSZ,
1958 caps->qpc_buf_pg_sz + PG_SHIFT_OFFSET);
1959 hr_reg_write(req, CFG_BT_ATTR_QPC_HOPNUM,
1960 to_hr_hem_hopnum(caps->qpc_hop_num, caps->num_qps));
1961
1962 hr_reg_write(req, CFG_BT_ATTR_SRQC_BA_PGSZ,
1963 caps->srqc_ba_pg_sz + PG_SHIFT_OFFSET);
1964 hr_reg_write(req, CFG_BT_ATTR_SRQC_BUF_PGSZ,
1965 caps->srqc_buf_pg_sz + PG_SHIFT_OFFSET);
1966 hr_reg_write(req, CFG_BT_ATTR_SRQC_HOPNUM,
1967 to_hr_hem_hopnum(caps->srqc_hop_num, caps->num_srqs));
1968
1969 hr_reg_write(req, CFG_BT_ATTR_CQC_BA_PGSZ,
1970 caps->cqc_ba_pg_sz + PG_SHIFT_OFFSET);
1971 hr_reg_write(req, CFG_BT_ATTR_CQC_BUF_PGSZ,
1972 caps->cqc_buf_pg_sz + PG_SHIFT_OFFSET);
1973 hr_reg_write(req, CFG_BT_ATTR_CQC_HOPNUM,
1974 to_hr_hem_hopnum(caps->cqc_hop_num, caps->num_cqs));
1975
1976 hr_reg_write(req, CFG_BT_ATTR_MPT_BA_PGSZ,
1977 caps->mpt_ba_pg_sz + PG_SHIFT_OFFSET);
1978 hr_reg_write(req, CFG_BT_ATTR_MPT_BUF_PGSZ,
1979 caps->mpt_buf_pg_sz + PG_SHIFT_OFFSET);
1980 hr_reg_write(req, CFG_BT_ATTR_MPT_HOPNUM,
1981 to_hr_hem_hopnum(caps->mpt_hop_num, caps->num_mtpts));
1982
1983 hr_reg_write(req, CFG_BT_ATTR_SCCC_BA_PGSZ,
1984 caps->sccc_ba_pg_sz + PG_SHIFT_OFFSET);
1985 hr_reg_write(req, CFG_BT_ATTR_SCCC_BUF_PGSZ,
1986 caps->sccc_buf_pg_sz + PG_SHIFT_OFFSET);
1987 hr_reg_write(req, CFG_BT_ATTR_SCCC_HOPNUM,
1988 to_hr_hem_hopnum(caps->sccc_hop_num, caps->num_qps));
1989
1990 return hns_roce_cmq_send(hr_dev, &desc, 1);
1991 }
1992
calc_pg_sz(u32 obj_num,u32 obj_size,u32 hop_num,u32 ctx_bt_num,u32 * buf_page_size,u32 * bt_page_size,u32 hem_type)1993 static void calc_pg_sz(u32 obj_num, u32 obj_size, u32 hop_num, u32 ctx_bt_num,
1994 u32 *buf_page_size, u32 *bt_page_size, u32 hem_type)
1995 {
1996 u64 obj_per_chunk;
1997 u64 bt_chunk_size = PAGE_SIZE;
1998 u64 buf_chunk_size = PAGE_SIZE;
1999 u64 obj_per_chunk_default = buf_chunk_size / obj_size;
2000
2001 *buf_page_size = 0;
2002 *bt_page_size = 0;
2003
2004 switch (hop_num) {
2005 case 3:
2006 obj_per_chunk = ctx_bt_num * (bt_chunk_size / BA_BYTE_LEN) *
2007 (bt_chunk_size / BA_BYTE_LEN) *
2008 (bt_chunk_size / BA_BYTE_LEN) *
2009 obj_per_chunk_default;
2010 break;
2011 case 2:
2012 obj_per_chunk = ctx_bt_num * (bt_chunk_size / BA_BYTE_LEN) *
2013 (bt_chunk_size / BA_BYTE_LEN) *
2014 obj_per_chunk_default;
2015 break;
2016 case 1:
2017 obj_per_chunk = ctx_bt_num * (bt_chunk_size / BA_BYTE_LEN) *
2018 obj_per_chunk_default;
2019 break;
2020 case HNS_ROCE_HOP_NUM_0:
2021 obj_per_chunk = ctx_bt_num * obj_per_chunk_default;
2022 break;
2023 default:
2024 pr_err("table %u not support hop_num = %u!\n", hem_type,
2025 hop_num);
2026 return;
2027 }
2028
2029 if (hem_type >= HEM_TYPE_MTT)
2030 *bt_page_size = ilog2(DIV_ROUND_UP(obj_num, obj_per_chunk));
2031 else
2032 *buf_page_size = ilog2(DIV_ROUND_UP(obj_num, obj_per_chunk));
2033 }
2034
set_hem_page_size(struct hns_roce_dev * hr_dev)2035 static void set_hem_page_size(struct hns_roce_dev *hr_dev)
2036 {
2037 struct hns_roce_caps *caps = &hr_dev->caps;
2038
2039 /* EQ */
2040 caps->eqe_ba_pg_sz = 0;
2041 caps->eqe_buf_pg_sz = 0;
2042
2043 /* Link Table */
2044 caps->llm_buf_pg_sz = 0;
2045
2046 /* MR */
2047 caps->mpt_ba_pg_sz = 0;
2048 caps->mpt_buf_pg_sz = 0;
2049 caps->pbl_ba_pg_sz = HNS_ROCE_BA_PG_SZ_SUPPORTED_16K;
2050 caps->pbl_buf_pg_sz = 0;
2051 calc_pg_sz(caps->num_mtpts, caps->mtpt_entry_sz, caps->mpt_hop_num,
2052 caps->mpt_bt_num, &caps->mpt_buf_pg_sz, &caps->mpt_ba_pg_sz,
2053 HEM_TYPE_MTPT);
2054
2055 /* QP */
2056 caps->qpc_ba_pg_sz = 0;
2057 caps->qpc_buf_pg_sz = 0;
2058 caps->qpc_timer_ba_pg_sz = 0;
2059 caps->qpc_timer_buf_pg_sz = 0;
2060 caps->sccc_ba_pg_sz = 0;
2061 caps->sccc_buf_pg_sz = 0;
2062 caps->mtt_ba_pg_sz = 0;
2063 caps->mtt_buf_pg_sz = 0;
2064 calc_pg_sz(caps->num_qps, caps->qpc_sz, caps->qpc_hop_num,
2065 caps->qpc_bt_num, &caps->qpc_buf_pg_sz, &caps->qpc_ba_pg_sz,
2066 HEM_TYPE_QPC);
2067
2068 if (caps->flags & HNS_ROCE_CAP_FLAG_QP_FLOW_CTRL)
2069 calc_pg_sz(caps->num_qps, caps->sccc_sz, caps->sccc_hop_num,
2070 caps->sccc_bt_num, &caps->sccc_buf_pg_sz,
2071 &caps->sccc_ba_pg_sz, HEM_TYPE_SCCC);
2072
2073 /* CQ */
2074 caps->cqc_ba_pg_sz = 0;
2075 caps->cqc_buf_pg_sz = 0;
2076 caps->cqc_timer_ba_pg_sz = 0;
2077 caps->cqc_timer_buf_pg_sz = 0;
2078 caps->cqe_ba_pg_sz = HNS_ROCE_BA_PG_SZ_SUPPORTED_256K;
2079 caps->cqe_buf_pg_sz = 0;
2080 calc_pg_sz(caps->num_cqs, caps->cqc_entry_sz, caps->cqc_hop_num,
2081 caps->cqc_bt_num, &caps->cqc_buf_pg_sz, &caps->cqc_ba_pg_sz,
2082 HEM_TYPE_CQC);
2083 calc_pg_sz(caps->max_cqes, caps->cqe_sz, caps->cqe_hop_num,
2084 1, &caps->cqe_buf_pg_sz, &caps->cqe_ba_pg_sz, HEM_TYPE_CQE);
2085
2086 /* SRQ */
2087 if (caps->flags & HNS_ROCE_CAP_FLAG_SRQ) {
2088 caps->srqc_ba_pg_sz = 0;
2089 caps->srqc_buf_pg_sz = 0;
2090 caps->srqwqe_ba_pg_sz = 0;
2091 caps->srqwqe_buf_pg_sz = 0;
2092 caps->idx_ba_pg_sz = 0;
2093 caps->idx_buf_pg_sz = 0;
2094 calc_pg_sz(caps->num_srqs, caps->srqc_entry_sz,
2095 caps->srqc_hop_num, caps->srqc_bt_num,
2096 &caps->srqc_buf_pg_sz, &caps->srqc_ba_pg_sz,
2097 HEM_TYPE_SRQC);
2098 calc_pg_sz(caps->num_srqwqe_segs, caps->mtt_entry_sz,
2099 caps->srqwqe_hop_num, 1, &caps->srqwqe_buf_pg_sz,
2100 &caps->srqwqe_ba_pg_sz, HEM_TYPE_SRQWQE);
2101 calc_pg_sz(caps->num_idx_segs, caps->idx_entry_sz,
2102 caps->idx_hop_num, 1, &caps->idx_buf_pg_sz,
2103 &caps->idx_ba_pg_sz, HEM_TYPE_IDX);
2104 }
2105
2106 /* GMV */
2107 caps->gmv_ba_pg_sz = 0;
2108 caps->gmv_buf_pg_sz = 0;
2109 }
2110
2111 /* Apply all loaded caps before setting to hardware */
apply_func_caps(struct hns_roce_dev * hr_dev)2112 static void apply_func_caps(struct hns_roce_dev *hr_dev)
2113 {
2114 #define MAX_GID_TBL_LEN 256
2115 struct hns_roce_caps *caps = &hr_dev->caps;
2116 struct hns_roce_v2_priv *priv = hr_dev->priv;
2117
2118 /* The following configurations don't need to be got from firmware. */
2119 caps->qpc_timer_entry_sz = HNS_ROCE_V2_QPC_TIMER_ENTRY_SZ;
2120 caps->cqc_timer_entry_sz = HNS_ROCE_V2_CQC_TIMER_ENTRY_SZ;
2121 caps->mtt_entry_sz = HNS_ROCE_V2_MTT_ENTRY_SZ;
2122
2123 caps->pbl_hop_num = HNS_ROCE_PBL_HOP_NUM;
2124 caps->qpc_timer_hop_num = HNS_ROCE_HOP_NUM_0;
2125 caps->cqc_timer_hop_num = HNS_ROCE_HOP_NUM_0;
2126
2127 caps->num_srqwqe_segs = HNS_ROCE_V2_MAX_SRQWQE_SEGS;
2128 caps->num_idx_segs = HNS_ROCE_V2_MAX_IDX_SEGS;
2129
2130 if (!caps->num_comp_vectors)
2131 caps->num_comp_vectors =
2132 min_t(u32, caps->eqc_bt_num - HNS_ROCE_V2_AEQE_VEC_NUM,
2133 (u32)priv->handle->rinfo.num_vectors -
2134 (HNS_ROCE_V2_AEQE_VEC_NUM + HNS_ROCE_V2_ABNORMAL_VEC_NUM));
2135
2136 if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09) {
2137 caps->eqe_hop_num = HNS_ROCE_V3_EQE_HOP_NUM;
2138 caps->ceqe_size = HNS_ROCE_V3_EQE_SIZE;
2139 caps->aeqe_size = HNS_ROCE_V3_EQE_SIZE;
2140
2141 /* The following configurations will be overwritten */
2142 caps->qpc_sz = HNS_ROCE_V3_QPC_SZ;
2143 caps->cqe_sz = HNS_ROCE_V3_CQE_SIZE;
2144 caps->sccc_sz = HNS_ROCE_V3_SCCC_SZ;
2145
2146 /* The following configurations are not got from firmware */
2147 caps->gmv_entry_sz = HNS_ROCE_V3_GMV_ENTRY_SZ;
2148
2149 caps->gmv_hop_num = HNS_ROCE_HOP_NUM_0;
2150
2151 /* It's meaningless to support excessively large gid_table_len,
2152 * as the type of sgid_index in kernel struct ib_global_route
2153 * and userspace struct ibv_global_route are u8/uint8_t (0-255).
2154 */
2155 caps->gid_table_len[0] = min_t(u32, MAX_GID_TBL_LEN,
2156 caps->gmv_bt_num *
2157 (HNS_HW_PAGE_SIZE / caps->gmv_entry_sz));
2158
2159 caps->gmv_entry_num = caps->gmv_bt_num * (HNS_HW_PAGE_SIZE /
2160 caps->gmv_entry_sz);
2161 } else {
2162 u32 func_num = max_t(u32, 1, hr_dev->func_num);
2163
2164 caps->eqe_hop_num = HNS_ROCE_V2_EQE_HOP_NUM;
2165 caps->ceqe_size = HNS_ROCE_CEQE_SIZE;
2166 caps->aeqe_size = HNS_ROCE_AEQE_SIZE;
2167 caps->gid_table_len[0] /= func_num;
2168 }
2169
2170 if (hr_dev->is_vf) {
2171 caps->default_aeq_arm_st = 0x3;
2172 caps->default_ceq_arm_st = 0x3;
2173 caps->default_ceq_max_cnt = 0x1;
2174 caps->default_ceq_period = 0x10;
2175 caps->default_aeq_max_cnt = 0x1;
2176 caps->default_aeq_period = 0x10;
2177 }
2178
2179 set_hem_page_size(hr_dev);
2180 }
2181
hns_roce_query_caps(struct hns_roce_dev * hr_dev)2182 static int hns_roce_query_caps(struct hns_roce_dev *hr_dev)
2183 {
2184 struct hns_roce_cmq_desc desc[HNS_ROCE_QUERY_PF_CAPS_CMD_NUM] = {};
2185 struct hns_roce_caps *caps = &hr_dev->caps;
2186 struct hns_roce_query_pf_caps_a *resp_a;
2187 struct hns_roce_query_pf_caps_b *resp_b;
2188 struct hns_roce_query_pf_caps_c *resp_c;
2189 struct hns_roce_query_pf_caps_d *resp_d;
2190 struct hns_roce_query_pf_caps_e *resp_e;
2191 struct hns_roce_query_pf_caps_f *resp_f;
2192 enum hns_roce_opcode_type cmd;
2193 int ctx_hop_num;
2194 int pbl_hop_num;
2195 int cmd_num;
2196 int ret;
2197 int i;
2198
2199 cmd = hr_dev->is_vf ? HNS_ROCE_OPC_QUERY_VF_CAPS_NUM :
2200 HNS_ROCE_OPC_QUERY_PF_CAPS_NUM;
2201 cmd_num = hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08 ?
2202 HNS_ROCE_QUERY_PF_CAPS_CMD_NUM_HIP08 :
2203 HNS_ROCE_QUERY_PF_CAPS_CMD_NUM;
2204
2205 for (i = 0; i < cmd_num - 1; i++) {
2206 hns_roce_cmq_setup_basic_desc(&desc[i], cmd, true);
2207 desc[i].flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT);
2208 }
2209
2210 hns_roce_cmq_setup_basic_desc(&desc[cmd_num - 1], cmd, true);
2211 desc[cmd_num - 1].flag &= ~cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT);
2212
2213 ret = hns_roce_cmq_send(hr_dev, desc, cmd_num);
2214 if (ret)
2215 return ret;
2216
2217 resp_a = (struct hns_roce_query_pf_caps_a *)desc[0].data;
2218 resp_b = (struct hns_roce_query_pf_caps_b *)desc[1].data;
2219 resp_c = (struct hns_roce_query_pf_caps_c *)desc[2].data;
2220 resp_d = (struct hns_roce_query_pf_caps_d *)desc[3].data;
2221 resp_e = (struct hns_roce_query_pf_caps_e *)desc[4].data;
2222 resp_f = (struct hns_roce_query_pf_caps_f *)desc[5].data;
2223
2224 caps->local_ca_ack_delay = resp_a->local_ca_ack_delay;
2225 caps->max_sq_sg = le16_to_cpu(resp_a->max_sq_sg);
2226 caps->max_sq_inline = le16_to_cpu(resp_a->max_sq_inline);
2227 caps->max_rq_sg = le16_to_cpu(resp_a->max_rq_sg);
2228 caps->max_rq_sg = roundup_pow_of_two(caps->max_rq_sg);
2229 caps->max_srq_sges = le16_to_cpu(resp_a->max_srq_sges);
2230 caps->max_srq_sges = roundup_pow_of_two(caps->max_srq_sges);
2231 caps->num_aeq_vectors = resp_a->num_aeq_vectors;
2232 caps->num_other_vectors = resp_a->num_other_vectors;
2233 caps->max_sq_desc_sz = resp_a->max_sq_desc_sz;
2234 caps->max_rq_desc_sz = resp_a->max_rq_desc_sz;
2235
2236 caps->mtpt_entry_sz = resp_b->mtpt_entry_sz;
2237 caps->irrl_entry_sz = resp_b->irrl_entry_sz;
2238 caps->trrl_entry_sz = resp_b->trrl_entry_sz;
2239 caps->cqc_entry_sz = resp_b->cqc_entry_sz;
2240 caps->srqc_entry_sz = resp_b->srqc_entry_sz;
2241 caps->idx_entry_sz = resp_b->idx_entry_sz;
2242 caps->sccc_sz = resp_b->sccc_sz;
2243 caps->max_mtu = resp_b->max_mtu;
2244 caps->min_cqes = resp_b->min_cqes;
2245 caps->min_wqes = resp_b->min_wqes;
2246 caps->page_size_cap = le32_to_cpu(resp_b->page_size_cap);
2247 caps->pkey_table_len[0] = resp_b->pkey_table_len;
2248 caps->phy_num_uars = resp_b->phy_num_uars;
2249 ctx_hop_num = resp_b->ctx_hop_num;
2250 pbl_hop_num = resp_b->pbl_hop_num;
2251
2252 caps->num_pds = 1 << hr_reg_read(resp_c, PF_CAPS_C_NUM_PDS);
2253
2254 caps->flags = hr_reg_read(resp_c, PF_CAPS_C_CAP_FLAGS);
2255 caps->flags |= le16_to_cpu(resp_d->cap_flags_ex) <<
2256 HNS_ROCE_CAP_FLAGS_EX_SHIFT;
2257
2258 caps->num_cqs = 1 << hr_reg_read(resp_c, PF_CAPS_C_NUM_CQS);
2259 caps->gid_table_len[0] = hr_reg_read(resp_c, PF_CAPS_C_MAX_GID);
2260 caps->max_cqes = 1 << hr_reg_read(resp_c, PF_CAPS_C_CQ_DEPTH);
2261 caps->num_xrcds = 1 << hr_reg_read(resp_c, PF_CAPS_C_NUM_XRCDS);
2262 caps->num_mtpts = 1 << hr_reg_read(resp_c, PF_CAPS_C_NUM_MRWS);
2263 caps->num_qps = 1 << hr_reg_read(resp_c, PF_CAPS_C_NUM_QPS);
2264 caps->max_qp_init_rdma = hr_reg_read(resp_c, PF_CAPS_C_MAX_ORD);
2265 caps->max_qp_dest_rdma = caps->max_qp_init_rdma;
2266 caps->max_wqes = 1 << le16_to_cpu(resp_c->sq_depth);
2267
2268 caps->num_srqs = 1 << hr_reg_read(resp_d, PF_CAPS_D_NUM_SRQS);
2269 caps->cong_cap = hr_reg_read(resp_d, PF_CAPS_D_CONG_CAP);
2270 caps->max_srq_wrs = 1 << le16_to_cpu(resp_d->srq_depth);
2271 caps->ceqe_depth = 1 << hr_reg_read(resp_d, PF_CAPS_D_CEQ_DEPTH);
2272 caps->num_comp_vectors = hr_reg_read(resp_d, PF_CAPS_D_NUM_CEQS);
2273 caps->aeqe_depth = 1 << hr_reg_read(resp_d, PF_CAPS_D_AEQ_DEPTH);
2274 caps->default_cong_type = hr_reg_read(resp_d, PF_CAPS_D_DEFAULT_ALG);
2275 caps->reserved_pds = hr_reg_read(resp_d, PF_CAPS_D_RSV_PDS);
2276 caps->num_uars = 1 << hr_reg_read(resp_d, PF_CAPS_D_NUM_UARS);
2277 caps->reserved_qps = hr_reg_read(resp_d, PF_CAPS_D_RSV_QPS);
2278 caps->reserved_uars = hr_reg_read(resp_d, PF_CAPS_D_RSV_UARS);
2279
2280 caps->reserved_mrws = hr_reg_read(resp_e, PF_CAPS_E_RSV_MRWS);
2281 caps->chunk_sz = 1 << hr_reg_read(resp_e, PF_CAPS_E_CHUNK_SIZE_SHIFT);
2282 caps->reserved_cqs = hr_reg_read(resp_e, PF_CAPS_E_RSV_CQS);
2283 caps->reserved_xrcds = hr_reg_read(resp_e, PF_CAPS_E_RSV_XRCDS);
2284 caps->reserved_srqs = hr_reg_read(resp_e, PF_CAPS_E_RSV_SRQS);
2285 caps->reserved_lkey = hr_reg_read(resp_e, PF_CAPS_E_RSV_LKEYS);
2286
2287 caps->max_ack_req_msg_len = le32_to_cpu(resp_f->max_ack_req_msg_len);
2288
2289 caps->qpc_hop_num = ctx_hop_num;
2290 caps->sccc_hop_num = ctx_hop_num;
2291 caps->srqc_hop_num = ctx_hop_num;
2292 caps->cqc_hop_num = ctx_hop_num;
2293 caps->mpt_hop_num = ctx_hop_num;
2294 caps->mtt_hop_num = pbl_hop_num;
2295 caps->cqe_hop_num = pbl_hop_num;
2296 caps->srqwqe_hop_num = pbl_hop_num;
2297 caps->idx_hop_num = pbl_hop_num;
2298 caps->wqe_sq_hop_num = hr_reg_read(resp_d, PF_CAPS_D_SQWQE_HOP_NUM);
2299 caps->wqe_sge_hop_num = hr_reg_read(resp_d, PF_CAPS_D_EX_SGE_HOP_NUM);
2300 caps->wqe_rq_hop_num = hr_reg_read(resp_d, PF_CAPS_D_RQWQE_HOP_NUM);
2301
2302 if (!(caps->page_size_cap & PAGE_SIZE))
2303 caps->page_size_cap = HNS_ROCE_V2_PAGE_SIZE_SUPPORTED;
2304
2305 if (!hr_dev->is_vf) {
2306 caps->cqe_sz = resp_a->cqe_sz;
2307 caps->qpc_sz = le16_to_cpu(resp_b->qpc_sz);
2308 caps->default_aeq_arm_st =
2309 hr_reg_read(resp_d, PF_CAPS_D_AEQ_ARM_ST);
2310 caps->default_ceq_arm_st =
2311 hr_reg_read(resp_d, PF_CAPS_D_CEQ_ARM_ST);
2312 caps->default_ceq_max_cnt = le16_to_cpu(resp_e->ceq_max_cnt);
2313 caps->default_ceq_period = le16_to_cpu(resp_e->ceq_period);
2314 caps->default_aeq_max_cnt = le16_to_cpu(resp_e->aeq_max_cnt);
2315 caps->default_aeq_period = le16_to_cpu(resp_e->aeq_period);
2316 }
2317
2318 return 0;
2319 }
2320
config_hem_entry_size(struct hns_roce_dev * hr_dev,u32 type,u32 val)2321 static int config_hem_entry_size(struct hns_roce_dev *hr_dev, u32 type, u32 val)
2322 {
2323 struct hns_roce_cmq_desc desc;
2324 struct hns_roce_cmq_req *req = (struct hns_roce_cmq_req *)desc.data;
2325
2326 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CFG_ENTRY_SIZE,
2327 false);
2328
2329 hr_reg_write(req, CFG_HEM_ENTRY_SIZE_TYPE, type);
2330 hr_reg_write(req, CFG_HEM_ENTRY_SIZE_VALUE, val);
2331
2332 return hns_roce_cmq_send(hr_dev, &desc, 1);
2333 }
2334
hns_roce_config_entry_size(struct hns_roce_dev * hr_dev)2335 static int hns_roce_config_entry_size(struct hns_roce_dev *hr_dev)
2336 {
2337 struct hns_roce_caps *caps = &hr_dev->caps;
2338 int ret;
2339
2340 if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08)
2341 return 0;
2342
2343 ret = config_hem_entry_size(hr_dev, HNS_ROCE_CFG_QPC_SIZE,
2344 caps->qpc_sz);
2345 if (ret) {
2346 dev_err(hr_dev->dev, "failed to cfg qpc sz, ret = %d.\n", ret);
2347 return ret;
2348 }
2349
2350 ret = config_hem_entry_size(hr_dev, HNS_ROCE_CFG_SCCC_SIZE,
2351 caps->sccc_sz);
2352 if (ret)
2353 dev_err(hr_dev->dev, "failed to cfg sccc sz, ret = %d.\n", ret);
2354
2355 return ret;
2356 }
2357
hns_roce_v2_vf_profile(struct hns_roce_dev * hr_dev)2358 static int hns_roce_v2_vf_profile(struct hns_roce_dev *hr_dev)
2359 {
2360 struct device *dev = hr_dev->dev;
2361 int ret;
2362
2363 hr_dev->func_num = 1;
2364
2365 ret = hns_roce_query_caps(hr_dev);
2366 if (ret) {
2367 dev_err(dev, "failed to query VF caps, ret = %d.\n", ret);
2368 return ret;
2369 }
2370
2371 ret = hns_roce_query_vf_resource(hr_dev);
2372 if (ret) {
2373 dev_err(dev, "failed to query VF resource, ret = %d.\n", ret);
2374 return ret;
2375 }
2376
2377 apply_func_caps(hr_dev);
2378
2379 ret = hns_roce_v2_set_bt(hr_dev);
2380 if (ret)
2381 dev_err(dev, "failed to config VF BA table, ret = %d.\n", ret);
2382
2383 return ret;
2384 }
2385
hns_roce_v2_pf_profile(struct hns_roce_dev * hr_dev)2386 static int hns_roce_v2_pf_profile(struct hns_roce_dev *hr_dev)
2387 {
2388 struct device *dev = hr_dev->dev;
2389 int ret;
2390
2391 ret = hns_roce_query_func_info(hr_dev);
2392 if (ret) {
2393 dev_err(dev, "failed to query func info, ret = %d.\n", ret);
2394 return ret;
2395 }
2396
2397 ret = hns_roce_config_global_param(hr_dev);
2398 if (ret) {
2399 dev_err(dev, "failed to config global param, ret = %d.\n", ret);
2400 return ret;
2401 }
2402
2403 ret = hns_roce_set_vf_switch_param(hr_dev);
2404 if (ret) {
2405 dev_err(dev, "failed to set switch param, ret = %d.\n", ret);
2406 return ret;
2407 }
2408
2409 ret = hns_roce_query_caps(hr_dev);
2410 if (ret) {
2411 dev_err(dev, "failed to query PF caps, ret = %d.\n", ret);
2412 return ret;
2413 }
2414
2415 ret = hns_roce_query_pf_resource(hr_dev);
2416 if (ret) {
2417 dev_err(dev, "failed to query pf resource, ret = %d.\n", ret);
2418 return ret;
2419 }
2420
2421 apply_func_caps(hr_dev);
2422
2423 ret = hns_roce_alloc_vf_resource(hr_dev);
2424 if (ret) {
2425 dev_err(dev, "failed to alloc vf resource, ret = %d.\n", ret);
2426 return ret;
2427 }
2428
2429 ret = hns_roce_v2_set_bt(hr_dev);
2430 if (ret) {
2431 dev_err(dev, "failed to config BA table, ret = %d.\n", ret);
2432 return ret;
2433 }
2434
2435 /* Configure the size of QPC, SCCC, etc. */
2436 return hns_roce_config_entry_size(hr_dev);
2437 }
2438
hns_roce_v2_profile(struct hns_roce_dev * hr_dev)2439 static int hns_roce_v2_profile(struct hns_roce_dev *hr_dev)
2440 {
2441 struct device *dev = hr_dev->dev;
2442 int ret;
2443
2444 ret = hns_roce_cmq_query_hw_info(hr_dev);
2445 if (ret) {
2446 dev_err(dev, "failed to query hardware info, ret = %d.\n", ret);
2447 return ret;
2448 }
2449
2450 ret = hns_roce_query_fw_ver(hr_dev);
2451 if (ret) {
2452 dev_err(dev, "failed to query firmware info, ret = %d.\n", ret);
2453 return ret;
2454 }
2455
2456 hr_dev->vendor_part_id = hr_dev->pci_dev->device;
2457 hr_dev->sys_image_guid = be64_to_cpu(hr_dev->ib_dev.node_guid);
2458
2459 if (hr_dev->is_vf)
2460 return hns_roce_v2_vf_profile(hr_dev);
2461 else
2462 return hns_roce_v2_pf_profile(hr_dev);
2463 }
2464
config_llm_table(struct hns_roce_buf * data_buf,void * cfg_buf)2465 static void config_llm_table(struct hns_roce_buf *data_buf, void *cfg_buf)
2466 {
2467 u32 i, next_ptr, page_num;
2468 __le64 *entry = cfg_buf;
2469 dma_addr_t addr;
2470 u64 val;
2471
2472 page_num = data_buf->npages;
2473 for (i = 0; i < page_num; i++) {
2474 addr = hns_roce_buf_page(data_buf, i);
2475 if (i == (page_num - 1))
2476 next_ptr = 0;
2477 else
2478 next_ptr = i + 1;
2479
2480 val = HNS_ROCE_EXT_LLM_ENTRY(addr, (u64)next_ptr);
2481 entry[i] = cpu_to_le64(val);
2482 }
2483 }
2484
set_llm_cfg_to_hw(struct hns_roce_dev * hr_dev,struct hns_roce_link_table * table)2485 static int set_llm_cfg_to_hw(struct hns_roce_dev *hr_dev,
2486 struct hns_roce_link_table *table)
2487 {
2488 struct hns_roce_cmq_desc desc[2];
2489 struct hns_roce_cmq_req *r_a = (struct hns_roce_cmq_req *)desc[0].data;
2490 struct hns_roce_cmq_req *r_b = (struct hns_roce_cmq_req *)desc[1].data;
2491 struct hns_roce_buf *buf = table->buf;
2492 enum hns_roce_opcode_type opcode;
2493 dma_addr_t addr;
2494
2495 opcode = HNS_ROCE_OPC_CFG_EXT_LLM;
2496 hns_roce_cmq_setup_basic_desc(&desc[0], opcode, false);
2497 desc[0].flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT);
2498 hns_roce_cmq_setup_basic_desc(&desc[1], opcode, false);
2499
2500 hr_reg_write(r_a, CFG_LLM_A_BA_L, lower_32_bits(table->table.map));
2501 hr_reg_write(r_a, CFG_LLM_A_BA_H, upper_32_bits(table->table.map));
2502 hr_reg_write(r_a, CFG_LLM_A_DEPTH, buf->npages);
2503 hr_reg_write(r_a, CFG_LLM_A_PGSZ, to_hr_hw_page_shift(buf->page_shift));
2504 hr_reg_enable(r_a, CFG_LLM_A_INIT_EN);
2505
2506 addr = to_hr_hw_page_addr(hns_roce_buf_page(buf, 0));
2507 hr_reg_write(r_a, CFG_LLM_A_HEAD_BA_L, lower_32_bits(addr));
2508 hr_reg_write(r_a, CFG_LLM_A_HEAD_BA_H, upper_32_bits(addr));
2509 hr_reg_write(r_a, CFG_LLM_A_HEAD_NXTPTR, 1);
2510 hr_reg_write(r_a, CFG_LLM_A_HEAD_PTR, 0);
2511
2512 addr = to_hr_hw_page_addr(hns_roce_buf_page(buf, buf->npages - 1));
2513 hr_reg_write(r_b, CFG_LLM_B_TAIL_BA_L, lower_32_bits(addr));
2514 hr_reg_write(r_b, CFG_LLM_B_TAIL_BA_H, upper_32_bits(addr));
2515 hr_reg_write(r_b, CFG_LLM_B_TAIL_PTR, buf->npages - 1);
2516
2517 return hns_roce_cmq_send(hr_dev, desc, 2);
2518 }
2519
2520 static struct hns_roce_link_table *
alloc_link_table_buf(struct hns_roce_dev * hr_dev)2521 alloc_link_table_buf(struct hns_roce_dev *hr_dev)
2522 {
2523 u16 total_sl = hr_dev->caps.sl_num * hr_dev->func_num;
2524 struct hns_roce_v2_priv *priv = hr_dev->priv;
2525 struct hns_roce_link_table *link_tbl;
2526 u32 pg_shift, size, min_size;
2527
2528 link_tbl = &priv->ext_llm;
2529 pg_shift = hr_dev->caps.llm_buf_pg_sz + PAGE_SHIFT;
2530 size = hr_dev->caps.num_qps * hr_dev->func_num *
2531 HNS_ROCE_V2_EXT_LLM_ENTRY_SZ;
2532 min_size = HNS_ROCE_EXT_LLM_MIN_PAGES(total_sl) << pg_shift;
2533
2534 /* Alloc data table */
2535 size = max(size, min_size);
2536 link_tbl->buf = hns_roce_buf_alloc(hr_dev, size, pg_shift, 0);
2537 if (IS_ERR(link_tbl->buf))
2538 return ERR_PTR(-ENOMEM);
2539
2540 /* Alloc config table */
2541 size = link_tbl->buf->npages * sizeof(u64);
2542 link_tbl->table.buf = dma_alloc_coherent(hr_dev->dev, size,
2543 &link_tbl->table.map,
2544 GFP_KERNEL);
2545 if (!link_tbl->table.buf) {
2546 hns_roce_buf_free(hr_dev, link_tbl->buf);
2547 return ERR_PTR(-ENOMEM);
2548 }
2549
2550 return link_tbl;
2551 }
2552
free_link_table_buf(struct hns_roce_dev * hr_dev,struct hns_roce_link_table * tbl)2553 static void free_link_table_buf(struct hns_roce_dev *hr_dev,
2554 struct hns_roce_link_table *tbl)
2555 {
2556 if (tbl->buf) {
2557 u32 size = tbl->buf->npages * sizeof(u64);
2558
2559 dma_free_coherent(hr_dev->dev, size, tbl->table.buf,
2560 tbl->table.map);
2561 }
2562
2563 hns_roce_buf_free(hr_dev, tbl->buf);
2564 }
2565
hns_roce_init_link_table(struct hns_roce_dev * hr_dev)2566 static int hns_roce_init_link_table(struct hns_roce_dev *hr_dev)
2567 {
2568 struct hns_roce_link_table *link_tbl;
2569 int ret;
2570
2571 link_tbl = alloc_link_table_buf(hr_dev);
2572 if (IS_ERR(link_tbl))
2573 return -ENOMEM;
2574
2575 if (WARN_ON(link_tbl->buf->npages > HNS_ROCE_V2_EXT_LLM_MAX_DEPTH)) {
2576 ret = -EINVAL;
2577 goto err_alloc;
2578 }
2579
2580 config_llm_table(link_tbl->buf, link_tbl->table.buf);
2581 ret = set_llm_cfg_to_hw(hr_dev, link_tbl);
2582 if (ret)
2583 goto err_alloc;
2584
2585 return 0;
2586
2587 err_alloc:
2588 free_link_table_buf(hr_dev, link_tbl);
2589 return ret;
2590 }
2591
hns_roce_free_link_table(struct hns_roce_dev * hr_dev)2592 static void hns_roce_free_link_table(struct hns_roce_dev *hr_dev)
2593 {
2594 struct hns_roce_v2_priv *priv = hr_dev->priv;
2595
2596 free_link_table_buf(hr_dev, &priv->ext_llm);
2597 }
2598
free_dip_entry(struct hns_roce_dev * hr_dev)2599 static void free_dip_entry(struct hns_roce_dev *hr_dev)
2600 {
2601 struct hns_roce_dip *hr_dip;
2602 unsigned long idx;
2603
2604 xa_lock(&hr_dev->qp_table.dip_xa);
2605
2606 xa_for_each(&hr_dev->qp_table.dip_xa, idx, hr_dip) {
2607 __xa_erase(&hr_dev->qp_table.dip_xa, hr_dip->dip_idx);
2608 kfree(hr_dip);
2609 }
2610
2611 xa_unlock(&hr_dev->qp_table.dip_xa);
2612 }
2613
free_mr_init_pd(struct hns_roce_dev * hr_dev)2614 static struct ib_pd *free_mr_init_pd(struct hns_roce_dev *hr_dev)
2615 {
2616 struct hns_roce_v2_priv *priv = hr_dev->priv;
2617 struct hns_roce_v2_free_mr *free_mr = &priv->free_mr;
2618 struct ib_device *ibdev = &hr_dev->ib_dev;
2619 struct hns_roce_pd *hr_pd;
2620 struct ib_pd *pd;
2621
2622 hr_pd = kzalloc(sizeof(*hr_pd), GFP_KERNEL);
2623 if (ZERO_OR_NULL_PTR(hr_pd))
2624 return NULL;
2625 pd = &hr_pd->ibpd;
2626 pd->device = ibdev;
2627
2628 if (hns_roce_alloc_pd(pd, NULL)) {
2629 ibdev_err(ibdev, "failed to create pd for free mr.\n");
2630 kfree(hr_pd);
2631 return NULL;
2632 }
2633 free_mr->rsv_pd = to_hr_pd(pd);
2634 free_mr->rsv_pd->ibpd.device = &hr_dev->ib_dev;
2635 free_mr->rsv_pd->ibpd.uobject = NULL;
2636 free_mr->rsv_pd->ibpd.__internal_mr = NULL;
2637 atomic_set(&free_mr->rsv_pd->ibpd.usecnt, 0);
2638
2639 return pd;
2640 }
2641
free_mr_init_cq(struct hns_roce_dev * hr_dev)2642 static struct ib_cq *free_mr_init_cq(struct hns_roce_dev *hr_dev)
2643 {
2644 struct hns_roce_v2_priv *priv = hr_dev->priv;
2645 struct hns_roce_v2_free_mr *free_mr = &priv->free_mr;
2646 struct ib_device *ibdev = &hr_dev->ib_dev;
2647 struct ib_cq_init_attr cq_init_attr = {};
2648 struct hns_roce_cq *hr_cq;
2649 struct ib_cq *cq;
2650
2651 cq_init_attr.cqe = HNS_ROCE_FREE_MR_USED_CQE_NUM;
2652
2653 hr_cq = kzalloc(sizeof(*hr_cq), GFP_KERNEL);
2654 if (ZERO_OR_NULL_PTR(hr_cq))
2655 return NULL;
2656
2657 cq = &hr_cq->ib_cq;
2658 cq->device = ibdev;
2659
2660 if (hns_roce_create_cq(cq, &cq_init_attr, NULL)) {
2661 ibdev_err(ibdev, "failed to create cq for free mr.\n");
2662 kfree(hr_cq);
2663 return NULL;
2664 }
2665 free_mr->rsv_cq = to_hr_cq(cq);
2666 free_mr->rsv_cq->ib_cq.device = &hr_dev->ib_dev;
2667 free_mr->rsv_cq->ib_cq.uobject = NULL;
2668 free_mr->rsv_cq->ib_cq.comp_handler = NULL;
2669 free_mr->rsv_cq->ib_cq.event_handler = NULL;
2670 free_mr->rsv_cq->ib_cq.cq_context = NULL;
2671 atomic_set(&free_mr->rsv_cq->ib_cq.usecnt, 0);
2672
2673 return cq;
2674 }
2675
free_mr_init_qp(struct hns_roce_dev * hr_dev,struct ib_cq * cq,struct ib_qp_init_attr * init_attr,int i)2676 static int free_mr_init_qp(struct hns_roce_dev *hr_dev, struct ib_cq *cq,
2677 struct ib_qp_init_attr *init_attr, int i)
2678 {
2679 struct hns_roce_v2_priv *priv = hr_dev->priv;
2680 struct hns_roce_v2_free_mr *free_mr = &priv->free_mr;
2681 struct ib_device *ibdev = &hr_dev->ib_dev;
2682 struct hns_roce_qp *hr_qp;
2683 struct ib_qp *qp;
2684 int ret;
2685
2686 hr_qp = kzalloc(sizeof(*hr_qp), GFP_KERNEL);
2687 if (ZERO_OR_NULL_PTR(hr_qp))
2688 return -ENOMEM;
2689
2690 qp = &hr_qp->ibqp;
2691 qp->device = ibdev;
2692
2693 ret = hns_roce_create_qp(qp, init_attr, NULL);
2694 if (ret) {
2695 ibdev_err(ibdev, "failed to create qp for free mr.\n");
2696 kfree(hr_qp);
2697 return ret;
2698 }
2699
2700 free_mr->rsv_qp[i] = hr_qp;
2701 free_mr->rsv_qp[i]->ibqp.recv_cq = cq;
2702 free_mr->rsv_qp[i]->ibqp.send_cq = cq;
2703
2704 return 0;
2705 }
2706
free_mr_exit(struct hns_roce_dev * hr_dev)2707 static void free_mr_exit(struct hns_roce_dev *hr_dev)
2708 {
2709 struct hns_roce_v2_priv *priv = hr_dev->priv;
2710 struct hns_roce_v2_free_mr *free_mr = &priv->free_mr;
2711 struct ib_qp *qp;
2712 int i;
2713
2714 for (i = 0; i < ARRAY_SIZE(free_mr->rsv_qp); i++) {
2715 if (free_mr->rsv_qp[i]) {
2716 qp = &free_mr->rsv_qp[i]->ibqp;
2717 hns_roce_v2_destroy_qp(qp, NULL);
2718 kfree(free_mr->rsv_qp[i]);
2719 free_mr->rsv_qp[i] = NULL;
2720 }
2721 }
2722
2723 if (free_mr->rsv_cq) {
2724 hns_roce_destroy_cq(&free_mr->rsv_cq->ib_cq, NULL);
2725 kfree(free_mr->rsv_cq);
2726 free_mr->rsv_cq = NULL;
2727 }
2728
2729 if (free_mr->rsv_pd) {
2730 hns_roce_dealloc_pd(&free_mr->rsv_pd->ibpd, NULL);
2731 kfree(free_mr->rsv_pd);
2732 free_mr->rsv_pd = NULL;
2733 }
2734
2735 mutex_destroy(&free_mr->mutex);
2736 }
2737
free_mr_alloc_res(struct hns_roce_dev * hr_dev)2738 static int free_mr_alloc_res(struct hns_roce_dev *hr_dev)
2739 {
2740 struct hns_roce_v2_priv *priv = hr_dev->priv;
2741 struct hns_roce_v2_free_mr *free_mr = &priv->free_mr;
2742 struct ib_qp_init_attr qp_init_attr = {};
2743 struct ib_pd *pd;
2744 struct ib_cq *cq;
2745 int ret;
2746 int i;
2747
2748 pd = free_mr_init_pd(hr_dev);
2749 if (!pd)
2750 return -ENOMEM;
2751
2752 cq = free_mr_init_cq(hr_dev);
2753 if (!cq) {
2754 ret = -ENOMEM;
2755 goto create_failed_cq;
2756 }
2757
2758 qp_init_attr.qp_type = IB_QPT_RC;
2759 qp_init_attr.sq_sig_type = IB_SIGNAL_ALL_WR;
2760 qp_init_attr.send_cq = cq;
2761 qp_init_attr.recv_cq = cq;
2762 for (i = 0; i < ARRAY_SIZE(free_mr->rsv_qp); i++) {
2763 qp_init_attr.cap.max_send_wr = HNS_ROCE_FREE_MR_USED_SQWQE_NUM;
2764 qp_init_attr.cap.max_send_sge = HNS_ROCE_FREE_MR_USED_SQSGE_NUM;
2765 qp_init_attr.cap.max_recv_wr = HNS_ROCE_FREE_MR_USED_RQWQE_NUM;
2766 qp_init_attr.cap.max_recv_sge = HNS_ROCE_FREE_MR_USED_RQSGE_NUM;
2767
2768 ret = free_mr_init_qp(hr_dev, cq, &qp_init_attr, i);
2769 if (ret)
2770 goto create_failed_qp;
2771 }
2772
2773 return 0;
2774
2775 create_failed_qp:
2776 for (i--; i >= 0; i--) {
2777 hns_roce_v2_destroy_qp(&free_mr->rsv_qp[i]->ibqp, NULL);
2778 kfree(free_mr->rsv_qp[i]);
2779 }
2780 hns_roce_destroy_cq(cq, NULL);
2781 kfree(cq);
2782
2783 create_failed_cq:
2784 hns_roce_dealloc_pd(pd, NULL);
2785 kfree(pd);
2786
2787 return ret;
2788 }
2789
free_mr_modify_rsv_qp(struct hns_roce_dev * hr_dev,struct ib_qp_attr * attr,int sl_num)2790 static int free_mr_modify_rsv_qp(struct hns_roce_dev *hr_dev,
2791 struct ib_qp_attr *attr, int sl_num)
2792 {
2793 struct hns_roce_v2_priv *priv = hr_dev->priv;
2794 struct hns_roce_v2_free_mr *free_mr = &priv->free_mr;
2795 struct ib_device *ibdev = &hr_dev->ib_dev;
2796 struct hns_roce_qp *hr_qp;
2797 int loopback;
2798 int mask;
2799 int ret;
2800
2801 hr_qp = to_hr_qp(&free_mr->rsv_qp[sl_num]->ibqp);
2802 hr_qp->free_mr_en = 1;
2803 hr_qp->ibqp.device = ibdev;
2804 hr_qp->ibqp.qp_type = IB_QPT_RC;
2805
2806 mask = IB_QP_STATE | IB_QP_PKEY_INDEX | IB_QP_PORT | IB_QP_ACCESS_FLAGS;
2807 attr->qp_state = IB_QPS_INIT;
2808 attr->port_num = 1;
2809 attr->qp_access_flags = IB_ACCESS_REMOTE_WRITE;
2810 ret = hr_dev->hw->modify_qp(&hr_qp->ibqp, attr, mask, IB_QPS_INIT,
2811 IB_QPS_INIT, NULL);
2812 if (ret) {
2813 ibdev_err_ratelimited(ibdev, "failed to modify qp to init, ret = %d.\n",
2814 ret);
2815 return ret;
2816 }
2817
2818 loopback = hr_dev->loop_idc;
2819 /* Set qpc lbi = 1 incidate loopback IO */
2820 hr_dev->loop_idc = 1;
2821
2822 mask = IB_QP_STATE | IB_QP_AV | IB_QP_PATH_MTU | IB_QP_DEST_QPN |
2823 IB_QP_RQ_PSN | IB_QP_MAX_DEST_RD_ATOMIC | IB_QP_MIN_RNR_TIMER;
2824 attr->qp_state = IB_QPS_RTR;
2825 attr->ah_attr.type = RDMA_AH_ATTR_TYPE_ROCE;
2826 attr->path_mtu = IB_MTU_256;
2827 attr->dest_qp_num = hr_qp->qpn;
2828 attr->rq_psn = HNS_ROCE_FREE_MR_USED_PSN;
2829
2830 rdma_ah_set_sl(&attr->ah_attr, (u8)sl_num);
2831
2832 ret = hr_dev->hw->modify_qp(&hr_qp->ibqp, attr, mask, IB_QPS_INIT,
2833 IB_QPS_RTR, NULL);
2834 hr_dev->loop_idc = loopback;
2835 if (ret) {
2836 ibdev_err(ibdev, "failed to modify qp to rtr, ret = %d.\n",
2837 ret);
2838 return ret;
2839 }
2840
2841 mask = IB_QP_STATE | IB_QP_SQ_PSN | IB_QP_RETRY_CNT | IB_QP_TIMEOUT |
2842 IB_QP_RNR_RETRY | IB_QP_MAX_QP_RD_ATOMIC;
2843 attr->qp_state = IB_QPS_RTS;
2844 attr->sq_psn = HNS_ROCE_FREE_MR_USED_PSN;
2845 attr->retry_cnt = HNS_ROCE_FREE_MR_USED_QP_RETRY_CNT;
2846 attr->timeout = HNS_ROCE_FREE_MR_USED_QP_TIMEOUT;
2847 ret = hr_dev->hw->modify_qp(&hr_qp->ibqp, attr, mask, IB_QPS_RTR,
2848 IB_QPS_RTS, NULL);
2849 if (ret)
2850 ibdev_err(ibdev, "failed to modify qp to rts, ret = %d.\n",
2851 ret);
2852
2853 return ret;
2854 }
2855
free_mr_modify_qp(struct hns_roce_dev * hr_dev)2856 static int free_mr_modify_qp(struct hns_roce_dev *hr_dev)
2857 {
2858 struct hns_roce_v2_priv *priv = hr_dev->priv;
2859 struct hns_roce_v2_free_mr *free_mr = &priv->free_mr;
2860 struct ib_qp_attr attr = {};
2861 int ret;
2862 int i;
2863
2864 rdma_ah_set_grh(&attr.ah_attr, NULL, 0, 0, 1, 0);
2865 rdma_ah_set_static_rate(&attr.ah_attr, 3);
2866 rdma_ah_set_port_num(&attr.ah_attr, 1);
2867
2868 for (i = 0; i < ARRAY_SIZE(free_mr->rsv_qp); i++) {
2869 ret = free_mr_modify_rsv_qp(hr_dev, &attr, i);
2870 if (ret)
2871 return ret;
2872 }
2873
2874 return 0;
2875 }
2876
free_mr_init(struct hns_roce_dev * hr_dev)2877 static int free_mr_init(struct hns_roce_dev *hr_dev)
2878 {
2879 struct hns_roce_v2_priv *priv = hr_dev->priv;
2880 struct hns_roce_v2_free_mr *free_mr = &priv->free_mr;
2881 int ret;
2882
2883 mutex_init(&free_mr->mutex);
2884
2885 ret = free_mr_alloc_res(hr_dev);
2886 if (ret) {
2887 mutex_destroy(&free_mr->mutex);
2888 return ret;
2889 }
2890
2891 ret = free_mr_modify_qp(hr_dev);
2892 if (ret)
2893 goto err_modify_qp;
2894
2895 return 0;
2896
2897 err_modify_qp:
2898 free_mr_exit(hr_dev);
2899
2900 return ret;
2901 }
2902
get_hem_table(struct hns_roce_dev * hr_dev)2903 static int get_hem_table(struct hns_roce_dev *hr_dev)
2904 {
2905 unsigned int qpc_count;
2906 unsigned int cqc_count;
2907 unsigned int gmv_count;
2908 int ret;
2909 int i;
2910
2911 /* Alloc memory for source address table buffer space chunk */
2912 for (gmv_count = 0; gmv_count < hr_dev->caps.gmv_entry_num;
2913 gmv_count++) {
2914 ret = hns_roce_table_get(hr_dev, &hr_dev->gmv_table, gmv_count);
2915 if (ret)
2916 goto err_gmv_failed;
2917 }
2918
2919 if (hr_dev->is_vf)
2920 return 0;
2921
2922 /* Alloc memory for QPC Timer buffer space chunk */
2923 for (qpc_count = 0; qpc_count < hr_dev->caps.qpc_timer_bt_num;
2924 qpc_count++) {
2925 ret = hns_roce_table_get(hr_dev, &hr_dev->qpc_timer_table,
2926 qpc_count);
2927 if (ret) {
2928 dev_err(hr_dev->dev, "QPC Timer get failed\n");
2929 goto err_qpc_timer_failed;
2930 }
2931 }
2932
2933 /* Alloc memory for CQC Timer buffer space chunk */
2934 for (cqc_count = 0; cqc_count < hr_dev->caps.cqc_timer_bt_num;
2935 cqc_count++) {
2936 ret = hns_roce_table_get(hr_dev, &hr_dev->cqc_timer_table,
2937 cqc_count);
2938 if (ret) {
2939 dev_err(hr_dev->dev, "CQC Timer get failed\n");
2940 goto err_cqc_timer_failed;
2941 }
2942 }
2943
2944 return 0;
2945
2946 err_cqc_timer_failed:
2947 for (i = 0; i < cqc_count; i++)
2948 hns_roce_table_put(hr_dev, &hr_dev->cqc_timer_table, i);
2949
2950 err_qpc_timer_failed:
2951 for (i = 0; i < qpc_count; i++)
2952 hns_roce_table_put(hr_dev, &hr_dev->qpc_timer_table, i);
2953
2954 err_gmv_failed:
2955 for (i = 0; i < gmv_count; i++)
2956 hns_roce_table_put(hr_dev, &hr_dev->gmv_table, i);
2957
2958 return ret;
2959 }
2960
put_hem_table(struct hns_roce_dev * hr_dev)2961 static void put_hem_table(struct hns_roce_dev *hr_dev)
2962 {
2963 int i;
2964
2965 for (i = 0; i < hr_dev->caps.gmv_entry_num; i++)
2966 hns_roce_table_put(hr_dev, &hr_dev->gmv_table, i);
2967
2968 if (hr_dev->is_vf)
2969 return;
2970
2971 for (i = 0; i < hr_dev->caps.qpc_timer_bt_num; i++)
2972 hns_roce_table_put(hr_dev, &hr_dev->qpc_timer_table, i);
2973
2974 for (i = 0; i < hr_dev->caps.cqc_timer_bt_num; i++)
2975 hns_roce_table_put(hr_dev, &hr_dev->cqc_timer_table, i);
2976 }
2977
hns_roce_v2_init(struct hns_roce_dev * hr_dev)2978 static int hns_roce_v2_init(struct hns_roce_dev *hr_dev)
2979 {
2980 int ret;
2981
2982 if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08) {
2983 ret = free_mr_init(hr_dev);
2984 if (ret) {
2985 dev_err(hr_dev->dev, "failed to init free mr!\n");
2986 return ret;
2987 }
2988 }
2989
2990 /* The hns ROCEE requires the extdb info to be cleared before using */
2991 ret = hns_roce_clear_extdb_list_info(hr_dev);
2992 if (ret)
2993 goto err_clear_extdb_failed;
2994
2995 ret = get_hem_table(hr_dev);
2996 if (ret)
2997 goto err_get_hem_table_failed;
2998
2999 if (hr_dev->is_vf)
3000 return 0;
3001
3002 ret = hns_roce_init_link_table(hr_dev);
3003 if (ret) {
3004 dev_err(hr_dev->dev, "failed to init llm, ret = %d.\n", ret);
3005 goto err_llm_init_failed;
3006 }
3007
3008 return 0;
3009
3010 err_llm_init_failed:
3011 put_hem_table(hr_dev);
3012 err_get_hem_table_failed:
3013 hns_roce_function_clear(hr_dev);
3014 err_clear_extdb_failed:
3015 if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08)
3016 free_mr_exit(hr_dev);
3017
3018 return ret;
3019 }
3020
hns_roce_v2_exit(struct hns_roce_dev * hr_dev)3021 static void hns_roce_v2_exit(struct hns_roce_dev *hr_dev)
3022 {
3023 if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08)
3024 free_mr_exit(hr_dev);
3025
3026 hns_roce_function_clear(hr_dev);
3027
3028 if (!hr_dev->is_vf)
3029 hns_roce_free_link_table(hr_dev);
3030
3031 if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09)
3032 free_dip_entry(hr_dev);
3033 }
3034
hns_roce_mbox_post(struct hns_roce_dev * hr_dev,struct hns_roce_mbox_msg * mbox_msg)3035 static int hns_roce_mbox_post(struct hns_roce_dev *hr_dev,
3036 struct hns_roce_mbox_msg *mbox_msg)
3037 {
3038 struct hns_roce_cmq_desc desc;
3039 struct hns_roce_post_mbox *mb = (struct hns_roce_post_mbox *)desc.data;
3040
3041 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_POST_MB, false);
3042
3043 mb->in_param_l = cpu_to_le32(mbox_msg->in_param);
3044 mb->in_param_h = cpu_to_le32(mbox_msg->in_param >> 32);
3045 mb->out_param_l = cpu_to_le32(mbox_msg->out_param);
3046 mb->out_param_h = cpu_to_le32(mbox_msg->out_param >> 32);
3047 mb->cmd_tag = cpu_to_le32(mbox_msg->tag << 8 | mbox_msg->cmd);
3048 mb->token_event_en = cpu_to_le32(mbox_msg->event_en << 16 |
3049 mbox_msg->token);
3050
3051 return hns_roce_cmq_send(hr_dev, &desc, 1);
3052 }
3053
v2_wait_mbox_complete(struct hns_roce_dev * hr_dev,u32 timeout,u8 * complete_status)3054 static int v2_wait_mbox_complete(struct hns_roce_dev *hr_dev, u32 timeout,
3055 u8 *complete_status)
3056 {
3057 struct hns_roce_mbox_status *mb_st;
3058 struct hns_roce_cmq_desc desc;
3059 unsigned long end;
3060 int ret = -EBUSY;
3061 u32 status;
3062 bool busy;
3063
3064 mb_st = (struct hns_roce_mbox_status *)desc.data;
3065 end = msecs_to_jiffies(timeout) + jiffies;
3066 while (v2_chk_mbox_is_avail(hr_dev, &busy)) {
3067 if (hr_dev->cmd.state == HNS_ROCE_CMDQ_STATE_FATAL_ERR)
3068 return -EIO;
3069
3070 status = 0;
3071 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_QUERY_MB_ST,
3072 true);
3073 ret = __hns_roce_cmq_send(hr_dev, &desc, 1);
3074 if (!ret) {
3075 status = le32_to_cpu(mb_st->mb_status_hw_run);
3076 /* No pending message exists in ROCEE mbox. */
3077 if (!(status & MB_ST_HW_RUN_M))
3078 break;
3079 } else if (!v2_chk_mbox_is_avail(hr_dev, &busy)) {
3080 break;
3081 }
3082
3083 if (time_after(jiffies, end)) {
3084 dev_err_ratelimited(hr_dev->dev,
3085 "failed to wait mbox status 0x%x\n",
3086 status);
3087 return -ETIMEDOUT;
3088 }
3089
3090 cond_resched();
3091 ret = -EBUSY;
3092 }
3093
3094 if (!ret) {
3095 *complete_status = (u8)(status & MB_ST_COMPLETE_M);
3096 } else if (!v2_chk_mbox_is_avail(hr_dev, &busy)) {
3097 /* Ignore all errors if the mbox is unavailable. */
3098 ret = 0;
3099 *complete_status = MB_ST_COMPLETE_M;
3100 }
3101
3102 return ret;
3103 }
3104
v2_post_mbox(struct hns_roce_dev * hr_dev,struct hns_roce_mbox_msg * mbox_msg)3105 static int v2_post_mbox(struct hns_roce_dev *hr_dev,
3106 struct hns_roce_mbox_msg *mbox_msg)
3107 {
3108 u8 status = 0;
3109 int ret;
3110
3111 /* Waiting for the mbox to be idle */
3112 ret = v2_wait_mbox_complete(hr_dev, HNS_ROCE_V2_GO_BIT_TIMEOUT_MSECS,
3113 &status);
3114 if (unlikely(ret)) {
3115 dev_err_ratelimited(hr_dev->dev,
3116 "failed to check post mbox status = 0x%x, ret = %d.\n",
3117 status, ret);
3118 return ret;
3119 }
3120
3121 /* Post new message to mbox */
3122 ret = hns_roce_mbox_post(hr_dev, mbox_msg);
3123 if (ret)
3124 dev_err_ratelimited(hr_dev->dev,
3125 "failed to post mailbox, ret = %d.\n", ret);
3126
3127 return ret;
3128 }
3129
v2_poll_mbox_done(struct hns_roce_dev * hr_dev)3130 static int v2_poll_mbox_done(struct hns_roce_dev *hr_dev)
3131 {
3132 u8 status = 0;
3133 int ret;
3134
3135 ret = v2_wait_mbox_complete(hr_dev, HNS_ROCE_CMD_TIMEOUT_MSECS,
3136 &status);
3137 if (!ret) {
3138 if (status != MB_ST_COMPLETE_SUCC)
3139 return -EBUSY;
3140 } else {
3141 dev_err_ratelimited(hr_dev->dev,
3142 "failed to check mbox status = 0x%x, ret = %d.\n",
3143 status, ret);
3144 }
3145
3146 return ret;
3147 }
3148
copy_gid(void * dest,const union ib_gid * gid)3149 static void copy_gid(void *dest, const union ib_gid *gid)
3150 {
3151 #define GID_SIZE 4
3152 const union ib_gid *src = gid;
3153 __le32 (*p)[GID_SIZE] = dest;
3154 int i;
3155
3156 if (!gid)
3157 src = &zgid;
3158
3159 for (i = 0; i < GID_SIZE; i++)
3160 (*p)[i] = cpu_to_le32(*(u32 *)&src->raw[i * sizeof(u32)]);
3161 }
3162
config_sgid_table(struct hns_roce_dev * hr_dev,int gid_index,const union ib_gid * gid,enum hns_roce_sgid_type sgid_type)3163 static int config_sgid_table(struct hns_roce_dev *hr_dev,
3164 int gid_index, const union ib_gid *gid,
3165 enum hns_roce_sgid_type sgid_type)
3166 {
3167 struct hns_roce_cmq_desc desc;
3168 struct hns_roce_cfg_sgid_tb *sgid_tb =
3169 (struct hns_roce_cfg_sgid_tb *)desc.data;
3170
3171 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CFG_SGID_TB, false);
3172
3173 hr_reg_write(sgid_tb, CFG_SGID_TB_TABLE_IDX, gid_index);
3174 hr_reg_write(sgid_tb, CFG_SGID_TB_VF_SGID_TYPE, sgid_type);
3175
3176 copy_gid(&sgid_tb->vf_sgid_l, gid);
3177
3178 return hns_roce_cmq_send(hr_dev, &desc, 1);
3179 }
3180
config_gmv_table(struct hns_roce_dev * hr_dev,int gid_index,const union ib_gid * gid,enum hns_roce_sgid_type sgid_type,const struct ib_gid_attr * attr)3181 static int config_gmv_table(struct hns_roce_dev *hr_dev,
3182 int gid_index, const union ib_gid *gid,
3183 enum hns_roce_sgid_type sgid_type,
3184 const struct ib_gid_attr *attr)
3185 {
3186 struct hns_roce_cmq_desc desc[2];
3187 struct hns_roce_cfg_gmv_tb_a *tb_a =
3188 (struct hns_roce_cfg_gmv_tb_a *)desc[0].data;
3189 struct hns_roce_cfg_gmv_tb_b *tb_b =
3190 (struct hns_roce_cfg_gmv_tb_b *)desc[1].data;
3191
3192 u16 vlan_id = VLAN_CFI_MASK;
3193 u8 mac[ETH_ALEN] = {};
3194 int ret;
3195
3196 if (gid) {
3197 ret = rdma_read_gid_l2_fields(attr, &vlan_id, mac);
3198 if (ret)
3199 return ret;
3200 }
3201
3202 hns_roce_cmq_setup_basic_desc(&desc[0], HNS_ROCE_OPC_CFG_GMV_TBL, false);
3203 desc[0].flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT);
3204
3205 hns_roce_cmq_setup_basic_desc(&desc[1], HNS_ROCE_OPC_CFG_GMV_TBL, false);
3206
3207 copy_gid(&tb_a->vf_sgid_l, gid);
3208
3209 hr_reg_write(tb_a, GMV_TB_A_VF_SGID_TYPE, sgid_type);
3210 hr_reg_write(tb_a, GMV_TB_A_VF_VLAN_EN, vlan_id < VLAN_CFI_MASK);
3211 hr_reg_write(tb_a, GMV_TB_A_VF_VLAN_ID, vlan_id);
3212
3213 tb_b->vf_smac_l = cpu_to_le32(*(u32 *)mac);
3214
3215 hr_reg_write(tb_b, GMV_TB_B_SMAC_H, *(u16 *)&mac[4]);
3216 hr_reg_write(tb_b, GMV_TB_B_SGID_IDX, gid_index);
3217
3218 return hns_roce_cmq_send(hr_dev, desc, 2);
3219 }
3220
hns_roce_v2_set_gid(struct hns_roce_dev * hr_dev,int gid_index,const union ib_gid * gid,const struct ib_gid_attr * attr)3221 static int hns_roce_v2_set_gid(struct hns_roce_dev *hr_dev, int gid_index,
3222 const union ib_gid *gid,
3223 const struct ib_gid_attr *attr)
3224 {
3225 enum hns_roce_sgid_type sgid_type = GID_TYPE_FLAG_ROCE_V1;
3226 int ret;
3227
3228 if (gid) {
3229 if (attr->gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP) {
3230 if (ipv6_addr_v4mapped((void *)gid))
3231 sgid_type = GID_TYPE_FLAG_ROCE_V2_IPV4;
3232 else
3233 sgid_type = GID_TYPE_FLAG_ROCE_V2_IPV6;
3234 } else if (attr->gid_type == IB_GID_TYPE_ROCE) {
3235 sgid_type = GID_TYPE_FLAG_ROCE_V1;
3236 }
3237 }
3238
3239 if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09)
3240 ret = config_gmv_table(hr_dev, gid_index, gid, sgid_type, attr);
3241 else
3242 ret = config_sgid_table(hr_dev, gid_index, gid, sgid_type);
3243
3244 if (ret)
3245 ibdev_err(&hr_dev->ib_dev, "failed to set gid, ret = %d!\n",
3246 ret);
3247
3248 return ret;
3249 }
3250
hns_roce_v2_set_mac(struct hns_roce_dev * hr_dev,u8 phy_port,const u8 * addr)3251 static int hns_roce_v2_set_mac(struct hns_roce_dev *hr_dev, u8 phy_port,
3252 const u8 *addr)
3253 {
3254 struct hns_roce_cmq_desc desc;
3255 struct hns_roce_cfg_smac_tb *smac_tb =
3256 (struct hns_roce_cfg_smac_tb *)desc.data;
3257 u16 reg_smac_h;
3258 u32 reg_smac_l;
3259
3260 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CFG_SMAC_TB, false);
3261
3262 reg_smac_l = *(u32 *)(&addr[0]);
3263 reg_smac_h = *(u16 *)(&addr[4]);
3264
3265 hr_reg_write(smac_tb, CFG_SMAC_TB_IDX, phy_port);
3266 hr_reg_write(smac_tb, CFG_SMAC_TB_VF_SMAC_H, reg_smac_h);
3267 smac_tb->vf_smac_l = cpu_to_le32(reg_smac_l);
3268
3269 return hns_roce_cmq_send(hr_dev, &desc, 1);
3270 }
3271
set_mtpt_pbl(struct hns_roce_dev * hr_dev,struct hns_roce_v2_mpt_entry * mpt_entry,struct hns_roce_mr * mr)3272 static int set_mtpt_pbl(struct hns_roce_dev *hr_dev,
3273 struct hns_roce_v2_mpt_entry *mpt_entry,
3274 struct hns_roce_mr *mr)
3275 {
3276 u64 pages[HNS_ROCE_V2_MAX_INNER_MTPT_NUM] = { 0 };
3277 struct ib_device *ibdev = &hr_dev->ib_dev;
3278 dma_addr_t pbl_ba;
3279 int ret;
3280 int i;
3281
3282 ret = hns_roce_mtr_find(hr_dev, &mr->pbl_mtr, 0, pages,
3283 min_t(int, ARRAY_SIZE(pages), mr->npages));
3284 if (ret) {
3285 ibdev_err(ibdev, "failed to find PBL mtr, ret = %d.\n", ret);
3286 return ret;
3287 }
3288
3289 /* Aligned to the hardware address access unit */
3290 for (i = 0; i < ARRAY_SIZE(pages); i++)
3291 pages[i] >>= MPT_PBL_BUF_ADDR_S;
3292
3293 pbl_ba = hns_roce_get_mtr_ba(&mr->pbl_mtr);
3294
3295 mpt_entry->pbl_size = cpu_to_le32(mr->npages);
3296 mpt_entry->pbl_ba_l = cpu_to_le32(pbl_ba >> MPT_PBL_BA_ADDR_S);
3297 hr_reg_write(mpt_entry, MPT_PBL_BA_H,
3298 upper_32_bits(pbl_ba >> MPT_PBL_BA_ADDR_S));
3299
3300 mpt_entry->pa0_l = cpu_to_le32(lower_32_bits(pages[0]));
3301 hr_reg_write(mpt_entry, MPT_PA0_H, upper_32_bits(pages[0]));
3302
3303 mpt_entry->pa1_l = cpu_to_le32(lower_32_bits(pages[1]));
3304 hr_reg_write(mpt_entry, MPT_PA1_H, upper_32_bits(pages[1]));
3305 hr_reg_write(mpt_entry, MPT_PBL_BUF_PG_SZ,
3306 to_hr_hw_page_shift(mr->pbl_mtr.hem_cfg.buf_pg_shift));
3307
3308 return 0;
3309 }
3310
hns_roce_v2_write_mtpt(struct hns_roce_dev * hr_dev,void * mb_buf,struct hns_roce_mr * mr)3311 static int hns_roce_v2_write_mtpt(struct hns_roce_dev *hr_dev,
3312 void *mb_buf, struct hns_roce_mr *mr)
3313 {
3314 struct hns_roce_v2_mpt_entry *mpt_entry;
3315
3316 mpt_entry = mb_buf;
3317 memset(mpt_entry, 0, sizeof(*mpt_entry));
3318
3319 hr_reg_write(mpt_entry, MPT_ST, V2_MPT_ST_VALID);
3320 hr_reg_write(mpt_entry, MPT_PD, mr->pd);
3321
3322 hr_reg_write_bool(mpt_entry, MPT_BIND_EN,
3323 mr->access & IB_ACCESS_MW_BIND);
3324 hr_reg_write_bool(mpt_entry, MPT_ATOMIC_EN,
3325 mr->access & IB_ACCESS_REMOTE_ATOMIC);
3326 hr_reg_write_bool(mpt_entry, MPT_RR_EN,
3327 mr->access & IB_ACCESS_REMOTE_READ);
3328 hr_reg_write_bool(mpt_entry, MPT_RW_EN,
3329 mr->access & IB_ACCESS_REMOTE_WRITE);
3330 hr_reg_write_bool(mpt_entry, MPT_LW_EN,
3331 mr->access & IB_ACCESS_LOCAL_WRITE);
3332
3333 mpt_entry->len_l = cpu_to_le32(lower_32_bits(mr->size));
3334 mpt_entry->len_h = cpu_to_le32(upper_32_bits(mr->size));
3335 mpt_entry->lkey = cpu_to_le32(mr->key);
3336 mpt_entry->va_l = cpu_to_le32(lower_32_bits(mr->iova));
3337 mpt_entry->va_h = cpu_to_le32(upper_32_bits(mr->iova));
3338
3339 if (mr->type != MR_TYPE_MR)
3340 hr_reg_enable(mpt_entry, MPT_PA);
3341
3342 if (mr->type == MR_TYPE_DMA)
3343 return 0;
3344
3345 if (mr->pbl_hop_num != HNS_ROCE_HOP_NUM_0)
3346 hr_reg_write(mpt_entry, MPT_PBL_HOP_NUM, mr->pbl_hop_num);
3347
3348 hr_reg_write(mpt_entry, MPT_PBL_BA_PG_SZ,
3349 to_hr_hw_page_shift(mr->pbl_mtr.hem_cfg.ba_pg_shift));
3350 hr_reg_enable(mpt_entry, MPT_INNER_PA_VLD);
3351
3352 return set_mtpt_pbl(hr_dev, mpt_entry, mr);
3353 }
3354
hns_roce_v2_rereg_write_mtpt(struct hns_roce_dev * hr_dev,struct hns_roce_mr * mr,int flags,void * mb_buf)3355 static int hns_roce_v2_rereg_write_mtpt(struct hns_roce_dev *hr_dev,
3356 struct hns_roce_mr *mr, int flags,
3357 void *mb_buf)
3358 {
3359 struct hns_roce_v2_mpt_entry *mpt_entry = mb_buf;
3360 u32 mr_access_flags = mr->access;
3361 int ret = 0;
3362
3363 hr_reg_write(mpt_entry, MPT_ST, V2_MPT_ST_VALID);
3364 hr_reg_write(mpt_entry, MPT_PD, mr->pd);
3365
3366 if (flags & IB_MR_REREG_ACCESS) {
3367 hr_reg_write(mpt_entry, MPT_BIND_EN,
3368 (mr_access_flags & IB_ACCESS_MW_BIND ? 1 : 0));
3369 hr_reg_write(mpt_entry, MPT_ATOMIC_EN,
3370 mr_access_flags & IB_ACCESS_REMOTE_ATOMIC ? 1 : 0);
3371 hr_reg_write(mpt_entry, MPT_RR_EN,
3372 mr_access_flags & IB_ACCESS_REMOTE_READ ? 1 : 0);
3373 hr_reg_write(mpt_entry, MPT_RW_EN,
3374 mr_access_flags & IB_ACCESS_REMOTE_WRITE ? 1 : 0);
3375 hr_reg_write(mpt_entry, MPT_LW_EN,
3376 mr_access_flags & IB_ACCESS_LOCAL_WRITE ? 1 : 0);
3377 }
3378
3379 if (flags & IB_MR_REREG_TRANS) {
3380 mpt_entry->va_l = cpu_to_le32(lower_32_bits(mr->iova));
3381 mpt_entry->va_h = cpu_to_le32(upper_32_bits(mr->iova));
3382 mpt_entry->len_l = cpu_to_le32(lower_32_bits(mr->size));
3383 mpt_entry->len_h = cpu_to_le32(upper_32_bits(mr->size));
3384
3385 ret = set_mtpt_pbl(hr_dev, mpt_entry, mr);
3386 }
3387
3388 return ret;
3389 }
3390
hns_roce_v2_frmr_write_mtpt(void * mb_buf,struct hns_roce_mr * mr)3391 static int hns_roce_v2_frmr_write_mtpt(void *mb_buf, struct hns_roce_mr *mr)
3392 {
3393 dma_addr_t pbl_ba = hns_roce_get_mtr_ba(&mr->pbl_mtr);
3394 struct hns_roce_v2_mpt_entry *mpt_entry;
3395
3396 mpt_entry = mb_buf;
3397 memset(mpt_entry, 0, sizeof(*mpt_entry));
3398
3399 hr_reg_write(mpt_entry, MPT_ST, V2_MPT_ST_FREE);
3400 hr_reg_write(mpt_entry, MPT_PD, mr->pd);
3401
3402 hr_reg_enable(mpt_entry, MPT_RA_EN);
3403 hr_reg_enable(mpt_entry, MPT_R_INV_EN);
3404
3405 hr_reg_enable(mpt_entry, MPT_FRE);
3406 hr_reg_clear(mpt_entry, MPT_MR_MW);
3407 hr_reg_enable(mpt_entry, MPT_BPD);
3408 hr_reg_clear(mpt_entry, MPT_PA);
3409
3410 hr_reg_write(mpt_entry, MPT_PBL_HOP_NUM, 1);
3411 hr_reg_write(mpt_entry, MPT_PBL_BA_PG_SZ,
3412 to_hr_hw_page_shift(mr->pbl_mtr.hem_cfg.ba_pg_shift));
3413 hr_reg_write(mpt_entry, MPT_PBL_BUF_PG_SZ,
3414 to_hr_hw_page_shift(mr->pbl_mtr.hem_cfg.buf_pg_shift));
3415
3416 mpt_entry->pbl_size = cpu_to_le32(mr->npages);
3417
3418 mpt_entry->pbl_ba_l = cpu_to_le32(lower_32_bits(pbl_ba >>
3419 MPT_PBL_BA_ADDR_S));
3420 hr_reg_write(mpt_entry, MPT_PBL_BA_H,
3421 upper_32_bits(pbl_ba >> MPT_PBL_BA_ADDR_S));
3422
3423 return 0;
3424 }
3425
hns_roce_v2_mw_write_mtpt(void * mb_buf,struct hns_roce_mw * mw)3426 static int hns_roce_v2_mw_write_mtpt(void *mb_buf, struct hns_roce_mw *mw)
3427 {
3428 struct hns_roce_v2_mpt_entry *mpt_entry;
3429
3430 mpt_entry = mb_buf;
3431 memset(mpt_entry, 0, sizeof(*mpt_entry));
3432
3433 hr_reg_write(mpt_entry, MPT_ST, V2_MPT_ST_FREE);
3434 hr_reg_write(mpt_entry, MPT_PD, mw->pdn);
3435
3436 hr_reg_enable(mpt_entry, MPT_R_INV_EN);
3437 hr_reg_enable(mpt_entry, MPT_LW_EN);
3438
3439 hr_reg_enable(mpt_entry, MPT_MR_MW);
3440 hr_reg_enable(mpt_entry, MPT_BPD);
3441 hr_reg_clear(mpt_entry, MPT_PA);
3442 hr_reg_write(mpt_entry, MPT_BQP,
3443 mw->ibmw.type == IB_MW_TYPE_1 ? 0 : 1);
3444
3445 mpt_entry->lkey = cpu_to_le32(mw->rkey);
3446
3447 hr_reg_write(mpt_entry, MPT_PBL_HOP_NUM,
3448 mw->pbl_hop_num == HNS_ROCE_HOP_NUM_0 ? 0 :
3449 mw->pbl_hop_num);
3450 hr_reg_write(mpt_entry, MPT_PBL_BA_PG_SZ,
3451 mw->pbl_ba_pg_sz + PG_SHIFT_OFFSET);
3452 hr_reg_write(mpt_entry, MPT_PBL_BUF_PG_SZ,
3453 mw->pbl_buf_pg_sz + PG_SHIFT_OFFSET);
3454
3455 return 0;
3456 }
3457
free_mr_post_send_lp_wqe(struct hns_roce_qp * hr_qp)3458 static int free_mr_post_send_lp_wqe(struct hns_roce_qp *hr_qp)
3459 {
3460 struct hns_roce_dev *hr_dev = to_hr_dev(hr_qp->ibqp.device);
3461 struct ib_device *ibdev = &hr_dev->ib_dev;
3462 const struct ib_send_wr *bad_wr;
3463 struct ib_rdma_wr rdma_wr = {};
3464 struct ib_send_wr *send_wr;
3465 int ret;
3466
3467 send_wr = &rdma_wr.wr;
3468 send_wr->opcode = IB_WR_RDMA_WRITE;
3469
3470 ret = hns_roce_v2_post_send(&hr_qp->ibqp, send_wr, &bad_wr);
3471 if (ret) {
3472 ibdev_err_ratelimited(ibdev, "failed to post wqe for free mr, ret = %d.\n",
3473 ret);
3474 return ret;
3475 }
3476
3477 return 0;
3478 }
3479
3480 static int hns_roce_v2_poll_cq(struct ib_cq *ibcq, int num_entries,
3481 struct ib_wc *wc);
3482
free_mr_send_cmd_to_hw(struct hns_roce_dev * hr_dev)3483 static void free_mr_send_cmd_to_hw(struct hns_roce_dev *hr_dev)
3484 {
3485 struct hns_roce_v2_priv *priv = hr_dev->priv;
3486 struct hns_roce_v2_free_mr *free_mr = &priv->free_mr;
3487 struct ib_wc wc[ARRAY_SIZE(free_mr->rsv_qp)];
3488 struct ib_device *ibdev = &hr_dev->ib_dev;
3489 struct hns_roce_qp *hr_qp;
3490 unsigned long end;
3491 int cqe_cnt = 0;
3492 int npolled;
3493 int ret;
3494 int i;
3495
3496 /*
3497 * If the device initialization is not complete or in the uninstall
3498 * process, then there is no need to execute free mr.
3499 */
3500 if (priv->handle->rinfo.reset_state == HNS_ROCE_STATE_RST_INIT ||
3501 priv->handle->rinfo.instance_state == HNS_ROCE_STATE_INIT ||
3502 hr_dev->state == HNS_ROCE_DEVICE_STATE_UNINIT)
3503 return;
3504
3505 mutex_lock(&free_mr->mutex);
3506
3507 for (i = 0; i < ARRAY_SIZE(free_mr->rsv_qp); i++) {
3508 hr_qp = free_mr->rsv_qp[i];
3509
3510 ret = free_mr_post_send_lp_wqe(hr_qp);
3511 if (ret) {
3512 ibdev_err_ratelimited(ibdev,
3513 "failed to send wqe (qp:0x%lx) for free mr, ret = %d.\n",
3514 hr_qp->qpn, ret);
3515 break;
3516 }
3517
3518 cqe_cnt++;
3519 }
3520
3521 end = msecs_to_jiffies(HNS_ROCE_V2_FREE_MR_TIMEOUT) + jiffies;
3522 while (cqe_cnt) {
3523 npolled = hns_roce_v2_poll_cq(&free_mr->rsv_cq->ib_cq, cqe_cnt, wc);
3524 if (npolled < 0) {
3525 ibdev_err_ratelimited(ibdev,
3526 "failed to poll cqe for free mr, remain %d cqe.\n",
3527 cqe_cnt);
3528 goto out;
3529 }
3530
3531 if (time_after(jiffies, end)) {
3532 ibdev_err_ratelimited(ibdev,
3533 "failed to poll cqe for free mr and timeout, remain %d cqe.\n",
3534 cqe_cnt);
3535 goto out;
3536 }
3537 cqe_cnt -= npolled;
3538 }
3539
3540 out:
3541 mutex_unlock(&free_mr->mutex);
3542 }
3543
hns_roce_v2_dereg_mr(struct hns_roce_dev * hr_dev)3544 static void hns_roce_v2_dereg_mr(struct hns_roce_dev *hr_dev)
3545 {
3546 if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08)
3547 free_mr_send_cmd_to_hw(hr_dev);
3548 }
3549
get_cqe_v2(struct hns_roce_cq * hr_cq,int n)3550 static void *get_cqe_v2(struct hns_roce_cq *hr_cq, int n)
3551 {
3552 return hns_roce_buf_offset(hr_cq->mtr.kmem, n * hr_cq->cqe_size);
3553 }
3554
get_sw_cqe_v2(struct hns_roce_cq * hr_cq,unsigned int n)3555 static void *get_sw_cqe_v2(struct hns_roce_cq *hr_cq, unsigned int n)
3556 {
3557 struct hns_roce_v2_cqe *cqe = get_cqe_v2(hr_cq, n & hr_cq->ib_cq.cqe);
3558
3559 /* Get cqe when Owner bit is Conversely with the MSB of cons_idx */
3560 return (hr_reg_read(cqe, CQE_OWNER) ^ !!(n & hr_cq->cq_depth)) ? cqe :
3561 NULL;
3562 }
3563
update_cq_db(struct hns_roce_dev * hr_dev,struct hns_roce_cq * hr_cq)3564 static inline void update_cq_db(struct hns_roce_dev *hr_dev,
3565 struct hns_roce_cq *hr_cq)
3566 {
3567 if (likely(hr_cq->flags & HNS_ROCE_CQ_FLAG_RECORD_DB)) {
3568 *hr_cq->set_ci_db = hr_cq->cons_index & V2_CQ_DB_CONS_IDX_M;
3569 } else {
3570 struct hns_roce_v2_db cq_db = {};
3571
3572 hr_reg_write(&cq_db, DB_TAG, hr_cq->cqn);
3573 hr_reg_write(&cq_db, DB_CMD, HNS_ROCE_V2_CQ_DB);
3574 hr_reg_write(&cq_db, DB_CQ_CI, hr_cq->cons_index);
3575 hr_reg_write(&cq_db, DB_CQ_CMD_SN, 1);
3576
3577 hns_roce_write64(hr_dev, (__le32 *)&cq_db, hr_cq->db_reg);
3578 }
3579 }
3580
__hns_roce_v2_cq_clean(struct hns_roce_cq * hr_cq,u32 qpn,struct hns_roce_srq * srq)3581 static void __hns_roce_v2_cq_clean(struct hns_roce_cq *hr_cq, u32 qpn,
3582 struct hns_roce_srq *srq)
3583 {
3584 struct hns_roce_dev *hr_dev = to_hr_dev(hr_cq->ib_cq.device);
3585 struct hns_roce_v2_cqe *cqe, *dest;
3586 u32 prod_index;
3587 int nfreed = 0;
3588 int wqe_index;
3589 u8 owner_bit;
3590
3591 for (prod_index = hr_cq->cons_index; get_sw_cqe_v2(hr_cq, prod_index);
3592 ++prod_index) {
3593 if (prod_index > hr_cq->cons_index + hr_cq->ib_cq.cqe)
3594 break;
3595 }
3596
3597 /*
3598 * Now backwards through the CQ, removing CQ entries
3599 * that match our QP by overwriting them with next entries.
3600 */
3601 while ((int) --prod_index - (int) hr_cq->cons_index >= 0) {
3602 cqe = get_cqe_v2(hr_cq, prod_index & hr_cq->ib_cq.cqe);
3603 if (hr_reg_read(cqe, CQE_LCL_QPN) == qpn) {
3604 if (srq && hr_reg_read(cqe, CQE_S_R)) {
3605 wqe_index = hr_reg_read(cqe, CQE_WQE_IDX);
3606 hns_roce_free_srq_wqe(srq, wqe_index);
3607 }
3608 ++nfreed;
3609 } else if (nfreed) {
3610 dest = get_cqe_v2(hr_cq, (prod_index + nfreed) &
3611 hr_cq->ib_cq.cqe);
3612 owner_bit = hr_reg_read(dest, CQE_OWNER);
3613 memcpy(dest, cqe, hr_cq->cqe_size);
3614 hr_reg_write(dest, CQE_OWNER, owner_bit);
3615 }
3616 }
3617
3618 if (nfreed) {
3619 hr_cq->cons_index += nfreed;
3620 update_cq_db(hr_dev, hr_cq);
3621 }
3622 }
3623
hns_roce_v2_cq_clean(struct hns_roce_cq * hr_cq,u32 qpn,struct hns_roce_srq * srq)3624 static void hns_roce_v2_cq_clean(struct hns_roce_cq *hr_cq, u32 qpn,
3625 struct hns_roce_srq *srq)
3626 {
3627 spin_lock_irq(&hr_cq->lock);
3628 __hns_roce_v2_cq_clean(hr_cq, qpn, srq);
3629 spin_unlock_irq(&hr_cq->lock);
3630 }
3631
hns_roce_v2_write_cqc(struct hns_roce_dev * hr_dev,struct hns_roce_cq * hr_cq,void * mb_buf,u64 * mtts,dma_addr_t dma_handle)3632 static void hns_roce_v2_write_cqc(struct hns_roce_dev *hr_dev,
3633 struct hns_roce_cq *hr_cq, void *mb_buf,
3634 u64 *mtts, dma_addr_t dma_handle)
3635 {
3636 struct hns_roce_v2_cq_context *cq_context;
3637
3638 cq_context = mb_buf;
3639 memset(cq_context, 0, sizeof(*cq_context));
3640
3641 hr_reg_write(cq_context, CQC_CQ_ST, V2_CQ_STATE_VALID);
3642 hr_reg_write(cq_context, CQC_ARM_ST, NO_ARMED);
3643 hr_reg_write(cq_context, CQC_SHIFT, ilog2(hr_cq->cq_depth));
3644 hr_reg_write(cq_context, CQC_CEQN, hr_cq->vector);
3645 hr_reg_write(cq_context, CQC_CQN, hr_cq->cqn);
3646
3647 if (hr_cq->cqe_size == HNS_ROCE_V3_CQE_SIZE)
3648 hr_reg_write(cq_context, CQC_CQE_SIZE, CQE_SIZE_64B);
3649
3650 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_STASH)
3651 hr_reg_enable(cq_context, CQC_STASH);
3652
3653 hr_reg_write(cq_context, CQC_CQE_CUR_BLK_ADDR_L,
3654 to_hr_hw_page_addr(mtts[0]));
3655 hr_reg_write(cq_context, CQC_CQE_CUR_BLK_ADDR_H,
3656 upper_32_bits(to_hr_hw_page_addr(mtts[0])));
3657 hr_reg_write(cq_context, CQC_CQE_HOP_NUM, hr_dev->caps.cqe_hop_num ==
3658 HNS_ROCE_HOP_NUM_0 ? 0 : hr_dev->caps.cqe_hop_num);
3659 hr_reg_write(cq_context, CQC_CQE_NEX_BLK_ADDR_L,
3660 to_hr_hw_page_addr(mtts[1]));
3661 hr_reg_write(cq_context, CQC_CQE_NEX_BLK_ADDR_H,
3662 upper_32_bits(to_hr_hw_page_addr(mtts[1])));
3663 hr_reg_write(cq_context, CQC_CQE_BAR_PG_SZ,
3664 to_hr_hw_page_shift(hr_cq->mtr.hem_cfg.ba_pg_shift));
3665 hr_reg_write(cq_context, CQC_CQE_BUF_PG_SZ,
3666 to_hr_hw_page_shift(hr_cq->mtr.hem_cfg.buf_pg_shift));
3667 hr_reg_write(cq_context, CQC_CQE_BA_L, dma_handle >> CQC_CQE_BA_L_S);
3668 hr_reg_write(cq_context, CQC_CQE_BA_H, dma_handle >> CQC_CQE_BA_H_S);
3669 hr_reg_write_bool(cq_context, CQC_DB_RECORD_EN,
3670 hr_cq->flags & HNS_ROCE_CQ_FLAG_RECORD_DB);
3671 hr_reg_write(cq_context, CQC_CQE_DB_RECORD_ADDR_L,
3672 ((u32)hr_cq->db.dma) >> 1);
3673 hr_reg_write(cq_context, CQC_CQE_DB_RECORD_ADDR_H,
3674 hr_cq->db.dma >> CQC_CQE_DB_RECORD_ADDR_H_S);
3675 hr_reg_write(cq_context, CQC_CQ_MAX_CNT,
3676 HNS_ROCE_V2_CQ_DEFAULT_BURST_NUM);
3677 hr_reg_write(cq_context, CQC_CQ_PERIOD,
3678 HNS_ROCE_V2_CQ_DEFAULT_INTERVAL);
3679 }
3680
hns_roce_v2_req_notify_cq(struct ib_cq * ibcq,enum ib_cq_notify_flags flags)3681 static int hns_roce_v2_req_notify_cq(struct ib_cq *ibcq,
3682 enum ib_cq_notify_flags flags)
3683 {
3684 struct hns_roce_dev *hr_dev = to_hr_dev(ibcq->device);
3685 struct hns_roce_cq *hr_cq = to_hr_cq(ibcq);
3686 struct hns_roce_v2_db cq_db = {};
3687 u32 notify_flag;
3688
3689 /*
3690 * flags = 0, then notify_flag : next
3691 * flags = 1, then notify flag : solocited
3692 */
3693 notify_flag = (flags & IB_CQ_SOLICITED_MASK) == IB_CQ_SOLICITED ?
3694 V2_CQ_DB_REQ_NOT : V2_CQ_DB_REQ_NOT_SOL;
3695
3696 hr_reg_write(&cq_db, DB_TAG, hr_cq->cqn);
3697 hr_reg_write(&cq_db, DB_CMD, HNS_ROCE_V2_CQ_DB_NOTIFY);
3698 hr_reg_write(&cq_db, DB_CQ_CI, hr_cq->cons_index);
3699 hr_reg_write(&cq_db, DB_CQ_CMD_SN, hr_cq->arm_sn);
3700 hr_reg_write(&cq_db, DB_CQ_NOTIFY, notify_flag);
3701
3702 hns_roce_write64(hr_dev, (__le32 *)&cq_db, hr_cq->db_reg);
3703
3704 return 0;
3705 }
3706
sw_comp(struct hns_roce_qp * hr_qp,struct hns_roce_wq * wq,int num_entries,struct ib_wc * wc)3707 static int sw_comp(struct hns_roce_qp *hr_qp, struct hns_roce_wq *wq,
3708 int num_entries, struct ib_wc *wc)
3709 {
3710 unsigned int left;
3711 int npolled = 0;
3712
3713 left = wq->head - wq->tail;
3714 if (left == 0)
3715 return 0;
3716
3717 left = min_t(unsigned int, (unsigned int)num_entries, left);
3718 while (npolled < left) {
3719 wc->wr_id = wq->wrid[wq->tail & (wq->wqe_cnt - 1)];
3720 wc->status = IB_WC_WR_FLUSH_ERR;
3721 wc->vendor_err = 0;
3722 wc->qp = &hr_qp->ibqp;
3723
3724 wq->tail++;
3725 wc++;
3726 npolled++;
3727 }
3728
3729 return npolled;
3730 }
3731
hns_roce_v2_sw_poll_cq(struct hns_roce_cq * hr_cq,int num_entries,struct ib_wc * wc)3732 static int hns_roce_v2_sw_poll_cq(struct hns_roce_cq *hr_cq, int num_entries,
3733 struct ib_wc *wc)
3734 {
3735 struct hns_roce_qp *hr_qp;
3736 int npolled = 0;
3737
3738 list_for_each_entry(hr_qp, &hr_cq->sq_list, sq_node) {
3739 npolled += sw_comp(hr_qp, &hr_qp->sq,
3740 num_entries - npolled, wc + npolled);
3741 if (npolled >= num_entries)
3742 goto out;
3743 }
3744
3745 list_for_each_entry(hr_qp, &hr_cq->rq_list, rq_node) {
3746 npolled += sw_comp(hr_qp, &hr_qp->rq,
3747 num_entries - npolled, wc + npolled);
3748 if (npolled >= num_entries)
3749 goto out;
3750 }
3751
3752 out:
3753 return npolled;
3754 }
3755
get_cqe_status(struct hns_roce_dev * hr_dev,struct hns_roce_qp * qp,struct hns_roce_cq * cq,struct hns_roce_v2_cqe * cqe,struct ib_wc * wc)3756 static void get_cqe_status(struct hns_roce_dev *hr_dev, struct hns_roce_qp *qp,
3757 struct hns_roce_cq *cq, struct hns_roce_v2_cqe *cqe,
3758 struct ib_wc *wc)
3759 {
3760 static const struct {
3761 u32 cqe_status;
3762 enum ib_wc_status wc_status;
3763 } map[] = {
3764 { HNS_ROCE_CQE_V2_SUCCESS, IB_WC_SUCCESS },
3765 { HNS_ROCE_CQE_V2_LOCAL_LENGTH_ERR, IB_WC_LOC_LEN_ERR },
3766 { HNS_ROCE_CQE_V2_LOCAL_QP_OP_ERR, IB_WC_LOC_QP_OP_ERR },
3767 { HNS_ROCE_CQE_V2_LOCAL_PROT_ERR, IB_WC_LOC_PROT_ERR },
3768 { HNS_ROCE_CQE_V2_WR_FLUSH_ERR, IB_WC_WR_FLUSH_ERR },
3769 { HNS_ROCE_CQE_V2_MW_BIND_ERR, IB_WC_MW_BIND_ERR },
3770 { HNS_ROCE_CQE_V2_BAD_RESP_ERR, IB_WC_BAD_RESP_ERR },
3771 { HNS_ROCE_CQE_V2_LOCAL_ACCESS_ERR, IB_WC_LOC_ACCESS_ERR },
3772 { HNS_ROCE_CQE_V2_REMOTE_INVAL_REQ_ERR, IB_WC_REM_INV_REQ_ERR },
3773 { HNS_ROCE_CQE_V2_REMOTE_ACCESS_ERR, IB_WC_REM_ACCESS_ERR },
3774 { HNS_ROCE_CQE_V2_REMOTE_OP_ERR, IB_WC_REM_OP_ERR },
3775 { HNS_ROCE_CQE_V2_TRANSPORT_RETRY_EXC_ERR,
3776 IB_WC_RETRY_EXC_ERR },
3777 { HNS_ROCE_CQE_V2_RNR_RETRY_EXC_ERR, IB_WC_RNR_RETRY_EXC_ERR },
3778 { HNS_ROCE_CQE_V2_REMOTE_ABORT_ERR, IB_WC_REM_ABORT_ERR },
3779 { HNS_ROCE_CQE_V2_GENERAL_ERR, IB_WC_GENERAL_ERR}
3780 };
3781
3782 u32 cqe_status = hr_reg_read(cqe, CQE_STATUS);
3783 int i;
3784
3785 wc->status = IB_WC_GENERAL_ERR;
3786 for (i = 0; i < ARRAY_SIZE(map); i++)
3787 if (cqe_status == map[i].cqe_status) {
3788 wc->status = map[i].wc_status;
3789 break;
3790 }
3791
3792 if (likely(wc->status == IB_WC_SUCCESS ||
3793 wc->status == IB_WC_WR_FLUSH_ERR))
3794 return;
3795
3796 ibdev_err_ratelimited(&hr_dev->ib_dev, "error cqe status 0x%x:\n",
3797 cqe_status);
3798 print_hex_dump(KERN_DEBUG, "", DUMP_PREFIX_NONE, 16, 4, cqe,
3799 cq->cqe_size, false);
3800 wc->vendor_err = hr_reg_read(cqe, CQE_SUB_STATUS);
3801
3802 /*
3803 * For hns ROCEE, GENERAL_ERR is an error type that is not defined in
3804 * the standard protocol, the driver must ignore it and needn't to set
3805 * the QP to an error state.
3806 */
3807 if (cqe_status == HNS_ROCE_CQE_V2_GENERAL_ERR)
3808 return;
3809
3810 flush_cqe(hr_dev, qp);
3811 }
3812
get_cur_qp(struct hns_roce_cq * hr_cq,struct hns_roce_v2_cqe * cqe,struct hns_roce_qp ** cur_qp)3813 static int get_cur_qp(struct hns_roce_cq *hr_cq, struct hns_roce_v2_cqe *cqe,
3814 struct hns_roce_qp **cur_qp)
3815 {
3816 struct hns_roce_dev *hr_dev = to_hr_dev(hr_cq->ib_cq.device);
3817 struct hns_roce_qp *hr_qp = *cur_qp;
3818 u32 qpn;
3819
3820 qpn = hr_reg_read(cqe, CQE_LCL_QPN);
3821
3822 if (!hr_qp || qpn != hr_qp->qpn) {
3823 hr_qp = __hns_roce_qp_lookup(hr_dev, qpn);
3824 if (unlikely(!hr_qp)) {
3825 ibdev_err(&hr_dev->ib_dev,
3826 "CQ %06lx with entry for unknown QPN %06x\n",
3827 hr_cq->cqn, qpn);
3828 return -EINVAL;
3829 }
3830 *cur_qp = hr_qp;
3831 }
3832
3833 return 0;
3834 }
3835
3836 /*
3837 * mapped-value = 1 + real-value
3838 * The ib wc opcode's real value is start from 0, In order to distinguish
3839 * between initialized and uninitialized map values, we plus 1 to the actual
3840 * value when defining the mapping, so that the validity can be identified by
3841 * checking whether the mapped value is greater than 0.
3842 */
3843 #define HR_WC_OP_MAP(hr_key, ib_key) \
3844 [HNS_ROCE_V2_WQE_OP_ ## hr_key] = 1 + IB_WC_ ## ib_key
3845
3846 static const u32 wc_send_op_map[] = {
3847 HR_WC_OP_MAP(SEND, SEND),
3848 HR_WC_OP_MAP(SEND_WITH_INV, SEND),
3849 HR_WC_OP_MAP(SEND_WITH_IMM, SEND),
3850 HR_WC_OP_MAP(RDMA_READ, RDMA_READ),
3851 HR_WC_OP_MAP(RDMA_WRITE, RDMA_WRITE),
3852 HR_WC_OP_MAP(RDMA_WRITE_WITH_IMM, RDMA_WRITE),
3853 HR_WC_OP_MAP(ATOM_CMP_AND_SWAP, COMP_SWAP),
3854 HR_WC_OP_MAP(ATOM_FETCH_AND_ADD, FETCH_ADD),
3855 HR_WC_OP_MAP(ATOM_MSK_CMP_AND_SWAP, MASKED_COMP_SWAP),
3856 HR_WC_OP_MAP(ATOM_MSK_FETCH_AND_ADD, MASKED_FETCH_ADD),
3857 HR_WC_OP_MAP(FAST_REG_PMR, REG_MR),
3858 HR_WC_OP_MAP(BIND_MW, REG_MR),
3859 };
3860
to_ib_wc_send_op(u32 hr_opcode)3861 static int to_ib_wc_send_op(u32 hr_opcode)
3862 {
3863 if (hr_opcode >= ARRAY_SIZE(wc_send_op_map))
3864 return -EINVAL;
3865
3866 return wc_send_op_map[hr_opcode] ? wc_send_op_map[hr_opcode] - 1 :
3867 -EINVAL;
3868 }
3869
3870 static const u32 wc_recv_op_map[] = {
3871 HR_WC_OP_MAP(RDMA_WRITE_WITH_IMM, WITH_IMM),
3872 HR_WC_OP_MAP(SEND, RECV),
3873 HR_WC_OP_MAP(SEND_WITH_IMM, WITH_IMM),
3874 HR_WC_OP_MAP(SEND_WITH_INV, RECV),
3875 };
3876
to_ib_wc_recv_op(u32 hr_opcode)3877 static int to_ib_wc_recv_op(u32 hr_opcode)
3878 {
3879 if (hr_opcode >= ARRAY_SIZE(wc_recv_op_map))
3880 return -EINVAL;
3881
3882 return wc_recv_op_map[hr_opcode] ? wc_recv_op_map[hr_opcode] - 1 :
3883 -EINVAL;
3884 }
3885
fill_send_wc(struct ib_wc * wc,struct hns_roce_v2_cqe * cqe)3886 static void fill_send_wc(struct ib_wc *wc, struct hns_roce_v2_cqe *cqe)
3887 {
3888 u32 hr_opcode;
3889 int ib_opcode;
3890
3891 wc->wc_flags = 0;
3892
3893 hr_opcode = hr_reg_read(cqe, CQE_OPCODE);
3894 switch (hr_opcode) {
3895 case HNS_ROCE_V2_WQE_OP_RDMA_READ:
3896 wc->byte_len = le32_to_cpu(cqe->byte_cnt);
3897 break;
3898 case HNS_ROCE_V2_WQE_OP_SEND_WITH_IMM:
3899 case HNS_ROCE_V2_WQE_OP_RDMA_WRITE_WITH_IMM:
3900 wc->wc_flags |= IB_WC_WITH_IMM;
3901 break;
3902 case HNS_ROCE_V2_WQE_OP_ATOM_CMP_AND_SWAP:
3903 case HNS_ROCE_V2_WQE_OP_ATOM_FETCH_AND_ADD:
3904 case HNS_ROCE_V2_WQE_OP_ATOM_MSK_CMP_AND_SWAP:
3905 case HNS_ROCE_V2_WQE_OP_ATOM_MSK_FETCH_AND_ADD:
3906 wc->byte_len = 8;
3907 break;
3908 default:
3909 break;
3910 }
3911
3912 ib_opcode = to_ib_wc_send_op(hr_opcode);
3913 if (ib_opcode < 0)
3914 wc->status = IB_WC_GENERAL_ERR;
3915 else
3916 wc->opcode = ib_opcode;
3917 }
3918
fill_recv_wc(struct ib_wc * wc,struct hns_roce_v2_cqe * cqe)3919 static int fill_recv_wc(struct ib_wc *wc, struct hns_roce_v2_cqe *cqe)
3920 {
3921 u32 hr_opcode;
3922 int ib_opcode;
3923
3924 wc->byte_len = le32_to_cpu(cqe->byte_cnt);
3925
3926 hr_opcode = hr_reg_read(cqe, CQE_OPCODE);
3927 switch (hr_opcode) {
3928 case HNS_ROCE_V2_OPCODE_RDMA_WRITE_IMM:
3929 case HNS_ROCE_V2_OPCODE_SEND_WITH_IMM:
3930 wc->wc_flags = IB_WC_WITH_IMM;
3931 wc->ex.imm_data = cpu_to_be32(le32_to_cpu(cqe->immtdata));
3932 break;
3933 case HNS_ROCE_V2_OPCODE_SEND_WITH_INV:
3934 wc->wc_flags = IB_WC_WITH_INVALIDATE;
3935 wc->ex.invalidate_rkey = le32_to_cpu(cqe->rkey);
3936 break;
3937 default:
3938 wc->wc_flags = 0;
3939 }
3940
3941 ib_opcode = to_ib_wc_recv_op(hr_opcode);
3942 if (ib_opcode < 0)
3943 wc->status = IB_WC_GENERAL_ERR;
3944 else
3945 wc->opcode = ib_opcode;
3946
3947 wc->sl = hr_reg_read(cqe, CQE_SL);
3948 wc->src_qp = hr_reg_read(cqe, CQE_RMT_QPN);
3949 wc->slid = 0;
3950 wc->wc_flags |= hr_reg_read(cqe, CQE_GRH) ? IB_WC_GRH : 0;
3951 wc->port_num = hr_reg_read(cqe, CQE_PORTN);
3952 wc->pkey_index = 0;
3953
3954 if (hr_reg_read(cqe, CQE_VID_VLD)) {
3955 wc->vlan_id = hr_reg_read(cqe, CQE_VID);
3956 wc->wc_flags |= IB_WC_WITH_VLAN;
3957 } else {
3958 wc->vlan_id = 0xffff;
3959 }
3960
3961 wc->network_hdr_type = hr_reg_read(cqe, CQE_PORT_TYPE);
3962
3963 return 0;
3964 }
3965
hns_roce_v2_poll_one(struct hns_roce_cq * hr_cq,struct hns_roce_qp ** cur_qp,struct ib_wc * wc)3966 static int hns_roce_v2_poll_one(struct hns_roce_cq *hr_cq,
3967 struct hns_roce_qp **cur_qp, struct ib_wc *wc)
3968 {
3969 struct hns_roce_dev *hr_dev = to_hr_dev(hr_cq->ib_cq.device);
3970 struct hns_roce_qp *qp = *cur_qp;
3971 struct hns_roce_srq *srq = NULL;
3972 struct hns_roce_v2_cqe *cqe;
3973 struct hns_roce_wq *wq;
3974 int is_send;
3975 u16 wqe_idx;
3976 int ret;
3977
3978 cqe = get_sw_cqe_v2(hr_cq, hr_cq->cons_index);
3979 if (!cqe)
3980 return -EAGAIN;
3981
3982 ++hr_cq->cons_index;
3983 /* Memory barrier */
3984 rmb();
3985
3986 ret = get_cur_qp(hr_cq, cqe, &qp);
3987 if (ret)
3988 return ret;
3989
3990 wc->qp = &qp->ibqp;
3991 wc->vendor_err = 0;
3992
3993 wqe_idx = hr_reg_read(cqe, CQE_WQE_IDX);
3994
3995 is_send = !hr_reg_read(cqe, CQE_S_R);
3996 if (is_send) {
3997 wq = &qp->sq;
3998
3999 /* If sg_signal_bit is set, tail pointer will be updated to
4000 * the WQE corresponding to the current CQE.
4001 */
4002 if (qp->sq_signal_bits)
4003 wq->tail += (wqe_idx - (u16)wq->tail) &
4004 (wq->wqe_cnt - 1);
4005
4006 wc->wr_id = wq->wrid[wq->tail & (wq->wqe_cnt - 1)];
4007 ++wq->tail;
4008
4009 fill_send_wc(wc, cqe);
4010 } else {
4011 if (qp->ibqp.srq) {
4012 srq = to_hr_srq(qp->ibqp.srq);
4013 wc->wr_id = srq->wrid[wqe_idx];
4014 hns_roce_free_srq_wqe(srq, wqe_idx);
4015 } else {
4016 wq = &qp->rq;
4017 wc->wr_id = wq->wrid[wq->tail & (wq->wqe_cnt - 1)];
4018 ++wq->tail;
4019 }
4020
4021 ret = fill_recv_wc(wc, cqe);
4022 }
4023
4024 get_cqe_status(hr_dev, qp, hr_cq, cqe, wc);
4025 if (unlikely(wc->status != IB_WC_SUCCESS))
4026 return 0;
4027
4028 return ret;
4029 }
4030
hns_roce_v2_poll_cq(struct ib_cq * ibcq,int num_entries,struct ib_wc * wc)4031 static int hns_roce_v2_poll_cq(struct ib_cq *ibcq, int num_entries,
4032 struct ib_wc *wc)
4033 {
4034 struct hns_roce_dev *hr_dev = to_hr_dev(ibcq->device);
4035 struct hns_roce_cq *hr_cq = to_hr_cq(ibcq);
4036 struct hns_roce_qp *cur_qp = NULL;
4037 unsigned long flags;
4038 int npolled;
4039
4040 spin_lock_irqsave(&hr_cq->lock, flags);
4041
4042 /*
4043 * When the device starts to reset, the state is RST_DOWN. At this time,
4044 * there may still be some valid CQEs in the hardware that are not
4045 * polled. Therefore, it is not allowed to switch to the software mode
4046 * immediately. When the state changes to UNINIT, CQE no longer exists
4047 * in the hardware, and then switch to software mode.
4048 */
4049 if (hr_dev->state == HNS_ROCE_DEVICE_STATE_UNINIT) {
4050 npolled = hns_roce_v2_sw_poll_cq(hr_cq, num_entries, wc);
4051 goto out;
4052 }
4053
4054 for (npolled = 0; npolled < num_entries; ++npolled) {
4055 if (hns_roce_v2_poll_one(hr_cq, &cur_qp, wc + npolled))
4056 break;
4057 }
4058
4059 if (npolled)
4060 update_cq_db(hr_dev, hr_cq);
4061
4062 out:
4063 spin_unlock_irqrestore(&hr_cq->lock, flags);
4064
4065 return npolled;
4066 }
4067
get_op_for_set_hem(struct hns_roce_dev * hr_dev,u32 type,u32 step_idx,u8 * mbox_cmd)4068 static int get_op_for_set_hem(struct hns_roce_dev *hr_dev, u32 type,
4069 u32 step_idx, u8 *mbox_cmd)
4070 {
4071 u8 cmd;
4072
4073 switch (type) {
4074 case HEM_TYPE_QPC:
4075 cmd = HNS_ROCE_CMD_WRITE_QPC_BT0;
4076 break;
4077 case HEM_TYPE_MTPT:
4078 cmd = HNS_ROCE_CMD_WRITE_MPT_BT0;
4079 break;
4080 case HEM_TYPE_CQC:
4081 cmd = HNS_ROCE_CMD_WRITE_CQC_BT0;
4082 break;
4083 case HEM_TYPE_SRQC:
4084 cmd = HNS_ROCE_CMD_WRITE_SRQC_BT0;
4085 break;
4086 case HEM_TYPE_SCCC:
4087 cmd = HNS_ROCE_CMD_WRITE_SCCC_BT0;
4088 break;
4089 case HEM_TYPE_QPC_TIMER:
4090 cmd = HNS_ROCE_CMD_WRITE_QPC_TIMER_BT0;
4091 break;
4092 case HEM_TYPE_CQC_TIMER:
4093 cmd = HNS_ROCE_CMD_WRITE_CQC_TIMER_BT0;
4094 break;
4095 default:
4096 dev_warn(hr_dev->dev, "failed to check hem type %u.\n", type);
4097 return -EINVAL;
4098 }
4099
4100 *mbox_cmd = cmd + step_idx;
4101
4102 return 0;
4103 }
4104
config_gmv_ba_to_hw(struct hns_roce_dev * hr_dev,unsigned long obj,dma_addr_t base_addr)4105 static int config_gmv_ba_to_hw(struct hns_roce_dev *hr_dev, unsigned long obj,
4106 dma_addr_t base_addr)
4107 {
4108 struct hns_roce_cmq_desc desc;
4109 struct hns_roce_cmq_req *req = (struct hns_roce_cmq_req *)desc.data;
4110 u32 idx = obj / (HNS_HW_PAGE_SIZE / hr_dev->caps.gmv_entry_sz);
4111 u64 addr = to_hr_hw_page_addr(base_addr);
4112
4113 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CFG_GMV_BT, false);
4114
4115 hr_reg_write(req, CFG_GMV_BT_BA_L, lower_32_bits(addr));
4116 hr_reg_write(req, CFG_GMV_BT_BA_H, upper_32_bits(addr));
4117 hr_reg_write(req, CFG_GMV_BT_IDX, idx);
4118
4119 return hns_roce_cmq_send(hr_dev, &desc, 1);
4120 }
4121
set_hem_to_hw(struct hns_roce_dev * hr_dev,int obj,dma_addr_t base_addr,u32 hem_type,u32 step_idx)4122 static int set_hem_to_hw(struct hns_roce_dev *hr_dev, int obj,
4123 dma_addr_t base_addr, u32 hem_type, u32 step_idx)
4124 {
4125 int ret;
4126 u8 cmd;
4127
4128 if (unlikely(hem_type == HEM_TYPE_GMV))
4129 return config_gmv_ba_to_hw(hr_dev, obj, base_addr);
4130
4131 if (unlikely(hem_type == HEM_TYPE_SCCC && step_idx))
4132 return 0;
4133
4134 ret = get_op_for_set_hem(hr_dev, hem_type, step_idx, &cmd);
4135 if (ret < 0)
4136 return ret;
4137
4138 return config_hem_ba_to_hw(hr_dev, base_addr, cmd, obj);
4139 }
4140
hns_roce_v2_set_hem(struct hns_roce_dev * hr_dev,struct hns_roce_hem_table * table,int obj,u32 step_idx)4141 static int hns_roce_v2_set_hem(struct hns_roce_dev *hr_dev,
4142 struct hns_roce_hem_table *table, int obj,
4143 u32 step_idx)
4144 {
4145 struct hns_roce_hem_mhop mhop;
4146 struct hns_roce_hem *hem;
4147 unsigned long mhop_obj = obj;
4148 int i, j, k;
4149 int ret = 0;
4150 u64 hem_idx = 0;
4151 u64 l1_idx = 0;
4152 u64 bt_ba = 0;
4153 u32 chunk_ba_num;
4154 u32 hop_num;
4155
4156 if (!hns_roce_check_whether_mhop(hr_dev, table->type))
4157 return 0;
4158
4159 hns_roce_calc_hem_mhop(hr_dev, table, &mhop_obj, &mhop);
4160 i = mhop.l0_idx;
4161 j = mhop.l1_idx;
4162 k = mhop.l2_idx;
4163 hop_num = mhop.hop_num;
4164 chunk_ba_num = mhop.bt_chunk_size / 8;
4165
4166 if (hop_num == 2) {
4167 hem_idx = i * chunk_ba_num * chunk_ba_num + j * chunk_ba_num +
4168 k;
4169 l1_idx = i * chunk_ba_num + j;
4170 } else if (hop_num == 1) {
4171 hem_idx = i * chunk_ba_num + j;
4172 } else if (hop_num == HNS_ROCE_HOP_NUM_0) {
4173 hem_idx = i;
4174 }
4175
4176 if (table->type == HEM_TYPE_SCCC)
4177 obj = mhop.l0_idx;
4178
4179 if (check_whether_last_step(hop_num, step_idx)) {
4180 hem = table->hem[hem_idx];
4181
4182 ret = set_hem_to_hw(hr_dev, obj, hem->dma, table->type, step_idx);
4183 } else {
4184 if (step_idx == 0)
4185 bt_ba = table->bt_l0_dma_addr[i];
4186 else if (step_idx == 1 && hop_num == 2)
4187 bt_ba = table->bt_l1_dma_addr[l1_idx];
4188
4189 ret = set_hem_to_hw(hr_dev, obj, bt_ba, table->type, step_idx);
4190 }
4191
4192 return ret;
4193 }
4194
hns_roce_v2_clear_hem(struct hns_roce_dev * hr_dev,struct hns_roce_hem_table * table,int tag,u32 step_idx)4195 static int hns_roce_v2_clear_hem(struct hns_roce_dev *hr_dev,
4196 struct hns_roce_hem_table *table,
4197 int tag, u32 step_idx)
4198 {
4199 struct hns_roce_cmd_mailbox *mailbox;
4200 struct device *dev = hr_dev->dev;
4201 u8 cmd = 0xff;
4202 int ret;
4203
4204 if (!hns_roce_check_whether_mhop(hr_dev, table->type))
4205 return 0;
4206
4207 switch (table->type) {
4208 case HEM_TYPE_QPC:
4209 cmd = HNS_ROCE_CMD_DESTROY_QPC_BT0;
4210 break;
4211 case HEM_TYPE_MTPT:
4212 cmd = HNS_ROCE_CMD_DESTROY_MPT_BT0;
4213 break;
4214 case HEM_TYPE_CQC:
4215 cmd = HNS_ROCE_CMD_DESTROY_CQC_BT0;
4216 break;
4217 case HEM_TYPE_SRQC:
4218 cmd = HNS_ROCE_CMD_DESTROY_SRQC_BT0;
4219 break;
4220 case HEM_TYPE_SCCC:
4221 case HEM_TYPE_QPC_TIMER:
4222 case HEM_TYPE_CQC_TIMER:
4223 case HEM_TYPE_GMV:
4224 return 0;
4225 default:
4226 dev_warn(dev, "table %u not to be destroyed by mailbox!\n",
4227 table->type);
4228 return 0;
4229 }
4230
4231 cmd += step_idx;
4232
4233 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev);
4234 if (IS_ERR(mailbox))
4235 return PTR_ERR(mailbox);
4236
4237 ret = hns_roce_cmd_mbox(hr_dev, 0, mailbox->dma, cmd, tag);
4238
4239 hns_roce_free_cmd_mailbox(hr_dev, mailbox);
4240 return ret;
4241 }
4242
hns_roce_v2_qp_modify(struct hns_roce_dev * hr_dev,struct hns_roce_v2_qp_context * context,struct hns_roce_v2_qp_context * qpc_mask,struct hns_roce_qp * hr_qp)4243 static int hns_roce_v2_qp_modify(struct hns_roce_dev *hr_dev,
4244 struct hns_roce_v2_qp_context *context,
4245 struct hns_roce_v2_qp_context *qpc_mask,
4246 struct hns_roce_qp *hr_qp)
4247 {
4248 struct hns_roce_cmd_mailbox *mailbox;
4249 int qpc_size;
4250 int ret;
4251
4252 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev);
4253 if (IS_ERR(mailbox))
4254 return PTR_ERR(mailbox);
4255
4256 /* The qpc size of HIP08 is only 256B, which is half of HIP09 */
4257 qpc_size = hr_dev->caps.qpc_sz;
4258 memcpy(mailbox->buf, context, qpc_size);
4259 memcpy(mailbox->buf + qpc_size, qpc_mask, qpc_size);
4260
4261 ret = hns_roce_cmd_mbox(hr_dev, mailbox->dma, 0,
4262 HNS_ROCE_CMD_MODIFY_QPC, hr_qp->qpn);
4263
4264 hns_roce_free_cmd_mailbox(hr_dev, mailbox);
4265
4266 return ret;
4267 }
4268
set_access_flags(struct hns_roce_qp * hr_qp,struct hns_roce_v2_qp_context * context,struct hns_roce_v2_qp_context * qpc_mask,const struct ib_qp_attr * attr,int attr_mask)4269 static void set_access_flags(struct hns_roce_qp *hr_qp,
4270 struct hns_roce_v2_qp_context *context,
4271 struct hns_roce_v2_qp_context *qpc_mask,
4272 const struct ib_qp_attr *attr, int attr_mask)
4273 {
4274 u8 dest_rd_atomic;
4275 u32 access_flags;
4276
4277 dest_rd_atomic = (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) ?
4278 attr->max_dest_rd_atomic : hr_qp->resp_depth;
4279
4280 access_flags = (attr_mask & IB_QP_ACCESS_FLAGS) ?
4281 attr->qp_access_flags : hr_qp->atomic_rd_en;
4282
4283 if (!dest_rd_atomic)
4284 access_flags &= IB_ACCESS_REMOTE_WRITE;
4285
4286 hr_reg_write_bool(context, QPC_RRE,
4287 access_flags & IB_ACCESS_REMOTE_READ);
4288 hr_reg_clear(qpc_mask, QPC_RRE);
4289
4290 hr_reg_write_bool(context, QPC_RWE,
4291 access_flags & IB_ACCESS_REMOTE_WRITE);
4292 hr_reg_clear(qpc_mask, QPC_RWE);
4293
4294 hr_reg_write_bool(context, QPC_ATE,
4295 access_flags & IB_ACCESS_REMOTE_ATOMIC);
4296 hr_reg_clear(qpc_mask, QPC_ATE);
4297 hr_reg_write_bool(context, QPC_EXT_ATE,
4298 access_flags & IB_ACCESS_REMOTE_ATOMIC);
4299 hr_reg_clear(qpc_mask, QPC_EXT_ATE);
4300 }
4301
set_qpc_wqe_cnt(struct hns_roce_qp * hr_qp,struct hns_roce_v2_qp_context * context)4302 static void set_qpc_wqe_cnt(struct hns_roce_qp *hr_qp,
4303 struct hns_roce_v2_qp_context *context)
4304 {
4305 hr_reg_write(context, QPC_SGE_SHIFT,
4306 to_hr_hem_entries_shift(hr_qp->sge.sge_cnt,
4307 hr_qp->sge.sge_shift));
4308
4309 hr_reg_write(context, QPC_SQ_SHIFT, ilog2(hr_qp->sq.wqe_cnt));
4310
4311 hr_reg_write(context, QPC_RQ_SHIFT, ilog2(hr_qp->rq.wqe_cnt));
4312 }
4313
get_cqn(struct ib_cq * ib_cq)4314 static inline int get_cqn(struct ib_cq *ib_cq)
4315 {
4316 return ib_cq ? to_hr_cq(ib_cq)->cqn : 0;
4317 }
4318
get_pdn(struct ib_pd * ib_pd)4319 static inline int get_pdn(struct ib_pd *ib_pd)
4320 {
4321 return ib_pd ? to_hr_pd(ib_pd)->pdn : 0;
4322 }
4323
modify_qp_reset_to_init(struct ib_qp * ibqp,struct hns_roce_v2_qp_context * context,struct hns_roce_v2_qp_context * qpc_mask)4324 static void modify_qp_reset_to_init(struct ib_qp *ibqp,
4325 struct hns_roce_v2_qp_context *context,
4326 struct hns_roce_v2_qp_context *qpc_mask)
4327 {
4328 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
4329 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
4330
4331 /*
4332 * In v2 engine, software pass context and context mask to hardware
4333 * when modifying qp. If software need modify some fields in context,
4334 * we should set all bits of the relevant fields in context mask to
4335 * 0 at the same time, else set them to 0x1.
4336 */
4337 hr_reg_write(context, QPC_TST, to_hr_qp_type(ibqp->qp_type));
4338
4339 hr_reg_write(context, QPC_PD, get_pdn(ibqp->pd));
4340
4341 hr_reg_write(context, QPC_RQWS, ilog2(hr_qp->rq.max_gs));
4342
4343 set_qpc_wqe_cnt(hr_qp, context);
4344
4345 /* No VLAN need to set 0xFFF */
4346 hr_reg_write(context, QPC_VLAN_ID, 0xfff);
4347
4348 if (ibqp->qp_type == IB_QPT_XRC_TGT) {
4349 context->qkey_xrcd = cpu_to_le32(hr_qp->xrcdn);
4350
4351 hr_reg_enable(context, QPC_XRC_QP_TYPE);
4352 }
4353
4354 if (hr_qp->en_flags & HNS_ROCE_QP_CAP_RQ_RECORD_DB)
4355 hr_reg_enable(context, QPC_RQ_RECORD_EN);
4356
4357 if (hr_qp->en_flags & HNS_ROCE_QP_CAP_OWNER_DB)
4358 hr_reg_enable(context, QPC_OWNER_MODE);
4359
4360 hr_reg_write(context, QPC_RQ_DB_RECORD_ADDR_L,
4361 lower_32_bits(hr_qp->rdb.dma) >> 1);
4362 hr_reg_write(context, QPC_RQ_DB_RECORD_ADDR_H,
4363 upper_32_bits(hr_qp->rdb.dma));
4364
4365 hr_reg_write(context, QPC_RX_CQN, get_cqn(ibqp->recv_cq));
4366
4367 if (ibqp->srq) {
4368 hr_reg_enable(context, QPC_SRQ_EN);
4369 hr_reg_write(context, QPC_SRQN, to_hr_srq(ibqp->srq)->srqn);
4370 }
4371
4372 hr_reg_enable(context, QPC_FRE);
4373
4374 hr_reg_write(context, QPC_TX_CQN, get_cqn(ibqp->send_cq));
4375
4376 if (hr_dev->caps.qpc_sz < HNS_ROCE_V3_QPC_SZ)
4377 return;
4378
4379 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_STASH)
4380 hr_reg_enable(&context->ext, QPCEX_STASH);
4381 }
4382
modify_qp_init_to_init(struct ib_qp * ibqp,struct hns_roce_v2_qp_context * context,struct hns_roce_v2_qp_context * qpc_mask)4383 static void modify_qp_init_to_init(struct ib_qp *ibqp,
4384 struct hns_roce_v2_qp_context *context,
4385 struct hns_roce_v2_qp_context *qpc_mask)
4386 {
4387 /*
4388 * In v2 engine, software pass context and context mask to hardware
4389 * when modifying qp. If software need modify some fields in context,
4390 * we should set all bits of the relevant fields in context mask to
4391 * 0 at the same time, else set them to 0x1.
4392 */
4393 hr_reg_write(context, QPC_TST, to_hr_qp_type(ibqp->qp_type));
4394 hr_reg_clear(qpc_mask, QPC_TST);
4395
4396 hr_reg_write(context, QPC_PD, get_pdn(ibqp->pd));
4397 hr_reg_clear(qpc_mask, QPC_PD);
4398
4399 hr_reg_write(context, QPC_RX_CQN, get_cqn(ibqp->recv_cq));
4400 hr_reg_clear(qpc_mask, QPC_RX_CQN);
4401
4402 hr_reg_write(context, QPC_TX_CQN, get_cqn(ibqp->send_cq));
4403 hr_reg_clear(qpc_mask, QPC_TX_CQN);
4404
4405 if (ibqp->srq) {
4406 hr_reg_enable(context, QPC_SRQ_EN);
4407 hr_reg_clear(qpc_mask, QPC_SRQ_EN);
4408 hr_reg_write(context, QPC_SRQN, to_hr_srq(ibqp->srq)->srqn);
4409 hr_reg_clear(qpc_mask, QPC_SRQN);
4410 }
4411 }
4412
config_qp_rq_buf(struct hns_roce_dev * hr_dev,struct hns_roce_qp * hr_qp,struct hns_roce_v2_qp_context * context,struct hns_roce_v2_qp_context * qpc_mask)4413 static int config_qp_rq_buf(struct hns_roce_dev *hr_dev,
4414 struct hns_roce_qp *hr_qp,
4415 struct hns_roce_v2_qp_context *context,
4416 struct hns_roce_v2_qp_context *qpc_mask)
4417 {
4418 u64 mtts[MTT_MIN_COUNT] = { 0 };
4419 u64 wqe_sge_ba;
4420 int ret;
4421
4422 /* Search qp buf's mtts */
4423 ret = hns_roce_mtr_find(hr_dev, &hr_qp->mtr, hr_qp->rq.offset, mtts,
4424 MTT_MIN_COUNT);
4425 if (hr_qp->rq.wqe_cnt && ret) {
4426 ibdev_err(&hr_dev->ib_dev,
4427 "failed to find QP(0x%lx) RQ WQE buf, ret = %d.\n",
4428 hr_qp->qpn, ret);
4429 return ret;
4430 }
4431
4432 wqe_sge_ba = hns_roce_get_mtr_ba(&hr_qp->mtr);
4433
4434 context->wqe_sge_ba = cpu_to_le32(wqe_sge_ba >> 3);
4435 qpc_mask->wqe_sge_ba = 0;
4436
4437 /*
4438 * In v2 engine, software pass context and context mask to hardware
4439 * when modifying qp. If software need modify some fields in context,
4440 * we should set all bits of the relevant fields in context mask to
4441 * 0 at the same time, else set them to 0x1.
4442 */
4443 hr_reg_write(context, QPC_WQE_SGE_BA_H, wqe_sge_ba >> (32 + 3));
4444 hr_reg_clear(qpc_mask, QPC_WQE_SGE_BA_H);
4445
4446 hr_reg_write(context, QPC_SQ_HOP_NUM,
4447 to_hr_hem_hopnum(hr_dev->caps.wqe_sq_hop_num,
4448 hr_qp->sq.wqe_cnt));
4449 hr_reg_clear(qpc_mask, QPC_SQ_HOP_NUM);
4450
4451 hr_reg_write(context, QPC_SGE_HOP_NUM,
4452 to_hr_hem_hopnum(hr_dev->caps.wqe_sge_hop_num,
4453 hr_qp->sge.sge_cnt));
4454 hr_reg_clear(qpc_mask, QPC_SGE_HOP_NUM);
4455
4456 hr_reg_write(context, QPC_RQ_HOP_NUM,
4457 to_hr_hem_hopnum(hr_dev->caps.wqe_rq_hop_num,
4458 hr_qp->rq.wqe_cnt));
4459
4460 hr_reg_clear(qpc_mask, QPC_RQ_HOP_NUM);
4461
4462 hr_reg_write(context, QPC_WQE_SGE_BA_PG_SZ,
4463 to_hr_hw_page_shift(hr_qp->mtr.hem_cfg.ba_pg_shift));
4464 hr_reg_clear(qpc_mask, QPC_WQE_SGE_BA_PG_SZ);
4465
4466 hr_reg_write(context, QPC_WQE_SGE_BUF_PG_SZ,
4467 to_hr_hw_page_shift(hr_qp->mtr.hem_cfg.buf_pg_shift));
4468 hr_reg_clear(qpc_mask, QPC_WQE_SGE_BUF_PG_SZ);
4469
4470 context->rq_cur_blk_addr = cpu_to_le32(to_hr_hw_page_addr(mtts[0]));
4471 qpc_mask->rq_cur_blk_addr = 0;
4472
4473 hr_reg_write(context, QPC_RQ_CUR_BLK_ADDR_H,
4474 upper_32_bits(to_hr_hw_page_addr(mtts[0])));
4475 hr_reg_clear(qpc_mask, QPC_RQ_CUR_BLK_ADDR_H);
4476
4477 if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08) {
4478 context->rq_nxt_blk_addr =
4479 cpu_to_le32(to_hr_hw_page_addr(mtts[1]));
4480 qpc_mask->rq_nxt_blk_addr = 0;
4481 hr_reg_write(context, QPC_RQ_NXT_BLK_ADDR_H,
4482 upper_32_bits(to_hr_hw_page_addr(mtts[1])));
4483 hr_reg_clear(qpc_mask, QPC_RQ_NXT_BLK_ADDR_H);
4484 }
4485
4486 return 0;
4487 }
4488
config_qp_sq_buf(struct hns_roce_dev * hr_dev,struct hns_roce_qp * hr_qp,struct hns_roce_v2_qp_context * context,struct hns_roce_v2_qp_context * qpc_mask)4489 static int config_qp_sq_buf(struct hns_roce_dev *hr_dev,
4490 struct hns_roce_qp *hr_qp,
4491 struct hns_roce_v2_qp_context *context,
4492 struct hns_roce_v2_qp_context *qpc_mask)
4493 {
4494 struct ib_device *ibdev = &hr_dev->ib_dev;
4495 u64 sge_cur_blk = 0;
4496 u64 sq_cur_blk = 0;
4497 int ret;
4498
4499 /* search qp buf's mtts */
4500 ret = hns_roce_mtr_find(hr_dev, &hr_qp->mtr, hr_qp->sq.offset,
4501 &sq_cur_blk, 1);
4502 if (ret) {
4503 ibdev_err(ibdev, "failed to find QP(0x%lx) SQ WQE buf, ret = %d.\n",
4504 hr_qp->qpn, ret);
4505 return ret;
4506 }
4507 if (hr_qp->sge.sge_cnt > 0) {
4508 ret = hns_roce_mtr_find(hr_dev, &hr_qp->mtr,
4509 hr_qp->sge.offset, &sge_cur_blk, 1);
4510 if (ret) {
4511 ibdev_err(ibdev, "failed to find QP(0x%lx) SGE buf, ret = %d.\n",
4512 hr_qp->qpn, ret);
4513 return ret;
4514 }
4515 }
4516
4517 /*
4518 * In v2 engine, software pass context and context mask to hardware
4519 * when modifying qp. If software need modify some fields in context,
4520 * we should set all bits of the relevant fields in context mask to
4521 * 0 at the same time, else set them to 0x1.
4522 */
4523 hr_reg_write(context, QPC_SQ_CUR_BLK_ADDR_L,
4524 lower_32_bits(to_hr_hw_page_addr(sq_cur_blk)));
4525 hr_reg_write(context, QPC_SQ_CUR_BLK_ADDR_H,
4526 upper_32_bits(to_hr_hw_page_addr(sq_cur_blk)));
4527 hr_reg_clear(qpc_mask, QPC_SQ_CUR_BLK_ADDR_L);
4528 hr_reg_clear(qpc_mask, QPC_SQ_CUR_BLK_ADDR_H);
4529
4530 hr_reg_write(context, QPC_SQ_CUR_SGE_BLK_ADDR_L,
4531 lower_32_bits(to_hr_hw_page_addr(sge_cur_blk)));
4532 hr_reg_write(context, QPC_SQ_CUR_SGE_BLK_ADDR_H,
4533 upper_32_bits(to_hr_hw_page_addr(sge_cur_blk)));
4534 hr_reg_clear(qpc_mask, QPC_SQ_CUR_SGE_BLK_ADDR_L);
4535 hr_reg_clear(qpc_mask, QPC_SQ_CUR_SGE_BLK_ADDR_H);
4536
4537 hr_reg_write(context, QPC_RX_SQ_CUR_BLK_ADDR_L,
4538 lower_32_bits(to_hr_hw_page_addr(sq_cur_blk)));
4539 hr_reg_write(context, QPC_RX_SQ_CUR_BLK_ADDR_H,
4540 upper_32_bits(to_hr_hw_page_addr(sq_cur_blk)));
4541 hr_reg_clear(qpc_mask, QPC_RX_SQ_CUR_BLK_ADDR_L);
4542 hr_reg_clear(qpc_mask, QPC_RX_SQ_CUR_BLK_ADDR_H);
4543
4544 return 0;
4545 }
4546
get_mtu(struct ib_qp * ibqp,const struct ib_qp_attr * attr)4547 static inline enum ib_mtu get_mtu(struct ib_qp *ibqp,
4548 const struct ib_qp_attr *attr)
4549 {
4550 if (ibqp->qp_type == IB_QPT_GSI || ibqp->qp_type == IB_QPT_UD)
4551 return IB_MTU_4096;
4552
4553 return attr->path_mtu;
4554 }
4555
modify_qp_init_to_rtr(struct ib_qp * ibqp,const struct ib_qp_attr * attr,int attr_mask,struct hns_roce_v2_qp_context * context,struct hns_roce_v2_qp_context * qpc_mask,struct ib_udata * udata)4556 static int modify_qp_init_to_rtr(struct ib_qp *ibqp,
4557 const struct ib_qp_attr *attr, int attr_mask,
4558 struct hns_roce_v2_qp_context *context,
4559 struct hns_roce_v2_qp_context *qpc_mask,
4560 struct ib_udata *udata)
4561 {
4562 struct hns_roce_ucontext *uctx = rdma_udata_to_drv_context(udata,
4563 struct hns_roce_ucontext, ibucontext);
4564 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
4565 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
4566 struct ib_device *ibdev = &hr_dev->ib_dev;
4567 dma_addr_t trrl_ba;
4568 dma_addr_t irrl_ba;
4569 enum ib_mtu ib_mtu;
4570 u8 ack_req_freq;
4571 const u8 *smac;
4572 int lp_msg_len;
4573 u8 lp_pktn_ini;
4574 u64 *mtts;
4575 u8 *dmac;
4576 u32 port;
4577 int mtu;
4578 int ret;
4579
4580 ret = config_qp_rq_buf(hr_dev, hr_qp, context, qpc_mask);
4581 if (ret) {
4582 ibdev_err(ibdev, "failed to config rq buf, ret = %d.\n", ret);
4583 return ret;
4584 }
4585
4586 /* Search IRRL's mtts */
4587 mtts = hns_roce_table_find(hr_dev, &hr_dev->qp_table.irrl_table,
4588 hr_qp->qpn, &irrl_ba);
4589 if (!mtts) {
4590 ibdev_err(ibdev, "failed to find qp irrl_table.\n");
4591 return -EINVAL;
4592 }
4593
4594 /* Search TRRL's mtts */
4595 mtts = hns_roce_table_find(hr_dev, &hr_dev->qp_table.trrl_table,
4596 hr_qp->qpn, &trrl_ba);
4597 if (!mtts) {
4598 ibdev_err(ibdev, "failed to find qp trrl_table.\n");
4599 return -EINVAL;
4600 }
4601
4602 if (attr_mask & IB_QP_ALT_PATH) {
4603 ibdev_err(ibdev, "INIT2RTR attr_mask (0x%x) error.\n",
4604 attr_mask);
4605 return -EINVAL;
4606 }
4607
4608 hr_reg_write(context, QPC_TRRL_BA_L, trrl_ba >> QPC_TRRL_BA_L_S);
4609 hr_reg_clear(qpc_mask, QPC_TRRL_BA_L);
4610 context->trrl_ba = cpu_to_le32(trrl_ba >> QPC_TRRL_BA_M_S);
4611 qpc_mask->trrl_ba = 0;
4612 hr_reg_write(context, QPC_TRRL_BA_H, trrl_ba >> QPC_TRRL_BA_H_S);
4613 hr_reg_clear(qpc_mask, QPC_TRRL_BA_H);
4614
4615 context->irrl_ba = cpu_to_le32(irrl_ba >> QPC_IRRL_BA_L_S);
4616 qpc_mask->irrl_ba = 0;
4617 hr_reg_write(context, QPC_IRRL_BA_H, irrl_ba >> QPC_IRRL_BA_H_S);
4618 hr_reg_clear(qpc_mask, QPC_IRRL_BA_H);
4619
4620 hr_reg_enable(context, QPC_RMT_E2E);
4621 hr_reg_clear(qpc_mask, QPC_RMT_E2E);
4622
4623 hr_reg_write(context, QPC_SIG_TYPE, hr_qp->sq_signal_bits);
4624 hr_reg_clear(qpc_mask, QPC_SIG_TYPE);
4625
4626 port = (attr_mask & IB_QP_PORT) ? (attr->port_num - 1) : hr_qp->port;
4627
4628 smac = (const u8 *)hr_dev->dev_addr[port];
4629 dmac = (u8 *)attr->ah_attr.roce.dmac;
4630 /* when dmac equals smac or loop_idc is 1, it should loopback */
4631 if (ether_addr_equal_unaligned(dmac, smac) ||
4632 hr_dev->loop_idc == 0x1) {
4633 hr_reg_write(context, QPC_LBI, hr_dev->loop_idc);
4634 hr_reg_clear(qpc_mask, QPC_LBI);
4635 }
4636
4637 if (attr_mask & IB_QP_DEST_QPN) {
4638 hr_reg_write(context, QPC_DQPN, attr->dest_qp_num);
4639 hr_reg_clear(qpc_mask, QPC_DQPN);
4640 }
4641
4642 memcpy(&context->dmac, dmac, sizeof(u32));
4643 hr_reg_write(context, QPC_DMAC_H, *((u16 *)(&dmac[4])));
4644 qpc_mask->dmac = 0;
4645 hr_reg_clear(qpc_mask, QPC_DMAC_H);
4646
4647 ib_mtu = get_mtu(ibqp, attr);
4648 hr_qp->path_mtu = ib_mtu;
4649
4650 mtu = ib_mtu_enum_to_int(ib_mtu);
4651 if (WARN_ON(mtu <= 0))
4652 return -EINVAL;
4653 #define MIN_LP_MSG_LEN 1024
4654 /* mtu * (2 ^ lp_pktn_ini) should be in the range of 1024 to mtu */
4655 lp_msg_len = max(mtu, MIN_LP_MSG_LEN);
4656 lp_pktn_ini = ilog2(lp_msg_len / mtu);
4657
4658 if (attr_mask & IB_QP_PATH_MTU) {
4659 hr_reg_write(context, QPC_MTU, ib_mtu);
4660 hr_reg_clear(qpc_mask, QPC_MTU);
4661 }
4662
4663 hr_reg_write(context, QPC_LP_PKTN_INI, lp_pktn_ini);
4664 hr_reg_clear(qpc_mask, QPC_LP_PKTN_INI);
4665
4666 /*
4667 * There are several constraints for ACK_REQ_FREQ:
4668 * 1. mtu * (2 ^ ACK_REQ_FREQ) should not be too large, otherwise
4669 * it may cause some unexpected retries when sending large
4670 * payload.
4671 * 2. ACK_REQ_FREQ should be larger than or equal to LP_PKTN_INI.
4672 * 3. ACK_REQ_FREQ must be equal to LP_PKTN_INI when using LDCP
4673 * or HC3 congestion control algorithm.
4674 */
4675 if (hr_qp->cong_type == CONG_TYPE_LDCP ||
4676 hr_qp->cong_type == CONG_TYPE_HC3 ||
4677 hr_dev->caps.max_ack_req_msg_len < lp_msg_len)
4678 ack_req_freq = lp_pktn_ini;
4679 else
4680 ack_req_freq = ilog2(hr_dev->caps.max_ack_req_msg_len / mtu);
4681 hr_reg_write(context, QPC_ACK_REQ_FREQ, ack_req_freq);
4682 hr_reg_clear(qpc_mask, QPC_ACK_REQ_FREQ);
4683
4684 hr_reg_clear(qpc_mask, QPC_RX_REQ_PSN_ERR);
4685 hr_reg_clear(qpc_mask, QPC_RX_REQ_MSN);
4686 hr_reg_clear(qpc_mask, QPC_RX_REQ_LAST_OPTYPE);
4687
4688 context->rq_rnr_timer = 0;
4689 qpc_mask->rq_rnr_timer = 0;
4690
4691 hr_reg_clear(qpc_mask, QPC_TRRL_HEAD_MAX);
4692 hr_reg_clear(qpc_mask, QPC_TRRL_TAIL_MAX);
4693
4694 #define MAX_LP_SGEN 3
4695 /* rocee send 2^lp_sgen_ini segs every time */
4696 hr_reg_write(context, QPC_LP_SGEN_INI, MAX_LP_SGEN);
4697 hr_reg_clear(qpc_mask, QPC_LP_SGEN_INI);
4698
4699 if (udata && ibqp->qp_type == IB_QPT_RC &&
4700 (uctx->config & HNS_ROCE_RQ_INLINE_FLAGS)) {
4701 hr_reg_write_bool(context, QPC_RQIE,
4702 hr_dev->caps.flags &
4703 HNS_ROCE_CAP_FLAG_RQ_INLINE);
4704 hr_reg_clear(qpc_mask, QPC_RQIE);
4705 }
4706
4707 if (udata &&
4708 (ibqp->qp_type == IB_QPT_RC || ibqp->qp_type == IB_QPT_XRC_TGT) &&
4709 (uctx->config & HNS_ROCE_CQE_INLINE_FLAGS)) {
4710 hr_reg_write_bool(context, QPC_CQEIE,
4711 hr_dev->caps.flags &
4712 HNS_ROCE_CAP_FLAG_CQE_INLINE);
4713 hr_reg_clear(qpc_mask, QPC_CQEIE);
4714
4715 hr_reg_write(context, QPC_CQEIS, 0);
4716 hr_reg_clear(qpc_mask, QPC_CQEIS);
4717 }
4718
4719 return 0;
4720 }
4721
modify_qp_rtr_to_rts(struct ib_qp * ibqp,int attr_mask,struct hns_roce_v2_qp_context * context,struct hns_roce_v2_qp_context * qpc_mask)4722 static int modify_qp_rtr_to_rts(struct ib_qp *ibqp, int attr_mask,
4723 struct hns_roce_v2_qp_context *context,
4724 struct hns_roce_v2_qp_context *qpc_mask)
4725 {
4726 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
4727 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
4728 struct ib_device *ibdev = &hr_dev->ib_dev;
4729 int ret;
4730
4731 /* Not support alternate path and path migration */
4732 if (attr_mask & (IB_QP_ALT_PATH | IB_QP_PATH_MIG_STATE)) {
4733 ibdev_err(ibdev, "RTR2RTS attr_mask (0x%x)error\n", attr_mask);
4734 return -EINVAL;
4735 }
4736
4737 ret = config_qp_sq_buf(hr_dev, hr_qp, context, qpc_mask);
4738 if (ret) {
4739 ibdev_err(ibdev, "failed to config sq buf, ret = %d.\n", ret);
4740 return ret;
4741 }
4742
4743 /*
4744 * Set some fields in context to zero, Because the default values
4745 * of all fields in context are zero, we need not set them to 0 again.
4746 * but we should set the relevant fields of context mask to 0.
4747 */
4748 hr_reg_clear(qpc_mask, QPC_IRRL_SGE_IDX);
4749
4750 hr_reg_clear(qpc_mask, QPC_RX_ACK_MSN);
4751
4752 hr_reg_clear(qpc_mask, QPC_ACK_LAST_OPTYPE);
4753 hr_reg_clear(qpc_mask, QPC_IRRL_PSN_VLD);
4754 hr_reg_clear(qpc_mask, QPC_IRRL_PSN);
4755
4756 hr_reg_clear(qpc_mask, QPC_IRRL_TAIL_REAL);
4757
4758 hr_reg_clear(qpc_mask, QPC_RETRY_MSG_MSN);
4759
4760 hr_reg_clear(qpc_mask, QPC_RNR_RETRY_FLAG);
4761
4762 hr_reg_clear(qpc_mask, QPC_CHECK_FLG);
4763
4764 hr_reg_clear(qpc_mask, QPC_V2_IRRL_HEAD);
4765
4766 return 0;
4767 }
4768
alloc_dip_entry(struct xarray * dip_xa,u32 qpn)4769 static int alloc_dip_entry(struct xarray *dip_xa, u32 qpn)
4770 {
4771 struct hns_roce_dip *hr_dip;
4772 int ret;
4773
4774 hr_dip = xa_load(dip_xa, qpn);
4775 if (hr_dip)
4776 return 0;
4777
4778 hr_dip = kzalloc(sizeof(*hr_dip), GFP_KERNEL);
4779 if (!hr_dip)
4780 return -ENOMEM;
4781
4782 ret = xa_err(xa_store(dip_xa, qpn, hr_dip, GFP_KERNEL));
4783 if (ret)
4784 kfree(hr_dip);
4785
4786 return ret;
4787 }
4788
get_dip_ctx_idx(struct ib_qp * ibqp,const struct ib_qp_attr * attr,u32 * dip_idx)4789 static int get_dip_ctx_idx(struct ib_qp *ibqp, const struct ib_qp_attr *attr,
4790 u32 *dip_idx)
4791 {
4792 const struct ib_global_route *grh = rdma_ah_read_grh(&attr->ah_attr);
4793 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
4794 struct xarray *dip_xa = &hr_dev->qp_table.dip_xa;
4795 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
4796 struct hns_roce_dip *hr_dip;
4797 unsigned long idx;
4798 int ret = 0;
4799
4800 ret = alloc_dip_entry(dip_xa, ibqp->qp_num);
4801 if (ret)
4802 return ret;
4803
4804 xa_lock(dip_xa);
4805
4806 xa_for_each(dip_xa, idx, hr_dip) {
4807 if (hr_dip->qp_cnt &&
4808 !memcmp(grh->dgid.raw, hr_dip->dgid, GID_LEN_V2)) {
4809 *dip_idx = hr_dip->dip_idx;
4810 hr_dip->qp_cnt++;
4811 hr_qp->dip = hr_dip;
4812 goto out;
4813 }
4814 }
4815
4816 /* If no dgid is found, a new dip and a mapping between dgid and
4817 * dip_idx will be created.
4818 */
4819 xa_for_each(dip_xa, idx, hr_dip) {
4820 if (hr_dip->qp_cnt)
4821 continue;
4822
4823 *dip_idx = idx;
4824 memcpy(hr_dip->dgid, grh->dgid.raw, sizeof(grh->dgid.raw));
4825 hr_dip->dip_idx = idx;
4826 hr_dip->qp_cnt++;
4827 hr_qp->dip = hr_dip;
4828 break;
4829 }
4830
4831 /* This should never happen. */
4832 if (WARN_ON_ONCE(!hr_qp->dip))
4833 ret = -ENOSPC;
4834
4835 out:
4836 xa_unlock(dip_xa);
4837 return ret;
4838 }
4839
4840 enum {
4841 CONG_DCQCN,
4842 CONG_WINDOW,
4843 };
4844
4845 enum {
4846 UNSUPPORT_CONG_LEVEL,
4847 SUPPORT_CONG_LEVEL,
4848 };
4849
4850 enum {
4851 CONG_LDCP,
4852 CONG_HC3,
4853 };
4854
4855 enum {
4856 DIP_INVALID,
4857 DIP_VALID,
4858 };
4859
4860 enum {
4861 WND_LIMIT,
4862 WND_UNLIMIT,
4863 };
4864
check_cong_type(struct ib_qp * ibqp,struct hns_roce_congestion_algorithm * cong_alg)4865 static int check_cong_type(struct ib_qp *ibqp,
4866 struct hns_roce_congestion_algorithm *cong_alg)
4867 {
4868 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
4869
4870 /* different congestion types match different configurations */
4871 switch (hr_qp->cong_type) {
4872 case CONG_TYPE_DCQCN:
4873 cong_alg->alg_sel = CONG_DCQCN;
4874 cong_alg->alg_sub_sel = UNSUPPORT_CONG_LEVEL;
4875 cong_alg->dip_vld = DIP_INVALID;
4876 cong_alg->wnd_mode_sel = WND_LIMIT;
4877 break;
4878 case CONG_TYPE_LDCP:
4879 cong_alg->alg_sel = CONG_WINDOW;
4880 cong_alg->alg_sub_sel = CONG_LDCP;
4881 cong_alg->dip_vld = DIP_INVALID;
4882 cong_alg->wnd_mode_sel = WND_UNLIMIT;
4883 break;
4884 case CONG_TYPE_HC3:
4885 cong_alg->alg_sel = CONG_WINDOW;
4886 cong_alg->alg_sub_sel = CONG_HC3;
4887 cong_alg->dip_vld = DIP_INVALID;
4888 cong_alg->wnd_mode_sel = WND_LIMIT;
4889 break;
4890 case CONG_TYPE_DIP:
4891 cong_alg->alg_sel = CONG_DCQCN;
4892 cong_alg->alg_sub_sel = UNSUPPORT_CONG_LEVEL;
4893 cong_alg->dip_vld = DIP_VALID;
4894 cong_alg->wnd_mode_sel = WND_LIMIT;
4895 break;
4896 default:
4897 hr_qp->cong_type = CONG_TYPE_DCQCN;
4898 cong_alg->alg_sel = CONG_DCQCN;
4899 cong_alg->alg_sub_sel = UNSUPPORT_CONG_LEVEL;
4900 cong_alg->dip_vld = DIP_INVALID;
4901 cong_alg->wnd_mode_sel = WND_LIMIT;
4902 break;
4903 }
4904
4905 return 0;
4906 }
4907
fill_cong_field(struct ib_qp * ibqp,const struct ib_qp_attr * attr,struct hns_roce_v2_qp_context * context,struct hns_roce_v2_qp_context * qpc_mask)4908 static int fill_cong_field(struct ib_qp *ibqp, const struct ib_qp_attr *attr,
4909 struct hns_roce_v2_qp_context *context,
4910 struct hns_roce_v2_qp_context *qpc_mask)
4911 {
4912 const struct ib_global_route *grh = rdma_ah_read_grh(&attr->ah_attr);
4913 struct hns_roce_congestion_algorithm cong_field;
4914 struct ib_device *ibdev = ibqp->device;
4915 struct hns_roce_dev *hr_dev = to_hr_dev(ibdev);
4916 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
4917 u32 dip_idx = 0;
4918 int ret;
4919
4920 if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08 ||
4921 grh->sgid_attr->gid_type == IB_GID_TYPE_ROCE)
4922 return 0;
4923
4924 ret = check_cong_type(ibqp, &cong_field);
4925 if (ret)
4926 return ret;
4927
4928 hr_reg_write(context, QPC_CONG_ALGO_TMPL_ID, hr_dev->cong_algo_tmpl_id +
4929 hr_qp->cong_type * HNS_ROCE_CONG_SIZE);
4930 hr_reg_clear(qpc_mask, QPC_CONG_ALGO_TMPL_ID);
4931 hr_reg_write(&context->ext, QPCEX_CONG_ALG_SEL, cong_field.alg_sel);
4932 hr_reg_clear(&qpc_mask->ext, QPCEX_CONG_ALG_SEL);
4933 hr_reg_write(&context->ext, QPCEX_CONG_ALG_SUB_SEL,
4934 cong_field.alg_sub_sel);
4935 hr_reg_clear(&qpc_mask->ext, QPCEX_CONG_ALG_SUB_SEL);
4936 hr_reg_write(&context->ext, QPCEX_DIP_CTX_IDX_VLD, cong_field.dip_vld);
4937 hr_reg_clear(&qpc_mask->ext, QPCEX_DIP_CTX_IDX_VLD);
4938 hr_reg_write(&context->ext, QPCEX_SQ_RQ_NOT_FORBID_EN,
4939 cong_field.wnd_mode_sel);
4940 hr_reg_clear(&qpc_mask->ext, QPCEX_SQ_RQ_NOT_FORBID_EN);
4941
4942 /* if dip is disabled, there is no need to set dip idx */
4943 if (cong_field.dip_vld == 0)
4944 return 0;
4945
4946 ret = get_dip_ctx_idx(ibqp, attr, &dip_idx);
4947 if (ret) {
4948 ibdev_err(ibdev, "failed to fill cong field, ret = %d.\n", ret);
4949 return ret;
4950 }
4951
4952 hr_reg_write(&context->ext, QPCEX_DIP_CTX_IDX, dip_idx);
4953 hr_reg_write(&qpc_mask->ext, QPCEX_DIP_CTX_IDX, 0);
4954
4955 return 0;
4956 }
4957
hns_roce_hw_v2_get_dscp(struct hns_roce_dev * hr_dev,u8 dscp,u8 * tc_mode,u8 * priority)4958 static int hns_roce_hw_v2_get_dscp(struct hns_roce_dev *hr_dev, u8 dscp,
4959 u8 *tc_mode, u8 *priority)
4960 {
4961 struct hns_roce_v2_priv *priv = hr_dev->priv;
4962 struct hnae3_handle *handle = priv->handle;
4963 const struct hnae3_ae_ops *ops = handle->ae_algo->ops;
4964
4965 if (!ops->get_dscp_prio)
4966 return -EOPNOTSUPP;
4967
4968 return ops->get_dscp_prio(handle, dscp, tc_mode, priority);
4969 }
4970
check_sl_valid(struct hns_roce_dev * hr_dev,u8 sl)4971 bool check_sl_valid(struct hns_roce_dev *hr_dev, u8 sl)
4972 {
4973 u32 max_sl;
4974
4975 max_sl = min_t(u32, MAX_SERVICE_LEVEL, hr_dev->caps.sl_num - 1);
4976 if (unlikely(sl > max_sl)) {
4977 ibdev_err_ratelimited(&hr_dev->ib_dev,
4978 "failed to set SL(%u). Shouldn't be larger than %u.\n",
4979 sl, max_sl);
4980 return false;
4981 }
4982
4983 return true;
4984 }
4985
hns_roce_set_sl(struct ib_qp * ibqp,const struct ib_qp_attr * attr,struct hns_roce_v2_qp_context * context,struct hns_roce_v2_qp_context * qpc_mask)4986 static int hns_roce_set_sl(struct ib_qp *ibqp,
4987 const struct ib_qp_attr *attr,
4988 struct hns_roce_v2_qp_context *context,
4989 struct hns_roce_v2_qp_context *qpc_mask)
4990 {
4991 const struct ib_global_route *grh = rdma_ah_read_grh(&attr->ah_attr);
4992 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
4993 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
4994 struct ib_device *ibdev = &hr_dev->ib_dev;
4995 int ret;
4996
4997 ret = hns_roce_hw_v2_get_dscp(hr_dev, get_tclass(&attr->ah_attr.grh),
4998 &hr_qp->tc_mode, &hr_qp->priority);
4999 if (ret && ret != -EOPNOTSUPP &&
5000 grh->sgid_attr->gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP) {
5001 ibdev_err_ratelimited(ibdev,
5002 "failed to get dscp, ret = %d.\n", ret);
5003 return ret;
5004 }
5005
5006 if (hr_qp->tc_mode == HNAE3_TC_MAP_MODE_DSCP &&
5007 grh->sgid_attr->gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP)
5008 hr_qp->sl = hr_qp->priority;
5009 else
5010 hr_qp->sl = rdma_ah_get_sl(&attr->ah_attr);
5011
5012 if (!check_sl_valid(hr_dev, hr_qp->sl))
5013 return -EINVAL;
5014
5015 hr_reg_write(context, QPC_SL, hr_qp->sl);
5016 hr_reg_clear(qpc_mask, QPC_SL);
5017
5018 return 0;
5019 }
5020
hns_roce_v2_set_path(struct ib_qp * ibqp,const struct ib_qp_attr * attr,int attr_mask,struct hns_roce_v2_qp_context * context,struct hns_roce_v2_qp_context * qpc_mask)5021 static int hns_roce_v2_set_path(struct ib_qp *ibqp,
5022 const struct ib_qp_attr *attr,
5023 int attr_mask,
5024 struct hns_roce_v2_qp_context *context,
5025 struct hns_roce_v2_qp_context *qpc_mask)
5026 {
5027 const struct ib_global_route *grh = rdma_ah_read_grh(&attr->ah_attr);
5028 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
5029 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
5030 struct ib_device *ibdev = &hr_dev->ib_dev;
5031 const struct ib_gid_attr *gid_attr = NULL;
5032 u8 sl = rdma_ah_get_sl(&attr->ah_attr);
5033 int is_roce_protocol;
5034 u16 vlan_id = 0xffff;
5035 bool is_udp = false;
5036 u8 ib_port;
5037 u8 hr_port;
5038 int ret;
5039
5040 /*
5041 * If free_mr_en of qp is set, it means that this qp comes from
5042 * free mr. This qp will perform the loopback operation.
5043 * In the loopback scenario, only sl needs to be set.
5044 */
5045 if (hr_qp->free_mr_en) {
5046 if (!check_sl_valid(hr_dev, sl))
5047 return -EINVAL;
5048 hr_reg_write(context, QPC_SL, sl);
5049 hr_reg_clear(qpc_mask, QPC_SL);
5050 hr_qp->sl = sl;
5051 return 0;
5052 }
5053
5054 ib_port = (attr_mask & IB_QP_PORT) ? attr->port_num : hr_qp->port + 1;
5055 hr_port = ib_port - 1;
5056 is_roce_protocol = rdma_cap_eth_ah(&hr_dev->ib_dev, ib_port) &&
5057 rdma_ah_get_ah_flags(&attr->ah_attr) & IB_AH_GRH;
5058
5059 if (is_roce_protocol) {
5060 gid_attr = attr->ah_attr.grh.sgid_attr;
5061 ret = rdma_read_gid_l2_fields(gid_attr, &vlan_id, NULL);
5062 if (ret)
5063 return ret;
5064
5065 is_udp = (gid_attr->gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP);
5066 }
5067
5068 /* Only HIP08 needs to set the vlan_en bits in QPC */
5069 if (vlan_id < VLAN_N_VID &&
5070 hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08) {
5071 hr_reg_enable(context, QPC_RQ_VLAN_EN);
5072 hr_reg_clear(qpc_mask, QPC_RQ_VLAN_EN);
5073 hr_reg_enable(context, QPC_SQ_VLAN_EN);
5074 hr_reg_clear(qpc_mask, QPC_SQ_VLAN_EN);
5075 }
5076
5077 hr_reg_write(context, QPC_VLAN_ID, vlan_id);
5078 hr_reg_clear(qpc_mask, QPC_VLAN_ID);
5079
5080 if (grh->sgid_index >= hr_dev->caps.gid_table_len[hr_port]) {
5081 ibdev_err(ibdev, "sgid_index(%u) too large. max is %d\n",
5082 grh->sgid_index, hr_dev->caps.gid_table_len[hr_port]);
5083 return -EINVAL;
5084 }
5085
5086 if (attr->ah_attr.type != RDMA_AH_ATTR_TYPE_ROCE) {
5087 ibdev_err(ibdev, "ah attr is not RDMA roce type\n");
5088 return -EINVAL;
5089 }
5090
5091 hr_reg_write(context, QPC_UDPSPN,
5092 is_udp ? rdma_get_udp_sport(grh->flow_label, ibqp->qp_num,
5093 attr->dest_qp_num) :
5094 0);
5095
5096 hr_reg_clear(qpc_mask, QPC_UDPSPN);
5097
5098 hr_reg_write(context, QPC_GMV_IDX, grh->sgid_index);
5099
5100 hr_reg_clear(qpc_mask, QPC_GMV_IDX);
5101
5102 hr_reg_write(context, QPC_HOPLIMIT, grh->hop_limit);
5103 hr_reg_clear(qpc_mask, QPC_HOPLIMIT);
5104
5105 ret = fill_cong_field(ibqp, attr, context, qpc_mask);
5106 if (ret)
5107 return ret;
5108
5109 hr_reg_write(context, QPC_TC, get_tclass(&attr->ah_attr.grh));
5110 hr_reg_clear(qpc_mask, QPC_TC);
5111
5112 hr_reg_write(context, QPC_FL, grh->flow_label);
5113 hr_reg_clear(qpc_mask, QPC_FL);
5114 memcpy(context->dgid, grh->dgid.raw, sizeof(grh->dgid.raw));
5115 memset(qpc_mask->dgid, 0, sizeof(grh->dgid.raw));
5116
5117 return hns_roce_set_sl(ibqp, attr, context, qpc_mask);
5118 }
5119
check_qp_state(enum ib_qp_state cur_state,enum ib_qp_state new_state)5120 static bool check_qp_state(enum ib_qp_state cur_state,
5121 enum ib_qp_state new_state)
5122 {
5123 static const bool sm[][IB_QPS_ERR + 1] = {
5124 [IB_QPS_RESET] = { [IB_QPS_RESET] = true,
5125 [IB_QPS_INIT] = true },
5126 [IB_QPS_INIT] = { [IB_QPS_RESET] = true,
5127 [IB_QPS_INIT] = true,
5128 [IB_QPS_RTR] = true,
5129 [IB_QPS_ERR] = true },
5130 [IB_QPS_RTR] = { [IB_QPS_RESET] = true,
5131 [IB_QPS_RTS] = true,
5132 [IB_QPS_ERR] = true },
5133 [IB_QPS_RTS] = { [IB_QPS_RESET] = true,
5134 [IB_QPS_RTS] = true,
5135 [IB_QPS_ERR] = true },
5136 [IB_QPS_SQD] = {},
5137 [IB_QPS_SQE] = {},
5138 [IB_QPS_ERR] = { [IB_QPS_RESET] = true,
5139 [IB_QPS_ERR] = true }
5140 };
5141
5142 return sm[cur_state][new_state];
5143 }
5144
hns_roce_v2_set_abs_fields(struct ib_qp * ibqp,const struct ib_qp_attr * attr,int attr_mask,enum ib_qp_state cur_state,enum ib_qp_state new_state,struct hns_roce_v2_qp_context * context,struct hns_roce_v2_qp_context * qpc_mask,struct ib_udata * udata)5145 static int hns_roce_v2_set_abs_fields(struct ib_qp *ibqp,
5146 const struct ib_qp_attr *attr,
5147 int attr_mask,
5148 enum ib_qp_state cur_state,
5149 enum ib_qp_state new_state,
5150 struct hns_roce_v2_qp_context *context,
5151 struct hns_roce_v2_qp_context *qpc_mask,
5152 struct ib_udata *udata)
5153 {
5154 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
5155 int ret = 0;
5156
5157 if (!check_qp_state(cur_state, new_state))
5158 return -EINVAL;
5159
5160 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
5161 memset(qpc_mask, 0, hr_dev->caps.qpc_sz);
5162 modify_qp_reset_to_init(ibqp, context, qpc_mask);
5163 } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_INIT) {
5164 modify_qp_init_to_init(ibqp, context, qpc_mask);
5165 } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_RTR) {
5166 ret = modify_qp_init_to_rtr(ibqp, attr, attr_mask, context,
5167 qpc_mask, udata);
5168 } else if (cur_state == IB_QPS_RTR && new_state == IB_QPS_RTS) {
5169 ret = modify_qp_rtr_to_rts(ibqp, attr_mask, context, qpc_mask);
5170 }
5171
5172 return ret;
5173 }
5174
check_qp_timeout_cfg_range(struct hns_roce_dev * hr_dev,u8 * timeout)5175 static bool check_qp_timeout_cfg_range(struct hns_roce_dev *hr_dev, u8 *timeout)
5176 {
5177 #define QP_ACK_TIMEOUT_MAX_HIP08 20
5178 #define QP_ACK_TIMEOUT_MAX 31
5179
5180 if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08) {
5181 if (*timeout > QP_ACK_TIMEOUT_MAX_HIP08) {
5182 ibdev_warn(&hr_dev->ib_dev,
5183 "local ACK timeout shall be 0 to 20.\n");
5184 return false;
5185 }
5186 *timeout += HNS_ROCE_V2_QP_ACK_TIMEOUT_OFS_HIP08;
5187 } else if (hr_dev->pci_dev->revision > PCI_REVISION_ID_HIP08) {
5188 if (*timeout > QP_ACK_TIMEOUT_MAX) {
5189 ibdev_warn(&hr_dev->ib_dev,
5190 "local ACK timeout shall be 0 to 31.\n");
5191 return false;
5192 }
5193 }
5194
5195 return true;
5196 }
5197
hns_roce_v2_set_opt_fields(struct ib_qp * ibqp,const struct ib_qp_attr * attr,int attr_mask,struct hns_roce_v2_qp_context * context,struct hns_roce_v2_qp_context * qpc_mask)5198 static int hns_roce_v2_set_opt_fields(struct ib_qp *ibqp,
5199 const struct ib_qp_attr *attr,
5200 int attr_mask,
5201 struct hns_roce_v2_qp_context *context,
5202 struct hns_roce_v2_qp_context *qpc_mask)
5203 {
5204 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
5205 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
5206 int ret = 0;
5207 u8 timeout;
5208
5209 if (attr_mask & IB_QP_AV) {
5210 ret = hns_roce_v2_set_path(ibqp, attr, attr_mask, context,
5211 qpc_mask);
5212 if (ret)
5213 return ret;
5214 }
5215
5216 if (attr_mask & IB_QP_TIMEOUT) {
5217 timeout = attr->timeout;
5218 if (check_qp_timeout_cfg_range(hr_dev, &timeout)) {
5219 hr_reg_write(context, QPC_AT, timeout);
5220 hr_reg_clear(qpc_mask, QPC_AT);
5221 }
5222 }
5223
5224 if (attr_mask & IB_QP_RETRY_CNT) {
5225 hr_reg_write(context, QPC_RETRY_NUM_INIT, attr->retry_cnt);
5226 hr_reg_clear(qpc_mask, QPC_RETRY_NUM_INIT);
5227
5228 hr_reg_write(context, QPC_RETRY_CNT, attr->retry_cnt);
5229 hr_reg_clear(qpc_mask, QPC_RETRY_CNT);
5230 }
5231
5232 if (attr_mask & IB_QP_RNR_RETRY) {
5233 hr_reg_write(context, QPC_RNR_NUM_INIT, attr->rnr_retry);
5234 hr_reg_clear(qpc_mask, QPC_RNR_NUM_INIT);
5235
5236 hr_reg_write(context, QPC_RNR_CNT, attr->rnr_retry);
5237 hr_reg_clear(qpc_mask, QPC_RNR_CNT);
5238 }
5239
5240 if (attr_mask & IB_QP_SQ_PSN) {
5241 hr_reg_write(context, QPC_SQ_CUR_PSN, attr->sq_psn);
5242 hr_reg_clear(qpc_mask, QPC_SQ_CUR_PSN);
5243
5244 hr_reg_write(context, QPC_SQ_MAX_PSN, attr->sq_psn);
5245 hr_reg_clear(qpc_mask, QPC_SQ_MAX_PSN);
5246
5247 hr_reg_write(context, QPC_RETRY_MSG_PSN_L, attr->sq_psn);
5248 hr_reg_clear(qpc_mask, QPC_RETRY_MSG_PSN_L);
5249
5250 hr_reg_write(context, QPC_RETRY_MSG_PSN_H,
5251 attr->sq_psn >> RETRY_MSG_PSN_SHIFT);
5252 hr_reg_clear(qpc_mask, QPC_RETRY_MSG_PSN_H);
5253
5254 hr_reg_write(context, QPC_RETRY_MSG_FPKT_PSN, attr->sq_psn);
5255 hr_reg_clear(qpc_mask, QPC_RETRY_MSG_FPKT_PSN);
5256
5257 hr_reg_write(context, QPC_RX_ACK_EPSN, attr->sq_psn);
5258 hr_reg_clear(qpc_mask, QPC_RX_ACK_EPSN);
5259 }
5260
5261 if ((attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) &&
5262 attr->max_dest_rd_atomic) {
5263 hr_reg_write(context, QPC_RR_MAX,
5264 fls(attr->max_dest_rd_atomic - 1));
5265 hr_reg_clear(qpc_mask, QPC_RR_MAX);
5266 }
5267
5268 if ((attr_mask & IB_QP_MAX_QP_RD_ATOMIC) && attr->max_rd_atomic) {
5269 hr_reg_write(context, QPC_SR_MAX, fls(attr->max_rd_atomic - 1));
5270 hr_reg_clear(qpc_mask, QPC_SR_MAX);
5271 }
5272
5273 if (attr_mask & (IB_QP_ACCESS_FLAGS | IB_QP_MAX_DEST_RD_ATOMIC))
5274 set_access_flags(hr_qp, context, qpc_mask, attr, attr_mask);
5275
5276 if (attr_mask & IB_QP_MIN_RNR_TIMER) {
5277 hr_reg_write(context, QPC_MIN_RNR_TIME,
5278 hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08 ?
5279 HNS_ROCE_RNR_TIMER_10NS : attr->min_rnr_timer);
5280 hr_reg_clear(qpc_mask, QPC_MIN_RNR_TIME);
5281 }
5282
5283 if (attr_mask & IB_QP_RQ_PSN) {
5284 hr_reg_write(context, QPC_RX_REQ_EPSN, attr->rq_psn);
5285 hr_reg_clear(qpc_mask, QPC_RX_REQ_EPSN);
5286
5287 hr_reg_write(context, QPC_RAQ_PSN, attr->rq_psn - 1);
5288 hr_reg_clear(qpc_mask, QPC_RAQ_PSN);
5289 }
5290
5291 if (attr_mask & IB_QP_QKEY) {
5292 context->qkey_xrcd = cpu_to_le32(attr->qkey);
5293 qpc_mask->qkey_xrcd = 0;
5294 hr_qp->qkey = attr->qkey;
5295 }
5296
5297 return ret;
5298 }
5299
hns_roce_v2_record_opt_fields(struct ib_qp * ibqp,const struct ib_qp_attr * attr,int attr_mask)5300 static void hns_roce_v2_record_opt_fields(struct ib_qp *ibqp,
5301 const struct ib_qp_attr *attr,
5302 int attr_mask)
5303 {
5304 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
5305 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
5306
5307 if (attr_mask & IB_QP_ACCESS_FLAGS)
5308 hr_qp->atomic_rd_en = attr->qp_access_flags;
5309
5310 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
5311 hr_qp->resp_depth = attr->max_dest_rd_atomic;
5312 if (attr_mask & IB_QP_PORT) {
5313 hr_qp->port = attr->port_num - 1;
5314 hr_qp->phy_port = hr_dev->iboe.phy_port[hr_qp->port];
5315 }
5316 }
5317
clear_qp(struct hns_roce_qp * hr_qp)5318 static void clear_qp(struct hns_roce_qp *hr_qp)
5319 {
5320 struct ib_qp *ibqp = &hr_qp->ibqp;
5321
5322 if (ibqp->send_cq)
5323 hns_roce_v2_cq_clean(to_hr_cq(ibqp->send_cq),
5324 hr_qp->qpn, NULL);
5325
5326 if (ibqp->recv_cq && ibqp->recv_cq != ibqp->send_cq)
5327 hns_roce_v2_cq_clean(to_hr_cq(ibqp->recv_cq),
5328 hr_qp->qpn, ibqp->srq ?
5329 to_hr_srq(ibqp->srq) : NULL);
5330
5331 if (hr_qp->en_flags & HNS_ROCE_QP_CAP_RQ_RECORD_DB)
5332 *hr_qp->rdb.db_record = 0;
5333
5334 hr_qp->rq.head = 0;
5335 hr_qp->rq.tail = 0;
5336 hr_qp->sq.head = 0;
5337 hr_qp->sq.tail = 0;
5338 hr_qp->next_sge = 0;
5339 }
5340
v2_set_flushed_fields(struct ib_qp * ibqp,struct hns_roce_v2_qp_context * context,struct hns_roce_v2_qp_context * qpc_mask)5341 static void v2_set_flushed_fields(struct ib_qp *ibqp,
5342 struct hns_roce_v2_qp_context *context,
5343 struct hns_roce_v2_qp_context *qpc_mask)
5344 {
5345 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
5346 unsigned long sq_flag = 0;
5347 unsigned long rq_flag = 0;
5348
5349 if (ibqp->qp_type == IB_QPT_XRC_TGT)
5350 return;
5351
5352 spin_lock_irqsave(&hr_qp->sq.lock, sq_flag);
5353 hr_reg_write(context, QPC_SQ_PRODUCER_IDX, hr_qp->sq.head);
5354 hr_reg_clear(qpc_mask, QPC_SQ_PRODUCER_IDX);
5355 hr_qp->state = IB_QPS_ERR;
5356 spin_unlock_irqrestore(&hr_qp->sq.lock, sq_flag);
5357
5358 if (ibqp->srq || ibqp->qp_type == IB_QPT_XRC_INI) /* no RQ */
5359 return;
5360
5361 spin_lock_irqsave(&hr_qp->rq.lock, rq_flag);
5362 hr_reg_write(context, QPC_RQ_PRODUCER_IDX, hr_qp->rq.head);
5363 hr_reg_clear(qpc_mask, QPC_RQ_PRODUCER_IDX);
5364 spin_unlock_irqrestore(&hr_qp->rq.lock, rq_flag);
5365 }
5366
hns_roce_v2_modify_qp(struct ib_qp * ibqp,const struct ib_qp_attr * attr,int attr_mask,enum ib_qp_state cur_state,enum ib_qp_state new_state,struct ib_udata * udata)5367 static int hns_roce_v2_modify_qp(struct ib_qp *ibqp,
5368 const struct ib_qp_attr *attr,
5369 int attr_mask, enum ib_qp_state cur_state,
5370 enum ib_qp_state new_state, struct ib_udata *udata)
5371 {
5372 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
5373 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
5374 struct hns_roce_v2_qp_context *context;
5375 struct hns_roce_v2_qp_context *qpc_mask;
5376 struct ib_device *ibdev = &hr_dev->ib_dev;
5377 int ret = -ENOMEM;
5378
5379 if (attr_mask & ~IB_QP_ATTR_STANDARD_BITS)
5380 return -EOPNOTSUPP;
5381
5382 /*
5383 * In v2 engine, software pass context and context mask to hardware
5384 * when modifying qp. If software need modify some fields in context,
5385 * we should set all bits of the relevant fields in context mask to
5386 * 0 at the same time, else set them to 0x1.
5387 */
5388 context = kvzalloc(sizeof(*context), GFP_KERNEL);
5389 qpc_mask = kvzalloc(sizeof(*qpc_mask), GFP_KERNEL);
5390 if (!context || !qpc_mask)
5391 goto out;
5392
5393 memset(qpc_mask, 0xff, hr_dev->caps.qpc_sz);
5394
5395 ret = hns_roce_v2_set_abs_fields(ibqp, attr, attr_mask, cur_state,
5396 new_state, context, qpc_mask, udata);
5397 if (ret)
5398 goto out;
5399
5400 /* When QP state is err, SQ and RQ WQE should be flushed */
5401 if (new_state == IB_QPS_ERR)
5402 v2_set_flushed_fields(ibqp, context, qpc_mask);
5403
5404 /* Configure the optional fields */
5405 ret = hns_roce_v2_set_opt_fields(ibqp, attr, attr_mask, context,
5406 qpc_mask);
5407 if (ret)
5408 goto out;
5409
5410 hr_reg_write_bool(context, QPC_INV_CREDIT,
5411 to_hr_qp_type(hr_qp->ibqp.qp_type) == SERV_TYPE_XRC ||
5412 ibqp->srq);
5413 hr_reg_clear(qpc_mask, QPC_INV_CREDIT);
5414
5415 /* Every status migrate must change state */
5416 hr_reg_write(context, QPC_QP_ST, new_state);
5417 hr_reg_clear(qpc_mask, QPC_QP_ST);
5418
5419 /* SW pass context to HW */
5420 ret = hns_roce_v2_qp_modify(hr_dev, context, qpc_mask, hr_qp);
5421 if (ret) {
5422 ibdev_err_ratelimited(ibdev, "failed to modify QP, ret = %d.\n", ret);
5423 goto out;
5424 }
5425
5426 hr_qp->state = new_state;
5427
5428 hns_roce_v2_record_opt_fields(ibqp, attr, attr_mask);
5429
5430 if (new_state == IB_QPS_RESET && !ibqp->uobject)
5431 clear_qp(hr_qp);
5432
5433 out:
5434 kvfree(qpc_mask);
5435 kvfree(context);
5436 return ret;
5437 }
5438
to_ib_qp_st(enum hns_roce_v2_qp_state state)5439 static int to_ib_qp_st(enum hns_roce_v2_qp_state state)
5440 {
5441 static const enum ib_qp_state map[] = {
5442 [HNS_ROCE_QP_ST_RST] = IB_QPS_RESET,
5443 [HNS_ROCE_QP_ST_INIT] = IB_QPS_INIT,
5444 [HNS_ROCE_QP_ST_RTR] = IB_QPS_RTR,
5445 [HNS_ROCE_QP_ST_RTS] = IB_QPS_RTS,
5446 [HNS_ROCE_QP_ST_SQD] = IB_QPS_SQD,
5447 [HNS_ROCE_QP_ST_SQER] = IB_QPS_SQE,
5448 [HNS_ROCE_QP_ST_ERR] = IB_QPS_ERR,
5449 [HNS_ROCE_QP_ST_SQ_DRAINING] = IB_QPS_SQD
5450 };
5451
5452 return (state < ARRAY_SIZE(map)) ? map[state] : -1;
5453 }
5454
hns_roce_v2_query_qpc(struct hns_roce_dev * hr_dev,u32 qpn,void * buffer)5455 static int hns_roce_v2_query_qpc(struct hns_roce_dev *hr_dev, u32 qpn,
5456 void *buffer)
5457 {
5458 struct hns_roce_cmd_mailbox *mailbox;
5459 int ret;
5460
5461 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev);
5462 if (IS_ERR(mailbox))
5463 return PTR_ERR(mailbox);
5464
5465 ret = hns_roce_cmd_mbox(hr_dev, 0, mailbox->dma, HNS_ROCE_CMD_QUERY_QPC,
5466 qpn);
5467 if (ret)
5468 goto out;
5469
5470 memcpy(buffer, mailbox->buf, hr_dev->caps.qpc_sz);
5471
5472 out:
5473 hns_roce_free_cmd_mailbox(hr_dev, mailbox);
5474 return ret;
5475 }
5476
hns_roce_v2_query_srqc(struct hns_roce_dev * hr_dev,u32 srqn,void * buffer)5477 static int hns_roce_v2_query_srqc(struct hns_roce_dev *hr_dev, u32 srqn,
5478 void *buffer)
5479 {
5480 struct hns_roce_srq_context *context;
5481 struct hns_roce_cmd_mailbox *mailbox;
5482 int ret;
5483
5484 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev);
5485 if (IS_ERR(mailbox))
5486 return PTR_ERR(mailbox);
5487
5488 context = mailbox->buf;
5489 ret = hns_roce_cmd_mbox(hr_dev, 0, mailbox->dma, HNS_ROCE_CMD_QUERY_SRQC,
5490 srqn);
5491 if (ret)
5492 goto out;
5493
5494 memcpy(buffer, context, sizeof(*context));
5495
5496 out:
5497 hns_roce_free_cmd_mailbox(hr_dev, mailbox);
5498 return ret;
5499 }
5500
hns_roce_v2_query_sccc(struct hns_roce_dev * hr_dev,u32 sccn,void * buffer)5501 static int hns_roce_v2_query_sccc(struct hns_roce_dev *hr_dev, u32 sccn,
5502 void *buffer)
5503 {
5504 struct hns_roce_v2_scc_context *context;
5505 struct hns_roce_cmd_mailbox *mailbox;
5506 int ret;
5507
5508 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev);
5509 if (IS_ERR(mailbox))
5510 return PTR_ERR(mailbox);
5511
5512 ret = hns_roce_cmd_mbox(hr_dev, 0, mailbox->dma, HNS_ROCE_CMD_QUERY_SCCC,
5513 sccn);
5514 if (ret)
5515 goto out;
5516
5517 context = mailbox->buf;
5518 memcpy(buffer, context, sizeof(*context));
5519
5520 out:
5521 hns_roce_free_cmd_mailbox(hr_dev, mailbox);
5522 return ret;
5523 }
5524
get_qp_timeout_attr(struct hns_roce_dev * hr_dev,struct hns_roce_v2_qp_context * context)5525 static u8 get_qp_timeout_attr(struct hns_roce_dev *hr_dev,
5526 struct hns_roce_v2_qp_context *context)
5527 {
5528 u8 timeout;
5529
5530 timeout = (u8)hr_reg_read(context, QPC_AT);
5531 if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08)
5532 timeout -= HNS_ROCE_V2_QP_ACK_TIMEOUT_OFS_HIP08;
5533
5534 return timeout;
5535 }
5536
hns_roce_v2_query_qp(struct ib_qp * ibqp,struct ib_qp_attr * qp_attr,int qp_attr_mask,struct ib_qp_init_attr * qp_init_attr)5537 static int hns_roce_v2_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr,
5538 int qp_attr_mask,
5539 struct ib_qp_init_attr *qp_init_attr)
5540 {
5541 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
5542 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
5543 struct hns_roce_v2_qp_context context = {};
5544 struct ib_device *ibdev = &hr_dev->ib_dev;
5545 int tmp_qp_state;
5546 int state;
5547 int ret;
5548
5549 memset(qp_attr, 0, sizeof(*qp_attr));
5550 memset(qp_init_attr, 0, sizeof(*qp_init_attr));
5551
5552 mutex_lock(&hr_qp->mutex);
5553
5554 if (hr_qp->state == IB_QPS_RESET) {
5555 qp_attr->qp_state = IB_QPS_RESET;
5556 ret = 0;
5557 goto done;
5558 }
5559
5560 ret = hns_roce_v2_query_qpc(hr_dev, hr_qp->qpn, &context);
5561 if (ret) {
5562 ibdev_err_ratelimited(ibdev,
5563 "failed to query QPC, ret = %d.\n",
5564 ret);
5565 ret = -EINVAL;
5566 goto out;
5567 }
5568
5569 state = hr_reg_read(&context, QPC_QP_ST);
5570 tmp_qp_state = to_ib_qp_st((enum hns_roce_v2_qp_state)state);
5571 if (tmp_qp_state == -1) {
5572 ibdev_err_ratelimited(ibdev, "Illegal ib_qp_state\n");
5573 ret = -EINVAL;
5574 goto out;
5575 }
5576 hr_qp->state = (u8)tmp_qp_state;
5577 qp_attr->qp_state = (enum ib_qp_state)hr_qp->state;
5578 qp_attr->path_mtu = (enum ib_mtu)hr_reg_read(&context, QPC_MTU);
5579 qp_attr->path_mig_state = IB_MIG_ARMED;
5580 qp_attr->ah_attr.type = RDMA_AH_ATTR_TYPE_ROCE;
5581 if (hr_qp->ibqp.qp_type == IB_QPT_UD)
5582 qp_attr->qkey = le32_to_cpu(context.qkey_xrcd);
5583
5584 qp_attr->rq_psn = hr_reg_read(&context, QPC_RX_REQ_EPSN);
5585 qp_attr->sq_psn = (u32)hr_reg_read(&context, QPC_SQ_CUR_PSN);
5586 qp_attr->dest_qp_num = hr_reg_read(&context, QPC_DQPN);
5587 qp_attr->qp_access_flags =
5588 ((hr_reg_read(&context, QPC_RRE)) << V2_QP_RRE_S) |
5589 ((hr_reg_read(&context, QPC_RWE)) << V2_QP_RWE_S) |
5590 ((hr_reg_read(&context, QPC_ATE)) << V2_QP_ATE_S);
5591
5592 if (hr_qp->ibqp.qp_type == IB_QPT_RC ||
5593 hr_qp->ibqp.qp_type == IB_QPT_XRC_INI ||
5594 hr_qp->ibqp.qp_type == IB_QPT_XRC_TGT) {
5595 struct ib_global_route *grh =
5596 rdma_ah_retrieve_grh(&qp_attr->ah_attr);
5597
5598 rdma_ah_set_sl(&qp_attr->ah_attr,
5599 hr_reg_read(&context, QPC_SL));
5600 rdma_ah_set_port_num(&qp_attr->ah_attr, hr_qp->port + 1);
5601 rdma_ah_set_ah_flags(&qp_attr->ah_attr, IB_AH_GRH);
5602 grh->flow_label = hr_reg_read(&context, QPC_FL);
5603 grh->sgid_index = hr_reg_read(&context, QPC_GMV_IDX);
5604 grh->hop_limit = hr_reg_read(&context, QPC_HOPLIMIT);
5605 grh->traffic_class = hr_reg_read(&context, QPC_TC);
5606
5607 memcpy(grh->dgid.raw, context.dgid, sizeof(grh->dgid.raw));
5608 }
5609
5610 qp_attr->port_num = hr_qp->port + 1;
5611 qp_attr->sq_draining = 0;
5612 qp_attr->max_rd_atomic = 1 << hr_reg_read(&context, QPC_SR_MAX);
5613 qp_attr->max_dest_rd_atomic = 1 << hr_reg_read(&context, QPC_RR_MAX);
5614
5615 qp_attr->min_rnr_timer = (u8)hr_reg_read(&context, QPC_MIN_RNR_TIME);
5616 qp_attr->timeout = get_qp_timeout_attr(hr_dev, &context);
5617 qp_attr->retry_cnt = hr_reg_read(&context, QPC_RETRY_NUM_INIT);
5618 qp_attr->rnr_retry = hr_reg_read(&context, QPC_RNR_NUM_INIT);
5619
5620 done:
5621 qp_attr->cur_qp_state = qp_attr->qp_state;
5622 qp_attr->cap.max_recv_wr = hr_qp->rq.wqe_cnt;
5623 qp_attr->cap.max_recv_sge = hr_qp->rq.max_gs - hr_qp->rq.rsv_sge;
5624 qp_attr->cap.max_inline_data = hr_qp->max_inline_data;
5625
5626 qp_attr->cap.max_send_wr = hr_qp->sq.wqe_cnt;
5627 qp_attr->cap.max_send_sge = hr_qp->sq.max_gs;
5628
5629 qp_init_attr->qp_context = ibqp->qp_context;
5630 qp_init_attr->qp_type = ibqp->qp_type;
5631 qp_init_attr->recv_cq = ibqp->recv_cq;
5632 qp_init_attr->send_cq = ibqp->send_cq;
5633 qp_init_attr->srq = ibqp->srq;
5634 qp_init_attr->cap = qp_attr->cap;
5635 qp_init_attr->sq_sig_type = hr_qp->sq_signal_bits;
5636
5637 out:
5638 mutex_unlock(&hr_qp->mutex);
5639 return ret;
5640 }
5641
modify_qp_is_ok(struct hns_roce_qp * hr_qp)5642 static inline int modify_qp_is_ok(struct hns_roce_qp *hr_qp)
5643 {
5644 return ((hr_qp->ibqp.qp_type == IB_QPT_RC ||
5645 hr_qp->ibqp.qp_type == IB_QPT_UD ||
5646 hr_qp->ibqp.qp_type == IB_QPT_XRC_INI ||
5647 hr_qp->ibqp.qp_type == IB_QPT_XRC_TGT) &&
5648 hr_qp->state != IB_QPS_RESET);
5649 }
5650
hns_roce_v2_destroy_qp_common(struct hns_roce_dev * hr_dev,struct hns_roce_qp * hr_qp,struct ib_udata * udata)5651 static int hns_roce_v2_destroy_qp_common(struct hns_roce_dev *hr_dev,
5652 struct hns_roce_qp *hr_qp,
5653 struct ib_udata *udata)
5654 {
5655 struct ib_device *ibdev = &hr_dev->ib_dev;
5656 struct hns_roce_cq *send_cq, *recv_cq;
5657 unsigned long flags;
5658 int ret = 0;
5659
5660 if (modify_qp_is_ok(hr_qp)) {
5661 /* Modify qp to reset before destroying qp */
5662 ret = hns_roce_v2_modify_qp(&hr_qp->ibqp, NULL, 0,
5663 hr_qp->state, IB_QPS_RESET, udata);
5664 if (ret)
5665 ibdev_err_ratelimited(ibdev,
5666 "failed to modify QP to RST, ret = %d.\n",
5667 ret);
5668 }
5669
5670 send_cq = hr_qp->ibqp.send_cq ? to_hr_cq(hr_qp->ibqp.send_cq) : NULL;
5671 recv_cq = hr_qp->ibqp.recv_cq ? to_hr_cq(hr_qp->ibqp.recv_cq) : NULL;
5672
5673 spin_lock_irqsave(&hr_dev->qp_list_lock, flags);
5674 hns_roce_lock_cqs(send_cq, recv_cq);
5675
5676 if (!udata) {
5677 if (recv_cq)
5678 __hns_roce_v2_cq_clean(recv_cq, hr_qp->qpn,
5679 (hr_qp->ibqp.srq ?
5680 to_hr_srq(hr_qp->ibqp.srq) :
5681 NULL));
5682
5683 if (send_cq && send_cq != recv_cq)
5684 __hns_roce_v2_cq_clean(send_cq, hr_qp->qpn, NULL);
5685 }
5686
5687 hns_roce_qp_remove(hr_dev, hr_qp);
5688
5689 hns_roce_unlock_cqs(send_cq, recv_cq);
5690 spin_unlock_irqrestore(&hr_dev->qp_list_lock, flags);
5691
5692 return ret;
5693 }
5694
put_dip_ctx_idx(struct hns_roce_dev * hr_dev,struct hns_roce_qp * hr_qp)5695 static void put_dip_ctx_idx(struct hns_roce_dev *hr_dev,
5696 struct hns_roce_qp *hr_qp)
5697 {
5698 struct hns_roce_dip *hr_dip = hr_qp->dip;
5699
5700 if (!hr_dip)
5701 return;
5702
5703 xa_lock(&hr_dev->qp_table.dip_xa);
5704
5705 hr_dip->qp_cnt--;
5706 if (!hr_dip->qp_cnt)
5707 memset(hr_dip->dgid, 0, GID_LEN_V2);
5708
5709 xa_unlock(&hr_dev->qp_table.dip_xa);
5710 }
5711
hns_roce_v2_destroy_qp(struct ib_qp * ibqp,struct ib_udata * udata)5712 int hns_roce_v2_destroy_qp(struct ib_qp *ibqp, struct ib_udata *udata)
5713 {
5714 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
5715 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
5716 unsigned long flags;
5717 int ret;
5718
5719 /* Make sure flush_cqe() is completed */
5720 spin_lock_irqsave(&hr_qp->flush_lock, flags);
5721 set_bit(HNS_ROCE_STOP_FLUSH_FLAG, &hr_qp->flush_flag);
5722 spin_unlock_irqrestore(&hr_qp->flush_lock, flags);
5723 flush_work(&hr_qp->flush_work.work);
5724
5725 if (hr_qp->cong_type == CONG_TYPE_DIP)
5726 put_dip_ctx_idx(hr_dev, hr_qp);
5727
5728 ret = hns_roce_v2_destroy_qp_common(hr_dev, hr_qp, udata);
5729 if (ret)
5730 ibdev_err_ratelimited(&hr_dev->ib_dev,
5731 "failed to destroy QP, QPN = 0x%06lx, ret = %d.\n",
5732 hr_qp->qpn, ret);
5733
5734 hns_roce_qp_destroy(hr_dev, hr_qp, udata);
5735
5736 return 0;
5737 }
5738
hns_roce_v2_qp_flow_control_init(struct hns_roce_dev * hr_dev,struct hns_roce_qp * hr_qp)5739 static int hns_roce_v2_qp_flow_control_init(struct hns_roce_dev *hr_dev,
5740 struct hns_roce_qp *hr_qp)
5741 {
5742 struct ib_device *ibdev = &hr_dev->ib_dev;
5743 struct hns_roce_sccc_clr_done *resp;
5744 struct hns_roce_sccc_clr *clr;
5745 struct hns_roce_cmq_desc desc;
5746 int ret, i;
5747
5748 if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09)
5749 return 0;
5750
5751 mutex_lock(&hr_dev->qp_table.scc_mutex);
5752
5753 /* set scc ctx clear done flag */
5754 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_RESET_SCCC, false);
5755 ret = hns_roce_cmq_send(hr_dev, &desc, 1);
5756 if (ret) {
5757 ibdev_err(ibdev, "failed to reset SCC ctx, ret = %d.\n", ret);
5758 goto out;
5759 }
5760
5761 /* clear scc context */
5762 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CLR_SCCC, false);
5763 clr = (struct hns_roce_sccc_clr *)desc.data;
5764 clr->qpn = cpu_to_le32(hr_qp->qpn);
5765 ret = hns_roce_cmq_send(hr_dev, &desc, 1);
5766 if (ret) {
5767 ibdev_err(ibdev, "failed to clear SCC ctx, ret = %d.\n", ret);
5768 goto out;
5769 }
5770
5771 /* query scc context clear is done or not */
5772 resp = (struct hns_roce_sccc_clr_done *)desc.data;
5773 for (i = 0; i <= HNS_ROCE_CMQ_SCC_CLR_DONE_CNT; i++) {
5774 hns_roce_cmq_setup_basic_desc(&desc,
5775 HNS_ROCE_OPC_QUERY_SCCC, true);
5776 ret = hns_roce_cmq_send(hr_dev, &desc, 1);
5777 if (ret) {
5778 ibdev_err(ibdev, "failed to query clr cmq, ret = %d\n",
5779 ret);
5780 goto out;
5781 }
5782
5783 if (resp->clr_done)
5784 goto out;
5785
5786 msleep(20);
5787 }
5788
5789 ibdev_err(ibdev, "query SCC clr done flag overtime.\n");
5790 ret = -ETIMEDOUT;
5791
5792 out:
5793 mutex_unlock(&hr_dev->qp_table.scc_mutex);
5794 return ret;
5795 }
5796
5797 #define DMA_IDX_SHIFT 3
5798 #define DMA_WQE_SHIFT 3
5799
hns_roce_v2_write_srqc_index_queue(struct hns_roce_srq * srq,struct hns_roce_srq_context * ctx)5800 static int hns_roce_v2_write_srqc_index_queue(struct hns_roce_srq *srq,
5801 struct hns_roce_srq_context *ctx)
5802 {
5803 struct hns_roce_idx_que *idx_que = &srq->idx_que;
5804 struct ib_device *ibdev = srq->ibsrq.device;
5805 struct hns_roce_dev *hr_dev = to_hr_dev(ibdev);
5806 u64 mtts_idx[MTT_MIN_COUNT] = {};
5807 dma_addr_t dma_handle_idx;
5808 int ret;
5809
5810 /* Get physical address of idx que buf */
5811 ret = hns_roce_mtr_find(hr_dev, &idx_que->mtr, 0, mtts_idx,
5812 ARRAY_SIZE(mtts_idx));
5813 if (ret) {
5814 ibdev_err(ibdev, "failed to find mtr for SRQ idx, ret = %d.\n",
5815 ret);
5816 return ret;
5817 }
5818
5819 dma_handle_idx = hns_roce_get_mtr_ba(&idx_que->mtr);
5820
5821 hr_reg_write(ctx, SRQC_IDX_HOP_NUM,
5822 to_hr_hem_hopnum(hr_dev->caps.idx_hop_num, srq->wqe_cnt));
5823
5824 hr_reg_write(ctx, SRQC_IDX_BT_BA_L, dma_handle_idx >> DMA_IDX_SHIFT);
5825 hr_reg_write(ctx, SRQC_IDX_BT_BA_H,
5826 upper_32_bits(dma_handle_idx >> DMA_IDX_SHIFT));
5827
5828 hr_reg_write(ctx, SRQC_IDX_BA_PG_SZ,
5829 to_hr_hw_page_shift(idx_que->mtr.hem_cfg.ba_pg_shift));
5830 hr_reg_write(ctx, SRQC_IDX_BUF_PG_SZ,
5831 to_hr_hw_page_shift(idx_que->mtr.hem_cfg.buf_pg_shift));
5832
5833 hr_reg_write(ctx, SRQC_IDX_CUR_BLK_ADDR_L,
5834 to_hr_hw_page_addr(mtts_idx[0]));
5835 hr_reg_write(ctx, SRQC_IDX_CUR_BLK_ADDR_H,
5836 upper_32_bits(to_hr_hw_page_addr(mtts_idx[0])));
5837
5838 hr_reg_write(ctx, SRQC_IDX_NXT_BLK_ADDR_L,
5839 to_hr_hw_page_addr(mtts_idx[1]));
5840 hr_reg_write(ctx, SRQC_IDX_NXT_BLK_ADDR_H,
5841 upper_32_bits(to_hr_hw_page_addr(mtts_idx[1])));
5842
5843 return 0;
5844 }
5845
hns_roce_v2_write_srqc(struct hns_roce_srq * srq,void * mb_buf)5846 static int hns_roce_v2_write_srqc(struct hns_roce_srq *srq, void *mb_buf)
5847 {
5848 struct ib_device *ibdev = srq->ibsrq.device;
5849 struct hns_roce_dev *hr_dev = to_hr_dev(ibdev);
5850 struct hns_roce_srq_context *ctx = mb_buf;
5851 u64 mtts_wqe[MTT_MIN_COUNT] = {};
5852 dma_addr_t dma_handle_wqe;
5853 int ret;
5854
5855 memset(ctx, 0, sizeof(*ctx));
5856
5857 /* Get the physical address of srq buf */
5858 ret = hns_roce_mtr_find(hr_dev, &srq->buf_mtr, 0, mtts_wqe,
5859 ARRAY_SIZE(mtts_wqe));
5860 if (ret) {
5861 ibdev_err(ibdev, "failed to find mtr for SRQ WQE, ret = %d.\n",
5862 ret);
5863 return ret;
5864 }
5865
5866 dma_handle_wqe = hns_roce_get_mtr_ba(&srq->buf_mtr);
5867
5868 hr_reg_write(ctx, SRQC_SRQ_ST, 1);
5869 hr_reg_write_bool(ctx, SRQC_SRQ_TYPE,
5870 srq->ibsrq.srq_type == IB_SRQT_XRC);
5871 hr_reg_write(ctx, SRQC_PD, to_hr_pd(srq->ibsrq.pd)->pdn);
5872 hr_reg_write(ctx, SRQC_SRQN, srq->srqn);
5873 hr_reg_write(ctx, SRQC_XRCD, srq->xrcdn);
5874 hr_reg_write(ctx, SRQC_XRC_CQN, srq->cqn);
5875 hr_reg_write(ctx, SRQC_SHIFT, ilog2(srq->wqe_cnt));
5876 hr_reg_write(ctx, SRQC_RQWS,
5877 srq->max_gs <= 0 ? 0 : fls(srq->max_gs - 1));
5878
5879 hr_reg_write(ctx, SRQC_WQE_HOP_NUM,
5880 to_hr_hem_hopnum(hr_dev->caps.srqwqe_hop_num,
5881 srq->wqe_cnt));
5882
5883 hr_reg_write(ctx, SRQC_WQE_BT_BA_L, dma_handle_wqe >> DMA_WQE_SHIFT);
5884 hr_reg_write(ctx, SRQC_WQE_BT_BA_H,
5885 upper_32_bits(dma_handle_wqe >> DMA_WQE_SHIFT));
5886
5887 hr_reg_write(ctx, SRQC_WQE_BA_PG_SZ,
5888 to_hr_hw_page_shift(srq->buf_mtr.hem_cfg.ba_pg_shift));
5889 hr_reg_write(ctx, SRQC_WQE_BUF_PG_SZ,
5890 to_hr_hw_page_shift(srq->buf_mtr.hem_cfg.buf_pg_shift));
5891
5892 if (srq->cap_flags & HNS_ROCE_SRQ_CAP_RECORD_DB) {
5893 hr_reg_enable(ctx, SRQC_DB_RECORD_EN);
5894 hr_reg_write(ctx, SRQC_DB_RECORD_ADDR_L,
5895 lower_32_bits(srq->rdb.dma) >> 1);
5896 hr_reg_write(ctx, SRQC_DB_RECORD_ADDR_H,
5897 upper_32_bits(srq->rdb.dma));
5898 }
5899
5900 return hns_roce_v2_write_srqc_index_queue(srq, ctx);
5901 }
5902
hns_roce_v2_modify_srq(struct ib_srq * ibsrq,struct ib_srq_attr * srq_attr,enum ib_srq_attr_mask srq_attr_mask,struct ib_udata * udata)5903 static int hns_roce_v2_modify_srq(struct ib_srq *ibsrq,
5904 struct ib_srq_attr *srq_attr,
5905 enum ib_srq_attr_mask srq_attr_mask,
5906 struct ib_udata *udata)
5907 {
5908 struct hns_roce_dev *hr_dev = to_hr_dev(ibsrq->device);
5909 struct hns_roce_srq *srq = to_hr_srq(ibsrq);
5910 struct hns_roce_srq_context *srq_context;
5911 struct hns_roce_srq_context *srqc_mask;
5912 struct hns_roce_cmd_mailbox *mailbox;
5913 int ret = 0;
5914
5915 /* Resizing SRQs is not supported yet */
5916 if (srq_attr_mask & IB_SRQ_MAX_WR) {
5917 ret = -EOPNOTSUPP;
5918 goto out;
5919 }
5920
5921 if (srq_attr_mask & IB_SRQ_LIMIT) {
5922 if (srq_attr->srq_limit > srq->wqe_cnt) {
5923 ret = -EINVAL;
5924 goto out;
5925 }
5926
5927 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev);
5928 if (IS_ERR(mailbox)) {
5929 ret = PTR_ERR(mailbox);
5930 goto out;
5931 }
5932
5933 srq_context = mailbox->buf;
5934 srqc_mask = (struct hns_roce_srq_context *)mailbox->buf + 1;
5935
5936 memset(srqc_mask, 0xff, sizeof(*srqc_mask));
5937
5938 hr_reg_write(srq_context, SRQC_LIMIT_WL, srq_attr->srq_limit);
5939 hr_reg_clear(srqc_mask, SRQC_LIMIT_WL);
5940
5941 ret = hns_roce_cmd_mbox(hr_dev, mailbox->dma, 0,
5942 HNS_ROCE_CMD_MODIFY_SRQC, srq->srqn);
5943 hns_roce_free_cmd_mailbox(hr_dev, mailbox);
5944 if (ret)
5945 ibdev_err(&hr_dev->ib_dev,
5946 "failed to handle cmd of modifying SRQ, ret = %d.\n",
5947 ret);
5948 }
5949
5950 out:
5951 if (ret)
5952 atomic64_inc(&hr_dev->dfx_cnt[HNS_ROCE_DFX_SRQ_MODIFY_ERR_CNT]);
5953
5954 return ret;
5955 }
5956
hns_roce_v2_query_srq(struct ib_srq * ibsrq,struct ib_srq_attr * attr)5957 static int hns_roce_v2_query_srq(struct ib_srq *ibsrq, struct ib_srq_attr *attr)
5958 {
5959 struct hns_roce_dev *hr_dev = to_hr_dev(ibsrq->device);
5960 struct hns_roce_srq *srq = to_hr_srq(ibsrq);
5961 struct hns_roce_srq_context *srq_context;
5962 struct hns_roce_cmd_mailbox *mailbox;
5963 int ret;
5964
5965 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev);
5966 if (IS_ERR(mailbox))
5967 return PTR_ERR(mailbox);
5968
5969 srq_context = mailbox->buf;
5970 ret = hns_roce_cmd_mbox(hr_dev, 0, mailbox->dma,
5971 HNS_ROCE_CMD_QUERY_SRQC, srq->srqn);
5972 if (ret) {
5973 ibdev_err(&hr_dev->ib_dev,
5974 "failed to process cmd of querying SRQ, ret = %d.\n",
5975 ret);
5976 goto out;
5977 }
5978
5979 attr->srq_limit = hr_reg_read(srq_context, SRQC_LIMIT_WL);
5980 attr->max_wr = srq->wqe_cnt;
5981 attr->max_sge = srq->max_gs - srq->rsv_sge;
5982
5983 out:
5984 hns_roce_free_cmd_mailbox(hr_dev, mailbox);
5985 return ret;
5986 }
5987
hns_roce_v2_modify_cq(struct ib_cq * cq,u16 cq_count,u16 cq_period)5988 static int hns_roce_v2_modify_cq(struct ib_cq *cq, u16 cq_count, u16 cq_period)
5989 {
5990 struct hns_roce_dev *hr_dev = to_hr_dev(cq->device);
5991 struct hns_roce_v2_cq_context *cq_context;
5992 struct hns_roce_cq *hr_cq = to_hr_cq(cq);
5993 struct hns_roce_v2_cq_context *cqc_mask;
5994 struct hns_roce_cmd_mailbox *mailbox;
5995 int ret;
5996
5997 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev);
5998 ret = PTR_ERR_OR_ZERO(mailbox);
5999 if (ret)
6000 goto err_out;
6001
6002 cq_context = mailbox->buf;
6003 cqc_mask = (struct hns_roce_v2_cq_context *)mailbox->buf + 1;
6004
6005 memset(cqc_mask, 0xff, sizeof(*cqc_mask));
6006
6007 hr_reg_write(cq_context, CQC_CQ_MAX_CNT, cq_count);
6008 hr_reg_clear(cqc_mask, CQC_CQ_MAX_CNT);
6009
6010 if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08) {
6011 if (cq_period * HNS_ROCE_CLOCK_ADJUST > USHRT_MAX) {
6012 dev_info(hr_dev->dev,
6013 "cq_period(%u) reached the upper limit, adjusted to 65.\n",
6014 cq_period);
6015 cq_period = HNS_ROCE_MAX_CQ_PERIOD_HIP08;
6016 }
6017 cq_period *= HNS_ROCE_CLOCK_ADJUST;
6018 }
6019 hr_reg_write(cq_context, CQC_CQ_PERIOD, cq_period);
6020 hr_reg_clear(cqc_mask, CQC_CQ_PERIOD);
6021
6022 ret = hns_roce_cmd_mbox(hr_dev, mailbox->dma, 0,
6023 HNS_ROCE_CMD_MODIFY_CQC, hr_cq->cqn);
6024 hns_roce_free_cmd_mailbox(hr_dev, mailbox);
6025 if (ret)
6026 ibdev_err_ratelimited(&hr_dev->ib_dev,
6027 "failed to process cmd when modifying CQ, ret = %d.\n",
6028 ret);
6029
6030 err_out:
6031 if (ret)
6032 atomic64_inc(&hr_dev->dfx_cnt[HNS_ROCE_DFX_CQ_MODIFY_ERR_CNT]);
6033
6034 return ret;
6035 }
6036
hns_roce_v2_query_cqc(struct hns_roce_dev * hr_dev,u32 cqn,void * buffer)6037 static int hns_roce_v2_query_cqc(struct hns_roce_dev *hr_dev, u32 cqn,
6038 void *buffer)
6039 {
6040 struct hns_roce_v2_cq_context *context;
6041 struct hns_roce_cmd_mailbox *mailbox;
6042 int ret;
6043
6044 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev);
6045 if (IS_ERR(mailbox))
6046 return PTR_ERR(mailbox);
6047
6048 context = mailbox->buf;
6049 ret = hns_roce_cmd_mbox(hr_dev, 0, mailbox->dma,
6050 HNS_ROCE_CMD_QUERY_CQC, cqn);
6051 if (ret) {
6052 ibdev_err_ratelimited(&hr_dev->ib_dev,
6053 "failed to process cmd when querying CQ, ret = %d.\n",
6054 ret);
6055 goto err_mailbox;
6056 }
6057
6058 memcpy(buffer, context, sizeof(*context));
6059
6060 err_mailbox:
6061 hns_roce_free_cmd_mailbox(hr_dev, mailbox);
6062
6063 return ret;
6064 }
6065
hns_roce_v2_query_mpt(struct hns_roce_dev * hr_dev,u32 key,void * buffer)6066 static int hns_roce_v2_query_mpt(struct hns_roce_dev *hr_dev, u32 key,
6067 void *buffer)
6068 {
6069 struct hns_roce_v2_mpt_entry *context;
6070 struct hns_roce_cmd_mailbox *mailbox;
6071 int ret;
6072
6073 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev);
6074 if (IS_ERR(mailbox))
6075 return PTR_ERR(mailbox);
6076
6077 context = mailbox->buf;
6078 ret = hns_roce_cmd_mbox(hr_dev, 0, mailbox->dma, HNS_ROCE_CMD_QUERY_MPT,
6079 key_to_hw_index(key));
6080 if (ret) {
6081 ibdev_err(&hr_dev->ib_dev,
6082 "failed to process cmd when querying MPT, ret = %d.\n",
6083 ret);
6084 goto err_mailbox;
6085 }
6086
6087 memcpy(buffer, context, sizeof(*context));
6088
6089 err_mailbox:
6090 hns_roce_free_cmd_mailbox(hr_dev, mailbox);
6091
6092 return ret;
6093 }
6094
dump_aeqe_log(struct hns_roce_work * irq_work)6095 static void dump_aeqe_log(struct hns_roce_work *irq_work)
6096 {
6097 struct hns_roce_dev *hr_dev = irq_work->hr_dev;
6098 struct ib_device *ibdev = &hr_dev->ib_dev;
6099
6100 switch (irq_work->event_type) {
6101 case HNS_ROCE_EVENT_TYPE_PATH_MIG:
6102 ibdev_info(ibdev, "path migrated succeeded.\n");
6103 break;
6104 case HNS_ROCE_EVENT_TYPE_PATH_MIG_FAILED:
6105 ibdev_warn(ibdev, "path migration failed.\n");
6106 break;
6107 case HNS_ROCE_EVENT_TYPE_COMM_EST:
6108 break;
6109 case HNS_ROCE_EVENT_TYPE_SQ_DRAINED:
6110 ibdev_dbg(ibdev, "send queue drained.\n");
6111 break;
6112 case HNS_ROCE_EVENT_TYPE_WQ_CATAS_ERROR:
6113 ibdev_err(ibdev, "local work queue 0x%x catast error, sub_event type is: %d\n",
6114 irq_work->queue_num, irq_work->sub_type);
6115 break;
6116 case HNS_ROCE_EVENT_TYPE_INV_REQ_LOCAL_WQ_ERROR:
6117 ibdev_err(ibdev, "invalid request local work queue 0x%x error.\n",
6118 irq_work->queue_num);
6119 break;
6120 case HNS_ROCE_EVENT_TYPE_LOCAL_WQ_ACCESS_ERROR:
6121 ibdev_err(ibdev, "local access violation work queue 0x%x error, sub_event type is: %d\n",
6122 irq_work->queue_num, irq_work->sub_type);
6123 break;
6124 case HNS_ROCE_EVENT_TYPE_SRQ_LIMIT_REACH:
6125 ibdev_dbg(ibdev, "SRQ limit reach.\n");
6126 break;
6127 case HNS_ROCE_EVENT_TYPE_SRQ_LAST_WQE_REACH:
6128 ibdev_dbg(ibdev, "SRQ last wqe reach.\n");
6129 break;
6130 case HNS_ROCE_EVENT_TYPE_SRQ_CATAS_ERROR:
6131 ibdev_err(ibdev, "SRQ catas error.\n");
6132 break;
6133 case HNS_ROCE_EVENT_TYPE_CQ_ACCESS_ERROR:
6134 ibdev_err(ibdev, "CQ 0x%x access err.\n", irq_work->queue_num);
6135 break;
6136 case HNS_ROCE_EVENT_TYPE_CQ_OVERFLOW:
6137 ibdev_warn(ibdev, "CQ 0x%x overflow\n", irq_work->queue_num);
6138 break;
6139 case HNS_ROCE_EVENT_TYPE_DB_OVERFLOW:
6140 ibdev_warn(ibdev, "DB overflow.\n");
6141 break;
6142 case HNS_ROCE_EVENT_TYPE_MB:
6143 break;
6144 case HNS_ROCE_EVENT_TYPE_FLR:
6145 ibdev_warn(ibdev, "function level reset.\n");
6146 break;
6147 case HNS_ROCE_EVENT_TYPE_XRCD_VIOLATION:
6148 ibdev_err(ibdev, "xrc domain violation error.\n");
6149 break;
6150 case HNS_ROCE_EVENT_TYPE_INVALID_XRCETH:
6151 ibdev_err(ibdev, "invalid xrceth error.\n");
6152 break;
6153 default:
6154 ibdev_info(ibdev, "Undefined event %d.\n",
6155 irq_work->event_type);
6156 break;
6157 }
6158 }
6159
hns_roce_irq_work_handle(struct work_struct * work)6160 static void hns_roce_irq_work_handle(struct work_struct *work)
6161 {
6162 struct hns_roce_work *irq_work =
6163 container_of(work, struct hns_roce_work, work);
6164 struct hns_roce_dev *hr_dev = irq_work->hr_dev;
6165 int event_type = irq_work->event_type;
6166 u32 queue_num = irq_work->queue_num;
6167
6168 switch (event_type) {
6169 case HNS_ROCE_EVENT_TYPE_PATH_MIG:
6170 case HNS_ROCE_EVENT_TYPE_PATH_MIG_FAILED:
6171 case HNS_ROCE_EVENT_TYPE_COMM_EST:
6172 case HNS_ROCE_EVENT_TYPE_SQ_DRAINED:
6173 case HNS_ROCE_EVENT_TYPE_WQ_CATAS_ERROR:
6174 case HNS_ROCE_EVENT_TYPE_SRQ_LAST_WQE_REACH:
6175 case HNS_ROCE_EVENT_TYPE_INV_REQ_LOCAL_WQ_ERROR:
6176 case HNS_ROCE_EVENT_TYPE_LOCAL_WQ_ACCESS_ERROR:
6177 case HNS_ROCE_EVENT_TYPE_XRCD_VIOLATION:
6178 case HNS_ROCE_EVENT_TYPE_INVALID_XRCETH:
6179 hns_roce_qp_event(hr_dev, queue_num, event_type);
6180 break;
6181 case HNS_ROCE_EVENT_TYPE_SRQ_LIMIT_REACH:
6182 case HNS_ROCE_EVENT_TYPE_SRQ_CATAS_ERROR:
6183 hns_roce_srq_event(hr_dev, queue_num, event_type);
6184 break;
6185 case HNS_ROCE_EVENT_TYPE_CQ_ACCESS_ERROR:
6186 case HNS_ROCE_EVENT_TYPE_CQ_OVERFLOW:
6187 hns_roce_cq_event(hr_dev, queue_num, event_type);
6188 break;
6189 default:
6190 break;
6191 }
6192
6193 dump_aeqe_log(irq_work);
6194
6195 kfree(irq_work);
6196 }
6197
hns_roce_v2_init_irq_work(struct hns_roce_dev * hr_dev,struct hns_roce_eq * eq,u32 queue_num)6198 static void hns_roce_v2_init_irq_work(struct hns_roce_dev *hr_dev,
6199 struct hns_roce_eq *eq, u32 queue_num)
6200 {
6201 struct hns_roce_work *irq_work;
6202
6203 irq_work = kzalloc(sizeof(struct hns_roce_work), GFP_ATOMIC);
6204 if (!irq_work)
6205 return;
6206
6207 INIT_WORK(&irq_work->work, hns_roce_irq_work_handle);
6208 irq_work->hr_dev = hr_dev;
6209 irq_work->event_type = eq->event_type;
6210 irq_work->sub_type = eq->sub_type;
6211 irq_work->queue_num = queue_num;
6212 queue_work(hr_dev->irq_workq, &irq_work->work);
6213 }
6214
update_eq_db(struct hns_roce_eq * eq)6215 static void update_eq_db(struct hns_roce_eq *eq)
6216 {
6217 struct hns_roce_dev *hr_dev = eq->hr_dev;
6218 struct hns_roce_v2_db eq_db = {};
6219
6220 if (eq->type_flag == HNS_ROCE_AEQ) {
6221 hr_reg_write(&eq_db, EQ_DB_CMD,
6222 eq->arm_st == HNS_ROCE_V2_EQ_ALWAYS_ARMED ?
6223 HNS_ROCE_EQ_DB_CMD_AEQ :
6224 HNS_ROCE_EQ_DB_CMD_AEQ_ARMED);
6225 } else {
6226 hr_reg_write(&eq_db, EQ_DB_TAG, eq->eqn);
6227
6228 hr_reg_write(&eq_db, EQ_DB_CMD,
6229 eq->arm_st == HNS_ROCE_V2_EQ_ALWAYS_ARMED ?
6230 HNS_ROCE_EQ_DB_CMD_CEQ :
6231 HNS_ROCE_EQ_DB_CMD_CEQ_ARMED);
6232 }
6233
6234 hr_reg_write(&eq_db, EQ_DB_CI, eq->cons_index);
6235
6236 hns_roce_write64(hr_dev, (__le32 *)&eq_db, eq->db_reg);
6237 }
6238
next_aeqe_sw_v2(struct hns_roce_eq * eq)6239 static struct hns_roce_aeqe *next_aeqe_sw_v2(struct hns_roce_eq *eq)
6240 {
6241 struct hns_roce_aeqe *aeqe;
6242
6243 aeqe = hns_roce_buf_offset(eq->mtr.kmem,
6244 (eq->cons_index & (eq->entries - 1)) *
6245 eq->eqe_size);
6246
6247 return (hr_reg_read(aeqe, AEQE_OWNER) ^
6248 !!(eq->cons_index & eq->entries)) ? aeqe : NULL;
6249 }
6250
hns_roce_v2_aeq_int(struct hns_roce_dev * hr_dev,struct hns_roce_eq * eq)6251 static irqreturn_t hns_roce_v2_aeq_int(struct hns_roce_dev *hr_dev,
6252 struct hns_roce_eq *eq)
6253 {
6254 struct hns_roce_aeqe *aeqe = next_aeqe_sw_v2(eq);
6255 irqreturn_t aeqe_found = IRQ_NONE;
6256 int num_aeqes = 0;
6257 int event_type;
6258 u32 queue_num;
6259 int sub_type;
6260
6261 while (aeqe && num_aeqes < HNS_AEQ_POLLING_BUDGET) {
6262 /* Make sure we read AEQ entry after we have checked the
6263 * ownership bit
6264 */
6265 dma_rmb();
6266
6267 event_type = hr_reg_read(aeqe, AEQE_EVENT_TYPE);
6268 sub_type = hr_reg_read(aeqe, AEQE_SUB_TYPE);
6269 queue_num = hr_reg_read(aeqe, AEQE_EVENT_QUEUE_NUM);
6270
6271 switch (event_type) {
6272 case HNS_ROCE_EVENT_TYPE_WQ_CATAS_ERROR:
6273 case HNS_ROCE_EVENT_TYPE_INV_REQ_LOCAL_WQ_ERROR:
6274 case HNS_ROCE_EVENT_TYPE_LOCAL_WQ_ACCESS_ERROR:
6275 case HNS_ROCE_EVENT_TYPE_XRCD_VIOLATION:
6276 case HNS_ROCE_EVENT_TYPE_INVALID_XRCETH:
6277 hns_roce_flush_cqe(hr_dev, queue_num);
6278 break;
6279 case HNS_ROCE_EVENT_TYPE_MB:
6280 hns_roce_cmd_event(hr_dev,
6281 le16_to_cpu(aeqe->event.cmd.token),
6282 aeqe->event.cmd.status,
6283 le64_to_cpu(aeqe->event.cmd.out_param));
6284 break;
6285 default:
6286 break;
6287 }
6288
6289 eq->event_type = event_type;
6290 eq->sub_type = sub_type;
6291 ++eq->cons_index;
6292 aeqe_found = IRQ_HANDLED;
6293
6294 atomic64_inc(&hr_dev->dfx_cnt[HNS_ROCE_DFX_AEQE_CNT]);
6295
6296 hns_roce_v2_init_irq_work(hr_dev, eq, queue_num);
6297
6298 aeqe = next_aeqe_sw_v2(eq);
6299 ++num_aeqes;
6300 }
6301
6302 update_eq_db(eq);
6303
6304 return IRQ_RETVAL(aeqe_found);
6305 }
6306
next_ceqe_sw_v2(struct hns_roce_eq * eq)6307 static struct hns_roce_ceqe *next_ceqe_sw_v2(struct hns_roce_eq *eq)
6308 {
6309 struct hns_roce_ceqe *ceqe;
6310
6311 ceqe = hns_roce_buf_offset(eq->mtr.kmem,
6312 (eq->cons_index & (eq->entries - 1)) *
6313 eq->eqe_size);
6314
6315 return (hr_reg_read(ceqe, CEQE_OWNER) ^
6316 !!(eq->cons_index & eq->entries)) ? ceqe : NULL;
6317 }
6318
hns_roce_v2_ceq_int(struct hns_roce_eq * eq)6319 static irqreturn_t hns_roce_v2_ceq_int(struct hns_roce_eq *eq)
6320 {
6321 queue_work(system_bh_wq, &eq->work);
6322
6323 return IRQ_HANDLED;
6324 }
6325
hns_roce_v2_msix_interrupt_eq(int irq,void * eq_ptr)6326 static irqreturn_t hns_roce_v2_msix_interrupt_eq(int irq, void *eq_ptr)
6327 {
6328 struct hns_roce_eq *eq = eq_ptr;
6329 struct hns_roce_dev *hr_dev = eq->hr_dev;
6330 irqreturn_t int_work;
6331
6332 if (eq->type_flag == HNS_ROCE_CEQ)
6333 /* Completion event interrupt */
6334 int_work = hns_roce_v2_ceq_int(eq);
6335 else
6336 /* Asynchronous event interrupt */
6337 int_work = hns_roce_v2_aeq_int(hr_dev, eq);
6338
6339 return IRQ_RETVAL(int_work);
6340 }
6341
abnormal_interrupt_basic(struct hns_roce_dev * hr_dev,u32 int_st)6342 static irqreturn_t abnormal_interrupt_basic(struct hns_roce_dev *hr_dev,
6343 u32 int_st)
6344 {
6345 struct pci_dev *pdev = hr_dev->pci_dev;
6346 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
6347 const struct hnae3_ae_ops *ops = ae_dev->ops;
6348 enum hnae3_reset_type reset_type;
6349 irqreturn_t int_work = IRQ_NONE;
6350 u32 int_en;
6351
6352 int_en = roce_read(hr_dev, ROCEE_VF_ABN_INT_EN_REG);
6353
6354 if (int_st & BIT(HNS_ROCE_V2_VF_INT_ST_AEQ_OVERFLOW_S)) {
6355 dev_err(hr_dev->dev, "AEQ overflow!\n");
6356
6357 roce_write(hr_dev, ROCEE_VF_ABN_INT_ST_REG,
6358 1 << HNS_ROCE_V2_VF_INT_ST_AEQ_OVERFLOW_S);
6359
6360 reset_type = hr_dev->is_vf ?
6361 HNAE3_VF_FUNC_RESET : HNAE3_FUNC_RESET;
6362
6363 /* Set reset level for reset_event() */
6364 if (ops->set_default_reset_request)
6365 ops->set_default_reset_request(ae_dev, reset_type);
6366 if (ops->reset_event)
6367 ops->reset_event(pdev, NULL);
6368
6369 int_en |= 1 << HNS_ROCE_V2_VF_ABN_INT_EN_S;
6370 roce_write(hr_dev, ROCEE_VF_ABN_INT_EN_REG, int_en);
6371
6372 int_work = IRQ_HANDLED;
6373 } else {
6374 dev_err(hr_dev->dev, "there is no basic abn irq found.\n");
6375 }
6376
6377 return IRQ_RETVAL(int_work);
6378 }
6379
fmea_ram_ecc_query(struct hns_roce_dev * hr_dev,struct fmea_ram_ecc * ecc_info)6380 static int fmea_ram_ecc_query(struct hns_roce_dev *hr_dev,
6381 struct fmea_ram_ecc *ecc_info)
6382 {
6383 struct hns_roce_cmq_desc desc;
6384 struct hns_roce_cmq_req *req = (struct hns_roce_cmq_req *)desc.data;
6385 int ret;
6386
6387 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_QUERY_RAM_ECC, true);
6388 ret = hns_roce_cmq_send(hr_dev, &desc, 1);
6389 if (ret)
6390 return ret;
6391
6392 ecc_info->is_ecc_err = hr_reg_read(req, QUERY_RAM_ECC_1BIT_ERR);
6393 ecc_info->res_type = hr_reg_read(req, QUERY_RAM_ECC_RES_TYPE);
6394 ecc_info->index = hr_reg_read(req, QUERY_RAM_ECC_TAG);
6395
6396 return 0;
6397 }
6398
fmea_recover_gmv(struct hns_roce_dev * hr_dev,u32 idx)6399 static int fmea_recover_gmv(struct hns_roce_dev *hr_dev, u32 idx)
6400 {
6401 struct hns_roce_cmq_desc desc;
6402 struct hns_roce_cmq_req *req = (struct hns_roce_cmq_req *)desc.data;
6403 u32 addr_upper;
6404 u32 addr_low;
6405 int ret;
6406
6407 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CFG_GMV_BT, true);
6408 hr_reg_write(req, CFG_GMV_BT_IDX, idx);
6409
6410 ret = hns_roce_cmq_send(hr_dev, &desc, 1);
6411 if (ret) {
6412 dev_err(hr_dev->dev,
6413 "failed to execute cmd to read gmv, ret = %d.\n", ret);
6414 return ret;
6415 }
6416
6417 addr_low = hr_reg_read(req, CFG_GMV_BT_BA_L);
6418 addr_upper = hr_reg_read(req, CFG_GMV_BT_BA_H);
6419
6420 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CFG_GMV_BT, false);
6421 hr_reg_write(req, CFG_GMV_BT_BA_L, addr_low);
6422 hr_reg_write(req, CFG_GMV_BT_BA_H, addr_upper);
6423 hr_reg_write(req, CFG_GMV_BT_IDX, idx);
6424
6425 return hns_roce_cmq_send(hr_dev, &desc, 1);
6426 }
6427
fmea_get_ram_res_addr(u32 res_type,__le64 * data)6428 static u64 fmea_get_ram_res_addr(u32 res_type, __le64 *data)
6429 {
6430 if (res_type == ECC_RESOURCE_QPC_TIMER ||
6431 res_type == ECC_RESOURCE_CQC_TIMER ||
6432 res_type == ECC_RESOURCE_SCCC)
6433 return le64_to_cpu(*data);
6434
6435 return le64_to_cpu(*data) << HNS_HW_PAGE_SHIFT;
6436 }
6437
fmea_recover_others(struct hns_roce_dev * hr_dev,u32 res_type,u32 index)6438 static int fmea_recover_others(struct hns_roce_dev *hr_dev, u32 res_type,
6439 u32 index)
6440 {
6441 u8 write_bt0_op = fmea_ram_res[res_type].write_bt0_op;
6442 u8 read_bt0_op = fmea_ram_res[res_type].read_bt0_op;
6443 struct hns_roce_cmd_mailbox *mailbox;
6444 u64 addr;
6445 int ret;
6446
6447 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev);
6448 if (IS_ERR(mailbox))
6449 return PTR_ERR(mailbox);
6450
6451 ret = hns_roce_cmd_mbox(hr_dev, 0, mailbox->dma, read_bt0_op, index);
6452 if (ret) {
6453 dev_err(hr_dev->dev,
6454 "failed to execute cmd to read fmea ram, ret = %d.\n",
6455 ret);
6456 goto out;
6457 }
6458
6459 addr = fmea_get_ram_res_addr(res_type, mailbox->buf);
6460
6461 ret = hns_roce_cmd_mbox(hr_dev, addr, 0, write_bt0_op, index);
6462 if (ret)
6463 dev_err(hr_dev->dev,
6464 "failed to execute cmd to write fmea ram, ret = %d.\n",
6465 ret);
6466
6467 out:
6468 hns_roce_free_cmd_mailbox(hr_dev, mailbox);
6469 return ret;
6470 }
6471
fmea_ram_ecc_recover(struct hns_roce_dev * hr_dev,struct fmea_ram_ecc * ecc_info)6472 static void fmea_ram_ecc_recover(struct hns_roce_dev *hr_dev,
6473 struct fmea_ram_ecc *ecc_info)
6474 {
6475 u32 res_type = ecc_info->res_type;
6476 u32 index = ecc_info->index;
6477 int ret;
6478
6479 BUILD_BUG_ON(ARRAY_SIZE(fmea_ram_res) != ECC_RESOURCE_COUNT);
6480
6481 if (res_type >= ECC_RESOURCE_COUNT) {
6482 dev_err(hr_dev->dev, "unsupported fmea ram ecc type %u.\n",
6483 res_type);
6484 return;
6485 }
6486
6487 if (res_type == ECC_RESOURCE_GMV)
6488 ret = fmea_recover_gmv(hr_dev, index);
6489 else
6490 ret = fmea_recover_others(hr_dev, res_type, index);
6491 if (ret)
6492 dev_err(hr_dev->dev,
6493 "failed to recover %s, index = %u, ret = %d.\n",
6494 fmea_ram_res[res_type].name, index, ret);
6495 }
6496
fmea_ram_ecc_work(struct work_struct * ecc_work)6497 static void fmea_ram_ecc_work(struct work_struct *ecc_work)
6498 {
6499 struct hns_roce_dev *hr_dev =
6500 container_of(ecc_work, struct hns_roce_dev, ecc_work);
6501 struct fmea_ram_ecc ecc_info = {};
6502
6503 if (fmea_ram_ecc_query(hr_dev, &ecc_info)) {
6504 dev_err(hr_dev->dev, "failed to query fmea ram ecc.\n");
6505 return;
6506 }
6507
6508 if (!ecc_info.is_ecc_err) {
6509 dev_err(hr_dev->dev, "there is no fmea ram ecc err found.\n");
6510 return;
6511 }
6512
6513 fmea_ram_ecc_recover(hr_dev, &ecc_info);
6514 }
6515
hns_roce_v2_msix_interrupt_abn(int irq,void * dev_id)6516 static irqreturn_t hns_roce_v2_msix_interrupt_abn(int irq, void *dev_id)
6517 {
6518 struct hns_roce_dev *hr_dev = dev_id;
6519 irqreturn_t int_work = IRQ_NONE;
6520 u32 int_st;
6521
6522 int_st = roce_read(hr_dev, ROCEE_VF_ABN_INT_ST_REG);
6523
6524 if (int_st) {
6525 int_work = abnormal_interrupt_basic(hr_dev, int_st);
6526 } else if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09) {
6527 queue_work(hr_dev->irq_workq, &hr_dev->ecc_work);
6528 int_work = IRQ_HANDLED;
6529 } else {
6530 dev_err(hr_dev->dev, "there is no abnormal irq found.\n");
6531 }
6532
6533 return IRQ_RETVAL(int_work);
6534 }
6535
hns_roce_v2_int_mask_enable(struct hns_roce_dev * hr_dev,int eq_num,u32 enable_flag)6536 static void hns_roce_v2_int_mask_enable(struct hns_roce_dev *hr_dev,
6537 int eq_num, u32 enable_flag)
6538 {
6539 int i;
6540
6541 for (i = 0; i < eq_num; i++)
6542 roce_write(hr_dev, ROCEE_VF_EVENT_INT_EN_REG +
6543 i * EQ_REG_OFFSET, enable_flag);
6544
6545 roce_write(hr_dev, ROCEE_VF_ABN_INT_EN_REG, enable_flag);
6546 roce_write(hr_dev, ROCEE_VF_ABN_INT_CFG_REG, enable_flag);
6547 }
6548
free_eq_buf(struct hns_roce_dev * hr_dev,struct hns_roce_eq * eq)6549 static void free_eq_buf(struct hns_roce_dev *hr_dev, struct hns_roce_eq *eq)
6550 {
6551 hns_roce_mtr_destroy(hr_dev, &eq->mtr);
6552 }
6553
hns_roce_v2_destroy_eqc(struct hns_roce_dev * hr_dev,struct hns_roce_eq * eq)6554 static void hns_roce_v2_destroy_eqc(struct hns_roce_dev *hr_dev,
6555 struct hns_roce_eq *eq)
6556 {
6557 struct device *dev = hr_dev->dev;
6558 int eqn = eq->eqn;
6559 int ret;
6560 u8 cmd;
6561
6562 if (eqn < hr_dev->caps.num_comp_vectors)
6563 cmd = HNS_ROCE_CMD_DESTROY_CEQC;
6564 else
6565 cmd = HNS_ROCE_CMD_DESTROY_AEQC;
6566
6567 ret = hns_roce_destroy_hw_ctx(hr_dev, cmd, eqn & HNS_ROCE_V2_EQN_M);
6568 if (ret)
6569 dev_err(dev, "[mailbox cmd] destroy eqc(%d) failed.\n", eqn);
6570
6571 free_eq_buf(hr_dev, eq);
6572 }
6573
init_eq_config(struct hns_roce_dev * hr_dev,struct hns_roce_eq * eq)6574 static void init_eq_config(struct hns_roce_dev *hr_dev, struct hns_roce_eq *eq)
6575 {
6576 eq->db_reg = hr_dev->reg_base + ROCEE_VF_EQ_DB_CFG0_REG;
6577 eq->cons_index = 0;
6578 eq->over_ignore = HNS_ROCE_V2_EQ_OVER_IGNORE_0;
6579 eq->coalesce = HNS_ROCE_V2_EQ_COALESCE_0;
6580 eq->arm_st = HNS_ROCE_V2_EQ_ALWAYS_ARMED;
6581 eq->shift = ilog2((unsigned int)eq->entries);
6582 }
6583
config_eqc(struct hns_roce_dev * hr_dev,struct hns_roce_eq * eq,void * mb_buf)6584 static int config_eqc(struct hns_roce_dev *hr_dev, struct hns_roce_eq *eq,
6585 void *mb_buf)
6586 {
6587 u64 eqe_ba[MTT_MIN_COUNT] = { 0 };
6588 struct hns_roce_eq_context *eqc;
6589 u64 bt_ba = 0;
6590 int ret;
6591
6592 eqc = mb_buf;
6593 memset(eqc, 0, sizeof(struct hns_roce_eq_context));
6594
6595 init_eq_config(hr_dev, eq);
6596
6597 /* if not multi-hop, eqe buffer only use one trunk */
6598 ret = hns_roce_mtr_find(hr_dev, &eq->mtr, 0, eqe_ba,
6599 ARRAY_SIZE(eqe_ba));
6600 if (ret) {
6601 dev_err(hr_dev->dev, "failed to find EQE mtr, ret = %d\n", ret);
6602 return ret;
6603 }
6604
6605 bt_ba = hns_roce_get_mtr_ba(&eq->mtr);
6606
6607 hr_reg_write(eqc, EQC_EQ_ST, HNS_ROCE_V2_EQ_STATE_VALID);
6608 hr_reg_write(eqc, EQC_EQE_HOP_NUM, eq->hop_num);
6609 hr_reg_write(eqc, EQC_OVER_IGNORE, eq->over_ignore);
6610 hr_reg_write(eqc, EQC_COALESCE, eq->coalesce);
6611 hr_reg_write(eqc, EQC_ARM_ST, eq->arm_st);
6612 hr_reg_write(eqc, EQC_EQN, eq->eqn);
6613 hr_reg_write(eqc, EQC_EQE_CNT, HNS_ROCE_EQ_INIT_EQE_CNT);
6614 hr_reg_write(eqc, EQC_EQE_BA_PG_SZ,
6615 to_hr_hw_page_shift(eq->mtr.hem_cfg.ba_pg_shift));
6616 hr_reg_write(eqc, EQC_EQE_BUF_PG_SZ,
6617 to_hr_hw_page_shift(eq->mtr.hem_cfg.buf_pg_shift));
6618 hr_reg_write(eqc, EQC_EQ_PROD_INDX, HNS_ROCE_EQ_INIT_PROD_IDX);
6619 hr_reg_write(eqc, EQC_EQ_MAX_CNT, eq->eq_max_cnt);
6620
6621 if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08) {
6622 if (eq->eq_period * HNS_ROCE_CLOCK_ADJUST > USHRT_MAX) {
6623 dev_info(hr_dev->dev, "eq_period(%u) reached the upper limit, adjusted to 65.\n",
6624 eq->eq_period);
6625 eq->eq_period = HNS_ROCE_MAX_EQ_PERIOD;
6626 }
6627 eq->eq_period *= HNS_ROCE_CLOCK_ADJUST;
6628 }
6629
6630 hr_reg_write(eqc, EQC_EQ_PERIOD, eq->eq_period);
6631 hr_reg_write(eqc, EQC_EQE_REPORT_TIMER, HNS_ROCE_EQ_INIT_REPORT_TIMER);
6632 hr_reg_write(eqc, EQC_EQE_BA_L, bt_ba >> 3);
6633 hr_reg_write(eqc, EQC_EQE_BA_H, bt_ba >> 35);
6634 hr_reg_write(eqc, EQC_SHIFT, eq->shift);
6635 hr_reg_write(eqc, EQC_MSI_INDX, HNS_ROCE_EQ_INIT_MSI_IDX);
6636 hr_reg_write(eqc, EQC_CUR_EQE_BA_L, eqe_ba[0] >> 12);
6637 hr_reg_write(eqc, EQC_CUR_EQE_BA_M, eqe_ba[0] >> 28);
6638 hr_reg_write(eqc, EQC_CUR_EQE_BA_H, eqe_ba[0] >> 60);
6639 hr_reg_write(eqc, EQC_EQ_CONS_INDX, HNS_ROCE_EQ_INIT_CONS_IDX);
6640 hr_reg_write(eqc, EQC_NEX_EQE_BA_L, eqe_ba[1] >> 12);
6641 hr_reg_write(eqc, EQC_NEX_EQE_BA_H, eqe_ba[1] >> 44);
6642 hr_reg_write(eqc, EQC_EQE_SIZE, eq->eqe_size == HNS_ROCE_V3_EQE_SIZE);
6643
6644 return 0;
6645 }
6646
alloc_eq_buf(struct hns_roce_dev * hr_dev,struct hns_roce_eq * eq)6647 static int alloc_eq_buf(struct hns_roce_dev *hr_dev, struct hns_roce_eq *eq)
6648 {
6649 struct hns_roce_buf_attr buf_attr = {};
6650 int err;
6651
6652 if (hr_dev->caps.eqe_hop_num == HNS_ROCE_HOP_NUM_0)
6653 eq->hop_num = 0;
6654 else
6655 eq->hop_num = hr_dev->caps.eqe_hop_num;
6656
6657 buf_attr.page_shift = hr_dev->caps.eqe_buf_pg_sz + PAGE_SHIFT;
6658 buf_attr.region[0].size = eq->entries * eq->eqe_size;
6659 buf_attr.region[0].hopnum = eq->hop_num;
6660 buf_attr.region_count = 1;
6661
6662 err = hns_roce_mtr_create(hr_dev, &eq->mtr, &buf_attr,
6663 hr_dev->caps.eqe_ba_pg_sz + PAGE_SHIFT, NULL,
6664 0);
6665 if (err)
6666 dev_err(hr_dev->dev, "failed to alloc EQE mtr, err %d\n", err);
6667
6668 return err;
6669 }
6670
hns_roce_v2_create_eq(struct hns_roce_dev * hr_dev,struct hns_roce_eq * eq,u8 eq_cmd)6671 static int hns_roce_v2_create_eq(struct hns_roce_dev *hr_dev,
6672 struct hns_roce_eq *eq, u8 eq_cmd)
6673 {
6674 struct hns_roce_cmd_mailbox *mailbox;
6675 int ret;
6676
6677 /* Allocate mailbox memory */
6678 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev);
6679 if (IS_ERR(mailbox))
6680 return PTR_ERR(mailbox);
6681
6682 ret = alloc_eq_buf(hr_dev, eq);
6683 if (ret)
6684 goto free_cmd_mbox;
6685
6686 ret = config_eqc(hr_dev, eq, mailbox->buf);
6687 if (ret)
6688 goto err_cmd_mbox;
6689
6690 ret = hns_roce_create_hw_ctx(hr_dev, mailbox, eq_cmd, eq->eqn);
6691 if (ret) {
6692 dev_err(hr_dev->dev, "[mailbox cmd] create eqc failed.\n");
6693 goto err_cmd_mbox;
6694 }
6695
6696 hns_roce_free_cmd_mailbox(hr_dev, mailbox);
6697
6698 return 0;
6699
6700 err_cmd_mbox:
6701 free_eq_buf(hr_dev, eq);
6702
6703 free_cmd_mbox:
6704 hns_roce_free_cmd_mailbox(hr_dev, mailbox);
6705
6706 return ret;
6707 }
6708
hns_roce_ceq_work(struct work_struct * work)6709 static void hns_roce_ceq_work(struct work_struct *work)
6710 {
6711 struct hns_roce_eq *eq = from_work(eq, work, work);
6712 struct hns_roce_ceqe *ceqe = next_ceqe_sw_v2(eq);
6713 struct hns_roce_dev *hr_dev = eq->hr_dev;
6714 int ceqe_num = 0;
6715 u32 cqn;
6716
6717 while (ceqe && ceqe_num < hr_dev->caps.ceqe_depth) {
6718 /* Make sure we read CEQ entry after we have checked the
6719 * ownership bit
6720 */
6721 dma_rmb();
6722
6723 cqn = hr_reg_read(ceqe, CEQE_CQN);
6724
6725 hns_roce_cq_completion(hr_dev, cqn);
6726
6727 ++eq->cons_index;
6728 ++ceqe_num;
6729 atomic64_inc(&hr_dev->dfx_cnt[HNS_ROCE_DFX_CEQE_CNT]);
6730
6731 ceqe = next_ceqe_sw_v2(eq);
6732 }
6733
6734 update_eq_db(eq);
6735 }
6736
__hns_roce_request_irq(struct hns_roce_dev * hr_dev,int irq_num,int comp_num,int aeq_num,int other_num)6737 static int __hns_roce_request_irq(struct hns_roce_dev *hr_dev, int irq_num,
6738 int comp_num, int aeq_num, int other_num)
6739 {
6740 struct hns_roce_eq_table *eq_table = &hr_dev->eq_table;
6741 int i, j;
6742 int ret;
6743
6744 for (i = 0; i < irq_num; i++) {
6745 hr_dev->irq_names[i] = kzalloc(HNS_ROCE_INT_NAME_LEN,
6746 GFP_KERNEL);
6747 if (!hr_dev->irq_names[i]) {
6748 ret = -ENOMEM;
6749 goto err_kzalloc_failed;
6750 }
6751 }
6752
6753 /* irq contains: abnormal + AEQ + CEQ */
6754 for (j = 0; j < other_num; j++)
6755 snprintf((char *)hr_dev->irq_names[j], HNS_ROCE_INT_NAME_LEN,
6756 "hns-%s-abn-%d", pci_name(hr_dev->pci_dev), j);
6757
6758 for (j = other_num; j < (other_num + aeq_num); j++)
6759 snprintf((char *)hr_dev->irq_names[j], HNS_ROCE_INT_NAME_LEN,
6760 "hns-%s-aeq-%d", pci_name(hr_dev->pci_dev), j - other_num);
6761
6762 for (j = (other_num + aeq_num); j < irq_num; j++)
6763 snprintf((char *)hr_dev->irq_names[j], HNS_ROCE_INT_NAME_LEN,
6764 "hns-%s-ceq-%d", pci_name(hr_dev->pci_dev),
6765 j - other_num - aeq_num);
6766
6767 for (j = 0; j < irq_num; j++) {
6768 if (j < other_num) {
6769 ret = request_irq(hr_dev->irq[j],
6770 hns_roce_v2_msix_interrupt_abn,
6771 0, hr_dev->irq_names[j], hr_dev);
6772 } else if (j < (other_num + comp_num)) {
6773 INIT_WORK(&eq_table->eq[j - other_num].work,
6774 hns_roce_ceq_work);
6775 ret = request_irq(eq_table->eq[j - other_num].irq,
6776 hns_roce_v2_msix_interrupt_eq,
6777 0, hr_dev->irq_names[j + aeq_num],
6778 &eq_table->eq[j - other_num]);
6779 } else {
6780 ret = request_irq(eq_table->eq[j - other_num].irq,
6781 hns_roce_v2_msix_interrupt_eq,
6782 0, hr_dev->irq_names[j - comp_num],
6783 &eq_table->eq[j - other_num]);
6784 }
6785
6786 if (ret) {
6787 dev_err(hr_dev->dev, "request irq error!\n");
6788 goto err_request_failed;
6789 }
6790 }
6791
6792 return 0;
6793
6794 err_request_failed:
6795 for (j -= 1; j >= 0; j--) {
6796 if (j < other_num) {
6797 free_irq(hr_dev->irq[j], hr_dev);
6798 continue;
6799 }
6800 free_irq(eq_table->eq[j - other_num].irq,
6801 &eq_table->eq[j - other_num]);
6802 if (j < other_num + comp_num)
6803 cancel_work_sync(&eq_table->eq[j - other_num].work);
6804 }
6805
6806 err_kzalloc_failed:
6807 for (i -= 1; i >= 0; i--)
6808 kfree(hr_dev->irq_names[i]);
6809
6810 return ret;
6811 }
6812
__hns_roce_free_irq(struct hns_roce_dev * hr_dev)6813 static void __hns_roce_free_irq(struct hns_roce_dev *hr_dev)
6814 {
6815 int irq_num;
6816 int eq_num;
6817 int i;
6818
6819 eq_num = hr_dev->caps.num_comp_vectors + hr_dev->caps.num_aeq_vectors;
6820 irq_num = eq_num + hr_dev->caps.num_other_vectors;
6821
6822 for (i = 0; i < hr_dev->caps.num_other_vectors; i++)
6823 free_irq(hr_dev->irq[i], hr_dev);
6824
6825 for (i = 0; i < eq_num; i++) {
6826 free_irq(hr_dev->eq_table.eq[i].irq, &hr_dev->eq_table.eq[i]);
6827 if (i < hr_dev->caps.num_comp_vectors)
6828 cancel_work_sync(&hr_dev->eq_table.eq[i].work);
6829 }
6830
6831 for (i = 0; i < irq_num; i++)
6832 kfree(hr_dev->irq_names[i]);
6833 }
6834
hns_roce_v2_init_eq_table(struct hns_roce_dev * hr_dev)6835 static int hns_roce_v2_init_eq_table(struct hns_roce_dev *hr_dev)
6836 {
6837 struct hns_roce_eq_table *eq_table = &hr_dev->eq_table;
6838 struct device *dev = hr_dev->dev;
6839 struct hns_roce_eq *eq;
6840 int other_num;
6841 int comp_num;
6842 int aeq_num;
6843 int irq_num;
6844 int eq_num;
6845 u8 eq_cmd;
6846 int ret;
6847 int i;
6848
6849 if (hr_dev->caps.aeqe_depth < HNS_AEQ_POLLING_BUDGET)
6850 return -EINVAL;
6851
6852 other_num = hr_dev->caps.num_other_vectors;
6853 comp_num = hr_dev->caps.num_comp_vectors;
6854 aeq_num = hr_dev->caps.num_aeq_vectors;
6855
6856 eq_num = comp_num + aeq_num;
6857 irq_num = eq_num + other_num;
6858
6859 eq_table->eq = kcalloc(eq_num, sizeof(*eq_table->eq), GFP_KERNEL);
6860 if (!eq_table->eq)
6861 return -ENOMEM;
6862
6863 /* create eq */
6864 for (i = 0; i < eq_num; i++) {
6865 eq = &eq_table->eq[i];
6866 eq->hr_dev = hr_dev;
6867 eq->eqn = i;
6868 if (i < comp_num) {
6869 /* CEQ */
6870 eq_cmd = HNS_ROCE_CMD_CREATE_CEQC;
6871 eq->type_flag = HNS_ROCE_CEQ;
6872 eq->entries = hr_dev->caps.ceqe_depth;
6873 eq->eqe_size = hr_dev->caps.ceqe_size;
6874 eq->irq = hr_dev->irq[i + other_num + aeq_num];
6875 eq->eq_max_cnt = HNS_ROCE_CEQ_DEFAULT_BURST_NUM;
6876 eq->eq_period = HNS_ROCE_CEQ_DEFAULT_INTERVAL;
6877 } else {
6878 /* AEQ */
6879 eq_cmd = HNS_ROCE_CMD_CREATE_AEQC;
6880 eq->type_flag = HNS_ROCE_AEQ;
6881 eq->entries = hr_dev->caps.aeqe_depth;
6882 eq->eqe_size = hr_dev->caps.aeqe_size;
6883 eq->irq = hr_dev->irq[i - comp_num + other_num];
6884 eq->eq_max_cnt = HNS_ROCE_AEQ_DEFAULT_BURST_NUM;
6885 eq->eq_period = HNS_ROCE_AEQ_DEFAULT_INTERVAL;
6886 }
6887
6888 ret = hns_roce_v2_create_eq(hr_dev, eq, eq_cmd);
6889 if (ret) {
6890 dev_err(dev, "failed to create eq.\n");
6891 goto err_create_eq_fail;
6892 }
6893 }
6894
6895 INIT_WORK(&hr_dev->ecc_work, fmea_ram_ecc_work);
6896
6897 hr_dev->irq_workq = alloc_ordered_workqueue("hns_roce_irq_workq", 0);
6898 if (!hr_dev->irq_workq) {
6899 dev_err(dev, "failed to create irq workqueue.\n");
6900 ret = -ENOMEM;
6901 goto err_create_eq_fail;
6902 }
6903
6904 ret = __hns_roce_request_irq(hr_dev, irq_num, comp_num, aeq_num,
6905 other_num);
6906 if (ret) {
6907 dev_err(dev, "failed to request irq.\n");
6908 goto err_request_irq_fail;
6909 }
6910
6911 /* enable irq */
6912 hns_roce_v2_int_mask_enable(hr_dev, eq_num, EQ_ENABLE);
6913
6914 return 0;
6915
6916 err_request_irq_fail:
6917 destroy_workqueue(hr_dev->irq_workq);
6918
6919 err_create_eq_fail:
6920 for (i -= 1; i >= 0; i--)
6921 hns_roce_v2_destroy_eqc(hr_dev, &eq_table->eq[i]);
6922 kfree(eq_table->eq);
6923
6924 return ret;
6925 }
6926
hns_roce_v2_cleanup_eq_table(struct hns_roce_dev * hr_dev)6927 static void hns_roce_v2_cleanup_eq_table(struct hns_roce_dev *hr_dev)
6928 {
6929 struct hns_roce_eq_table *eq_table = &hr_dev->eq_table;
6930 int eq_num;
6931 int i;
6932
6933 eq_num = hr_dev->caps.num_comp_vectors + hr_dev->caps.num_aeq_vectors;
6934
6935 /* Disable irq */
6936 hns_roce_v2_int_mask_enable(hr_dev, eq_num, EQ_DISABLE);
6937
6938 __hns_roce_free_irq(hr_dev);
6939 destroy_workqueue(hr_dev->irq_workq);
6940
6941 for (i = 0; i < eq_num; i++)
6942 hns_roce_v2_destroy_eqc(hr_dev, &eq_table->eq[i]);
6943
6944 kfree(eq_table->eq);
6945 }
6946
6947 static const struct ib_device_ops hns_roce_v2_dev_ops = {
6948 .destroy_qp = hns_roce_v2_destroy_qp,
6949 .modify_cq = hns_roce_v2_modify_cq,
6950 .poll_cq = hns_roce_v2_poll_cq,
6951 .post_recv = hns_roce_v2_post_recv,
6952 .post_send = hns_roce_v2_post_send,
6953 .query_qp = hns_roce_v2_query_qp,
6954 .req_notify_cq = hns_roce_v2_req_notify_cq,
6955 };
6956
6957 static const struct ib_device_ops hns_roce_v2_dev_srq_ops = {
6958 .modify_srq = hns_roce_v2_modify_srq,
6959 .post_srq_recv = hns_roce_v2_post_srq_recv,
6960 .query_srq = hns_roce_v2_query_srq,
6961 };
6962
6963 static const struct hns_roce_hw hns_roce_hw_v2 = {
6964 .cmq_init = hns_roce_v2_cmq_init,
6965 .cmq_exit = hns_roce_v2_cmq_exit,
6966 .hw_profile = hns_roce_v2_profile,
6967 .hw_init = hns_roce_v2_init,
6968 .hw_exit = hns_roce_v2_exit,
6969 .post_mbox = v2_post_mbox,
6970 .poll_mbox_done = v2_poll_mbox_done,
6971 .chk_mbox_avail = v2_chk_mbox_is_avail,
6972 .set_gid = hns_roce_v2_set_gid,
6973 .set_mac = hns_roce_v2_set_mac,
6974 .write_mtpt = hns_roce_v2_write_mtpt,
6975 .rereg_write_mtpt = hns_roce_v2_rereg_write_mtpt,
6976 .frmr_write_mtpt = hns_roce_v2_frmr_write_mtpt,
6977 .mw_write_mtpt = hns_roce_v2_mw_write_mtpt,
6978 .write_cqc = hns_roce_v2_write_cqc,
6979 .set_hem = hns_roce_v2_set_hem,
6980 .clear_hem = hns_roce_v2_clear_hem,
6981 .modify_qp = hns_roce_v2_modify_qp,
6982 .dereg_mr = hns_roce_v2_dereg_mr,
6983 .qp_flow_control_init = hns_roce_v2_qp_flow_control_init,
6984 .init_eq = hns_roce_v2_init_eq_table,
6985 .cleanup_eq = hns_roce_v2_cleanup_eq_table,
6986 .write_srqc = hns_roce_v2_write_srqc,
6987 .query_cqc = hns_roce_v2_query_cqc,
6988 .query_qpc = hns_roce_v2_query_qpc,
6989 .query_mpt = hns_roce_v2_query_mpt,
6990 .query_srqc = hns_roce_v2_query_srqc,
6991 .query_sccc = hns_roce_v2_query_sccc,
6992 .query_hw_counter = hns_roce_hw_v2_query_counter,
6993 .get_dscp = hns_roce_hw_v2_get_dscp,
6994 .hns_roce_dev_ops = &hns_roce_v2_dev_ops,
6995 .hns_roce_dev_srq_ops = &hns_roce_v2_dev_srq_ops,
6996 };
6997
6998 static const struct pci_device_id hns_roce_hw_v2_pci_tbl[] = {
6999 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA), 0},
7000 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA_MACSEC), 0},
7001 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA), 0},
7002 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA_MACSEC), 0},
7003 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_RDMA_MACSEC), 0},
7004 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_200G_RDMA), 0},
7005 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_RDMA_DCB_PFC_VF),
7006 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
7007 /* required last entry */
7008 {0, }
7009 };
7010
7011 MODULE_DEVICE_TABLE(pci, hns_roce_hw_v2_pci_tbl);
7012
hns_roce_hw_v2_get_cfg(struct hns_roce_dev * hr_dev,struct hnae3_handle * handle)7013 static void hns_roce_hw_v2_get_cfg(struct hns_roce_dev *hr_dev,
7014 struct hnae3_handle *handle)
7015 {
7016 struct hns_roce_v2_priv *priv = hr_dev->priv;
7017 const struct pci_device_id *id;
7018 int i;
7019
7020 hr_dev->pci_dev = handle->pdev;
7021 id = pci_match_id(hns_roce_hw_v2_pci_tbl, hr_dev->pci_dev);
7022 hr_dev->is_vf = id->driver_data;
7023 hr_dev->dev = &handle->pdev->dev;
7024 hr_dev->hw = &hns_roce_hw_v2;
7025 hr_dev->sdb_offset = ROCEE_DB_SQ_L_0_REG;
7026 hr_dev->odb_offset = hr_dev->sdb_offset;
7027
7028 /* Get info from NIC driver. */
7029 hr_dev->reg_base = handle->rinfo.roce_io_base;
7030 hr_dev->mem_base = handle->rinfo.roce_mem_base;
7031 hr_dev->caps.num_ports = 1;
7032 hr_dev->iboe.netdevs[0] = handle->rinfo.netdev;
7033 hr_dev->iboe.phy_port[0] = 0;
7034
7035 addrconf_addr_eui48((u8 *)&hr_dev->ib_dev.node_guid,
7036 hr_dev->iboe.netdevs[0]->dev_addr);
7037
7038 for (i = 0; i < handle->rinfo.num_vectors; i++)
7039 hr_dev->irq[i] = pci_irq_vector(handle->pdev,
7040 i + handle->rinfo.base_vector);
7041
7042 /* cmd issue mode: 0 is poll, 1 is event */
7043 hr_dev->cmd_mod = 1;
7044 hr_dev->loop_idc = 0;
7045
7046 hr_dev->reset_cnt = handle->ae_algo->ops->ae_dev_reset_cnt(handle);
7047 priv->handle = handle;
7048 }
7049
__hns_roce_hw_v2_init_instance(struct hnae3_handle * handle)7050 static int __hns_roce_hw_v2_init_instance(struct hnae3_handle *handle)
7051 {
7052 struct hns_roce_dev *hr_dev;
7053 int ret;
7054
7055 hr_dev = ib_alloc_device(hns_roce_dev, ib_dev);
7056 if (!hr_dev)
7057 return -ENOMEM;
7058
7059 hr_dev->priv = kzalloc(sizeof(struct hns_roce_v2_priv), GFP_KERNEL);
7060 if (!hr_dev->priv) {
7061 ret = -ENOMEM;
7062 goto error_failed_kzalloc;
7063 }
7064
7065 hns_roce_hw_v2_get_cfg(hr_dev, handle);
7066
7067 ret = hns_roce_init(hr_dev);
7068 if (ret) {
7069 dev_err(hr_dev->dev, "RoCE Engine init failed!\n");
7070 goto error_failed_roce_init;
7071 }
7072
7073
7074 handle->priv = hr_dev;
7075
7076 return 0;
7077
7078 error_failed_roce_init:
7079 kfree(hr_dev->priv);
7080
7081 error_failed_kzalloc:
7082 ib_dealloc_device(&hr_dev->ib_dev);
7083
7084 return ret;
7085 }
7086
__hns_roce_hw_v2_uninit_instance(struct hnae3_handle * handle,bool reset)7087 static void __hns_roce_hw_v2_uninit_instance(struct hnae3_handle *handle,
7088 bool reset)
7089 {
7090 struct hns_roce_dev *hr_dev = handle->priv;
7091
7092 if (!hr_dev)
7093 return;
7094
7095 handle->priv = NULL;
7096
7097 hr_dev->state = HNS_ROCE_DEVICE_STATE_UNINIT;
7098 hns_roce_handle_device_err(hr_dev);
7099
7100 hns_roce_exit(hr_dev);
7101 kfree(hr_dev->priv);
7102 ib_dealloc_device(&hr_dev->ib_dev);
7103 }
7104
hns_roce_hw_v2_init_instance(struct hnae3_handle * handle)7105 static int hns_roce_hw_v2_init_instance(struct hnae3_handle *handle)
7106 {
7107 const struct hnae3_ae_ops *ops = handle->ae_algo->ops;
7108 const struct pci_device_id *id;
7109 struct device *dev = &handle->pdev->dev;
7110 int ret;
7111
7112 handle->rinfo.instance_state = HNS_ROCE_STATE_INIT;
7113
7114 if (ops->ae_dev_resetting(handle) || ops->get_hw_reset_stat(handle)) {
7115 handle->rinfo.instance_state = HNS_ROCE_STATE_NON_INIT;
7116 goto reset_chk_err;
7117 }
7118
7119 id = pci_match_id(hns_roce_hw_v2_pci_tbl, handle->pdev);
7120 if (!id)
7121 return 0;
7122
7123 if (id->driver_data && handle->pdev->revision == PCI_REVISION_ID_HIP08)
7124 return 0;
7125
7126 ret = __hns_roce_hw_v2_init_instance(handle);
7127 if (ret) {
7128 handle->rinfo.instance_state = HNS_ROCE_STATE_NON_INIT;
7129 dev_err(dev, "RoCE instance init failed! ret = %d\n", ret);
7130 if (ops->ae_dev_resetting(handle) ||
7131 ops->get_hw_reset_stat(handle))
7132 goto reset_chk_err;
7133 else
7134 return ret;
7135 }
7136
7137 handle->rinfo.instance_state = HNS_ROCE_STATE_INITED;
7138
7139 return 0;
7140
7141 reset_chk_err:
7142 dev_err(dev, "Device is busy in resetting state.\n"
7143 "please retry later.\n");
7144
7145 return -EBUSY;
7146 }
7147
hns_roce_hw_v2_uninit_instance(struct hnae3_handle * handle,bool reset)7148 static void hns_roce_hw_v2_uninit_instance(struct hnae3_handle *handle,
7149 bool reset)
7150 {
7151 if (handle->rinfo.instance_state != HNS_ROCE_STATE_INITED)
7152 return;
7153
7154 handle->rinfo.instance_state = HNS_ROCE_STATE_UNINIT;
7155
7156 __hns_roce_hw_v2_uninit_instance(handle, reset);
7157
7158 handle->rinfo.instance_state = HNS_ROCE_STATE_NON_INIT;
7159 }
7160
hns_roce_hw_v2_reset_notify_down(struct hnae3_handle * handle)7161 static int hns_roce_hw_v2_reset_notify_down(struct hnae3_handle *handle)
7162 {
7163 struct hns_roce_dev *hr_dev;
7164
7165 if (handle->rinfo.instance_state != HNS_ROCE_STATE_INITED) {
7166 set_bit(HNS_ROCE_RST_DIRECT_RETURN, &handle->rinfo.state);
7167 return 0;
7168 }
7169
7170 handle->rinfo.reset_state = HNS_ROCE_STATE_RST_DOWN;
7171 clear_bit(HNS_ROCE_RST_DIRECT_RETURN, &handle->rinfo.state);
7172
7173 hr_dev = handle->priv;
7174 if (!hr_dev)
7175 return 0;
7176
7177 hr_dev->active = false;
7178 hr_dev->dis_db = true;
7179
7180 rdma_user_mmap_disassociate(&hr_dev->ib_dev);
7181
7182 hr_dev->state = HNS_ROCE_DEVICE_STATE_RST_DOWN;
7183
7184 return 0;
7185 }
7186
hns_roce_hw_v2_reset_notify_init(struct hnae3_handle * handle)7187 static int hns_roce_hw_v2_reset_notify_init(struct hnae3_handle *handle)
7188 {
7189 struct device *dev = &handle->pdev->dev;
7190 int ret;
7191
7192 if (test_and_clear_bit(HNS_ROCE_RST_DIRECT_RETURN,
7193 &handle->rinfo.state)) {
7194 handle->rinfo.reset_state = HNS_ROCE_STATE_RST_INITED;
7195 return 0;
7196 }
7197
7198 handle->rinfo.reset_state = HNS_ROCE_STATE_RST_INIT;
7199
7200 dev_info(&handle->pdev->dev, "In reset process RoCE client reinit.\n");
7201 ret = __hns_roce_hw_v2_init_instance(handle);
7202 if (ret) {
7203 /* when reset notify type is HNAE3_INIT_CLIENT In reset notify
7204 * callback function, RoCE Engine reinitialize. If RoCE reinit
7205 * failed, we should inform NIC driver.
7206 */
7207 handle->priv = NULL;
7208 dev_err(dev, "In reset process RoCE reinit failed %d.\n", ret);
7209 } else {
7210 handle->rinfo.reset_state = HNS_ROCE_STATE_RST_INITED;
7211 dev_info(dev, "reset done, RoCE client reinit finished.\n");
7212 }
7213
7214 return ret;
7215 }
7216
hns_roce_hw_v2_reset_notify_uninit(struct hnae3_handle * handle)7217 static int hns_roce_hw_v2_reset_notify_uninit(struct hnae3_handle *handle)
7218 {
7219 if (test_bit(HNS_ROCE_RST_DIRECT_RETURN, &handle->rinfo.state))
7220 return 0;
7221
7222 handle->rinfo.reset_state = HNS_ROCE_STATE_RST_UNINIT;
7223 dev_info(&handle->pdev->dev, "In reset process RoCE client uninit.\n");
7224 msleep(HNS_ROCE_V2_HW_RST_UNINT_DELAY);
7225 __hns_roce_hw_v2_uninit_instance(handle, false);
7226
7227 return 0;
7228 }
7229
hns_roce_hw_v2_reset_notify(struct hnae3_handle * handle,enum hnae3_reset_notify_type type)7230 static int hns_roce_hw_v2_reset_notify(struct hnae3_handle *handle,
7231 enum hnae3_reset_notify_type type)
7232 {
7233 int ret = 0;
7234
7235 switch (type) {
7236 case HNAE3_DOWN_CLIENT:
7237 ret = hns_roce_hw_v2_reset_notify_down(handle);
7238 break;
7239 case HNAE3_INIT_CLIENT:
7240 ret = hns_roce_hw_v2_reset_notify_init(handle);
7241 break;
7242 case HNAE3_UNINIT_CLIENT:
7243 ret = hns_roce_hw_v2_reset_notify_uninit(handle);
7244 break;
7245 default:
7246 break;
7247 }
7248
7249 return ret;
7250 }
7251
7252 static const struct hnae3_client_ops hns_roce_hw_v2_ops = {
7253 .init_instance = hns_roce_hw_v2_init_instance,
7254 .uninit_instance = hns_roce_hw_v2_uninit_instance,
7255 .reset_notify = hns_roce_hw_v2_reset_notify,
7256 };
7257
7258 static struct hnae3_client hns_roce_hw_v2_client = {
7259 .name = "hns_roce_hw_v2",
7260 .type = HNAE3_CLIENT_ROCE,
7261 .ops = &hns_roce_hw_v2_ops,
7262 };
7263
hns_roce_hw_v2_init(void)7264 static int __init hns_roce_hw_v2_init(void)
7265 {
7266 hns_roce_init_debugfs();
7267 return hnae3_register_client(&hns_roce_hw_v2_client);
7268 }
7269
hns_roce_hw_v2_exit(void)7270 static void __exit hns_roce_hw_v2_exit(void)
7271 {
7272 hnae3_unregister_client(&hns_roce_hw_v2_client);
7273 hns_roce_cleanup_debugfs();
7274 }
7275
7276 module_init(hns_roce_hw_v2_init);
7277 module_exit(hns_roce_hw_v2_exit);
7278
7279 MODULE_LICENSE("Dual BSD/GPL");
7280 MODULE_AUTHOR("Wei Hu <xavier.huwei@huawei.com>");
7281 MODULE_AUTHOR("Lijun Ou <oulijun@huawei.com>");
7282 MODULE_AUTHOR("Shaobo Xu <xushaobo2@huawei.com>");
7283 MODULE_DESCRIPTION("Hisilicon Hip08 Family RoCE Driver");
7284