1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (c) 2019, The Linux Foundation. All rights reserved.
4 */
5
6 #include <linux/acpi.h>
7 #include <linux/adreno-smmu-priv.h>
8 #include <linux/delay.h>
9 #include <linux/of_device.h>
10 #include <linux/firmware/qcom/qcom_scm.h>
11 #include <linux/platform_device.h>
12 #include <linux/pm_runtime.h>
13
14 #include "arm-smmu.h"
15 #include "arm-smmu-qcom.h"
16
17 #define QCOM_DUMMY_VAL -1
18
to_qcom_smmu(struct arm_smmu_device * smmu)19 static struct qcom_smmu *to_qcom_smmu(struct arm_smmu_device *smmu)
20 {
21 return container_of(smmu, struct qcom_smmu, smmu);
22 }
23
qcom_smmu_tlb_sync(struct arm_smmu_device * smmu,int page,int sync,int status)24 static void qcom_smmu_tlb_sync(struct arm_smmu_device *smmu, int page,
25 int sync, int status)
26 {
27 unsigned int spin_cnt, delay;
28 u32 reg;
29
30 arm_smmu_writel(smmu, page, sync, QCOM_DUMMY_VAL);
31 for (delay = 1; delay < TLB_LOOP_TIMEOUT; delay *= 2) {
32 for (spin_cnt = TLB_SPIN_COUNT; spin_cnt > 0; spin_cnt--) {
33 reg = arm_smmu_readl(smmu, page, status);
34 if (!(reg & ARM_SMMU_sTLBGSTATUS_GSACTIVE))
35 return;
36 cpu_relax();
37 }
38 udelay(delay);
39 }
40
41 qcom_smmu_tlb_sync_debug(smmu);
42 }
43
qcom_adreno_smmu_write_sctlr(struct arm_smmu_device * smmu,int idx,u32 reg)44 static void qcom_adreno_smmu_write_sctlr(struct arm_smmu_device *smmu, int idx,
45 u32 reg)
46 {
47 struct qcom_smmu *qsmmu = to_qcom_smmu(smmu);
48
49 /*
50 * On the GPU device we want to process subsequent transactions after a
51 * fault to keep the GPU from hanging
52 */
53 reg |= ARM_SMMU_SCTLR_HUPCF;
54
55 if (qsmmu->stall_enabled & BIT(idx))
56 reg |= ARM_SMMU_SCTLR_CFCFG;
57
58 arm_smmu_cb_write(smmu, idx, ARM_SMMU_CB_SCTLR, reg);
59 }
60
qcom_adreno_smmu_get_fault_info(const void * cookie,struct adreno_smmu_fault_info * info)61 static void qcom_adreno_smmu_get_fault_info(const void *cookie,
62 struct adreno_smmu_fault_info *info)
63 {
64 struct arm_smmu_domain *smmu_domain = (void *)cookie;
65 struct arm_smmu_cfg *cfg = &smmu_domain->cfg;
66 struct arm_smmu_device *smmu = smmu_domain->smmu;
67
68 info->fsr = arm_smmu_cb_read(smmu, cfg->cbndx, ARM_SMMU_CB_FSR);
69 info->fsynr0 = arm_smmu_cb_read(smmu, cfg->cbndx, ARM_SMMU_CB_FSYNR0);
70 info->fsynr1 = arm_smmu_cb_read(smmu, cfg->cbndx, ARM_SMMU_CB_FSYNR1);
71 info->far = arm_smmu_cb_readq(smmu, cfg->cbndx, ARM_SMMU_CB_FAR);
72 info->cbfrsynra = arm_smmu_gr1_read(smmu, ARM_SMMU_GR1_CBFRSYNRA(cfg->cbndx));
73 info->ttbr0 = arm_smmu_cb_readq(smmu, cfg->cbndx, ARM_SMMU_CB_TTBR0);
74 info->contextidr = arm_smmu_cb_read(smmu, cfg->cbndx, ARM_SMMU_CB_CONTEXTIDR);
75 }
76
qcom_adreno_smmu_set_stall(const void * cookie,bool enabled)77 static void qcom_adreno_smmu_set_stall(const void *cookie, bool enabled)
78 {
79 struct arm_smmu_domain *smmu_domain = (void *)cookie;
80 struct arm_smmu_cfg *cfg = &smmu_domain->cfg;
81 struct qcom_smmu *qsmmu = to_qcom_smmu(smmu_domain->smmu);
82
83 if (enabled)
84 qsmmu->stall_enabled |= BIT(cfg->cbndx);
85 else
86 qsmmu->stall_enabled &= ~BIT(cfg->cbndx);
87 }
88
qcom_adreno_smmu_resume_translation(const void * cookie,bool terminate)89 static void qcom_adreno_smmu_resume_translation(const void *cookie, bool terminate)
90 {
91 struct arm_smmu_domain *smmu_domain = (void *)cookie;
92 struct arm_smmu_cfg *cfg = &smmu_domain->cfg;
93 struct arm_smmu_device *smmu = smmu_domain->smmu;
94 u32 reg = 0;
95
96 if (terminate)
97 reg |= ARM_SMMU_RESUME_TERMINATE;
98
99 arm_smmu_cb_write(smmu, cfg->cbndx, ARM_SMMU_CB_RESUME, reg);
100 }
101
102 #define QCOM_ADRENO_SMMU_GPU_SID 0
103
qcom_adreno_smmu_is_gpu_device(struct device * dev)104 static bool qcom_adreno_smmu_is_gpu_device(struct device *dev)
105 {
106 struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev);
107 int i;
108
109 /*
110 * The GPU will always use SID 0 so that is a handy way to uniquely
111 * identify it and configure it for per-instance pagetables
112 */
113 for (i = 0; i < fwspec->num_ids; i++) {
114 u16 sid = FIELD_GET(ARM_SMMU_SMR_ID, fwspec->ids[i]);
115
116 if (sid == QCOM_ADRENO_SMMU_GPU_SID)
117 return true;
118 }
119
120 return false;
121 }
122
qcom_adreno_smmu_get_ttbr1_cfg(const void * cookie)123 static const struct io_pgtable_cfg *qcom_adreno_smmu_get_ttbr1_cfg(
124 const void *cookie)
125 {
126 struct arm_smmu_domain *smmu_domain = (void *)cookie;
127 struct io_pgtable *pgtable =
128 io_pgtable_ops_to_pgtable(smmu_domain->pgtbl_ops);
129 return &pgtable->cfg;
130 }
131
132 /*
133 * Local implementation to configure TTBR0 with the specified pagetable config.
134 * The GPU driver will call this to enable TTBR0 when per-instance pagetables
135 * are active
136 */
137
qcom_adreno_smmu_set_ttbr0_cfg(const void * cookie,const struct io_pgtable_cfg * pgtbl_cfg)138 static int qcom_adreno_smmu_set_ttbr0_cfg(const void *cookie,
139 const struct io_pgtable_cfg *pgtbl_cfg)
140 {
141 struct arm_smmu_domain *smmu_domain = (void *)cookie;
142 struct io_pgtable *pgtable = io_pgtable_ops_to_pgtable(smmu_domain->pgtbl_ops);
143 struct arm_smmu_cfg *cfg = &smmu_domain->cfg;
144 struct arm_smmu_cb *cb = &smmu_domain->smmu->cbs[cfg->cbndx];
145
146 /* The domain must have split pagetables already enabled */
147 if (cb->tcr[0] & ARM_SMMU_TCR_EPD1)
148 return -EINVAL;
149
150 /* If the pagetable config is NULL, disable TTBR0 */
151 if (!pgtbl_cfg) {
152 /* Do nothing if it is already disabled */
153 if ((cb->tcr[0] & ARM_SMMU_TCR_EPD0))
154 return -EINVAL;
155
156 /* Set TCR to the original configuration */
157 cb->tcr[0] = arm_smmu_lpae_tcr(&pgtable->cfg);
158 cb->ttbr[0] = FIELD_PREP(ARM_SMMU_TTBRn_ASID, cb->cfg->asid);
159 } else {
160 u32 tcr = cb->tcr[0];
161
162 /* Don't call this again if TTBR0 is already enabled */
163 if (!(cb->tcr[0] & ARM_SMMU_TCR_EPD0))
164 return -EINVAL;
165
166 tcr |= arm_smmu_lpae_tcr(pgtbl_cfg);
167 tcr &= ~(ARM_SMMU_TCR_EPD0 | ARM_SMMU_TCR_EPD1);
168
169 cb->tcr[0] = tcr;
170 cb->ttbr[0] = pgtbl_cfg->arm_lpae_s1_cfg.ttbr;
171 cb->ttbr[0] |= FIELD_PREP(ARM_SMMU_TTBRn_ASID, cb->cfg->asid);
172 }
173
174 arm_smmu_write_context_bank(smmu_domain->smmu, cb->cfg->cbndx);
175
176 return 0;
177 }
178
qcom_adreno_smmu_alloc_context_bank(struct arm_smmu_domain * smmu_domain,struct arm_smmu_device * smmu,struct device * dev,int start)179 static int qcom_adreno_smmu_alloc_context_bank(struct arm_smmu_domain *smmu_domain,
180 struct arm_smmu_device *smmu,
181 struct device *dev, int start)
182 {
183 int count;
184
185 /*
186 * Assign context bank 0 to the GPU device so the GPU hardware can
187 * switch pagetables
188 */
189 if (qcom_adreno_smmu_is_gpu_device(dev)) {
190 start = 0;
191 count = 1;
192 } else {
193 start = 1;
194 count = smmu->num_context_banks;
195 }
196
197 return __arm_smmu_alloc_bitmap(smmu->context_map, start, count);
198 }
199
qcom_adreno_can_do_ttbr1(struct arm_smmu_device * smmu)200 static bool qcom_adreno_can_do_ttbr1(struct arm_smmu_device *smmu)
201 {
202 const struct device_node *np = smmu->dev->of_node;
203
204 if (of_device_is_compatible(np, "qcom,msm8996-smmu-v2"))
205 return false;
206
207 return true;
208 }
209
qcom_adreno_smmu_init_context(struct arm_smmu_domain * smmu_domain,struct io_pgtable_cfg * pgtbl_cfg,struct device * dev)210 static int qcom_adreno_smmu_init_context(struct arm_smmu_domain *smmu_domain,
211 struct io_pgtable_cfg *pgtbl_cfg, struct device *dev)
212 {
213 struct adreno_smmu_priv *priv;
214
215 smmu_domain->cfg.flush_walk_prefer_tlbiasid = true;
216
217 /* Only enable split pagetables for the GPU device (SID 0) */
218 if (!qcom_adreno_smmu_is_gpu_device(dev))
219 return 0;
220
221 /*
222 * All targets that use the qcom,adreno-smmu compatible string *should*
223 * be AARCH64 stage 1 but double check because the arm-smmu code assumes
224 * that is the case when the TTBR1 quirk is enabled
225 */
226 if (qcom_adreno_can_do_ttbr1(smmu_domain->smmu) &&
227 (smmu_domain->stage == ARM_SMMU_DOMAIN_S1) &&
228 (smmu_domain->cfg.fmt == ARM_SMMU_CTX_FMT_AARCH64))
229 pgtbl_cfg->quirks |= IO_PGTABLE_QUIRK_ARM_TTBR1;
230
231 /*
232 * Initialize private interface with GPU:
233 */
234
235 priv = dev_get_drvdata(dev);
236 priv->cookie = smmu_domain;
237 priv->get_ttbr1_cfg = qcom_adreno_smmu_get_ttbr1_cfg;
238 priv->set_ttbr0_cfg = qcom_adreno_smmu_set_ttbr0_cfg;
239 priv->get_fault_info = qcom_adreno_smmu_get_fault_info;
240 priv->set_stall = qcom_adreno_smmu_set_stall;
241 priv->resume_translation = qcom_adreno_smmu_resume_translation;
242
243 return 0;
244 }
245
246 static const struct of_device_id qcom_smmu_client_of_match[] __maybe_unused = {
247 { .compatible = "qcom,adreno" },
248 { .compatible = "qcom,adreno-gmu" },
249 { .compatible = "qcom,mdp4" },
250 { .compatible = "qcom,mdss" },
251 { .compatible = "qcom,qcm2290-mdss" },
252 { .compatible = "qcom,sc7180-mdss" },
253 { .compatible = "qcom,sc7180-mss-pil" },
254 { .compatible = "qcom,sc7280-mdss" },
255 { .compatible = "qcom,sc7280-mss-pil" },
256 { .compatible = "qcom,sc8180x-mdss" },
257 { .compatible = "qcom,sc8280xp-mdss" },
258 { .compatible = "qcom,sdm670-mdss" },
259 { .compatible = "qcom,sdm845-mdss" },
260 { .compatible = "qcom,sdm845-mss-pil" },
261 { .compatible = "qcom,sm6115-mdss" },
262 { .compatible = "qcom,sm6350-mdss" },
263 { .compatible = "qcom,sm6375-mdss" },
264 { .compatible = "qcom,sm8150-mdss" },
265 { .compatible = "qcom,sm8250-mdss" },
266 { .compatible = "qcom,x1e80100-mdss" },
267 { }
268 };
269
qcom_smmu_init_context(struct arm_smmu_domain * smmu_domain,struct io_pgtable_cfg * pgtbl_cfg,struct device * dev)270 static int qcom_smmu_init_context(struct arm_smmu_domain *smmu_domain,
271 struct io_pgtable_cfg *pgtbl_cfg, struct device *dev)
272 {
273 smmu_domain->cfg.flush_walk_prefer_tlbiasid = true;
274
275 return 0;
276 }
277
qcom_smmu_cfg_probe(struct arm_smmu_device * smmu)278 static int qcom_smmu_cfg_probe(struct arm_smmu_device *smmu)
279 {
280 struct qcom_smmu *qsmmu = to_qcom_smmu(smmu);
281 unsigned int last_s2cr;
282 u32 reg;
283 u32 smr;
284 int i;
285
286 /*
287 * MSM8998 LPASS SMMU reports 13 context banks, but accessing
288 * the last context bank crashes the system.
289 */
290 if (of_device_is_compatible(smmu->dev->of_node, "qcom,msm8998-smmu-v2") &&
291 smmu->num_context_banks == 13) {
292 smmu->num_context_banks = 12;
293 } else if (of_device_is_compatible(smmu->dev->of_node, "qcom,sdm630-smmu-v2")) {
294 if (smmu->num_context_banks == 21) /* SDM630 / SDM660 A2NOC SMMU */
295 smmu->num_context_banks = 7;
296 else if (smmu->num_context_banks == 14) /* SDM630 / SDM660 LPASS SMMU */
297 smmu->num_context_banks = 13;
298 }
299
300 /*
301 * Some platforms support more than the Arm SMMU architected maximum of
302 * 128 stream matching groups. For unknown reasons, the additional
303 * groups don't exhibit the same behavior as the architected registers,
304 * so limit the groups to 128 until the behavior is fixed for the other
305 * groups.
306 */
307 if (smmu->num_mapping_groups > 128) {
308 dev_notice(smmu->dev, "\tLimiting the stream matching groups to 128\n");
309 smmu->num_mapping_groups = 128;
310 }
311
312 last_s2cr = ARM_SMMU_GR0_S2CR(smmu->num_mapping_groups - 1);
313
314 /*
315 * With some firmware versions writes to S2CR of type FAULT are
316 * ignored, and writing BYPASS will end up written as FAULT in the
317 * register. Perform a write to S2CR to detect if this is the case and
318 * if so reserve a context bank to emulate bypass streams.
319 */
320 reg = FIELD_PREP(ARM_SMMU_S2CR_TYPE, S2CR_TYPE_BYPASS) |
321 FIELD_PREP(ARM_SMMU_S2CR_CBNDX, 0xff) |
322 FIELD_PREP(ARM_SMMU_S2CR_PRIVCFG, S2CR_PRIVCFG_DEFAULT);
323 arm_smmu_gr0_write(smmu, last_s2cr, reg);
324 reg = arm_smmu_gr0_read(smmu, last_s2cr);
325 if (FIELD_GET(ARM_SMMU_S2CR_TYPE, reg) != S2CR_TYPE_BYPASS) {
326 qsmmu->bypass_quirk = true;
327 qsmmu->bypass_cbndx = smmu->num_context_banks - 1;
328
329 set_bit(qsmmu->bypass_cbndx, smmu->context_map);
330
331 arm_smmu_cb_write(smmu, qsmmu->bypass_cbndx, ARM_SMMU_CB_SCTLR, 0);
332
333 reg = FIELD_PREP(ARM_SMMU_CBAR_TYPE, CBAR_TYPE_S1_TRANS_S2_BYPASS);
334 arm_smmu_gr1_write(smmu, ARM_SMMU_GR1_CBAR(qsmmu->bypass_cbndx), reg);
335 }
336
337 for (i = 0; i < smmu->num_mapping_groups; i++) {
338 smr = arm_smmu_gr0_read(smmu, ARM_SMMU_GR0_SMR(i));
339
340 if (FIELD_GET(ARM_SMMU_SMR_VALID, smr)) {
341 /* Ignore valid bit for SMR mask extraction. */
342 smr &= ~ARM_SMMU_SMR_VALID;
343 smmu->smrs[i].id = FIELD_GET(ARM_SMMU_SMR_ID, smr);
344 smmu->smrs[i].mask = FIELD_GET(ARM_SMMU_SMR_MASK, smr);
345 smmu->smrs[i].valid = true;
346
347 smmu->s2crs[i].type = S2CR_TYPE_BYPASS;
348 smmu->s2crs[i].privcfg = S2CR_PRIVCFG_DEFAULT;
349 smmu->s2crs[i].cbndx = 0xff;
350 }
351 }
352
353 return 0;
354 }
355
qcom_adreno_smmuv2_cfg_probe(struct arm_smmu_device * smmu)356 static int qcom_adreno_smmuv2_cfg_probe(struct arm_smmu_device *smmu)
357 {
358 /* Support for 16K pages is advertised on some SoCs, but it doesn't seem to work */
359 smmu->features &= ~ARM_SMMU_FEAT_FMT_AARCH64_16K;
360
361 /* TZ protects several last context banks, hide them from Linux */
362 if (of_device_is_compatible(smmu->dev->of_node, "qcom,sdm630-smmu-v2") &&
363 smmu->num_context_banks == 5)
364 smmu->num_context_banks = 2;
365
366 return 0;
367 }
368
qcom_smmu_write_s2cr(struct arm_smmu_device * smmu,int idx)369 static void qcom_smmu_write_s2cr(struct arm_smmu_device *smmu, int idx)
370 {
371 struct arm_smmu_s2cr *s2cr = smmu->s2crs + idx;
372 struct qcom_smmu *qsmmu = to_qcom_smmu(smmu);
373 u32 cbndx = s2cr->cbndx;
374 u32 type = s2cr->type;
375 u32 reg;
376
377 if (qsmmu->bypass_quirk) {
378 if (type == S2CR_TYPE_BYPASS) {
379 /*
380 * Firmware with quirky S2CR handling will substitute
381 * BYPASS writes with FAULT, so point the stream to the
382 * reserved context bank and ask for translation on the
383 * stream
384 */
385 type = S2CR_TYPE_TRANS;
386 cbndx = qsmmu->bypass_cbndx;
387 } else if (type == S2CR_TYPE_FAULT) {
388 /*
389 * Firmware with quirky S2CR handling will ignore FAULT
390 * writes, so trick it to write FAULT by asking for a
391 * BYPASS.
392 */
393 type = S2CR_TYPE_BYPASS;
394 cbndx = 0xff;
395 }
396 }
397
398 reg = FIELD_PREP(ARM_SMMU_S2CR_TYPE, type) |
399 FIELD_PREP(ARM_SMMU_S2CR_CBNDX, cbndx) |
400 FIELD_PREP(ARM_SMMU_S2CR_PRIVCFG, s2cr->privcfg);
401 arm_smmu_gr0_write(smmu, ARM_SMMU_GR0_S2CR(idx), reg);
402 }
403
qcom_smmu_def_domain_type(struct device * dev)404 static int qcom_smmu_def_domain_type(struct device *dev)
405 {
406 const struct of_device_id *match =
407 of_match_device(qcom_smmu_client_of_match, dev);
408
409 return match ? IOMMU_DOMAIN_IDENTITY : 0;
410 }
411
qcom_sdm845_smmu500_reset(struct arm_smmu_device * smmu)412 static int qcom_sdm845_smmu500_reset(struct arm_smmu_device *smmu)
413 {
414 int ret;
415
416 arm_mmu500_reset(smmu);
417
418 /*
419 * To address performance degradation in non-real time clients,
420 * such as USB and UFS, turn off wait-for-safe on sdm845 based boards,
421 * such as MTP and db845, whose firmwares implement secure monitor
422 * call handlers to turn on/off the wait-for-safe logic.
423 */
424 ret = qcom_scm_qsmmu500_wait_safe_toggle(0);
425 if (ret)
426 dev_warn(smmu->dev, "Failed to turn off SAFE logic\n");
427
428 return ret;
429 }
430
431 static const struct arm_smmu_impl qcom_smmu_v2_impl = {
432 .init_context = qcom_smmu_init_context,
433 .cfg_probe = qcom_smmu_cfg_probe,
434 .def_domain_type = qcom_smmu_def_domain_type,
435 .write_s2cr = qcom_smmu_write_s2cr,
436 .tlb_sync = qcom_smmu_tlb_sync,
437 };
438
439 static const struct arm_smmu_impl qcom_smmu_500_impl = {
440 .init_context = qcom_smmu_init_context,
441 .cfg_probe = qcom_smmu_cfg_probe,
442 .def_domain_type = qcom_smmu_def_domain_type,
443 .reset = arm_mmu500_reset,
444 .write_s2cr = qcom_smmu_write_s2cr,
445 .tlb_sync = qcom_smmu_tlb_sync,
446 #ifdef CONFIG_ARM_SMMU_QCOM_DEBUG
447 .context_fault = qcom_smmu_context_fault,
448 .context_fault_needs_threaded_irq = true,
449 #endif
450 };
451
452 static const struct arm_smmu_impl sdm845_smmu_500_impl = {
453 .init_context = qcom_smmu_init_context,
454 .cfg_probe = qcom_smmu_cfg_probe,
455 .def_domain_type = qcom_smmu_def_domain_type,
456 .reset = qcom_sdm845_smmu500_reset,
457 .write_s2cr = qcom_smmu_write_s2cr,
458 .tlb_sync = qcom_smmu_tlb_sync,
459 #ifdef CONFIG_ARM_SMMU_QCOM_DEBUG
460 .context_fault = qcom_smmu_context_fault,
461 .context_fault_needs_threaded_irq = true,
462 #endif
463 };
464
465 static const struct arm_smmu_impl qcom_adreno_smmu_v2_impl = {
466 .init_context = qcom_adreno_smmu_init_context,
467 .cfg_probe = qcom_adreno_smmuv2_cfg_probe,
468 .def_domain_type = qcom_smmu_def_domain_type,
469 .alloc_context_bank = qcom_adreno_smmu_alloc_context_bank,
470 .write_sctlr = qcom_adreno_smmu_write_sctlr,
471 .tlb_sync = qcom_smmu_tlb_sync,
472 };
473
474 static const struct arm_smmu_impl qcom_adreno_smmu_500_impl = {
475 .init_context = qcom_adreno_smmu_init_context,
476 .def_domain_type = qcom_smmu_def_domain_type,
477 .reset = arm_mmu500_reset,
478 .alloc_context_bank = qcom_adreno_smmu_alloc_context_bank,
479 .write_sctlr = qcom_adreno_smmu_write_sctlr,
480 .tlb_sync = qcom_smmu_tlb_sync,
481 };
482
qcom_smmu_create(struct arm_smmu_device * smmu,const struct qcom_smmu_match_data * data)483 static struct arm_smmu_device *qcom_smmu_create(struct arm_smmu_device *smmu,
484 const struct qcom_smmu_match_data *data)
485 {
486 const struct device_node *np = smmu->dev->of_node;
487 const struct arm_smmu_impl *impl;
488 struct qcom_smmu *qsmmu;
489
490 if (!data)
491 return ERR_PTR(-EINVAL);
492
493 if (np && of_device_is_compatible(np, "qcom,adreno-smmu"))
494 impl = data->adreno_impl;
495 else
496 impl = data->impl;
497
498 if (!impl)
499 return smmu;
500
501 /* Check to make sure qcom_scm has finished probing */
502 if (!qcom_scm_is_available())
503 return ERR_PTR(dev_err_probe(smmu->dev, -EPROBE_DEFER,
504 "qcom_scm not ready\n"));
505
506 qsmmu = devm_krealloc(smmu->dev, smmu, sizeof(*qsmmu), GFP_KERNEL);
507 if (!qsmmu)
508 return ERR_PTR(-ENOMEM);
509
510 qsmmu->smmu.impl = impl;
511 qsmmu->cfg = data->cfg;
512
513 return &qsmmu->smmu;
514 }
515
516 /* Implementation Defined Register Space 0 register offsets */
517 static const u32 qcom_smmu_impl0_reg_offset[] = {
518 [QCOM_SMMU_TBU_PWR_STATUS] = 0x2204,
519 [QCOM_SMMU_STATS_SYNC_INV_TBU_ACK] = 0x25dc,
520 [QCOM_SMMU_MMU2QSS_AND_SAFE_WAIT_CNTR] = 0x2670,
521 };
522
523 static const struct qcom_smmu_config qcom_smmu_impl0_cfg = {
524 .reg_offset = qcom_smmu_impl0_reg_offset,
525 };
526
527 /*
528 * It is not yet possible to use MDP SMMU with the bypass quirk on the msm8996,
529 * there are not enough context banks.
530 */
531 static const struct qcom_smmu_match_data msm8996_smmu_data = {
532 .impl = NULL,
533 .adreno_impl = &qcom_adreno_smmu_v2_impl,
534 };
535
536 static const struct qcom_smmu_match_data qcom_smmu_v2_data = {
537 .impl = &qcom_smmu_v2_impl,
538 .adreno_impl = &qcom_adreno_smmu_v2_impl,
539 };
540
541 static const struct qcom_smmu_match_data sdm845_smmu_500_data = {
542 .impl = &sdm845_smmu_500_impl,
543 /*
544 * No need for adreno impl here. On sdm845 the Adreno SMMU is handled
545 * by the separate sdm845-smmu-v2 device.
546 */
547 /* Also no debug configuration. */
548 };
549
550 static const struct qcom_smmu_match_data qcom_smmu_500_impl0_data = {
551 .impl = &qcom_smmu_500_impl,
552 .adreno_impl = &qcom_adreno_smmu_500_impl,
553 .cfg = &qcom_smmu_impl0_cfg,
554 };
555
556 /*
557 * Do not add any more qcom,SOC-smmu-500 entries to this list, unless they need
558 * special handling and can not be covered by the qcom,smmu-500 entry.
559 */
560 static const struct of_device_id __maybe_unused qcom_smmu_impl_of_match[] = {
561 { .compatible = "qcom,msm8996-smmu-v2", .data = &msm8996_smmu_data },
562 { .compatible = "qcom,msm8998-smmu-v2", .data = &qcom_smmu_v2_data },
563 { .compatible = "qcom,qcm2290-smmu-500", .data = &qcom_smmu_500_impl0_data },
564 { .compatible = "qcom,qdu1000-smmu-500", .data = &qcom_smmu_500_impl0_data },
565 { .compatible = "qcom,sc7180-smmu-500", .data = &qcom_smmu_500_impl0_data },
566 { .compatible = "qcom,sc7180-smmu-v2", .data = &qcom_smmu_v2_data },
567 { .compatible = "qcom,sc7280-smmu-500", .data = &qcom_smmu_500_impl0_data },
568 { .compatible = "qcom,sc8180x-smmu-500", .data = &qcom_smmu_500_impl0_data },
569 { .compatible = "qcom,sc8280xp-smmu-500", .data = &qcom_smmu_500_impl0_data },
570 { .compatible = "qcom,sdm630-smmu-v2", .data = &qcom_smmu_v2_data },
571 { .compatible = "qcom,sdm670-smmu-v2", .data = &qcom_smmu_v2_data },
572 { .compatible = "qcom,sdm845-smmu-v2", .data = &qcom_smmu_v2_data },
573 { .compatible = "qcom,sdm845-smmu-500", .data = &sdm845_smmu_500_data },
574 { .compatible = "qcom,sm6115-smmu-500", .data = &qcom_smmu_500_impl0_data},
575 { .compatible = "qcom,sm6125-smmu-500", .data = &qcom_smmu_500_impl0_data },
576 { .compatible = "qcom,sm6350-smmu-v2", .data = &qcom_smmu_v2_data },
577 { .compatible = "qcom,sm6350-smmu-500", .data = &qcom_smmu_500_impl0_data },
578 { .compatible = "qcom,sm6375-smmu-v2", .data = &qcom_smmu_v2_data },
579 { .compatible = "qcom,sm6375-smmu-500", .data = &qcom_smmu_500_impl0_data },
580 { .compatible = "qcom,sm7150-smmu-v2", .data = &qcom_smmu_v2_data },
581 { .compatible = "qcom,sm8150-smmu-500", .data = &qcom_smmu_500_impl0_data },
582 { .compatible = "qcom,sm8250-smmu-500", .data = &qcom_smmu_500_impl0_data },
583 { .compatible = "qcom,sm8350-smmu-500", .data = &qcom_smmu_500_impl0_data },
584 { .compatible = "qcom,sm8450-smmu-500", .data = &qcom_smmu_500_impl0_data },
585 { .compatible = "qcom,smmu-500", .data = &qcom_smmu_500_impl0_data },
586 { }
587 };
588
589 #ifdef CONFIG_ACPI
590 static struct acpi_platform_list qcom_acpi_platlist[] = {
591 { "LENOVO", "CB-01 ", 0x8180, ACPI_SIG_IORT, equal, "QCOM SMMU" },
592 { "QCOM ", "QCOMEDK2", 0x8180, ACPI_SIG_IORT, equal, "QCOM SMMU" },
593 { }
594 };
595 #endif
596
qcom_smmu_tbu_probe(struct platform_device * pdev)597 static int qcom_smmu_tbu_probe(struct platform_device *pdev)
598 {
599 struct device *dev = &pdev->dev;
600 int ret;
601
602 if (IS_ENABLED(CONFIG_ARM_SMMU_QCOM_DEBUG)) {
603 ret = qcom_tbu_probe(pdev);
604 if (ret)
605 return ret;
606 }
607
608 if (dev->pm_domain) {
609 pm_runtime_set_active(dev);
610 pm_runtime_enable(dev);
611 }
612
613 return 0;
614 }
615
616 static const struct of_device_id qcom_smmu_tbu_of_match[] = {
617 { .compatible = "qcom,sc7280-tbu" },
618 { .compatible = "qcom,sdm845-tbu" },
619 { }
620 };
621
622 static struct platform_driver qcom_smmu_tbu_driver = {
623 .driver = {
624 .name = "qcom_tbu",
625 .of_match_table = qcom_smmu_tbu_of_match,
626 },
627 .probe = qcom_smmu_tbu_probe,
628 };
629
qcom_smmu_impl_init(struct arm_smmu_device * smmu)630 struct arm_smmu_device *qcom_smmu_impl_init(struct arm_smmu_device *smmu)
631 {
632 const struct device_node *np = smmu->dev->of_node;
633 const struct of_device_id *match;
634 static u8 tbu_registered;
635
636 if (!tbu_registered++)
637 platform_driver_register(&qcom_smmu_tbu_driver);
638
639 #ifdef CONFIG_ACPI
640 if (np == NULL) {
641 /* Match platform for ACPI boot */
642 if (acpi_match_platform_list(qcom_acpi_platlist) >= 0)
643 return qcom_smmu_create(smmu, &qcom_smmu_500_impl0_data);
644 }
645 #endif
646
647 match = of_match_node(qcom_smmu_impl_of_match, np);
648 if (match)
649 return qcom_smmu_create(smmu, match->data);
650
651 /*
652 * If you hit this WARN_ON() you are missing an entry in the
653 * qcom_smmu_impl_of_match[] table, and GPU per-process page-
654 * tables will be broken.
655 */
656 WARN(of_device_is_compatible(np, "qcom,adreno-smmu"),
657 "Missing qcom_smmu_impl_of_match entry for: %s",
658 dev_name(smmu->dev));
659
660 return smmu;
661 }
662