1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * imx214.c - imx214 sensor driver
4 *
5 * Copyright 2018 Qtechnology A/S
6 *
7 * Ricardo Ribalda <ribalda@kernel.org>
8 */
9 #include <linux/clk.h>
10 #include <linux/delay.h>
11 #include <linux/gpio/consumer.h>
12 #include <linux/i2c.h>
13 #include <linux/module.h>
14 #include <linux/pm_runtime.h>
15 #include <linux/regmap.h>
16 #include <linux/regulator/consumer.h>
17 #include <media/media-entity.h>
18 #include <media/v4l2-cci.h>
19 #include <media/v4l2-ctrls.h>
20 #include <media/v4l2-fwnode.h>
21 #include <media/v4l2-subdev.h>
22
23 #define IMX214_REG_MODE_SELECT CCI_REG8(0x0100)
24 #define IMX214_MODE_STANDBY 0x00
25 #define IMX214_MODE_STREAMING 0x01
26
27 #define IMX214_REG_FAST_STANDBY_CTRL CCI_REG8(0x0106)
28
29 #define IMX214_DEFAULT_CLK_FREQ 24000000
30 #define IMX214_DEFAULT_LINK_FREQ 600000000
31 /* Keep wrong link frequency for backward compatibility */
32 #define IMX214_DEFAULT_LINK_FREQ_LEGACY 480000000
33 #define IMX214_DEFAULT_PIXEL_RATE ((IMX214_DEFAULT_LINK_FREQ * 8LL) / 10)
34 #define IMX214_FPS 30
35 #define IMX214_MBUS_CODE MEDIA_BUS_FMT_SRGGB10_1X10
36
37 /* V-TIMING internal */
38 #define IMX214_REG_FRM_LENGTH_LINES CCI_REG16(0x0340)
39
40 /* Exposure control */
41 #define IMX214_REG_EXPOSURE CCI_REG16(0x0202)
42 #define IMX214_EXPOSURE_MIN 0
43 #define IMX214_EXPOSURE_MAX 3184
44 #define IMX214_EXPOSURE_STEP 1
45 #define IMX214_EXPOSURE_DEFAULT 3184
46 #define IMX214_REG_EXPOSURE_RATIO CCI_REG8(0x0222)
47 #define IMX214_REG_SHORT_EXPOSURE CCI_REG16(0x0224)
48
49 /* Analog gain control */
50 #define IMX214_REG_ANALOG_GAIN CCI_REG16(0x0204)
51 #define IMX214_REG_SHORT_ANALOG_GAIN CCI_REG16(0x0216)
52
53 /* Digital gain control */
54 #define IMX214_REG_DIG_GAIN_GREENR CCI_REG16(0x020e)
55 #define IMX214_REG_DIG_GAIN_RED CCI_REG16(0x0210)
56 #define IMX214_REG_DIG_GAIN_BLUE CCI_REG16(0x0212)
57 #define IMX214_REG_DIG_GAIN_GREENB CCI_REG16(0x0214)
58
59 #define IMX214_REG_ORIENTATION CCI_REG8(0x0101)
60
61 #define IMX214_REG_MASK_CORR_FRAMES CCI_REG8(0x0105)
62 #define IMX214_CORR_FRAMES_TRANSMIT 0
63 #define IMX214_CORR_FRAMES_MASK 1
64
65 #define IMX214_REG_CSI_DATA_FORMAT CCI_REG16(0x0112)
66 #define IMX214_CSI_DATA_FORMAT_RAW8 0x0808
67 #define IMX214_CSI_DATA_FORMAT_RAW10 0x0A0A
68 #define IMX214_CSI_DATA_FORMAT_COMP6 0x0A06
69 #define IMX214_CSI_DATA_FORMAT_COMP8 0x0A08
70
71 #define IMX214_REG_CSI_LANE_MODE CCI_REG8(0x0114)
72 #define IMX214_CSI_2_LANE_MODE 1
73 #define IMX214_CSI_4_LANE_MODE 3
74
75 #define IMX214_REG_EXCK_FREQ CCI_REG16(0x0136)
76 #define IMX214_EXCK_FREQ(n) ((n) * 256) /* n expressed in MHz */
77
78 #define IMX214_REG_TEMP_SENSOR_CONTROL CCI_REG8(0x0138)
79
80 #define IMX214_REG_HDR_MODE CCI_REG8(0x0220)
81 #define IMX214_HDR_MODE_OFF 0
82 #define IMX214_HDR_MODE_ON 1
83
84 #define IMX214_REG_HDR_RES_REDUCTION CCI_REG8(0x0221)
85 #define IMX214_HDR_RES_REDU_THROUGH 0x11
86 #define IMX214_HDR_RES_REDU_2_BINNING 0x22
87
88 /* PLL settings */
89 #define IMX214_REG_VTPXCK_DIV CCI_REG8(0x0301)
90 #define IMX214_REG_VTSYCK_DIV CCI_REG8(0x0303)
91 #define IMX214_REG_PREPLLCK_VT_DIV CCI_REG8(0x0305)
92 #define IMX214_REG_PLL_VT_MPY CCI_REG16(0x0306)
93 #define IMX214_REG_OPPXCK_DIV CCI_REG8(0x0309)
94 #define IMX214_REG_OPSYCK_DIV CCI_REG8(0x030b)
95 #define IMX214_REG_PLL_MULT_DRIV CCI_REG8(0x0310)
96 #define IMX214_PLL_SINGLE 0
97 #define IMX214_PLL_DUAL 1
98
99 #define IMX214_REG_LINE_LENGTH_PCK CCI_REG16(0x0342)
100 #define IMX214_REG_X_ADD_STA CCI_REG16(0x0344)
101 #define IMX214_REG_Y_ADD_STA CCI_REG16(0x0346)
102 #define IMX214_REG_X_ADD_END CCI_REG16(0x0348)
103 #define IMX214_REG_Y_ADD_END CCI_REG16(0x034a)
104 #define IMX214_REG_X_OUTPUT_SIZE CCI_REG16(0x034c)
105 #define IMX214_REG_Y_OUTPUT_SIZE CCI_REG16(0x034e)
106 #define IMX214_REG_X_EVEN_INC CCI_REG8(0x0381)
107 #define IMX214_REG_X_ODD_INC CCI_REG8(0x0383)
108 #define IMX214_REG_Y_EVEN_INC CCI_REG8(0x0385)
109 #define IMX214_REG_Y_ODD_INC CCI_REG8(0x0387)
110
111 #define IMX214_REG_SCALE_MODE CCI_REG8(0x0401)
112 #define IMX214_SCALE_NONE 0
113 #define IMX214_SCALE_HORIZONTAL 1
114 #define IMX214_SCALE_FULL 2
115 #define IMX214_REG_SCALE_M CCI_REG16(0x0404)
116
117 #define IMX214_REG_DIG_CROP_X_OFFSET CCI_REG16(0x0408)
118 #define IMX214_REG_DIG_CROP_Y_OFFSET CCI_REG16(0x040a)
119 #define IMX214_REG_DIG_CROP_WIDTH CCI_REG16(0x040c)
120 #define IMX214_REG_DIG_CROP_HEIGHT CCI_REG16(0x040e)
121
122 #define IMX214_REG_REQ_LINK_BIT_RATE CCI_REG32(0x0820)
123 #define IMX214_LINK_BIT_RATE_MBPS(n) ((n) << 16)
124
125 /* Binning mode */
126 #define IMX214_REG_BINNING_MODE CCI_REG8(0x0900)
127 #define IMX214_BINNING_NONE 0
128 #define IMX214_BINNING_ENABLE 1
129 #define IMX214_REG_BINNING_TYPE CCI_REG8(0x0901)
130 #define IMX214_REG_BINNING_WEIGHTING CCI_REG8(0x0902)
131 #define IMX214_BINNING_AVERAGE 0x00
132 #define IMX214_BINNING_SUMMED 0x01
133 #define IMX214_BINNING_BAYER 0x02
134
135 #define IMX214_REG_SING_DEF_CORR_EN CCI_REG8(0x0b06)
136 #define IMX214_SING_DEF_CORR_OFF 0
137 #define IMX214_SING_DEF_CORR_ON 1
138
139 /* AWB control */
140 #define IMX214_REG_ABS_GAIN_GREENR CCI_REG16(0x0b8e)
141 #define IMX214_REG_ABS_GAIN_RED CCI_REG16(0x0b90)
142 #define IMX214_REG_ABS_GAIN_BLUE CCI_REG16(0x0b92)
143 #define IMX214_REG_ABS_GAIN_GREENB CCI_REG16(0x0b94)
144
145 #define IMX214_REG_RMSC_NR_MODE CCI_REG8(0x3001)
146 #define IMX214_REG_STATS_OUT_EN CCI_REG8(0x3013)
147 #define IMX214_STATS_OUT_OFF 0
148 #define IMX214_STATS_OUT_ON 1
149
150 /* Chroma noise reduction */
151 #define IMX214_REG_NML_NR_EN CCI_REG8(0x30a2)
152 #define IMX214_NML_NR_OFF 0
153 #define IMX214_NML_NR_ON 1
154
155 #define IMX214_REG_EBD_SIZE_V CCI_REG8(0x5041)
156 #define IMX214_EBD_NO 0
157 #define IMX214_EBD_4_LINE 4
158
159 #define IMX214_REG_RG_STATS_LMT CCI_REG16(0x6d12)
160 #define IMX214_RG_STATS_LMT_10_BIT 0x03FF
161 #define IMX214_RG_STATS_LMT_14_BIT 0x3FFF
162
163 #define IMX214_REG_ATR_FAST_MOVE CCI_REG8(0x9300)
164
165 /* IMX214 native and active pixel array size */
166 #define IMX214_NATIVE_WIDTH 4224U
167 #define IMX214_NATIVE_HEIGHT 3136U
168 #define IMX214_PIXEL_ARRAY_LEFT 8U
169 #define IMX214_PIXEL_ARRAY_TOP 8U
170 #define IMX214_PIXEL_ARRAY_WIDTH 4208U
171 #define IMX214_PIXEL_ARRAY_HEIGHT 3120U
172
173 static const char * const imx214_supply_name[] = {
174 "vdda",
175 "vddd",
176 "vdddo",
177 };
178
179 #define IMX214_NUM_SUPPLIES ARRAY_SIZE(imx214_supply_name)
180
181 struct imx214 {
182 struct device *dev;
183 struct clk *xclk;
184 struct regmap *regmap;
185
186 struct v4l2_subdev sd;
187 struct media_pad pad;
188
189 struct v4l2_ctrl_handler ctrls;
190 struct v4l2_ctrl *pixel_rate;
191 struct v4l2_ctrl *link_freq;
192 struct v4l2_ctrl *exposure;
193 struct v4l2_ctrl *unit_size;
194
195 struct regulator_bulk_data supplies[IMX214_NUM_SUPPLIES];
196
197 struct gpio_desc *enable_gpio;
198 };
199
200 /*From imx214_mode_tbls.h*/
201 static const struct cci_reg_sequence mode_4096x2304[] = {
202 { IMX214_REG_HDR_MODE, IMX214_HDR_MODE_OFF },
203 { IMX214_REG_HDR_RES_REDUCTION, IMX214_HDR_RES_REDU_THROUGH },
204 { IMX214_REG_EXPOSURE_RATIO, 1 },
205 { IMX214_REG_FRM_LENGTH_LINES, 3194 },
206 { IMX214_REG_LINE_LENGTH_PCK, 5008 },
207 { IMX214_REG_X_ADD_STA, 56 },
208 { IMX214_REG_Y_ADD_STA, 408 },
209 { IMX214_REG_X_ADD_END, 4151 },
210 { IMX214_REG_Y_ADD_END, 2711 },
211 { IMX214_REG_X_EVEN_INC, 1 },
212 { IMX214_REG_X_ODD_INC, 1 },
213 { IMX214_REG_Y_EVEN_INC, 1 },
214 { IMX214_REG_Y_ODD_INC, 1 },
215 { IMX214_REG_BINNING_MODE, IMX214_BINNING_NONE },
216 { IMX214_REG_BINNING_TYPE, 0 },
217 { IMX214_REG_BINNING_WEIGHTING, IMX214_BINNING_AVERAGE },
218 { CCI_REG8(0x3000), 0x35 },
219 { CCI_REG8(0x3054), 0x01 },
220 { CCI_REG8(0x305C), 0x11 },
221
222 { IMX214_REG_CSI_DATA_FORMAT, IMX214_CSI_DATA_FORMAT_RAW10 },
223 { IMX214_REG_X_OUTPUT_SIZE, 4096 },
224 { IMX214_REG_Y_OUTPUT_SIZE, 2304 },
225 { IMX214_REG_SCALE_MODE, IMX214_SCALE_NONE },
226 { IMX214_REG_SCALE_M, 2 },
227 { IMX214_REG_DIG_CROP_X_OFFSET, 0 },
228 { IMX214_REG_DIG_CROP_Y_OFFSET, 0 },
229 { IMX214_REG_DIG_CROP_WIDTH, 4096 },
230 { IMX214_REG_DIG_CROP_HEIGHT, 2304 },
231
232 { IMX214_REG_VTPXCK_DIV, 5 },
233 { IMX214_REG_VTSYCK_DIV, 2 },
234 { IMX214_REG_PREPLLCK_VT_DIV, 3 },
235 { IMX214_REG_PLL_VT_MPY, 150 },
236 { IMX214_REG_OPPXCK_DIV, 10 },
237 { IMX214_REG_OPSYCK_DIV, 1 },
238 { IMX214_REG_PLL_MULT_DRIV, IMX214_PLL_SINGLE },
239
240 { IMX214_REG_REQ_LINK_BIT_RATE, IMX214_LINK_BIT_RATE_MBPS(4800) },
241
242 { CCI_REG8(0x3A03), 0x09 },
243 { CCI_REG8(0x3A04), 0x50 },
244 { CCI_REG8(0x3A05), 0x01 },
245
246 { IMX214_REG_SING_DEF_CORR_EN, IMX214_SING_DEF_CORR_ON },
247 { IMX214_REG_NML_NR_EN, IMX214_NML_NR_OFF },
248
249 { CCI_REG8(0x30B4), 0x00 },
250
251 { CCI_REG8(0x3A02), 0xFF },
252
253 { CCI_REG8(0x3011), 0x00 },
254 { IMX214_REG_STATS_OUT_EN, IMX214_STATS_OUT_ON },
255
256 { IMX214_REG_EXPOSURE, IMX214_EXPOSURE_DEFAULT },
257 { IMX214_REG_SHORT_EXPOSURE, 500 },
258
259 { IMX214_REG_ANALOG_GAIN, 0 },
260 { IMX214_REG_DIG_GAIN_GREENR, 256 },
261 { IMX214_REG_DIG_GAIN_RED, 256 },
262 { IMX214_REG_DIG_GAIN_BLUE, 256 },
263 { IMX214_REG_DIG_GAIN_GREENB, 256 },
264 { IMX214_REG_SHORT_ANALOG_GAIN, 0 },
265
266 { CCI_REG8(0x4170), 0x00 },
267 { CCI_REG8(0x4171), 0x10 },
268 { CCI_REG8(0x4176), 0x00 },
269 { CCI_REG8(0x4177), 0x3C },
270 { CCI_REG8(0xAE20), 0x04 },
271 { CCI_REG8(0xAE21), 0x5C },
272 };
273
274 static const struct cci_reg_sequence mode_1920x1080[] = {
275 { IMX214_REG_HDR_MODE, IMX214_HDR_MODE_OFF },
276 { IMX214_REG_HDR_RES_REDUCTION, IMX214_HDR_RES_REDU_THROUGH },
277 { IMX214_REG_EXPOSURE_RATIO, 1 },
278 { IMX214_REG_FRM_LENGTH_LINES, 3194 },
279 { IMX214_REG_LINE_LENGTH_PCK, 5008 },
280 { IMX214_REG_X_ADD_STA, 1144 },
281 { IMX214_REG_Y_ADD_STA, 1020 },
282 { IMX214_REG_X_ADD_END, 3063 },
283 { IMX214_REG_Y_ADD_END, 2099 },
284 { IMX214_REG_X_EVEN_INC, 1 },
285 { IMX214_REG_X_ODD_INC, 1 },
286 { IMX214_REG_Y_EVEN_INC, 1 },
287 { IMX214_REG_Y_ODD_INC, 1 },
288 { IMX214_REG_BINNING_MODE, IMX214_BINNING_NONE },
289 { IMX214_REG_BINNING_TYPE, 0 },
290 { IMX214_REG_BINNING_WEIGHTING, IMX214_BINNING_AVERAGE },
291 { CCI_REG8(0x3000), 0x35 },
292 { CCI_REG8(0x3054), 0x01 },
293 { CCI_REG8(0x305C), 0x11 },
294
295 { IMX214_REG_CSI_DATA_FORMAT, IMX214_CSI_DATA_FORMAT_RAW10 },
296 { IMX214_REG_X_OUTPUT_SIZE, 1920 },
297 { IMX214_REG_Y_OUTPUT_SIZE, 1080 },
298 { IMX214_REG_SCALE_MODE, IMX214_SCALE_NONE },
299 { IMX214_REG_SCALE_M, 2 },
300 { IMX214_REG_DIG_CROP_X_OFFSET, 0 },
301 { IMX214_REG_DIG_CROP_Y_OFFSET, 0 },
302 { IMX214_REG_DIG_CROP_WIDTH, 1920 },
303 { IMX214_REG_DIG_CROP_HEIGHT, 1080 },
304
305 { IMX214_REG_VTPXCK_DIV, 5 },
306 { IMX214_REG_VTSYCK_DIV, 2 },
307 { IMX214_REG_PREPLLCK_VT_DIV, 3 },
308 { IMX214_REG_PLL_VT_MPY, 150 },
309 { IMX214_REG_OPPXCK_DIV, 10 },
310 { IMX214_REG_OPSYCK_DIV, 1 },
311 { IMX214_REG_PLL_MULT_DRIV, IMX214_PLL_SINGLE },
312
313 { IMX214_REG_REQ_LINK_BIT_RATE, IMX214_LINK_BIT_RATE_MBPS(4800) },
314
315 { CCI_REG8(0x3A03), 0x04 },
316 { CCI_REG8(0x3A04), 0xF8 },
317 { CCI_REG8(0x3A05), 0x02 },
318
319 { IMX214_REG_SING_DEF_CORR_EN, IMX214_SING_DEF_CORR_ON },
320 { IMX214_REG_NML_NR_EN, IMX214_NML_NR_OFF },
321
322 { CCI_REG8(0x30B4), 0x00 },
323
324 { CCI_REG8(0x3A02), 0xFF },
325
326 { CCI_REG8(0x3011), 0x00 },
327 { IMX214_REG_STATS_OUT_EN, IMX214_STATS_OUT_ON },
328
329 { IMX214_REG_EXPOSURE, IMX214_EXPOSURE_DEFAULT },
330 { IMX214_REG_SHORT_EXPOSURE, 500 },
331
332 { IMX214_REG_ANALOG_GAIN, 0 },
333 { IMX214_REG_DIG_GAIN_GREENR, 256 },
334 { IMX214_REG_DIG_GAIN_RED, 256 },
335 { IMX214_REG_DIG_GAIN_BLUE, 256 },
336 { IMX214_REG_DIG_GAIN_GREENB, 256 },
337 { IMX214_REG_SHORT_ANALOG_GAIN, 0 },
338
339 { CCI_REG8(0x4170), 0x00 },
340 { CCI_REG8(0x4171), 0x10 },
341 { CCI_REG8(0x4176), 0x00 },
342 { CCI_REG8(0x4177), 0x3C },
343 { CCI_REG8(0xAE20), 0x04 },
344 { CCI_REG8(0xAE21), 0x5C },
345 };
346
347 static const struct cci_reg_sequence mode_table_common[] = {
348 /* software reset */
349
350 /* software standby settings */
351 { IMX214_REG_MODE_SELECT, IMX214_MODE_STANDBY },
352
353 /* ATR setting */
354 { IMX214_REG_ATR_FAST_MOVE, 2 },
355
356 /* external clock setting */
357 { IMX214_REG_EXCK_FREQ, IMX214_EXCK_FREQ(IMX214_DEFAULT_CLK_FREQ / 1000000) },
358
359 /* global setting */
360 /* basic config */
361 { IMX214_REG_ORIENTATION, 0 },
362 { IMX214_REG_MASK_CORR_FRAMES, IMX214_CORR_FRAMES_MASK },
363 { IMX214_REG_FAST_STANDBY_CTRL, 1 },
364 { CCI_REG8(0x4550), 0x02 },
365 { CCI_REG8(0x4601), 0x00 },
366 { CCI_REG8(0x4642), 0x05 },
367 { CCI_REG8(0x6227), 0x11 },
368 { CCI_REG8(0x6276), 0x00 },
369 { CCI_REG8(0x900E), 0x06 },
370 { CCI_REG8(0xA802), 0x90 },
371 { CCI_REG8(0xA803), 0x11 },
372 { CCI_REG8(0xA804), 0x62 },
373 { CCI_REG8(0xA805), 0x77 },
374 { CCI_REG8(0xA806), 0xAE },
375 { CCI_REG8(0xA807), 0x34 },
376 { CCI_REG8(0xA808), 0xAE },
377 { CCI_REG8(0xA809), 0x35 },
378 { CCI_REG8(0xA80A), 0x62 },
379 { CCI_REG8(0xA80B), 0x83 },
380 { CCI_REG8(0xAE33), 0x00 },
381
382 /* analog setting */
383 { CCI_REG8(0x4174), 0x00 },
384 { CCI_REG8(0x4175), 0x11 },
385 { CCI_REG8(0x4612), 0x29 },
386 { CCI_REG8(0x461B), 0x12 },
387 { CCI_REG8(0x461F), 0x06 },
388 { CCI_REG8(0x4635), 0x07 },
389 { CCI_REG8(0x4637), 0x30 },
390 { CCI_REG8(0x463F), 0x18 },
391 { CCI_REG8(0x4641), 0x0D },
392 { CCI_REG8(0x465B), 0x12 },
393 { CCI_REG8(0x465F), 0x11 },
394 { CCI_REG8(0x4663), 0x11 },
395 { CCI_REG8(0x4667), 0x0F },
396 { CCI_REG8(0x466F), 0x0F },
397 { CCI_REG8(0x470E), 0x09 },
398 { CCI_REG8(0x4909), 0xAB },
399 { CCI_REG8(0x490B), 0x95 },
400 { CCI_REG8(0x4915), 0x5D },
401 { CCI_REG8(0x4A5F), 0xFF },
402 { CCI_REG8(0x4A61), 0xFF },
403 { CCI_REG8(0x4A73), 0x62 },
404 { CCI_REG8(0x4A85), 0x00 },
405 { CCI_REG8(0x4A87), 0xFF },
406
407 /* embedded data */
408 { IMX214_REG_EBD_SIZE_V, IMX214_EBD_4_LINE },
409 { CCI_REG8(0x583C), 0x04 },
410 { CCI_REG8(0x620E), 0x04 },
411 { CCI_REG8(0x6EB2), 0x01 },
412 { CCI_REG8(0x6EB3), 0x00 },
413 { IMX214_REG_ATR_FAST_MOVE, 2 },
414
415 /* imagequality */
416 /* HDR setting */
417 { IMX214_REG_RMSC_NR_MODE, 0x07 },
418 { IMX214_REG_RG_STATS_LMT, IMX214_RG_STATS_LMT_14_BIT },
419 { CCI_REG8(0x9344), 0x03 },
420 { CCI_REG8(0x9706), 0x10 },
421 { CCI_REG8(0x9707), 0x03 },
422 { CCI_REG8(0x9708), 0x03 },
423 { CCI_REG8(0x9E04), 0x01 },
424 { CCI_REG8(0x9E05), 0x00 },
425 { CCI_REG8(0x9E0C), 0x01 },
426 { CCI_REG8(0x9E0D), 0x02 },
427 { CCI_REG8(0x9E24), 0x00 },
428 { CCI_REG8(0x9E25), 0x8C },
429 { CCI_REG8(0x9E26), 0x00 },
430 { CCI_REG8(0x9E27), 0x94 },
431 { CCI_REG8(0x9E28), 0x00 },
432 { CCI_REG8(0x9E29), 0x96 },
433
434 /* CNR parameter setting */
435 { CCI_REG8(0x69DB), 0x01 },
436
437 /* Moire reduction */
438 { CCI_REG8(0x6957), 0x01 },
439
440 /* image enhancement */
441 { CCI_REG8(0x6987), 0x17 },
442 { CCI_REG8(0x698A), 0x03 },
443 { CCI_REG8(0x698B), 0x03 },
444
445 /* white balanace */
446 { IMX214_REG_ABS_GAIN_GREENR, 0x0100 },
447 { IMX214_REG_ABS_GAIN_RED, 0x0100 },
448 { IMX214_REG_ABS_GAIN_BLUE, 0x0100 },
449 { IMX214_REG_ABS_GAIN_GREENB, 0x0100 },
450
451 /* ATR setting */
452 { CCI_REG8(0x6E50), 0x00 },
453 { CCI_REG8(0x6E51), 0x32 },
454 { CCI_REG8(0x9340), 0x00 },
455 { CCI_REG8(0x9341), 0x3C },
456 { CCI_REG8(0x9342), 0x03 },
457 { CCI_REG8(0x9343), 0xFF },
458 };
459
460 /*
461 * Declare modes in order, from biggest
462 * to smallest height.
463 */
464 static const struct imx214_mode {
465 u32 width;
466 u32 height;
467 unsigned int num_of_regs;
468 const struct cci_reg_sequence *reg_table;
469 } imx214_modes[] = {
470 {
471 .width = 4096,
472 .height = 2304,
473 .num_of_regs = ARRAY_SIZE(mode_4096x2304),
474 .reg_table = mode_4096x2304,
475 },
476 {
477 .width = 1920,
478 .height = 1080,
479 .num_of_regs = ARRAY_SIZE(mode_1920x1080),
480 .reg_table = mode_1920x1080,
481 },
482 };
483
to_imx214(struct v4l2_subdev * sd)484 static inline struct imx214 *to_imx214(struct v4l2_subdev *sd)
485 {
486 return container_of(sd, struct imx214, sd);
487 }
488
imx214_power_on(struct device * dev)489 static int __maybe_unused imx214_power_on(struct device *dev)
490 {
491 struct i2c_client *client = to_i2c_client(dev);
492 struct v4l2_subdev *sd = i2c_get_clientdata(client);
493 struct imx214 *imx214 = to_imx214(sd);
494 int ret;
495
496 ret = regulator_bulk_enable(IMX214_NUM_SUPPLIES, imx214->supplies);
497 if (ret < 0) {
498 dev_err(imx214->dev, "failed to enable regulators: %d\n", ret);
499 return ret;
500 }
501
502 usleep_range(2000, 3000);
503
504 ret = clk_prepare_enable(imx214->xclk);
505 if (ret < 0) {
506 regulator_bulk_disable(IMX214_NUM_SUPPLIES, imx214->supplies);
507 dev_err(imx214->dev, "clk prepare enable failed\n");
508 return ret;
509 }
510
511 gpiod_set_value_cansleep(imx214->enable_gpio, 1);
512 usleep_range(12000, 15000);
513
514 return 0;
515 }
516
imx214_power_off(struct device * dev)517 static int __maybe_unused imx214_power_off(struct device *dev)
518 {
519 struct i2c_client *client = to_i2c_client(dev);
520 struct v4l2_subdev *sd = i2c_get_clientdata(client);
521 struct imx214 *imx214 = to_imx214(sd);
522
523 gpiod_set_value_cansleep(imx214->enable_gpio, 0);
524
525 clk_disable_unprepare(imx214->xclk);
526
527 regulator_bulk_disable(IMX214_NUM_SUPPLIES, imx214->supplies);
528 usleep_range(10, 20);
529
530 return 0;
531 }
532
imx214_update_pad_format(struct imx214 * imx214,const struct imx214_mode * mode,struct v4l2_mbus_framefmt * fmt,u32 code)533 static void imx214_update_pad_format(struct imx214 *imx214,
534 const struct imx214_mode *mode,
535 struct v4l2_mbus_framefmt *fmt, u32 code)
536 {
537 fmt->code = IMX214_MBUS_CODE;
538 fmt->width = mode->width;
539 fmt->height = mode->height;
540 fmt->field = V4L2_FIELD_NONE;
541 fmt->colorspace = V4L2_COLORSPACE_SRGB;
542 fmt->ycbcr_enc = V4L2_MAP_YCBCR_ENC_DEFAULT(fmt->colorspace);
543 fmt->quantization = V4L2_MAP_QUANTIZATION_DEFAULT(true,
544 fmt->colorspace,
545 fmt->ycbcr_enc);
546 fmt->xfer_func = V4L2_MAP_XFER_FUNC_DEFAULT(fmt->colorspace);
547 }
548
imx214_enum_mbus_code(struct v4l2_subdev * sd,struct v4l2_subdev_state * sd_state,struct v4l2_subdev_mbus_code_enum * code)549 static int imx214_enum_mbus_code(struct v4l2_subdev *sd,
550 struct v4l2_subdev_state *sd_state,
551 struct v4l2_subdev_mbus_code_enum *code)
552 {
553 if (code->index > 0)
554 return -EINVAL;
555
556 code->code = IMX214_MBUS_CODE;
557
558 return 0;
559 }
560
imx214_enum_frame_size(struct v4l2_subdev * subdev,struct v4l2_subdev_state * sd_state,struct v4l2_subdev_frame_size_enum * fse)561 static int imx214_enum_frame_size(struct v4l2_subdev *subdev,
562 struct v4l2_subdev_state *sd_state,
563 struct v4l2_subdev_frame_size_enum *fse)
564 {
565 if (fse->code != IMX214_MBUS_CODE)
566 return -EINVAL;
567
568 if (fse->index >= ARRAY_SIZE(imx214_modes))
569 return -EINVAL;
570
571 fse->min_width = fse->max_width = imx214_modes[fse->index].width;
572 fse->min_height = fse->max_height = imx214_modes[fse->index].height;
573
574 return 0;
575 }
576
577 #ifdef CONFIG_VIDEO_ADV_DEBUG
imx214_s_register(struct v4l2_subdev * subdev,const struct v4l2_dbg_register * reg)578 static int imx214_s_register(struct v4l2_subdev *subdev,
579 const struct v4l2_dbg_register *reg)
580 {
581 struct imx214 *imx214 = container_of(subdev, struct imx214, sd);
582
583 return regmap_write(imx214->regmap, reg->reg, reg->val);
584 }
585
imx214_g_register(struct v4l2_subdev * subdev,struct v4l2_dbg_register * reg)586 static int imx214_g_register(struct v4l2_subdev *subdev,
587 struct v4l2_dbg_register *reg)
588 {
589 struct imx214 *imx214 = container_of(subdev, struct imx214, sd);
590 unsigned int aux;
591 int ret;
592
593 reg->size = 1;
594 ret = regmap_read(imx214->regmap, reg->reg, &aux);
595 reg->val = aux;
596
597 return ret;
598 }
599 #endif
600
601 static const struct v4l2_subdev_core_ops imx214_core_ops = {
602 #ifdef CONFIG_VIDEO_ADV_DEBUG
603 .g_register = imx214_g_register,
604 .s_register = imx214_s_register,
605 #endif
606 };
607
imx214_set_format(struct v4l2_subdev * sd,struct v4l2_subdev_state * sd_state,struct v4l2_subdev_format * format)608 static int imx214_set_format(struct v4l2_subdev *sd,
609 struct v4l2_subdev_state *sd_state,
610 struct v4l2_subdev_format *format)
611 {
612 struct imx214 *imx214 = to_imx214(sd);
613 struct v4l2_mbus_framefmt *__format;
614 struct v4l2_rect *__crop;
615 const struct imx214_mode *mode;
616
617 mode = v4l2_find_nearest_size(imx214_modes,
618 ARRAY_SIZE(imx214_modes), width, height,
619 format->format.width,
620 format->format.height);
621
622 imx214_update_pad_format(imx214, mode, &format->format,
623 format->format.code);
624 __format = v4l2_subdev_state_get_format(sd_state, 0);
625
626 *__format = format->format;
627
628 __crop = v4l2_subdev_state_get_crop(sd_state, 0);
629 __crop->width = mode->width;
630 __crop->height = mode->height;
631
632 return 0;
633 }
634
imx214_get_selection(struct v4l2_subdev * sd,struct v4l2_subdev_state * sd_state,struct v4l2_subdev_selection * sel)635 static int imx214_get_selection(struct v4l2_subdev *sd,
636 struct v4l2_subdev_state *sd_state,
637 struct v4l2_subdev_selection *sel)
638 {
639 switch (sel->target) {
640 case V4L2_SEL_TGT_CROP:
641 sel->r = *v4l2_subdev_state_get_crop(sd_state, 0);
642 return 0;
643
644 case V4L2_SEL_TGT_NATIVE_SIZE:
645 sel->r.top = 0;
646 sel->r.left = 0;
647 sel->r.width = IMX214_NATIVE_WIDTH;
648 sel->r.height = IMX214_NATIVE_HEIGHT;
649 return 0;
650
651 case V4L2_SEL_TGT_CROP_DEFAULT:
652 case V4L2_SEL_TGT_CROP_BOUNDS:
653 sel->r.top = IMX214_PIXEL_ARRAY_TOP;
654 sel->r.left = IMX214_PIXEL_ARRAY_LEFT;
655 sel->r.width = IMX214_PIXEL_ARRAY_WIDTH;
656 sel->r.height = IMX214_PIXEL_ARRAY_HEIGHT;
657 return 0;
658 }
659
660 return -EINVAL;
661 }
662
imx214_entity_init_state(struct v4l2_subdev * subdev,struct v4l2_subdev_state * sd_state)663 static int imx214_entity_init_state(struct v4l2_subdev *subdev,
664 struct v4l2_subdev_state *sd_state)
665 {
666 struct v4l2_subdev_format fmt = { };
667
668 fmt.which = sd_state ? V4L2_SUBDEV_FORMAT_TRY : V4L2_SUBDEV_FORMAT_ACTIVE;
669 fmt.format.width = imx214_modes[0].width;
670 fmt.format.height = imx214_modes[0].height;
671
672 imx214_set_format(subdev, sd_state, &fmt);
673
674 return 0;
675 }
676
imx214_set_ctrl(struct v4l2_ctrl * ctrl)677 static int imx214_set_ctrl(struct v4l2_ctrl *ctrl)
678 {
679 struct imx214 *imx214 = container_of(ctrl->handler,
680 struct imx214, ctrls);
681 int ret;
682
683 /*
684 * Applying V4L2 control value only happens
685 * when power is up for streaming
686 */
687 if (!pm_runtime_get_if_in_use(imx214->dev))
688 return 0;
689
690 switch (ctrl->id) {
691 case V4L2_CID_EXPOSURE:
692 cci_write(imx214->regmap, IMX214_REG_EXPOSURE, ctrl->val, &ret);
693 break;
694
695 default:
696 ret = -EINVAL;
697 }
698
699 pm_runtime_put(imx214->dev);
700
701 return ret;
702 }
703
704 static const struct v4l2_ctrl_ops imx214_ctrl_ops = {
705 .s_ctrl = imx214_set_ctrl,
706 };
707
imx214_ctrls_init(struct imx214 * imx214)708 static int imx214_ctrls_init(struct imx214 *imx214)
709 {
710 static const s64 link_freq[] = {
711 IMX214_DEFAULT_LINK_FREQ
712 };
713 static const struct v4l2_area unit_size = {
714 .width = 1120,
715 .height = 1120,
716 };
717 struct v4l2_fwnode_device_properties props;
718 struct v4l2_ctrl_handler *ctrl_hdlr;
719 int ret;
720
721 ret = v4l2_fwnode_device_parse(imx214->dev, &props);
722 if (ret < 0)
723 return ret;
724
725 ctrl_hdlr = &imx214->ctrls;
726 ret = v4l2_ctrl_handler_init(&imx214->ctrls, 6);
727 if (ret)
728 return ret;
729
730 imx214->pixel_rate = v4l2_ctrl_new_std(ctrl_hdlr, NULL,
731 V4L2_CID_PIXEL_RATE, 0,
732 IMX214_DEFAULT_PIXEL_RATE, 1,
733 IMX214_DEFAULT_PIXEL_RATE);
734
735 imx214->link_freq = v4l2_ctrl_new_int_menu(ctrl_hdlr, NULL,
736 V4L2_CID_LINK_FREQ,
737 ARRAY_SIZE(link_freq) - 1,
738 0, link_freq);
739 if (imx214->link_freq)
740 imx214->link_freq->flags |= V4L2_CTRL_FLAG_READ_ONLY;
741
742 /*
743 * WARNING!
744 * Values obtained reverse engineering blobs and/or devices.
745 * Ranges and functionality might be wrong.
746 *
747 * Sony, please release some register set documentation for the
748 * device.
749 *
750 * Yours sincerely, Ricardo.
751 */
752 imx214->exposure = v4l2_ctrl_new_std(ctrl_hdlr, &imx214_ctrl_ops,
753 V4L2_CID_EXPOSURE,
754 IMX214_EXPOSURE_MIN,
755 IMX214_EXPOSURE_MAX,
756 IMX214_EXPOSURE_STEP,
757 IMX214_EXPOSURE_DEFAULT);
758
759 imx214->unit_size = v4l2_ctrl_new_std_compound(ctrl_hdlr,
760 NULL,
761 V4L2_CID_UNIT_CELL_SIZE,
762 v4l2_ctrl_ptr_create((void *)&unit_size),
763 v4l2_ctrl_ptr_create(NULL),
764 v4l2_ctrl_ptr_create(NULL));
765
766 v4l2_ctrl_new_fwnode_properties(ctrl_hdlr, &imx214_ctrl_ops, &props);
767
768 ret = ctrl_hdlr->error;
769 if (ret) {
770 v4l2_ctrl_handler_free(ctrl_hdlr);
771 dev_err(imx214->dev, "failed to add controls: %d\n", ret);
772 return ret;
773 }
774
775 imx214->sd.ctrl_handler = ctrl_hdlr;
776
777 return 0;
778 };
779
imx214_start_streaming(struct imx214 * imx214)780 static int imx214_start_streaming(struct imx214 *imx214)
781 {
782 const struct v4l2_mbus_framefmt *fmt;
783 struct v4l2_subdev_state *state;
784 const struct imx214_mode *mode;
785 int ret;
786
787 ret = cci_multi_reg_write(imx214->regmap, mode_table_common,
788 ARRAY_SIZE(mode_table_common), NULL);
789 if (ret < 0) {
790 dev_err(imx214->dev, "could not sent common table %d\n", ret);
791 return ret;
792 }
793
794 ret = cci_write(imx214->regmap, IMX214_REG_CSI_LANE_MODE,
795 IMX214_CSI_4_LANE_MODE, NULL);
796 if (ret) {
797 dev_err(imx214->dev, "failed to configure lanes\n");
798 return ret;
799 }
800
801 state = v4l2_subdev_get_locked_active_state(&imx214->sd);
802 fmt = v4l2_subdev_state_get_format(state, 0);
803 mode = v4l2_find_nearest_size(imx214_modes, ARRAY_SIZE(imx214_modes),
804 width, height, fmt->width, fmt->height);
805 ret = cci_multi_reg_write(imx214->regmap, mode->reg_table,
806 mode->num_of_regs, NULL);
807 if (ret < 0) {
808 dev_err(imx214->dev, "could not sent mode table %d\n", ret);
809 return ret;
810 }
811
812 usleep_range(10000, 10500);
813
814 cci_write(imx214->regmap, IMX214_REG_TEMP_SENSOR_CONTROL, 0x01, NULL);
815
816 ret = __v4l2_ctrl_handler_setup(&imx214->ctrls);
817 if (ret < 0) {
818 dev_err(imx214->dev, "could not sync v4l2 controls\n");
819 return ret;
820 }
821 ret = cci_write(imx214->regmap, IMX214_REG_MODE_SELECT,
822 IMX214_MODE_STREAMING, NULL);
823 if (ret < 0)
824 dev_err(imx214->dev, "could not sent start table %d\n", ret);
825
826 return ret;
827 }
828
imx214_stop_streaming(struct imx214 * imx214)829 static int imx214_stop_streaming(struct imx214 *imx214)
830 {
831 int ret;
832
833 ret = cci_write(imx214->regmap, IMX214_REG_MODE_SELECT,
834 IMX214_MODE_STANDBY, NULL);
835 if (ret < 0)
836 dev_err(imx214->dev, "could not sent stop table %d\n", ret);
837
838 return ret;
839 }
840
imx214_s_stream(struct v4l2_subdev * subdev,int enable)841 static int imx214_s_stream(struct v4l2_subdev *subdev, int enable)
842 {
843 struct imx214 *imx214 = to_imx214(subdev);
844 struct v4l2_subdev_state *state;
845 int ret = 0;
846
847 if (enable) {
848 ret = pm_runtime_resume_and_get(imx214->dev);
849 if (ret < 0)
850 return ret;
851
852 state = v4l2_subdev_lock_and_get_active_state(subdev);
853 ret = imx214_start_streaming(imx214);
854 v4l2_subdev_unlock_state(state);
855 if (ret < 0)
856 goto err_rpm_put;
857 } else {
858 ret = imx214_stop_streaming(imx214);
859 if (ret < 0)
860 goto err_rpm_put;
861 pm_runtime_put(imx214->dev);
862 }
863
864 return 0;
865
866 err_rpm_put:
867 pm_runtime_put(imx214->dev);
868 return ret;
869 }
870
imx214_get_frame_interval(struct v4l2_subdev * subdev,struct v4l2_subdev_state * sd_state,struct v4l2_subdev_frame_interval * fival)871 static int imx214_get_frame_interval(struct v4l2_subdev *subdev,
872 struct v4l2_subdev_state *sd_state,
873 struct v4l2_subdev_frame_interval *fival)
874 {
875 /*
876 * FIXME: Implement support for V4L2_SUBDEV_FORMAT_TRY, using the V4L2
877 * subdev active state API.
878 */
879 if (fival->which != V4L2_SUBDEV_FORMAT_ACTIVE)
880 return -EINVAL;
881
882 fival->interval.numerator = 1;
883 fival->interval.denominator = IMX214_FPS;
884
885 return 0;
886 }
887
imx214_enum_frame_interval(struct v4l2_subdev * subdev,struct v4l2_subdev_state * sd_state,struct v4l2_subdev_frame_interval_enum * fie)888 static int imx214_enum_frame_interval(struct v4l2_subdev *subdev,
889 struct v4l2_subdev_state *sd_state,
890 struct v4l2_subdev_frame_interval_enum *fie)
891 {
892 const struct imx214_mode *mode;
893
894 if (fie->index != 0)
895 return -EINVAL;
896
897 mode = v4l2_find_nearest_size(imx214_modes,
898 ARRAY_SIZE(imx214_modes), width, height,
899 fie->width, fie->height);
900
901 fie->code = IMX214_MBUS_CODE;
902 fie->width = mode->width;
903 fie->height = mode->height;
904 fie->interval.numerator = 1;
905 fie->interval.denominator = IMX214_FPS;
906
907 return 0;
908 }
909
910 static const struct v4l2_subdev_video_ops imx214_video_ops = {
911 .s_stream = imx214_s_stream,
912 };
913
914 static const struct v4l2_subdev_pad_ops imx214_subdev_pad_ops = {
915 .enum_mbus_code = imx214_enum_mbus_code,
916 .enum_frame_size = imx214_enum_frame_size,
917 .enum_frame_interval = imx214_enum_frame_interval,
918 .get_fmt = v4l2_subdev_get_fmt,
919 .set_fmt = imx214_set_format,
920 .get_selection = imx214_get_selection,
921 .get_frame_interval = imx214_get_frame_interval,
922 .set_frame_interval = imx214_get_frame_interval,
923 };
924
925 static const struct v4l2_subdev_ops imx214_subdev_ops = {
926 .core = &imx214_core_ops,
927 .video = &imx214_video_ops,
928 .pad = &imx214_subdev_pad_ops,
929 };
930
931 static const struct v4l2_subdev_internal_ops imx214_internal_ops = {
932 .init_state = imx214_entity_init_state,
933 };
934
imx214_get_regulators(struct device * dev,struct imx214 * imx214)935 static int imx214_get_regulators(struct device *dev, struct imx214 *imx214)
936 {
937 unsigned int i;
938
939 for (i = 0; i < IMX214_NUM_SUPPLIES; i++)
940 imx214->supplies[i].supply = imx214_supply_name[i];
941
942 return devm_regulator_bulk_get(dev, IMX214_NUM_SUPPLIES,
943 imx214->supplies);
944 }
945
imx214_parse_fwnode(struct device * dev)946 static int imx214_parse_fwnode(struct device *dev)
947 {
948 struct fwnode_handle *endpoint;
949 struct v4l2_fwnode_endpoint bus_cfg = {
950 .bus_type = V4L2_MBUS_CSI2_DPHY,
951 };
952 unsigned int i;
953 int ret;
954
955 endpoint = fwnode_graph_get_next_endpoint(dev_fwnode(dev), NULL);
956 if (!endpoint)
957 return dev_err_probe(dev, -EINVAL, "endpoint node not found\n");
958
959 ret = v4l2_fwnode_endpoint_alloc_parse(endpoint, &bus_cfg);
960 if (ret) {
961 dev_err_probe(dev, ret, "parsing endpoint node failed\n");
962 goto done;
963 }
964
965 /* Check the number of MIPI CSI2 data lanes */
966 if (bus_cfg.bus.mipi_csi2.num_data_lanes != 4) {
967 ret = dev_err_probe(dev, -EINVAL,
968 "only 4 data lanes are currently supported\n");
969 goto done;
970 }
971
972 if (bus_cfg.nr_of_link_frequencies != 1)
973 dev_warn(dev, "Only one link-frequency supported, please review your DT. Continuing anyway\n");
974
975 for (i = 0; i < bus_cfg.nr_of_link_frequencies; i++) {
976 if (bus_cfg.link_frequencies[i] == IMX214_DEFAULT_LINK_FREQ)
977 break;
978 if (bus_cfg.link_frequencies[i] ==
979 IMX214_DEFAULT_LINK_FREQ_LEGACY) {
980 dev_warn(dev,
981 "link-frequencies %d not supported, please review your DT. Continuing anyway\n",
982 IMX214_DEFAULT_LINK_FREQ);
983 break;
984 }
985 }
986
987 if (i == bus_cfg.nr_of_link_frequencies)
988 ret = dev_err_probe(dev, -EINVAL,
989 "link-frequencies %d not supported, please review your DT\n",
990 IMX214_DEFAULT_LINK_FREQ);
991
992 done:
993 v4l2_fwnode_endpoint_free(&bus_cfg);
994 fwnode_handle_put(endpoint);
995 return ret;
996 }
997
imx214_probe(struct i2c_client * client)998 static int imx214_probe(struct i2c_client *client)
999 {
1000 struct device *dev = &client->dev;
1001 struct imx214 *imx214;
1002 int ret;
1003
1004 ret = imx214_parse_fwnode(dev);
1005 if (ret)
1006 return ret;
1007
1008 imx214 = devm_kzalloc(dev, sizeof(*imx214), GFP_KERNEL);
1009 if (!imx214)
1010 return -ENOMEM;
1011
1012 imx214->dev = dev;
1013
1014 imx214->xclk = devm_clk_get(dev, NULL);
1015 if (IS_ERR(imx214->xclk))
1016 return dev_err_probe(dev, PTR_ERR(imx214->xclk),
1017 "failed to get xclk\n");
1018
1019 ret = clk_set_rate(imx214->xclk, IMX214_DEFAULT_CLK_FREQ);
1020 if (ret)
1021 return dev_err_probe(dev, ret,
1022 "failed to set xclk frequency\n");
1023
1024 ret = imx214_get_regulators(dev, imx214);
1025 if (ret < 0)
1026 return dev_err_probe(dev, ret, "failed to get regulators\n");
1027
1028 imx214->enable_gpio = devm_gpiod_get(dev, "enable", GPIOD_OUT_LOW);
1029 if (IS_ERR(imx214->enable_gpio))
1030 return dev_err_probe(dev, PTR_ERR(imx214->enable_gpio),
1031 "failed to get enable gpio\n");
1032
1033 imx214->regmap = devm_cci_regmap_init_i2c(client, 16);
1034 if (IS_ERR(imx214->regmap))
1035 return dev_err_probe(dev, PTR_ERR(imx214->regmap),
1036 "failed to initialize CCI\n");
1037
1038 v4l2_i2c_subdev_init(&imx214->sd, client, &imx214_subdev_ops);
1039 imx214->sd.internal_ops = &imx214_internal_ops;
1040
1041 /*
1042 * Enable power initially, to avoid warnings
1043 * from clk_disable on power_off
1044 */
1045 imx214_power_on(imx214->dev);
1046
1047 ret = imx214_ctrls_init(imx214);
1048 if (ret < 0)
1049 goto error_power_off;
1050
1051 imx214->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
1052 imx214->pad.flags = MEDIA_PAD_FL_SOURCE;
1053 imx214->sd.dev = &client->dev;
1054 imx214->sd.entity.function = MEDIA_ENT_F_CAM_SENSOR;
1055
1056 ret = media_entity_pads_init(&imx214->sd.entity, 1, &imx214->pad);
1057 if (ret < 0) {
1058 dev_err_probe(dev, ret, "failed to init entity pads\n");
1059 goto free_ctrl;
1060 }
1061
1062 imx214->sd.state_lock = imx214->ctrls.lock;
1063 ret = v4l2_subdev_init_finalize(&imx214->sd);
1064 if (ret < 0) {
1065 dev_err_probe(dev, ret, "subdev init error\n");
1066 goto free_entity;
1067 }
1068
1069 pm_runtime_set_active(imx214->dev);
1070 pm_runtime_enable(imx214->dev);
1071
1072 ret = v4l2_async_register_subdev_sensor(&imx214->sd);
1073 if (ret < 0) {
1074 dev_err_probe(dev, ret,
1075 "failed to register sensor sub-device\n");
1076 goto error_subdev_cleanup;
1077 }
1078
1079 pm_runtime_idle(imx214->dev);
1080
1081 return 0;
1082
1083 error_subdev_cleanup:
1084 pm_runtime_disable(imx214->dev);
1085 pm_runtime_set_suspended(&client->dev);
1086 v4l2_subdev_cleanup(&imx214->sd);
1087
1088 free_entity:
1089 media_entity_cleanup(&imx214->sd.entity);
1090
1091 free_ctrl:
1092 v4l2_ctrl_handler_free(&imx214->ctrls);
1093
1094 error_power_off:
1095 imx214_power_off(imx214->dev);
1096
1097 return ret;
1098 }
1099
imx214_remove(struct i2c_client * client)1100 static void imx214_remove(struct i2c_client *client)
1101 {
1102 struct v4l2_subdev *sd = i2c_get_clientdata(client);
1103 struct imx214 *imx214 = to_imx214(sd);
1104
1105 v4l2_async_unregister_subdev(&imx214->sd);
1106 v4l2_subdev_cleanup(sd);
1107 media_entity_cleanup(&imx214->sd.entity);
1108 v4l2_ctrl_handler_free(&imx214->ctrls);
1109 pm_runtime_disable(&client->dev);
1110 if (!pm_runtime_status_suspended(&client->dev)) {
1111 imx214_power_off(imx214->dev);
1112 pm_runtime_set_suspended(&client->dev);
1113 }
1114 }
1115
1116 static const struct of_device_id imx214_of_match[] = {
1117 { .compatible = "sony,imx214" },
1118 { }
1119 };
1120 MODULE_DEVICE_TABLE(of, imx214_of_match);
1121
1122 static const struct dev_pm_ops imx214_pm_ops = {
1123 SET_RUNTIME_PM_OPS(imx214_power_off, imx214_power_on, NULL)
1124 };
1125
1126 static struct i2c_driver imx214_i2c_driver = {
1127 .driver = {
1128 .of_match_table = imx214_of_match,
1129 .pm = &imx214_pm_ops,
1130 .name = "imx214",
1131 },
1132 .probe = imx214_probe,
1133 .remove = imx214_remove,
1134 };
1135
1136 module_i2c_driver(imx214_i2c_driver);
1137
1138 MODULE_DESCRIPTION("Sony IMX214 Camera driver");
1139 MODULE_AUTHOR("Ricardo Ribalda <ribalda@kernel.org>");
1140 MODULE_LICENSE("GPL v2");
1141