1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * tc358743 - Toshiba HDMI to CSI-2 bridge
4 *
5 * Copyright 2015 Cisco Systems, Inc. and/or its affiliates. All rights
6 * reserved.
7 */
8
9 /*
10 * References (c = chapter, p = page):
11 * REF_01 - Toshiba, TC358743XBG (H2C), Functional Specification, Rev 0.60
12 * REF_02 - Toshiba, TC358743XBG_HDMI-CSI_Tv11p_nm.xls
13 */
14
15 #include <linux/kernel.h>
16 #include <linux/module.h>
17 #include <linux/slab.h>
18 #include <linux/i2c.h>
19 #include <linux/clk.h>
20 #include <linux/delay.h>
21 #include <linux/gpio/consumer.h>
22 #include <linux/interrupt.h>
23 #include <linux/timer.h>
24 #include <linux/of_graph.h>
25 #include <linux/videodev2.h>
26 #include <linux/workqueue.h>
27 #include <linux/v4l2-dv-timings.h>
28 #include <linux/hdmi.h>
29 #include <media/cec.h>
30 #include <media/v4l2-dv-timings.h>
31 #include <media/v4l2-device.h>
32 #include <media/v4l2-ctrls.h>
33 #include <media/v4l2-event.h>
34 #include <media/v4l2-fwnode.h>
35 #include <media/i2c/tc358743.h>
36
37 #include "tc358743_regs.h"
38
39 static int debug;
40 module_param(debug, int, 0644);
41 MODULE_PARM_DESC(debug, "debug level (0-3)");
42
43 MODULE_DESCRIPTION("Toshiba TC358743 HDMI to CSI-2 bridge driver");
44 MODULE_AUTHOR("Ramakrishnan Muthukrishnan <ram@rkrishnan.org>");
45 MODULE_AUTHOR("Mikhail Khelik <mkhelik@cisco.com>");
46 MODULE_AUTHOR("Mats Randgaard <matrandg@cisco.com>");
47 MODULE_LICENSE("GPL");
48
49 #define EDID_NUM_BLOCKS_MAX 8
50 #define EDID_BLOCK_SIZE 128
51
52 #define I2C_MAX_XFER_SIZE (EDID_BLOCK_SIZE + 2)
53
54 #define POLL_INTERVAL_CEC_MS 10
55 #define POLL_INTERVAL_MS 1000
56
57 static const struct v4l2_dv_timings_cap tc358743_timings_cap = {
58 .type = V4L2_DV_BT_656_1120,
59 /* keep this initialization for compatibility with GCC < 4.4.6 */
60 .reserved = { 0 },
61 /* Pixel clock from REF_01 p. 20. Min/max height/width are unknown */
62 V4L2_INIT_BT_TIMINGS(640, 1920, 350, 1200, 13000000, 165000000,
63 V4L2_DV_BT_STD_CEA861 | V4L2_DV_BT_STD_DMT |
64 V4L2_DV_BT_STD_GTF | V4L2_DV_BT_STD_CVT,
65 V4L2_DV_BT_CAP_PROGRESSIVE |
66 V4L2_DV_BT_CAP_REDUCED_BLANKING |
67 V4L2_DV_BT_CAP_CUSTOM)
68 };
69
70 struct tc358743_state {
71 struct tc358743_platform_data pdata;
72 struct v4l2_mbus_config_mipi_csi2 bus;
73 struct v4l2_subdev sd;
74 struct media_pad pad;
75 struct v4l2_ctrl_handler hdl;
76 struct i2c_client *i2c_client;
77 /* CONFCTL is modified in ops and tc358743_hdmi_sys_int_handler */
78 struct mutex confctl_mutex;
79
80 /* controls */
81 struct v4l2_ctrl *detect_tx_5v_ctrl;
82 struct v4l2_ctrl *audio_sampling_rate_ctrl;
83 struct v4l2_ctrl *audio_present_ctrl;
84
85 struct delayed_work delayed_work_enable_hotplug;
86
87 struct timer_list timer;
88 struct work_struct work_i2c_poll;
89
90 /* edid */
91 u8 edid_blocks_written;
92
93 struct v4l2_dv_timings timings;
94 u32 mbus_fmt_code;
95 u8 csi_lanes_in_use;
96
97 struct gpio_desc *reset_gpio;
98
99 struct cec_adapter *cec_adap;
100 };
101
102 static void tc358743_enable_interrupts(struct v4l2_subdev *sd,
103 bool cable_connected);
104 static int tc358743_s_ctrl_detect_tx_5v(struct v4l2_subdev *sd);
105
to_state(struct v4l2_subdev * sd)106 static inline struct tc358743_state *to_state(struct v4l2_subdev *sd)
107 {
108 return container_of(sd, struct tc358743_state, sd);
109 }
110
111 /* --------------- I2C --------------- */
112
i2c_rd(struct v4l2_subdev * sd,u16 reg,u8 * values,u32 n)113 static int i2c_rd(struct v4l2_subdev *sd, u16 reg, u8 *values, u32 n)
114 {
115 struct tc358743_state *state = to_state(sd);
116 struct i2c_client *client = state->i2c_client;
117 int err;
118 u8 buf[2] = { reg >> 8, reg & 0xff };
119 struct i2c_msg msgs[] = {
120 {
121 .addr = client->addr,
122 .flags = 0,
123 .len = 2,
124 .buf = buf,
125 },
126 {
127 .addr = client->addr,
128 .flags = I2C_M_RD,
129 .len = n,
130 .buf = values,
131 },
132 };
133
134 err = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs));
135 if (err != ARRAY_SIZE(msgs)) {
136 v4l2_err(sd, "%s: reading register 0x%x from 0x%x failed: %d\n",
137 __func__, reg, client->addr, err);
138 }
139 return err != ARRAY_SIZE(msgs);
140 }
141
i2c_wr(struct v4l2_subdev * sd,u16 reg,u8 * values,u32 n)142 static void i2c_wr(struct v4l2_subdev *sd, u16 reg, u8 *values, u32 n)
143 {
144 struct tc358743_state *state = to_state(sd);
145 struct i2c_client *client = state->i2c_client;
146 int err, i;
147 struct i2c_msg msg;
148 u8 data[I2C_MAX_XFER_SIZE];
149
150 if ((2 + n) > I2C_MAX_XFER_SIZE) {
151 n = I2C_MAX_XFER_SIZE - 2;
152 v4l2_warn(sd, "i2c wr reg=%04x: len=%d is too big!\n",
153 reg, 2 + n);
154 }
155
156 msg.addr = client->addr;
157 msg.buf = data;
158 msg.len = 2 + n;
159 msg.flags = 0;
160
161 data[0] = reg >> 8;
162 data[1] = reg & 0xff;
163
164 for (i = 0; i < n; i++)
165 data[2 + i] = values[i];
166
167 err = i2c_transfer(client->adapter, &msg, 1);
168 if (err != 1) {
169 v4l2_err(sd, "%s: writing register 0x%x from 0x%x failed: %d\n",
170 __func__, reg, client->addr, err);
171 return;
172 }
173
174 if (debug < 3)
175 return;
176
177 switch (n) {
178 case 1:
179 v4l2_info(sd, "I2C write 0x%04x = 0x%02x",
180 reg, data[2]);
181 break;
182 case 2:
183 v4l2_info(sd, "I2C write 0x%04x = 0x%02x%02x",
184 reg, data[3], data[2]);
185 break;
186 case 4:
187 v4l2_info(sd, "I2C write 0x%04x = 0x%02x%02x%02x%02x",
188 reg, data[5], data[4], data[3], data[2]);
189 break;
190 default:
191 v4l2_info(sd, "I2C write %d bytes from address 0x%04x\n",
192 n, reg);
193 }
194 }
195
i2c_rdreg_err(struct v4l2_subdev * sd,u16 reg,u32 n,int * err)196 static noinline u32 i2c_rdreg_err(struct v4l2_subdev *sd, u16 reg, u32 n,
197 int *err)
198 {
199 int error;
200 __le32 val = 0;
201
202 error = i2c_rd(sd, reg, (u8 __force *)&val, n);
203 if (err)
204 *err = error;
205
206 return le32_to_cpu(val);
207 }
208
i2c_rdreg(struct v4l2_subdev * sd,u16 reg,u32 n)209 static inline u32 i2c_rdreg(struct v4l2_subdev *sd, u16 reg, u32 n)
210 {
211 return i2c_rdreg_err(sd, reg, n, NULL);
212 }
213
i2c_wrreg(struct v4l2_subdev * sd,u16 reg,u32 val,u32 n)214 static noinline void i2c_wrreg(struct v4l2_subdev *sd, u16 reg, u32 val, u32 n)
215 {
216 __le32 raw = cpu_to_le32(val);
217
218 i2c_wr(sd, reg, (u8 __force *)&raw, n);
219 }
220
i2c_rd8(struct v4l2_subdev * sd,u16 reg)221 static u8 i2c_rd8(struct v4l2_subdev *sd, u16 reg)
222 {
223 return i2c_rdreg(sd, reg, 1);
224 }
225
i2c_wr8(struct v4l2_subdev * sd,u16 reg,u8 val)226 static void i2c_wr8(struct v4l2_subdev *sd, u16 reg, u8 val)
227 {
228 i2c_wrreg(sd, reg, val, 1);
229 }
230
i2c_wr8_and_or(struct v4l2_subdev * sd,u16 reg,u8 mask,u8 val)231 static void i2c_wr8_and_or(struct v4l2_subdev *sd, u16 reg,
232 u8 mask, u8 val)
233 {
234 i2c_wrreg(sd, reg, (i2c_rdreg(sd, reg, 1) & mask) | val, 1);
235 }
236
i2c_rd16(struct v4l2_subdev * sd,u16 reg)237 static u16 i2c_rd16(struct v4l2_subdev *sd, u16 reg)
238 {
239 return i2c_rdreg(sd, reg, 2);
240 }
241
i2c_rd16_err(struct v4l2_subdev * sd,u16 reg,u16 * value)242 static int i2c_rd16_err(struct v4l2_subdev *sd, u16 reg, u16 *value)
243 {
244 int err;
245 *value = i2c_rdreg_err(sd, reg, 2, &err);
246 return err;
247 }
248
i2c_wr16(struct v4l2_subdev * sd,u16 reg,u16 val)249 static void i2c_wr16(struct v4l2_subdev *sd, u16 reg, u16 val)
250 {
251 i2c_wrreg(sd, reg, val, 2);
252 }
253
i2c_wr16_and_or(struct v4l2_subdev * sd,u16 reg,u16 mask,u16 val)254 static void i2c_wr16_and_or(struct v4l2_subdev *sd, u16 reg, u16 mask, u16 val)
255 {
256 i2c_wrreg(sd, reg, (i2c_rdreg(sd, reg, 2) & mask) | val, 2);
257 }
258
i2c_rd32(struct v4l2_subdev * sd,u16 reg)259 static u32 i2c_rd32(struct v4l2_subdev *sd, u16 reg)
260 {
261 return i2c_rdreg(sd, reg, 4);
262 }
263
i2c_wr32(struct v4l2_subdev * sd,u16 reg,u32 val)264 static void i2c_wr32(struct v4l2_subdev *sd, u16 reg, u32 val)
265 {
266 i2c_wrreg(sd, reg, val, 4);
267 }
268
269 /* --------------- STATUS --------------- */
270
is_hdmi(struct v4l2_subdev * sd)271 static inline bool is_hdmi(struct v4l2_subdev *sd)
272 {
273 return i2c_rd8(sd, SYS_STATUS) & MASK_S_HDMI;
274 }
275
tx_5v_power_present(struct v4l2_subdev * sd)276 static inline bool tx_5v_power_present(struct v4l2_subdev *sd)
277 {
278 return i2c_rd8(sd, SYS_STATUS) & MASK_S_DDC5V;
279 }
280
no_signal(struct v4l2_subdev * sd)281 static inline bool no_signal(struct v4l2_subdev *sd)
282 {
283 return !(i2c_rd8(sd, SYS_STATUS) & MASK_S_TMDS);
284 }
285
no_sync(struct v4l2_subdev * sd)286 static inline bool no_sync(struct v4l2_subdev *sd)
287 {
288 return !(i2c_rd8(sd, SYS_STATUS) & MASK_S_SYNC);
289 }
290
audio_present(struct v4l2_subdev * sd)291 static inline bool audio_present(struct v4l2_subdev *sd)
292 {
293 return i2c_rd8(sd, AU_STATUS0) & MASK_S_A_SAMPLE;
294 }
295
get_audio_sampling_rate(struct v4l2_subdev * sd)296 static int get_audio_sampling_rate(struct v4l2_subdev *sd)
297 {
298 static const int code_to_rate[] = {
299 44100, 0, 48000, 32000, 22050, 384000, 24000, 352800,
300 88200, 768000, 96000, 705600, 176400, 0, 192000, 0
301 };
302
303 /* Register FS_SET is not cleared when the cable is disconnected */
304 if (no_signal(sd))
305 return 0;
306
307 return code_to_rate[i2c_rd8(sd, FS_SET) & MASK_FS];
308 }
309
310 /* --------------- TIMINGS --------------- */
311
fps(const struct v4l2_bt_timings * t)312 static inline unsigned fps(const struct v4l2_bt_timings *t)
313 {
314 if (!V4L2_DV_BT_FRAME_HEIGHT(t) || !V4L2_DV_BT_FRAME_WIDTH(t))
315 return 0;
316
317 return DIV_ROUND_CLOSEST((unsigned)t->pixelclock,
318 V4L2_DV_BT_FRAME_HEIGHT(t) * V4L2_DV_BT_FRAME_WIDTH(t));
319 }
320
tc358743_get_detected_timings(struct v4l2_subdev * sd,struct v4l2_dv_timings * timings)321 static int tc358743_get_detected_timings(struct v4l2_subdev *sd,
322 struct v4l2_dv_timings *timings)
323 {
324 struct v4l2_bt_timings *bt = &timings->bt;
325 unsigned width, height, frame_width, frame_height, frame_interval, fps;
326
327 memset(timings, 0, sizeof(struct v4l2_dv_timings));
328
329 if (no_signal(sd)) {
330 v4l2_dbg(1, debug, sd, "%s: no valid signal\n", __func__);
331 return -ENOLINK;
332 }
333 if (no_sync(sd)) {
334 v4l2_dbg(1, debug, sd, "%s: no sync on signal\n", __func__);
335 return -ENOLCK;
336 }
337
338 timings->type = V4L2_DV_BT_656_1120;
339 bt->interlaced = i2c_rd8(sd, VI_STATUS1) & MASK_S_V_INTERLACE ?
340 V4L2_DV_INTERLACED : V4L2_DV_PROGRESSIVE;
341
342 width = ((i2c_rd8(sd, DE_WIDTH_H_HI) & 0x1f) << 8) +
343 i2c_rd8(sd, DE_WIDTH_H_LO);
344 height = ((i2c_rd8(sd, DE_WIDTH_V_HI) & 0x1f) << 8) +
345 i2c_rd8(sd, DE_WIDTH_V_LO);
346 frame_width = ((i2c_rd8(sd, H_SIZE_HI) & 0x1f) << 8) +
347 i2c_rd8(sd, H_SIZE_LO);
348 frame_height = (((i2c_rd8(sd, V_SIZE_HI) & 0x3f) << 8) +
349 i2c_rd8(sd, V_SIZE_LO)) / 2;
350 /* frame interval in milliseconds * 10
351 * Require SYS_FREQ0 and SYS_FREQ1 are precisely set */
352 frame_interval = ((i2c_rd8(sd, FV_CNT_HI) & 0x3) << 8) +
353 i2c_rd8(sd, FV_CNT_LO);
354 fps = (frame_interval > 0) ?
355 DIV_ROUND_CLOSEST(10000, frame_interval) : 0;
356
357 bt->width = width;
358 bt->height = height;
359 bt->vsync = frame_height - height;
360 bt->hsync = frame_width - width;
361 bt->pixelclock = frame_width * frame_height * fps;
362 if (bt->interlaced == V4L2_DV_INTERLACED) {
363 bt->height *= 2;
364 bt->il_vsync = bt->vsync + 1;
365 bt->pixelclock /= 2;
366 }
367
368 return 0;
369 }
370
371 /* --------------- HOTPLUG / HDCP / EDID --------------- */
372
tc358743_delayed_work_enable_hotplug(struct work_struct * work)373 static void tc358743_delayed_work_enable_hotplug(struct work_struct *work)
374 {
375 struct delayed_work *dwork = to_delayed_work(work);
376 struct tc358743_state *state = container_of(dwork,
377 struct tc358743_state, delayed_work_enable_hotplug);
378 struct v4l2_subdev *sd = &state->sd;
379
380 v4l2_dbg(2, debug, sd, "%s:\n", __func__);
381
382 i2c_wr8_and_or(sd, HPD_CTL, ~MASK_HPD_OUT0, MASK_HPD_OUT0);
383 }
384
tc358743_set_hdmi_hdcp(struct v4l2_subdev * sd,bool enable)385 static void tc358743_set_hdmi_hdcp(struct v4l2_subdev *sd, bool enable)
386 {
387 v4l2_dbg(2, debug, sd, "%s: %s\n", __func__, enable ?
388 "enable" : "disable");
389
390 if (enable) {
391 i2c_wr8_and_or(sd, HDCP_REG3, ~KEY_RD_CMD, KEY_RD_CMD);
392
393 i2c_wr8_and_or(sd, HDCP_MODE, ~MASK_MANUAL_AUTHENTICATION, 0);
394
395 i2c_wr8_and_or(sd, HDCP_REG1, 0xff,
396 MASK_AUTH_UNAUTH_SEL_16_FRAMES |
397 MASK_AUTH_UNAUTH_AUTO);
398
399 i2c_wr8_and_or(sd, HDCP_REG2, ~MASK_AUTO_P3_RESET,
400 SET_AUTO_P3_RESET_FRAMES(0x0f));
401 } else {
402 i2c_wr8_and_or(sd, HDCP_MODE, ~MASK_MANUAL_AUTHENTICATION,
403 MASK_MANUAL_AUTHENTICATION);
404 }
405 }
406
tc358743_disable_edid(struct v4l2_subdev * sd)407 static void tc358743_disable_edid(struct v4l2_subdev *sd)
408 {
409 struct tc358743_state *state = to_state(sd);
410
411 v4l2_dbg(2, debug, sd, "%s:\n", __func__);
412
413 cancel_delayed_work_sync(&state->delayed_work_enable_hotplug);
414
415 /* DDC access to EDID is also disabled when hotplug is disabled. See
416 * register DDC_CTL */
417 i2c_wr8_and_or(sd, HPD_CTL, ~MASK_HPD_OUT0, 0x0);
418 }
419
tc358743_enable_edid(struct v4l2_subdev * sd)420 static void tc358743_enable_edid(struct v4l2_subdev *sd)
421 {
422 struct tc358743_state *state = to_state(sd);
423
424 if (state->edid_blocks_written == 0) {
425 v4l2_dbg(2, debug, sd, "%s: no EDID -> no hotplug\n", __func__);
426 tc358743_s_ctrl_detect_tx_5v(sd);
427 return;
428 }
429
430 v4l2_dbg(2, debug, sd, "%s:\n", __func__);
431
432 /* Enable hotplug after 100 ms. DDC access to EDID is also enabled when
433 * hotplug is enabled. See register DDC_CTL */
434 schedule_delayed_work(&state->delayed_work_enable_hotplug, HZ / 10);
435
436 tc358743_enable_interrupts(sd, true);
437 tc358743_s_ctrl_detect_tx_5v(sd);
438 }
439
tc358743_erase_bksv(struct v4l2_subdev * sd)440 static void tc358743_erase_bksv(struct v4l2_subdev *sd)
441 {
442 int i;
443
444 for (i = 0; i < 5; i++)
445 i2c_wr8(sd, BKSV + i, 0);
446 }
447
448 /* --------------- AVI infoframe --------------- */
449
print_avi_infoframe(struct v4l2_subdev * sd)450 static void print_avi_infoframe(struct v4l2_subdev *sd)
451 {
452 struct i2c_client *client = v4l2_get_subdevdata(sd);
453 struct device *dev = &client->dev;
454 union hdmi_infoframe frame;
455 u8 buffer[HDMI_INFOFRAME_SIZE(AVI)];
456
457 if (!is_hdmi(sd)) {
458 v4l2_info(sd, "DVI-D signal - AVI infoframe not supported\n");
459 return;
460 }
461
462 i2c_rd(sd, PK_AVI_0HEAD, buffer, HDMI_INFOFRAME_SIZE(AVI));
463
464 if (hdmi_infoframe_unpack(&frame, buffer, sizeof(buffer)) < 0) {
465 v4l2_err(sd, "%s: unpack of AVI infoframe failed\n", __func__);
466 return;
467 }
468
469 hdmi_infoframe_log(KERN_INFO, dev, &frame);
470 }
471
472 /* --------------- CTRLS --------------- */
473
tc358743_s_ctrl_detect_tx_5v(struct v4l2_subdev * sd)474 static int tc358743_s_ctrl_detect_tx_5v(struct v4l2_subdev *sd)
475 {
476 struct tc358743_state *state = to_state(sd);
477
478 return v4l2_ctrl_s_ctrl(state->detect_tx_5v_ctrl,
479 tx_5v_power_present(sd));
480 }
481
tc358743_s_ctrl_audio_sampling_rate(struct v4l2_subdev * sd)482 static int tc358743_s_ctrl_audio_sampling_rate(struct v4l2_subdev *sd)
483 {
484 struct tc358743_state *state = to_state(sd);
485
486 return v4l2_ctrl_s_ctrl(state->audio_sampling_rate_ctrl,
487 get_audio_sampling_rate(sd));
488 }
489
tc358743_s_ctrl_audio_present(struct v4l2_subdev * sd)490 static int tc358743_s_ctrl_audio_present(struct v4l2_subdev *sd)
491 {
492 struct tc358743_state *state = to_state(sd);
493
494 return v4l2_ctrl_s_ctrl(state->audio_present_ctrl,
495 audio_present(sd));
496 }
497
tc358743_update_controls(struct v4l2_subdev * sd)498 static int tc358743_update_controls(struct v4l2_subdev *sd)
499 {
500 int ret = 0;
501
502 ret |= tc358743_s_ctrl_detect_tx_5v(sd);
503 ret |= tc358743_s_ctrl_audio_sampling_rate(sd);
504 ret |= tc358743_s_ctrl_audio_present(sd);
505
506 return ret;
507 }
508
509 /* --------------- INIT --------------- */
510
tc358743_reset_phy(struct v4l2_subdev * sd)511 static void tc358743_reset_phy(struct v4l2_subdev *sd)
512 {
513 v4l2_dbg(1, debug, sd, "%s:\n", __func__);
514
515 i2c_wr8_and_or(sd, PHY_RST, ~MASK_RESET_CTRL, 0);
516 i2c_wr8_and_or(sd, PHY_RST, ~MASK_RESET_CTRL, MASK_RESET_CTRL);
517 }
518
tc358743_reset(struct v4l2_subdev * sd,uint16_t mask)519 static void tc358743_reset(struct v4l2_subdev *sd, uint16_t mask)
520 {
521 u16 sysctl = i2c_rd16(sd, SYSCTL);
522
523 i2c_wr16(sd, SYSCTL, sysctl | mask);
524 i2c_wr16(sd, SYSCTL, sysctl & ~mask);
525 }
526
tc358743_sleep_mode(struct v4l2_subdev * sd,bool enable)527 static inline void tc358743_sleep_mode(struct v4l2_subdev *sd, bool enable)
528 {
529 i2c_wr16_and_or(sd, SYSCTL, ~MASK_SLEEP,
530 enable ? MASK_SLEEP : 0);
531 }
532
enable_stream(struct v4l2_subdev * sd,bool enable)533 static inline void enable_stream(struct v4l2_subdev *sd, bool enable)
534 {
535 struct tc358743_state *state = to_state(sd);
536
537 v4l2_dbg(3, debug, sd, "%s: %sable\n",
538 __func__, enable ? "en" : "dis");
539
540 if (enable) {
541 /* It is critical for CSI receiver to see lane transition
542 * LP11->HS. Set to non-continuous mode to enable clock lane
543 * LP11 state. */
544 i2c_wr32(sd, TXOPTIONCNTRL, 0);
545 /* Set to continuous mode to trigger LP11->HS transition */
546 i2c_wr32(sd, TXOPTIONCNTRL, MASK_CONTCLKMODE);
547 /* Unmute video */
548 i2c_wr8(sd, VI_MUTE, MASK_AUTO_MUTE);
549 } else {
550 /* Mute video so that all data lanes go to LSP11 state.
551 * No data is output to CSI Tx block. */
552 i2c_wr8(sd, VI_MUTE, MASK_AUTO_MUTE | MASK_VI_MUTE);
553 }
554
555 mutex_lock(&state->confctl_mutex);
556 i2c_wr16_and_or(sd, CONFCTL, ~(MASK_VBUFEN | MASK_ABUFEN),
557 enable ? (MASK_VBUFEN | MASK_ABUFEN) : 0x0);
558 mutex_unlock(&state->confctl_mutex);
559 }
560
tc358743_set_pll(struct v4l2_subdev * sd)561 static void tc358743_set_pll(struct v4l2_subdev *sd)
562 {
563 struct tc358743_state *state = to_state(sd);
564 struct tc358743_platform_data *pdata = &state->pdata;
565 u16 pllctl0 = i2c_rd16(sd, PLLCTL0);
566 u16 pllctl1 = i2c_rd16(sd, PLLCTL1);
567 u16 pllctl0_new = SET_PLL_PRD(pdata->pll_prd) |
568 SET_PLL_FBD(pdata->pll_fbd);
569 u32 hsck = (pdata->refclk_hz / pdata->pll_prd) * pdata->pll_fbd;
570
571 v4l2_dbg(2, debug, sd, "%s:\n", __func__);
572
573 /* Only rewrite when needed (new value or disabled), since rewriting
574 * triggers another format change event. */
575 if ((pllctl0 != pllctl0_new) || ((pllctl1 & MASK_PLL_EN) == 0)) {
576 u16 pll_frs;
577
578 if (hsck > 500000000)
579 pll_frs = 0x0;
580 else if (hsck > 250000000)
581 pll_frs = 0x1;
582 else if (hsck > 125000000)
583 pll_frs = 0x2;
584 else
585 pll_frs = 0x3;
586
587 v4l2_dbg(1, debug, sd, "%s: updating PLL clock\n", __func__);
588 tc358743_sleep_mode(sd, true);
589 i2c_wr16(sd, PLLCTL0, pllctl0_new);
590 i2c_wr16_and_or(sd, PLLCTL1,
591 ~(MASK_PLL_FRS | MASK_RESETB | MASK_PLL_EN),
592 (SET_PLL_FRS(pll_frs) | MASK_RESETB |
593 MASK_PLL_EN));
594 udelay(10); /* REF_02, Sheet "Source HDMI" */
595 i2c_wr16_and_or(sd, PLLCTL1, ~MASK_CKEN, MASK_CKEN);
596 tc358743_sleep_mode(sd, false);
597 }
598 }
599
tc358743_set_ref_clk(struct v4l2_subdev * sd)600 static void tc358743_set_ref_clk(struct v4l2_subdev *sd)
601 {
602 struct tc358743_state *state = to_state(sd);
603 struct tc358743_platform_data *pdata = &state->pdata;
604 u32 sys_freq;
605 u32 lockdet_ref;
606 u32 cec_freq;
607 u16 fh_min;
608 u16 fh_max;
609
610 BUG_ON(!(pdata->refclk_hz == 26000000 ||
611 pdata->refclk_hz == 27000000 ||
612 pdata->refclk_hz == 42000000));
613
614 sys_freq = pdata->refclk_hz / 10000;
615 i2c_wr8(sd, SYS_FREQ0, sys_freq & 0x00ff);
616 i2c_wr8(sd, SYS_FREQ1, (sys_freq & 0xff00) >> 8);
617
618 i2c_wr8_and_or(sd, PHY_CTL0, ~MASK_PHY_SYSCLK_IND,
619 (pdata->refclk_hz == 42000000) ?
620 MASK_PHY_SYSCLK_IND : 0x0);
621
622 fh_min = pdata->refclk_hz / 100000;
623 i2c_wr8(sd, FH_MIN0, fh_min & 0x00ff);
624 i2c_wr8(sd, FH_MIN1, (fh_min & 0xff00) >> 8);
625
626 fh_max = (fh_min * 66) / 10;
627 i2c_wr8(sd, FH_MAX0, fh_max & 0x00ff);
628 i2c_wr8(sd, FH_MAX1, (fh_max & 0xff00) >> 8);
629
630 lockdet_ref = pdata->refclk_hz / 100;
631 i2c_wr8(sd, LOCKDET_REF0, lockdet_ref & 0x0000ff);
632 i2c_wr8(sd, LOCKDET_REF1, (lockdet_ref & 0x00ff00) >> 8);
633 i2c_wr8(sd, LOCKDET_REF2, (lockdet_ref & 0x0f0000) >> 16);
634
635 i2c_wr8_and_or(sd, NCO_F0_MOD, ~MASK_NCO_F0_MOD,
636 (pdata->refclk_hz == 27000000) ?
637 MASK_NCO_F0_MOD_27MHZ : 0x0);
638
639 /*
640 * Trial and error suggests that the default register value
641 * of 656 is for a 42 MHz reference clock. Use that to derive
642 * a new value based on the actual reference clock.
643 */
644 cec_freq = (656 * sys_freq) / 4200;
645 i2c_wr16(sd, CECHCLK, cec_freq);
646 i2c_wr16(sd, CECLCLK, cec_freq);
647 }
648
tc358743_set_csi_color_space(struct v4l2_subdev * sd)649 static void tc358743_set_csi_color_space(struct v4l2_subdev *sd)
650 {
651 struct tc358743_state *state = to_state(sd);
652
653 switch (state->mbus_fmt_code) {
654 case MEDIA_BUS_FMT_UYVY8_1X16:
655 v4l2_dbg(2, debug, sd, "%s: YCbCr 422 16-bit\n", __func__);
656 i2c_wr8_and_or(sd, VOUT_SET2,
657 ~(MASK_SEL422 | MASK_VOUT_422FIL_100) & 0xff,
658 MASK_SEL422 | MASK_VOUT_422FIL_100);
659 i2c_wr8_and_or(sd, VI_REP, ~MASK_VOUT_COLOR_SEL & 0xff,
660 MASK_VOUT_COLOR_601_YCBCR_LIMITED);
661 mutex_lock(&state->confctl_mutex);
662 i2c_wr16_and_or(sd, CONFCTL, ~MASK_YCBCRFMT,
663 MASK_YCBCRFMT_422_8_BIT);
664 mutex_unlock(&state->confctl_mutex);
665 break;
666 case MEDIA_BUS_FMT_RGB888_1X24:
667 v4l2_dbg(2, debug, sd, "%s: RGB 888 24-bit\n", __func__);
668 i2c_wr8_and_or(sd, VOUT_SET2,
669 ~(MASK_SEL422 | MASK_VOUT_422FIL_100) & 0xff,
670 0x00);
671 i2c_wr8_and_or(sd, VI_REP, ~MASK_VOUT_COLOR_SEL & 0xff,
672 MASK_VOUT_COLOR_RGB_FULL);
673 mutex_lock(&state->confctl_mutex);
674 i2c_wr16_and_or(sd, CONFCTL, ~MASK_YCBCRFMT, 0);
675 mutex_unlock(&state->confctl_mutex);
676 break;
677 default:
678 v4l2_dbg(2, debug, sd, "%s: Unsupported format code 0x%x\n",
679 __func__, state->mbus_fmt_code);
680 }
681 }
682
tc358743_num_csi_lanes_needed(struct v4l2_subdev * sd)683 static unsigned tc358743_num_csi_lanes_needed(struct v4l2_subdev *sd)
684 {
685 struct tc358743_state *state = to_state(sd);
686 struct v4l2_bt_timings *bt = &state->timings.bt;
687 struct tc358743_platform_data *pdata = &state->pdata;
688 u32 bits_pr_pixel =
689 (state->mbus_fmt_code == MEDIA_BUS_FMT_UYVY8_1X16) ? 16 : 24;
690 u32 bps = bt->width * bt->height * fps(bt) * bits_pr_pixel;
691 u32 bps_pr_lane = (pdata->refclk_hz / pdata->pll_prd) * pdata->pll_fbd;
692
693 return DIV_ROUND_UP(bps, bps_pr_lane);
694 }
695
tc358743_set_csi(struct v4l2_subdev * sd)696 static void tc358743_set_csi(struct v4l2_subdev *sd)
697 {
698 struct tc358743_state *state = to_state(sd);
699 struct tc358743_platform_data *pdata = &state->pdata;
700 unsigned lanes = tc358743_num_csi_lanes_needed(sd);
701
702 v4l2_dbg(3, debug, sd, "%s:\n", __func__);
703
704 state->csi_lanes_in_use = lanes;
705
706 tc358743_reset(sd, MASK_CTXRST);
707
708 if (lanes < 1)
709 i2c_wr32(sd, CLW_CNTRL, MASK_CLW_LANEDISABLE);
710 if (lanes < 1)
711 i2c_wr32(sd, D0W_CNTRL, MASK_D0W_LANEDISABLE);
712 if (lanes < 2)
713 i2c_wr32(sd, D1W_CNTRL, MASK_D1W_LANEDISABLE);
714 if (lanes < 3)
715 i2c_wr32(sd, D2W_CNTRL, MASK_D2W_LANEDISABLE);
716 if (lanes < 4)
717 i2c_wr32(sd, D3W_CNTRL, MASK_D3W_LANEDISABLE);
718
719 i2c_wr32(sd, LINEINITCNT, pdata->lineinitcnt);
720 i2c_wr32(sd, LPTXTIMECNT, pdata->lptxtimecnt);
721 i2c_wr32(sd, TCLK_HEADERCNT, pdata->tclk_headercnt);
722 i2c_wr32(sd, TCLK_TRAILCNT, pdata->tclk_trailcnt);
723 i2c_wr32(sd, THS_HEADERCNT, pdata->ths_headercnt);
724 i2c_wr32(sd, TWAKEUP, pdata->twakeup);
725 i2c_wr32(sd, TCLK_POSTCNT, pdata->tclk_postcnt);
726 i2c_wr32(sd, THS_TRAILCNT, pdata->ths_trailcnt);
727 i2c_wr32(sd, HSTXVREGCNT, pdata->hstxvregcnt);
728
729 i2c_wr32(sd, HSTXVREGEN,
730 ((lanes > 0) ? MASK_CLM_HSTXVREGEN : 0x0) |
731 ((lanes > 0) ? MASK_D0M_HSTXVREGEN : 0x0) |
732 ((lanes > 1) ? MASK_D1M_HSTXVREGEN : 0x0) |
733 ((lanes > 2) ? MASK_D2M_HSTXVREGEN : 0x0) |
734 ((lanes > 3) ? MASK_D3M_HSTXVREGEN : 0x0));
735
736 i2c_wr32(sd, TXOPTIONCNTRL, (state->bus.flags &
737 V4L2_MBUS_CSI2_NONCONTINUOUS_CLOCK) ? 0 : MASK_CONTCLKMODE);
738 i2c_wr32(sd, STARTCNTRL, MASK_START);
739 i2c_wr32(sd, CSI_START, MASK_STRT);
740
741 i2c_wr32(sd, CSI_CONFW, MASK_MODE_SET |
742 MASK_ADDRESS_CSI_CONTROL |
743 MASK_CSI_MODE |
744 MASK_TXHSMD |
745 ((lanes == 4) ? MASK_NOL_4 :
746 (lanes == 3) ? MASK_NOL_3 :
747 (lanes == 2) ? MASK_NOL_2 : MASK_NOL_1));
748
749 i2c_wr32(sd, CSI_CONFW, MASK_MODE_SET |
750 MASK_ADDRESS_CSI_ERR_INTENA | MASK_TXBRK | MASK_QUNK |
751 MASK_WCER | MASK_INER);
752
753 i2c_wr32(sd, CSI_CONFW, MASK_MODE_CLEAR |
754 MASK_ADDRESS_CSI_ERR_HALT | MASK_TXBRK | MASK_QUNK);
755
756 i2c_wr32(sd, CSI_CONFW, MASK_MODE_SET |
757 MASK_ADDRESS_CSI_INT_ENA | MASK_INTER);
758 }
759
tc358743_set_hdmi_phy(struct v4l2_subdev * sd)760 static void tc358743_set_hdmi_phy(struct v4l2_subdev *sd)
761 {
762 struct tc358743_state *state = to_state(sd);
763 struct tc358743_platform_data *pdata = &state->pdata;
764
765 /* Default settings from REF_02, sheet "Source HDMI"
766 * and custom settings as platform data */
767 i2c_wr8_and_or(sd, PHY_EN, ~MASK_ENABLE_PHY, 0x0);
768 i2c_wr8(sd, PHY_CTL1, SET_PHY_AUTO_RST1_US(1600) |
769 SET_FREQ_RANGE_MODE_CYCLES(1));
770 i2c_wr8_and_or(sd, PHY_CTL2, ~MASK_PHY_AUTO_RSTn,
771 (pdata->hdmi_phy_auto_reset_tmds_detected ?
772 MASK_PHY_AUTO_RST2 : 0) |
773 (pdata->hdmi_phy_auto_reset_tmds_in_range ?
774 MASK_PHY_AUTO_RST3 : 0) |
775 (pdata->hdmi_phy_auto_reset_tmds_valid ?
776 MASK_PHY_AUTO_RST4 : 0));
777 i2c_wr8(sd, PHY_BIAS, 0x40);
778 i2c_wr8(sd, PHY_CSQ, SET_CSQ_CNT_LEVEL(0x0a));
779 i2c_wr8(sd, AVM_CTL, 45);
780 i2c_wr8_and_or(sd, HDMI_DET, ~MASK_HDMI_DET_V,
781 pdata->hdmi_detection_delay << 4);
782 i2c_wr8_and_or(sd, HV_RST, ~(MASK_H_PI_RST | MASK_V_PI_RST),
783 (pdata->hdmi_phy_auto_reset_hsync_out_of_range ?
784 MASK_H_PI_RST : 0) |
785 (pdata->hdmi_phy_auto_reset_vsync_out_of_range ?
786 MASK_V_PI_RST : 0));
787 i2c_wr8_and_or(sd, PHY_EN, ~MASK_ENABLE_PHY, MASK_ENABLE_PHY);
788 }
789
tc358743_set_hdmi_audio(struct v4l2_subdev * sd)790 static void tc358743_set_hdmi_audio(struct v4l2_subdev *sd)
791 {
792 struct tc358743_state *state = to_state(sd);
793
794 /* Default settings from REF_02, sheet "Source HDMI" */
795 i2c_wr8(sd, FORCE_MUTE, 0x00);
796 i2c_wr8(sd, AUTO_CMD0, MASK_AUTO_MUTE7 | MASK_AUTO_MUTE6 |
797 MASK_AUTO_MUTE5 | MASK_AUTO_MUTE4 |
798 MASK_AUTO_MUTE1 | MASK_AUTO_MUTE0);
799 i2c_wr8(sd, AUTO_CMD1, MASK_AUTO_MUTE9);
800 i2c_wr8(sd, AUTO_CMD2, MASK_AUTO_PLAY3 | MASK_AUTO_PLAY2);
801 i2c_wr8(sd, BUFINIT_START, SET_BUFINIT_START_MS(500));
802 i2c_wr8(sd, FS_MUTE, 0x00);
803 i2c_wr8(sd, FS_IMODE, MASK_NLPCM_SMODE | MASK_FS_SMODE);
804 i2c_wr8(sd, ACR_MODE, MASK_CTS_MODE);
805 i2c_wr8(sd, ACR_MDF0, MASK_ACR_L2MDF_1976_PPM | MASK_ACR_L1MDF_976_PPM);
806 i2c_wr8(sd, ACR_MDF1, MASK_ACR_L3MDF_3906_PPM);
807 i2c_wr8(sd, SDO_MODE1, MASK_SDO_FMT_I2S);
808 i2c_wr8(sd, DIV_MODE, SET_DIV_DLY_MS(100));
809
810 mutex_lock(&state->confctl_mutex);
811 i2c_wr16_and_or(sd, CONFCTL, 0xffff, MASK_AUDCHNUM_2 |
812 MASK_AUDOUTSEL_I2S | MASK_AUTOINDEX);
813 mutex_unlock(&state->confctl_mutex);
814 }
815
tc358743_set_hdmi_info_frame_mode(struct v4l2_subdev * sd)816 static void tc358743_set_hdmi_info_frame_mode(struct v4l2_subdev *sd)
817 {
818 /* Default settings from REF_02, sheet "Source HDMI" */
819 i2c_wr8(sd, PK_INT_MODE, MASK_ISRC2_INT_MODE | MASK_ISRC_INT_MODE |
820 MASK_ACP_INT_MODE | MASK_VS_INT_MODE |
821 MASK_SPD_INT_MODE | MASK_MS_INT_MODE |
822 MASK_AUD_INT_MODE | MASK_AVI_INT_MODE);
823 i2c_wr8(sd, NO_PKT_LIMIT, 0x2c);
824 i2c_wr8(sd, NO_PKT_CLR, 0x53);
825 i2c_wr8(sd, ERR_PK_LIMIT, 0x01);
826 i2c_wr8(sd, NO_PKT_LIMIT2, 0x30);
827 i2c_wr8(sd, NO_GDB_LIMIT, 0x10);
828 }
829
tc358743_initial_setup(struct v4l2_subdev * sd)830 static void tc358743_initial_setup(struct v4l2_subdev *sd)
831 {
832 struct tc358743_state *state = to_state(sd);
833 struct tc358743_platform_data *pdata = &state->pdata;
834
835 /*
836 * IR is not supported by this driver.
837 * CEC is only enabled if needed.
838 */
839 i2c_wr16_and_or(sd, SYSCTL, ~(MASK_IRRST | MASK_CECRST),
840 (MASK_IRRST | MASK_CECRST));
841
842 tc358743_reset(sd, MASK_CTXRST | MASK_HDMIRST);
843 #ifdef CONFIG_VIDEO_TC358743_CEC
844 tc358743_reset(sd, MASK_CECRST);
845 #endif
846 tc358743_sleep_mode(sd, false);
847
848 i2c_wr16(sd, FIFOCTL, pdata->fifo_level);
849
850 tc358743_set_ref_clk(sd);
851
852 i2c_wr8_and_or(sd, DDC_CTL, ~MASK_DDC5V_MODE,
853 pdata->ddc5v_delay & MASK_DDC5V_MODE);
854 i2c_wr8_and_or(sd, EDID_MODE, ~MASK_EDID_MODE, MASK_EDID_MODE_E_DDC);
855
856 tc358743_set_hdmi_phy(sd);
857 tc358743_set_hdmi_hdcp(sd, pdata->enable_hdcp);
858 tc358743_set_hdmi_audio(sd);
859 tc358743_set_hdmi_info_frame_mode(sd);
860
861 /* All CE and IT formats are detected as RGB full range in DVI mode */
862 i2c_wr8_and_or(sd, VI_MODE, ~MASK_RGB_DVI, 0);
863
864 i2c_wr8_and_or(sd, VOUT_SET2, ~MASK_VOUTCOLORMODE,
865 MASK_VOUTCOLORMODE_AUTO);
866 i2c_wr8(sd, VOUT_SET3, MASK_VOUT_EXTCNT);
867 }
868
869 /* --------------- CEC --------------- */
870
871 #ifdef CONFIG_VIDEO_TC358743_CEC
tc358743_cec_adap_enable(struct cec_adapter * adap,bool enable)872 static int tc358743_cec_adap_enable(struct cec_adapter *adap, bool enable)
873 {
874 struct tc358743_state *state = adap->priv;
875 struct v4l2_subdev *sd = &state->sd;
876
877 i2c_wr32(sd, CECIMSK, enable ? MASK_CECTIM | MASK_CECRIM : 0);
878 i2c_wr32(sd, CECICLR, MASK_CECTICLR | MASK_CECRICLR);
879 i2c_wr32(sd, CECEN, enable);
880 if (enable)
881 i2c_wr32(sd, CECREN, MASK_CECREN);
882 return 0;
883 }
884
tc358743_cec_adap_monitor_all_enable(struct cec_adapter * adap,bool enable)885 static int tc358743_cec_adap_monitor_all_enable(struct cec_adapter *adap,
886 bool enable)
887 {
888 struct tc358743_state *state = adap->priv;
889 struct v4l2_subdev *sd = &state->sd;
890 u32 reg;
891
892 reg = i2c_rd32(sd, CECRCTL1);
893 if (enable)
894 reg |= MASK_CECOTH;
895 else
896 reg &= ~MASK_CECOTH;
897 i2c_wr32(sd, CECRCTL1, reg);
898 return 0;
899 }
900
tc358743_cec_adap_log_addr(struct cec_adapter * adap,u8 log_addr)901 static int tc358743_cec_adap_log_addr(struct cec_adapter *adap, u8 log_addr)
902 {
903 struct tc358743_state *state = adap->priv;
904 struct v4l2_subdev *sd = &state->sd;
905 unsigned int la = 0;
906
907 if (log_addr != CEC_LOG_ADDR_INVALID) {
908 la = i2c_rd32(sd, CECADD);
909 la |= 1 << log_addr;
910 }
911 i2c_wr32(sd, CECADD, la);
912 return 0;
913 }
914
tc358743_cec_adap_transmit(struct cec_adapter * adap,u8 attempts,u32 signal_free_time,struct cec_msg * msg)915 static int tc358743_cec_adap_transmit(struct cec_adapter *adap, u8 attempts,
916 u32 signal_free_time, struct cec_msg *msg)
917 {
918 struct tc358743_state *state = adap->priv;
919 struct v4l2_subdev *sd = &state->sd;
920 unsigned int i;
921
922 i2c_wr32(sd, CECTCTL,
923 (cec_msg_is_broadcast(msg) ? MASK_CECBRD : 0) |
924 (signal_free_time - 1));
925 for (i = 0; i < msg->len; i++)
926 i2c_wr32(sd, CECTBUF1 + i * 4,
927 msg->msg[i] | ((i == msg->len - 1) ? MASK_CECTEOM : 0));
928 i2c_wr32(sd, CECTEN, MASK_CECTEN);
929 return 0;
930 }
931
932 static const struct cec_adap_ops tc358743_cec_adap_ops = {
933 .adap_enable = tc358743_cec_adap_enable,
934 .adap_log_addr = tc358743_cec_adap_log_addr,
935 .adap_transmit = tc358743_cec_adap_transmit,
936 .adap_monitor_all_enable = tc358743_cec_adap_monitor_all_enable,
937 };
938
tc358743_cec_handler(struct v4l2_subdev * sd,u16 intstatus,bool * handled)939 static void tc358743_cec_handler(struct v4l2_subdev *sd, u16 intstatus,
940 bool *handled)
941 {
942 struct tc358743_state *state = to_state(sd);
943 unsigned int cec_rxint, cec_txint;
944 unsigned int clr = 0;
945
946 cec_rxint = i2c_rd32(sd, CECRSTAT);
947 cec_txint = i2c_rd32(sd, CECTSTAT);
948
949 if (intstatus & MASK_CEC_RINT)
950 clr |= MASK_CECRICLR;
951 if (intstatus & MASK_CEC_TINT)
952 clr |= MASK_CECTICLR;
953 i2c_wr32(sd, CECICLR, clr);
954
955 if ((intstatus & MASK_CEC_TINT) && cec_txint) {
956 if (cec_txint & MASK_CECTIEND)
957 cec_transmit_attempt_done(state->cec_adap,
958 CEC_TX_STATUS_OK);
959 else if (cec_txint & MASK_CECTIAL)
960 cec_transmit_attempt_done(state->cec_adap,
961 CEC_TX_STATUS_ARB_LOST);
962 else if (cec_txint & MASK_CECTIACK)
963 cec_transmit_attempt_done(state->cec_adap,
964 CEC_TX_STATUS_NACK);
965 else if (cec_txint & MASK_CECTIUR) {
966 /*
967 * Not sure when this bit is set. Treat
968 * it as an error for now.
969 */
970 cec_transmit_attempt_done(state->cec_adap,
971 CEC_TX_STATUS_ERROR);
972 }
973 if (handled)
974 *handled = true;
975 }
976 if ((intstatus & MASK_CEC_RINT) &&
977 (cec_rxint & MASK_CECRIEND)) {
978 struct cec_msg msg = {};
979 unsigned int i;
980 unsigned int v;
981
982 v = i2c_rd32(sd, CECRCTR);
983 msg.len = v & 0x1f;
984 if (msg.len > CEC_MAX_MSG_SIZE)
985 msg.len = CEC_MAX_MSG_SIZE;
986 for (i = 0; i < msg.len; i++) {
987 v = i2c_rd32(sd, CECRBUF1 + i * 4);
988 msg.msg[i] = v & 0xff;
989 }
990 cec_received_msg(state->cec_adap, &msg);
991 if (handled)
992 *handled = true;
993 }
994 i2c_wr16(sd, INTSTATUS,
995 intstatus & (MASK_CEC_RINT | MASK_CEC_TINT));
996 }
997
998 #endif
999
1000 /* --------------- IRQ --------------- */
1001
tc358743_format_change(struct v4l2_subdev * sd)1002 static void tc358743_format_change(struct v4l2_subdev *sd)
1003 {
1004 struct tc358743_state *state = to_state(sd);
1005 struct v4l2_dv_timings timings;
1006 const struct v4l2_event tc358743_ev_fmt = {
1007 .type = V4L2_EVENT_SOURCE_CHANGE,
1008 .u.src_change.changes = V4L2_EVENT_SRC_CH_RESOLUTION,
1009 };
1010
1011 if (tc358743_get_detected_timings(sd, &timings)) {
1012 enable_stream(sd, false);
1013
1014 v4l2_dbg(1, debug, sd, "%s: No signal\n",
1015 __func__);
1016 } else {
1017 if (!v4l2_match_dv_timings(&state->timings, &timings, 0, false))
1018 enable_stream(sd, false);
1019
1020 if (debug)
1021 v4l2_print_dv_timings(sd->name,
1022 "tc358743_format_change: New format: ",
1023 &timings, false);
1024 }
1025
1026 if (sd->devnode)
1027 v4l2_subdev_notify_event(sd, &tc358743_ev_fmt);
1028 }
1029
tc358743_init_interrupts(struct v4l2_subdev * sd)1030 static void tc358743_init_interrupts(struct v4l2_subdev *sd)
1031 {
1032 u16 i;
1033
1034 /* clear interrupt status registers */
1035 for (i = SYS_INT; i <= KEY_INT; i++)
1036 i2c_wr8(sd, i, 0xff);
1037
1038 i2c_wr16(sd, INTSTATUS, 0xffff);
1039 }
1040
tc358743_enable_interrupts(struct v4l2_subdev * sd,bool cable_connected)1041 static void tc358743_enable_interrupts(struct v4l2_subdev *sd,
1042 bool cable_connected)
1043 {
1044 v4l2_dbg(2, debug, sd, "%s: cable connected = %d\n", __func__,
1045 cable_connected);
1046
1047 if (cable_connected) {
1048 i2c_wr8(sd, SYS_INTM, ~(MASK_M_DDC | MASK_M_DVI_DET |
1049 MASK_M_HDMI_DET) & 0xff);
1050 i2c_wr8(sd, CLK_INTM, ~MASK_M_IN_DE_CHG);
1051 i2c_wr8(sd, CBIT_INTM, ~(MASK_M_CBIT_FS | MASK_M_AF_LOCK |
1052 MASK_M_AF_UNLOCK) & 0xff);
1053 i2c_wr8(sd, AUDIO_INTM, ~MASK_M_BUFINIT_END);
1054 i2c_wr8(sd, MISC_INTM, ~MASK_M_SYNC_CHG);
1055 } else {
1056 i2c_wr8(sd, SYS_INTM, ~MASK_M_DDC & 0xff);
1057 i2c_wr8(sd, CLK_INTM, 0xff);
1058 i2c_wr8(sd, CBIT_INTM, 0xff);
1059 i2c_wr8(sd, AUDIO_INTM, 0xff);
1060 i2c_wr8(sd, MISC_INTM, 0xff);
1061 }
1062 }
1063
tc358743_hdmi_audio_int_handler(struct v4l2_subdev * sd,bool * handled)1064 static void tc358743_hdmi_audio_int_handler(struct v4l2_subdev *sd,
1065 bool *handled)
1066 {
1067 u8 audio_int_mask = i2c_rd8(sd, AUDIO_INTM);
1068 u8 audio_int = i2c_rd8(sd, AUDIO_INT) & ~audio_int_mask;
1069
1070 i2c_wr8(sd, AUDIO_INT, audio_int);
1071
1072 v4l2_dbg(3, debug, sd, "%s: AUDIO_INT = 0x%02x\n", __func__, audio_int);
1073
1074 tc358743_s_ctrl_audio_sampling_rate(sd);
1075 tc358743_s_ctrl_audio_present(sd);
1076 }
1077
tc358743_csi_err_int_handler(struct v4l2_subdev * sd,bool * handled)1078 static void tc358743_csi_err_int_handler(struct v4l2_subdev *sd, bool *handled)
1079 {
1080 v4l2_err(sd, "%s: CSI_ERR = 0x%x\n", __func__, i2c_rd32(sd, CSI_ERR));
1081
1082 i2c_wr32(sd, CSI_INT_CLR, MASK_ICRER);
1083 }
1084
tc358743_hdmi_misc_int_handler(struct v4l2_subdev * sd,bool * handled)1085 static void tc358743_hdmi_misc_int_handler(struct v4l2_subdev *sd,
1086 bool *handled)
1087 {
1088 u8 misc_int_mask = i2c_rd8(sd, MISC_INTM);
1089 u8 misc_int = i2c_rd8(sd, MISC_INT) & ~misc_int_mask;
1090
1091 i2c_wr8(sd, MISC_INT, misc_int);
1092
1093 v4l2_dbg(3, debug, sd, "%s: MISC_INT = 0x%02x\n", __func__, misc_int);
1094
1095 if (misc_int & MASK_I_SYNC_CHG) {
1096 /* Reset the HDMI PHY to try to trigger proper lock on the
1097 * incoming video format. Erase BKSV to prevent that old keys
1098 * are used when a new source is connected. */
1099 if (no_sync(sd) || no_signal(sd)) {
1100 tc358743_reset_phy(sd);
1101 tc358743_erase_bksv(sd);
1102 }
1103
1104 tc358743_format_change(sd);
1105
1106 misc_int &= ~MASK_I_SYNC_CHG;
1107 if (handled)
1108 *handled = true;
1109 }
1110
1111 if (misc_int) {
1112 v4l2_err(sd, "%s: Unhandled MISC_INT interrupts: 0x%02x\n",
1113 __func__, misc_int);
1114 }
1115 }
1116
tc358743_hdmi_cbit_int_handler(struct v4l2_subdev * sd,bool * handled)1117 static void tc358743_hdmi_cbit_int_handler(struct v4l2_subdev *sd,
1118 bool *handled)
1119 {
1120 u8 cbit_int_mask = i2c_rd8(sd, CBIT_INTM);
1121 u8 cbit_int = i2c_rd8(sd, CBIT_INT) & ~cbit_int_mask;
1122
1123 i2c_wr8(sd, CBIT_INT, cbit_int);
1124
1125 v4l2_dbg(3, debug, sd, "%s: CBIT_INT = 0x%02x\n", __func__, cbit_int);
1126
1127 if (cbit_int & MASK_I_CBIT_FS) {
1128
1129 v4l2_dbg(1, debug, sd, "%s: Audio sample rate changed\n",
1130 __func__);
1131 tc358743_s_ctrl_audio_sampling_rate(sd);
1132
1133 cbit_int &= ~MASK_I_CBIT_FS;
1134 if (handled)
1135 *handled = true;
1136 }
1137
1138 if (cbit_int & (MASK_I_AF_LOCK | MASK_I_AF_UNLOCK)) {
1139
1140 v4l2_dbg(1, debug, sd, "%s: Audio present changed\n",
1141 __func__);
1142 tc358743_s_ctrl_audio_present(sd);
1143
1144 cbit_int &= ~(MASK_I_AF_LOCK | MASK_I_AF_UNLOCK);
1145 if (handled)
1146 *handled = true;
1147 }
1148
1149 if (cbit_int) {
1150 v4l2_err(sd, "%s: Unhandled CBIT_INT interrupts: 0x%02x\n",
1151 __func__, cbit_int);
1152 }
1153 }
1154
tc358743_hdmi_clk_int_handler(struct v4l2_subdev * sd,bool * handled)1155 static void tc358743_hdmi_clk_int_handler(struct v4l2_subdev *sd, bool *handled)
1156 {
1157 u8 clk_int_mask = i2c_rd8(sd, CLK_INTM);
1158 u8 clk_int = i2c_rd8(sd, CLK_INT) & ~clk_int_mask;
1159
1160 /* Bit 7 and bit 6 are set even when they are masked */
1161 i2c_wr8(sd, CLK_INT, clk_int | 0x80 | MASK_I_OUT_H_CHG);
1162
1163 v4l2_dbg(3, debug, sd, "%s: CLK_INT = 0x%02x\n", __func__, clk_int);
1164
1165 if (clk_int & (MASK_I_IN_DE_CHG)) {
1166
1167 v4l2_dbg(1, debug, sd, "%s: DE size or position has changed\n",
1168 __func__);
1169
1170 /* If the source switch to a new resolution with the same pixel
1171 * frequency as the existing (e.g. 1080p25 -> 720p50), the
1172 * I_SYNC_CHG interrupt is not always triggered, while the
1173 * I_IN_DE_CHG interrupt seems to work fine. Format change
1174 * notifications are only sent when the signal is stable to
1175 * reduce the number of notifications. */
1176 if (!no_signal(sd) && !no_sync(sd))
1177 tc358743_format_change(sd);
1178
1179 clk_int &= ~(MASK_I_IN_DE_CHG);
1180 if (handled)
1181 *handled = true;
1182 }
1183
1184 if (clk_int) {
1185 v4l2_err(sd, "%s: Unhandled CLK_INT interrupts: 0x%02x\n",
1186 __func__, clk_int);
1187 }
1188 }
1189
tc358743_hdmi_sys_int_handler(struct v4l2_subdev * sd,bool * handled)1190 static void tc358743_hdmi_sys_int_handler(struct v4l2_subdev *sd, bool *handled)
1191 {
1192 struct tc358743_state *state = to_state(sd);
1193 u8 sys_int_mask = i2c_rd8(sd, SYS_INTM);
1194 u8 sys_int = i2c_rd8(sd, SYS_INT) & ~sys_int_mask;
1195
1196 i2c_wr8(sd, SYS_INT, sys_int);
1197
1198 v4l2_dbg(3, debug, sd, "%s: SYS_INT = 0x%02x\n", __func__, sys_int);
1199
1200 if (sys_int & MASK_I_DDC) {
1201 bool tx_5v = tx_5v_power_present(sd);
1202
1203 v4l2_dbg(1, debug, sd, "%s: Tx 5V power present: %s\n",
1204 __func__, tx_5v ? "yes" : "no");
1205
1206 if (tx_5v) {
1207 tc358743_enable_edid(sd);
1208 } else {
1209 tc358743_enable_interrupts(sd, false);
1210 tc358743_disable_edid(sd);
1211 memset(&state->timings, 0, sizeof(state->timings));
1212 tc358743_erase_bksv(sd);
1213 tc358743_update_controls(sd);
1214 }
1215
1216 sys_int &= ~MASK_I_DDC;
1217 if (handled)
1218 *handled = true;
1219 }
1220
1221 if (sys_int & MASK_I_DVI) {
1222 v4l2_dbg(1, debug, sd, "%s: HDMI->DVI change detected\n",
1223 __func__);
1224
1225 /* Reset the HDMI PHY to try to trigger proper lock on the
1226 * incoming video format. Erase BKSV to prevent that old keys
1227 * are used when a new source is connected. */
1228 if (no_sync(sd) || no_signal(sd)) {
1229 tc358743_reset_phy(sd);
1230 tc358743_erase_bksv(sd);
1231 }
1232
1233 sys_int &= ~MASK_I_DVI;
1234 if (handled)
1235 *handled = true;
1236 }
1237
1238 if (sys_int & MASK_I_HDMI) {
1239 v4l2_dbg(1, debug, sd, "%s: DVI->HDMI change detected\n",
1240 __func__);
1241
1242 /* Register is reset in DVI mode (REF_01, c. 6.6.41) */
1243 i2c_wr8(sd, ANA_CTL, MASK_APPL_PCSX_NORMAL | MASK_ANALOG_ON);
1244
1245 sys_int &= ~MASK_I_HDMI;
1246 if (handled)
1247 *handled = true;
1248 }
1249
1250 if (sys_int) {
1251 v4l2_err(sd, "%s: Unhandled SYS_INT interrupts: 0x%02x\n",
1252 __func__, sys_int);
1253 }
1254 }
1255
1256 /* --------------- CORE OPS --------------- */
1257
tc358743_log_status(struct v4l2_subdev * sd)1258 static int tc358743_log_status(struct v4l2_subdev *sd)
1259 {
1260 struct tc358743_state *state = to_state(sd);
1261 struct v4l2_dv_timings timings;
1262 uint8_t hdmi_sys_status = i2c_rd8(sd, SYS_STATUS);
1263 uint16_t sysctl = i2c_rd16(sd, SYSCTL);
1264 u8 vi_status3 = i2c_rd8(sd, VI_STATUS3);
1265 const int deep_color_mode[4] = { 8, 10, 12, 16 };
1266 static const char * const input_color_space[] = {
1267 "RGB", "YCbCr 601", "opRGB", "YCbCr 709", "NA (4)",
1268 "xvYCC 601", "NA(6)", "xvYCC 709", "NA(8)", "sYCC601",
1269 "NA(10)", "NA(11)", "NA(12)", "opYCC 601"};
1270
1271 v4l2_info(sd, "-----Chip status-----\n");
1272 v4l2_info(sd, "Chip ID: 0x%02x\n",
1273 (i2c_rd16(sd, CHIPID) & MASK_CHIPID) >> 8);
1274 v4l2_info(sd, "Chip revision: 0x%02x\n",
1275 i2c_rd16(sd, CHIPID) & MASK_REVID);
1276 v4l2_info(sd, "Reset: IR: %d, CEC: %d, CSI TX: %d, HDMI: %d\n",
1277 !!(sysctl & MASK_IRRST),
1278 !!(sysctl & MASK_CECRST),
1279 !!(sysctl & MASK_CTXRST),
1280 !!(sysctl & MASK_HDMIRST));
1281 v4l2_info(sd, "Sleep mode: %s\n", sysctl & MASK_SLEEP ? "on" : "off");
1282 v4l2_info(sd, "Cable detected (+5V power): %s\n",
1283 hdmi_sys_status & MASK_S_DDC5V ? "yes" : "no");
1284 v4l2_info(sd, "DDC lines enabled: %s\n",
1285 (i2c_rd8(sd, EDID_MODE) & MASK_EDID_MODE_E_DDC) ?
1286 "yes" : "no");
1287 v4l2_info(sd, "Hotplug enabled: %s\n",
1288 (i2c_rd8(sd, HPD_CTL) & MASK_HPD_OUT0) ?
1289 "yes" : "no");
1290 v4l2_info(sd, "CEC enabled: %s\n",
1291 (i2c_rd16(sd, CECEN) & MASK_CECEN) ? "yes" : "no");
1292 v4l2_info(sd, "-----Signal status-----\n");
1293 v4l2_info(sd, "TMDS signal detected: %s\n",
1294 hdmi_sys_status & MASK_S_TMDS ? "yes" : "no");
1295 v4l2_info(sd, "Stable sync signal: %s\n",
1296 hdmi_sys_status & MASK_S_SYNC ? "yes" : "no");
1297 v4l2_info(sd, "PHY PLL locked: %s\n",
1298 hdmi_sys_status & MASK_S_PHY_PLL ? "yes" : "no");
1299 v4l2_info(sd, "PHY DE detected: %s\n",
1300 hdmi_sys_status & MASK_S_PHY_SCDT ? "yes" : "no");
1301
1302 if (tc358743_get_detected_timings(sd, &timings)) {
1303 v4l2_info(sd, "No video detected\n");
1304 } else {
1305 v4l2_print_dv_timings(sd->name, "Detected format: ", &timings,
1306 true);
1307 }
1308 v4l2_print_dv_timings(sd->name, "Configured format: ", &state->timings,
1309 true);
1310
1311 v4l2_info(sd, "-----CSI-TX status-----\n");
1312 v4l2_info(sd, "Lanes needed: %d\n",
1313 tc358743_num_csi_lanes_needed(sd));
1314 v4l2_info(sd, "Lanes in use: %d\n",
1315 state->csi_lanes_in_use);
1316 v4l2_info(sd, "Waiting for particular sync signal: %s\n",
1317 (i2c_rd16(sd, CSI_STATUS) & MASK_S_WSYNC) ?
1318 "yes" : "no");
1319 v4l2_info(sd, "Transmit mode: %s\n",
1320 (i2c_rd16(sd, CSI_STATUS) & MASK_S_TXACT) ?
1321 "yes" : "no");
1322 v4l2_info(sd, "Receive mode: %s\n",
1323 (i2c_rd16(sd, CSI_STATUS) & MASK_S_RXACT) ?
1324 "yes" : "no");
1325 v4l2_info(sd, "Stopped: %s\n",
1326 (i2c_rd16(sd, CSI_STATUS) & MASK_S_HLT) ?
1327 "yes" : "no");
1328 v4l2_info(sd, "Color space: %s\n",
1329 state->mbus_fmt_code == MEDIA_BUS_FMT_UYVY8_1X16 ?
1330 "YCbCr 422 16-bit" :
1331 state->mbus_fmt_code == MEDIA_BUS_FMT_RGB888_1X24 ?
1332 "RGB 888 24-bit" : "Unsupported");
1333
1334 v4l2_info(sd, "-----%s status-----\n", is_hdmi(sd) ? "HDMI" : "DVI-D");
1335 v4l2_info(sd, "HDCP encrypted content: %s\n",
1336 hdmi_sys_status & MASK_S_HDCP ? "yes" : "no");
1337 v4l2_info(sd, "Input color space: %s %s range\n",
1338 input_color_space[(vi_status3 & MASK_S_V_COLOR) >> 1],
1339 (vi_status3 & MASK_LIMITED) ? "limited" : "full");
1340 if (!is_hdmi(sd))
1341 return 0;
1342 v4l2_info(sd, "AV Mute: %s\n", hdmi_sys_status & MASK_S_AVMUTE ? "on" :
1343 "off");
1344 v4l2_info(sd, "Deep color mode: %d-bits per channel\n",
1345 deep_color_mode[(i2c_rd8(sd, VI_STATUS1) &
1346 MASK_S_DEEPCOLOR) >> 2]);
1347 print_avi_infoframe(sd);
1348
1349 return 0;
1350 }
1351
1352 #ifdef CONFIG_VIDEO_ADV_DEBUG
tc358743_print_register_map(struct v4l2_subdev * sd)1353 static void tc358743_print_register_map(struct v4l2_subdev *sd)
1354 {
1355 v4l2_info(sd, "0x0000-0x00FF: Global Control Register\n");
1356 v4l2_info(sd, "0x0100-0x01FF: CSI2-TX PHY Register\n");
1357 v4l2_info(sd, "0x0200-0x03FF: CSI2-TX PPI Register\n");
1358 v4l2_info(sd, "0x0400-0x05FF: Reserved\n");
1359 v4l2_info(sd, "0x0600-0x06FF: CEC Register\n");
1360 v4l2_info(sd, "0x0700-0x84FF: Reserved\n");
1361 v4l2_info(sd, "0x8500-0x85FF: HDMIRX System Control Register\n");
1362 v4l2_info(sd, "0x8600-0x86FF: HDMIRX Audio Control Register\n");
1363 v4l2_info(sd, "0x8700-0x87FF: HDMIRX InfoFrame packet data Register\n");
1364 v4l2_info(sd, "0x8800-0x88FF: HDMIRX HDCP Port Register\n");
1365 v4l2_info(sd, "0x8900-0x89FF: HDMIRX Video Output Port & 3D Register\n");
1366 v4l2_info(sd, "0x8A00-0x8BFF: Reserved\n");
1367 v4l2_info(sd, "0x8C00-0x8FFF: HDMIRX EDID-RAM (1024bytes)\n");
1368 v4l2_info(sd, "0x9000-0x90FF: HDMIRX GBD Extraction Control\n");
1369 v4l2_info(sd, "0x9100-0x92FF: HDMIRX GBD RAM read\n");
1370 v4l2_info(sd, "0x9300- : Reserved\n");
1371 }
1372
tc358743_get_reg_size(u16 address)1373 static int tc358743_get_reg_size(u16 address)
1374 {
1375 /* REF_01 p. 66-72 */
1376 if (address <= 0x00ff)
1377 return 2;
1378 else if ((address >= 0x0100) && (address <= 0x06FF))
1379 return 4;
1380 else if ((address >= 0x0700) && (address <= 0x84ff))
1381 return 2;
1382 else
1383 return 1;
1384 }
1385
tc358743_g_register(struct v4l2_subdev * sd,struct v4l2_dbg_register * reg)1386 static int tc358743_g_register(struct v4l2_subdev *sd,
1387 struct v4l2_dbg_register *reg)
1388 {
1389 if (reg->reg > 0xffff) {
1390 tc358743_print_register_map(sd);
1391 return -EINVAL;
1392 }
1393
1394 reg->size = tc358743_get_reg_size(reg->reg);
1395
1396 reg->val = i2c_rdreg(sd, reg->reg, reg->size);
1397
1398 return 0;
1399 }
1400
tc358743_s_register(struct v4l2_subdev * sd,const struct v4l2_dbg_register * reg)1401 static int tc358743_s_register(struct v4l2_subdev *sd,
1402 const struct v4l2_dbg_register *reg)
1403 {
1404 if (reg->reg > 0xffff) {
1405 tc358743_print_register_map(sd);
1406 return -EINVAL;
1407 }
1408
1409 /* It should not be possible for the user to enable HDCP with a simple
1410 * v4l2-dbg command.
1411 *
1412 * DO NOT REMOVE THIS unless all other issues with HDCP have been
1413 * resolved.
1414 */
1415 if (reg->reg == HDCP_MODE ||
1416 reg->reg == HDCP_REG1 ||
1417 reg->reg == HDCP_REG2 ||
1418 reg->reg == HDCP_REG3 ||
1419 reg->reg == BCAPS)
1420 return 0;
1421
1422 i2c_wrreg(sd, (u16)reg->reg, reg->val,
1423 tc358743_get_reg_size(reg->reg));
1424
1425 return 0;
1426 }
1427 #endif
1428
tc358743_isr(struct v4l2_subdev * sd,u32 status,bool * handled)1429 static int tc358743_isr(struct v4l2_subdev *sd, u32 status, bool *handled)
1430 {
1431 u16 intstatus = i2c_rd16(sd, INTSTATUS);
1432
1433 v4l2_dbg(1, debug, sd, "%s: IntStatus = 0x%04x\n", __func__, intstatus);
1434
1435 if (intstatus & MASK_HDMI_INT) {
1436 u8 hdmi_int0 = i2c_rd8(sd, HDMI_INT0);
1437 u8 hdmi_int1 = i2c_rd8(sd, HDMI_INT1);
1438
1439 if (hdmi_int0 & MASK_I_MISC)
1440 tc358743_hdmi_misc_int_handler(sd, handled);
1441 if (hdmi_int1 & MASK_I_CBIT)
1442 tc358743_hdmi_cbit_int_handler(sd, handled);
1443 if (hdmi_int1 & MASK_I_CLK)
1444 tc358743_hdmi_clk_int_handler(sd, handled);
1445 if (hdmi_int1 & MASK_I_SYS)
1446 tc358743_hdmi_sys_int_handler(sd, handled);
1447 if (hdmi_int1 & MASK_I_AUD)
1448 tc358743_hdmi_audio_int_handler(sd, handled);
1449
1450 i2c_wr16(sd, INTSTATUS, MASK_HDMI_INT);
1451 intstatus &= ~MASK_HDMI_INT;
1452 }
1453
1454 #ifdef CONFIG_VIDEO_TC358743_CEC
1455 if (intstatus & (MASK_CEC_RINT | MASK_CEC_TINT)) {
1456 tc358743_cec_handler(sd, intstatus, handled);
1457 i2c_wr16(sd, INTSTATUS,
1458 intstatus & (MASK_CEC_RINT | MASK_CEC_TINT));
1459 intstatus &= ~(MASK_CEC_RINT | MASK_CEC_TINT);
1460 }
1461 #endif
1462
1463 if (intstatus & MASK_CSI_INT) {
1464 u32 csi_int = i2c_rd32(sd, CSI_INT);
1465
1466 if (csi_int & MASK_INTER)
1467 tc358743_csi_err_int_handler(sd, handled);
1468
1469 i2c_wr16(sd, INTSTATUS, MASK_CSI_INT);
1470 }
1471
1472 intstatus = i2c_rd16(sd, INTSTATUS);
1473 if (intstatus) {
1474 v4l2_dbg(1, debug, sd,
1475 "%s: Unhandled IntStatus interrupts: 0x%02x\n",
1476 __func__, intstatus);
1477 }
1478
1479 return 0;
1480 }
1481
tc358743_irq_handler(int irq,void * dev_id)1482 static irqreturn_t tc358743_irq_handler(int irq, void *dev_id)
1483 {
1484 struct tc358743_state *state = dev_id;
1485 bool handled = false;
1486
1487 tc358743_isr(&state->sd, 0, &handled);
1488
1489 return handled ? IRQ_HANDLED : IRQ_NONE;
1490 }
1491
tc358743_irq_poll_timer(struct timer_list * t)1492 static void tc358743_irq_poll_timer(struct timer_list *t)
1493 {
1494 struct tc358743_state *state = from_timer(state, t, timer);
1495 unsigned int msecs;
1496
1497 schedule_work(&state->work_i2c_poll);
1498 /*
1499 * If CEC is present, then we need to poll more frequently,
1500 * otherwise we will miss CEC messages.
1501 */
1502 msecs = state->cec_adap ? POLL_INTERVAL_CEC_MS : POLL_INTERVAL_MS;
1503 mod_timer(&state->timer, jiffies + msecs_to_jiffies(msecs));
1504 }
1505
tc358743_work_i2c_poll(struct work_struct * work)1506 static void tc358743_work_i2c_poll(struct work_struct *work)
1507 {
1508 struct tc358743_state *state = container_of(work,
1509 struct tc358743_state, work_i2c_poll);
1510 bool handled;
1511
1512 tc358743_isr(&state->sd, 0, &handled);
1513 }
1514
tc358743_subscribe_event(struct v4l2_subdev * sd,struct v4l2_fh * fh,struct v4l2_event_subscription * sub)1515 static int tc358743_subscribe_event(struct v4l2_subdev *sd, struct v4l2_fh *fh,
1516 struct v4l2_event_subscription *sub)
1517 {
1518 switch (sub->type) {
1519 case V4L2_EVENT_SOURCE_CHANGE:
1520 return v4l2_src_change_event_subdev_subscribe(sd, fh, sub);
1521 case V4L2_EVENT_CTRL:
1522 return v4l2_ctrl_subdev_subscribe_event(sd, fh, sub);
1523 default:
1524 return -EINVAL;
1525 }
1526 }
1527
1528 /* --------------- VIDEO OPS --------------- */
1529
tc358743_g_input_status(struct v4l2_subdev * sd,u32 * status)1530 static int tc358743_g_input_status(struct v4l2_subdev *sd, u32 *status)
1531 {
1532 *status = 0;
1533 *status |= no_signal(sd) ? V4L2_IN_ST_NO_SIGNAL : 0;
1534 *status |= no_sync(sd) ? V4L2_IN_ST_NO_SYNC : 0;
1535
1536 v4l2_dbg(1, debug, sd, "%s: status = 0x%x\n", __func__, *status);
1537
1538 return 0;
1539 }
1540
tc358743_s_dv_timings(struct v4l2_subdev * sd,unsigned int pad,struct v4l2_dv_timings * timings)1541 static int tc358743_s_dv_timings(struct v4l2_subdev *sd, unsigned int pad,
1542 struct v4l2_dv_timings *timings)
1543 {
1544 struct tc358743_state *state = to_state(sd);
1545
1546 if (pad != 0)
1547 return -EINVAL;
1548
1549 if (!timings)
1550 return -EINVAL;
1551
1552 if (debug)
1553 v4l2_print_dv_timings(sd->name, "tc358743_s_dv_timings: ",
1554 timings, false);
1555
1556 if (v4l2_match_dv_timings(&state->timings, timings, 0, false)) {
1557 v4l2_dbg(1, debug, sd, "%s: no change\n", __func__);
1558 return 0;
1559 }
1560
1561 if (!v4l2_valid_dv_timings(timings,
1562 &tc358743_timings_cap, NULL, NULL)) {
1563 v4l2_dbg(1, debug, sd, "%s: timings out of range\n", __func__);
1564 return -ERANGE;
1565 }
1566
1567 state->timings = *timings;
1568
1569 enable_stream(sd, false);
1570 tc358743_set_pll(sd);
1571 tc358743_set_csi(sd);
1572
1573 return 0;
1574 }
1575
tc358743_g_dv_timings(struct v4l2_subdev * sd,unsigned int pad,struct v4l2_dv_timings * timings)1576 static int tc358743_g_dv_timings(struct v4l2_subdev *sd, unsigned int pad,
1577 struct v4l2_dv_timings *timings)
1578 {
1579 struct tc358743_state *state = to_state(sd);
1580
1581 if (pad != 0)
1582 return -EINVAL;
1583
1584 *timings = state->timings;
1585
1586 return 0;
1587 }
1588
tc358743_enum_dv_timings(struct v4l2_subdev * sd,struct v4l2_enum_dv_timings * timings)1589 static int tc358743_enum_dv_timings(struct v4l2_subdev *sd,
1590 struct v4l2_enum_dv_timings *timings)
1591 {
1592 if (timings->pad != 0)
1593 return -EINVAL;
1594
1595 return v4l2_enum_dv_timings_cap(timings,
1596 &tc358743_timings_cap, NULL, NULL);
1597 }
1598
tc358743_query_dv_timings(struct v4l2_subdev * sd,unsigned int pad,struct v4l2_dv_timings * timings)1599 static int tc358743_query_dv_timings(struct v4l2_subdev *sd, unsigned int pad,
1600 struct v4l2_dv_timings *timings)
1601 {
1602 int ret;
1603
1604 if (pad != 0)
1605 return -EINVAL;
1606
1607 ret = tc358743_get_detected_timings(sd, timings);
1608 if (ret)
1609 return ret;
1610
1611 if (debug)
1612 v4l2_print_dv_timings(sd->name, "tc358743_query_dv_timings: ",
1613 timings, false);
1614
1615 if (!v4l2_valid_dv_timings(timings,
1616 &tc358743_timings_cap, NULL, NULL)) {
1617 v4l2_dbg(1, debug, sd, "%s: timings out of range\n", __func__);
1618 return -ERANGE;
1619 }
1620
1621 return 0;
1622 }
1623
tc358743_dv_timings_cap(struct v4l2_subdev * sd,struct v4l2_dv_timings_cap * cap)1624 static int tc358743_dv_timings_cap(struct v4l2_subdev *sd,
1625 struct v4l2_dv_timings_cap *cap)
1626 {
1627 if (cap->pad != 0)
1628 return -EINVAL;
1629
1630 *cap = tc358743_timings_cap;
1631
1632 return 0;
1633 }
1634
tc358743_get_mbus_config(struct v4l2_subdev * sd,unsigned int pad,struct v4l2_mbus_config * cfg)1635 static int tc358743_get_mbus_config(struct v4l2_subdev *sd,
1636 unsigned int pad,
1637 struct v4l2_mbus_config *cfg)
1638 {
1639 struct tc358743_state *state = to_state(sd);
1640
1641 cfg->type = V4L2_MBUS_CSI2_DPHY;
1642
1643 /* Support for non-continuous CSI-2 clock is missing in the driver */
1644 cfg->bus.mipi_csi2.flags = 0;
1645 cfg->bus.mipi_csi2.num_data_lanes = state->csi_lanes_in_use;
1646
1647 return 0;
1648 }
1649
tc358743_s_stream(struct v4l2_subdev * sd,int enable)1650 static int tc358743_s_stream(struct v4l2_subdev *sd, int enable)
1651 {
1652 enable_stream(sd, enable);
1653 if (!enable) {
1654 /* Put all lanes in LP-11 state (STOPSTATE) */
1655 tc358743_set_csi(sd);
1656 }
1657
1658 return 0;
1659 }
1660
1661 /* --------------- PAD OPS --------------- */
1662
tc358743_enum_mbus_code(struct v4l2_subdev * sd,struct v4l2_subdev_state * sd_state,struct v4l2_subdev_mbus_code_enum * code)1663 static int tc358743_enum_mbus_code(struct v4l2_subdev *sd,
1664 struct v4l2_subdev_state *sd_state,
1665 struct v4l2_subdev_mbus_code_enum *code)
1666 {
1667 switch (code->index) {
1668 case 0:
1669 code->code = MEDIA_BUS_FMT_RGB888_1X24;
1670 break;
1671 case 1:
1672 code->code = MEDIA_BUS_FMT_UYVY8_1X16;
1673 break;
1674 default:
1675 return -EINVAL;
1676 }
1677 return 0;
1678 }
1679
tc358743_g_colorspace(u32 code)1680 static u32 tc358743_g_colorspace(u32 code)
1681 {
1682 switch (code) {
1683 case MEDIA_BUS_FMT_RGB888_1X24:
1684 return V4L2_COLORSPACE_SRGB;
1685 case MEDIA_BUS_FMT_UYVY8_1X16:
1686 return V4L2_COLORSPACE_SMPTE170M;
1687 default:
1688 return 0;
1689 }
1690 }
1691
tc358743_get_fmt(struct v4l2_subdev * sd,struct v4l2_subdev_state * sd_state,struct v4l2_subdev_format * format)1692 static int tc358743_get_fmt(struct v4l2_subdev *sd,
1693 struct v4l2_subdev_state *sd_state,
1694 struct v4l2_subdev_format *format)
1695 {
1696 struct tc358743_state *state = to_state(sd);
1697
1698 if (format->pad != 0)
1699 return -EINVAL;
1700
1701 format->format.code = state->mbus_fmt_code;
1702 format->format.width = state->timings.bt.width;
1703 format->format.height = state->timings.bt.height;
1704 format->format.field = V4L2_FIELD_NONE;
1705
1706 format->format.colorspace = tc358743_g_colorspace(format->format.code);
1707
1708 return 0;
1709 }
1710
tc358743_set_fmt(struct v4l2_subdev * sd,struct v4l2_subdev_state * sd_state,struct v4l2_subdev_format * format)1711 static int tc358743_set_fmt(struct v4l2_subdev *sd,
1712 struct v4l2_subdev_state *sd_state,
1713 struct v4l2_subdev_format *format)
1714 {
1715 struct tc358743_state *state = to_state(sd);
1716
1717 u32 code = format->format.code; /* is overwritten by get_fmt */
1718 int ret = tc358743_get_fmt(sd, sd_state, format);
1719
1720 if (code == MEDIA_BUS_FMT_RGB888_1X24 ||
1721 code == MEDIA_BUS_FMT_UYVY8_1X16)
1722 format->format.code = code;
1723 format->format.colorspace = tc358743_g_colorspace(format->format.code);
1724
1725 if (ret)
1726 return ret;
1727
1728 if (format->which == V4L2_SUBDEV_FORMAT_TRY)
1729 return 0;
1730
1731 state->mbus_fmt_code = format->format.code;
1732
1733 enable_stream(sd, false);
1734 tc358743_set_pll(sd);
1735 tc358743_set_csi(sd);
1736 tc358743_set_csi_color_space(sd);
1737
1738 return 0;
1739 }
1740
tc358743_g_edid(struct v4l2_subdev * sd,struct v4l2_subdev_edid * edid)1741 static int tc358743_g_edid(struct v4l2_subdev *sd,
1742 struct v4l2_subdev_edid *edid)
1743 {
1744 struct tc358743_state *state = to_state(sd);
1745
1746 memset(edid->reserved, 0, sizeof(edid->reserved));
1747
1748 if (edid->pad != 0)
1749 return -EINVAL;
1750
1751 if (edid->start_block == 0 && edid->blocks == 0) {
1752 edid->blocks = state->edid_blocks_written;
1753 return 0;
1754 }
1755
1756 if (state->edid_blocks_written == 0)
1757 return -ENODATA;
1758
1759 if (edid->start_block >= state->edid_blocks_written ||
1760 edid->blocks == 0)
1761 return -EINVAL;
1762
1763 if (edid->start_block + edid->blocks > state->edid_blocks_written)
1764 edid->blocks = state->edid_blocks_written - edid->start_block;
1765
1766 i2c_rd(sd, EDID_RAM + (edid->start_block * EDID_BLOCK_SIZE), edid->edid,
1767 edid->blocks * EDID_BLOCK_SIZE);
1768
1769 return 0;
1770 }
1771
tc358743_s_edid(struct v4l2_subdev * sd,struct v4l2_subdev_edid * edid)1772 static int tc358743_s_edid(struct v4l2_subdev *sd,
1773 struct v4l2_subdev_edid *edid)
1774 {
1775 struct tc358743_state *state = to_state(sd);
1776 u16 edid_len = edid->blocks * EDID_BLOCK_SIZE;
1777 u16 pa;
1778 int err;
1779 int i;
1780
1781 v4l2_dbg(2, debug, sd, "%s, pad %d, start block %d, blocks %d\n",
1782 __func__, edid->pad, edid->start_block, edid->blocks);
1783
1784 memset(edid->reserved, 0, sizeof(edid->reserved));
1785
1786 if (edid->pad != 0)
1787 return -EINVAL;
1788
1789 if (edid->start_block != 0)
1790 return -EINVAL;
1791
1792 if (edid->blocks > EDID_NUM_BLOCKS_MAX) {
1793 edid->blocks = EDID_NUM_BLOCKS_MAX;
1794 return -E2BIG;
1795 }
1796 pa = cec_get_edid_phys_addr(edid->edid, edid->blocks * 128, NULL);
1797 err = v4l2_phys_addr_validate(pa, &pa, NULL);
1798 if (err)
1799 return err;
1800
1801 cec_phys_addr_invalidate(state->cec_adap);
1802
1803 tc358743_disable_edid(sd);
1804
1805 i2c_wr8(sd, EDID_LEN1, edid_len & 0xff);
1806 i2c_wr8(sd, EDID_LEN2, edid_len >> 8);
1807
1808 if (edid->blocks == 0) {
1809 state->edid_blocks_written = 0;
1810 return 0;
1811 }
1812
1813 for (i = 0; i < edid_len; i += EDID_BLOCK_SIZE)
1814 i2c_wr(sd, EDID_RAM + i, edid->edid + i, EDID_BLOCK_SIZE);
1815
1816 state->edid_blocks_written = edid->blocks;
1817
1818 cec_s_phys_addr(state->cec_adap, pa, false);
1819
1820 if (tx_5v_power_present(sd))
1821 tc358743_enable_edid(sd);
1822
1823 return 0;
1824 }
1825
1826 /* -------------------------------------------------------------------------- */
1827
1828 static const struct v4l2_subdev_core_ops tc358743_core_ops = {
1829 .log_status = tc358743_log_status,
1830 #ifdef CONFIG_VIDEO_ADV_DEBUG
1831 .g_register = tc358743_g_register,
1832 .s_register = tc358743_s_register,
1833 #endif
1834 .interrupt_service_routine = tc358743_isr,
1835 .subscribe_event = tc358743_subscribe_event,
1836 .unsubscribe_event = v4l2_event_subdev_unsubscribe,
1837 };
1838
1839 static const struct v4l2_subdev_video_ops tc358743_video_ops = {
1840 .g_input_status = tc358743_g_input_status,
1841 .s_stream = tc358743_s_stream,
1842 };
1843
1844 static const struct v4l2_subdev_pad_ops tc358743_pad_ops = {
1845 .enum_mbus_code = tc358743_enum_mbus_code,
1846 .set_fmt = tc358743_set_fmt,
1847 .get_fmt = tc358743_get_fmt,
1848 .get_edid = tc358743_g_edid,
1849 .set_edid = tc358743_s_edid,
1850 .s_dv_timings = tc358743_s_dv_timings,
1851 .g_dv_timings = tc358743_g_dv_timings,
1852 .query_dv_timings = tc358743_query_dv_timings,
1853 .enum_dv_timings = tc358743_enum_dv_timings,
1854 .dv_timings_cap = tc358743_dv_timings_cap,
1855 .get_mbus_config = tc358743_get_mbus_config,
1856 };
1857
1858 static const struct v4l2_subdev_ops tc358743_ops = {
1859 .core = &tc358743_core_ops,
1860 .video = &tc358743_video_ops,
1861 .pad = &tc358743_pad_ops,
1862 };
1863
1864 /* --------------- CUSTOM CTRLS --------------- */
1865
1866 static const struct v4l2_ctrl_config tc358743_ctrl_audio_sampling_rate = {
1867 .id = TC358743_CID_AUDIO_SAMPLING_RATE,
1868 .name = "Audio sampling rate",
1869 .type = V4L2_CTRL_TYPE_INTEGER,
1870 .min = 0,
1871 .max = 768000,
1872 .step = 1,
1873 .def = 0,
1874 .flags = V4L2_CTRL_FLAG_READ_ONLY,
1875 };
1876
1877 static const struct v4l2_ctrl_config tc358743_ctrl_audio_present = {
1878 .id = TC358743_CID_AUDIO_PRESENT,
1879 .name = "Audio present",
1880 .type = V4L2_CTRL_TYPE_BOOLEAN,
1881 .min = 0,
1882 .max = 1,
1883 .step = 1,
1884 .def = 0,
1885 .flags = V4L2_CTRL_FLAG_READ_ONLY,
1886 };
1887
1888 /* --------------- PROBE / REMOVE --------------- */
1889
1890 #ifdef CONFIG_OF
tc358743_gpio_reset(struct tc358743_state * state)1891 static void tc358743_gpio_reset(struct tc358743_state *state)
1892 {
1893 usleep_range(5000, 10000);
1894 gpiod_set_value(state->reset_gpio, 1);
1895 usleep_range(1000, 2000);
1896 gpiod_set_value(state->reset_gpio, 0);
1897 msleep(20);
1898 }
1899
tc358743_probe_of(struct tc358743_state * state)1900 static int tc358743_probe_of(struct tc358743_state *state)
1901 {
1902 struct device *dev = &state->i2c_client->dev;
1903 struct v4l2_fwnode_endpoint endpoint = { .bus_type = 0 };
1904 struct device_node *ep;
1905 struct clk *refclk;
1906 u32 bps_pr_lane;
1907 int ret;
1908
1909 refclk = devm_clk_get(dev, "refclk");
1910 if (IS_ERR(refclk))
1911 return dev_err_probe(dev, PTR_ERR(refclk),
1912 "failed to get refclk\n");
1913
1914 ep = of_graph_get_endpoint_by_regs(dev->of_node, 0, -1);
1915 if (!ep) {
1916 dev_err(dev, "missing endpoint node\n");
1917 return -EINVAL;
1918 }
1919
1920 ret = v4l2_fwnode_endpoint_alloc_parse(of_fwnode_handle(ep), &endpoint);
1921 if (ret) {
1922 dev_err(dev, "failed to parse endpoint\n");
1923 goto put_node;
1924 }
1925
1926 if (endpoint.bus_type != V4L2_MBUS_CSI2_DPHY ||
1927 endpoint.bus.mipi_csi2.num_data_lanes == 0 ||
1928 endpoint.nr_of_link_frequencies == 0) {
1929 dev_err(dev, "missing CSI-2 properties in endpoint\n");
1930 ret = -EINVAL;
1931 goto free_endpoint;
1932 }
1933
1934 if (endpoint.bus.mipi_csi2.num_data_lanes > 4) {
1935 dev_err(dev, "invalid number of lanes\n");
1936 ret = -EINVAL;
1937 goto free_endpoint;
1938 }
1939
1940 state->bus = endpoint.bus.mipi_csi2;
1941
1942 ret = clk_prepare_enable(refclk);
1943 if (ret) {
1944 dev_err(dev, "Failed! to enable clock\n");
1945 goto free_endpoint;
1946 }
1947
1948 state->pdata.refclk_hz = clk_get_rate(refclk);
1949 state->pdata.ddc5v_delay = DDC5V_DELAY_100_MS;
1950 state->pdata.enable_hdcp = false;
1951 /*
1952 * Ideally the FIFO trigger level should be set based on the input and
1953 * output data rates, but the calculations required are buried in
1954 * Toshiba's register settings spreadsheet.
1955 * A value of 16 works with a 594Mbps data rate for 720p60 (using 2
1956 * lanes) and 1080p60 (using 4 lanes), but fails when the data rate
1957 * is increased, or a lower pixel clock is used that result in CSI
1958 * reading out faster than the data is arriving.
1959 *
1960 * A value of 374 works with both those modes at 594Mbps, and with most
1961 * modes on 972Mbps.
1962 */
1963 state->pdata.fifo_level = 374;
1964 /*
1965 * The PLL input clock is obtained by dividing refclk by pll_prd.
1966 * It must be between 6 MHz and 40 MHz, lower frequency is better.
1967 */
1968 switch (state->pdata.refclk_hz) {
1969 case 26000000:
1970 case 27000000:
1971 case 42000000:
1972 state->pdata.pll_prd = state->pdata.refclk_hz / 6000000;
1973 break;
1974 default:
1975 dev_err(dev, "unsupported refclk rate: %u Hz\n",
1976 state->pdata.refclk_hz);
1977 goto disable_clk;
1978 }
1979
1980 /*
1981 * The CSI bps per lane must be between 62.5 Mbps and 1 Gbps.
1982 * The default is 594 Mbps for 4-lane 1080p60 or 2-lane 720p60.
1983 */
1984 bps_pr_lane = 2 * endpoint.link_frequencies[0];
1985 if (bps_pr_lane < 62500000U || bps_pr_lane > 1000000000U) {
1986 dev_err(dev, "unsupported bps per lane: %u bps\n", bps_pr_lane);
1987 ret = -EINVAL;
1988 goto disable_clk;
1989 }
1990
1991 /* The CSI speed per lane is refclk / pll_prd * pll_fbd */
1992 state->pdata.pll_fbd = bps_pr_lane /
1993 state->pdata.refclk_hz * state->pdata.pll_prd;
1994
1995 /*
1996 * FIXME: These timings are from REF_02 for 594 Mbps per lane (297 MHz
1997 * link frequency). In principle it should be possible to calculate
1998 * them based on link frequency and resolution.
1999 */
2000 if (bps_pr_lane != 594000000U)
2001 dev_warn(dev, "untested bps per lane: %u bps\n", bps_pr_lane);
2002 state->pdata.lineinitcnt = 0xe80;
2003 state->pdata.lptxtimecnt = 0x003;
2004 /* tclk-preparecnt: 3, tclk-zerocnt: 20 */
2005 state->pdata.tclk_headercnt = 0x1403;
2006 state->pdata.tclk_trailcnt = 0x00;
2007 /* ths-preparecnt: 3, ths-zerocnt: 1 */
2008 state->pdata.ths_headercnt = 0x0103;
2009 state->pdata.twakeup = 0x4882;
2010 state->pdata.tclk_postcnt = 0x008;
2011 state->pdata.ths_trailcnt = 0x2;
2012 state->pdata.hstxvregcnt = 0;
2013
2014 state->reset_gpio = devm_gpiod_get_optional(dev, "reset",
2015 GPIOD_OUT_LOW);
2016 if (IS_ERR(state->reset_gpio)) {
2017 dev_err(dev, "failed to get reset gpio\n");
2018 ret = PTR_ERR(state->reset_gpio);
2019 goto disable_clk;
2020 }
2021
2022 if (state->reset_gpio)
2023 tc358743_gpio_reset(state);
2024
2025 ret = 0;
2026 goto free_endpoint;
2027
2028 disable_clk:
2029 clk_disable_unprepare(refclk);
2030 free_endpoint:
2031 v4l2_fwnode_endpoint_free(&endpoint);
2032 put_node:
2033 of_node_put(ep);
2034 return ret;
2035 }
2036 #else
tc358743_probe_of(struct tc358743_state * state)2037 static inline int tc358743_probe_of(struct tc358743_state *state)
2038 {
2039 return -ENODEV;
2040 }
2041 #endif
2042
tc358743_probe(struct i2c_client * client)2043 static int tc358743_probe(struct i2c_client *client)
2044 {
2045 static struct v4l2_dv_timings default_timing =
2046 V4L2_DV_BT_CEA_640X480P59_94;
2047 struct tc358743_state *state;
2048 struct tc358743_platform_data *pdata = client->dev.platform_data;
2049 struct v4l2_subdev *sd;
2050 u16 irq_mask = MASK_HDMI_MSK | MASK_CSI_MSK;
2051 u16 chipid;
2052 int err;
2053
2054 if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE_DATA))
2055 return -EIO;
2056 v4l_dbg(1, debug, client, "chip found @ 0x%x (%s)\n",
2057 client->addr << 1, client->adapter->name);
2058
2059 state = devm_kzalloc(&client->dev, sizeof(struct tc358743_state),
2060 GFP_KERNEL);
2061 if (!state)
2062 return -ENOMEM;
2063
2064 state->i2c_client = client;
2065
2066 /* platform data */
2067 if (pdata) {
2068 state->pdata = *pdata;
2069 state->bus.flags = 0;
2070 } else {
2071 err = tc358743_probe_of(state);
2072 if (err == -ENODEV)
2073 v4l_err(client, "No platform data!\n");
2074 if (err)
2075 return err;
2076 }
2077
2078 sd = &state->sd;
2079 v4l2_i2c_subdev_init(sd, client, &tc358743_ops);
2080 sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE | V4L2_SUBDEV_FL_HAS_EVENTS;
2081
2082 /* i2c access */
2083 if (i2c_rd16_err(sd, CHIPID, &chipid) ||
2084 (chipid & MASK_CHIPID) != 0) {
2085 v4l2_info(sd, "not a TC358743 on address 0x%x\n",
2086 client->addr << 1);
2087 return -ENODEV;
2088 }
2089
2090 /* control handlers */
2091 v4l2_ctrl_handler_init(&state->hdl, 3);
2092
2093 state->detect_tx_5v_ctrl = v4l2_ctrl_new_std(&state->hdl, NULL,
2094 V4L2_CID_DV_RX_POWER_PRESENT, 0, 1, 0, 0);
2095
2096 /* custom controls */
2097 state->audio_sampling_rate_ctrl = v4l2_ctrl_new_custom(&state->hdl,
2098 &tc358743_ctrl_audio_sampling_rate, NULL);
2099
2100 state->audio_present_ctrl = v4l2_ctrl_new_custom(&state->hdl,
2101 &tc358743_ctrl_audio_present, NULL);
2102
2103 sd->ctrl_handler = &state->hdl;
2104 if (state->hdl.error) {
2105 err = state->hdl.error;
2106 goto err_hdl;
2107 }
2108
2109 if (tc358743_update_controls(sd)) {
2110 err = -ENODEV;
2111 goto err_hdl;
2112 }
2113
2114 state->pad.flags = MEDIA_PAD_FL_SOURCE;
2115 sd->entity.function = MEDIA_ENT_F_VID_IF_BRIDGE;
2116 err = media_entity_pads_init(&sd->entity, 1, &state->pad);
2117 if (err < 0)
2118 goto err_hdl;
2119
2120 state->mbus_fmt_code = MEDIA_BUS_FMT_RGB888_1X24;
2121
2122 sd->dev = &client->dev;
2123
2124 mutex_init(&state->confctl_mutex);
2125
2126 INIT_DELAYED_WORK(&state->delayed_work_enable_hotplug,
2127 tc358743_delayed_work_enable_hotplug);
2128
2129 #ifdef CONFIG_VIDEO_TC358743_CEC
2130 state->cec_adap = cec_allocate_adapter(&tc358743_cec_adap_ops,
2131 state, dev_name(&client->dev),
2132 CEC_CAP_DEFAULTS | CEC_CAP_MONITOR_ALL, CEC_MAX_LOG_ADDRS);
2133 if (IS_ERR(state->cec_adap)) {
2134 err = PTR_ERR(state->cec_adap);
2135 goto err_hdl;
2136 }
2137 irq_mask |= MASK_CEC_RMSK | MASK_CEC_TMSK;
2138 #endif
2139
2140 tc358743_initial_setup(sd);
2141
2142 tc358743_s_dv_timings(sd, 0, &default_timing);
2143
2144 tc358743_set_csi_color_space(sd);
2145
2146 tc358743_init_interrupts(sd);
2147
2148 if (state->i2c_client->irq) {
2149 err = devm_request_threaded_irq(&client->dev,
2150 state->i2c_client->irq,
2151 NULL, tc358743_irq_handler,
2152 IRQF_TRIGGER_HIGH | IRQF_ONESHOT,
2153 "tc358743", state);
2154 if (err)
2155 goto err_work_queues;
2156 } else {
2157 INIT_WORK(&state->work_i2c_poll,
2158 tc358743_work_i2c_poll);
2159 timer_setup(&state->timer, tc358743_irq_poll_timer, 0);
2160 state->timer.expires = jiffies +
2161 msecs_to_jiffies(POLL_INTERVAL_MS);
2162 add_timer(&state->timer);
2163 }
2164
2165 err = cec_register_adapter(state->cec_adap, &client->dev);
2166 if (err < 0) {
2167 pr_err("%s: failed to register the cec device\n", __func__);
2168 cec_delete_adapter(state->cec_adap);
2169 state->cec_adap = NULL;
2170 goto err_work_queues;
2171 }
2172
2173 tc358743_enable_interrupts(sd, tx_5v_power_present(sd));
2174 i2c_wr16(sd, INTMASK, ~irq_mask);
2175
2176 err = v4l2_ctrl_handler_setup(sd->ctrl_handler);
2177 if (err)
2178 goto err_work_queues;
2179
2180 err = v4l2_async_register_subdev(sd);
2181 if (err < 0)
2182 goto err_work_queues;
2183
2184 v4l2_info(sd, "%s found @ 0x%x (%s)\n", client->name,
2185 client->addr << 1, client->adapter->name);
2186
2187 return 0;
2188
2189 err_work_queues:
2190 cec_unregister_adapter(state->cec_adap);
2191 if (!state->i2c_client->irq) {
2192 timer_delete_sync(&state->timer);
2193 flush_work(&state->work_i2c_poll);
2194 }
2195 cancel_delayed_work_sync(&state->delayed_work_enable_hotplug);
2196 mutex_destroy(&state->confctl_mutex);
2197 err_hdl:
2198 media_entity_cleanup(&sd->entity);
2199 v4l2_ctrl_handler_free(&state->hdl);
2200 return err;
2201 }
2202
tc358743_remove(struct i2c_client * client)2203 static void tc358743_remove(struct i2c_client *client)
2204 {
2205 struct v4l2_subdev *sd = i2c_get_clientdata(client);
2206 struct tc358743_state *state = to_state(sd);
2207
2208 if (!state->i2c_client->irq) {
2209 del_timer_sync(&state->timer);
2210 flush_work(&state->work_i2c_poll);
2211 }
2212 cancel_delayed_work_sync(&state->delayed_work_enable_hotplug);
2213 cec_unregister_adapter(state->cec_adap);
2214 v4l2_async_unregister_subdev(sd);
2215 v4l2_device_unregister_subdev(sd);
2216 mutex_destroy(&state->confctl_mutex);
2217 media_entity_cleanup(&sd->entity);
2218 v4l2_ctrl_handler_free(&state->hdl);
2219 }
2220
2221 static const struct i2c_device_id tc358743_id[] = {
2222 { "tc358743" },
2223 {}
2224 };
2225
2226 MODULE_DEVICE_TABLE(i2c, tc358743_id);
2227
2228 #if IS_ENABLED(CONFIG_OF)
2229 static const struct of_device_id tc358743_of_match[] = {
2230 { .compatible = "toshiba,tc358743" },
2231 {},
2232 };
2233 MODULE_DEVICE_TABLE(of, tc358743_of_match);
2234 #endif
2235
2236 static struct i2c_driver tc358743_driver = {
2237 .driver = {
2238 .name = "tc358743",
2239 .of_match_table = of_match_ptr(tc358743_of_match),
2240 },
2241 .probe = tc358743_probe,
2242 .remove = tc358743_remove,
2243 .id_table = tc358743_id,
2244 };
2245
2246 module_i2c_driver(tc358743_driver);
2247