1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Hantro VPU codec driver
4 *
5 * Copyright (C) 2018 Rockchip Electronics Co., Ltd.
6 * Jeffy Chen <jeffy.chen@rock-chips.com>
7 */
8
9 #include <linux/clk.h>
10
11 #include "hantro.h"
12 #include "hantro_jpeg.h"
13 #include "hantro_g1_regs.h"
14 #include "hantro_h1_regs.h"
15 #include "rockchip_vpu2_regs.h"
16 #include "rockchip_vpu981_regs.h"
17
18 #define RK3066_ACLK_MAX_FREQ (300 * 1000 * 1000)
19 #define RK3288_ACLK_MAX_FREQ (400 * 1000 * 1000)
20
21 #define ROCKCHIP_VPU981_MIN_SIZE 64
22
23 /*
24 * Supported formats.
25 */
26
27 static const struct hantro_fmt rockchip_vpu_enc_fmts[] = {
28 {
29 .fourcc = V4L2_PIX_FMT_YUV420M,
30 .codec_mode = HANTRO_MODE_NONE,
31 .enc_fmt = ROCKCHIP_VPU_ENC_FMT_YUV420P,
32 },
33 {
34 .fourcc = V4L2_PIX_FMT_NV12M,
35 .codec_mode = HANTRO_MODE_NONE,
36 .enc_fmt = ROCKCHIP_VPU_ENC_FMT_YUV420SP,
37 },
38 {
39 .fourcc = V4L2_PIX_FMT_YUYV,
40 .codec_mode = HANTRO_MODE_NONE,
41 .enc_fmt = ROCKCHIP_VPU_ENC_FMT_YUYV422,
42 },
43 {
44 .fourcc = V4L2_PIX_FMT_UYVY,
45 .codec_mode = HANTRO_MODE_NONE,
46 .enc_fmt = ROCKCHIP_VPU_ENC_FMT_UYVY422,
47 },
48 {
49 .fourcc = V4L2_PIX_FMT_JPEG,
50 .codec_mode = HANTRO_MODE_JPEG_ENC,
51 .max_depth = 2,
52 .header_size = JPEG_HEADER_SIZE,
53 .frmsize = {
54 .min_width = 96,
55 .max_width = 8192,
56 .step_width = MB_DIM,
57 .min_height = 32,
58 .max_height = 8192,
59 .step_height = MB_DIM,
60 },
61 },
62 };
63
64 static const struct hantro_fmt rockchip_vpu1_postproc_fmts[] = {
65 {
66 .fourcc = V4L2_PIX_FMT_YUYV,
67 .codec_mode = HANTRO_MODE_NONE,
68 .postprocessed = true,
69 .frmsize = {
70 .min_width = FMT_MIN_WIDTH,
71 .max_width = FMT_FHD_WIDTH,
72 .step_width = MB_DIM,
73 .min_height = FMT_MIN_HEIGHT,
74 .max_height = FMT_FHD_HEIGHT,
75 .step_height = MB_DIM,
76 },
77 },
78 };
79
80 static const struct hantro_fmt rockchip_vpu981_postproc_fmts[] = {
81 {
82 .fourcc = V4L2_PIX_FMT_NV12,
83 .codec_mode = HANTRO_MODE_NONE,
84 .postprocessed = true,
85 .frmsize = {
86 .min_width = ROCKCHIP_VPU981_MIN_SIZE,
87 .max_width = FMT_UHD_WIDTH,
88 .step_width = MB_DIM,
89 .min_height = ROCKCHIP_VPU981_MIN_SIZE,
90 .max_height = FMT_UHD_HEIGHT,
91 .step_height = MB_DIM,
92 },
93 },
94 {
95 .fourcc = V4L2_PIX_FMT_P010,
96 .codec_mode = HANTRO_MODE_NONE,
97 .match_depth = true,
98 .postprocessed = true,
99 .frmsize = {
100 .min_width = ROCKCHIP_VPU981_MIN_SIZE,
101 .max_width = FMT_UHD_WIDTH,
102 .step_width = MB_DIM,
103 .min_height = ROCKCHIP_VPU981_MIN_SIZE,
104 .max_height = FMT_UHD_HEIGHT,
105 .step_height = MB_DIM,
106 },
107 },
108 };
109
110 static const struct hantro_fmt rk3066_vpu_dec_fmts[] = {
111 {
112 .fourcc = V4L2_PIX_FMT_NV12,
113 .codec_mode = HANTRO_MODE_NONE,
114 .frmsize = {
115 .min_width = FMT_MIN_WIDTH,
116 .max_width = FMT_FHD_WIDTH,
117 .step_width = MB_DIM,
118 .min_height = FMT_MIN_HEIGHT,
119 .max_height = FMT_FHD_HEIGHT,
120 .step_height = MB_DIM,
121 },
122 },
123 {
124 .fourcc = V4L2_PIX_FMT_H264_SLICE,
125 .codec_mode = HANTRO_MODE_H264_DEC,
126 .max_depth = 2,
127 .frmsize = {
128 .min_width = FMT_MIN_WIDTH,
129 .max_width = FMT_FHD_WIDTH,
130 .step_width = MB_DIM,
131 .min_height = FMT_MIN_HEIGHT,
132 .max_height = FMT_FHD_HEIGHT,
133 .step_height = MB_DIM,
134 },
135 },
136 {
137 .fourcc = V4L2_PIX_FMT_MPEG2_SLICE,
138 .codec_mode = HANTRO_MODE_MPEG2_DEC,
139 .max_depth = 2,
140 .frmsize = {
141 .min_width = FMT_MIN_WIDTH,
142 .max_width = FMT_FHD_WIDTH,
143 .step_width = MB_DIM,
144 .min_height = FMT_MIN_HEIGHT,
145 .max_height = FMT_FHD_HEIGHT,
146 .step_height = MB_DIM,
147 },
148 },
149 {
150 .fourcc = V4L2_PIX_FMT_VP8_FRAME,
151 .codec_mode = HANTRO_MODE_VP8_DEC,
152 .max_depth = 2,
153 .frmsize = {
154 .min_width = FMT_MIN_WIDTH,
155 .max_width = FMT_FHD_WIDTH,
156 .step_width = MB_DIM,
157 .min_height = FMT_MIN_HEIGHT,
158 .max_height = FMT_FHD_HEIGHT,
159 .step_height = MB_DIM,
160 },
161 },
162 };
163
164 static const struct hantro_fmt rk3288_vpu_dec_fmts[] = {
165 {
166 .fourcc = V4L2_PIX_FMT_NV12,
167 .codec_mode = HANTRO_MODE_NONE,
168 .frmsize = {
169 .min_width = FMT_MIN_WIDTH,
170 .max_width = FMT_4K_WIDTH,
171 .step_width = MB_DIM,
172 .min_height = FMT_MIN_HEIGHT,
173 .max_height = FMT_4K_HEIGHT,
174 .step_height = MB_DIM,
175 },
176 },
177 {
178 .fourcc = V4L2_PIX_FMT_H264_SLICE,
179 .codec_mode = HANTRO_MODE_H264_DEC,
180 .max_depth = 2,
181 .frmsize = {
182 .min_width = FMT_MIN_WIDTH,
183 .max_width = FMT_4K_WIDTH,
184 .step_width = MB_DIM,
185 .min_height = FMT_MIN_HEIGHT,
186 .max_height = FMT_4K_HEIGHT,
187 .step_height = MB_DIM,
188 },
189 },
190 {
191 .fourcc = V4L2_PIX_FMT_MPEG2_SLICE,
192 .codec_mode = HANTRO_MODE_MPEG2_DEC,
193 .max_depth = 2,
194 .frmsize = {
195 .min_width = FMT_MIN_WIDTH,
196 .max_width = FMT_FHD_WIDTH,
197 .step_width = MB_DIM,
198 .min_height = FMT_MIN_HEIGHT,
199 .max_height = FMT_FHD_HEIGHT,
200 .step_height = MB_DIM,
201 },
202 },
203 {
204 .fourcc = V4L2_PIX_FMT_VP8_FRAME,
205 .codec_mode = HANTRO_MODE_VP8_DEC,
206 .max_depth = 2,
207 .frmsize = {
208 .min_width = FMT_MIN_WIDTH,
209 .max_width = FMT_UHD_WIDTH,
210 .step_width = MB_DIM,
211 .min_height = FMT_MIN_HEIGHT,
212 .max_height = FMT_UHD_HEIGHT,
213 .step_height = MB_DIM,
214 },
215 },
216 };
217
218 static const struct hantro_fmt rockchip_vdpu2_dec_fmts[] = {
219 {
220 .fourcc = V4L2_PIX_FMT_NV12,
221 .codec_mode = HANTRO_MODE_NONE,
222 .frmsize = {
223 .min_width = FMT_MIN_WIDTH,
224 .max_width = FMT_FHD_WIDTH,
225 .step_width = MB_DIM,
226 .min_height = FMT_MIN_HEIGHT,
227 .max_height = FMT_FHD_HEIGHT,
228 .step_height = MB_DIM,
229 },
230 },
231 {
232 .fourcc = V4L2_PIX_FMT_H264_SLICE,
233 .codec_mode = HANTRO_MODE_H264_DEC,
234 .max_depth = 2,
235 .frmsize = {
236 .min_width = FMT_MIN_WIDTH,
237 .max_width = FMT_FHD_WIDTH,
238 .step_width = MB_DIM,
239 .min_height = FMT_MIN_HEIGHT,
240 .max_height = FMT_FHD_HEIGHT,
241 .step_height = MB_DIM,
242 },
243 },
244 {
245 .fourcc = V4L2_PIX_FMT_MPEG2_SLICE,
246 .codec_mode = HANTRO_MODE_MPEG2_DEC,
247 .max_depth = 2,
248 .frmsize = {
249 .min_width = FMT_MIN_WIDTH,
250 .max_width = FMT_FHD_WIDTH,
251 .step_width = MB_DIM,
252 .min_height = FMT_MIN_HEIGHT,
253 .max_height = FMT_FHD_HEIGHT,
254 .step_height = MB_DIM,
255 },
256 },
257 {
258 .fourcc = V4L2_PIX_FMT_VP8_FRAME,
259 .codec_mode = HANTRO_MODE_VP8_DEC,
260 .max_depth = 2,
261 .frmsize = {
262 .min_width = FMT_MIN_WIDTH,
263 .max_width = FMT_UHD_WIDTH,
264 .step_width = MB_DIM,
265 .min_height = FMT_MIN_HEIGHT,
266 .max_height = FMT_UHD_HEIGHT,
267 .step_height = MB_DIM,
268 },
269 },
270 };
271
272 static const struct hantro_fmt rk3399_vpu_dec_fmts[] = {
273 {
274 .fourcc = V4L2_PIX_FMT_NV12,
275 .codec_mode = HANTRO_MODE_NONE,
276 .frmsize = {
277 .min_width = FMT_MIN_WIDTH,
278 .max_width = FMT_FHD_WIDTH,
279 .step_width = MB_DIM,
280 .min_height = FMT_MIN_HEIGHT,
281 .max_height = FMT_FHD_HEIGHT,
282 .step_height = MB_DIM,
283 },
284 },
285 {
286 .fourcc = V4L2_PIX_FMT_MPEG2_SLICE,
287 .codec_mode = HANTRO_MODE_MPEG2_DEC,
288 .max_depth = 2,
289 .frmsize = {
290 .min_width = FMT_MIN_WIDTH,
291 .max_width = FMT_FHD_WIDTH,
292 .step_width = MB_DIM,
293 .min_height = FMT_MIN_HEIGHT,
294 .max_height = FMT_FHD_HEIGHT,
295 .step_height = MB_DIM,
296 },
297 },
298 {
299 .fourcc = V4L2_PIX_FMT_VP8_FRAME,
300 .codec_mode = HANTRO_MODE_VP8_DEC,
301 .max_depth = 2,
302 .frmsize = {
303 .min_width = FMT_MIN_WIDTH,
304 .max_width = FMT_UHD_WIDTH,
305 .step_width = MB_DIM,
306 .min_height = FMT_MIN_HEIGHT,
307 .max_height = FMT_UHD_HEIGHT,
308 .step_height = MB_DIM,
309 },
310 },
311 };
312
313 static const struct hantro_fmt rockchip_vpu981_dec_fmts[] = {
314 {
315 .fourcc = V4L2_PIX_FMT_NV12_4L4,
316 .codec_mode = HANTRO_MODE_NONE,
317 .match_depth = true,
318 .frmsize = {
319 .min_width = ROCKCHIP_VPU981_MIN_SIZE,
320 .max_width = FMT_UHD_WIDTH,
321 .step_width = MB_DIM,
322 .min_height = ROCKCHIP_VPU981_MIN_SIZE,
323 .max_height = FMT_UHD_HEIGHT,
324 .step_height = MB_DIM,
325 },
326 },
327 {
328 .fourcc = V4L2_PIX_FMT_NV15_4L4,
329 .codec_mode = HANTRO_MODE_NONE,
330 .match_depth = true,
331 .frmsize = {
332 .min_width = ROCKCHIP_VPU981_MIN_SIZE,
333 .max_width = FMT_UHD_WIDTH,
334 .step_width = MB_DIM,
335 .min_height = ROCKCHIP_VPU981_MIN_SIZE,
336 .max_height = FMT_UHD_HEIGHT,
337 .step_height = MB_DIM,
338 },
339 },
340 {
341 .fourcc = V4L2_PIX_FMT_AV1_FRAME,
342 .codec_mode = HANTRO_MODE_AV1_DEC,
343 .max_depth = 2,
344 .frmsize = {
345 .min_width = ROCKCHIP_VPU981_MIN_SIZE,
346 .max_width = FMT_UHD_WIDTH,
347 .step_width = MB_DIM,
348 .min_height = ROCKCHIP_VPU981_MIN_SIZE,
349 .max_height = FMT_UHD_HEIGHT,
350 .step_height = MB_DIM,
351 },
352 },
353 };
354
rockchip_vpu1_vepu_irq(int irq,void * dev_id)355 static irqreturn_t rockchip_vpu1_vepu_irq(int irq, void *dev_id)
356 {
357 struct hantro_dev *vpu = dev_id;
358 enum vb2_buffer_state state;
359 u32 status;
360
361 status = vepu_read(vpu, H1_REG_INTERRUPT);
362 state = (status & H1_REG_INTERRUPT_FRAME_RDY) ?
363 VB2_BUF_STATE_DONE : VB2_BUF_STATE_ERROR;
364
365 vepu_write(vpu, 0, H1_REG_INTERRUPT);
366 vepu_write(vpu, 0, H1_REG_AXI_CTRL);
367
368 hantro_irq_done(vpu, state);
369
370 return IRQ_HANDLED;
371 }
372
rockchip_vpu2_vdpu_irq(int irq,void * dev_id)373 static irqreturn_t rockchip_vpu2_vdpu_irq(int irq, void *dev_id)
374 {
375 struct hantro_dev *vpu = dev_id;
376 enum vb2_buffer_state state;
377 u32 status;
378
379 status = vdpu_read(vpu, VDPU_REG_INTERRUPT);
380 state = (status & VDPU_REG_INTERRUPT_DEC_IRQ) ?
381 VB2_BUF_STATE_DONE : VB2_BUF_STATE_ERROR;
382
383 vdpu_write(vpu, 0, VDPU_REG_INTERRUPT);
384 vdpu_write(vpu, 0, VDPU_REG_AXI_CTRL);
385
386 hantro_irq_done(vpu, state);
387
388 return IRQ_HANDLED;
389 }
390
rockchip_vpu2_vepu_irq(int irq,void * dev_id)391 static irqreturn_t rockchip_vpu2_vepu_irq(int irq, void *dev_id)
392 {
393 struct hantro_dev *vpu = dev_id;
394 enum vb2_buffer_state state;
395 u32 status;
396
397 status = vepu_read(vpu, VEPU_REG_INTERRUPT);
398 state = (status & VEPU_REG_INTERRUPT_FRAME_READY) ?
399 VB2_BUF_STATE_DONE : VB2_BUF_STATE_ERROR;
400
401 vepu_write(vpu, 0, VEPU_REG_INTERRUPT);
402 vepu_write(vpu, 0, VEPU_REG_AXI_CTRL);
403
404 hantro_irq_done(vpu, state);
405
406 return IRQ_HANDLED;
407 }
408
rk3588_vpu981_irq(int irq,void * dev_id)409 static irqreturn_t rk3588_vpu981_irq(int irq, void *dev_id)
410 {
411 struct hantro_dev *vpu = dev_id;
412 enum vb2_buffer_state state;
413 u32 status;
414
415 status = vdpu_read(vpu, AV1_REG_INTERRUPT);
416 state = (status & AV1_REG_INTERRUPT_DEC_RDY_INT) ?
417 VB2_BUF_STATE_DONE : VB2_BUF_STATE_ERROR;
418
419 vdpu_write(vpu, 0, AV1_REG_INTERRUPT);
420 vdpu_write(vpu, AV1_REG_CONFIG_DEC_CLK_GATE_E, AV1_REG_CONFIG);
421
422 hantro_irq_done(vpu, state);
423
424 return IRQ_HANDLED;
425 }
426
rk3036_vpu_hw_init(struct hantro_dev * vpu)427 static int rk3036_vpu_hw_init(struct hantro_dev *vpu)
428 {
429 /* Bump ACLK to max. possible freq. to improve performance. */
430 clk_set_rate(vpu->clocks[0].clk, RK3066_ACLK_MAX_FREQ);
431 return 0;
432 }
433
rk3066_vpu_hw_init(struct hantro_dev * vpu)434 static int rk3066_vpu_hw_init(struct hantro_dev *vpu)
435 {
436 /* Bump ACLKs to max. possible freq. to improve performance. */
437 clk_set_rate(vpu->clocks[0].clk, RK3066_ACLK_MAX_FREQ);
438 clk_set_rate(vpu->clocks[2].clk, RK3066_ACLK_MAX_FREQ);
439 return 0;
440 }
441
rockchip_vpu_hw_init(struct hantro_dev * vpu)442 static int rockchip_vpu_hw_init(struct hantro_dev *vpu)
443 {
444 /* Bump ACLK to max. possible freq. to improve performance. */
445 clk_set_rate(vpu->clocks[0].clk, RK3288_ACLK_MAX_FREQ);
446 return 0;
447 }
448
rk3066_vpu_dec_reset(struct hantro_ctx * ctx)449 static void rk3066_vpu_dec_reset(struct hantro_ctx *ctx)
450 {
451 struct hantro_dev *vpu = ctx->dev;
452
453 vdpu_write(vpu, G1_REG_INTERRUPT_DEC_IRQ_DIS, G1_REG_INTERRUPT);
454 vdpu_write(vpu, G1_REG_CONFIG_DEC_CLK_GATE_E, G1_REG_CONFIG);
455 }
456
rockchip_vpu1_enc_reset(struct hantro_ctx * ctx)457 static void rockchip_vpu1_enc_reset(struct hantro_ctx *ctx)
458 {
459 struct hantro_dev *vpu = ctx->dev;
460
461 vepu_write(vpu, H1_REG_INTERRUPT_DIS_BIT, H1_REG_INTERRUPT);
462 vepu_write(vpu, 0, H1_REG_ENC_CTRL);
463 vepu_write(vpu, 0, H1_REG_AXI_CTRL);
464 }
465
rockchip_vpu2_dec_reset(struct hantro_ctx * ctx)466 static void rockchip_vpu2_dec_reset(struct hantro_ctx *ctx)
467 {
468 struct hantro_dev *vpu = ctx->dev;
469
470 vdpu_write(vpu, VDPU_REG_INTERRUPT_DEC_IRQ_DIS, VDPU_REG_INTERRUPT);
471 vdpu_write(vpu, 0, VDPU_REG_EN_FLAGS);
472 vdpu_write(vpu, 1, VDPU_REG_SOFT_RESET);
473 }
474
rockchip_vpu2_enc_reset(struct hantro_ctx * ctx)475 static void rockchip_vpu2_enc_reset(struct hantro_ctx *ctx)
476 {
477 struct hantro_dev *vpu = ctx->dev;
478
479 vepu_write(vpu, VEPU_REG_INTERRUPT_DIS_BIT, VEPU_REG_INTERRUPT);
480 vepu_write(vpu, 0, VEPU_REG_ENCODE_START);
481 vepu_write(vpu, 0, VEPU_REG_AXI_CTRL);
482 }
483
484 /*
485 * Supported codec ops.
486 */
487 static const struct hantro_codec_ops rk3036_vpu_codec_ops[] = {
488 [HANTRO_MODE_H264_DEC] = {
489 .run = hantro_g1_h264_dec_run,
490 .reset = hantro_g1_reset,
491 .init = hantro_h264_dec_init,
492 .exit = hantro_h264_dec_exit,
493 },
494 [HANTRO_MODE_MPEG2_DEC] = {
495 .run = hantro_g1_mpeg2_dec_run,
496 .reset = hantro_g1_reset,
497 .init = hantro_mpeg2_dec_init,
498 .exit = hantro_mpeg2_dec_exit,
499 },
500 [HANTRO_MODE_VP8_DEC] = {
501 .run = hantro_g1_vp8_dec_run,
502 .reset = hantro_g1_reset,
503 .init = hantro_vp8_dec_init,
504 .exit = hantro_vp8_dec_exit,
505 },
506 };
507
508 static const struct hantro_codec_ops rk3066_vpu_codec_ops[] = {
509 [HANTRO_MODE_JPEG_ENC] = {
510 .run = hantro_h1_jpeg_enc_run,
511 .reset = rockchip_vpu1_enc_reset,
512 .done = hantro_h1_jpeg_enc_done,
513 },
514 [HANTRO_MODE_H264_DEC] = {
515 .run = hantro_g1_h264_dec_run,
516 .reset = rk3066_vpu_dec_reset,
517 .init = hantro_h264_dec_init,
518 .exit = hantro_h264_dec_exit,
519 },
520 [HANTRO_MODE_MPEG2_DEC] = {
521 .run = hantro_g1_mpeg2_dec_run,
522 .reset = rk3066_vpu_dec_reset,
523 .init = hantro_mpeg2_dec_init,
524 .exit = hantro_mpeg2_dec_exit,
525 },
526 [HANTRO_MODE_VP8_DEC] = {
527 .run = hantro_g1_vp8_dec_run,
528 .reset = rk3066_vpu_dec_reset,
529 .init = hantro_vp8_dec_init,
530 .exit = hantro_vp8_dec_exit,
531 },
532 };
533
534 static const struct hantro_codec_ops rk3288_vpu_codec_ops[] = {
535 [HANTRO_MODE_JPEG_ENC] = {
536 .run = hantro_h1_jpeg_enc_run,
537 .reset = rockchip_vpu1_enc_reset,
538 .done = hantro_h1_jpeg_enc_done,
539 },
540 [HANTRO_MODE_H264_DEC] = {
541 .run = hantro_g1_h264_dec_run,
542 .reset = hantro_g1_reset,
543 .init = hantro_h264_dec_init,
544 .exit = hantro_h264_dec_exit,
545 },
546 [HANTRO_MODE_MPEG2_DEC] = {
547 .run = hantro_g1_mpeg2_dec_run,
548 .reset = hantro_g1_reset,
549 .init = hantro_mpeg2_dec_init,
550 .exit = hantro_mpeg2_dec_exit,
551 },
552 [HANTRO_MODE_VP8_DEC] = {
553 .run = hantro_g1_vp8_dec_run,
554 .reset = hantro_g1_reset,
555 .init = hantro_vp8_dec_init,
556 .exit = hantro_vp8_dec_exit,
557 },
558 };
559
560 static const struct hantro_codec_ops rk3399_vpu_codec_ops[] = {
561 [HANTRO_MODE_JPEG_ENC] = {
562 .run = rockchip_vpu2_jpeg_enc_run,
563 .reset = rockchip_vpu2_enc_reset,
564 .done = rockchip_vpu2_jpeg_enc_done,
565 },
566 [HANTRO_MODE_H264_DEC] = {
567 .run = rockchip_vpu2_h264_dec_run,
568 .reset = rockchip_vpu2_dec_reset,
569 .init = hantro_h264_dec_init,
570 .exit = hantro_h264_dec_exit,
571 },
572 [HANTRO_MODE_MPEG2_DEC] = {
573 .run = rockchip_vpu2_mpeg2_dec_run,
574 .reset = rockchip_vpu2_dec_reset,
575 .init = hantro_mpeg2_dec_init,
576 .exit = hantro_mpeg2_dec_exit,
577 },
578 [HANTRO_MODE_VP8_DEC] = {
579 .run = rockchip_vpu2_vp8_dec_run,
580 .reset = rockchip_vpu2_dec_reset,
581 .init = hantro_vp8_dec_init,
582 .exit = hantro_vp8_dec_exit,
583 },
584 };
585
586 static const struct hantro_codec_ops rk3568_vepu_codec_ops[] = {
587 [HANTRO_MODE_JPEG_ENC] = {
588 .run = rockchip_vpu2_jpeg_enc_run,
589 .reset = rockchip_vpu2_enc_reset,
590 .done = rockchip_vpu2_jpeg_enc_done,
591 },
592 };
593
594 static const struct hantro_codec_ops rk3588_vpu981_codec_ops[] = {
595 [HANTRO_MODE_AV1_DEC] = {
596 .run = rockchip_vpu981_av1_dec_run,
597 .init = rockchip_vpu981_av1_dec_init,
598 .exit = rockchip_vpu981_av1_dec_exit,
599 .done = rockchip_vpu981_av1_dec_done,
600 },
601 };
602 /*
603 * VPU variant.
604 */
605
606 static const struct hantro_irq rockchip_vdpu1_irqs[] = {
607 { "vdpu", hantro_g1_irq },
608 };
609
610 static const struct hantro_irq rockchip_vpu1_irqs[] = {
611 { "vepu", rockchip_vpu1_vepu_irq },
612 { "vdpu", hantro_g1_irq },
613 };
614
615 static const struct hantro_irq rockchip_vdpu2_irqs[] = {
616 { "vdpu", rockchip_vpu2_vdpu_irq },
617 };
618
619 static const struct hantro_irq rockchip_vpu2_irqs[] = {
620 { "vepu", rockchip_vpu2_vepu_irq },
621 { "vdpu", rockchip_vpu2_vdpu_irq },
622 };
623
624 static const struct hantro_irq rk3568_vepu_irqs[] = {
625 { "vepu", rockchip_vpu2_vepu_irq },
626 };
627
628 static const char * const rk3066_vpu_clk_names[] = {
629 "aclk_vdpu", "hclk_vdpu",
630 "aclk_vepu", "hclk_vepu"
631 };
632
633 static const struct hantro_irq rk3588_vpu981_irqs[] = {
634 { "vdpu", rk3588_vpu981_irq },
635 };
636
637 static const char * const rockchip_vpu_clk_names[] = {
638 "aclk", "hclk"
639 };
640
641 static const char * const rk3588_vpu981_vpu_clk_names[] = {
642 "aclk", "hclk",
643 };
644
645 /* VDPU1/VEPU1 */
646
647 const struct hantro_variant rk3036_vpu_variant = {
648 .dec_offset = 0x400,
649 .dec_fmts = rk3066_vpu_dec_fmts,
650 .num_dec_fmts = ARRAY_SIZE(rk3066_vpu_dec_fmts),
651 .postproc_fmts = rockchip_vpu1_postproc_fmts,
652 .num_postproc_fmts = ARRAY_SIZE(rockchip_vpu1_postproc_fmts),
653 .postproc_ops = &hantro_g1_postproc_ops,
654 .codec = HANTRO_MPEG2_DECODER | HANTRO_VP8_DECODER |
655 HANTRO_H264_DECODER,
656 .codec_ops = rk3036_vpu_codec_ops,
657 .irqs = rockchip_vdpu1_irqs,
658 .num_irqs = ARRAY_SIZE(rockchip_vdpu1_irqs),
659 .init = rk3036_vpu_hw_init,
660 .clk_names = rockchip_vpu_clk_names,
661 .num_clocks = ARRAY_SIZE(rockchip_vpu_clk_names)
662 };
663
664 /*
665 * Despite this variant has separate clocks for decoder and encoder,
666 * it's still required to enable all four of them for either decoding
667 * or encoding and we can't split it in separate g1/h1 variants.
668 */
669 const struct hantro_variant rk3066_vpu_variant = {
670 .enc_offset = 0x0,
671 .enc_fmts = rockchip_vpu_enc_fmts,
672 .num_enc_fmts = ARRAY_SIZE(rockchip_vpu_enc_fmts),
673 .dec_offset = 0x400,
674 .dec_fmts = rk3066_vpu_dec_fmts,
675 .num_dec_fmts = ARRAY_SIZE(rk3066_vpu_dec_fmts),
676 .postproc_fmts = rockchip_vpu1_postproc_fmts,
677 .num_postproc_fmts = ARRAY_SIZE(rockchip_vpu1_postproc_fmts),
678 .postproc_ops = &hantro_g1_postproc_ops,
679 .codec = HANTRO_JPEG_ENCODER | HANTRO_MPEG2_DECODER |
680 HANTRO_VP8_DECODER | HANTRO_H264_DECODER,
681 .codec_ops = rk3066_vpu_codec_ops,
682 .irqs = rockchip_vpu1_irqs,
683 .num_irqs = ARRAY_SIZE(rockchip_vpu1_irqs),
684 .init = rk3066_vpu_hw_init,
685 .clk_names = rk3066_vpu_clk_names,
686 .num_clocks = ARRAY_SIZE(rk3066_vpu_clk_names)
687 };
688
689 const struct hantro_variant rk3288_vpu_variant = {
690 .enc_offset = 0x0,
691 .enc_fmts = rockchip_vpu_enc_fmts,
692 .num_enc_fmts = ARRAY_SIZE(rockchip_vpu_enc_fmts),
693 .dec_offset = 0x400,
694 .dec_fmts = rk3288_vpu_dec_fmts,
695 .num_dec_fmts = ARRAY_SIZE(rk3288_vpu_dec_fmts),
696 .postproc_fmts = rockchip_vpu1_postproc_fmts,
697 .num_postproc_fmts = ARRAY_SIZE(rockchip_vpu1_postproc_fmts),
698 .postproc_ops = &hantro_g1_postproc_ops,
699 .codec = HANTRO_JPEG_ENCODER | HANTRO_MPEG2_DECODER |
700 HANTRO_VP8_DECODER | HANTRO_H264_DECODER,
701 .codec_ops = rk3288_vpu_codec_ops,
702 .irqs = rockchip_vpu1_irqs,
703 .num_irqs = ARRAY_SIZE(rockchip_vpu1_irqs),
704 .init = rockchip_vpu_hw_init,
705 .clk_names = rockchip_vpu_clk_names,
706 .num_clocks = ARRAY_SIZE(rockchip_vpu_clk_names)
707 };
708
709 /* VDPU2/VEPU2 */
710
711 const struct hantro_variant rk3328_vpu_variant = {
712 .dec_offset = 0x400,
713 .dec_fmts = rockchip_vdpu2_dec_fmts,
714 .num_dec_fmts = ARRAY_SIZE(rockchip_vdpu2_dec_fmts),
715 .codec = HANTRO_MPEG2_DECODER | HANTRO_VP8_DECODER |
716 HANTRO_H264_DECODER,
717 .codec_ops = rk3399_vpu_codec_ops,
718 .irqs = rockchip_vdpu2_irqs,
719 .num_irqs = ARRAY_SIZE(rockchip_vdpu2_irqs),
720 .init = rockchip_vpu_hw_init,
721 .clk_names = rockchip_vpu_clk_names,
722 .num_clocks = ARRAY_SIZE(rockchip_vpu_clk_names),
723 };
724
725 /*
726 * H.264 decoding explicitly disabled in RK3399.
727 * This ensures userspace applications use the Rockchip VDEC core,
728 * which has better performance.
729 */
730 const struct hantro_variant rk3399_vpu_variant = {
731 .enc_offset = 0x0,
732 .enc_fmts = rockchip_vpu_enc_fmts,
733 .num_enc_fmts = ARRAY_SIZE(rockchip_vpu_enc_fmts),
734 .dec_offset = 0x400,
735 .dec_fmts = rk3399_vpu_dec_fmts,
736 .num_dec_fmts = ARRAY_SIZE(rk3399_vpu_dec_fmts),
737 .codec = HANTRO_JPEG_ENCODER | HANTRO_MPEG2_DECODER |
738 HANTRO_VP8_DECODER,
739 .codec_ops = rk3399_vpu_codec_ops,
740 .irqs = rockchip_vpu2_irqs,
741 .num_irqs = ARRAY_SIZE(rockchip_vpu2_irqs),
742 .init = rockchip_vpu_hw_init,
743 .clk_names = rockchip_vpu_clk_names,
744 .num_clocks = ARRAY_SIZE(rockchip_vpu_clk_names)
745 };
746
747 const struct hantro_variant rk3568_vepu_variant = {
748 .enc_offset = 0x0,
749 .enc_fmts = rockchip_vpu_enc_fmts,
750 .num_enc_fmts = ARRAY_SIZE(rockchip_vpu_enc_fmts),
751 .codec = HANTRO_JPEG_ENCODER,
752 .codec_ops = rk3568_vepu_codec_ops,
753 .irqs = rk3568_vepu_irqs,
754 .num_irqs = ARRAY_SIZE(rk3568_vepu_irqs),
755 .init = rockchip_vpu_hw_init,
756 .clk_names = rockchip_vpu_clk_names,
757 .num_clocks = ARRAY_SIZE(rockchip_vpu_clk_names)
758 };
759
760 const struct hantro_variant rk3568_vpu_variant = {
761 .dec_offset = 0x400,
762 .dec_fmts = rockchip_vdpu2_dec_fmts,
763 .num_dec_fmts = ARRAY_SIZE(rockchip_vdpu2_dec_fmts),
764 .codec = HANTRO_MPEG2_DECODER |
765 HANTRO_VP8_DECODER | HANTRO_H264_DECODER,
766 .codec_ops = rk3399_vpu_codec_ops,
767 .irqs = rockchip_vdpu2_irqs,
768 .num_irqs = ARRAY_SIZE(rockchip_vdpu2_irqs),
769 .init = rockchip_vpu_hw_init,
770 .clk_names = rockchip_vpu_clk_names,
771 .num_clocks = ARRAY_SIZE(rockchip_vpu_clk_names)
772 };
773
774 const struct hantro_variant px30_vpu_variant = {
775 .enc_offset = 0x0,
776 .enc_fmts = rockchip_vpu_enc_fmts,
777 .num_enc_fmts = ARRAY_SIZE(rockchip_vpu_enc_fmts),
778 .dec_offset = 0x400,
779 .dec_fmts = rockchip_vdpu2_dec_fmts,
780 .num_dec_fmts = ARRAY_SIZE(rockchip_vdpu2_dec_fmts),
781 .codec = HANTRO_JPEG_ENCODER | HANTRO_MPEG2_DECODER |
782 HANTRO_VP8_DECODER | HANTRO_H264_DECODER,
783 .codec_ops = rk3399_vpu_codec_ops,
784 .irqs = rockchip_vpu2_irqs,
785 .num_irqs = ARRAY_SIZE(rockchip_vpu2_irqs),
786 .init = rk3036_vpu_hw_init,
787 .clk_names = rockchip_vpu_clk_names,
788 .num_clocks = ARRAY_SIZE(rockchip_vpu_clk_names)
789 };
790
791 const struct hantro_variant rk3588_vpu981_variant = {
792 .dec_offset = 0x0,
793 .dec_fmts = rockchip_vpu981_dec_fmts,
794 .num_dec_fmts = ARRAY_SIZE(rockchip_vpu981_dec_fmts),
795 .postproc_fmts = rockchip_vpu981_postproc_fmts,
796 .num_postproc_fmts = ARRAY_SIZE(rockchip_vpu981_postproc_fmts),
797 .postproc_ops = &rockchip_vpu981_postproc_ops,
798 .codec = HANTRO_AV1_DECODER,
799 .codec_ops = rk3588_vpu981_codec_ops,
800 .irqs = rk3588_vpu981_irqs,
801 .num_irqs = ARRAY_SIZE(rk3588_vpu981_irqs),
802 .clk_names = rk3588_vpu981_vpu_clk_names,
803 .num_clocks = ARRAY_SIZE(rk3588_vpu981_vpu_clk_names)
804 };
805