1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * MFD core driver for Intel Broxton Whiskey Cove PMIC
4 *
5 * Copyright (C) 2015-2017, 2022 Intel Corporation. All rights reserved.
6 */
7
8 #include <linux/acpi.h>
9 #include <linux/bits.h>
10 #include <linux/delay.h>
11 #include <linux/err.h>
12 #include <linux/interrupt.h>
13 #include <linux/kernel.h>
14 #include <linux/mfd/core.h>
15 #include <linux/mfd/intel_soc_pmic.h>
16 #include <linux/mfd/intel_soc_pmic_bxtwc.h>
17 #include <linux/module.h>
18 #include <linux/platform_data/x86/intel_scu_ipc.h>
19
20 /* PMIC device registers */
21 #define REG_ADDR_MASK GENMASK(15, 8)
22 #define REG_ADDR_SHIFT 8
23 #define REG_OFFSET_MASK GENMASK(7, 0)
24
25 /* Interrupt Status Registers */
26 #define BXTWC_IRQLVL1 0x4E02
27
28 #define BXTWC_PWRBTNIRQ 0x4E03
29 #define BXTWC_THRM0IRQ 0x4E04
30 #define BXTWC_THRM1IRQ 0x4E05
31 #define BXTWC_THRM2IRQ 0x4E06
32 #define BXTWC_BCUIRQ 0x4E07
33 #define BXTWC_ADCIRQ 0x4E08
34 #define BXTWC_CHGR0IRQ 0x4E09
35 #define BXTWC_CHGR1IRQ 0x4E0A
36 #define BXTWC_GPIOIRQ0 0x4E0B
37 #define BXTWC_GPIOIRQ1 0x4E0C
38 #define BXTWC_CRITIRQ 0x4E0D
39 #define BXTWC_TMUIRQ 0x4FB6
40
41 /* Interrupt MASK Registers */
42 #define BXTWC_MIRQLVL1 0x4E0E
43 #define BXTWC_MIRQLVL1_MCHGR BIT(5)
44
45 #define BXTWC_MPWRBTNIRQ 0x4E0F
46 #define BXTWC_MTHRM0IRQ 0x4E12
47 #define BXTWC_MTHRM1IRQ 0x4E13
48 #define BXTWC_MTHRM2IRQ 0x4E14
49 #define BXTWC_MBCUIRQ 0x4E15
50 #define BXTWC_MADCIRQ 0x4E16
51 #define BXTWC_MCHGR0IRQ 0x4E17
52 #define BXTWC_MCHGR1IRQ 0x4E18
53 #define BXTWC_MGPIO0IRQ 0x4E19
54 #define BXTWC_MGPIO1IRQ 0x4E1A
55 #define BXTWC_MCRITIRQ 0x4E1B
56 #define BXTWC_MTMUIRQ 0x4FB7
57
58 /* Whiskey Cove PMIC share same ACPI ID between different platforms */
59 #define BROXTON_PMIC_WC_HRV 4
60
61 #define PMC_PMIC_ACCESS 0xFF
62 #define PMC_PMIC_READ 0x0
63 #define PMC_PMIC_WRITE 0x1
64
65 enum bxtwc_irqs {
66 BXTWC_PWRBTN_LVL1_IRQ = 0,
67 BXTWC_TMU_LVL1_IRQ,
68 BXTWC_THRM_LVL1_IRQ,
69 BXTWC_BCU_LVL1_IRQ,
70 BXTWC_ADC_LVL1_IRQ,
71 BXTWC_CHGR_LVL1_IRQ,
72 BXTWC_GPIO_LVL1_IRQ,
73 BXTWC_CRIT_LVL1_IRQ,
74 };
75
76 enum bxtwc_irqs_pwrbtn {
77 BXTWC_PWRBTN_IRQ = 0,
78 BXTWC_UIBTN_IRQ,
79 };
80
81 enum bxtwc_irqs_bcu {
82 BXTWC_BCU_IRQ = 0,
83 };
84
85 enum bxtwc_irqs_adc {
86 BXTWC_ADC_IRQ = 0,
87 };
88
89 enum bxtwc_irqs_chgr {
90 BXTWC_USBC_IRQ = 0,
91 BXTWC_CHGR0_IRQ,
92 BXTWC_CHGR1_IRQ,
93 };
94
95 enum bxtwc_irqs_tmu {
96 BXTWC_TMU_IRQ = 0,
97 };
98
99 enum bxtwc_irqs_crit {
100 BXTWC_CRIT_IRQ = 0,
101 };
102
103 static const struct regmap_irq bxtwc_regmap_irqs[] = {
104 REGMAP_IRQ_REG(BXTWC_PWRBTN_LVL1_IRQ, 0, BIT(0)),
105 REGMAP_IRQ_REG(BXTWC_TMU_LVL1_IRQ, 0, BIT(1)),
106 REGMAP_IRQ_REG(BXTWC_THRM_LVL1_IRQ, 0, BIT(2)),
107 REGMAP_IRQ_REG(BXTWC_BCU_LVL1_IRQ, 0, BIT(3)),
108 REGMAP_IRQ_REG(BXTWC_ADC_LVL1_IRQ, 0, BIT(4)),
109 REGMAP_IRQ_REG(BXTWC_CHGR_LVL1_IRQ, 0, BIT(5)),
110 REGMAP_IRQ_REG(BXTWC_GPIO_LVL1_IRQ, 0, BIT(6)),
111 REGMAP_IRQ_REG(BXTWC_CRIT_LVL1_IRQ, 0, BIT(7)),
112 };
113
114 static const struct regmap_irq bxtwc_regmap_irqs_pwrbtn[] = {
115 REGMAP_IRQ_REG(BXTWC_PWRBTN_IRQ, 0, BIT(0)),
116 };
117
118 static const struct regmap_irq bxtwc_regmap_irqs_bcu[] = {
119 REGMAP_IRQ_REG(BXTWC_BCU_IRQ, 0, GENMASK(4, 0)),
120 };
121
122 static const struct regmap_irq bxtwc_regmap_irqs_adc[] = {
123 REGMAP_IRQ_REG(BXTWC_ADC_IRQ, 0, GENMASK(7, 0)),
124 };
125
126 static const struct regmap_irq bxtwc_regmap_irqs_chgr[] = {
127 REGMAP_IRQ_REG(BXTWC_USBC_IRQ, 0, BIT(5)),
128 REGMAP_IRQ_REG(BXTWC_CHGR0_IRQ, 0, GENMASK(4, 0)),
129 REGMAP_IRQ_REG(BXTWC_CHGR1_IRQ, 1, GENMASK(4, 0)),
130 };
131
132 static const struct regmap_irq bxtwc_regmap_irqs_tmu[] = {
133 REGMAP_IRQ_REG(BXTWC_TMU_IRQ, 0, GENMASK(2, 1)),
134 };
135
136 static const struct regmap_irq bxtwc_regmap_irqs_crit[] = {
137 REGMAP_IRQ_REG(BXTWC_CRIT_IRQ, 0, GENMASK(1, 0)),
138 };
139
140 static const struct regmap_irq_chip bxtwc_regmap_irq_chip = {
141 .name = "bxtwc_irq_chip",
142 .status_base = BXTWC_IRQLVL1,
143 .mask_base = BXTWC_MIRQLVL1,
144 .irqs = bxtwc_regmap_irqs,
145 .num_irqs = ARRAY_SIZE(bxtwc_regmap_irqs),
146 .num_regs = 1,
147 };
148
149 static const struct regmap_irq_chip bxtwc_regmap_irq_chip_pwrbtn = {
150 .name = "bxtwc_irq_chip_pwrbtn",
151 .domain_suffix = "PWRBTN",
152 .status_base = BXTWC_PWRBTNIRQ,
153 .mask_base = BXTWC_MPWRBTNIRQ,
154 .irqs = bxtwc_regmap_irqs_pwrbtn,
155 .num_irqs = ARRAY_SIZE(bxtwc_regmap_irqs_pwrbtn),
156 .num_regs = 1,
157 };
158
159 static const struct regmap_irq_chip bxtwc_regmap_irq_chip_tmu = {
160 .name = "bxtwc_irq_chip_tmu",
161 .domain_suffix = "TMU",
162 .status_base = BXTWC_TMUIRQ,
163 .mask_base = BXTWC_MTMUIRQ,
164 .irqs = bxtwc_regmap_irqs_tmu,
165 .num_irqs = ARRAY_SIZE(bxtwc_regmap_irqs_tmu),
166 .num_regs = 1,
167 };
168
169 static const struct regmap_irq_chip bxtwc_regmap_irq_chip_bcu = {
170 .name = "bxtwc_irq_chip_bcu",
171 .domain_suffix = "BCU",
172 .status_base = BXTWC_BCUIRQ,
173 .mask_base = BXTWC_MBCUIRQ,
174 .irqs = bxtwc_regmap_irqs_bcu,
175 .num_irqs = ARRAY_SIZE(bxtwc_regmap_irqs_bcu),
176 .num_regs = 1,
177 };
178
179 static const struct regmap_irq_chip bxtwc_regmap_irq_chip_adc = {
180 .name = "bxtwc_irq_chip_adc",
181 .domain_suffix = "ADC",
182 .status_base = BXTWC_ADCIRQ,
183 .mask_base = BXTWC_MADCIRQ,
184 .irqs = bxtwc_regmap_irqs_adc,
185 .num_irqs = ARRAY_SIZE(bxtwc_regmap_irqs_adc),
186 .num_regs = 1,
187 };
188
189 static const struct regmap_irq_chip bxtwc_regmap_irq_chip_chgr = {
190 .name = "bxtwc_irq_chip_chgr",
191 .domain_suffix = "CHGR",
192 .status_base = BXTWC_CHGR0IRQ,
193 .mask_base = BXTWC_MCHGR0IRQ,
194 .irqs = bxtwc_regmap_irqs_chgr,
195 .num_irqs = ARRAY_SIZE(bxtwc_regmap_irqs_chgr),
196 .num_regs = 2,
197 };
198
199 static const struct regmap_irq_chip bxtwc_regmap_irq_chip_crit = {
200 .name = "bxtwc_irq_chip_crit",
201 .domain_suffix = "CRIT",
202 .status_base = BXTWC_CRITIRQ,
203 .mask_base = BXTWC_MCRITIRQ,
204 .irqs = bxtwc_regmap_irqs_crit,
205 .num_irqs = ARRAY_SIZE(bxtwc_regmap_irqs_crit),
206 .num_regs = 1,
207 };
208
209 static const struct resource gpio_resources[] = {
210 DEFINE_RES_IRQ_NAMED(BXTWC_GPIO_LVL1_IRQ, "GPIO"),
211 };
212
213 static const struct resource adc_resources[] = {
214 DEFINE_RES_IRQ_NAMED(BXTWC_ADC_IRQ, "ADC"),
215 };
216
217 static const struct resource usbc_resources[] = {
218 DEFINE_RES_IRQ(BXTWC_USBC_IRQ),
219 };
220
221 static const struct resource charger_resources[] = {
222 DEFINE_RES_IRQ_NAMED(BXTWC_CHGR0_IRQ, "CHARGER"),
223 DEFINE_RES_IRQ_NAMED(BXTWC_CHGR1_IRQ, "CHARGER1"),
224 };
225
226 static const struct resource thermal_resources[] = {
227 DEFINE_RES_IRQ(BXTWC_THRM_LVL1_IRQ),
228 };
229
230 static const struct resource bcu_resources[] = {
231 DEFINE_RES_IRQ_NAMED(BXTWC_BCU_IRQ, "BCU"),
232 };
233
234 static const struct resource tmu_resources[] = {
235 DEFINE_RES_IRQ_NAMED(BXTWC_TMU_IRQ, "TMU"),
236 };
237
238 static struct mfd_cell bxt_wc_dev[] = {
239 {
240 .name = "bxt_wcove_thermal",
241 .num_resources = ARRAY_SIZE(thermal_resources),
242 .resources = thermal_resources,
243 },
244 {
245 .name = "bxt_wcove_gpio",
246 .num_resources = ARRAY_SIZE(gpio_resources),
247 .resources = gpio_resources,
248 },
249 {
250 .name = "bxt_wcove_region",
251 },
252 };
253
254 static const struct mfd_cell bxt_wc_tmu_dev[] = {
255 {
256 .name = "bxt_wcove_tmu",
257 .num_resources = ARRAY_SIZE(tmu_resources),
258 .resources = tmu_resources,
259 },
260 };
261
262 static const struct mfd_cell bxt_wc_bcu_dev[] = {
263 {
264 .name = "bxt_wcove_bcu",
265 .num_resources = ARRAY_SIZE(bcu_resources),
266 .resources = bcu_resources,
267 },
268 };
269
270 static const struct mfd_cell bxt_wc_adc_dev[] = {
271 {
272 .name = "bxt_wcove_gpadc",
273 .num_resources = ARRAY_SIZE(adc_resources),
274 .resources = adc_resources,
275 },
276 };
277
278 static struct mfd_cell bxt_wc_chgr_dev[] = {
279 {
280 .name = "bxt_wcove_usbc",
281 .num_resources = ARRAY_SIZE(usbc_resources),
282 .resources = usbc_resources,
283 },
284 {
285 .name = "bxt_wcove_ext_charger",
286 .num_resources = ARRAY_SIZE(charger_resources),
287 .resources = charger_resources,
288 },
289 };
290
regmap_ipc_byte_reg_read(void * context,unsigned int reg,unsigned int * val)291 static int regmap_ipc_byte_reg_read(void *context, unsigned int reg,
292 unsigned int *val)
293 {
294 int ret;
295 int i2c_addr;
296 u8 ipc_in[2];
297 u8 ipc_out[4];
298 struct intel_soc_pmic *pmic = context;
299
300 if (!pmic)
301 return -EINVAL;
302
303 if (reg & REG_ADDR_MASK)
304 i2c_addr = (reg & REG_ADDR_MASK) >> REG_ADDR_SHIFT;
305 else
306 i2c_addr = BXTWC_DEVICE1_ADDR;
307
308 reg &= REG_OFFSET_MASK;
309
310 ipc_in[0] = reg;
311 ipc_in[1] = i2c_addr;
312 ret = intel_scu_ipc_dev_command(pmic->scu, PMC_PMIC_ACCESS,
313 PMC_PMIC_READ, ipc_in, sizeof(ipc_in),
314 ipc_out, sizeof(ipc_out));
315 if (ret)
316 return ret;
317
318 *val = ipc_out[0];
319
320 return 0;
321 }
322
regmap_ipc_byte_reg_write(void * context,unsigned int reg,unsigned int val)323 static int regmap_ipc_byte_reg_write(void *context, unsigned int reg,
324 unsigned int val)
325 {
326 int i2c_addr;
327 u8 ipc_in[3];
328 struct intel_soc_pmic *pmic = context;
329
330 if (!pmic)
331 return -EINVAL;
332
333 if (reg & REG_ADDR_MASK)
334 i2c_addr = (reg & REG_ADDR_MASK) >> REG_ADDR_SHIFT;
335 else
336 i2c_addr = BXTWC_DEVICE1_ADDR;
337
338 reg &= REG_OFFSET_MASK;
339
340 ipc_in[0] = reg;
341 ipc_in[1] = i2c_addr;
342 ipc_in[2] = val;
343 return intel_scu_ipc_dev_command(pmic->scu, PMC_PMIC_ACCESS,
344 PMC_PMIC_WRITE, ipc_in, sizeof(ipc_in),
345 NULL, 0);
346 }
347
348 /* sysfs interfaces to r/w PMIC registers, required by initial script */
349 static unsigned long bxtwc_reg_addr;
addr_show(struct device * dev,struct device_attribute * attr,char * buf)350 static ssize_t addr_show(struct device *dev,
351 struct device_attribute *attr, char *buf)
352 {
353 return sysfs_emit(buf, "0x%lx\n", bxtwc_reg_addr);
354 }
355
addr_store(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)356 static ssize_t addr_store(struct device *dev,
357 struct device_attribute *attr, const char *buf, size_t count)
358 {
359 int ret;
360
361 ret = kstrtoul(buf, 0, &bxtwc_reg_addr);
362 if (ret)
363 return ret;
364
365 return count;
366 }
367
val_show(struct device * dev,struct device_attribute * attr,char * buf)368 static ssize_t val_show(struct device *dev,
369 struct device_attribute *attr, char *buf)
370 {
371 int ret;
372 unsigned int val;
373 struct intel_soc_pmic *pmic = dev_get_drvdata(dev);
374
375 ret = regmap_read(pmic->regmap, bxtwc_reg_addr, &val);
376 if (ret) {
377 dev_err(dev, "Failed to read 0x%lx\n", bxtwc_reg_addr);
378 return ret;
379 }
380
381 return sysfs_emit(buf, "0x%02x\n", val);
382 }
383
val_store(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)384 static ssize_t val_store(struct device *dev,
385 struct device_attribute *attr, const char *buf, size_t count)
386 {
387 int ret;
388 unsigned int val;
389 struct intel_soc_pmic *pmic = dev_get_drvdata(dev);
390
391 ret = kstrtouint(buf, 0, &val);
392 if (ret)
393 return ret;
394
395 ret = regmap_write(pmic->regmap, bxtwc_reg_addr, val);
396 if (ret) {
397 dev_err(dev, "Failed to write value 0x%02x to address 0x%lx",
398 val, bxtwc_reg_addr);
399 return ret;
400 }
401 return count;
402 }
403
404 static DEVICE_ATTR_ADMIN_RW(addr);
405 static DEVICE_ATTR_ADMIN_RW(val);
406 static struct attribute *bxtwc_attrs[] = {
407 &dev_attr_addr.attr,
408 &dev_attr_val.attr,
409 NULL
410 };
411
412 static const struct attribute_group bxtwc_group = {
413 .attrs = bxtwc_attrs,
414 };
415
416 static const struct attribute_group *bxtwc_groups[] = {
417 &bxtwc_group,
418 NULL
419 };
420
421 static const struct regmap_config bxtwc_regmap_config = {
422 .reg_bits = 16,
423 .val_bits = 8,
424 .reg_write = regmap_ipc_byte_reg_write,
425 .reg_read = regmap_ipc_byte_reg_read,
426 };
427
bxtwc_add_chained_irq_chip(struct intel_soc_pmic * pmic,struct regmap_irq_chip_data * pdata,int pirq,int irq_flags,const struct regmap_irq_chip * chip,struct regmap_irq_chip_data ** data)428 static int bxtwc_add_chained_irq_chip(struct intel_soc_pmic *pmic,
429 struct regmap_irq_chip_data *pdata,
430 int pirq, int irq_flags,
431 const struct regmap_irq_chip *chip,
432 struct regmap_irq_chip_data **data)
433 {
434 int irq;
435
436 irq = regmap_irq_get_virq(pdata, pirq);
437 if (irq < 0)
438 return dev_err_probe(pmic->dev, irq, "Failed to get parent vIRQ(%d) for chip %s\n",
439 pirq, chip->name);
440
441 return devm_regmap_add_irq_chip(pmic->dev, pmic->regmap, irq, irq_flags,
442 0, chip, data);
443 }
444
bxtwc_add_chained_devices(struct intel_soc_pmic * pmic,const struct mfd_cell * cells,int n_devs,struct regmap_irq_chip_data * pdata,int pirq,int irq_flags,const struct regmap_irq_chip * chip,struct regmap_irq_chip_data ** data)445 static int bxtwc_add_chained_devices(struct intel_soc_pmic *pmic,
446 const struct mfd_cell *cells, int n_devs,
447 struct regmap_irq_chip_data *pdata,
448 int pirq, int irq_flags,
449 const struct regmap_irq_chip *chip,
450 struct regmap_irq_chip_data **data)
451 {
452 struct device *dev = pmic->dev;
453 struct irq_domain *domain;
454 int ret;
455
456 ret = bxtwc_add_chained_irq_chip(pmic, pdata, pirq, irq_flags, chip, data);
457 if (ret)
458 return dev_err_probe(dev, ret, "Failed to add %s IRQ chip\n", chip->name);
459
460 domain = regmap_irq_get_domain(*data);
461
462 return devm_mfd_add_devices(dev, PLATFORM_DEVID_NONE, cells, n_devs, NULL, 0, domain);
463 }
464
bxtwc_probe(struct platform_device * pdev)465 static int bxtwc_probe(struct platform_device *pdev)
466 {
467 struct device *dev = &pdev->dev;
468 int ret;
469 acpi_status status;
470 unsigned long long hrv;
471 struct intel_soc_pmic *pmic;
472
473 status = acpi_evaluate_integer(ACPI_HANDLE(dev), "_HRV", NULL, &hrv);
474 if (ACPI_FAILURE(status))
475 return dev_err_probe(dev, -ENODEV, "Failed to get PMIC hardware revision\n");
476 if (hrv != BROXTON_PMIC_WC_HRV)
477 return dev_err_probe(dev, -ENODEV, "Invalid PMIC hardware revision: %llu\n", hrv);
478
479 pmic = devm_kzalloc(dev, sizeof(*pmic), GFP_KERNEL);
480 if (!pmic)
481 return -ENOMEM;
482
483 ret = platform_get_irq(pdev, 0);
484 if (ret < 0)
485 return ret;
486 pmic->irq = ret;
487
488 platform_set_drvdata(pdev, pmic);
489 pmic->dev = dev;
490
491 pmic->scu = devm_intel_scu_ipc_dev_get(dev);
492 if (!pmic->scu)
493 return -EPROBE_DEFER;
494
495 pmic->regmap = devm_regmap_init(dev, NULL, pmic, &bxtwc_regmap_config);
496 if (IS_ERR(pmic->regmap))
497 return dev_err_probe(dev, PTR_ERR(pmic->regmap), "Failed to initialise regmap\n");
498
499 ret = devm_regmap_add_irq_chip(dev, pmic->regmap, pmic->irq,
500 IRQF_ONESHOT | IRQF_SHARED,
501 0, &bxtwc_regmap_irq_chip,
502 &pmic->irq_chip_data);
503 if (ret)
504 return dev_err_probe(dev, ret, "Failed to add IRQ chip\n");
505
506 ret = bxtwc_add_chained_devices(pmic, bxt_wc_tmu_dev, ARRAY_SIZE(bxt_wc_tmu_dev),
507 pmic->irq_chip_data,
508 BXTWC_TMU_LVL1_IRQ,
509 IRQF_ONESHOT,
510 &bxtwc_regmap_irq_chip_tmu,
511 &pmic->irq_chip_data_tmu);
512 if (ret)
513 return ret;
514
515 ret = bxtwc_add_chained_irq_chip(pmic, pmic->irq_chip_data,
516 BXTWC_PWRBTN_LVL1_IRQ,
517 IRQF_ONESHOT,
518 &bxtwc_regmap_irq_chip_pwrbtn,
519 &pmic->irq_chip_data_pwrbtn);
520 if (ret)
521 return dev_err_probe(dev, ret, "Failed to add PWRBTN IRQ chip\n");
522
523 ret = bxtwc_add_chained_devices(pmic, bxt_wc_bcu_dev, ARRAY_SIZE(bxt_wc_bcu_dev),
524 pmic->irq_chip_data,
525 BXTWC_BCU_LVL1_IRQ,
526 IRQF_ONESHOT,
527 &bxtwc_regmap_irq_chip_bcu,
528 &pmic->irq_chip_data_bcu);
529 if (ret)
530 return ret;
531
532 ret = bxtwc_add_chained_devices(pmic, bxt_wc_adc_dev, ARRAY_SIZE(bxt_wc_adc_dev),
533 pmic->irq_chip_data,
534 BXTWC_ADC_LVL1_IRQ,
535 IRQF_ONESHOT,
536 &bxtwc_regmap_irq_chip_adc,
537 &pmic->irq_chip_data_adc);
538 if (ret)
539 return ret;
540
541 ret = bxtwc_add_chained_devices(pmic, bxt_wc_chgr_dev, ARRAY_SIZE(bxt_wc_chgr_dev),
542 pmic->irq_chip_data,
543 BXTWC_CHGR_LVL1_IRQ,
544 IRQF_ONESHOT,
545 &bxtwc_regmap_irq_chip_chgr,
546 &pmic->irq_chip_data_chgr);
547 if (ret)
548 return ret;
549
550 /* Add chained IRQ handler for CRIT IRQs */
551 ret = bxtwc_add_chained_irq_chip(pmic, pmic->irq_chip_data,
552 BXTWC_CRIT_LVL1_IRQ,
553 IRQF_ONESHOT,
554 &bxtwc_regmap_irq_chip_crit,
555 &pmic->irq_chip_data_crit);
556 if (ret)
557 return dev_err_probe(dev, ret, "Failed to add CRIT IRQ chip\n");
558
559 ret = devm_mfd_add_devices(dev, PLATFORM_DEVID_NONE, bxt_wc_dev, ARRAY_SIZE(bxt_wc_dev),
560 NULL, 0, NULL);
561 if (ret)
562 return dev_err_probe(dev, ret, "Failed to add devices\n");
563
564 /*
565 * There is a known H/W bug. Upon reset, BIT 5 of register
566 * BXTWC_CHGR_LVL1_IRQ is 0 which is the expected value. However,
567 * later it's set to 1(masked) automatically by hardware. So we
568 * place the software workaround here to unmask it again in order
569 * to re-enable the charger interrupt.
570 */
571 regmap_update_bits(pmic->regmap, BXTWC_MIRQLVL1, BXTWC_MIRQLVL1_MCHGR, 0);
572
573 return 0;
574 }
575
bxtwc_shutdown(struct platform_device * pdev)576 static void bxtwc_shutdown(struct platform_device *pdev)
577 {
578 struct intel_soc_pmic *pmic = platform_get_drvdata(pdev);
579
580 disable_irq(pmic->irq);
581 }
582
bxtwc_suspend(struct device * dev)583 static int bxtwc_suspend(struct device *dev)
584 {
585 struct intel_soc_pmic *pmic = dev_get_drvdata(dev);
586
587 disable_irq(pmic->irq);
588
589 return 0;
590 }
591
bxtwc_resume(struct device * dev)592 static int bxtwc_resume(struct device *dev)
593 {
594 struct intel_soc_pmic *pmic = dev_get_drvdata(dev);
595
596 enable_irq(pmic->irq);
597 return 0;
598 }
599
600 static DEFINE_SIMPLE_DEV_PM_OPS(bxtwc_pm_ops, bxtwc_suspend, bxtwc_resume);
601
602 static const struct acpi_device_id bxtwc_acpi_ids[] = {
603 { "INT34D3", },
604 { }
605 };
606 MODULE_DEVICE_TABLE(acpi, bxtwc_acpi_ids);
607
608 static struct platform_driver bxtwc_driver = {
609 .probe = bxtwc_probe,
610 .shutdown = bxtwc_shutdown,
611 .driver = {
612 .name = "BXTWC PMIC",
613 .pm = pm_sleep_ptr(&bxtwc_pm_ops),
614 .acpi_match_table = bxtwc_acpi_ids,
615 .dev_groups = bxtwc_groups,
616 },
617 };
618
619 module_platform_driver(bxtwc_driver);
620
621 MODULE_DESCRIPTION("Intel Broxton Whiskey Cove PMIC MFD core driver");
622 MODULE_LICENSE("GPL v2");
623 MODULE_AUTHOR("Qipeng Zha <qipeng.zha@intel.com>");
624