1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (c) 2014-2015, 2022 MediaTek Inc.
4 * Author: Chaotian.Jing <chaotian.jing@mediatek.com>
5 */
6
7 #include <linux/module.h>
8 #include <linux/bitops.h>
9 #include <linux/clk.h>
10 #include <linux/delay.h>
11 #include <linux/dma-mapping.h>
12 #include <linux/iopoll.h>
13 #include <linux/ioport.h>
14 #include <linux/irq.h>
15 #include <linux/of.h>
16 #include <linux/pinctrl/consumer.h>
17 #include <linux/platform_device.h>
18 #include <linux/pm.h>
19 #include <linux/pm_runtime.h>
20 #include <linux/pm_wakeirq.h>
21 #include <linux/regulator/consumer.h>
22 #include <linux/slab.h>
23 #include <linux/spinlock.h>
24 #include <linux/interrupt.h>
25 #include <linux/reset.h>
26
27 #include <linux/mmc/card.h>
28 #include <linux/mmc/core.h>
29 #include <linux/mmc/host.h>
30 #include <linux/mmc/mmc.h>
31 #include <linux/mmc/sd.h>
32 #include <linux/mmc/sdio.h>
33 #include <linux/mmc/slot-gpio.h>
34
35 #include "cqhci.h"
36
37 #define MAX_BD_NUM 1024
38 #define MSDC_NR_CLOCKS 3
39
40 /*--------------------------------------------------------------------------*/
41 /* Common Definition */
42 /*--------------------------------------------------------------------------*/
43 #define MSDC_BUS_1BITS 0x0
44 #define MSDC_BUS_4BITS 0x1
45 #define MSDC_BUS_8BITS 0x2
46
47 #define MSDC_BURST_64B 0x6
48
49 /*--------------------------------------------------------------------------*/
50 /* Register Offset */
51 /*--------------------------------------------------------------------------*/
52 #define MSDC_CFG 0x0
53 #define MSDC_IOCON 0x04
54 #define MSDC_PS 0x08
55 #define MSDC_INT 0x0c
56 #define MSDC_INTEN 0x10
57 #define MSDC_FIFOCS 0x14
58 #define SDC_CFG 0x30
59 #define SDC_CMD 0x34
60 #define SDC_ARG 0x38
61 #define SDC_STS 0x3c
62 #define SDC_RESP0 0x40
63 #define SDC_RESP1 0x44
64 #define SDC_RESP2 0x48
65 #define SDC_RESP3 0x4c
66 #define SDC_BLK_NUM 0x50
67 #define SDC_ADV_CFG0 0x64
68 #define EMMC_IOCON 0x7c
69 #define SDC_ACMD_RESP 0x80
70 #define DMA_SA_H4BIT 0x8c
71 #define MSDC_DMA_SA 0x90
72 #define MSDC_DMA_CTRL 0x98
73 #define MSDC_DMA_CFG 0x9c
74 #define MSDC_PATCH_BIT 0xb0
75 #define MSDC_PATCH_BIT1 0xb4
76 #define MSDC_PATCH_BIT2 0xb8
77 #define MSDC_PAD_TUNE 0xec
78 #define MSDC_PAD_TUNE0 0xf0
79 #define PAD_DS_TUNE 0x188
80 #define PAD_CMD_TUNE 0x18c
81 #define EMMC51_CFG0 0x204
82 #define EMMC50_CFG0 0x208
83 #define EMMC50_CFG1 0x20c
84 #define EMMC50_CFG3 0x220
85 #define SDC_FIFO_CFG 0x228
86 #define CQHCI_SETTING 0x7fc
87
88 /*--------------------------------------------------------------------------*/
89 /* Top Pad Register Offset */
90 /*--------------------------------------------------------------------------*/
91 #define EMMC_TOP_CONTROL 0x00
92 #define EMMC_TOP_CMD 0x04
93 #define EMMC50_PAD_DS_TUNE 0x0c
94
95 /*--------------------------------------------------------------------------*/
96 /* Register Mask */
97 /*--------------------------------------------------------------------------*/
98
99 /* MSDC_CFG mask */
100 #define MSDC_CFG_MODE BIT(0) /* RW */
101 #define MSDC_CFG_CKPDN BIT(1) /* RW */
102 #define MSDC_CFG_RST BIT(2) /* RW */
103 #define MSDC_CFG_PIO BIT(3) /* RW */
104 #define MSDC_CFG_CKDRVEN BIT(4) /* RW */
105 #define MSDC_CFG_BV18SDT BIT(5) /* RW */
106 #define MSDC_CFG_BV18PSS BIT(6) /* R */
107 #define MSDC_CFG_CKSTB BIT(7) /* R */
108 #define MSDC_CFG_CKDIV GENMASK(15, 8) /* RW */
109 #define MSDC_CFG_CKMOD GENMASK(17, 16) /* RW */
110 #define MSDC_CFG_HS400_CK_MODE BIT(18) /* RW */
111 #define MSDC_CFG_HS400_CK_MODE_EXTRA BIT(22) /* RW */
112 #define MSDC_CFG_CKDIV_EXTRA GENMASK(19, 8) /* RW */
113 #define MSDC_CFG_CKMOD_EXTRA GENMASK(21, 20) /* RW */
114
115 /* MSDC_IOCON mask */
116 #define MSDC_IOCON_SDR104CKS BIT(0) /* RW */
117 #define MSDC_IOCON_RSPL BIT(1) /* RW */
118 #define MSDC_IOCON_DSPL BIT(2) /* RW */
119 #define MSDC_IOCON_DDLSEL BIT(3) /* RW */
120 #define MSDC_IOCON_DDR50CKD BIT(4) /* RW */
121 #define MSDC_IOCON_DSPLSEL BIT(5) /* RW */
122 #define MSDC_IOCON_W_DSPL BIT(8) /* RW */
123 #define MSDC_IOCON_D0SPL BIT(16) /* RW */
124 #define MSDC_IOCON_D1SPL BIT(17) /* RW */
125 #define MSDC_IOCON_D2SPL BIT(18) /* RW */
126 #define MSDC_IOCON_D3SPL BIT(19) /* RW */
127 #define MSDC_IOCON_D4SPL BIT(20) /* RW */
128 #define MSDC_IOCON_D5SPL BIT(21) /* RW */
129 #define MSDC_IOCON_D6SPL BIT(22) /* RW */
130 #define MSDC_IOCON_D7SPL BIT(23) /* RW */
131 #define MSDC_IOCON_RISCSZ GENMASK(25, 24) /* RW */
132
133 /* MSDC_PS mask */
134 #define MSDC_PS_CDEN BIT(0) /* RW */
135 #define MSDC_PS_CDSTS BIT(1) /* R */
136 #define MSDC_PS_CDDEBOUNCE GENMASK(15, 12) /* RW */
137 #define MSDC_PS_DAT GENMASK(23, 16) /* R */
138 #define MSDC_PS_DATA1 BIT(17) /* R */
139 #define MSDC_PS_CMD BIT(24) /* R */
140 #define MSDC_PS_WP BIT(31) /* R */
141
142 /* MSDC_INT mask */
143 #define MSDC_INT_MMCIRQ BIT(0) /* W1C */
144 #define MSDC_INT_CDSC BIT(1) /* W1C */
145 #define MSDC_INT_ACMDRDY BIT(3) /* W1C */
146 #define MSDC_INT_ACMDTMO BIT(4) /* W1C */
147 #define MSDC_INT_ACMDCRCERR BIT(5) /* W1C */
148 #define MSDC_INT_DMAQ_EMPTY BIT(6) /* W1C */
149 #define MSDC_INT_SDIOIRQ BIT(7) /* W1C */
150 #define MSDC_INT_CMDRDY BIT(8) /* W1C */
151 #define MSDC_INT_CMDTMO BIT(9) /* W1C */
152 #define MSDC_INT_RSPCRCERR BIT(10) /* W1C */
153 #define MSDC_INT_CSTA BIT(11) /* R */
154 #define MSDC_INT_XFER_COMPL BIT(12) /* W1C */
155 #define MSDC_INT_DXFER_DONE BIT(13) /* W1C */
156 #define MSDC_INT_DATTMO BIT(14) /* W1C */
157 #define MSDC_INT_DATCRCERR BIT(15) /* W1C */
158 #define MSDC_INT_ACMD19_DONE BIT(16) /* W1C */
159 #define MSDC_INT_DMA_BDCSERR BIT(17) /* W1C */
160 #define MSDC_INT_DMA_GPDCSERR BIT(18) /* W1C */
161 #define MSDC_INT_DMA_PROTECT BIT(19) /* W1C */
162 #define MSDC_INT_CMDQ BIT(28) /* W1C */
163
164 /* MSDC_INTEN mask */
165 #define MSDC_INTEN_MMCIRQ BIT(0) /* RW */
166 #define MSDC_INTEN_CDSC BIT(1) /* RW */
167 #define MSDC_INTEN_ACMDRDY BIT(3) /* RW */
168 #define MSDC_INTEN_ACMDTMO BIT(4) /* RW */
169 #define MSDC_INTEN_ACMDCRCERR BIT(5) /* RW */
170 #define MSDC_INTEN_DMAQ_EMPTY BIT(6) /* RW */
171 #define MSDC_INTEN_SDIOIRQ BIT(7) /* RW */
172 #define MSDC_INTEN_CMDRDY BIT(8) /* RW */
173 #define MSDC_INTEN_CMDTMO BIT(9) /* RW */
174 #define MSDC_INTEN_RSPCRCERR BIT(10) /* RW */
175 #define MSDC_INTEN_CSTA BIT(11) /* RW */
176 #define MSDC_INTEN_XFER_COMPL BIT(12) /* RW */
177 #define MSDC_INTEN_DXFER_DONE BIT(13) /* RW */
178 #define MSDC_INTEN_DATTMO BIT(14) /* RW */
179 #define MSDC_INTEN_DATCRCERR BIT(15) /* RW */
180 #define MSDC_INTEN_ACMD19_DONE BIT(16) /* RW */
181 #define MSDC_INTEN_DMA_BDCSERR BIT(17) /* RW */
182 #define MSDC_INTEN_DMA_GPDCSERR BIT(18) /* RW */
183 #define MSDC_INTEN_DMA_PROTECT BIT(19) /* RW */
184
185 /* MSDC_FIFOCS mask */
186 #define MSDC_FIFOCS_RXCNT GENMASK(7, 0) /* R */
187 #define MSDC_FIFOCS_TXCNT GENMASK(23, 16) /* R */
188 #define MSDC_FIFOCS_CLR BIT(31) /* RW */
189
190 /* SDC_CFG mask */
191 #define SDC_CFG_SDIOINTWKUP BIT(0) /* RW */
192 #define SDC_CFG_INSWKUP BIT(1) /* RW */
193 #define SDC_CFG_WRDTOC GENMASK(14, 2) /* RW */
194 #define SDC_CFG_BUSWIDTH GENMASK(17, 16) /* RW */
195 #define SDC_CFG_SDIO BIT(19) /* RW */
196 #define SDC_CFG_SDIOIDE BIT(20) /* RW */
197 #define SDC_CFG_INTATGAP BIT(21) /* RW */
198 #define SDC_CFG_DTOC GENMASK(31, 24) /* RW */
199
200 /* SDC_STS mask */
201 #define SDC_STS_SDCBUSY BIT(0) /* RW */
202 #define SDC_STS_CMDBUSY BIT(1) /* RW */
203 #define SDC_STS_SWR_COMPL BIT(31) /* RW */
204
205 #define SDC_DAT1_IRQ_TRIGGER BIT(19) /* RW */
206 /* SDC_ADV_CFG0 mask */
207 #define SDC_RX_ENHANCE_EN BIT(20) /* RW */
208
209 /* DMA_SA_H4BIT mask */
210 #define DMA_ADDR_HIGH_4BIT GENMASK(3, 0) /* RW */
211
212 /* MSDC_DMA_CTRL mask */
213 #define MSDC_DMA_CTRL_START BIT(0) /* W */
214 #define MSDC_DMA_CTRL_STOP BIT(1) /* W */
215 #define MSDC_DMA_CTRL_RESUME BIT(2) /* W */
216 #define MSDC_DMA_CTRL_MODE BIT(8) /* RW */
217 #define MSDC_DMA_CTRL_LASTBUF BIT(10) /* RW */
218 #define MSDC_DMA_CTRL_BRUSTSZ GENMASK(14, 12) /* RW */
219
220 /* MSDC_DMA_CFG mask */
221 #define MSDC_DMA_CFG_STS BIT(0) /* R */
222 #define MSDC_DMA_CFG_DECSEN BIT(1) /* RW */
223 #define MSDC_DMA_CFG_AHBHPROT2 BIT(9) /* RW */
224 #define MSDC_DMA_CFG_ACTIVEEN BIT(13) /* RW */
225 #define MSDC_DMA_CFG_CS12B16B BIT(16) /* RW */
226
227 /* MSDC_PATCH_BIT mask */
228 #define MSDC_PATCH_BIT_ODDSUPP BIT(1) /* RW */
229 #define MSDC_INT_DAT_LATCH_CK_SEL GENMASK(9, 7)
230 #define MSDC_CKGEN_MSDC_DLY_SEL GENMASK(14, 10)
231 #define MSDC_PATCH_BIT_IODSSEL BIT(16) /* RW */
232 #define MSDC_PATCH_BIT_IOINTSEL BIT(17) /* RW */
233 #define MSDC_PATCH_BIT_BUSYDLY GENMASK(21, 18) /* RW */
234 #define MSDC_PATCH_BIT_WDOD GENMASK(25, 22) /* RW */
235 #define MSDC_PATCH_BIT_IDRTSEL BIT(26) /* RW */
236 #define MSDC_PATCH_BIT_CMDFSEL BIT(27) /* RW */
237 #define MSDC_PATCH_BIT_INTDLSEL BIT(28) /* RW */
238 #define MSDC_PATCH_BIT_SPCPUSH BIT(29) /* RW */
239 #define MSDC_PATCH_BIT_DECRCTMO BIT(30) /* RW */
240
241 #define MSDC_PATCH_BIT1_CMDTA GENMASK(5, 3) /* RW */
242 #define MSDC_PB1_BUSY_CHECK_SEL BIT(7) /* RW */
243 #define MSDC_PATCH_BIT1_STOP_DLY GENMASK(11, 8) /* RW */
244
245 #define MSDC_PATCH_BIT2_CFGRESP BIT(15) /* RW */
246 #define MSDC_PATCH_BIT2_CFGCRCSTS BIT(28) /* RW */
247 #define MSDC_PB2_SUPPORT_64G BIT(1) /* RW */
248 #define MSDC_PB2_RESPWAIT GENMASK(3, 2) /* RW */
249 #define MSDC_PB2_RESPSTSENSEL GENMASK(18, 16) /* RW */
250 #define MSDC_PB2_CRCSTSENSEL GENMASK(31, 29) /* RW */
251
252 #define MSDC_PAD_TUNE_DATWRDLY GENMASK(4, 0) /* RW */
253 #define MSDC_PAD_TUNE_DATRRDLY GENMASK(12, 8) /* RW */
254 #define MSDC_PAD_TUNE_DATRRDLY2 GENMASK(12, 8) /* RW */
255 #define MSDC_PAD_TUNE_CMDRDLY GENMASK(20, 16) /* RW */
256 #define MSDC_PAD_TUNE_CMDRDLY2 GENMASK(20, 16) /* RW */
257 #define MSDC_PAD_TUNE_CMDRRDLY GENMASK(26, 22) /* RW */
258 #define MSDC_PAD_TUNE_CLKTDLY GENMASK(31, 27) /* RW */
259 #define MSDC_PAD_TUNE_RXDLYSEL BIT(15) /* RW */
260 #define MSDC_PAD_TUNE_RD_SEL BIT(13) /* RW */
261 #define MSDC_PAD_TUNE_CMD_SEL BIT(21) /* RW */
262 #define MSDC_PAD_TUNE_RD2_SEL BIT(13) /* RW */
263 #define MSDC_PAD_TUNE_CMD2_SEL BIT(21) /* RW */
264
265 #define PAD_DS_TUNE_DLY_SEL BIT(0) /* RW */
266 #define PAD_DS_TUNE_DLY2_SEL BIT(1) /* RW */
267 #define PAD_DS_TUNE_DLY1 GENMASK(6, 2) /* RW */
268 #define PAD_DS_TUNE_DLY2 GENMASK(11, 7) /* RW */
269 #define PAD_DS_TUNE_DLY3 GENMASK(16, 12) /* RW */
270
271 #define PAD_CMD_TUNE_RX_DLY3 GENMASK(5, 1) /* RW */
272
273 /* EMMC51_CFG0 mask */
274 #define CMDQ_RDAT_CNT GENMASK(21, 12) /* RW */
275
276 #define EMMC50_CFG_PADCMD_LATCHCK BIT(0) /* RW */
277 #define EMMC50_CFG_CRCSTS_EDGE BIT(3) /* RW */
278 #define EMMC50_CFG_CFCSTS_SEL BIT(4) /* RW */
279 #define EMMC50_CFG_CMD_RESP_SEL BIT(9) /* RW */
280
281 /* EMMC50_CFG1 mask */
282 #define EMMC50_CFG1_DS_CFG BIT(28) /* RW */
283
284 #define EMMC50_CFG3_OUTS_WR GENMASK(4, 0) /* RW */
285
286 #define SDC_FIFO_CFG_WRVALIDSEL BIT(24) /* RW */
287 #define SDC_FIFO_CFG_RDVALIDSEL BIT(25) /* RW */
288
289 /* CQHCI_SETTING */
290 #define CQHCI_RD_CMD_WND_SEL BIT(14) /* RW */
291 #define CQHCI_WR_CMD_WND_SEL BIT(15) /* RW */
292
293 /* EMMC_TOP_CONTROL mask */
294 #define PAD_RXDLY_SEL BIT(0) /* RW */
295 #define DELAY_EN BIT(1) /* RW */
296 #define PAD_DAT_RD_RXDLY2 GENMASK(6, 2) /* RW */
297 #define PAD_DAT_RD_RXDLY GENMASK(11, 7) /* RW */
298 #define PAD_DAT_RD_RXDLY2_SEL BIT(12) /* RW */
299 #define PAD_DAT_RD_RXDLY_SEL BIT(13) /* RW */
300 #define DATA_K_VALUE_SEL BIT(14) /* RW */
301 #define SDC_RX_ENH_EN BIT(15) /* TW */
302
303 /* EMMC_TOP_CMD mask */
304 #define PAD_CMD_RXDLY2 GENMASK(4, 0) /* RW */
305 #define PAD_CMD_RXDLY GENMASK(9, 5) /* RW */
306 #define PAD_CMD_RD_RXDLY2_SEL BIT(10) /* RW */
307 #define PAD_CMD_RD_RXDLY_SEL BIT(11) /* RW */
308 #define PAD_CMD_TX_DLY GENMASK(16, 12) /* RW */
309
310 /* EMMC50_PAD_DS_TUNE mask */
311 #define PAD_DS_DLY_SEL BIT(16) /* RW */
312 #define PAD_DS_DLY2_SEL BIT(15) /* RW */
313 #define PAD_DS_DLY1 GENMASK(14, 10) /* RW */
314 #define PAD_DS_DLY3 GENMASK(4, 0) /* RW */
315
316 #define REQ_CMD_EIO BIT(0)
317 #define REQ_CMD_TMO BIT(1)
318 #define REQ_DAT_ERR BIT(2)
319 #define REQ_STOP_EIO BIT(3)
320 #define REQ_STOP_TMO BIT(4)
321 #define REQ_CMD_BUSY BIT(5)
322
323 #define MSDC_PREPARE_FLAG BIT(0)
324 #define MSDC_ASYNC_FLAG BIT(1)
325 #define MSDC_MMAP_FLAG BIT(2)
326
327 #define MTK_MMC_AUTOSUSPEND_DELAY 50
328 #define CMD_TIMEOUT (HZ/10 * 5) /* 100ms x5 */
329 #define DAT_TIMEOUT (HZ * 5) /* 1000ms x5 */
330
331 #define DEFAULT_DEBOUNCE (8) /* 8 cycles CD debounce */
332
333 #define TUNING_REG2_FIXED_OFFEST 4
334 #define PAD_DELAY_HALF 32 /* PAD delay cells */
335 #define PAD_DELAY_FULL 64
336 /*--------------------------------------------------------------------------*/
337 /* Descriptor Structure */
338 /*--------------------------------------------------------------------------*/
339 struct mt_gpdma_desc {
340 u32 gpd_info;
341 #define GPDMA_DESC_HWO BIT(0)
342 #define GPDMA_DESC_BDP BIT(1)
343 #define GPDMA_DESC_CHECKSUM GENMASK(15, 8)
344 #define GPDMA_DESC_INT BIT(16)
345 #define GPDMA_DESC_NEXT_H4 GENMASK(27, 24)
346 #define GPDMA_DESC_PTR_H4 GENMASK(31, 28)
347 u32 next;
348 u32 ptr;
349 u32 gpd_data_len;
350 #define GPDMA_DESC_BUFLEN GENMASK(15, 0)
351 #define GPDMA_DESC_EXTLEN GENMASK(23, 16)
352 u32 arg;
353 u32 blknum;
354 u32 cmd;
355 };
356
357 struct mt_bdma_desc {
358 u32 bd_info;
359 #define BDMA_DESC_EOL BIT(0)
360 #define BDMA_DESC_CHECKSUM GENMASK(15, 8)
361 #define BDMA_DESC_BLKPAD BIT(17)
362 #define BDMA_DESC_DWPAD BIT(18)
363 #define BDMA_DESC_NEXT_H4 GENMASK(27, 24)
364 #define BDMA_DESC_PTR_H4 GENMASK(31, 28)
365 u32 next;
366 u32 ptr;
367 u32 bd_data_len;
368 #define BDMA_DESC_BUFLEN GENMASK(15, 0)
369 #define BDMA_DESC_BUFLEN_EXT GENMASK(23, 0)
370 };
371
372 struct msdc_dma {
373 struct scatterlist *sg; /* I/O scatter list */
374 struct mt_gpdma_desc *gpd; /* pointer to gpd array */
375 struct mt_bdma_desc *bd; /* pointer to bd array */
376 dma_addr_t gpd_addr; /* the physical address of gpd array */
377 dma_addr_t bd_addr; /* the physical address of bd array */
378 };
379
380 struct msdc_save_para {
381 u32 msdc_cfg;
382 u32 iocon;
383 u32 sdc_cfg;
384 u32 pad_tune;
385 u32 patch_bit0;
386 u32 patch_bit1;
387 u32 patch_bit2;
388 u32 pad_ds_tune;
389 u32 pad_cmd_tune;
390 u32 emmc50_cfg0;
391 u32 emmc50_cfg3;
392 u32 sdc_fifo_cfg;
393 u32 emmc_top_control;
394 u32 emmc_top_cmd;
395 u32 emmc50_pad_ds_tune;
396 };
397
398 struct mtk_mmc_compatible {
399 u8 clk_div_bits;
400 bool recheck_sdio_irq;
401 bool hs400_tune; /* only used for MT8173 */
402 u32 pad_tune_reg;
403 bool async_fifo;
404 bool data_tune;
405 bool busy_check;
406 bool stop_clk_fix;
407 bool enhance_rx;
408 bool support_64g;
409 bool use_internal_cd;
410 };
411
412 struct msdc_tune_para {
413 u32 iocon;
414 u32 pad_tune;
415 u32 pad_cmd_tune;
416 u32 emmc_top_control;
417 u32 emmc_top_cmd;
418 };
419
420 struct msdc_delay_phase {
421 u8 maxlen;
422 u8 start;
423 u8 final_phase;
424 };
425
426 struct msdc_host {
427 struct device *dev;
428 const struct mtk_mmc_compatible *dev_comp;
429 int cmd_rsp;
430
431 spinlock_t lock;
432 struct mmc_request *mrq;
433 struct mmc_command *cmd;
434 struct mmc_data *data;
435 int error;
436
437 void __iomem *base; /* host base address */
438 void __iomem *top_base; /* host top register base address */
439
440 struct msdc_dma dma; /* dma channel */
441 u64 dma_mask;
442
443 u32 timeout_ns; /* data timeout ns */
444 u32 timeout_clks; /* data timeout clks */
445
446 struct pinctrl *pinctrl;
447 struct pinctrl_state *pins_default;
448 struct pinctrl_state *pins_uhs;
449 struct pinctrl_state *pins_eint;
450 struct delayed_work req_timeout;
451 int irq; /* host interrupt */
452 int eint_irq; /* interrupt from sdio device for waking up system */
453 struct reset_control *reset;
454
455 struct clk *src_clk; /* msdc source clock */
456 struct clk *h_clk; /* msdc h_clk */
457 struct clk *bus_clk; /* bus clock which used to access register */
458 struct clk *src_clk_cg; /* msdc source clock control gate */
459 struct clk *sys_clk_cg; /* msdc subsys clock control gate */
460 struct clk *crypto_clk; /* msdc crypto clock control gate */
461 struct clk_bulk_data bulk_clks[MSDC_NR_CLOCKS];
462 u32 mclk; /* mmc subsystem clock frequency */
463 u32 src_clk_freq; /* source clock frequency */
464 unsigned char timing;
465 bool vqmmc_enabled;
466 u32 latch_ck;
467 u32 hs400_ds_delay;
468 u32 hs400_ds_dly3;
469 u32 hs200_cmd_int_delay; /* cmd internal delay for HS200/SDR104 */
470 u32 hs400_cmd_int_delay; /* cmd internal delay for HS400 */
471 u32 tuning_step;
472 bool hs400_cmd_resp_sel_rising;
473 /* cmd response sample selection for HS400 */
474 bool hs400_mode; /* current eMMC will run at hs400 mode */
475 bool hs400_tuning; /* hs400 mode online tuning */
476 bool internal_cd; /* Use internal card-detect logic */
477 bool cqhci; /* support eMMC hw cmdq */
478 struct msdc_save_para save_para; /* used when gate HCLK */
479 struct msdc_tune_para def_tune_para; /* default tune setting */
480 struct msdc_tune_para saved_tune_para; /* tune result of CMD21/CMD19 */
481 struct cqhci_host *cq_host;
482 u32 cq_ssc1_time;
483 };
484
485 static const struct mtk_mmc_compatible mt2701_compat = {
486 .clk_div_bits = 12,
487 .recheck_sdio_irq = true,
488 .hs400_tune = false,
489 .pad_tune_reg = MSDC_PAD_TUNE0,
490 .async_fifo = true,
491 .data_tune = true,
492 .busy_check = false,
493 .stop_clk_fix = false,
494 .enhance_rx = false,
495 .support_64g = false,
496 };
497
498 static const struct mtk_mmc_compatible mt2712_compat = {
499 .clk_div_bits = 12,
500 .recheck_sdio_irq = false,
501 .hs400_tune = false,
502 .pad_tune_reg = MSDC_PAD_TUNE0,
503 .async_fifo = true,
504 .data_tune = true,
505 .busy_check = true,
506 .stop_clk_fix = true,
507 .enhance_rx = true,
508 .support_64g = true,
509 };
510
511 static const struct mtk_mmc_compatible mt6779_compat = {
512 .clk_div_bits = 12,
513 .recheck_sdio_irq = false,
514 .hs400_tune = false,
515 .pad_tune_reg = MSDC_PAD_TUNE0,
516 .async_fifo = true,
517 .data_tune = true,
518 .busy_check = true,
519 .stop_clk_fix = true,
520 .enhance_rx = true,
521 .support_64g = true,
522 };
523
524 static const struct mtk_mmc_compatible mt6795_compat = {
525 .clk_div_bits = 8,
526 .recheck_sdio_irq = false,
527 .hs400_tune = true,
528 .pad_tune_reg = MSDC_PAD_TUNE,
529 .async_fifo = false,
530 .data_tune = false,
531 .busy_check = false,
532 .stop_clk_fix = false,
533 .enhance_rx = false,
534 .support_64g = false,
535 };
536
537 static const struct mtk_mmc_compatible mt7620_compat = {
538 .clk_div_bits = 8,
539 .recheck_sdio_irq = true,
540 .hs400_tune = false,
541 .pad_tune_reg = MSDC_PAD_TUNE,
542 .async_fifo = false,
543 .data_tune = false,
544 .busy_check = false,
545 .stop_clk_fix = false,
546 .enhance_rx = false,
547 .use_internal_cd = true,
548 };
549
550 static const struct mtk_mmc_compatible mt7622_compat = {
551 .clk_div_bits = 12,
552 .recheck_sdio_irq = true,
553 .hs400_tune = false,
554 .pad_tune_reg = MSDC_PAD_TUNE0,
555 .async_fifo = true,
556 .data_tune = true,
557 .busy_check = true,
558 .stop_clk_fix = true,
559 .enhance_rx = true,
560 .support_64g = false,
561 };
562
563 static const struct mtk_mmc_compatible mt7986_compat = {
564 .clk_div_bits = 12,
565 .recheck_sdio_irq = true,
566 .hs400_tune = false,
567 .pad_tune_reg = MSDC_PAD_TUNE0,
568 .async_fifo = true,
569 .data_tune = true,
570 .busy_check = true,
571 .stop_clk_fix = true,
572 .enhance_rx = true,
573 .support_64g = true,
574 };
575
576 static const struct mtk_mmc_compatible mt8135_compat = {
577 .clk_div_bits = 8,
578 .recheck_sdio_irq = true,
579 .hs400_tune = false,
580 .pad_tune_reg = MSDC_PAD_TUNE,
581 .async_fifo = false,
582 .data_tune = false,
583 .busy_check = false,
584 .stop_clk_fix = false,
585 .enhance_rx = false,
586 .support_64g = false,
587 };
588
589 static const struct mtk_mmc_compatible mt8173_compat = {
590 .clk_div_bits = 8,
591 .recheck_sdio_irq = true,
592 .hs400_tune = true,
593 .pad_tune_reg = MSDC_PAD_TUNE,
594 .async_fifo = false,
595 .data_tune = false,
596 .busy_check = false,
597 .stop_clk_fix = false,
598 .enhance_rx = false,
599 .support_64g = false,
600 };
601
602 static const struct mtk_mmc_compatible mt8183_compat = {
603 .clk_div_bits = 12,
604 .recheck_sdio_irq = false,
605 .hs400_tune = false,
606 .pad_tune_reg = MSDC_PAD_TUNE0,
607 .async_fifo = true,
608 .data_tune = true,
609 .busy_check = true,
610 .stop_clk_fix = true,
611 .enhance_rx = true,
612 .support_64g = true,
613 };
614
615 static const struct mtk_mmc_compatible mt8516_compat = {
616 .clk_div_bits = 12,
617 .recheck_sdio_irq = true,
618 .hs400_tune = false,
619 .pad_tune_reg = MSDC_PAD_TUNE0,
620 .async_fifo = true,
621 .data_tune = true,
622 .busy_check = true,
623 .stop_clk_fix = true,
624 };
625
626 static const struct of_device_id msdc_of_ids[] = {
627 { .compatible = "mediatek,mt2701-mmc", .data = &mt2701_compat},
628 { .compatible = "mediatek,mt2712-mmc", .data = &mt2712_compat},
629 { .compatible = "mediatek,mt6779-mmc", .data = &mt6779_compat},
630 { .compatible = "mediatek,mt6795-mmc", .data = &mt6795_compat},
631 { .compatible = "mediatek,mt7620-mmc", .data = &mt7620_compat},
632 { .compatible = "mediatek,mt7622-mmc", .data = &mt7622_compat},
633 { .compatible = "mediatek,mt7986-mmc", .data = &mt7986_compat},
634 { .compatible = "mediatek,mt8135-mmc", .data = &mt8135_compat},
635 { .compatible = "mediatek,mt8173-mmc", .data = &mt8173_compat},
636 { .compatible = "mediatek,mt8183-mmc", .data = &mt8183_compat},
637 { .compatible = "mediatek,mt8516-mmc", .data = &mt8516_compat},
638
639 {}
640 };
641 MODULE_DEVICE_TABLE(of, msdc_of_ids);
642
sdr_set_bits(void __iomem * reg,u32 bs)643 static void sdr_set_bits(void __iomem *reg, u32 bs)
644 {
645 u32 val = readl(reg);
646
647 val |= bs;
648 writel(val, reg);
649 }
650
sdr_clr_bits(void __iomem * reg,u32 bs)651 static void sdr_clr_bits(void __iomem *reg, u32 bs)
652 {
653 u32 val = readl(reg);
654
655 val &= ~bs;
656 writel(val, reg);
657 }
658
sdr_set_field(void __iomem * reg,u32 field,u32 val)659 static void sdr_set_field(void __iomem *reg, u32 field, u32 val)
660 {
661 unsigned int tv = readl(reg);
662
663 tv &= ~field;
664 tv |= ((val) << (ffs((unsigned int)field) - 1));
665 writel(tv, reg);
666 }
667
sdr_get_field(void __iomem * reg,u32 field,u32 * val)668 static void sdr_get_field(void __iomem *reg, u32 field, u32 *val)
669 {
670 unsigned int tv = readl(reg);
671
672 *val = ((tv & field) >> (ffs((unsigned int)field) - 1));
673 }
674
msdc_reset_hw(struct msdc_host * host)675 static void msdc_reset_hw(struct msdc_host *host)
676 {
677 u32 val;
678
679 sdr_set_bits(host->base + MSDC_CFG, MSDC_CFG_RST);
680 readl_poll_timeout_atomic(host->base + MSDC_CFG, val, !(val & MSDC_CFG_RST), 0, 0);
681
682 sdr_set_bits(host->base + MSDC_FIFOCS, MSDC_FIFOCS_CLR);
683 readl_poll_timeout_atomic(host->base + MSDC_FIFOCS, val,
684 !(val & MSDC_FIFOCS_CLR), 0, 0);
685
686 val = readl(host->base + MSDC_INT);
687 writel(val, host->base + MSDC_INT);
688 }
689
690 static void msdc_cmd_next(struct msdc_host *host,
691 struct mmc_request *mrq, struct mmc_command *cmd);
692 static void __msdc_enable_sdio_irq(struct msdc_host *host, int enb);
693
694 static const u32 cmd_ints_mask = MSDC_INTEN_CMDRDY | MSDC_INTEN_RSPCRCERR |
695 MSDC_INTEN_CMDTMO | MSDC_INTEN_ACMDRDY |
696 MSDC_INTEN_ACMDCRCERR | MSDC_INTEN_ACMDTMO;
697 static const u32 data_ints_mask = MSDC_INTEN_XFER_COMPL | MSDC_INTEN_DATTMO |
698 MSDC_INTEN_DATCRCERR | MSDC_INTEN_DMA_BDCSERR |
699 MSDC_INTEN_DMA_GPDCSERR | MSDC_INTEN_DMA_PROTECT;
700
msdc_dma_calcs(u8 * buf,u32 len)701 static u8 msdc_dma_calcs(u8 *buf, u32 len)
702 {
703 u32 i, sum = 0;
704
705 for (i = 0; i < len; i++)
706 sum += buf[i];
707 return 0xff - (u8) sum;
708 }
709
msdc_dma_setup(struct msdc_host * host,struct msdc_dma * dma,struct mmc_data * data)710 static inline void msdc_dma_setup(struct msdc_host *host, struct msdc_dma *dma,
711 struct mmc_data *data)
712 {
713 unsigned int j, dma_len;
714 dma_addr_t dma_address;
715 u32 dma_ctrl;
716 struct scatterlist *sg;
717 struct mt_gpdma_desc *gpd;
718 struct mt_bdma_desc *bd;
719
720 sg = data->sg;
721
722 gpd = dma->gpd;
723 bd = dma->bd;
724
725 /* modify gpd */
726 gpd->gpd_info |= GPDMA_DESC_HWO;
727 gpd->gpd_info |= GPDMA_DESC_BDP;
728 /* need to clear first. use these bits to calc checksum */
729 gpd->gpd_info &= ~GPDMA_DESC_CHECKSUM;
730 gpd->gpd_info |= msdc_dma_calcs((u8 *) gpd, 16) << 8;
731
732 /* modify bd */
733 for_each_sg(data->sg, sg, data->sg_count, j) {
734 dma_address = sg_dma_address(sg);
735 dma_len = sg_dma_len(sg);
736
737 /* init bd */
738 bd[j].bd_info &= ~BDMA_DESC_BLKPAD;
739 bd[j].bd_info &= ~BDMA_DESC_DWPAD;
740 bd[j].ptr = lower_32_bits(dma_address);
741 if (host->dev_comp->support_64g) {
742 bd[j].bd_info &= ~BDMA_DESC_PTR_H4;
743 bd[j].bd_info |= (upper_32_bits(dma_address) & 0xf)
744 << 28;
745 }
746
747 if (host->dev_comp->support_64g) {
748 bd[j].bd_data_len &= ~BDMA_DESC_BUFLEN_EXT;
749 bd[j].bd_data_len |= (dma_len & BDMA_DESC_BUFLEN_EXT);
750 } else {
751 bd[j].bd_data_len &= ~BDMA_DESC_BUFLEN;
752 bd[j].bd_data_len |= (dma_len & BDMA_DESC_BUFLEN);
753 }
754
755 if (j == data->sg_count - 1) /* the last bd */
756 bd[j].bd_info |= BDMA_DESC_EOL;
757 else
758 bd[j].bd_info &= ~BDMA_DESC_EOL;
759
760 /* checksum need to clear first */
761 bd[j].bd_info &= ~BDMA_DESC_CHECKSUM;
762 bd[j].bd_info |= msdc_dma_calcs((u8 *)(&bd[j]), 16) << 8;
763 }
764
765 sdr_set_field(host->base + MSDC_DMA_CFG, MSDC_DMA_CFG_DECSEN, 1);
766 dma_ctrl = readl_relaxed(host->base + MSDC_DMA_CTRL);
767 dma_ctrl &= ~(MSDC_DMA_CTRL_BRUSTSZ | MSDC_DMA_CTRL_MODE);
768 dma_ctrl |= (MSDC_BURST_64B << 12 | BIT(8));
769 writel_relaxed(dma_ctrl, host->base + MSDC_DMA_CTRL);
770 if (host->dev_comp->support_64g)
771 sdr_set_field(host->base + DMA_SA_H4BIT, DMA_ADDR_HIGH_4BIT,
772 upper_32_bits(dma->gpd_addr) & 0xf);
773 writel(lower_32_bits(dma->gpd_addr), host->base + MSDC_DMA_SA);
774 }
775
msdc_prepare_data(struct msdc_host * host,struct mmc_data * data)776 static void msdc_prepare_data(struct msdc_host *host, struct mmc_data *data)
777 {
778 if (!(data->host_cookie & MSDC_PREPARE_FLAG)) {
779 data->sg_count = dma_map_sg(host->dev, data->sg, data->sg_len,
780 mmc_get_dma_dir(data));
781 if (data->sg_count)
782 data->host_cookie |= MSDC_PREPARE_FLAG;
783 }
784 }
785
msdc_data_prepared(struct mmc_data * data)786 static bool msdc_data_prepared(struct mmc_data *data)
787 {
788 return data->host_cookie & MSDC_PREPARE_FLAG;
789 }
790
msdc_unprepare_data(struct msdc_host * host,struct mmc_data * data)791 static void msdc_unprepare_data(struct msdc_host *host, struct mmc_data *data)
792 {
793 if (data->host_cookie & MSDC_ASYNC_FLAG)
794 return;
795
796 if (data->host_cookie & MSDC_PREPARE_FLAG) {
797 dma_unmap_sg(host->dev, data->sg, data->sg_len,
798 mmc_get_dma_dir(data));
799 data->host_cookie &= ~MSDC_PREPARE_FLAG;
800 }
801 }
802
msdc_timeout_cal(struct msdc_host * host,u64 ns,u64 clks)803 static u64 msdc_timeout_cal(struct msdc_host *host, u64 ns, u64 clks)
804 {
805 struct mmc_host *mmc = mmc_from_priv(host);
806 u64 timeout;
807 u32 clk_ns, mode = 0;
808
809 if (mmc->actual_clock == 0) {
810 timeout = 0;
811 } else {
812 clk_ns = 1000000000U / mmc->actual_clock;
813 timeout = ns + clk_ns - 1;
814 do_div(timeout, clk_ns);
815 timeout += clks;
816 /* in 1048576 sclk cycle unit */
817 timeout = DIV_ROUND_UP(timeout, BIT(20));
818 if (host->dev_comp->clk_div_bits == 8)
819 sdr_get_field(host->base + MSDC_CFG,
820 MSDC_CFG_CKMOD, &mode);
821 else
822 sdr_get_field(host->base + MSDC_CFG,
823 MSDC_CFG_CKMOD_EXTRA, &mode);
824 /*DDR mode will double the clk cycles for data timeout */
825 timeout = mode >= 2 ? timeout * 2 : timeout;
826 timeout = timeout > 1 ? timeout - 1 : 0;
827 }
828 return timeout;
829 }
830
831 /* clock control primitives */
msdc_set_timeout(struct msdc_host * host,u64 ns,u64 clks)832 static void msdc_set_timeout(struct msdc_host *host, u64 ns, u64 clks)
833 {
834 u64 timeout;
835
836 host->timeout_ns = ns;
837 host->timeout_clks = clks;
838
839 timeout = msdc_timeout_cal(host, ns, clks);
840 sdr_set_field(host->base + SDC_CFG, SDC_CFG_DTOC,
841 min_t(u32, timeout, 255));
842 }
843
msdc_set_busy_timeout(struct msdc_host * host,u64 ns,u64 clks)844 static void msdc_set_busy_timeout(struct msdc_host *host, u64 ns, u64 clks)
845 {
846 u64 timeout;
847
848 timeout = msdc_timeout_cal(host, ns, clks);
849 sdr_set_field(host->base + SDC_CFG, SDC_CFG_WRDTOC,
850 min_t(u32, timeout, 8191));
851 }
852
msdc_gate_clock(struct msdc_host * host)853 static void msdc_gate_clock(struct msdc_host *host)
854 {
855 clk_bulk_disable_unprepare(MSDC_NR_CLOCKS, host->bulk_clks);
856 clk_disable_unprepare(host->crypto_clk);
857 clk_disable_unprepare(host->src_clk_cg);
858 clk_disable_unprepare(host->src_clk);
859 clk_disable_unprepare(host->bus_clk);
860 clk_disable_unprepare(host->h_clk);
861 }
862
msdc_ungate_clock(struct msdc_host * host)863 static int msdc_ungate_clock(struct msdc_host *host)
864 {
865 u32 val;
866 int ret;
867
868 clk_prepare_enable(host->h_clk);
869 clk_prepare_enable(host->bus_clk);
870 clk_prepare_enable(host->src_clk);
871 clk_prepare_enable(host->src_clk_cg);
872 clk_prepare_enable(host->crypto_clk);
873 ret = clk_bulk_prepare_enable(MSDC_NR_CLOCKS, host->bulk_clks);
874 if (ret) {
875 dev_err(host->dev, "Cannot enable pclk/axi/ahb clock gates\n");
876 return ret;
877 }
878
879 return readl_poll_timeout(host->base + MSDC_CFG, val,
880 (val & MSDC_CFG_CKSTB), 1, 20000);
881 }
882
msdc_set_mclk(struct msdc_host * host,unsigned char timing,u32 hz)883 static void msdc_set_mclk(struct msdc_host *host, unsigned char timing, u32 hz)
884 {
885 struct mmc_host *mmc = mmc_from_priv(host);
886 u32 mode;
887 u32 flags;
888 u32 div;
889 u32 sclk;
890 u32 tune_reg = host->dev_comp->pad_tune_reg;
891 u32 val;
892
893 if (!hz) {
894 dev_dbg(host->dev, "set mclk to 0\n");
895 host->mclk = 0;
896 mmc->actual_clock = 0;
897 sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_CKPDN);
898 return;
899 }
900
901 flags = readl(host->base + MSDC_INTEN);
902 sdr_clr_bits(host->base + MSDC_INTEN, flags);
903 if (host->dev_comp->clk_div_bits == 8)
904 sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_HS400_CK_MODE);
905 else
906 sdr_clr_bits(host->base + MSDC_CFG,
907 MSDC_CFG_HS400_CK_MODE_EXTRA);
908 if (timing == MMC_TIMING_UHS_DDR50 ||
909 timing == MMC_TIMING_MMC_DDR52 ||
910 timing == MMC_TIMING_MMC_HS400) {
911 if (timing == MMC_TIMING_MMC_HS400)
912 mode = 0x3;
913 else
914 mode = 0x2; /* ddr mode and use divisor */
915
916 if (hz >= (host->src_clk_freq >> 2)) {
917 div = 0; /* mean div = 1/4 */
918 sclk = host->src_clk_freq >> 2; /* sclk = clk / 4 */
919 } else {
920 div = (host->src_clk_freq + ((hz << 2) - 1)) / (hz << 2);
921 sclk = (host->src_clk_freq >> 2) / div;
922 div = (div >> 1);
923 }
924
925 if (timing == MMC_TIMING_MMC_HS400 &&
926 hz >= (host->src_clk_freq >> 1)) {
927 if (host->dev_comp->clk_div_bits == 8)
928 sdr_set_bits(host->base + MSDC_CFG,
929 MSDC_CFG_HS400_CK_MODE);
930 else
931 sdr_set_bits(host->base + MSDC_CFG,
932 MSDC_CFG_HS400_CK_MODE_EXTRA);
933 sclk = host->src_clk_freq >> 1;
934 div = 0; /* div is ignore when bit18 is set */
935 }
936 } else if (hz >= host->src_clk_freq) {
937 mode = 0x1; /* no divisor */
938 div = 0;
939 sclk = host->src_clk_freq;
940 } else {
941 mode = 0x0; /* use divisor */
942 if (hz >= (host->src_clk_freq >> 1)) {
943 div = 0; /* mean div = 1/2 */
944 sclk = host->src_clk_freq >> 1; /* sclk = clk / 2 */
945 } else {
946 div = (host->src_clk_freq + ((hz << 2) - 1)) / (hz << 2);
947 sclk = (host->src_clk_freq >> 2) / div;
948 }
949 }
950 sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_CKPDN);
951
952 clk_disable_unprepare(host->src_clk_cg);
953 if (host->dev_comp->clk_div_bits == 8)
954 sdr_set_field(host->base + MSDC_CFG,
955 MSDC_CFG_CKMOD | MSDC_CFG_CKDIV,
956 (mode << 8) | div);
957 else
958 sdr_set_field(host->base + MSDC_CFG,
959 MSDC_CFG_CKMOD_EXTRA | MSDC_CFG_CKDIV_EXTRA,
960 (mode << 12) | div);
961
962 clk_prepare_enable(host->src_clk_cg);
963 readl_poll_timeout(host->base + MSDC_CFG, val, (val & MSDC_CFG_CKSTB), 0, 0);
964 sdr_set_bits(host->base + MSDC_CFG, MSDC_CFG_CKPDN);
965 mmc->actual_clock = sclk;
966 host->mclk = hz;
967 host->timing = timing;
968 /* need because clk changed. */
969 msdc_set_timeout(host, host->timeout_ns, host->timeout_clks);
970 sdr_set_bits(host->base + MSDC_INTEN, flags);
971
972 /*
973 * mmc_select_hs400() will drop to 50Mhz and High speed mode,
974 * tune result of hs200/200Mhz is not suitable for 50Mhz
975 */
976 if (mmc->actual_clock <= 52000000) {
977 writel(host->def_tune_para.iocon, host->base + MSDC_IOCON);
978 if (host->top_base) {
979 writel(host->def_tune_para.emmc_top_control,
980 host->top_base + EMMC_TOP_CONTROL);
981 writel(host->def_tune_para.emmc_top_cmd,
982 host->top_base + EMMC_TOP_CMD);
983 } else {
984 writel(host->def_tune_para.pad_tune,
985 host->base + tune_reg);
986 }
987 } else {
988 writel(host->saved_tune_para.iocon, host->base + MSDC_IOCON);
989 writel(host->saved_tune_para.pad_cmd_tune,
990 host->base + PAD_CMD_TUNE);
991 if (host->top_base) {
992 writel(host->saved_tune_para.emmc_top_control,
993 host->top_base + EMMC_TOP_CONTROL);
994 writel(host->saved_tune_para.emmc_top_cmd,
995 host->top_base + EMMC_TOP_CMD);
996 } else {
997 writel(host->saved_tune_para.pad_tune,
998 host->base + tune_reg);
999 }
1000 }
1001
1002 if (timing == MMC_TIMING_MMC_HS400 &&
1003 host->dev_comp->hs400_tune)
1004 sdr_set_field(host->base + tune_reg,
1005 MSDC_PAD_TUNE_CMDRRDLY,
1006 host->hs400_cmd_int_delay);
1007 dev_dbg(host->dev, "sclk: %d, timing: %d\n", mmc->actual_clock,
1008 timing);
1009 }
1010
msdc_cmd_find_resp(struct msdc_host * host,struct mmc_command * cmd)1011 static inline u32 msdc_cmd_find_resp(struct msdc_host *host,
1012 struct mmc_command *cmd)
1013 {
1014 u32 resp;
1015
1016 switch (mmc_resp_type(cmd)) {
1017 /* Actually, R1, R5, R6, R7 are the same */
1018 case MMC_RSP_R1:
1019 resp = 0x1;
1020 break;
1021 case MMC_RSP_R1B:
1022 resp = 0x7;
1023 break;
1024 case MMC_RSP_R2:
1025 resp = 0x2;
1026 break;
1027 case MMC_RSP_R3:
1028 resp = 0x3;
1029 break;
1030 case MMC_RSP_NONE:
1031 default:
1032 resp = 0x0;
1033 break;
1034 }
1035
1036 return resp;
1037 }
1038
msdc_cmd_prepare_raw_cmd(struct msdc_host * host,struct mmc_request * mrq,struct mmc_command * cmd)1039 static inline u32 msdc_cmd_prepare_raw_cmd(struct msdc_host *host,
1040 struct mmc_request *mrq, struct mmc_command *cmd)
1041 {
1042 struct mmc_host *mmc = mmc_from_priv(host);
1043 /* rawcmd :
1044 * vol_swt << 30 | auto_cmd << 28 | blklen << 16 | go_irq << 15 |
1045 * stop << 14 | rw << 13 | dtype << 11 | rsptyp << 7 | brk << 6 | opcode
1046 */
1047 u32 opcode = cmd->opcode;
1048 u32 resp = msdc_cmd_find_resp(host, cmd);
1049 u32 rawcmd = (opcode & 0x3f) | ((resp & 0x7) << 7);
1050
1051 host->cmd_rsp = resp;
1052
1053 if ((opcode == SD_IO_RW_DIRECT && cmd->flags == (unsigned int) -1) ||
1054 opcode == MMC_STOP_TRANSMISSION)
1055 rawcmd |= BIT(14);
1056 else if (opcode == SD_SWITCH_VOLTAGE)
1057 rawcmd |= BIT(30);
1058 else if (opcode == SD_APP_SEND_SCR ||
1059 opcode == SD_APP_SEND_NUM_WR_BLKS ||
1060 (opcode == SD_SWITCH && mmc_cmd_type(cmd) == MMC_CMD_ADTC) ||
1061 (opcode == SD_APP_SD_STATUS && mmc_cmd_type(cmd) == MMC_CMD_ADTC) ||
1062 (opcode == MMC_SEND_EXT_CSD && mmc_cmd_type(cmd) == MMC_CMD_ADTC))
1063 rawcmd |= BIT(11);
1064
1065 if (cmd->data) {
1066 struct mmc_data *data = cmd->data;
1067
1068 if (mmc_op_multi(opcode)) {
1069 if (mmc_card_mmc(mmc->card) && mrq->sbc &&
1070 !(mrq->sbc->arg & 0xFFFF0000))
1071 rawcmd |= BIT(29); /* AutoCMD23 */
1072 }
1073
1074 rawcmd |= ((data->blksz & 0xFFF) << 16);
1075 if (data->flags & MMC_DATA_WRITE)
1076 rawcmd |= BIT(13);
1077 if (data->blocks > 1)
1078 rawcmd |= BIT(12);
1079 else
1080 rawcmd |= BIT(11);
1081 /* Always use dma mode */
1082 sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_PIO);
1083
1084 if (host->timeout_ns != data->timeout_ns ||
1085 host->timeout_clks != data->timeout_clks)
1086 msdc_set_timeout(host, data->timeout_ns,
1087 data->timeout_clks);
1088
1089 writel(data->blocks, host->base + SDC_BLK_NUM);
1090 }
1091 return rawcmd;
1092 }
1093
msdc_start_data(struct msdc_host * host,struct mmc_command * cmd,struct mmc_data * data)1094 static void msdc_start_data(struct msdc_host *host, struct mmc_command *cmd,
1095 struct mmc_data *data)
1096 {
1097 bool read;
1098
1099 WARN_ON(host->data);
1100 host->data = data;
1101 read = data->flags & MMC_DATA_READ;
1102
1103 mod_delayed_work(system_wq, &host->req_timeout, DAT_TIMEOUT);
1104 msdc_dma_setup(host, &host->dma, data);
1105 sdr_set_bits(host->base + MSDC_INTEN, data_ints_mask);
1106 sdr_set_field(host->base + MSDC_DMA_CTRL, MSDC_DMA_CTRL_START, 1);
1107 dev_dbg(host->dev, "DMA start\n");
1108 dev_dbg(host->dev, "%s: cmd=%d DMA data: %d blocks; read=%d\n",
1109 __func__, cmd->opcode, data->blocks, read);
1110 }
1111
msdc_auto_cmd_done(struct msdc_host * host,int events,struct mmc_command * cmd)1112 static int msdc_auto_cmd_done(struct msdc_host *host, int events,
1113 struct mmc_command *cmd)
1114 {
1115 u32 *rsp = cmd->resp;
1116
1117 rsp[0] = readl(host->base + SDC_ACMD_RESP);
1118
1119 if (events & MSDC_INT_ACMDRDY) {
1120 cmd->error = 0;
1121 } else {
1122 msdc_reset_hw(host);
1123 if (events & MSDC_INT_ACMDCRCERR) {
1124 cmd->error = -EILSEQ;
1125 host->error |= REQ_STOP_EIO;
1126 } else if (events & MSDC_INT_ACMDTMO) {
1127 cmd->error = -ETIMEDOUT;
1128 host->error |= REQ_STOP_TMO;
1129 }
1130 dev_err(host->dev,
1131 "%s: AUTO_CMD%d arg=%08X; rsp %08X; cmd_error=%d\n",
1132 __func__, cmd->opcode, cmd->arg, rsp[0], cmd->error);
1133 }
1134 return cmd->error;
1135 }
1136
1137 /*
1138 * msdc_recheck_sdio_irq - recheck whether the SDIO irq is lost
1139 *
1140 * Host controller may lost interrupt in some special case.
1141 * Add SDIO irq recheck mechanism to make sure all interrupts
1142 * can be processed immediately
1143 */
msdc_recheck_sdio_irq(struct msdc_host * host)1144 static void msdc_recheck_sdio_irq(struct msdc_host *host)
1145 {
1146 struct mmc_host *mmc = mmc_from_priv(host);
1147 u32 reg_int, reg_inten, reg_ps;
1148
1149 if (mmc->caps & MMC_CAP_SDIO_IRQ) {
1150 reg_inten = readl(host->base + MSDC_INTEN);
1151 if (reg_inten & MSDC_INTEN_SDIOIRQ) {
1152 reg_int = readl(host->base + MSDC_INT);
1153 reg_ps = readl(host->base + MSDC_PS);
1154 if (!(reg_int & MSDC_INT_SDIOIRQ ||
1155 reg_ps & MSDC_PS_DATA1)) {
1156 __msdc_enable_sdio_irq(host, 0);
1157 sdio_signal_irq(mmc);
1158 }
1159 }
1160 }
1161 }
1162
msdc_track_cmd_data(struct msdc_host * host,struct mmc_command * cmd)1163 static void msdc_track_cmd_data(struct msdc_host *host, struct mmc_command *cmd)
1164 {
1165 if (host->error &&
1166 ((!mmc_op_tuning(cmd->opcode) && !host->hs400_tuning) ||
1167 cmd->error == -ETIMEDOUT))
1168 dev_warn(host->dev, "%s: cmd=%d arg=%08X; host->error=0x%08X\n",
1169 __func__, cmd->opcode, cmd->arg, host->error);
1170 }
1171
msdc_request_done(struct msdc_host * host,struct mmc_request * mrq)1172 static void msdc_request_done(struct msdc_host *host, struct mmc_request *mrq)
1173 {
1174 unsigned long flags;
1175
1176 /*
1177 * No need check the return value of cancel_delayed_work, as only ONE
1178 * path will go here!
1179 */
1180 cancel_delayed_work(&host->req_timeout);
1181
1182 spin_lock_irqsave(&host->lock, flags);
1183 host->mrq = NULL;
1184 spin_unlock_irqrestore(&host->lock, flags);
1185
1186 msdc_track_cmd_data(host, mrq->cmd);
1187 if (mrq->data)
1188 msdc_unprepare_data(host, mrq->data);
1189 if (host->error)
1190 msdc_reset_hw(host);
1191 mmc_request_done(mmc_from_priv(host), mrq);
1192 if (host->dev_comp->recheck_sdio_irq)
1193 msdc_recheck_sdio_irq(host);
1194 }
1195
1196 /* returns true if command is fully handled; returns false otherwise */
msdc_cmd_done(struct msdc_host * host,int events,struct mmc_request * mrq,struct mmc_command * cmd)1197 static bool msdc_cmd_done(struct msdc_host *host, int events,
1198 struct mmc_request *mrq, struct mmc_command *cmd)
1199 {
1200 bool done = false;
1201 bool sbc_error;
1202 unsigned long flags;
1203 u32 *rsp;
1204
1205 if (mrq->sbc && cmd == mrq->cmd &&
1206 (events & (MSDC_INT_ACMDRDY | MSDC_INT_ACMDCRCERR
1207 | MSDC_INT_ACMDTMO)))
1208 msdc_auto_cmd_done(host, events, mrq->sbc);
1209
1210 sbc_error = mrq->sbc && mrq->sbc->error;
1211
1212 if (!sbc_error && !(events & (MSDC_INT_CMDRDY
1213 | MSDC_INT_RSPCRCERR
1214 | MSDC_INT_CMDTMO)))
1215 return done;
1216
1217 spin_lock_irqsave(&host->lock, flags);
1218 done = !host->cmd;
1219 host->cmd = NULL;
1220 spin_unlock_irqrestore(&host->lock, flags);
1221
1222 if (done)
1223 return true;
1224 rsp = cmd->resp;
1225
1226 sdr_clr_bits(host->base + MSDC_INTEN, cmd_ints_mask);
1227
1228 if (cmd->flags & MMC_RSP_PRESENT) {
1229 if (cmd->flags & MMC_RSP_136) {
1230 rsp[0] = readl(host->base + SDC_RESP3);
1231 rsp[1] = readl(host->base + SDC_RESP2);
1232 rsp[2] = readl(host->base + SDC_RESP1);
1233 rsp[3] = readl(host->base + SDC_RESP0);
1234 } else {
1235 rsp[0] = readl(host->base + SDC_RESP0);
1236 }
1237 }
1238
1239 if (!sbc_error && !(events & MSDC_INT_CMDRDY)) {
1240 if ((events & MSDC_INT_CMDTMO && !host->hs400_tuning) ||
1241 (!mmc_op_tuning(cmd->opcode) && !host->hs400_tuning))
1242 /*
1243 * should not clear fifo/interrupt as the tune data
1244 * may have already come when cmd19/cmd21 gets response
1245 * CRC error.
1246 */
1247 msdc_reset_hw(host);
1248 if (events & MSDC_INT_RSPCRCERR) {
1249 cmd->error = -EILSEQ;
1250 host->error |= REQ_CMD_EIO;
1251 } else if (events & MSDC_INT_CMDTMO) {
1252 cmd->error = -ETIMEDOUT;
1253 host->error |= REQ_CMD_TMO;
1254 }
1255 }
1256 if (cmd->error)
1257 dev_dbg(host->dev,
1258 "%s: cmd=%d arg=%08X; rsp %08X; cmd_error=%d\n",
1259 __func__, cmd->opcode, cmd->arg, rsp[0],
1260 cmd->error);
1261
1262 msdc_cmd_next(host, mrq, cmd);
1263 return true;
1264 }
1265
1266 /* It is the core layer's responsibility to ensure card status
1267 * is correct before issue a request. but host design do below
1268 * checks recommended.
1269 */
msdc_cmd_is_ready(struct msdc_host * host,struct mmc_request * mrq,struct mmc_command * cmd)1270 static inline bool msdc_cmd_is_ready(struct msdc_host *host,
1271 struct mmc_request *mrq, struct mmc_command *cmd)
1272 {
1273 u32 val;
1274 int ret;
1275
1276 /* The max busy time we can endure is 20ms */
1277 ret = readl_poll_timeout_atomic(host->base + SDC_STS, val,
1278 !(val & SDC_STS_CMDBUSY), 1, 20000);
1279 if (ret) {
1280 dev_err(host->dev, "CMD bus busy detected\n");
1281 host->error |= REQ_CMD_BUSY;
1282 msdc_cmd_done(host, MSDC_INT_CMDTMO, mrq, cmd);
1283 return false;
1284 }
1285
1286 if (mmc_resp_type(cmd) == MMC_RSP_R1B || cmd->data) {
1287 /* R1B or with data, should check SDCBUSY */
1288 ret = readl_poll_timeout_atomic(host->base + SDC_STS, val,
1289 !(val & SDC_STS_SDCBUSY), 1, 20000);
1290 if (ret) {
1291 dev_err(host->dev, "Controller busy detected\n");
1292 host->error |= REQ_CMD_BUSY;
1293 msdc_cmd_done(host, MSDC_INT_CMDTMO, mrq, cmd);
1294 return false;
1295 }
1296 }
1297 return true;
1298 }
1299
msdc_start_command(struct msdc_host * host,struct mmc_request * mrq,struct mmc_command * cmd)1300 static void msdc_start_command(struct msdc_host *host,
1301 struct mmc_request *mrq, struct mmc_command *cmd)
1302 {
1303 u32 rawcmd;
1304 unsigned long flags;
1305
1306 WARN_ON(host->cmd);
1307 host->cmd = cmd;
1308
1309 mod_delayed_work(system_wq, &host->req_timeout, DAT_TIMEOUT);
1310 if (!msdc_cmd_is_ready(host, mrq, cmd))
1311 return;
1312
1313 if ((readl(host->base + MSDC_FIFOCS) & MSDC_FIFOCS_TXCNT) >> 16 ||
1314 readl(host->base + MSDC_FIFOCS) & MSDC_FIFOCS_RXCNT) {
1315 dev_err(host->dev, "TX/RX FIFO non-empty before start of IO. Reset\n");
1316 msdc_reset_hw(host);
1317 }
1318
1319 cmd->error = 0;
1320 rawcmd = msdc_cmd_prepare_raw_cmd(host, mrq, cmd);
1321
1322 spin_lock_irqsave(&host->lock, flags);
1323 sdr_set_bits(host->base + MSDC_INTEN, cmd_ints_mask);
1324 spin_unlock_irqrestore(&host->lock, flags);
1325
1326 writel(cmd->arg, host->base + SDC_ARG);
1327 writel(rawcmd, host->base + SDC_CMD);
1328 }
1329
msdc_cmd_next(struct msdc_host * host,struct mmc_request * mrq,struct mmc_command * cmd)1330 static void msdc_cmd_next(struct msdc_host *host,
1331 struct mmc_request *mrq, struct mmc_command *cmd)
1332 {
1333 if ((cmd->error && !host->hs400_tuning &&
1334 !(cmd->error == -EILSEQ &&
1335 mmc_op_tuning(cmd->opcode))) ||
1336 (mrq->sbc && mrq->sbc->error))
1337 msdc_request_done(host, mrq);
1338 else if (cmd == mrq->sbc)
1339 msdc_start_command(host, mrq, mrq->cmd);
1340 else if (!cmd->data)
1341 msdc_request_done(host, mrq);
1342 else
1343 msdc_start_data(host, cmd, cmd->data);
1344 }
1345
msdc_ops_request(struct mmc_host * mmc,struct mmc_request * mrq)1346 static void msdc_ops_request(struct mmc_host *mmc, struct mmc_request *mrq)
1347 {
1348 struct msdc_host *host = mmc_priv(mmc);
1349
1350 host->error = 0;
1351 WARN_ON(host->mrq);
1352 host->mrq = mrq;
1353
1354 if (mrq->data) {
1355 msdc_prepare_data(host, mrq->data);
1356 if (!msdc_data_prepared(mrq->data)) {
1357 host->mrq = NULL;
1358 /*
1359 * Failed to prepare DMA area, fail fast before
1360 * starting any commands.
1361 */
1362 mrq->cmd->error = -ENOSPC;
1363 mmc_request_done(mmc_from_priv(host), mrq);
1364 return;
1365 }
1366 }
1367
1368 /* if SBC is required, we have HW option and SW option.
1369 * if HW option is enabled, and SBC does not have "special" flags,
1370 * use HW option, otherwise use SW option
1371 */
1372 if (mrq->sbc && (!mmc_card_mmc(mmc->card) ||
1373 (mrq->sbc->arg & 0xFFFF0000)))
1374 msdc_start_command(host, mrq, mrq->sbc);
1375 else
1376 msdc_start_command(host, mrq, mrq->cmd);
1377 }
1378
msdc_pre_req(struct mmc_host * mmc,struct mmc_request * mrq)1379 static void msdc_pre_req(struct mmc_host *mmc, struct mmc_request *mrq)
1380 {
1381 struct msdc_host *host = mmc_priv(mmc);
1382 struct mmc_data *data = mrq->data;
1383
1384 if (!data)
1385 return;
1386
1387 msdc_prepare_data(host, data);
1388 data->host_cookie |= MSDC_ASYNC_FLAG;
1389 }
1390
msdc_post_req(struct mmc_host * mmc,struct mmc_request * mrq,int err)1391 static void msdc_post_req(struct mmc_host *mmc, struct mmc_request *mrq,
1392 int err)
1393 {
1394 struct msdc_host *host = mmc_priv(mmc);
1395 struct mmc_data *data = mrq->data;
1396
1397 if (!data)
1398 return;
1399
1400 if (data->host_cookie) {
1401 data->host_cookie &= ~MSDC_ASYNC_FLAG;
1402 msdc_unprepare_data(host, data);
1403 }
1404 }
1405
msdc_data_xfer_next(struct msdc_host * host,struct mmc_request * mrq)1406 static void msdc_data_xfer_next(struct msdc_host *host, struct mmc_request *mrq)
1407 {
1408 if (mmc_op_multi(mrq->cmd->opcode) && mrq->stop && !mrq->stop->error &&
1409 !mrq->sbc)
1410 msdc_start_command(host, mrq, mrq->stop);
1411 else
1412 msdc_request_done(host, mrq);
1413 }
1414
msdc_data_xfer_done(struct msdc_host * host,u32 events,struct mmc_request * mrq,struct mmc_data * data)1415 static void msdc_data_xfer_done(struct msdc_host *host, u32 events,
1416 struct mmc_request *mrq, struct mmc_data *data)
1417 {
1418 struct mmc_command *stop;
1419 unsigned long flags;
1420 bool done;
1421 unsigned int check_data = events &
1422 (MSDC_INT_XFER_COMPL | MSDC_INT_DATCRCERR | MSDC_INT_DATTMO
1423 | MSDC_INT_DMA_BDCSERR | MSDC_INT_DMA_GPDCSERR
1424 | MSDC_INT_DMA_PROTECT);
1425 u32 val;
1426 int ret;
1427
1428 spin_lock_irqsave(&host->lock, flags);
1429 done = !host->data;
1430 if (check_data)
1431 host->data = NULL;
1432 spin_unlock_irqrestore(&host->lock, flags);
1433
1434 if (done)
1435 return;
1436 stop = data->stop;
1437
1438 if (check_data || (stop && stop->error)) {
1439 dev_dbg(host->dev, "DMA status: 0x%8X\n",
1440 readl(host->base + MSDC_DMA_CFG));
1441 sdr_set_field(host->base + MSDC_DMA_CTRL, MSDC_DMA_CTRL_STOP,
1442 1);
1443
1444 ret = readl_poll_timeout_atomic(host->base + MSDC_DMA_CTRL, val,
1445 !(val & MSDC_DMA_CTRL_STOP), 1, 20000);
1446 if (ret)
1447 dev_dbg(host->dev, "DMA stop timed out\n");
1448
1449 ret = readl_poll_timeout_atomic(host->base + MSDC_DMA_CFG, val,
1450 !(val & MSDC_DMA_CFG_STS), 1, 20000);
1451 if (ret)
1452 dev_dbg(host->dev, "DMA inactive timed out\n");
1453
1454 sdr_clr_bits(host->base + MSDC_INTEN, data_ints_mask);
1455 dev_dbg(host->dev, "DMA stop\n");
1456
1457 if ((events & MSDC_INT_XFER_COMPL) && (!stop || !stop->error)) {
1458 data->bytes_xfered = data->blocks * data->blksz;
1459 } else {
1460 dev_dbg(host->dev, "interrupt events: %x\n", events);
1461 msdc_reset_hw(host);
1462 host->error |= REQ_DAT_ERR;
1463 data->bytes_xfered = 0;
1464
1465 if (events & MSDC_INT_DATTMO)
1466 data->error = -ETIMEDOUT;
1467 else if (events & MSDC_INT_DATCRCERR)
1468 data->error = -EILSEQ;
1469
1470 dev_dbg(host->dev, "%s: cmd=%d; blocks=%d",
1471 __func__, mrq->cmd->opcode, data->blocks);
1472 dev_dbg(host->dev, "data_error=%d xfer_size=%d\n",
1473 (int)data->error, data->bytes_xfered);
1474 }
1475
1476 msdc_data_xfer_next(host, mrq);
1477 }
1478 }
1479
msdc_set_buswidth(struct msdc_host * host,u32 width)1480 static void msdc_set_buswidth(struct msdc_host *host, u32 width)
1481 {
1482 u32 val = readl(host->base + SDC_CFG);
1483
1484 val &= ~SDC_CFG_BUSWIDTH;
1485
1486 switch (width) {
1487 default:
1488 case MMC_BUS_WIDTH_1:
1489 val |= (MSDC_BUS_1BITS << 16);
1490 break;
1491 case MMC_BUS_WIDTH_4:
1492 val |= (MSDC_BUS_4BITS << 16);
1493 break;
1494 case MMC_BUS_WIDTH_8:
1495 val |= (MSDC_BUS_8BITS << 16);
1496 break;
1497 }
1498
1499 writel(val, host->base + SDC_CFG);
1500 dev_dbg(host->dev, "Bus Width = %d", width);
1501 }
1502
msdc_ops_switch_volt(struct mmc_host * mmc,struct mmc_ios * ios)1503 static int msdc_ops_switch_volt(struct mmc_host *mmc, struct mmc_ios *ios)
1504 {
1505 struct msdc_host *host = mmc_priv(mmc);
1506 int ret;
1507
1508 if (!IS_ERR(mmc->supply.vqmmc)) {
1509 if (ios->signal_voltage != MMC_SIGNAL_VOLTAGE_330 &&
1510 ios->signal_voltage != MMC_SIGNAL_VOLTAGE_180) {
1511 dev_err(host->dev, "Unsupported signal voltage!\n");
1512 return -EINVAL;
1513 }
1514
1515 ret = mmc_regulator_set_vqmmc(mmc, ios);
1516 if (ret < 0) {
1517 dev_dbg(host->dev, "Regulator set error %d (%d)\n",
1518 ret, ios->signal_voltage);
1519 return ret;
1520 }
1521
1522 /* Apply different pinctrl settings for different signal voltage */
1523 if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_180)
1524 pinctrl_select_state(host->pinctrl, host->pins_uhs);
1525 else
1526 pinctrl_select_state(host->pinctrl, host->pins_default);
1527 }
1528 return 0;
1529 }
1530
msdc_card_busy(struct mmc_host * mmc)1531 static int msdc_card_busy(struct mmc_host *mmc)
1532 {
1533 struct msdc_host *host = mmc_priv(mmc);
1534 u32 status = readl(host->base + MSDC_PS);
1535
1536 /* only check if data0 is low */
1537 return !(status & BIT(16));
1538 }
1539
msdc_request_timeout(struct work_struct * work)1540 static void msdc_request_timeout(struct work_struct *work)
1541 {
1542 struct msdc_host *host = container_of(work, struct msdc_host,
1543 req_timeout.work);
1544
1545 /* simulate HW timeout status */
1546 dev_err(host->dev, "%s: aborting cmd/data/mrq\n", __func__);
1547 if (host->mrq) {
1548 dev_err(host->dev, "%s: aborting mrq=%p cmd=%d\n", __func__,
1549 host->mrq, host->mrq->cmd->opcode);
1550 if (host->cmd) {
1551 dev_err(host->dev, "%s: aborting cmd=%d\n",
1552 __func__, host->cmd->opcode);
1553 msdc_cmd_done(host, MSDC_INT_CMDTMO, host->mrq,
1554 host->cmd);
1555 } else if (host->data) {
1556 dev_err(host->dev, "%s: abort data: cmd%d; %d blocks\n",
1557 __func__, host->mrq->cmd->opcode,
1558 host->data->blocks);
1559 msdc_data_xfer_done(host, MSDC_INT_DATTMO, host->mrq,
1560 host->data);
1561 }
1562 }
1563 }
1564
__msdc_enable_sdio_irq(struct msdc_host * host,int enb)1565 static void __msdc_enable_sdio_irq(struct msdc_host *host, int enb)
1566 {
1567 if (enb) {
1568 sdr_set_bits(host->base + MSDC_INTEN, MSDC_INTEN_SDIOIRQ);
1569 sdr_set_bits(host->base + SDC_CFG, SDC_CFG_SDIOIDE);
1570 if (host->dev_comp->recheck_sdio_irq)
1571 msdc_recheck_sdio_irq(host);
1572 } else {
1573 sdr_clr_bits(host->base + MSDC_INTEN, MSDC_INTEN_SDIOIRQ);
1574 sdr_clr_bits(host->base + SDC_CFG, SDC_CFG_SDIOIDE);
1575 }
1576 }
1577
msdc_enable_sdio_irq(struct mmc_host * mmc,int enb)1578 static void msdc_enable_sdio_irq(struct mmc_host *mmc, int enb)
1579 {
1580 struct msdc_host *host = mmc_priv(mmc);
1581 unsigned long flags;
1582 int ret;
1583
1584 spin_lock_irqsave(&host->lock, flags);
1585 __msdc_enable_sdio_irq(host, enb);
1586 spin_unlock_irqrestore(&host->lock, flags);
1587
1588 if (mmc_card_enable_async_irq(mmc->card) && host->pins_eint) {
1589 if (enb) {
1590 /*
1591 * In dev_pm_set_dedicated_wake_irq_reverse(), eint pin will be set to
1592 * GPIO mode. We need to restore it to SDIO DAT1 mode after that.
1593 * Since the current pinstate is pins_uhs, to ensure pinctrl select take
1594 * affect successfully, we change the pinstate to pins_eint firstly.
1595 */
1596 pinctrl_select_state(host->pinctrl, host->pins_eint);
1597 ret = dev_pm_set_dedicated_wake_irq_reverse(host->dev, host->eint_irq);
1598
1599 if (ret) {
1600 dev_err(host->dev, "Failed to register SDIO wakeup irq!\n");
1601 host->pins_eint = NULL;
1602 pm_runtime_get_noresume(host->dev);
1603 } else {
1604 dev_dbg(host->dev, "SDIO eint irq: %d!\n", host->eint_irq);
1605 }
1606
1607 pinctrl_select_state(host->pinctrl, host->pins_uhs);
1608 } else {
1609 dev_pm_clear_wake_irq(host->dev);
1610 }
1611 } else {
1612 if (enb) {
1613 /* Ensure host->pins_eint is NULL */
1614 host->pins_eint = NULL;
1615 pm_runtime_get_noresume(host->dev);
1616 } else {
1617 pm_runtime_put_noidle(host->dev);
1618 }
1619 }
1620 }
1621
msdc_cmdq_irq(struct msdc_host * host,u32 intsts)1622 static irqreturn_t msdc_cmdq_irq(struct msdc_host *host, u32 intsts)
1623 {
1624 struct mmc_host *mmc = mmc_from_priv(host);
1625 int cmd_err = 0, dat_err = 0;
1626
1627 if (intsts & MSDC_INT_RSPCRCERR) {
1628 cmd_err = -EILSEQ;
1629 dev_err(host->dev, "%s: CMD CRC ERR", __func__);
1630 } else if (intsts & MSDC_INT_CMDTMO) {
1631 cmd_err = -ETIMEDOUT;
1632 dev_err(host->dev, "%s: CMD TIMEOUT ERR", __func__);
1633 }
1634
1635 if (intsts & MSDC_INT_DATCRCERR) {
1636 dat_err = -EILSEQ;
1637 dev_err(host->dev, "%s: DATA CRC ERR", __func__);
1638 } else if (intsts & MSDC_INT_DATTMO) {
1639 dat_err = -ETIMEDOUT;
1640 dev_err(host->dev, "%s: DATA TIMEOUT ERR", __func__);
1641 }
1642
1643 if (cmd_err || dat_err) {
1644 dev_err(host->dev, "cmd_err = %d, dat_err = %d, intsts = 0x%x",
1645 cmd_err, dat_err, intsts);
1646 }
1647
1648 return cqhci_irq(mmc, 0, cmd_err, dat_err);
1649 }
1650
msdc_irq(int irq,void * dev_id)1651 static irqreturn_t msdc_irq(int irq, void *dev_id)
1652 {
1653 struct msdc_host *host = (struct msdc_host *) dev_id;
1654 struct mmc_host *mmc = mmc_from_priv(host);
1655
1656 while (true) {
1657 struct mmc_request *mrq;
1658 struct mmc_command *cmd;
1659 struct mmc_data *data;
1660 u32 events, event_mask;
1661
1662 spin_lock(&host->lock);
1663 events = readl(host->base + MSDC_INT);
1664 event_mask = readl(host->base + MSDC_INTEN);
1665 if ((events & event_mask) & MSDC_INT_SDIOIRQ)
1666 __msdc_enable_sdio_irq(host, 0);
1667 /* clear interrupts */
1668 writel(events & event_mask, host->base + MSDC_INT);
1669
1670 mrq = host->mrq;
1671 cmd = host->cmd;
1672 data = host->data;
1673 spin_unlock(&host->lock);
1674
1675 if ((events & event_mask) & MSDC_INT_SDIOIRQ)
1676 sdio_signal_irq(mmc);
1677
1678 if ((events & event_mask) & MSDC_INT_CDSC) {
1679 if (host->internal_cd)
1680 mmc_detect_change(mmc, msecs_to_jiffies(20));
1681 events &= ~MSDC_INT_CDSC;
1682 }
1683
1684 if (!(events & (event_mask & ~MSDC_INT_SDIOIRQ)))
1685 break;
1686
1687 if ((mmc->caps2 & MMC_CAP2_CQE) &&
1688 (events & MSDC_INT_CMDQ)) {
1689 msdc_cmdq_irq(host, events);
1690 /* clear interrupts */
1691 writel(events, host->base + MSDC_INT);
1692 return IRQ_HANDLED;
1693 }
1694
1695 if (!mrq) {
1696 dev_err(host->dev,
1697 "%s: MRQ=NULL; events=%08X; event_mask=%08X\n",
1698 __func__, events, event_mask);
1699 WARN_ON(1);
1700 break;
1701 }
1702
1703 dev_dbg(host->dev, "%s: events=%08X\n", __func__, events);
1704
1705 if (cmd)
1706 msdc_cmd_done(host, events, mrq, cmd);
1707 else if (data)
1708 msdc_data_xfer_done(host, events, mrq, data);
1709 }
1710
1711 return IRQ_HANDLED;
1712 }
1713
msdc_init_hw(struct msdc_host * host)1714 static void msdc_init_hw(struct msdc_host *host)
1715 {
1716 u32 val;
1717 u32 tune_reg = host->dev_comp->pad_tune_reg;
1718 struct mmc_host *mmc = mmc_from_priv(host);
1719
1720 if (host->reset) {
1721 reset_control_assert(host->reset);
1722 usleep_range(10, 50);
1723 reset_control_deassert(host->reset);
1724 }
1725
1726 /* Configure to MMC/SD mode, clock free running */
1727 sdr_set_bits(host->base + MSDC_CFG, MSDC_CFG_MODE | MSDC_CFG_CKPDN);
1728
1729 /* Reset */
1730 msdc_reset_hw(host);
1731
1732 /* Disable and clear all interrupts */
1733 writel(0, host->base + MSDC_INTEN);
1734 val = readl(host->base + MSDC_INT);
1735 writel(val, host->base + MSDC_INT);
1736
1737 /* Configure card detection */
1738 if (host->internal_cd) {
1739 sdr_set_field(host->base + MSDC_PS, MSDC_PS_CDDEBOUNCE,
1740 DEFAULT_DEBOUNCE);
1741 sdr_set_bits(host->base + MSDC_PS, MSDC_PS_CDEN);
1742 sdr_set_bits(host->base + MSDC_INTEN, MSDC_INTEN_CDSC);
1743 sdr_set_bits(host->base + SDC_CFG, SDC_CFG_INSWKUP);
1744 } else {
1745 sdr_clr_bits(host->base + SDC_CFG, SDC_CFG_INSWKUP);
1746 sdr_clr_bits(host->base + MSDC_PS, MSDC_PS_CDEN);
1747 sdr_clr_bits(host->base + MSDC_INTEN, MSDC_INTEN_CDSC);
1748 }
1749
1750 if (host->top_base) {
1751 writel(0, host->top_base + EMMC_TOP_CONTROL);
1752 writel(0, host->top_base + EMMC_TOP_CMD);
1753 } else {
1754 writel(0, host->base + tune_reg);
1755 }
1756 writel(0, host->base + MSDC_IOCON);
1757 sdr_set_field(host->base + MSDC_IOCON, MSDC_IOCON_DDLSEL, 0);
1758 writel(0x403c0046, host->base + MSDC_PATCH_BIT);
1759 sdr_set_field(host->base + MSDC_PATCH_BIT, MSDC_CKGEN_MSDC_DLY_SEL, 1);
1760 writel(0xffff4089, host->base + MSDC_PATCH_BIT1);
1761 sdr_set_bits(host->base + EMMC50_CFG0, EMMC50_CFG_CFCSTS_SEL);
1762
1763 if (host->dev_comp->stop_clk_fix) {
1764 sdr_set_field(host->base + MSDC_PATCH_BIT1,
1765 MSDC_PATCH_BIT1_STOP_DLY, 3);
1766 sdr_clr_bits(host->base + SDC_FIFO_CFG,
1767 SDC_FIFO_CFG_WRVALIDSEL);
1768 sdr_clr_bits(host->base + SDC_FIFO_CFG,
1769 SDC_FIFO_CFG_RDVALIDSEL);
1770 }
1771
1772 if (host->dev_comp->busy_check)
1773 sdr_clr_bits(host->base + MSDC_PATCH_BIT1, BIT(7));
1774
1775 if (host->dev_comp->async_fifo) {
1776 sdr_set_field(host->base + MSDC_PATCH_BIT2,
1777 MSDC_PB2_RESPWAIT, 3);
1778 if (host->dev_comp->enhance_rx) {
1779 if (host->top_base)
1780 sdr_set_bits(host->top_base + EMMC_TOP_CONTROL,
1781 SDC_RX_ENH_EN);
1782 else
1783 sdr_set_bits(host->base + SDC_ADV_CFG0,
1784 SDC_RX_ENHANCE_EN);
1785 } else {
1786 sdr_set_field(host->base + MSDC_PATCH_BIT2,
1787 MSDC_PB2_RESPSTSENSEL, 2);
1788 sdr_set_field(host->base + MSDC_PATCH_BIT2,
1789 MSDC_PB2_CRCSTSENSEL, 2);
1790 }
1791 /* use async fifo, then no need tune internal delay */
1792 sdr_clr_bits(host->base + MSDC_PATCH_BIT2,
1793 MSDC_PATCH_BIT2_CFGRESP);
1794 sdr_set_bits(host->base + MSDC_PATCH_BIT2,
1795 MSDC_PATCH_BIT2_CFGCRCSTS);
1796 }
1797
1798 if (host->dev_comp->support_64g)
1799 sdr_set_bits(host->base + MSDC_PATCH_BIT2,
1800 MSDC_PB2_SUPPORT_64G);
1801 if (host->dev_comp->data_tune) {
1802 if (host->top_base) {
1803 sdr_set_bits(host->top_base + EMMC_TOP_CONTROL,
1804 PAD_DAT_RD_RXDLY_SEL);
1805 sdr_clr_bits(host->top_base + EMMC_TOP_CONTROL,
1806 DATA_K_VALUE_SEL);
1807 sdr_set_bits(host->top_base + EMMC_TOP_CMD,
1808 PAD_CMD_RD_RXDLY_SEL);
1809 if (host->tuning_step > PAD_DELAY_HALF) {
1810 sdr_set_bits(host->top_base + EMMC_TOP_CONTROL,
1811 PAD_DAT_RD_RXDLY2_SEL);
1812 sdr_set_bits(host->top_base + EMMC_TOP_CMD,
1813 PAD_CMD_RD_RXDLY2_SEL);
1814 }
1815 } else {
1816 sdr_set_bits(host->base + tune_reg,
1817 MSDC_PAD_TUNE_RD_SEL |
1818 MSDC_PAD_TUNE_CMD_SEL);
1819 if (host->tuning_step > PAD_DELAY_HALF)
1820 sdr_set_bits(host->base + tune_reg + TUNING_REG2_FIXED_OFFEST,
1821 MSDC_PAD_TUNE_RD2_SEL |
1822 MSDC_PAD_TUNE_CMD2_SEL);
1823 }
1824 } else {
1825 /* choose clock tune */
1826 if (host->top_base)
1827 sdr_set_bits(host->top_base + EMMC_TOP_CONTROL,
1828 PAD_RXDLY_SEL);
1829 else
1830 sdr_set_bits(host->base + tune_reg,
1831 MSDC_PAD_TUNE_RXDLYSEL);
1832 }
1833
1834 if (mmc->caps2 & MMC_CAP2_NO_SDIO) {
1835 sdr_clr_bits(host->base + SDC_CFG, SDC_CFG_SDIO);
1836 sdr_clr_bits(host->base + MSDC_INTEN, MSDC_INTEN_SDIOIRQ);
1837 sdr_clr_bits(host->base + SDC_ADV_CFG0, SDC_DAT1_IRQ_TRIGGER);
1838 } else {
1839 /* Configure to enable SDIO mode, otherwise SDIO CMD5 fails */
1840 sdr_set_bits(host->base + SDC_CFG, SDC_CFG_SDIO);
1841
1842 /* Config SDIO device detect interrupt function */
1843 sdr_clr_bits(host->base + SDC_CFG, SDC_CFG_SDIOIDE);
1844 sdr_set_bits(host->base + SDC_ADV_CFG0, SDC_DAT1_IRQ_TRIGGER);
1845 }
1846
1847 /* Configure to default data timeout */
1848 sdr_set_field(host->base + SDC_CFG, SDC_CFG_DTOC, 3);
1849
1850 host->def_tune_para.iocon = readl(host->base + MSDC_IOCON);
1851 host->saved_tune_para.iocon = readl(host->base + MSDC_IOCON);
1852 if (host->top_base) {
1853 host->def_tune_para.emmc_top_control =
1854 readl(host->top_base + EMMC_TOP_CONTROL);
1855 host->def_tune_para.emmc_top_cmd =
1856 readl(host->top_base + EMMC_TOP_CMD);
1857 host->saved_tune_para.emmc_top_control =
1858 readl(host->top_base + EMMC_TOP_CONTROL);
1859 host->saved_tune_para.emmc_top_cmd =
1860 readl(host->top_base + EMMC_TOP_CMD);
1861 } else {
1862 host->def_tune_para.pad_tune = readl(host->base + tune_reg);
1863 host->saved_tune_para.pad_tune = readl(host->base + tune_reg);
1864 }
1865 dev_dbg(host->dev, "init hardware done!");
1866 }
1867
msdc_deinit_hw(struct msdc_host * host)1868 static void msdc_deinit_hw(struct msdc_host *host)
1869 {
1870 u32 val;
1871
1872 if (host->internal_cd) {
1873 /* Disabled card-detect */
1874 sdr_clr_bits(host->base + MSDC_PS, MSDC_PS_CDEN);
1875 sdr_clr_bits(host->base + SDC_CFG, SDC_CFG_INSWKUP);
1876 }
1877
1878 /* Disable and clear all interrupts */
1879 writel(0, host->base + MSDC_INTEN);
1880
1881 val = readl(host->base + MSDC_INT);
1882 writel(val, host->base + MSDC_INT);
1883 }
1884
1885 /* init gpd and bd list in msdc_drv_probe */
msdc_init_gpd_bd(struct msdc_host * host,struct msdc_dma * dma)1886 static void msdc_init_gpd_bd(struct msdc_host *host, struct msdc_dma *dma)
1887 {
1888 struct mt_gpdma_desc *gpd = dma->gpd;
1889 struct mt_bdma_desc *bd = dma->bd;
1890 dma_addr_t dma_addr;
1891 int i;
1892
1893 memset(gpd, 0, sizeof(struct mt_gpdma_desc) * 2);
1894
1895 dma_addr = dma->gpd_addr + sizeof(struct mt_gpdma_desc);
1896 gpd->gpd_info = GPDMA_DESC_BDP; /* hwo, cs, bd pointer */
1897 /* gpd->next is must set for desc DMA
1898 * That's why must alloc 2 gpd structure.
1899 */
1900 gpd->next = lower_32_bits(dma_addr);
1901 if (host->dev_comp->support_64g)
1902 gpd->gpd_info |= (upper_32_bits(dma_addr) & 0xf) << 24;
1903
1904 dma_addr = dma->bd_addr;
1905 gpd->ptr = lower_32_bits(dma->bd_addr); /* physical address */
1906 if (host->dev_comp->support_64g)
1907 gpd->gpd_info |= (upper_32_bits(dma_addr) & 0xf) << 28;
1908
1909 memset(bd, 0, sizeof(struct mt_bdma_desc) * MAX_BD_NUM);
1910 for (i = 0; i < (MAX_BD_NUM - 1); i++) {
1911 dma_addr = dma->bd_addr + sizeof(*bd) * (i + 1);
1912 bd[i].next = lower_32_bits(dma_addr);
1913 if (host->dev_comp->support_64g)
1914 bd[i].bd_info |= (upper_32_bits(dma_addr) & 0xf) << 24;
1915 }
1916 }
1917
msdc_ops_set_ios(struct mmc_host * mmc,struct mmc_ios * ios)1918 static void msdc_ops_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1919 {
1920 struct msdc_host *host = mmc_priv(mmc);
1921 int ret;
1922
1923 msdc_set_buswidth(host, ios->bus_width);
1924
1925 /* Suspend/Resume will do power off/on */
1926 switch (ios->power_mode) {
1927 case MMC_POWER_UP:
1928 if (!IS_ERR(mmc->supply.vmmc)) {
1929 msdc_init_hw(host);
1930 ret = mmc_regulator_set_ocr(mmc, mmc->supply.vmmc,
1931 ios->vdd);
1932 if (ret) {
1933 dev_err(host->dev, "Failed to set vmmc power!\n");
1934 return;
1935 }
1936 }
1937 break;
1938 case MMC_POWER_ON:
1939 if (!IS_ERR(mmc->supply.vqmmc) && !host->vqmmc_enabled) {
1940 ret = regulator_enable(mmc->supply.vqmmc);
1941 if (ret)
1942 dev_err(host->dev, "Failed to set vqmmc power!\n");
1943 else
1944 host->vqmmc_enabled = true;
1945 }
1946 break;
1947 case MMC_POWER_OFF:
1948 if (!IS_ERR(mmc->supply.vmmc))
1949 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
1950
1951 if (!IS_ERR(mmc->supply.vqmmc) && host->vqmmc_enabled) {
1952 regulator_disable(mmc->supply.vqmmc);
1953 host->vqmmc_enabled = false;
1954 }
1955 break;
1956 default:
1957 break;
1958 }
1959
1960 if (host->mclk != ios->clock || host->timing != ios->timing)
1961 msdc_set_mclk(host, ios->timing, ios->clock);
1962 }
1963
test_delay_bit(u64 delay,u32 bit)1964 static u64 test_delay_bit(u64 delay, u32 bit)
1965 {
1966 bit %= PAD_DELAY_FULL;
1967 return delay & BIT_ULL(bit);
1968 }
1969
get_delay_len(u64 delay,u32 start_bit)1970 static int get_delay_len(u64 delay, u32 start_bit)
1971 {
1972 int i;
1973
1974 for (i = 0; i < (PAD_DELAY_FULL - start_bit); i++) {
1975 if (test_delay_bit(delay, start_bit + i) == 0)
1976 return i;
1977 }
1978 return PAD_DELAY_FULL - start_bit;
1979 }
1980
get_best_delay(struct msdc_host * host,u64 delay)1981 static struct msdc_delay_phase get_best_delay(struct msdc_host *host, u64 delay)
1982 {
1983 int start = 0, len = 0;
1984 int start_final = 0, len_final = 0;
1985 u8 final_phase = 0xff;
1986 struct msdc_delay_phase delay_phase = { 0, };
1987
1988 if (delay == 0) {
1989 dev_err(host->dev, "phase error: [map:%016llx]\n", delay);
1990 delay_phase.final_phase = final_phase;
1991 return delay_phase;
1992 }
1993
1994 while (start < PAD_DELAY_FULL) {
1995 len = get_delay_len(delay, start);
1996 if (len_final < len) {
1997 start_final = start;
1998 len_final = len;
1999 }
2000 start += len ? len : 1;
2001 if (!upper_32_bits(delay) && len >= 12 && start_final < 4)
2002 break;
2003 }
2004
2005 /* The rule is that to find the smallest delay cell */
2006 if (start_final == 0)
2007 final_phase = (start_final + len_final / 3) % PAD_DELAY_FULL;
2008 else
2009 final_phase = (start_final + len_final / 2) % PAD_DELAY_FULL;
2010 dev_dbg(host->dev, "phase: [map:%016llx] [maxlen:%d] [final:%d]\n",
2011 delay, len_final, final_phase);
2012
2013 delay_phase.maxlen = len_final;
2014 delay_phase.start = start_final;
2015 delay_phase.final_phase = final_phase;
2016 return delay_phase;
2017 }
2018
msdc_set_cmd_delay(struct msdc_host * host,u32 value)2019 static inline void msdc_set_cmd_delay(struct msdc_host *host, u32 value)
2020 {
2021 u32 tune_reg = host->dev_comp->pad_tune_reg;
2022
2023 if (host->top_base) {
2024 if (value < PAD_DELAY_HALF) {
2025 sdr_set_field(host->top_base + EMMC_TOP_CMD, PAD_CMD_RXDLY, value);
2026 sdr_set_field(host->top_base + EMMC_TOP_CMD, PAD_CMD_RXDLY2, 0);
2027 } else {
2028 sdr_set_field(host->top_base + EMMC_TOP_CMD, PAD_CMD_RXDLY,
2029 PAD_DELAY_HALF - 1);
2030 sdr_set_field(host->top_base + EMMC_TOP_CMD, PAD_CMD_RXDLY2,
2031 value - PAD_DELAY_HALF);
2032 }
2033 } else {
2034 if (value < PAD_DELAY_HALF) {
2035 sdr_set_field(host->base + tune_reg, MSDC_PAD_TUNE_CMDRDLY, value);
2036 sdr_set_field(host->base + tune_reg + TUNING_REG2_FIXED_OFFEST,
2037 MSDC_PAD_TUNE_CMDRDLY2, 0);
2038 } else {
2039 sdr_set_field(host->base + tune_reg, MSDC_PAD_TUNE_CMDRDLY,
2040 PAD_DELAY_HALF - 1);
2041 sdr_set_field(host->base + tune_reg + TUNING_REG2_FIXED_OFFEST,
2042 MSDC_PAD_TUNE_CMDRDLY2, value - PAD_DELAY_HALF);
2043 }
2044 }
2045 }
2046
msdc_set_data_delay(struct msdc_host * host,u32 value)2047 static inline void msdc_set_data_delay(struct msdc_host *host, u32 value)
2048 {
2049 u32 tune_reg = host->dev_comp->pad_tune_reg;
2050
2051 if (host->top_base) {
2052 if (value < PAD_DELAY_HALF) {
2053 sdr_set_field(host->top_base + EMMC_TOP_CONTROL,
2054 PAD_DAT_RD_RXDLY, value);
2055 sdr_set_field(host->top_base + EMMC_TOP_CONTROL,
2056 PAD_DAT_RD_RXDLY2, 0);
2057 } else {
2058 sdr_set_field(host->top_base + EMMC_TOP_CONTROL,
2059 PAD_DAT_RD_RXDLY, PAD_DELAY_HALF - 1);
2060 sdr_set_field(host->top_base + EMMC_TOP_CONTROL,
2061 PAD_DAT_RD_RXDLY2, value - PAD_DELAY_HALF);
2062 }
2063 } else {
2064 if (value < PAD_DELAY_HALF) {
2065 sdr_set_field(host->base + tune_reg, MSDC_PAD_TUNE_DATRRDLY, value);
2066 sdr_set_field(host->base + tune_reg + TUNING_REG2_FIXED_OFFEST,
2067 MSDC_PAD_TUNE_DATRRDLY2, 0);
2068 } else {
2069 sdr_set_field(host->base + tune_reg, MSDC_PAD_TUNE_DATRRDLY,
2070 PAD_DELAY_HALF - 1);
2071 sdr_set_field(host->base + tune_reg + TUNING_REG2_FIXED_OFFEST,
2072 MSDC_PAD_TUNE_DATRRDLY2, value - PAD_DELAY_HALF);
2073 }
2074 }
2075 }
2076
msdc_tune_response(struct mmc_host * mmc,u32 opcode)2077 static int msdc_tune_response(struct mmc_host *mmc, u32 opcode)
2078 {
2079 struct msdc_host *host = mmc_priv(mmc);
2080 u64 rise_delay = 0, fall_delay = 0;
2081 struct msdc_delay_phase final_rise_delay, final_fall_delay = { 0,};
2082 struct msdc_delay_phase internal_delay_phase;
2083 u8 final_delay, final_maxlen;
2084 u32 internal_delay = 0;
2085 u32 tune_reg = host->dev_comp->pad_tune_reg;
2086 int cmd_err;
2087 int i, j;
2088
2089 if (mmc->ios.timing == MMC_TIMING_MMC_HS200 ||
2090 mmc->ios.timing == MMC_TIMING_UHS_SDR104)
2091 sdr_set_field(host->base + tune_reg,
2092 MSDC_PAD_TUNE_CMDRRDLY,
2093 host->hs200_cmd_int_delay);
2094
2095 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
2096 for (i = 0; i < host->tuning_step; i++) {
2097 msdc_set_cmd_delay(host, i);
2098 /*
2099 * Using the same parameters, it may sometimes pass the test,
2100 * but sometimes it may fail. To make sure the parameters are
2101 * more stable, we test each set of parameters 3 times.
2102 */
2103 for (j = 0; j < 3; j++) {
2104 mmc_send_tuning(mmc, opcode, &cmd_err);
2105 if (!cmd_err) {
2106 rise_delay |= BIT_ULL(i);
2107 } else {
2108 rise_delay &= ~BIT_ULL(i);
2109 break;
2110 }
2111 }
2112 }
2113 final_rise_delay = get_best_delay(host, rise_delay);
2114 /* if rising edge has enough margin, then do not scan falling edge */
2115 if (final_rise_delay.maxlen >= 12 ||
2116 (final_rise_delay.start == 0 && final_rise_delay.maxlen >= 4))
2117 goto skip_fall;
2118
2119 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
2120 for (i = 0; i < host->tuning_step; i++) {
2121 msdc_set_cmd_delay(host, i);
2122 /*
2123 * Using the same parameters, it may sometimes pass the test,
2124 * but sometimes it may fail. To make sure the parameters are
2125 * more stable, we test each set of parameters 3 times.
2126 */
2127 for (j = 0; j < 3; j++) {
2128 mmc_send_tuning(mmc, opcode, &cmd_err);
2129 if (!cmd_err) {
2130 fall_delay |= BIT_ULL(i);
2131 } else {
2132 fall_delay &= ~BIT_ULL(i);
2133 break;
2134 }
2135 }
2136 }
2137 final_fall_delay = get_best_delay(host, fall_delay);
2138
2139 skip_fall:
2140 final_maxlen = max(final_rise_delay.maxlen, final_fall_delay.maxlen);
2141 if (final_fall_delay.maxlen >= 12 && final_fall_delay.start < 4)
2142 final_maxlen = final_fall_delay.maxlen;
2143 if (final_maxlen == final_rise_delay.maxlen) {
2144 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
2145 final_delay = final_rise_delay.final_phase;
2146 } else {
2147 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
2148 final_delay = final_fall_delay.final_phase;
2149 }
2150 msdc_set_cmd_delay(host, final_delay);
2151
2152 if (host->dev_comp->async_fifo || host->hs200_cmd_int_delay)
2153 goto skip_internal;
2154
2155 for (i = 0; i < host->tuning_step; i++) {
2156 sdr_set_field(host->base + tune_reg,
2157 MSDC_PAD_TUNE_CMDRRDLY, i);
2158 mmc_send_tuning(mmc, opcode, &cmd_err);
2159 if (!cmd_err)
2160 internal_delay |= BIT_ULL(i);
2161 }
2162 dev_dbg(host->dev, "Final internal delay: 0x%x\n", internal_delay);
2163 internal_delay_phase = get_best_delay(host, internal_delay);
2164 sdr_set_field(host->base + tune_reg, MSDC_PAD_TUNE_CMDRRDLY,
2165 internal_delay_phase.final_phase);
2166 skip_internal:
2167 dev_dbg(host->dev, "Final cmd pad delay: %x\n", final_delay);
2168 return final_delay == 0xff ? -EIO : 0;
2169 }
2170
hs400_tune_response(struct mmc_host * mmc,u32 opcode)2171 static int hs400_tune_response(struct mmc_host *mmc, u32 opcode)
2172 {
2173 struct msdc_host *host = mmc_priv(mmc);
2174 u32 cmd_delay = 0;
2175 struct msdc_delay_phase final_cmd_delay = { 0,};
2176 u8 final_delay;
2177 int cmd_err;
2178 int i, j;
2179
2180 /* select EMMC50 PAD CMD tune */
2181 sdr_set_bits(host->base + PAD_CMD_TUNE, BIT(0));
2182 sdr_set_field(host->base + MSDC_PATCH_BIT1, MSDC_PATCH_BIT1_CMDTA, 2);
2183
2184 if (mmc->ios.timing == MMC_TIMING_MMC_HS200 ||
2185 mmc->ios.timing == MMC_TIMING_UHS_SDR104)
2186 sdr_set_field(host->base + MSDC_PAD_TUNE,
2187 MSDC_PAD_TUNE_CMDRRDLY,
2188 host->hs200_cmd_int_delay);
2189
2190 if (host->hs400_cmd_resp_sel_rising)
2191 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
2192 else
2193 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
2194
2195 for (i = 0; i < PAD_DELAY_HALF; i++) {
2196 sdr_set_field(host->base + PAD_CMD_TUNE,
2197 PAD_CMD_TUNE_RX_DLY3, i);
2198 /*
2199 * Using the same parameters, it may sometimes pass the test,
2200 * but sometimes it may fail. To make sure the parameters are
2201 * more stable, we test each set of parameters 3 times.
2202 */
2203 for (j = 0; j < 3; j++) {
2204 mmc_send_tuning(mmc, opcode, &cmd_err);
2205 if (!cmd_err) {
2206 cmd_delay |= BIT(i);
2207 } else {
2208 cmd_delay &= ~BIT(i);
2209 break;
2210 }
2211 }
2212 }
2213 final_cmd_delay = get_best_delay(host, cmd_delay);
2214 sdr_set_field(host->base + PAD_CMD_TUNE, PAD_CMD_TUNE_RX_DLY3,
2215 final_cmd_delay.final_phase);
2216 final_delay = final_cmd_delay.final_phase;
2217
2218 dev_dbg(host->dev, "Final cmd pad delay: %x\n", final_delay);
2219 return final_delay == 0xff ? -EIO : 0;
2220 }
2221
msdc_tune_data(struct mmc_host * mmc,u32 opcode)2222 static int msdc_tune_data(struct mmc_host *mmc, u32 opcode)
2223 {
2224 struct msdc_host *host = mmc_priv(mmc);
2225 u64 rise_delay = 0, fall_delay = 0;
2226 struct msdc_delay_phase final_rise_delay, final_fall_delay = { 0,};
2227 u8 final_delay, final_maxlen;
2228 int i, ret;
2229
2230 sdr_set_field(host->base + MSDC_PATCH_BIT, MSDC_INT_DAT_LATCH_CK_SEL,
2231 host->latch_ck);
2232 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL);
2233 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL);
2234 for (i = 0; i < host->tuning_step; i++) {
2235 msdc_set_data_delay(host, i);
2236 ret = mmc_send_tuning(mmc, opcode, NULL);
2237 if (!ret)
2238 rise_delay |= BIT_ULL(i);
2239 }
2240 final_rise_delay = get_best_delay(host, rise_delay);
2241 /* if rising edge has enough margin, then do not scan falling edge */
2242 if (final_rise_delay.maxlen >= 12 ||
2243 (final_rise_delay.start == 0 && final_rise_delay.maxlen >= 4))
2244 goto skip_fall;
2245
2246 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL);
2247 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL);
2248 for (i = 0; i < host->tuning_step; i++) {
2249 msdc_set_data_delay(host, i);
2250 ret = mmc_send_tuning(mmc, opcode, NULL);
2251 if (!ret)
2252 fall_delay |= BIT_ULL(i);
2253 }
2254 final_fall_delay = get_best_delay(host, fall_delay);
2255
2256 skip_fall:
2257 final_maxlen = max(final_rise_delay.maxlen, final_fall_delay.maxlen);
2258 if (final_maxlen == final_rise_delay.maxlen) {
2259 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL);
2260 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL);
2261 final_delay = final_rise_delay.final_phase;
2262 } else {
2263 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL);
2264 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL);
2265 final_delay = final_fall_delay.final_phase;
2266 }
2267 msdc_set_data_delay(host, final_delay);
2268
2269 dev_dbg(host->dev, "Final data pad delay: %x\n", final_delay);
2270 return final_delay == 0xff ? -EIO : 0;
2271 }
2272
2273 /*
2274 * MSDC IP which supports data tune + async fifo can do CMD/DAT tune
2275 * together, which can save the tuning time.
2276 */
msdc_tune_together(struct mmc_host * mmc,u32 opcode)2277 static int msdc_tune_together(struct mmc_host *mmc, u32 opcode)
2278 {
2279 struct msdc_host *host = mmc_priv(mmc);
2280 u64 rise_delay = 0, fall_delay = 0;
2281 struct msdc_delay_phase final_rise_delay, final_fall_delay = { 0,};
2282 u8 final_delay, final_maxlen;
2283 int i, ret;
2284
2285 sdr_set_field(host->base + MSDC_PATCH_BIT, MSDC_INT_DAT_LATCH_CK_SEL,
2286 host->latch_ck);
2287
2288 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
2289 sdr_clr_bits(host->base + MSDC_IOCON,
2290 MSDC_IOCON_DSPL | MSDC_IOCON_W_DSPL);
2291 for (i = 0; i < host->tuning_step; i++) {
2292 msdc_set_cmd_delay(host, i);
2293 msdc_set_data_delay(host, i);
2294 ret = mmc_send_tuning(mmc, opcode, NULL);
2295 if (!ret)
2296 rise_delay |= BIT_ULL(i);
2297 }
2298 final_rise_delay = get_best_delay(host, rise_delay);
2299 /* if rising edge has enough margin, then do not scan falling edge */
2300 if (final_rise_delay.maxlen >= 12 ||
2301 (final_rise_delay.start == 0 && final_rise_delay.maxlen >= 4))
2302 goto skip_fall;
2303
2304 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
2305 sdr_set_bits(host->base + MSDC_IOCON,
2306 MSDC_IOCON_DSPL | MSDC_IOCON_W_DSPL);
2307 for (i = 0; i < host->tuning_step; i++) {
2308 msdc_set_cmd_delay(host, i);
2309 msdc_set_data_delay(host, i);
2310 ret = mmc_send_tuning(mmc, opcode, NULL);
2311 if (!ret)
2312 fall_delay |= BIT_ULL(i);
2313 }
2314 final_fall_delay = get_best_delay(host, fall_delay);
2315
2316 skip_fall:
2317 final_maxlen = max(final_rise_delay.maxlen, final_fall_delay.maxlen);
2318 if (final_maxlen == final_rise_delay.maxlen) {
2319 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
2320 sdr_clr_bits(host->base + MSDC_IOCON,
2321 MSDC_IOCON_DSPL | MSDC_IOCON_W_DSPL);
2322 final_delay = final_rise_delay.final_phase;
2323 } else {
2324 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
2325 sdr_set_bits(host->base + MSDC_IOCON,
2326 MSDC_IOCON_DSPL | MSDC_IOCON_W_DSPL);
2327 final_delay = final_fall_delay.final_phase;
2328 }
2329
2330 msdc_set_cmd_delay(host, final_delay);
2331 msdc_set_data_delay(host, final_delay);
2332
2333 dev_dbg(host->dev, "Final pad delay: %x\n", final_delay);
2334 return final_delay == 0xff ? -EIO : 0;
2335 }
2336
msdc_execute_tuning(struct mmc_host * mmc,u32 opcode)2337 static int msdc_execute_tuning(struct mmc_host *mmc, u32 opcode)
2338 {
2339 struct msdc_host *host = mmc_priv(mmc);
2340 int ret;
2341 u32 tune_reg = host->dev_comp->pad_tune_reg;
2342
2343 if (host->dev_comp->data_tune && host->dev_comp->async_fifo) {
2344 ret = msdc_tune_together(mmc, opcode);
2345 if (host->hs400_mode) {
2346 sdr_clr_bits(host->base + MSDC_IOCON,
2347 MSDC_IOCON_DSPL | MSDC_IOCON_W_DSPL);
2348 msdc_set_data_delay(host, 0);
2349 }
2350 goto tune_done;
2351 }
2352 if (host->hs400_mode &&
2353 host->dev_comp->hs400_tune)
2354 ret = hs400_tune_response(mmc, opcode);
2355 else
2356 ret = msdc_tune_response(mmc, opcode);
2357 if (ret == -EIO) {
2358 dev_err(host->dev, "Tune response fail!\n");
2359 return ret;
2360 }
2361 if (host->hs400_mode == false) {
2362 ret = msdc_tune_data(mmc, opcode);
2363 if (ret == -EIO)
2364 dev_err(host->dev, "Tune data fail!\n");
2365 }
2366
2367 tune_done:
2368 host->saved_tune_para.iocon = readl(host->base + MSDC_IOCON);
2369 host->saved_tune_para.pad_tune = readl(host->base + tune_reg);
2370 host->saved_tune_para.pad_cmd_tune = readl(host->base + PAD_CMD_TUNE);
2371 if (host->top_base) {
2372 host->saved_tune_para.emmc_top_control = readl(host->top_base +
2373 EMMC_TOP_CONTROL);
2374 host->saved_tune_para.emmc_top_cmd = readl(host->top_base +
2375 EMMC_TOP_CMD);
2376 }
2377 return ret;
2378 }
2379
msdc_prepare_hs400_tuning(struct mmc_host * mmc,struct mmc_ios * ios)2380 static int msdc_prepare_hs400_tuning(struct mmc_host *mmc, struct mmc_ios *ios)
2381 {
2382 struct msdc_host *host = mmc_priv(mmc);
2383
2384 host->hs400_mode = true;
2385
2386 if (host->top_base) {
2387 if (host->hs400_ds_dly3)
2388 sdr_set_field(host->top_base + EMMC50_PAD_DS_TUNE,
2389 PAD_DS_DLY3, host->hs400_ds_dly3);
2390 if (host->hs400_ds_delay)
2391 writel(host->hs400_ds_delay,
2392 host->top_base + EMMC50_PAD_DS_TUNE);
2393 } else {
2394 if (host->hs400_ds_dly3)
2395 sdr_set_field(host->base + PAD_DS_TUNE,
2396 PAD_DS_TUNE_DLY3, host->hs400_ds_dly3);
2397 if (host->hs400_ds_delay)
2398 writel(host->hs400_ds_delay, host->base + PAD_DS_TUNE);
2399 }
2400 /* hs400 mode must set it to 0 */
2401 sdr_clr_bits(host->base + MSDC_PATCH_BIT2, MSDC_PATCH_BIT2_CFGCRCSTS);
2402 /* to improve read performance, set outstanding to 2 */
2403 sdr_set_field(host->base + EMMC50_CFG3, EMMC50_CFG3_OUTS_WR, 2);
2404
2405 return 0;
2406 }
2407
msdc_execute_hs400_tuning(struct mmc_host * mmc,struct mmc_card * card)2408 static int msdc_execute_hs400_tuning(struct mmc_host *mmc, struct mmc_card *card)
2409 {
2410 struct msdc_host *host = mmc_priv(mmc);
2411 struct msdc_delay_phase dly1_delay;
2412 u32 val, result_dly1 = 0;
2413 u8 *ext_csd;
2414 int i, ret;
2415
2416 if (host->top_base) {
2417 sdr_set_bits(host->top_base + EMMC50_PAD_DS_TUNE,
2418 PAD_DS_DLY_SEL);
2419 sdr_clr_bits(host->top_base + EMMC50_PAD_DS_TUNE,
2420 PAD_DS_DLY2_SEL);
2421 } else {
2422 sdr_set_bits(host->base + PAD_DS_TUNE, PAD_DS_TUNE_DLY_SEL);
2423 sdr_clr_bits(host->base + PAD_DS_TUNE, PAD_DS_TUNE_DLY2_SEL);
2424 }
2425
2426 host->hs400_tuning = true;
2427 for (i = 0; i < PAD_DELAY_HALF; i++) {
2428 if (host->top_base)
2429 sdr_set_field(host->top_base + EMMC50_PAD_DS_TUNE,
2430 PAD_DS_DLY1, i);
2431 else
2432 sdr_set_field(host->base + PAD_DS_TUNE,
2433 PAD_DS_TUNE_DLY1, i);
2434 ret = mmc_get_ext_csd(card, &ext_csd);
2435 if (!ret) {
2436 result_dly1 |= BIT(i);
2437 kfree(ext_csd);
2438 }
2439 }
2440 host->hs400_tuning = false;
2441
2442 dly1_delay = get_best_delay(host, result_dly1);
2443 if (dly1_delay.maxlen == 0) {
2444 dev_err(host->dev, "Failed to get DLY1 delay!\n");
2445 goto fail;
2446 }
2447 if (host->top_base)
2448 sdr_set_field(host->top_base + EMMC50_PAD_DS_TUNE,
2449 PAD_DS_DLY1, dly1_delay.final_phase);
2450 else
2451 sdr_set_field(host->base + PAD_DS_TUNE,
2452 PAD_DS_TUNE_DLY1, dly1_delay.final_phase);
2453
2454 if (host->top_base)
2455 val = readl(host->top_base + EMMC50_PAD_DS_TUNE);
2456 else
2457 val = readl(host->base + PAD_DS_TUNE);
2458
2459 dev_info(host->dev, "Final PAD_DS_TUNE: 0x%x\n", val);
2460
2461 return 0;
2462
2463 fail:
2464 dev_err(host->dev, "Failed to tuning DS pin delay!\n");
2465 return -EIO;
2466 }
2467
msdc_hw_reset(struct mmc_host * mmc)2468 static void msdc_hw_reset(struct mmc_host *mmc)
2469 {
2470 struct msdc_host *host = mmc_priv(mmc);
2471
2472 sdr_set_bits(host->base + EMMC_IOCON, 1);
2473 udelay(10); /* 10us is enough */
2474 sdr_clr_bits(host->base + EMMC_IOCON, 1);
2475 }
2476
msdc_ack_sdio_irq(struct mmc_host * mmc)2477 static void msdc_ack_sdio_irq(struct mmc_host *mmc)
2478 {
2479 unsigned long flags;
2480 struct msdc_host *host = mmc_priv(mmc);
2481
2482 spin_lock_irqsave(&host->lock, flags);
2483 __msdc_enable_sdio_irq(host, 1);
2484 spin_unlock_irqrestore(&host->lock, flags);
2485 }
2486
msdc_get_cd(struct mmc_host * mmc)2487 static int msdc_get_cd(struct mmc_host *mmc)
2488 {
2489 struct msdc_host *host = mmc_priv(mmc);
2490 int val;
2491
2492 if (mmc->caps & MMC_CAP_NONREMOVABLE)
2493 return 1;
2494
2495 if (!host->internal_cd)
2496 return mmc_gpio_get_cd(mmc);
2497
2498 val = readl(host->base + MSDC_PS) & MSDC_PS_CDSTS;
2499 if (mmc->caps2 & MMC_CAP2_CD_ACTIVE_HIGH)
2500 return !!val;
2501 else
2502 return !val;
2503 }
2504
msdc_hs400_enhanced_strobe(struct mmc_host * mmc,struct mmc_ios * ios)2505 static void msdc_hs400_enhanced_strobe(struct mmc_host *mmc,
2506 struct mmc_ios *ios)
2507 {
2508 struct msdc_host *host = mmc_priv(mmc);
2509
2510 if (ios->enhanced_strobe) {
2511 msdc_prepare_hs400_tuning(mmc, ios);
2512 sdr_set_field(host->base + EMMC50_CFG0, EMMC50_CFG_PADCMD_LATCHCK, 1);
2513 sdr_set_field(host->base + EMMC50_CFG0, EMMC50_CFG_CMD_RESP_SEL, 1);
2514 sdr_set_field(host->base + EMMC50_CFG1, EMMC50_CFG1_DS_CFG, 1);
2515
2516 sdr_clr_bits(host->base + CQHCI_SETTING, CQHCI_RD_CMD_WND_SEL);
2517 sdr_clr_bits(host->base + CQHCI_SETTING, CQHCI_WR_CMD_WND_SEL);
2518 sdr_clr_bits(host->base + EMMC51_CFG0, CMDQ_RDAT_CNT);
2519 } else {
2520 sdr_set_field(host->base + EMMC50_CFG0, EMMC50_CFG_PADCMD_LATCHCK, 0);
2521 sdr_set_field(host->base + EMMC50_CFG0, EMMC50_CFG_CMD_RESP_SEL, 0);
2522 sdr_set_field(host->base + EMMC50_CFG1, EMMC50_CFG1_DS_CFG, 0);
2523
2524 sdr_set_bits(host->base + CQHCI_SETTING, CQHCI_RD_CMD_WND_SEL);
2525 sdr_set_bits(host->base + CQHCI_SETTING, CQHCI_WR_CMD_WND_SEL);
2526 sdr_set_field(host->base + EMMC51_CFG0, CMDQ_RDAT_CNT, 0xb4);
2527 }
2528 }
2529
msdc_cqe_cit_cal(struct msdc_host * host,u64 timer_ns)2530 static void msdc_cqe_cit_cal(struct msdc_host *host, u64 timer_ns)
2531 {
2532 struct mmc_host *mmc = mmc_from_priv(host);
2533 struct cqhci_host *cq_host = mmc->cqe_private;
2534 u8 itcfmul;
2535 u64 hclk_freq, value;
2536
2537 /*
2538 * On MediaTek SoCs the MSDC controller's CQE uses msdc_hclk as ITCFVAL
2539 * so we multiply/divide the HCLK frequency by ITCFMUL to calculate the
2540 * Send Status Command Idle Timer (CIT) value.
2541 */
2542 hclk_freq = (u64)clk_get_rate(host->h_clk);
2543 itcfmul = CQHCI_ITCFMUL(cqhci_readl(cq_host, CQHCI_CAP));
2544 switch (itcfmul) {
2545 case 0x0:
2546 do_div(hclk_freq, 1000);
2547 break;
2548 case 0x1:
2549 do_div(hclk_freq, 100);
2550 break;
2551 case 0x2:
2552 do_div(hclk_freq, 10);
2553 break;
2554 case 0x3:
2555 break;
2556 case 0x4:
2557 hclk_freq = hclk_freq * 10;
2558 break;
2559 default:
2560 host->cq_ssc1_time = 0x40;
2561 return;
2562 }
2563
2564 value = hclk_freq * timer_ns;
2565 do_div(value, 1000000000);
2566 host->cq_ssc1_time = value;
2567 }
2568
msdc_cqe_enable(struct mmc_host * mmc)2569 static void msdc_cqe_enable(struct mmc_host *mmc)
2570 {
2571 struct msdc_host *host = mmc_priv(mmc);
2572 struct cqhci_host *cq_host = mmc->cqe_private;
2573
2574 /* enable cmdq irq */
2575 writel(MSDC_INT_CMDQ, host->base + MSDC_INTEN);
2576 /* enable busy check */
2577 sdr_set_bits(host->base + MSDC_PATCH_BIT1, MSDC_PB1_BUSY_CHECK_SEL);
2578 /* default write data / busy timeout 20s */
2579 msdc_set_busy_timeout(host, 20 * 1000000000ULL, 0);
2580 /* default read data timeout 1s */
2581 msdc_set_timeout(host, 1000000000ULL, 0);
2582
2583 /* Set the send status command idle timer */
2584 cqhci_writel(cq_host, host->cq_ssc1_time, CQHCI_SSC1);
2585 }
2586
msdc_cqe_disable(struct mmc_host * mmc,bool recovery)2587 static void msdc_cqe_disable(struct mmc_host *mmc, bool recovery)
2588 {
2589 struct msdc_host *host = mmc_priv(mmc);
2590 unsigned int val = 0;
2591
2592 /* disable cmdq irq */
2593 sdr_clr_bits(host->base + MSDC_INTEN, MSDC_INT_CMDQ);
2594 /* disable busy check */
2595 sdr_clr_bits(host->base + MSDC_PATCH_BIT1, MSDC_PB1_BUSY_CHECK_SEL);
2596
2597 val = readl(host->base + MSDC_INT);
2598 writel(val, host->base + MSDC_INT);
2599
2600 if (recovery) {
2601 sdr_set_field(host->base + MSDC_DMA_CTRL,
2602 MSDC_DMA_CTRL_STOP, 1);
2603 if (WARN_ON(readl_poll_timeout(host->base + MSDC_DMA_CTRL, val,
2604 !(val & MSDC_DMA_CTRL_STOP), 1, 3000)))
2605 return;
2606 if (WARN_ON(readl_poll_timeout(host->base + MSDC_DMA_CFG, val,
2607 !(val & MSDC_DMA_CFG_STS), 1, 3000)))
2608 return;
2609 msdc_reset_hw(host);
2610 }
2611 }
2612
msdc_cqe_pre_enable(struct mmc_host * mmc)2613 static void msdc_cqe_pre_enable(struct mmc_host *mmc)
2614 {
2615 struct cqhci_host *cq_host = mmc->cqe_private;
2616 u32 reg;
2617
2618 reg = cqhci_readl(cq_host, CQHCI_CFG);
2619 reg |= CQHCI_ENABLE;
2620 cqhci_writel(cq_host, reg, CQHCI_CFG);
2621 }
2622
msdc_cqe_post_disable(struct mmc_host * mmc)2623 static void msdc_cqe_post_disable(struct mmc_host *mmc)
2624 {
2625 struct cqhci_host *cq_host = mmc->cqe_private;
2626 u32 reg;
2627
2628 reg = cqhci_readl(cq_host, CQHCI_CFG);
2629 reg &= ~CQHCI_ENABLE;
2630 cqhci_writel(cq_host, reg, CQHCI_CFG);
2631 }
2632
2633 static const struct mmc_host_ops mt_msdc_ops = {
2634 .post_req = msdc_post_req,
2635 .pre_req = msdc_pre_req,
2636 .request = msdc_ops_request,
2637 .set_ios = msdc_ops_set_ios,
2638 .get_ro = mmc_gpio_get_ro,
2639 .get_cd = msdc_get_cd,
2640 .hs400_enhanced_strobe = msdc_hs400_enhanced_strobe,
2641 .enable_sdio_irq = msdc_enable_sdio_irq,
2642 .ack_sdio_irq = msdc_ack_sdio_irq,
2643 .start_signal_voltage_switch = msdc_ops_switch_volt,
2644 .card_busy = msdc_card_busy,
2645 .execute_tuning = msdc_execute_tuning,
2646 .prepare_hs400_tuning = msdc_prepare_hs400_tuning,
2647 .execute_hs400_tuning = msdc_execute_hs400_tuning,
2648 .card_hw_reset = msdc_hw_reset,
2649 };
2650
2651 static const struct cqhci_host_ops msdc_cmdq_ops = {
2652 .enable = msdc_cqe_enable,
2653 .disable = msdc_cqe_disable,
2654 .pre_enable = msdc_cqe_pre_enable,
2655 .post_disable = msdc_cqe_post_disable,
2656 };
2657
msdc_of_property_parse(struct platform_device * pdev,struct msdc_host * host)2658 static void msdc_of_property_parse(struct platform_device *pdev,
2659 struct msdc_host *host)
2660 {
2661 struct mmc_host *mmc = mmc_from_priv(host);
2662
2663 of_property_read_u32(pdev->dev.of_node, "mediatek,latch-ck",
2664 &host->latch_ck);
2665
2666 of_property_read_u32(pdev->dev.of_node, "hs400-ds-delay",
2667 &host->hs400_ds_delay);
2668
2669 of_property_read_u32(pdev->dev.of_node, "mediatek,hs400-ds-dly3",
2670 &host->hs400_ds_dly3);
2671
2672 of_property_read_u32(pdev->dev.of_node, "mediatek,hs200-cmd-int-delay",
2673 &host->hs200_cmd_int_delay);
2674
2675 of_property_read_u32(pdev->dev.of_node, "mediatek,hs400-cmd-int-delay",
2676 &host->hs400_cmd_int_delay);
2677
2678 if (of_property_read_bool(pdev->dev.of_node,
2679 "mediatek,hs400-cmd-resp-sel-rising"))
2680 host->hs400_cmd_resp_sel_rising = true;
2681 else
2682 host->hs400_cmd_resp_sel_rising = false;
2683
2684 if (of_property_read_u32(pdev->dev.of_node, "mediatek,tuning-step",
2685 &host->tuning_step)) {
2686 if (mmc->caps2 & MMC_CAP2_NO_MMC)
2687 host->tuning_step = PAD_DELAY_FULL;
2688 else
2689 host->tuning_step = PAD_DELAY_HALF;
2690 }
2691
2692 if (of_property_read_bool(pdev->dev.of_node,
2693 "supports-cqe"))
2694 host->cqhci = true;
2695 else
2696 host->cqhci = false;
2697 }
2698
msdc_of_clock_parse(struct platform_device * pdev,struct msdc_host * host)2699 static int msdc_of_clock_parse(struct platform_device *pdev,
2700 struct msdc_host *host)
2701 {
2702 int ret;
2703
2704 host->src_clk = devm_clk_get(&pdev->dev, "source");
2705 if (IS_ERR(host->src_clk))
2706 return PTR_ERR(host->src_clk);
2707
2708 host->h_clk = devm_clk_get(&pdev->dev, "hclk");
2709 if (IS_ERR(host->h_clk))
2710 return PTR_ERR(host->h_clk);
2711
2712 host->bus_clk = devm_clk_get_optional(&pdev->dev, "bus_clk");
2713 if (IS_ERR(host->bus_clk))
2714 host->bus_clk = NULL;
2715
2716 /*source clock control gate is optional clock*/
2717 host->src_clk_cg = devm_clk_get_optional(&pdev->dev, "source_cg");
2718 if (IS_ERR(host->src_clk_cg))
2719 return PTR_ERR(host->src_clk_cg);
2720
2721 /*
2722 * Fallback for legacy device-trees: src_clk and HCLK use the same
2723 * bit to control gating but they are parented to a different mux,
2724 * hence if our intention is to gate only the source, required
2725 * during a clk mode switch to avoid hw hangs, we need to gate
2726 * its parent (specified as a different clock only on new DTs).
2727 */
2728 if (!host->src_clk_cg) {
2729 host->src_clk_cg = clk_get_parent(host->src_clk);
2730 if (IS_ERR(host->src_clk_cg))
2731 return PTR_ERR(host->src_clk_cg);
2732 }
2733
2734 /* If present, always enable for this clock gate */
2735 host->sys_clk_cg = devm_clk_get_optional_enabled(&pdev->dev, "sys_cg");
2736 if (IS_ERR(host->sys_clk_cg))
2737 host->sys_clk_cg = NULL;
2738
2739 host->bulk_clks[0].id = "pclk_cg";
2740 host->bulk_clks[1].id = "axi_cg";
2741 host->bulk_clks[2].id = "ahb_cg";
2742 ret = devm_clk_bulk_get_optional(&pdev->dev, MSDC_NR_CLOCKS,
2743 host->bulk_clks);
2744 if (ret) {
2745 dev_err(&pdev->dev, "Cannot get pclk/axi/ahb clock gates\n");
2746 return ret;
2747 }
2748
2749 return 0;
2750 }
2751
msdc_drv_probe(struct platform_device * pdev)2752 static int msdc_drv_probe(struct platform_device *pdev)
2753 {
2754 struct mmc_host *mmc;
2755 struct msdc_host *host;
2756 struct resource *res;
2757 int ret;
2758
2759 if (!pdev->dev.of_node) {
2760 dev_err(&pdev->dev, "No DT found\n");
2761 return -EINVAL;
2762 }
2763
2764 /* Allocate MMC host for this device */
2765 mmc = devm_mmc_alloc_host(&pdev->dev, sizeof(struct msdc_host));
2766 if (!mmc)
2767 return -ENOMEM;
2768
2769 host = mmc_priv(mmc);
2770 ret = mmc_of_parse(mmc);
2771 if (ret)
2772 return ret;
2773
2774 host->base = devm_platform_ioremap_resource(pdev, 0);
2775 if (IS_ERR(host->base))
2776 return PTR_ERR(host->base);
2777
2778 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
2779 if (res) {
2780 host->top_base = devm_ioremap_resource(&pdev->dev, res);
2781 if (IS_ERR(host->top_base))
2782 host->top_base = NULL;
2783 }
2784
2785 ret = mmc_regulator_get_supply(mmc);
2786 if (ret)
2787 return ret;
2788
2789 ret = msdc_of_clock_parse(pdev, host);
2790 if (ret)
2791 return ret;
2792
2793 host->reset = devm_reset_control_get_optional_exclusive(&pdev->dev,
2794 "hrst");
2795 if (IS_ERR(host->reset))
2796 return PTR_ERR(host->reset);
2797
2798 /* only eMMC has crypto property */
2799 if (!(mmc->caps2 & MMC_CAP2_NO_MMC)) {
2800 host->crypto_clk = devm_clk_get_optional(&pdev->dev, "crypto");
2801 if (IS_ERR(host->crypto_clk))
2802 return PTR_ERR(host->crypto_clk);
2803 else if (host->crypto_clk)
2804 mmc->caps2 |= MMC_CAP2_CRYPTO;
2805 }
2806
2807 host->irq = platform_get_irq(pdev, 0);
2808 if (host->irq < 0)
2809 return host->irq;
2810
2811 host->pinctrl = devm_pinctrl_get(&pdev->dev);
2812 if (IS_ERR(host->pinctrl))
2813 return dev_err_probe(&pdev->dev, PTR_ERR(host->pinctrl),
2814 "Cannot find pinctrl");
2815
2816 host->pins_default = pinctrl_lookup_state(host->pinctrl, "default");
2817 if (IS_ERR(host->pins_default)) {
2818 dev_err(&pdev->dev, "Cannot find pinctrl default!\n");
2819 return PTR_ERR(host->pins_default);
2820 }
2821
2822 host->pins_uhs = pinctrl_lookup_state(host->pinctrl, "state_uhs");
2823 if (IS_ERR(host->pins_uhs)) {
2824 dev_err(&pdev->dev, "Cannot find pinctrl uhs!\n");
2825 return PTR_ERR(host->pins_uhs);
2826 }
2827
2828 /* Support for SDIO eint irq ? */
2829 if ((mmc->pm_caps & MMC_PM_WAKE_SDIO_IRQ) && (mmc->pm_caps & MMC_PM_KEEP_POWER)) {
2830 host->eint_irq = platform_get_irq_byname_optional(pdev, "sdio_wakeup");
2831 if (host->eint_irq > 0) {
2832 host->pins_eint = pinctrl_lookup_state(host->pinctrl, "state_eint");
2833 if (IS_ERR(host->pins_eint)) {
2834 dev_err(&pdev->dev, "Cannot find pinctrl eint!\n");
2835 host->pins_eint = NULL;
2836 } else {
2837 device_init_wakeup(&pdev->dev, true);
2838 }
2839 }
2840 }
2841
2842 msdc_of_property_parse(pdev, host);
2843
2844 host->dev = &pdev->dev;
2845 host->dev_comp = of_device_get_match_data(&pdev->dev);
2846 host->src_clk_freq = clk_get_rate(host->src_clk);
2847 /* Set host parameters to mmc */
2848 mmc->ops = &mt_msdc_ops;
2849 if (host->dev_comp->clk_div_bits == 8)
2850 mmc->f_min = DIV_ROUND_UP(host->src_clk_freq, 4 * 255);
2851 else
2852 mmc->f_min = DIV_ROUND_UP(host->src_clk_freq, 4 * 4095);
2853
2854 if (!(mmc->caps & MMC_CAP_NONREMOVABLE) &&
2855 !mmc_can_gpio_cd(mmc) &&
2856 host->dev_comp->use_internal_cd) {
2857 /*
2858 * Is removable but no GPIO declared, so
2859 * use internal functionality.
2860 */
2861 host->internal_cd = true;
2862 }
2863
2864 if (mmc->caps & MMC_CAP_SDIO_IRQ)
2865 mmc->caps2 |= MMC_CAP2_SDIO_IRQ_NOTHREAD;
2866
2867 mmc->caps |= MMC_CAP_CMD23;
2868 if (host->cqhci)
2869 mmc->caps2 |= MMC_CAP2_CQE | MMC_CAP2_CQE_DCMD;
2870 /* MMC core transfer sizes tunable parameters */
2871 mmc->max_segs = MAX_BD_NUM;
2872 if (host->dev_comp->support_64g)
2873 mmc->max_seg_size = BDMA_DESC_BUFLEN_EXT;
2874 else
2875 mmc->max_seg_size = BDMA_DESC_BUFLEN;
2876 mmc->max_blk_size = 2048;
2877 mmc->max_req_size = 512 * 1024;
2878 mmc->max_blk_count = mmc->max_req_size / 512;
2879 if (host->dev_comp->support_64g)
2880 host->dma_mask = DMA_BIT_MASK(36);
2881 else
2882 host->dma_mask = DMA_BIT_MASK(32);
2883 mmc_dev(mmc)->dma_mask = &host->dma_mask;
2884
2885 host->timeout_clks = 3 * 1048576;
2886 host->dma.gpd = dma_alloc_coherent(&pdev->dev,
2887 2 * sizeof(struct mt_gpdma_desc),
2888 &host->dma.gpd_addr, GFP_KERNEL);
2889 host->dma.bd = dma_alloc_coherent(&pdev->dev,
2890 MAX_BD_NUM * sizeof(struct mt_bdma_desc),
2891 &host->dma.bd_addr, GFP_KERNEL);
2892 if (!host->dma.gpd || !host->dma.bd) {
2893 ret = -ENOMEM;
2894 goto release_mem;
2895 }
2896 msdc_init_gpd_bd(host, &host->dma);
2897 INIT_DELAYED_WORK(&host->req_timeout, msdc_request_timeout);
2898 spin_lock_init(&host->lock);
2899
2900 platform_set_drvdata(pdev, mmc);
2901 ret = msdc_ungate_clock(host);
2902 if (ret) {
2903 dev_err(&pdev->dev, "Cannot ungate clocks!\n");
2904 goto release_clk;
2905 }
2906 msdc_init_hw(host);
2907
2908 if (mmc->caps2 & MMC_CAP2_CQE) {
2909 host->cq_host = devm_kzalloc(mmc->parent,
2910 sizeof(*host->cq_host),
2911 GFP_KERNEL);
2912 if (!host->cq_host) {
2913 ret = -ENOMEM;
2914 goto release;
2915 }
2916 host->cq_host->caps |= CQHCI_TASK_DESC_SZ_128;
2917 host->cq_host->mmio = host->base + 0x800;
2918 host->cq_host->ops = &msdc_cmdq_ops;
2919 ret = cqhci_init(host->cq_host, mmc, true);
2920 if (ret)
2921 goto release;
2922 mmc->max_segs = 128;
2923 /* cqhci 16bit length */
2924 /* 0 size, means 65536 so we don't have to -1 here */
2925 mmc->max_seg_size = 64 * 1024;
2926 /* Reduce CIT to 0x40 that corresponds to 2.35us */
2927 msdc_cqe_cit_cal(host, 2350);
2928 }
2929
2930 ret = devm_request_irq(&pdev->dev, host->irq, msdc_irq,
2931 IRQF_TRIGGER_NONE, pdev->name, host);
2932 if (ret)
2933 goto release;
2934
2935 pm_runtime_set_active(host->dev);
2936 pm_runtime_set_autosuspend_delay(host->dev, MTK_MMC_AUTOSUSPEND_DELAY);
2937 pm_runtime_use_autosuspend(host->dev);
2938 pm_runtime_enable(host->dev);
2939 ret = mmc_add_host(mmc);
2940
2941 if (ret)
2942 goto end;
2943
2944 return 0;
2945 end:
2946 pm_runtime_disable(host->dev);
2947 release:
2948 msdc_deinit_hw(host);
2949 release_clk:
2950 msdc_gate_clock(host);
2951 platform_set_drvdata(pdev, NULL);
2952 release_mem:
2953 device_init_wakeup(&pdev->dev, false);
2954 if (host->dma.gpd)
2955 dma_free_coherent(&pdev->dev,
2956 2 * sizeof(struct mt_gpdma_desc),
2957 host->dma.gpd, host->dma.gpd_addr);
2958 if (host->dma.bd)
2959 dma_free_coherent(&pdev->dev,
2960 MAX_BD_NUM * sizeof(struct mt_bdma_desc),
2961 host->dma.bd, host->dma.bd_addr);
2962 return ret;
2963 }
2964
msdc_drv_remove(struct platform_device * pdev)2965 static void msdc_drv_remove(struct platform_device *pdev)
2966 {
2967 struct mmc_host *mmc;
2968 struct msdc_host *host;
2969
2970 mmc = platform_get_drvdata(pdev);
2971 host = mmc_priv(mmc);
2972
2973 pm_runtime_get_sync(host->dev);
2974
2975 platform_set_drvdata(pdev, NULL);
2976 mmc_remove_host(mmc);
2977 msdc_deinit_hw(host);
2978 msdc_gate_clock(host);
2979
2980 pm_runtime_disable(host->dev);
2981 pm_runtime_put_noidle(host->dev);
2982 dma_free_coherent(&pdev->dev,
2983 2 * sizeof(struct mt_gpdma_desc),
2984 host->dma.gpd, host->dma.gpd_addr);
2985 dma_free_coherent(&pdev->dev, MAX_BD_NUM * sizeof(struct mt_bdma_desc),
2986 host->dma.bd, host->dma.bd_addr);
2987 device_init_wakeup(&pdev->dev, false);
2988 }
2989
msdc_save_reg(struct msdc_host * host)2990 static void msdc_save_reg(struct msdc_host *host)
2991 {
2992 u32 tune_reg = host->dev_comp->pad_tune_reg;
2993
2994 host->save_para.msdc_cfg = readl(host->base + MSDC_CFG);
2995 host->save_para.iocon = readl(host->base + MSDC_IOCON);
2996 host->save_para.sdc_cfg = readl(host->base + SDC_CFG);
2997 host->save_para.patch_bit0 = readl(host->base + MSDC_PATCH_BIT);
2998 host->save_para.patch_bit1 = readl(host->base + MSDC_PATCH_BIT1);
2999 host->save_para.patch_bit2 = readl(host->base + MSDC_PATCH_BIT2);
3000 host->save_para.pad_ds_tune = readl(host->base + PAD_DS_TUNE);
3001 host->save_para.pad_cmd_tune = readl(host->base + PAD_CMD_TUNE);
3002 host->save_para.emmc50_cfg0 = readl(host->base + EMMC50_CFG0);
3003 host->save_para.emmc50_cfg3 = readl(host->base + EMMC50_CFG3);
3004 host->save_para.sdc_fifo_cfg = readl(host->base + SDC_FIFO_CFG);
3005 if (host->top_base) {
3006 host->save_para.emmc_top_control =
3007 readl(host->top_base + EMMC_TOP_CONTROL);
3008 host->save_para.emmc_top_cmd =
3009 readl(host->top_base + EMMC_TOP_CMD);
3010 host->save_para.emmc50_pad_ds_tune =
3011 readl(host->top_base + EMMC50_PAD_DS_TUNE);
3012 } else {
3013 host->save_para.pad_tune = readl(host->base + tune_reg);
3014 }
3015 }
3016
msdc_restore_reg(struct msdc_host * host)3017 static void msdc_restore_reg(struct msdc_host *host)
3018 {
3019 struct mmc_host *mmc = mmc_from_priv(host);
3020 u32 tune_reg = host->dev_comp->pad_tune_reg;
3021
3022 writel(host->save_para.msdc_cfg, host->base + MSDC_CFG);
3023 writel(host->save_para.iocon, host->base + MSDC_IOCON);
3024 writel(host->save_para.sdc_cfg, host->base + SDC_CFG);
3025 writel(host->save_para.patch_bit0, host->base + MSDC_PATCH_BIT);
3026 writel(host->save_para.patch_bit1, host->base + MSDC_PATCH_BIT1);
3027 writel(host->save_para.patch_bit2, host->base + MSDC_PATCH_BIT2);
3028 writel(host->save_para.pad_ds_tune, host->base + PAD_DS_TUNE);
3029 writel(host->save_para.pad_cmd_tune, host->base + PAD_CMD_TUNE);
3030 writel(host->save_para.emmc50_cfg0, host->base + EMMC50_CFG0);
3031 writel(host->save_para.emmc50_cfg3, host->base + EMMC50_CFG3);
3032 writel(host->save_para.sdc_fifo_cfg, host->base + SDC_FIFO_CFG);
3033 if (host->top_base) {
3034 writel(host->save_para.emmc_top_control,
3035 host->top_base + EMMC_TOP_CONTROL);
3036 writel(host->save_para.emmc_top_cmd,
3037 host->top_base + EMMC_TOP_CMD);
3038 writel(host->save_para.emmc50_pad_ds_tune,
3039 host->top_base + EMMC50_PAD_DS_TUNE);
3040 } else {
3041 writel(host->save_para.pad_tune, host->base + tune_reg);
3042 }
3043
3044 if (sdio_irq_claimed(mmc))
3045 __msdc_enable_sdio_irq(host, 1);
3046 }
3047
msdc_runtime_suspend(struct device * dev)3048 static int __maybe_unused msdc_runtime_suspend(struct device *dev)
3049 {
3050 struct mmc_host *mmc = dev_get_drvdata(dev);
3051 struct msdc_host *host = mmc_priv(mmc);
3052
3053 msdc_save_reg(host);
3054
3055 if (sdio_irq_claimed(mmc)) {
3056 if (host->pins_eint) {
3057 disable_irq(host->irq);
3058 pinctrl_select_state(host->pinctrl, host->pins_eint);
3059 }
3060
3061 __msdc_enable_sdio_irq(host, 0);
3062 }
3063 msdc_gate_clock(host);
3064 return 0;
3065 }
3066
msdc_runtime_resume(struct device * dev)3067 static int __maybe_unused msdc_runtime_resume(struct device *dev)
3068 {
3069 struct mmc_host *mmc = dev_get_drvdata(dev);
3070 struct msdc_host *host = mmc_priv(mmc);
3071 int ret;
3072
3073 ret = msdc_ungate_clock(host);
3074 if (ret)
3075 return ret;
3076
3077 msdc_restore_reg(host);
3078
3079 if (sdio_irq_claimed(mmc) && host->pins_eint) {
3080 pinctrl_select_state(host->pinctrl, host->pins_uhs);
3081 enable_irq(host->irq);
3082 }
3083 return 0;
3084 }
3085
msdc_suspend(struct device * dev)3086 static int __maybe_unused msdc_suspend(struct device *dev)
3087 {
3088 struct mmc_host *mmc = dev_get_drvdata(dev);
3089 struct msdc_host *host = mmc_priv(mmc);
3090 int ret;
3091 u32 val;
3092
3093 if (mmc->caps2 & MMC_CAP2_CQE) {
3094 ret = cqhci_suspend(mmc);
3095 if (ret)
3096 return ret;
3097 val = readl(host->base + MSDC_INT);
3098 writel(val, host->base + MSDC_INT);
3099 }
3100
3101 /*
3102 * Bump up runtime PM usage counter otherwise dev->power.needs_force_resume will
3103 * not be marked as 1, pm_runtime_force_resume() will go out directly.
3104 */
3105 if (sdio_irq_claimed(mmc) && host->pins_eint)
3106 pm_runtime_get_noresume(dev);
3107
3108 return pm_runtime_force_suspend(dev);
3109 }
3110
msdc_resume(struct device * dev)3111 static int __maybe_unused msdc_resume(struct device *dev)
3112 {
3113 struct mmc_host *mmc = dev_get_drvdata(dev);
3114 struct msdc_host *host = mmc_priv(mmc);
3115
3116 if (sdio_irq_claimed(mmc) && host->pins_eint)
3117 pm_runtime_put_noidle(dev);
3118
3119 return pm_runtime_force_resume(dev);
3120 }
3121
3122 static const struct dev_pm_ops msdc_dev_pm_ops = {
3123 SET_SYSTEM_SLEEP_PM_OPS(msdc_suspend, msdc_resume)
3124 SET_RUNTIME_PM_OPS(msdc_runtime_suspend, msdc_runtime_resume, NULL)
3125 };
3126
3127 static struct platform_driver mt_msdc_driver = {
3128 .probe = msdc_drv_probe,
3129 .remove_new = msdc_drv_remove,
3130 .driver = {
3131 .name = "mtk-msdc",
3132 .probe_type = PROBE_PREFER_ASYNCHRONOUS,
3133 .of_match_table = msdc_of_ids,
3134 .pm = &msdc_dev_pm_ops,
3135 },
3136 };
3137
3138 module_platform_driver(mt_msdc_driver);
3139 MODULE_LICENSE("GPL v2");
3140 MODULE_DESCRIPTION("MediaTek SD/MMC Card Driver");
3141