1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Freescale eSDHC i.MX controller driver for the platform bus.
4 *
5 * derived from the OF-version.
6 *
7 * Copyright (c) 2010 Pengutronix e.K.
8 * Author: Wolfram Sang <kernel@pengutronix.de>
9 */
10
11 #include <linux/bitfield.h>
12 #include <linux/io.h>
13 #include <linux/iopoll.h>
14 #include <linux/delay.h>
15 #include <linux/err.h>
16 #include <linux/clk.h>
17 #include <linux/module.h>
18 #include <linux/slab.h>
19 #include <linux/pm_qos.h>
20 #include <linux/mmc/host.h>
21 #include <linux/mmc/mmc.h>
22 #include <linux/mmc/sdio.h>
23 #include <linux/mmc/slot-gpio.h>
24 #include <linux/of.h>
25 #include <linux/platform_device.h>
26 #include <linux/pinctrl/consumer.h>
27 #include <linux/pm_runtime.h>
28 #include "sdhci-cqhci.h"
29 #include "sdhci-pltfm.h"
30 #include "sdhci-esdhc.h"
31 #include "cqhci.h"
32
33 #define ESDHC_SYS_CTRL_DTOCV_MASK 0x0f
34 #define ESDHC_CTRL_D3CD 0x08
35 #define ESDHC_BURST_LEN_EN_INCR (1 << 27)
36 /* VENDOR SPEC register */
37 #define ESDHC_VENDOR_SPEC 0xc0
38 #define ESDHC_VENDOR_SPEC_SDIO_QUIRK (1 << 1)
39 #define ESDHC_VENDOR_SPEC_VSELECT (1 << 1)
40 #define ESDHC_VENDOR_SPEC_FRC_SDCLK_ON (1 << 8)
41 #define ESDHC_DEBUG_SEL_AND_STATUS_REG 0xc2
42 #define ESDHC_DEBUG_SEL_REG 0xc3
43 #define ESDHC_DEBUG_SEL_MASK 0xf
44 #define ESDHC_DEBUG_SEL_CMD_STATE 1
45 #define ESDHC_DEBUG_SEL_DATA_STATE 2
46 #define ESDHC_DEBUG_SEL_TRANS_STATE 3
47 #define ESDHC_DEBUG_SEL_DMA_STATE 4
48 #define ESDHC_DEBUG_SEL_ADMA_STATE 5
49 #define ESDHC_DEBUG_SEL_FIFO_STATE 6
50 #define ESDHC_DEBUG_SEL_ASYNC_FIFO_STATE 7
51 #define ESDHC_WTMK_LVL 0x44
52 #define ESDHC_WTMK_DEFAULT_VAL 0x10401040
53 #define ESDHC_WTMK_LVL_RD_WML_MASK 0x000000FF
54 #define ESDHC_WTMK_LVL_RD_WML_SHIFT 0
55 #define ESDHC_WTMK_LVL_WR_WML_MASK 0x00FF0000
56 #define ESDHC_WTMK_LVL_WR_WML_SHIFT 16
57 #define ESDHC_WTMK_LVL_WML_VAL_DEF 64
58 #define ESDHC_WTMK_LVL_WML_VAL_MAX 128
59 #define ESDHC_MIX_CTRL 0x48
60 #define ESDHC_MIX_CTRL_DDREN (1 << 3)
61 #define ESDHC_MIX_CTRL_AC23EN (1 << 7)
62 #define ESDHC_MIX_CTRL_EXE_TUNE (1 << 22)
63 #define ESDHC_MIX_CTRL_SMPCLK_SEL (1 << 23)
64 #define ESDHC_MIX_CTRL_AUTO_TUNE_EN (1 << 24)
65 #define ESDHC_MIX_CTRL_FBCLK_SEL (1 << 25)
66 #define ESDHC_MIX_CTRL_HS400_EN (1 << 26)
67 #define ESDHC_MIX_CTRL_HS400_ES_EN (1 << 27)
68 /* Bits 3 and 6 are not SDHCI standard definitions */
69 #define ESDHC_MIX_CTRL_SDHCI_MASK 0xb7
70 /* Tuning bits */
71 #define ESDHC_MIX_CTRL_TUNING_MASK 0x03c00000
72
73 /* dll control register */
74 #define ESDHC_DLL_CTRL 0x60
75 #define ESDHC_DLL_OVERRIDE_VAL_SHIFT 9
76 #define ESDHC_DLL_OVERRIDE_EN_SHIFT 8
77
78 /* tune control register */
79 #define ESDHC_TUNE_CTRL_STATUS 0x68
80 #define ESDHC_TUNE_CTRL_STEP 1
81 #define ESDHC_TUNE_CTRL_MIN 0
82 #define ESDHC_TUNE_CTRL_MAX ((1 << 7) - 1)
83
84 /* strobe dll register */
85 #define ESDHC_STROBE_DLL_CTRL 0x70
86 #define ESDHC_STROBE_DLL_CTRL_ENABLE (1 << 0)
87 #define ESDHC_STROBE_DLL_CTRL_RESET (1 << 1)
88 #define ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_DEFAULT 0x7
89 #define ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_SHIFT 3
90 #define ESDHC_STROBE_DLL_CTRL_SLV_UPDATE_INT_DEFAULT (4 << 20)
91
92 #define ESDHC_STROBE_DLL_STATUS 0x74
93 #define ESDHC_STROBE_DLL_STS_REF_LOCK (1 << 1)
94 #define ESDHC_STROBE_DLL_STS_SLV_LOCK 0x1
95
96 #define ESDHC_VEND_SPEC2 0xc8
97 #define ESDHC_VEND_SPEC2_EN_BUSY_IRQ (1 << 8)
98 #define ESDHC_VEND_SPEC2_AUTO_TUNE_8BIT_EN (1 << 4)
99 #define ESDHC_VEND_SPEC2_AUTO_TUNE_4BIT_EN (0 << 4)
100 #define ESDHC_VEND_SPEC2_AUTO_TUNE_1BIT_EN (2 << 4)
101 #define ESDHC_VEND_SPEC2_AUTO_TUNE_CMD_EN (1 << 6)
102 #define ESDHC_VEND_SPEC2_AUTO_TUNE_MODE_MASK (7 << 4)
103
104 #define ESDHC_TUNING_CTRL 0xcc
105 #define ESDHC_STD_TUNING_EN (1 << 24)
106 /* NOTE: the minimum valid tuning start tap for mx6sl is 1 */
107 #define ESDHC_TUNING_START_TAP_DEFAULT 0x1
108 #define ESDHC_TUNING_START_TAP_MASK 0x7f
109 #define ESDHC_TUNING_CMD_CRC_CHECK_DISABLE (1 << 7)
110 #define ESDHC_TUNING_STEP_DEFAULT 0x1
111 #define ESDHC_TUNING_STEP_MASK 0x00070000
112 #define ESDHC_TUNING_STEP_SHIFT 16
113
114 /* pinctrl state */
115 #define ESDHC_PINCTRL_STATE_100MHZ "state_100mhz"
116 #define ESDHC_PINCTRL_STATE_200MHZ "state_200mhz"
117
118 /*
119 * Our interpretation of the SDHCI_HOST_CONTROL register
120 */
121 #define ESDHC_CTRL_4BITBUS (0x1 << 1)
122 #define ESDHC_CTRL_8BITBUS (0x2 << 1)
123 #define ESDHC_CTRL_BUSWIDTH_MASK (0x3 << 1)
124 #define USDHC_GET_BUSWIDTH(c) (c & ESDHC_CTRL_BUSWIDTH_MASK)
125
126 /*
127 * There is an INT DMA ERR mismatch between eSDHC and STD SDHC SPEC:
128 * Bit25 is used in STD SPEC, and is reserved in fsl eSDHC design,
129 * but bit28 is used as the INT DMA ERR in fsl eSDHC design.
130 * Define this macro DMA error INT for fsl eSDHC
131 */
132 #define ESDHC_INT_VENDOR_SPEC_DMA_ERR (1 << 28)
133
134 /* the address offset of CQHCI */
135 #define ESDHC_CQHCI_ADDR_OFFSET 0x100
136
137 /*
138 * The CMDTYPE of the CMD register (offset 0xE) should be set to
139 * "11" when the STOP CMD12 is issued on imx53 to abort one
140 * open ended multi-blk IO. Otherwise the TC INT wouldn't
141 * be generated.
142 * In exact block transfer, the controller doesn't complete the
143 * operations automatically as required at the end of the
144 * transfer and remains on hold if the abort command is not sent.
145 * As a result, the TC flag is not asserted and SW received timeout
146 * exception. Bit1 of Vendor Spec register is used to fix it.
147 */
148 #define ESDHC_FLAG_MULTIBLK_NO_INT BIT(1)
149 /*
150 * The flag tells that the ESDHC controller is an USDHC block that is
151 * integrated on the i.MX6 series.
152 */
153 #define ESDHC_FLAG_USDHC BIT(3)
154 /* The IP supports manual tuning process */
155 #define ESDHC_FLAG_MAN_TUNING BIT(4)
156 /* The IP supports standard tuning process */
157 #define ESDHC_FLAG_STD_TUNING BIT(5)
158 /* The IP has SDHCI_CAPABILITIES_1 register */
159 #define ESDHC_FLAG_HAVE_CAP1 BIT(6)
160 /*
161 * The IP has erratum ERR004536
162 * uSDHC: ADMA Length Mismatch Error occurs if the AHB read access is slow,
163 * when reading data from the card
164 * This flag is also set for i.MX25 and i.MX35 in order to get
165 * SDHCI_QUIRK_BROKEN_ADMA, but for different reasons (ADMA capability bits).
166 */
167 #define ESDHC_FLAG_ERR004536 BIT(7)
168 /* The IP supports HS200 mode */
169 #define ESDHC_FLAG_HS200 BIT(8)
170 /* The IP supports HS400 mode */
171 #define ESDHC_FLAG_HS400 BIT(9)
172 /*
173 * The IP has errata ERR010450
174 * uSDHC: At 1.8V due to the I/O timing limit, for SDR mode, SD card
175 * clock can't exceed 150MHz, for DDR mode, SD card clock can't exceed 45MHz.
176 */
177 #define ESDHC_FLAG_ERR010450 BIT(10)
178 /* The IP supports HS400ES mode */
179 #define ESDHC_FLAG_HS400_ES BIT(11)
180 /* The IP has Host Controller Interface for Command Queuing */
181 #define ESDHC_FLAG_CQHCI BIT(12)
182 /* need request pmqos during low power */
183 #define ESDHC_FLAG_PMQOS BIT(13)
184 /* The IP state got lost in low power mode */
185 #define ESDHC_FLAG_STATE_LOST_IN_LPMODE BIT(14)
186 /* The IP lost clock rate in PM_RUNTIME */
187 #define ESDHC_FLAG_CLK_RATE_LOST_IN_PM_RUNTIME BIT(15)
188 /*
189 * The IP do not support the ACMD23 feature completely when use ADMA mode.
190 * In ADMA mode, it only use the 16 bit block count of the register 0x4
191 * (BLOCK_ATT) as the CMD23's argument for ACMD23 mode, which means it will
192 * ignore the upper 16 bit of the CMD23's argument. This will block the reliable
193 * write operation in RPMB, because RPMB reliable write need to set the bit31
194 * of the CMD23's argument.
195 * imx6qpdl/imx6sx/imx6sl/imx7d has this limitation only for ADMA mode, SDMA
196 * do not has this limitation. so when these SoC use ADMA mode, it need to
197 * disable the ACMD23 feature.
198 */
199 #define ESDHC_FLAG_BROKEN_AUTO_CMD23 BIT(16)
200
201 /* ERR004536 is not applicable for the IP */
202 #define ESDHC_FLAG_SKIP_ERR004536 BIT(17)
203
204 /* The IP does not have GPIO CD wake capabilities */
205 #define ESDHC_FLAG_SKIP_CD_WAKE BIT(18)
206
207 enum wp_types {
208 ESDHC_WP_NONE, /* no WP, neither controller nor gpio */
209 ESDHC_WP_CONTROLLER, /* mmc controller internal WP */
210 ESDHC_WP_GPIO, /* external gpio pin for WP */
211 };
212
213 enum cd_types {
214 ESDHC_CD_NONE, /* no CD, neither controller nor gpio */
215 ESDHC_CD_CONTROLLER, /* mmc controller internal CD */
216 ESDHC_CD_GPIO, /* external gpio pin for CD */
217 ESDHC_CD_PERMANENT, /* no CD, card permanently wired to host */
218 };
219
220 /*
221 * struct esdhc_platform_data - platform data for esdhc on i.MX
222 *
223 * ESDHC_WP(CD)_CONTROLLER type is not available on i.MX25/35.
224 *
225 * @wp_type: type of write_protect method (see wp_types enum above)
226 * @cd_type: type of card_detect method (see cd_types enum above)
227 */
228
229 struct esdhc_platform_data {
230 enum wp_types wp_type;
231 enum cd_types cd_type;
232 int max_bus_width;
233 unsigned int delay_line;
234 unsigned int tuning_step; /* The delay cell steps in tuning procedure */
235 unsigned int tuning_start_tap; /* The start delay cell point in tuning procedure */
236 unsigned int strobe_dll_delay_target; /* The delay cell for strobe pad (read clock) */
237 };
238
239 struct esdhc_soc_data {
240 u32 flags;
241 u32 quirks;
242 };
243
244 static const struct esdhc_soc_data esdhc_imx25_data = {
245 .flags = ESDHC_FLAG_ERR004536,
246 };
247
248 static const struct esdhc_soc_data esdhc_imx35_data = {
249 .flags = ESDHC_FLAG_ERR004536,
250 };
251
252 static const struct esdhc_soc_data esdhc_imx51_data = {
253 .flags = 0,
254 };
255
256 static const struct esdhc_soc_data esdhc_imx53_data = {
257 .flags = ESDHC_FLAG_MULTIBLK_NO_INT,
258 };
259
260 static const struct esdhc_soc_data usdhc_imx6q_data = {
261 .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_MAN_TUNING
262 | ESDHC_FLAG_BROKEN_AUTO_CMD23,
263 };
264
265 static const struct esdhc_soc_data usdhc_imx6sl_data = {
266 .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING
267 | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_ERR004536
268 | ESDHC_FLAG_HS200
269 | ESDHC_FLAG_BROKEN_AUTO_CMD23,
270 };
271
272 static const struct esdhc_soc_data usdhc_imx6sll_data = {
273 .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING
274 | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200
275 | ESDHC_FLAG_HS400
276 | ESDHC_FLAG_STATE_LOST_IN_LPMODE,
277 };
278
279 static const struct esdhc_soc_data usdhc_imx6sx_data = {
280 .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING
281 | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200
282 | ESDHC_FLAG_STATE_LOST_IN_LPMODE
283 | ESDHC_FLAG_BROKEN_AUTO_CMD23,
284 };
285
286 static const struct esdhc_soc_data usdhc_imx6ull_data = {
287 .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING
288 | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200
289 | ESDHC_FLAG_ERR010450
290 | ESDHC_FLAG_STATE_LOST_IN_LPMODE,
291 };
292
293 static const struct esdhc_soc_data usdhc_imx7d_data = {
294 .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING
295 | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200
296 | ESDHC_FLAG_HS400
297 | ESDHC_FLAG_STATE_LOST_IN_LPMODE
298 | ESDHC_FLAG_BROKEN_AUTO_CMD23,
299 };
300
301 static struct esdhc_soc_data usdhc_s32g2_data = {
302 .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_MAN_TUNING
303 | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200
304 | ESDHC_FLAG_HS400 | ESDHC_FLAG_HS400_ES
305 | ESDHC_FLAG_SKIP_ERR004536 | ESDHC_FLAG_SKIP_CD_WAKE,
306 .quirks = SDHCI_QUIRK_NO_LED,
307 };
308
309 static struct esdhc_soc_data usdhc_imx7ulp_data = {
310 .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING
311 | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200
312 | ESDHC_FLAG_PMQOS | ESDHC_FLAG_HS400
313 | ESDHC_FLAG_STATE_LOST_IN_LPMODE,
314 .quirks = SDHCI_QUIRK_NO_LED,
315 };
316 static struct esdhc_soc_data usdhc_imxrt1050_data = {
317 .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING
318 | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200,
319 .quirks = SDHCI_QUIRK_NO_LED,
320 };
321
322 static struct esdhc_soc_data usdhc_imx8qxp_data = {
323 .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING
324 | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200
325 | ESDHC_FLAG_HS400 | ESDHC_FLAG_HS400_ES
326 | ESDHC_FLAG_STATE_LOST_IN_LPMODE
327 | ESDHC_FLAG_CLK_RATE_LOST_IN_PM_RUNTIME,
328 .quirks = SDHCI_QUIRK_NO_LED,
329 };
330
331 static struct esdhc_soc_data usdhc_imx8mm_data = {
332 .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING
333 | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200
334 | ESDHC_FLAG_HS400 | ESDHC_FLAG_HS400_ES
335 | ESDHC_FLAG_STATE_LOST_IN_LPMODE,
336 .quirks = SDHCI_QUIRK_NO_LED,
337 };
338
339 struct pltfm_imx_data {
340 u32 scratchpad;
341 struct pinctrl *pinctrl;
342 struct pinctrl_state *pins_100mhz;
343 struct pinctrl_state *pins_200mhz;
344 const struct esdhc_soc_data *socdata;
345 struct esdhc_platform_data boarddata;
346 struct clk *clk_ipg;
347 struct clk *clk_ahb;
348 struct clk *clk_per;
349 unsigned int actual_clock;
350
351 /*
352 * USDHC has one limition, require the SDIO device a different
353 * register setting. Driver has to recognize card type during
354 * the card init, but at this stage, mmc_host->card is not
355 * available. So involve this field to save the card type
356 * during card init through usdhc_init_card().
357 */
358 unsigned int init_card_type;
359
360 enum {
361 NO_CMD_PENDING, /* no multiblock command pending */
362 MULTIBLK_IN_PROCESS, /* exact multiblock cmd in process */
363 WAIT_FOR_INT, /* sent CMD12, waiting for response INT */
364 } multiblock_status;
365 u32 is_ddr;
366 struct pm_qos_request pm_qos_req;
367 };
368
369 static const struct of_device_id imx_esdhc_dt_ids[] = {
370 { .compatible = "fsl,imx25-esdhc", .data = &esdhc_imx25_data, },
371 { .compatible = "fsl,imx35-esdhc", .data = &esdhc_imx35_data, },
372 { .compatible = "fsl,imx51-esdhc", .data = &esdhc_imx51_data, },
373 { .compatible = "fsl,imx53-esdhc", .data = &esdhc_imx53_data, },
374 { .compatible = "fsl,imx6sx-usdhc", .data = &usdhc_imx6sx_data, },
375 { .compatible = "fsl,imx6sl-usdhc", .data = &usdhc_imx6sl_data, },
376 { .compatible = "fsl,imx6sll-usdhc", .data = &usdhc_imx6sll_data, },
377 { .compatible = "fsl,imx6q-usdhc", .data = &usdhc_imx6q_data, },
378 { .compatible = "fsl,imx6ull-usdhc", .data = &usdhc_imx6ull_data, },
379 { .compatible = "fsl,imx7d-usdhc", .data = &usdhc_imx7d_data, },
380 { .compatible = "fsl,imx7ulp-usdhc", .data = &usdhc_imx7ulp_data, },
381 { .compatible = "fsl,imx8qxp-usdhc", .data = &usdhc_imx8qxp_data, },
382 { .compatible = "fsl,imx8mm-usdhc", .data = &usdhc_imx8mm_data, },
383 { .compatible = "fsl,imxrt1050-usdhc", .data = &usdhc_imxrt1050_data, },
384 { .compatible = "nxp,s32g2-usdhc", .data = &usdhc_s32g2_data, },
385 { /* sentinel */ }
386 };
387 MODULE_DEVICE_TABLE(of, imx_esdhc_dt_ids);
388
is_imx25_esdhc(struct pltfm_imx_data * data)389 static inline int is_imx25_esdhc(struct pltfm_imx_data *data)
390 {
391 return data->socdata == &esdhc_imx25_data;
392 }
393
is_imx53_esdhc(struct pltfm_imx_data * data)394 static inline int is_imx53_esdhc(struct pltfm_imx_data *data)
395 {
396 return data->socdata == &esdhc_imx53_data;
397 }
398
esdhc_is_usdhc(struct pltfm_imx_data * data)399 static inline int esdhc_is_usdhc(struct pltfm_imx_data *data)
400 {
401 return !!(data->socdata->flags & ESDHC_FLAG_USDHC);
402 }
403
esdhc_clrset_le(struct sdhci_host * host,u32 mask,u32 val,int reg)404 static inline void esdhc_clrset_le(struct sdhci_host *host, u32 mask, u32 val, int reg)
405 {
406 void __iomem *base = host->ioaddr + (reg & ~0x3);
407 u32 shift = (reg & 0x3) * 8;
408
409 writel(((readl(base) & ~(mask << shift)) | (val << shift)), base);
410 }
411
412 #define DRIVER_NAME "sdhci-esdhc-imx"
413 #define ESDHC_IMX_DUMP(f, x...) \
414 pr_err("%s: " DRIVER_NAME ": " f, mmc_hostname(host->mmc), ## x)
esdhc_dump_debug_regs(struct sdhci_host * host)415 static void esdhc_dump_debug_regs(struct sdhci_host *host)
416 {
417 int i;
418 char *debug_status[7] = {
419 "cmd debug status",
420 "data debug status",
421 "trans debug status",
422 "dma debug status",
423 "adma debug status",
424 "fifo debug status",
425 "async fifo debug status"
426 };
427
428 ESDHC_IMX_DUMP("========= ESDHC IMX DEBUG STATUS DUMP =========\n");
429 for (i = 0; i < 7; i++) {
430 esdhc_clrset_le(host, ESDHC_DEBUG_SEL_MASK,
431 ESDHC_DEBUG_SEL_CMD_STATE + i, ESDHC_DEBUG_SEL_REG);
432 ESDHC_IMX_DUMP("%s: 0x%04x\n", debug_status[i],
433 readw(host->ioaddr + ESDHC_DEBUG_SEL_AND_STATUS_REG));
434 }
435
436 esdhc_clrset_le(host, ESDHC_DEBUG_SEL_MASK, 0, ESDHC_DEBUG_SEL_REG);
437
438 }
439
esdhc_wait_for_card_clock_gate_off(struct sdhci_host * host)440 static inline void esdhc_wait_for_card_clock_gate_off(struct sdhci_host *host)
441 {
442 u32 present_state;
443 int ret;
444
445 ret = readl_poll_timeout(host->ioaddr + ESDHC_PRSSTAT, present_state,
446 (present_state & ESDHC_CLOCK_GATE_OFF), 2, 100);
447 if (ret == -ETIMEDOUT)
448 dev_warn(mmc_dev(host->mmc), "%s: card clock still not gate off in 100us!.\n", __func__);
449 }
450
451 /* Enable the auto tuning circuit to check the CMD line and BUS line */
usdhc_auto_tuning_mode_sel_and_en(struct sdhci_host * host)452 static inline void usdhc_auto_tuning_mode_sel_and_en(struct sdhci_host *host)
453 {
454 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
455 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
456 u32 buswidth, auto_tune_buswidth;
457 u32 reg;
458
459 buswidth = USDHC_GET_BUSWIDTH(readl(host->ioaddr + SDHCI_HOST_CONTROL));
460
461 switch (buswidth) {
462 case ESDHC_CTRL_8BITBUS:
463 auto_tune_buswidth = ESDHC_VEND_SPEC2_AUTO_TUNE_8BIT_EN;
464 break;
465 case ESDHC_CTRL_4BITBUS:
466 auto_tune_buswidth = ESDHC_VEND_SPEC2_AUTO_TUNE_4BIT_EN;
467 break;
468 default: /* 1BITBUS */
469 auto_tune_buswidth = ESDHC_VEND_SPEC2_AUTO_TUNE_1BIT_EN;
470 break;
471 }
472
473 /*
474 * For USDHC, auto tuning circuit can not handle the async sdio
475 * device interrupt correctly. When sdio device use 4 data lines,
476 * async sdio interrupt will use the shared DAT[1], if enable auto
477 * tuning circuit check these 4 data lines, include the DAT[1],
478 * this circuit will detect this interrupt, take this as a data on
479 * DAT[1], and adjust the delay cell wrongly.
480 * This is the hardware design limitation, to avoid this, for sdio
481 * device, config the auto tuning circuit only check DAT[0] and CMD
482 * line.
483 */
484 if (imx_data->init_card_type == MMC_TYPE_SDIO)
485 auto_tune_buswidth = ESDHC_VEND_SPEC2_AUTO_TUNE_1BIT_EN;
486
487 esdhc_clrset_le(host, ESDHC_VEND_SPEC2_AUTO_TUNE_MODE_MASK,
488 auto_tune_buswidth | ESDHC_VEND_SPEC2_AUTO_TUNE_CMD_EN,
489 ESDHC_VEND_SPEC2);
490
491 reg = readl(host->ioaddr + ESDHC_MIX_CTRL);
492 reg |= ESDHC_MIX_CTRL_AUTO_TUNE_EN;
493 writel(reg, host->ioaddr + ESDHC_MIX_CTRL);
494 }
495
esdhc_readl_le(struct sdhci_host * host,int reg)496 static u32 esdhc_readl_le(struct sdhci_host *host, int reg)
497 {
498 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
499 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
500 u32 val = readl(host->ioaddr + reg);
501
502 if (unlikely(reg == SDHCI_PRESENT_STATE)) {
503 u32 fsl_prss = val;
504 /* save the least 20 bits */
505 val = fsl_prss & 0x000FFFFF;
506 /* move dat[0-3] bits */
507 val |= (fsl_prss & 0x0F000000) >> 4;
508 /* move cmd line bit */
509 val |= (fsl_prss & 0x00800000) << 1;
510 }
511
512 if (unlikely(reg == SDHCI_CAPABILITIES)) {
513 /* ignore bit[0-15] as it stores cap_1 register val for mx6sl */
514 if (imx_data->socdata->flags & ESDHC_FLAG_HAVE_CAP1)
515 val &= 0xffff0000;
516
517 /* In FSL esdhc IC module, only bit20 is used to indicate the
518 * ADMA2 capability of esdhc, but this bit is messed up on
519 * some SOCs (e.g. on MX25, MX35 this bit is set, but they
520 * don't actually support ADMA2). So set the BROKEN_ADMA
521 * quirk on MX25/35 platforms.
522 */
523
524 if (val & SDHCI_CAN_DO_ADMA1) {
525 val &= ~SDHCI_CAN_DO_ADMA1;
526 val |= SDHCI_CAN_DO_ADMA2;
527 }
528 }
529
530 if (unlikely(reg == SDHCI_CAPABILITIES_1)) {
531 if (esdhc_is_usdhc(imx_data)) {
532 if (imx_data->socdata->flags & ESDHC_FLAG_HAVE_CAP1)
533 val = readl(host->ioaddr + SDHCI_CAPABILITIES) & 0xFFFF;
534 else
535 /* imx6q/dl does not have cap_1 register, fake one */
536 val = SDHCI_SUPPORT_DDR50 | SDHCI_SUPPORT_SDR104
537 | SDHCI_SUPPORT_SDR50
538 | SDHCI_USE_SDR50_TUNING
539 | FIELD_PREP(SDHCI_RETUNING_MODE_MASK,
540 SDHCI_TUNING_MODE_3);
541
542 /*
543 * Do not advertise faster UHS modes if there are no
544 * pinctrl states for 100MHz/200MHz.
545 */
546 if (IS_ERR_OR_NULL(imx_data->pins_100mhz))
547 val &= ~(SDHCI_SUPPORT_SDR50 | SDHCI_SUPPORT_DDR50);
548 if (IS_ERR_OR_NULL(imx_data->pins_200mhz))
549 val &= ~(SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_HS400);
550 }
551 }
552
553 if (unlikely(reg == SDHCI_MAX_CURRENT) && esdhc_is_usdhc(imx_data)) {
554 val = 0;
555 val |= FIELD_PREP(SDHCI_MAX_CURRENT_330_MASK, 0xFF);
556 val |= FIELD_PREP(SDHCI_MAX_CURRENT_300_MASK, 0xFF);
557 val |= FIELD_PREP(SDHCI_MAX_CURRENT_180_MASK, 0xFF);
558 }
559
560 if (unlikely(reg == SDHCI_INT_STATUS)) {
561 if (val & ESDHC_INT_VENDOR_SPEC_DMA_ERR) {
562 val &= ~ESDHC_INT_VENDOR_SPEC_DMA_ERR;
563 val |= SDHCI_INT_ADMA_ERROR;
564 }
565
566 /*
567 * mask off the interrupt we get in response to the manually
568 * sent CMD12
569 */
570 if ((imx_data->multiblock_status == WAIT_FOR_INT) &&
571 ((val & SDHCI_INT_RESPONSE) == SDHCI_INT_RESPONSE)) {
572 val &= ~SDHCI_INT_RESPONSE;
573 writel(SDHCI_INT_RESPONSE, host->ioaddr +
574 SDHCI_INT_STATUS);
575 imx_data->multiblock_status = NO_CMD_PENDING;
576 }
577 }
578
579 return val;
580 }
581
esdhc_writel_le(struct sdhci_host * host,u32 val,int reg)582 static void esdhc_writel_le(struct sdhci_host *host, u32 val, int reg)
583 {
584 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
585 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
586 u32 data;
587
588 if (unlikely(reg == SDHCI_INT_ENABLE || reg == SDHCI_SIGNAL_ENABLE ||
589 reg == SDHCI_INT_STATUS)) {
590 if ((val & SDHCI_INT_CARD_INT) && !esdhc_is_usdhc(imx_data)) {
591 /*
592 * Clear and then set D3CD bit to avoid missing the
593 * card interrupt. This is an eSDHC controller problem
594 * so we need to apply the following workaround: clear
595 * and set D3CD bit will make eSDHC re-sample the card
596 * interrupt. In case a card interrupt was lost,
597 * re-sample it by the following steps.
598 */
599 data = readl(host->ioaddr + SDHCI_HOST_CONTROL);
600 data &= ~ESDHC_CTRL_D3CD;
601 writel(data, host->ioaddr + SDHCI_HOST_CONTROL);
602 data |= ESDHC_CTRL_D3CD;
603 writel(data, host->ioaddr + SDHCI_HOST_CONTROL);
604 }
605
606 if (val & SDHCI_INT_ADMA_ERROR) {
607 val &= ~SDHCI_INT_ADMA_ERROR;
608 val |= ESDHC_INT_VENDOR_SPEC_DMA_ERR;
609 }
610 }
611
612 if (unlikely((imx_data->socdata->flags & ESDHC_FLAG_MULTIBLK_NO_INT)
613 && (reg == SDHCI_INT_STATUS)
614 && (val & SDHCI_INT_DATA_END))) {
615 u32 v;
616 v = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
617 v &= ~ESDHC_VENDOR_SPEC_SDIO_QUIRK;
618 writel(v, host->ioaddr + ESDHC_VENDOR_SPEC);
619
620 if (imx_data->multiblock_status == MULTIBLK_IN_PROCESS)
621 {
622 /* send a manual CMD12 with RESPTYP=none */
623 data = MMC_STOP_TRANSMISSION << 24 |
624 SDHCI_CMD_ABORTCMD << 16;
625 writel(data, host->ioaddr + SDHCI_TRANSFER_MODE);
626 imx_data->multiblock_status = WAIT_FOR_INT;
627 }
628 }
629
630 writel(val, host->ioaddr + reg);
631 }
632
esdhc_readw_le(struct sdhci_host * host,int reg)633 static u16 esdhc_readw_le(struct sdhci_host *host, int reg)
634 {
635 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
636 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
637 u16 ret = 0;
638 u32 val;
639
640 if (unlikely(reg == SDHCI_HOST_VERSION)) {
641 reg ^= 2;
642 if (esdhc_is_usdhc(imx_data)) {
643 /*
644 * The usdhc register returns a wrong host version.
645 * Correct it here.
646 */
647 return SDHCI_SPEC_300;
648 }
649 }
650
651 if (unlikely(reg == SDHCI_HOST_CONTROL2)) {
652 val = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
653 if (val & ESDHC_VENDOR_SPEC_VSELECT)
654 ret |= SDHCI_CTRL_VDD_180;
655
656 if (esdhc_is_usdhc(imx_data)) {
657 if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING)
658 val = readl(host->ioaddr + ESDHC_MIX_CTRL);
659 else if (imx_data->socdata->flags & ESDHC_FLAG_STD_TUNING)
660 /* the std tuning bits is in ACMD12_ERR for imx6sl */
661 val = readl(host->ioaddr + SDHCI_AUTO_CMD_STATUS);
662 }
663
664 if (val & ESDHC_MIX_CTRL_EXE_TUNE)
665 ret |= SDHCI_CTRL_EXEC_TUNING;
666 if (val & ESDHC_MIX_CTRL_SMPCLK_SEL)
667 ret |= SDHCI_CTRL_TUNED_CLK;
668
669 ret &= ~SDHCI_CTRL_PRESET_VAL_ENABLE;
670
671 return ret;
672 }
673
674 if (unlikely(reg == SDHCI_TRANSFER_MODE)) {
675 if (esdhc_is_usdhc(imx_data)) {
676 u32 m = readl(host->ioaddr + ESDHC_MIX_CTRL);
677 ret = m & ESDHC_MIX_CTRL_SDHCI_MASK;
678 /* Swap AC23 bit */
679 if (m & ESDHC_MIX_CTRL_AC23EN) {
680 ret &= ~ESDHC_MIX_CTRL_AC23EN;
681 ret |= SDHCI_TRNS_AUTO_CMD23;
682 }
683 } else {
684 ret = readw(host->ioaddr + SDHCI_TRANSFER_MODE);
685 }
686
687 return ret;
688 }
689
690 return readw(host->ioaddr + reg);
691 }
692
esdhc_writew_le(struct sdhci_host * host,u16 val,int reg)693 static void esdhc_writew_le(struct sdhci_host *host, u16 val, int reg)
694 {
695 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
696 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
697 u32 new_val = 0;
698
699 switch (reg) {
700 case SDHCI_CLOCK_CONTROL:
701 new_val = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
702 if (val & SDHCI_CLOCK_CARD_EN)
703 new_val |= ESDHC_VENDOR_SPEC_FRC_SDCLK_ON;
704 else
705 new_val &= ~ESDHC_VENDOR_SPEC_FRC_SDCLK_ON;
706 writel(new_val, host->ioaddr + ESDHC_VENDOR_SPEC);
707 if (!(new_val & ESDHC_VENDOR_SPEC_FRC_SDCLK_ON))
708 esdhc_wait_for_card_clock_gate_off(host);
709 return;
710 case SDHCI_HOST_CONTROL2:
711 new_val = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
712 if (val & SDHCI_CTRL_VDD_180)
713 new_val |= ESDHC_VENDOR_SPEC_VSELECT;
714 else
715 new_val &= ~ESDHC_VENDOR_SPEC_VSELECT;
716 writel(new_val, host->ioaddr + ESDHC_VENDOR_SPEC);
717 if (imx_data->socdata->flags & ESDHC_FLAG_STD_TUNING) {
718 u32 v = readl(host->ioaddr + SDHCI_AUTO_CMD_STATUS);
719 u32 m = readl(host->ioaddr + ESDHC_MIX_CTRL);
720 if (val & SDHCI_CTRL_TUNED_CLK) {
721 v |= ESDHC_MIX_CTRL_SMPCLK_SEL;
722 } else {
723 v &= ~ESDHC_MIX_CTRL_SMPCLK_SEL;
724 m &= ~ESDHC_MIX_CTRL_FBCLK_SEL;
725 }
726
727 if (val & SDHCI_CTRL_EXEC_TUNING) {
728 v |= ESDHC_MIX_CTRL_EXE_TUNE;
729 m |= ESDHC_MIX_CTRL_FBCLK_SEL;
730 } else {
731 v &= ~ESDHC_MIX_CTRL_EXE_TUNE;
732 }
733
734 writel(v, host->ioaddr + SDHCI_AUTO_CMD_STATUS);
735 writel(m, host->ioaddr + ESDHC_MIX_CTRL);
736 }
737 return;
738 case SDHCI_TRANSFER_MODE:
739 if ((imx_data->socdata->flags & ESDHC_FLAG_MULTIBLK_NO_INT)
740 && (host->cmd->opcode == SD_IO_RW_EXTENDED)
741 && (host->cmd->data->blocks > 1)
742 && (host->cmd->data->flags & MMC_DATA_READ)) {
743 u32 v;
744 v = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
745 v |= ESDHC_VENDOR_SPEC_SDIO_QUIRK;
746 writel(v, host->ioaddr + ESDHC_VENDOR_SPEC);
747 }
748
749 if (esdhc_is_usdhc(imx_data)) {
750 u32 wml;
751 u32 m = readl(host->ioaddr + ESDHC_MIX_CTRL);
752 /* Swap AC23 bit */
753 if (val & SDHCI_TRNS_AUTO_CMD23) {
754 val &= ~SDHCI_TRNS_AUTO_CMD23;
755 val |= ESDHC_MIX_CTRL_AC23EN;
756 }
757 m = val | (m & ~ESDHC_MIX_CTRL_SDHCI_MASK);
758 writel(m, host->ioaddr + ESDHC_MIX_CTRL);
759
760 /* Set watermark levels for PIO access to maximum value
761 * (128 words) to accommodate full 512 bytes buffer.
762 * For DMA access restore the levels to default value.
763 */
764 m = readl(host->ioaddr + ESDHC_WTMK_LVL);
765 if (val & SDHCI_TRNS_DMA) {
766 wml = ESDHC_WTMK_LVL_WML_VAL_DEF;
767 } else {
768 u8 ctrl;
769 wml = ESDHC_WTMK_LVL_WML_VAL_MAX;
770
771 /*
772 * Since already disable DMA mode, so also need
773 * to clear the DMASEL. Otherwise, for standard
774 * tuning, when send tuning command, usdhc will
775 * still prefetch the ADMA script from wrong
776 * DMA address, then we will see IOMMU report
777 * some error which show lack of TLB mapping.
778 */
779 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
780 ctrl &= ~SDHCI_CTRL_DMA_MASK;
781 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
782 }
783 m &= ~(ESDHC_WTMK_LVL_RD_WML_MASK |
784 ESDHC_WTMK_LVL_WR_WML_MASK);
785 m |= (wml << ESDHC_WTMK_LVL_RD_WML_SHIFT) |
786 (wml << ESDHC_WTMK_LVL_WR_WML_SHIFT);
787 writel(m, host->ioaddr + ESDHC_WTMK_LVL);
788 } else {
789 /*
790 * Postpone this write, we must do it together with a
791 * command write that is down below.
792 */
793 imx_data->scratchpad = val;
794 }
795 return;
796 case SDHCI_COMMAND:
797 if (host->cmd->opcode == MMC_STOP_TRANSMISSION)
798 val |= SDHCI_CMD_ABORTCMD;
799
800 if ((host->cmd->opcode == MMC_SET_BLOCK_COUNT) &&
801 (imx_data->socdata->flags & ESDHC_FLAG_MULTIBLK_NO_INT))
802 imx_data->multiblock_status = MULTIBLK_IN_PROCESS;
803
804 if (esdhc_is_usdhc(imx_data))
805 writel(val << 16,
806 host->ioaddr + SDHCI_TRANSFER_MODE);
807 else
808 writel(val << 16 | imx_data->scratchpad,
809 host->ioaddr + SDHCI_TRANSFER_MODE);
810 return;
811 case SDHCI_BLOCK_SIZE:
812 val &= ~SDHCI_MAKE_BLKSZ(0x7, 0);
813 break;
814 }
815 esdhc_clrset_le(host, 0xffff, val, reg);
816 }
817
esdhc_readb_le(struct sdhci_host * host,int reg)818 static u8 esdhc_readb_le(struct sdhci_host *host, int reg)
819 {
820 u8 ret;
821 u32 val;
822
823 switch (reg) {
824 case SDHCI_HOST_CONTROL:
825 val = readl(host->ioaddr + reg);
826
827 ret = val & SDHCI_CTRL_LED;
828 ret |= (val >> 5) & SDHCI_CTRL_DMA_MASK;
829 ret |= (val & ESDHC_CTRL_4BITBUS);
830 ret |= (val & ESDHC_CTRL_8BITBUS) << 3;
831 return ret;
832 }
833
834 return readb(host->ioaddr + reg);
835 }
836
esdhc_writeb_le(struct sdhci_host * host,u8 val,int reg)837 static void esdhc_writeb_le(struct sdhci_host *host, u8 val, int reg)
838 {
839 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
840 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
841 u32 new_val = 0;
842 u32 mask;
843
844 switch (reg) {
845 case SDHCI_POWER_CONTROL:
846 /*
847 * FSL put some DMA bits here
848 * If your board has a regulator, code should be here
849 */
850 return;
851 case SDHCI_HOST_CONTROL:
852 /* FSL messed up here, so we need to manually compose it. */
853 new_val = val & SDHCI_CTRL_LED;
854 /* ensure the endianness */
855 new_val |= ESDHC_HOST_CONTROL_LE;
856 /* bits 8&9 are reserved on mx25 */
857 if (!is_imx25_esdhc(imx_data)) {
858 /* DMA mode bits are shifted */
859 new_val |= (val & SDHCI_CTRL_DMA_MASK) << 5;
860 }
861
862 /*
863 * Do not touch buswidth bits here. This is done in
864 * esdhc_pltfm_bus_width.
865 * Do not touch the D3CD bit either which is used for the
866 * SDIO interrupt erratum workaround.
867 */
868 mask = 0xffff & ~(ESDHC_CTRL_BUSWIDTH_MASK | ESDHC_CTRL_D3CD);
869
870 esdhc_clrset_le(host, mask, new_val, reg);
871 return;
872 case SDHCI_SOFTWARE_RESET:
873 if (val & SDHCI_RESET_DATA)
874 new_val = readl(host->ioaddr + SDHCI_HOST_CONTROL);
875 break;
876 }
877 esdhc_clrset_le(host, 0xff, val, reg);
878
879 if (reg == SDHCI_SOFTWARE_RESET) {
880 if (val & SDHCI_RESET_ALL) {
881 /*
882 * The esdhc has a design violation to SDHC spec which
883 * tells that software reset should not affect card
884 * detection circuit. But esdhc clears its SYSCTL
885 * register bits [0..2] during the software reset. This
886 * will stop those clocks that card detection circuit
887 * relies on. To work around it, we turn the clocks on
888 * back to keep card detection circuit functional.
889 */
890 esdhc_clrset_le(host, 0x7, 0x7, ESDHC_SYSTEM_CONTROL);
891 /*
892 * The reset on usdhc fails to clear MIX_CTRL register.
893 * Do it manually here.
894 */
895 if (esdhc_is_usdhc(imx_data)) {
896 /*
897 * the tuning bits should be kept during reset
898 */
899 new_val = readl(host->ioaddr + ESDHC_MIX_CTRL);
900 writel(new_val & ESDHC_MIX_CTRL_TUNING_MASK,
901 host->ioaddr + ESDHC_MIX_CTRL);
902 imx_data->is_ddr = 0;
903 }
904 } else if (val & SDHCI_RESET_DATA) {
905 /*
906 * The eSDHC DAT line software reset clears at least the
907 * data transfer width on i.MX25, so make sure that the
908 * Host Control register is unaffected.
909 */
910 esdhc_clrset_le(host, 0xff, new_val,
911 SDHCI_HOST_CONTROL);
912 }
913 }
914 }
915
esdhc_pltfm_get_max_clock(struct sdhci_host * host)916 static unsigned int esdhc_pltfm_get_max_clock(struct sdhci_host *host)
917 {
918 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
919
920 return pltfm_host->clock;
921 }
922
esdhc_pltfm_get_min_clock(struct sdhci_host * host)923 static unsigned int esdhc_pltfm_get_min_clock(struct sdhci_host *host)
924 {
925 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
926
927 return pltfm_host->clock / 256 / 16;
928 }
929
esdhc_pltfm_set_clock(struct sdhci_host * host,unsigned int clock)930 static inline void esdhc_pltfm_set_clock(struct sdhci_host *host,
931 unsigned int clock)
932 {
933 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
934 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
935 unsigned int host_clock = pltfm_host->clock;
936 int ddr_pre_div = imx_data->is_ddr ? 2 : 1;
937 int pre_div = 1;
938 int div = 1;
939 int ret;
940 u32 temp, val;
941
942 if (esdhc_is_usdhc(imx_data)) {
943 val = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
944 writel(val & ~ESDHC_VENDOR_SPEC_FRC_SDCLK_ON,
945 host->ioaddr + ESDHC_VENDOR_SPEC);
946 esdhc_wait_for_card_clock_gate_off(host);
947 }
948
949 if (clock == 0) {
950 host->mmc->actual_clock = 0;
951 return;
952 }
953
954 /* For i.MX53 eSDHCv3, SYSCTL.SDCLKFS may not be set to 0. */
955 if (is_imx53_esdhc(imx_data)) {
956 /*
957 * According to the i.MX53 reference manual, if DLLCTRL[10] can
958 * be set, then the controller is eSDHCv3, else it is eSDHCv2.
959 */
960 val = readl(host->ioaddr + ESDHC_DLL_CTRL);
961 writel(val | BIT(10), host->ioaddr + ESDHC_DLL_CTRL);
962 temp = readl(host->ioaddr + ESDHC_DLL_CTRL);
963 writel(val, host->ioaddr + ESDHC_DLL_CTRL);
964 if (temp & BIT(10))
965 pre_div = 2;
966 }
967
968 temp = sdhci_readl(host, ESDHC_SYSTEM_CONTROL);
969 temp &= ~(ESDHC_CLOCK_IPGEN | ESDHC_CLOCK_HCKEN | ESDHC_CLOCK_PEREN
970 | ESDHC_CLOCK_MASK);
971 sdhci_writel(host, temp, ESDHC_SYSTEM_CONTROL);
972
973 if ((imx_data->socdata->flags & ESDHC_FLAG_ERR010450) &&
974 (!(host->quirks2 & SDHCI_QUIRK2_NO_1_8_V))) {
975 unsigned int max_clock;
976
977 max_clock = imx_data->is_ddr ? 45000000 : 150000000;
978
979 clock = min(clock, max_clock);
980 }
981
982 while (host_clock / (16 * pre_div * ddr_pre_div) > clock &&
983 pre_div < 256)
984 pre_div *= 2;
985
986 while (host_clock / (div * pre_div * ddr_pre_div) > clock && div < 16)
987 div++;
988
989 host->mmc->actual_clock = host_clock / (div * pre_div * ddr_pre_div);
990 dev_dbg(mmc_dev(host->mmc), "desired SD clock: %d, actual: %d\n",
991 clock, host->mmc->actual_clock);
992
993 pre_div >>= 1;
994 div--;
995
996 temp = sdhci_readl(host, ESDHC_SYSTEM_CONTROL);
997 temp |= (ESDHC_CLOCK_IPGEN | ESDHC_CLOCK_HCKEN | ESDHC_CLOCK_PEREN
998 | (div << ESDHC_DIVIDER_SHIFT)
999 | (pre_div << ESDHC_PREDIV_SHIFT));
1000 sdhci_writel(host, temp, ESDHC_SYSTEM_CONTROL);
1001
1002 /* need to wait the bit 3 of the PRSSTAT to be set, make sure card clock is stable */
1003 ret = readl_poll_timeout(host->ioaddr + ESDHC_PRSSTAT, temp,
1004 (temp & ESDHC_CLOCK_STABLE), 2, 100);
1005 if (ret == -ETIMEDOUT)
1006 dev_warn(mmc_dev(host->mmc), "card clock still not stable in 100us!.\n");
1007
1008 if (esdhc_is_usdhc(imx_data)) {
1009 val = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
1010 writel(val | ESDHC_VENDOR_SPEC_FRC_SDCLK_ON,
1011 host->ioaddr + ESDHC_VENDOR_SPEC);
1012 }
1013
1014 }
1015
esdhc_pltfm_get_ro(struct sdhci_host * host)1016 static unsigned int esdhc_pltfm_get_ro(struct sdhci_host *host)
1017 {
1018 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1019 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
1020 struct esdhc_platform_data *boarddata = &imx_data->boarddata;
1021
1022 switch (boarddata->wp_type) {
1023 case ESDHC_WP_GPIO:
1024 return mmc_gpio_get_ro(host->mmc);
1025 case ESDHC_WP_CONTROLLER:
1026 return !(readl(host->ioaddr + SDHCI_PRESENT_STATE) &
1027 SDHCI_WRITE_PROTECT);
1028 case ESDHC_WP_NONE:
1029 break;
1030 }
1031
1032 return -ENOSYS;
1033 }
1034
esdhc_pltfm_set_bus_width(struct sdhci_host * host,int width)1035 static void esdhc_pltfm_set_bus_width(struct sdhci_host *host, int width)
1036 {
1037 u32 ctrl;
1038
1039 switch (width) {
1040 case MMC_BUS_WIDTH_8:
1041 ctrl = ESDHC_CTRL_8BITBUS;
1042 break;
1043 case MMC_BUS_WIDTH_4:
1044 ctrl = ESDHC_CTRL_4BITBUS;
1045 break;
1046 default:
1047 ctrl = 0;
1048 break;
1049 }
1050
1051 esdhc_clrset_le(host, ESDHC_CTRL_BUSWIDTH_MASK, ctrl,
1052 SDHCI_HOST_CONTROL);
1053 }
1054
esdhc_reset_tuning(struct sdhci_host * host)1055 static void esdhc_reset_tuning(struct sdhci_host *host)
1056 {
1057 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1058 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
1059 u32 ctrl;
1060 int ret;
1061
1062 /* Reset the tuning circuit */
1063 if (esdhc_is_usdhc(imx_data)) {
1064 ctrl = readl(host->ioaddr + ESDHC_MIX_CTRL);
1065 ctrl &= ~ESDHC_MIX_CTRL_AUTO_TUNE_EN;
1066 if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING) {
1067 ctrl &= ~ESDHC_MIX_CTRL_SMPCLK_SEL;
1068 ctrl &= ~ESDHC_MIX_CTRL_FBCLK_SEL;
1069 writel(ctrl, host->ioaddr + ESDHC_MIX_CTRL);
1070 writel(0, host->ioaddr + ESDHC_TUNE_CTRL_STATUS);
1071 } else if (imx_data->socdata->flags & ESDHC_FLAG_STD_TUNING) {
1072 writel(ctrl, host->ioaddr + ESDHC_MIX_CTRL);
1073 ctrl = readl(host->ioaddr + SDHCI_AUTO_CMD_STATUS);
1074 ctrl &= ~ESDHC_MIX_CTRL_SMPCLK_SEL;
1075 ctrl &= ~ESDHC_MIX_CTRL_EXE_TUNE;
1076 writel(ctrl, host->ioaddr + SDHCI_AUTO_CMD_STATUS);
1077 /* Make sure ESDHC_MIX_CTRL_EXE_TUNE cleared */
1078 ret = readl_poll_timeout(host->ioaddr + SDHCI_AUTO_CMD_STATUS,
1079 ctrl, !(ctrl & ESDHC_MIX_CTRL_EXE_TUNE), 1, 50);
1080 if (ret == -ETIMEDOUT)
1081 dev_warn(mmc_dev(host->mmc),
1082 "Warning! clear execute tuning bit failed\n");
1083 /*
1084 * SDHCI_INT_DATA_AVAIL is W1C bit, set this bit will clear the
1085 * usdhc IP internal logic flag execute_tuning_with_clr_buf, which
1086 * will finally make sure the normal data transfer logic correct.
1087 */
1088 ctrl = readl(host->ioaddr + SDHCI_INT_STATUS);
1089 ctrl |= SDHCI_INT_DATA_AVAIL;
1090 writel(ctrl, host->ioaddr + SDHCI_INT_STATUS);
1091 }
1092 }
1093 }
1094
usdhc_init_card(struct mmc_host * mmc,struct mmc_card * card)1095 static void usdhc_init_card(struct mmc_host *mmc, struct mmc_card *card)
1096 {
1097 struct sdhci_host *host = mmc_priv(mmc);
1098 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1099 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
1100
1101 imx_data->init_card_type = card->type;
1102 }
1103
usdhc_execute_tuning(struct mmc_host * mmc,u32 opcode)1104 static int usdhc_execute_tuning(struct mmc_host *mmc, u32 opcode)
1105 {
1106 struct sdhci_host *host = mmc_priv(mmc);
1107 int err;
1108
1109 /*
1110 * i.MX uSDHC internally already uses a fixed optimized timing for
1111 * DDR50, normally does not require tuning for DDR50 mode.
1112 */
1113 if (host->timing == MMC_TIMING_UHS_DDR50)
1114 return 0;
1115
1116 /*
1117 * Reset tuning circuit logic. If not, the previous tuning result
1118 * will impact current tuning, make current tuning can't set the
1119 * correct delay cell.
1120 */
1121 esdhc_reset_tuning(host);
1122 err = sdhci_execute_tuning(mmc, opcode);
1123 /* If tuning done, enable auto tuning */
1124 if (!err && !host->tuning_err)
1125 usdhc_auto_tuning_mode_sel_and_en(host);
1126
1127 return err;
1128 }
1129
esdhc_prepare_tuning(struct sdhci_host * host,u32 val)1130 static void esdhc_prepare_tuning(struct sdhci_host *host, u32 val)
1131 {
1132 u32 reg;
1133 u8 sw_rst;
1134 int ret;
1135
1136 /* FIXME: delay a bit for card to be ready for next tuning due to errors */
1137 mdelay(1);
1138
1139 /* IC suggest to reset USDHC before every tuning command */
1140 esdhc_clrset_le(host, 0xff, SDHCI_RESET_ALL, SDHCI_SOFTWARE_RESET);
1141 ret = readb_poll_timeout(host->ioaddr + SDHCI_SOFTWARE_RESET, sw_rst,
1142 !(sw_rst & SDHCI_RESET_ALL), 10, 100);
1143 if (ret == -ETIMEDOUT)
1144 dev_warn(mmc_dev(host->mmc),
1145 "warning! RESET_ALL never complete before sending tuning command\n");
1146
1147 reg = readl(host->ioaddr + ESDHC_MIX_CTRL);
1148 reg |= ESDHC_MIX_CTRL_EXE_TUNE | ESDHC_MIX_CTRL_SMPCLK_SEL |
1149 ESDHC_MIX_CTRL_FBCLK_SEL;
1150 writel(reg, host->ioaddr + ESDHC_MIX_CTRL);
1151 writel(val << 8, host->ioaddr + ESDHC_TUNE_CTRL_STATUS);
1152 dev_dbg(mmc_dev(host->mmc),
1153 "tuning with delay 0x%x ESDHC_TUNE_CTRL_STATUS 0x%x\n",
1154 val, readl(host->ioaddr + ESDHC_TUNE_CTRL_STATUS));
1155 }
1156
esdhc_post_tuning(struct sdhci_host * host)1157 static void esdhc_post_tuning(struct sdhci_host *host)
1158 {
1159 u32 reg;
1160
1161 reg = readl(host->ioaddr + ESDHC_MIX_CTRL);
1162 reg &= ~ESDHC_MIX_CTRL_EXE_TUNE;
1163 writel(reg, host->ioaddr + ESDHC_MIX_CTRL);
1164 }
1165
1166 /*
1167 * find the largest pass window, and use the average delay of this
1168 * largest window to get the best timing.
1169 */
esdhc_executing_tuning(struct sdhci_host * host,u32 opcode)1170 static int esdhc_executing_tuning(struct sdhci_host *host, u32 opcode)
1171 {
1172 int min, max, avg, ret;
1173 int win_length, target_min, target_max, target_win_length;
1174
1175 min = ESDHC_TUNE_CTRL_MIN;
1176 max = ESDHC_TUNE_CTRL_MIN;
1177 target_win_length = 0;
1178 while (max < ESDHC_TUNE_CTRL_MAX) {
1179 /* find the mininum delay first which can pass tuning */
1180 while (min < ESDHC_TUNE_CTRL_MAX) {
1181 esdhc_prepare_tuning(host, min);
1182 if (!mmc_send_tuning(host->mmc, opcode, NULL))
1183 break;
1184 min += ESDHC_TUNE_CTRL_STEP;
1185 }
1186
1187 /* find the maxinum delay which can not pass tuning */
1188 max = min + ESDHC_TUNE_CTRL_STEP;
1189 while (max < ESDHC_TUNE_CTRL_MAX) {
1190 esdhc_prepare_tuning(host, max);
1191 if (mmc_send_tuning(host->mmc, opcode, NULL)) {
1192 max -= ESDHC_TUNE_CTRL_STEP;
1193 break;
1194 }
1195 max += ESDHC_TUNE_CTRL_STEP;
1196 }
1197
1198 win_length = max - min + 1;
1199 /* get the largest pass window */
1200 if (win_length > target_win_length) {
1201 target_win_length = win_length;
1202 target_min = min;
1203 target_max = max;
1204 }
1205
1206 /* continue to find the next pass window */
1207 min = max + ESDHC_TUNE_CTRL_STEP;
1208 }
1209
1210 /* use average delay to get the best timing */
1211 avg = (target_min + target_max) / 2;
1212 esdhc_prepare_tuning(host, avg);
1213 ret = mmc_send_tuning(host->mmc, opcode, NULL);
1214 esdhc_post_tuning(host);
1215
1216 dev_dbg(mmc_dev(host->mmc), "tuning %s at 0x%x ret %d\n",
1217 ret ? "failed" : "passed", avg, ret);
1218
1219 return ret;
1220 }
1221
esdhc_hs400_enhanced_strobe(struct mmc_host * mmc,struct mmc_ios * ios)1222 static void esdhc_hs400_enhanced_strobe(struct mmc_host *mmc, struct mmc_ios *ios)
1223 {
1224 struct sdhci_host *host = mmc_priv(mmc);
1225 u32 m;
1226
1227 m = readl(host->ioaddr + ESDHC_MIX_CTRL);
1228 if (ios->enhanced_strobe)
1229 m |= ESDHC_MIX_CTRL_HS400_ES_EN;
1230 else
1231 m &= ~ESDHC_MIX_CTRL_HS400_ES_EN;
1232 writel(m, host->ioaddr + ESDHC_MIX_CTRL);
1233 }
1234
esdhc_change_pinstate(struct sdhci_host * host,unsigned int uhs)1235 static int esdhc_change_pinstate(struct sdhci_host *host,
1236 unsigned int uhs)
1237 {
1238 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1239 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
1240 struct pinctrl_state *pinctrl;
1241
1242 dev_dbg(mmc_dev(host->mmc), "change pinctrl state for uhs %d\n", uhs);
1243
1244 if (IS_ERR(imx_data->pinctrl) ||
1245 IS_ERR(imx_data->pins_100mhz) ||
1246 IS_ERR(imx_data->pins_200mhz))
1247 return -EINVAL;
1248
1249 switch (uhs) {
1250 case MMC_TIMING_UHS_SDR50:
1251 case MMC_TIMING_UHS_DDR50:
1252 pinctrl = imx_data->pins_100mhz;
1253 break;
1254 case MMC_TIMING_UHS_SDR104:
1255 case MMC_TIMING_MMC_HS200:
1256 case MMC_TIMING_MMC_HS400:
1257 pinctrl = imx_data->pins_200mhz;
1258 break;
1259 default:
1260 /* back to default state for other legacy timing */
1261 return pinctrl_select_default_state(mmc_dev(host->mmc));
1262 }
1263
1264 return pinctrl_select_state(imx_data->pinctrl, pinctrl);
1265 }
1266
1267 /*
1268 * For HS400 eMMC, there is a data_strobe line. This signal is generated
1269 * by the device and used for data output and CRC status response output
1270 * in HS400 mode. The frequency of this signal follows the frequency of
1271 * CLK generated by host. The host receives the data which is aligned to the
1272 * edge of data_strobe line. Due to the time delay between CLK line and
1273 * data_strobe line, if the delay time is larger than one clock cycle,
1274 * then CLK and data_strobe line will be misaligned, read error shows up.
1275 */
esdhc_set_strobe_dll(struct sdhci_host * host)1276 static void esdhc_set_strobe_dll(struct sdhci_host *host)
1277 {
1278 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1279 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
1280 u32 strobe_delay;
1281 u32 v;
1282 int ret;
1283
1284 /* disable clock before enabling strobe dll */
1285 writel(readl(host->ioaddr + ESDHC_VENDOR_SPEC) &
1286 ~ESDHC_VENDOR_SPEC_FRC_SDCLK_ON,
1287 host->ioaddr + ESDHC_VENDOR_SPEC);
1288 esdhc_wait_for_card_clock_gate_off(host);
1289
1290 /* force a reset on strobe dll */
1291 writel(ESDHC_STROBE_DLL_CTRL_RESET,
1292 host->ioaddr + ESDHC_STROBE_DLL_CTRL);
1293 /* clear the reset bit on strobe dll before any setting */
1294 writel(0, host->ioaddr + ESDHC_STROBE_DLL_CTRL);
1295
1296 /*
1297 * enable strobe dll ctrl and adjust the delay target
1298 * for the uSDHC loopback read clock
1299 */
1300 if (imx_data->boarddata.strobe_dll_delay_target)
1301 strobe_delay = imx_data->boarddata.strobe_dll_delay_target;
1302 else
1303 strobe_delay = ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_DEFAULT;
1304 v = ESDHC_STROBE_DLL_CTRL_ENABLE |
1305 ESDHC_STROBE_DLL_CTRL_SLV_UPDATE_INT_DEFAULT |
1306 (strobe_delay << ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_SHIFT);
1307 writel(v, host->ioaddr + ESDHC_STROBE_DLL_CTRL);
1308
1309 /* wait max 50us to get the REF/SLV lock */
1310 ret = readl_poll_timeout(host->ioaddr + ESDHC_STROBE_DLL_STATUS, v,
1311 ((v & ESDHC_STROBE_DLL_STS_REF_LOCK) && (v & ESDHC_STROBE_DLL_STS_SLV_LOCK)), 1, 50);
1312 if (ret == -ETIMEDOUT)
1313 dev_warn(mmc_dev(host->mmc),
1314 "warning! HS400 strobe DLL status REF/SLV not lock in 50us, STROBE DLL status is %x!\n", v);
1315 }
1316
esdhc_set_uhs_signaling(struct sdhci_host * host,unsigned timing)1317 static void esdhc_set_uhs_signaling(struct sdhci_host *host, unsigned timing)
1318 {
1319 u32 m;
1320 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1321 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
1322 struct esdhc_platform_data *boarddata = &imx_data->boarddata;
1323
1324 /* disable ddr mode and disable HS400 mode */
1325 m = readl(host->ioaddr + ESDHC_MIX_CTRL);
1326 m &= ~(ESDHC_MIX_CTRL_DDREN | ESDHC_MIX_CTRL_HS400_EN);
1327 imx_data->is_ddr = 0;
1328
1329 switch (timing) {
1330 case MMC_TIMING_UHS_SDR12:
1331 case MMC_TIMING_UHS_SDR25:
1332 case MMC_TIMING_UHS_SDR50:
1333 case MMC_TIMING_UHS_SDR104:
1334 case MMC_TIMING_MMC_HS:
1335 case MMC_TIMING_MMC_HS200:
1336 writel(m, host->ioaddr + ESDHC_MIX_CTRL);
1337 break;
1338 case MMC_TIMING_UHS_DDR50:
1339 case MMC_TIMING_MMC_DDR52:
1340 m |= ESDHC_MIX_CTRL_DDREN;
1341 writel(m, host->ioaddr + ESDHC_MIX_CTRL);
1342 imx_data->is_ddr = 1;
1343 if (boarddata->delay_line) {
1344 u32 v;
1345 v = boarddata->delay_line <<
1346 ESDHC_DLL_OVERRIDE_VAL_SHIFT |
1347 (1 << ESDHC_DLL_OVERRIDE_EN_SHIFT);
1348 if (is_imx53_esdhc(imx_data))
1349 v <<= 1;
1350 writel(v, host->ioaddr + ESDHC_DLL_CTRL);
1351 }
1352 break;
1353 case MMC_TIMING_MMC_HS400:
1354 m |= ESDHC_MIX_CTRL_DDREN | ESDHC_MIX_CTRL_HS400_EN;
1355 writel(m, host->ioaddr + ESDHC_MIX_CTRL);
1356 imx_data->is_ddr = 1;
1357 /* update clock after enable DDR for strobe DLL lock */
1358 host->ops->set_clock(host, host->clock);
1359 esdhc_set_strobe_dll(host);
1360 break;
1361 case MMC_TIMING_LEGACY:
1362 default:
1363 esdhc_reset_tuning(host);
1364 break;
1365 }
1366
1367 esdhc_change_pinstate(host, timing);
1368 }
1369
esdhc_reset(struct sdhci_host * host,u8 mask)1370 static void esdhc_reset(struct sdhci_host *host, u8 mask)
1371 {
1372 sdhci_and_cqhci_reset(host, mask);
1373
1374 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
1375 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
1376 }
1377
esdhc_get_max_timeout_count(struct sdhci_host * host)1378 static unsigned int esdhc_get_max_timeout_count(struct sdhci_host *host)
1379 {
1380 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1381 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
1382
1383 /* Doc Erratum: the uSDHC actual maximum timeout count is 1 << 29 */
1384 return esdhc_is_usdhc(imx_data) ? 1 << 29 : 1 << 27;
1385 }
1386
esdhc_set_timeout(struct sdhci_host * host,struct mmc_command * cmd)1387 static void esdhc_set_timeout(struct sdhci_host *host, struct mmc_command *cmd)
1388 {
1389 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1390 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
1391
1392 /* use maximum timeout counter */
1393 esdhc_clrset_le(host, ESDHC_SYS_CTRL_DTOCV_MASK,
1394 esdhc_is_usdhc(imx_data) ? 0xF : 0xE,
1395 SDHCI_TIMEOUT_CONTROL);
1396 }
1397
esdhc_cqhci_irq(struct sdhci_host * host,u32 intmask)1398 static u32 esdhc_cqhci_irq(struct sdhci_host *host, u32 intmask)
1399 {
1400 int cmd_error = 0;
1401 int data_error = 0;
1402
1403 if (!sdhci_cqe_irq(host, intmask, &cmd_error, &data_error))
1404 return intmask;
1405
1406 cqhci_irq(host->mmc, intmask, cmd_error, data_error);
1407
1408 return 0;
1409 }
1410
1411 static struct sdhci_ops sdhci_esdhc_ops = {
1412 .read_l = esdhc_readl_le,
1413 .read_w = esdhc_readw_le,
1414 .read_b = esdhc_readb_le,
1415 .write_l = esdhc_writel_le,
1416 .write_w = esdhc_writew_le,
1417 .write_b = esdhc_writeb_le,
1418 .set_clock = esdhc_pltfm_set_clock,
1419 .get_max_clock = esdhc_pltfm_get_max_clock,
1420 .get_min_clock = esdhc_pltfm_get_min_clock,
1421 .get_max_timeout_count = esdhc_get_max_timeout_count,
1422 .get_ro = esdhc_pltfm_get_ro,
1423 .set_timeout = esdhc_set_timeout,
1424 .set_bus_width = esdhc_pltfm_set_bus_width,
1425 .set_uhs_signaling = esdhc_set_uhs_signaling,
1426 .reset = esdhc_reset,
1427 .irq = esdhc_cqhci_irq,
1428 .dump_vendor_regs = esdhc_dump_debug_regs,
1429 };
1430
1431 static const struct sdhci_pltfm_data sdhci_esdhc_imx_pdata = {
1432 .quirks = ESDHC_DEFAULT_QUIRKS | SDHCI_QUIRK_NO_HISPD_BIT
1433 | SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC
1434 | SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC
1435 | SDHCI_QUIRK_BROKEN_CARD_DETECTION,
1436 .ops = &sdhci_esdhc_ops,
1437 };
1438
sdhci_esdhc_imx_hwinit(struct sdhci_host * host)1439 static void sdhci_esdhc_imx_hwinit(struct sdhci_host *host)
1440 {
1441 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1442 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
1443 struct cqhci_host *cq_host = host->mmc->cqe_private;
1444 u32 tmp;
1445
1446 if (esdhc_is_usdhc(imx_data)) {
1447 /*
1448 * The imx6q ROM code will change the default watermark
1449 * level setting to something insane. Change it back here.
1450 */
1451 writel(ESDHC_WTMK_DEFAULT_VAL, host->ioaddr + ESDHC_WTMK_LVL);
1452
1453 /*
1454 * ROM code will change the bit burst_length_enable setting
1455 * to zero if this usdhc is chosen to boot system. Change
1456 * it back here, otherwise it will impact the performance a
1457 * lot. This bit is used to enable/disable the burst length
1458 * for the external AHB2AXI bridge. It's useful especially
1459 * for INCR transfer because without burst length indicator,
1460 * the AHB2AXI bridge does not know the burst length in
1461 * advance. And without burst length indicator, AHB INCR
1462 * transfer can only be converted to singles on the AXI side.
1463 */
1464 writel(readl(host->ioaddr + SDHCI_HOST_CONTROL)
1465 | ESDHC_BURST_LEN_EN_INCR,
1466 host->ioaddr + SDHCI_HOST_CONTROL);
1467
1468 /*
1469 * erratum ESDHC_FLAG_ERR004536 fix for MX6Q TO1.2 and MX6DL
1470 * TO1.1, it's harmless for MX6SL
1471 */
1472 if (!(imx_data->socdata->flags & ESDHC_FLAG_SKIP_ERR004536)) {
1473 writel(readl(host->ioaddr + 0x6c) & ~BIT(7),
1474 host->ioaddr + 0x6c);
1475 }
1476
1477 /* disable DLL_CTRL delay line settings */
1478 writel(0x0, host->ioaddr + ESDHC_DLL_CTRL);
1479
1480 /*
1481 * For the case of command with busy, if set the bit
1482 * ESDHC_VEND_SPEC2_EN_BUSY_IRQ, USDHC will generate a
1483 * transfer complete interrupt when busy is deasserted.
1484 * When CQHCI use DCMD to send a CMD need R1b respons,
1485 * CQHCI require to set ESDHC_VEND_SPEC2_EN_BUSY_IRQ,
1486 * otherwise DCMD will always meet timeout waiting for
1487 * hardware interrupt issue.
1488 */
1489 if (imx_data->socdata->flags & ESDHC_FLAG_CQHCI) {
1490 tmp = readl(host->ioaddr + ESDHC_VEND_SPEC2);
1491 tmp |= ESDHC_VEND_SPEC2_EN_BUSY_IRQ;
1492 writel(tmp, host->ioaddr + ESDHC_VEND_SPEC2);
1493
1494 host->quirks &= ~SDHCI_QUIRK_NO_BUSY_IRQ;
1495 }
1496
1497 if (imx_data->socdata->flags & ESDHC_FLAG_STD_TUNING) {
1498 tmp = readl(host->ioaddr + ESDHC_TUNING_CTRL);
1499 tmp |= ESDHC_STD_TUNING_EN;
1500
1501 /*
1502 * ROM code or bootloader may config the start tap
1503 * and step, unmask them first.
1504 */
1505 tmp &= ~(ESDHC_TUNING_START_TAP_MASK | ESDHC_TUNING_STEP_MASK);
1506 if (imx_data->boarddata.tuning_start_tap)
1507 tmp |= imx_data->boarddata.tuning_start_tap;
1508 else
1509 tmp |= ESDHC_TUNING_START_TAP_DEFAULT;
1510
1511 if (imx_data->boarddata.tuning_step) {
1512 tmp |= imx_data->boarddata.tuning_step
1513 << ESDHC_TUNING_STEP_SHIFT;
1514 } else {
1515 tmp |= ESDHC_TUNING_STEP_DEFAULT
1516 << ESDHC_TUNING_STEP_SHIFT;
1517 }
1518
1519 /* Disable the CMD CRC check for tuning, if not, need to
1520 * add some delay after every tuning command, because
1521 * hardware standard tuning logic will directly go to next
1522 * step once it detect the CMD CRC error, will not wait for
1523 * the card side to finally send out the tuning data, trigger
1524 * the buffer read ready interrupt immediately. If usdhc send
1525 * the next tuning command some eMMC card will stuck, can't
1526 * response, block the tuning procedure or the first command
1527 * after the whole tuning procedure always can't get any response.
1528 */
1529 tmp |= ESDHC_TUNING_CMD_CRC_CHECK_DISABLE;
1530 writel(tmp, host->ioaddr + ESDHC_TUNING_CTRL);
1531 } else if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING) {
1532 /*
1533 * ESDHC_STD_TUNING_EN may be configed in bootloader
1534 * or ROM code, so clear this bit here to make sure
1535 * the manual tuning can work.
1536 */
1537 tmp = readl(host->ioaddr + ESDHC_TUNING_CTRL);
1538 tmp &= ~ESDHC_STD_TUNING_EN;
1539 writel(tmp, host->ioaddr + ESDHC_TUNING_CTRL);
1540 }
1541
1542 /*
1543 * On i.MX8MM, we are running Dual Linux OS, with 1st Linux using SD Card
1544 * as rootfs storage, 2nd Linux using eMMC as rootfs storage. We let
1545 * the 1st linux configure power/clock for the 2nd Linux.
1546 *
1547 * When the 2nd Linux is booting into rootfs stage, we let the 1st Linux
1548 * to destroy the 2nd linux, then restart the 2nd linux, we met SDHCI dump.
1549 * After we clear the pending interrupt and halt CQCTL, issue gone.
1550 */
1551 if (cq_host) {
1552 tmp = cqhci_readl(cq_host, CQHCI_IS);
1553 cqhci_writel(cq_host, tmp, CQHCI_IS);
1554 cqhci_writel(cq_host, CQHCI_HALT, CQHCI_CTL);
1555 }
1556 }
1557 }
1558
esdhc_cqe_enable(struct mmc_host * mmc)1559 static void esdhc_cqe_enable(struct mmc_host *mmc)
1560 {
1561 struct sdhci_host *host = mmc_priv(mmc);
1562 struct cqhci_host *cq_host = mmc->cqe_private;
1563 u32 reg;
1564 u16 mode;
1565 int count = 10;
1566
1567 /*
1568 * CQE gets stuck if it sees Buffer Read Enable bit set, which can be
1569 * the case after tuning, so ensure the buffer is drained.
1570 */
1571 reg = sdhci_readl(host, SDHCI_PRESENT_STATE);
1572 while (reg & SDHCI_DATA_AVAILABLE) {
1573 sdhci_readl(host, SDHCI_BUFFER);
1574 reg = sdhci_readl(host, SDHCI_PRESENT_STATE);
1575 if (count-- == 0) {
1576 dev_warn(mmc_dev(host->mmc),
1577 "CQE may get stuck because the Buffer Read Enable bit is set\n");
1578 break;
1579 }
1580 mdelay(1);
1581 }
1582
1583 /*
1584 * Runtime resume will reset the entire host controller, which
1585 * will also clear the DMAEN/BCEN of register ESDHC_MIX_CTRL.
1586 * Here set DMAEN and BCEN when enable CMDQ.
1587 */
1588 mode = sdhci_readw(host, SDHCI_TRANSFER_MODE);
1589 if (host->flags & SDHCI_REQ_USE_DMA)
1590 mode |= SDHCI_TRNS_DMA;
1591 if (!(host->quirks2 & SDHCI_QUIRK2_SUPPORT_SINGLE))
1592 mode |= SDHCI_TRNS_BLK_CNT_EN;
1593 sdhci_writew(host, mode, SDHCI_TRANSFER_MODE);
1594
1595 /*
1596 * Though Runtime resume reset the entire host controller,
1597 * but do not impact the CQHCI side, need to clear the
1598 * HALT bit, avoid CQHCI stuck in the first request when
1599 * system resume back.
1600 */
1601 cqhci_writel(cq_host, 0, CQHCI_CTL);
1602 if (cqhci_readl(cq_host, CQHCI_CTL) & CQHCI_HALT)
1603 dev_err(mmc_dev(host->mmc),
1604 "failed to exit halt state when enable CQE\n");
1605
1606
1607 sdhci_cqe_enable(mmc);
1608 }
1609
esdhc_sdhci_dumpregs(struct mmc_host * mmc)1610 static void esdhc_sdhci_dumpregs(struct mmc_host *mmc)
1611 {
1612 sdhci_dumpregs(mmc_priv(mmc));
1613 }
1614
1615 static const struct cqhci_host_ops esdhc_cqhci_ops = {
1616 .enable = esdhc_cqe_enable,
1617 .disable = sdhci_cqe_disable,
1618 .dumpregs = esdhc_sdhci_dumpregs,
1619 };
1620
1621 static int
sdhci_esdhc_imx_probe_dt(struct platform_device * pdev,struct sdhci_host * host,struct pltfm_imx_data * imx_data)1622 sdhci_esdhc_imx_probe_dt(struct platform_device *pdev,
1623 struct sdhci_host *host,
1624 struct pltfm_imx_data *imx_data)
1625 {
1626 struct device_node *np = pdev->dev.of_node;
1627 struct esdhc_platform_data *boarddata = &imx_data->boarddata;
1628 int ret;
1629
1630 if (of_property_read_bool(np, "fsl,wp-controller"))
1631 boarddata->wp_type = ESDHC_WP_CONTROLLER;
1632
1633 /*
1634 * If we have this property, then activate WP check.
1635 * Retrieveing and requesting the actual WP GPIO will happen
1636 * in the call to mmc_of_parse().
1637 */
1638 if (of_property_read_bool(np, "wp-gpios"))
1639 boarddata->wp_type = ESDHC_WP_GPIO;
1640
1641 of_property_read_u32(np, "fsl,tuning-step", &boarddata->tuning_step);
1642 of_property_read_u32(np, "fsl,tuning-start-tap",
1643 &boarddata->tuning_start_tap);
1644
1645 of_property_read_u32(np, "fsl,strobe-dll-delay-target",
1646 &boarddata->strobe_dll_delay_target);
1647 if (of_property_read_bool(np, "no-1-8-v"))
1648 host->quirks2 |= SDHCI_QUIRK2_NO_1_8_V;
1649
1650 if (of_property_read_u32(np, "fsl,delay-line", &boarddata->delay_line))
1651 boarddata->delay_line = 0;
1652
1653 mmc_of_parse_voltage(host->mmc, &host->ocr_mask);
1654
1655 if (esdhc_is_usdhc(imx_data) && !IS_ERR(imx_data->pinctrl)) {
1656 imx_data->pins_100mhz = pinctrl_lookup_state(imx_data->pinctrl,
1657 ESDHC_PINCTRL_STATE_100MHZ);
1658 imx_data->pins_200mhz = pinctrl_lookup_state(imx_data->pinctrl,
1659 ESDHC_PINCTRL_STATE_200MHZ);
1660 }
1661
1662 /* call to generic mmc_of_parse to support additional capabilities */
1663 ret = mmc_of_parse(host->mmc);
1664 if (ret)
1665 return ret;
1666
1667 /* HS400/HS400ES require 8 bit bus */
1668 if (!(host->mmc->caps & MMC_CAP_8_BIT_DATA))
1669 host->mmc->caps2 &= ~(MMC_CAP2_HS400 | MMC_CAP2_HS400_ES);
1670
1671 if (mmc_gpio_get_cd(host->mmc) >= 0)
1672 host->quirks &= ~SDHCI_QUIRK_BROKEN_CARD_DETECTION;
1673
1674 return 0;
1675 }
1676
sdhci_esdhc_imx_probe(struct platform_device * pdev)1677 static int sdhci_esdhc_imx_probe(struct platform_device *pdev)
1678 {
1679 struct sdhci_pltfm_host *pltfm_host;
1680 struct sdhci_host *host;
1681 struct cqhci_host *cq_host;
1682 int err;
1683 struct pltfm_imx_data *imx_data;
1684
1685 host = sdhci_pltfm_init(pdev, &sdhci_esdhc_imx_pdata,
1686 sizeof(*imx_data));
1687 if (IS_ERR(host))
1688 return PTR_ERR(host);
1689
1690 pltfm_host = sdhci_priv(host);
1691
1692 imx_data = sdhci_pltfm_priv(pltfm_host);
1693
1694 imx_data->socdata = device_get_match_data(&pdev->dev);
1695
1696 host->quirks |= imx_data->socdata->quirks;
1697 if (imx_data->socdata->flags & ESDHC_FLAG_PMQOS)
1698 cpu_latency_qos_add_request(&imx_data->pm_qos_req, 0);
1699
1700 imx_data->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
1701 if (IS_ERR(imx_data->clk_ipg)) {
1702 err = PTR_ERR(imx_data->clk_ipg);
1703 goto free_sdhci;
1704 }
1705
1706 imx_data->clk_ahb = devm_clk_get(&pdev->dev, "ahb");
1707 if (IS_ERR(imx_data->clk_ahb)) {
1708 err = PTR_ERR(imx_data->clk_ahb);
1709 goto free_sdhci;
1710 }
1711
1712 imx_data->clk_per = devm_clk_get(&pdev->dev, "per");
1713 if (IS_ERR(imx_data->clk_per)) {
1714 err = PTR_ERR(imx_data->clk_per);
1715 goto free_sdhci;
1716 }
1717
1718 pltfm_host->clk = imx_data->clk_per;
1719 err = clk_prepare_enable(imx_data->clk_per);
1720 if (err)
1721 goto free_sdhci;
1722 err = clk_prepare_enable(imx_data->clk_ipg);
1723 if (err)
1724 goto disable_per_clk;
1725 err = clk_prepare_enable(imx_data->clk_ahb);
1726 if (err)
1727 goto disable_ipg_clk;
1728
1729 pltfm_host->clock = clk_get_rate(pltfm_host->clk);
1730 if (!pltfm_host->clock) {
1731 dev_err(mmc_dev(host->mmc), "could not get clk rate\n");
1732 err = -EINVAL;
1733 goto disable_ahb_clk;
1734 }
1735
1736 imx_data->pinctrl = devm_pinctrl_get(&pdev->dev);
1737 if (IS_ERR(imx_data->pinctrl))
1738 dev_warn(mmc_dev(host->mmc), "could not get pinctrl\n");
1739
1740 if (esdhc_is_usdhc(imx_data)) {
1741 host->quirks2 |= SDHCI_QUIRK2_PRESET_VALUE_BROKEN;
1742 host->mmc->caps |= MMC_CAP_1_8V_DDR | MMC_CAP_3_3V_DDR;
1743
1744 /* GPIO CD can be set as a wakeup source */
1745 if (!(imx_data->socdata->flags & ESDHC_FLAG_SKIP_CD_WAKE))
1746 host->mmc->caps |= MMC_CAP_CD_WAKE;
1747
1748 if (!(imx_data->socdata->flags & ESDHC_FLAG_HS200))
1749 host->quirks2 |= SDHCI_QUIRK2_BROKEN_HS200;
1750
1751 /* clear tuning bits in case ROM has set it already */
1752 writel(0x0, host->ioaddr + ESDHC_MIX_CTRL);
1753 writel(0x0, host->ioaddr + SDHCI_AUTO_CMD_STATUS);
1754 writel(0x0, host->ioaddr + ESDHC_TUNE_CTRL_STATUS);
1755
1756 /*
1757 * Link usdhc specific mmc_host_ops execute_tuning function,
1758 * to replace the standard one in sdhci_ops.
1759 */
1760 host->mmc_host_ops.execute_tuning = usdhc_execute_tuning;
1761
1762 /*
1763 * Link usdhc specific mmc_host_ops init card function,
1764 * to distinguish the card type.
1765 */
1766 host->mmc_host_ops.init_card = usdhc_init_card;
1767 }
1768
1769 if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING)
1770 sdhci_esdhc_ops.platform_execute_tuning =
1771 esdhc_executing_tuning;
1772
1773 if (imx_data->socdata->flags & ESDHC_FLAG_ERR004536)
1774 host->quirks |= SDHCI_QUIRK_BROKEN_ADMA;
1775
1776 if (imx_data->socdata->flags & ESDHC_FLAG_HS400)
1777 host->mmc->caps2 |= MMC_CAP2_HS400;
1778
1779 if (imx_data->socdata->flags & ESDHC_FLAG_BROKEN_AUTO_CMD23)
1780 host->quirks2 |= SDHCI_QUIRK2_ACMD23_BROKEN;
1781
1782 if (imx_data->socdata->flags & ESDHC_FLAG_HS400_ES) {
1783 host->mmc->caps2 |= MMC_CAP2_HS400_ES;
1784 host->mmc_host_ops.hs400_enhanced_strobe =
1785 esdhc_hs400_enhanced_strobe;
1786 }
1787
1788 if (imx_data->socdata->flags & ESDHC_FLAG_CQHCI) {
1789 host->mmc->caps2 |= MMC_CAP2_CQE | MMC_CAP2_CQE_DCMD;
1790 cq_host = devm_kzalloc(&pdev->dev, sizeof(*cq_host), GFP_KERNEL);
1791 if (!cq_host) {
1792 err = -ENOMEM;
1793 goto disable_ahb_clk;
1794 }
1795
1796 cq_host->mmio = host->ioaddr + ESDHC_CQHCI_ADDR_OFFSET;
1797 cq_host->ops = &esdhc_cqhci_ops;
1798
1799 err = cqhci_init(cq_host, host->mmc, false);
1800 if (err)
1801 goto disable_ahb_clk;
1802 }
1803
1804 err = sdhci_esdhc_imx_probe_dt(pdev, host, imx_data);
1805 if (err)
1806 goto disable_ahb_clk;
1807
1808 sdhci_esdhc_imx_hwinit(host);
1809
1810 err = sdhci_add_host(host);
1811 if (err)
1812 goto disable_ahb_clk;
1813
1814 /*
1815 * Setup the wakeup capability here, let user to decide
1816 * whether need to enable this wakeup through sysfs interface.
1817 */
1818 if ((host->mmc->pm_caps & MMC_PM_KEEP_POWER) &&
1819 (host->mmc->pm_caps & MMC_PM_WAKE_SDIO_IRQ))
1820 device_set_wakeup_capable(&pdev->dev, true);
1821
1822 pm_runtime_set_active(&pdev->dev);
1823 pm_runtime_set_autosuspend_delay(&pdev->dev, 50);
1824 pm_runtime_use_autosuspend(&pdev->dev);
1825 pm_suspend_ignore_children(&pdev->dev, 1);
1826 pm_runtime_enable(&pdev->dev);
1827
1828 return 0;
1829
1830 disable_ahb_clk:
1831 clk_disable_unprepare(imx_data->clk_ahb);
1832 disable_ipg_clk:
1833 clk_disable_unprepare(imx_data->clk_ipg);
1834 disable_per_clk:
1835 clk_disable_unprepare(imx_data->clk_per);
1836 free_sdhci:
1837 if (imx_data->socdata->flags & ESDHC_FLAG_PMQOS)
1838 cpu_latency_qos_remove_request(&imx_data->pm_qos_req);
1839 sdhci_pltfm_free(pdev);
1840 return err;
1841 }
1842
sdhci_esdhc_imx_remove(struct platform_device * pdev)1843 static void sdhci_esdhc_imx_remove(struct platform_device *pdev)
1844 {
1845 struct sdhci_host *host = platform_get_drvdata(pdev);
1846 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1847 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
1848 int dead;
1849
1850 pm_runtime_get_sync(&pdev->dev);
1851 dead = (readl(host->ioaddr + SDHCI_INT_STATUS) == 0xffffffff);
1852 pm_runtime_disable(&pdev->dev);
1853 pm_runtime_put_noidle(&pdev->dev);
1854
1855 sdhci_remove_host(host, dead);
1856
1857 clk_disable_unprepare(imx_data->clk_per);
1858 clk_disable_unprepare(imx_data->clk_ipg);
1859 clk_disable_unprepare(imx_data->clk_ahb);
1860
1861 if (imx_data->socdata->flags & ESDHC_FLAG_PMQOS)
1862 cpu_latency_qos_remove_request(&imx_data->pm_qos_req);
1863
1864 sdhci_pltfm_free(pdev);
1865 }
1866
1867 #ifdef CONFIG_PM_SLEEP
sdhci_esdhc_suspend(struct device * dev)1868 static int sdhci_esdhc_suspend(struct device *dev)
1869 {
1870 struct sdhci_host *host = dev_get_drvdata(dev);
1871 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1872 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
1873 int ret;
1874
1875 if (host->mmc->caps2 & MMC_CAP2_CQE) {
1876 ret = cqhci_suspend(host->mmc);
1877 if (ret)
1878 return ret;
1879 }
1880
1881 if ((imx_data->socdata->flags & ESDHC_FLAG_STATE_LOST_IN_LPMODE) &&
1882 (host->tuning_mode != SDHCI_TUNING_MODE_1)) {
1883 mmc_retune_timer_stop(host->mmc);
1884 mmc_retune_needed(host->mmc);
1885 }
1886
1887 if (host->tuning_mode != SDHCI_TUNING_MODE_3)
1888 mmc_retune_needed(host->mmc);
1889
1890 ret = sdhci_suspend_host(host);
1891 if (ret)
1892 return ret;
1893
1894 ret = pinctrl_pm_select_sleep_state(dev);
1895 if (ret)
1896 return ret;
1897
1898 ret = mmc_gpio_set_cd_wake(host->mmc, true);
1899
1900 return ret;
1901 }
1902
sdhci_esdhc_resume(struct device * dev)1903 static int sdhci_esdhc_resume(struct device *dev)
1904 {
1905 struct sdhci_host *host = dev_get_drvdata(dev);
1906 int ret;
1907
1908 ret = pinctrl_pm_select_default_state(dev);
1909 if (ret)
1910 return ret;
1911
1912 /* re-initialize hw state in case it's lost in low power mode */
1913 sdhci_esdhc_imx_hwinit(host);
1914
1915 ret = sdhci_resume_host(host);
1916 if (ret)
1917 return ret;
1918
1919 if (host->mmc->caps2 & MMC_CAP2_CQE)
1920 ret = cqhci_resume(host->mmc);
1921
1922 if (!ret)
1923 ret = mmc_gpio_set_cd_wake(host->mmc, false);
1924
1925 return ret;
1926 }
1927 #endif
1928
1929 #ifdef CONFIG_PM
sdhci_esdhc_runtime_suspend(struct device * dev)1930 static int sdhci_esdhc_runtime_suspend(struct device *dev)
1931 {
1932 struct sdhci_host *host = dev_get_drvdata(dev);
1933 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1934 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
1935 int ret;
1936
1937 if (host->mmc->caps2 & MMC_CAP2_CQE) {
1938 ret = cqhci_suspend(host->mmc);
1939 if (ret)
1940 return ret;
1941 }
1942
1943 ret = sdhci_runtime_suspend_host(host);
1944 if (ret)
1945 return ret;
1946
1947 if (host->tuning_mode != SDHCI_TUNING_MODE_3)
1948 mmc_retune_needed(host->mmc);
1949
1950 imx_data->actual_clock = host->mmc->actual_clock;
1951 esdhc_pltfm_set_clock(host, 0);
1952 clk_disable_unprepare(imx_data->clk_per);
1953 clk_disable_unprepare(imx_data->clk_ipg);
1954 clk_disable_unprepare(imx_data->clk_ahb);
1955
1956 if (imx_data->socdata->flags & ESDHC_FLAG_PMQOS)
1957 cpu_latency_qos_remove_request(&imx_data->pm_qos_req);
1958
1959 return ret;
1960 }
1961
sdhci_esdhc_runtime_resume(struct device * dev)1962 static int sdhci_esdhc_runtime_resume(struct device *dev)
1963 {
1964 struct sdhci_host *host = dev_get_drvdata(dev);
1965 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1966 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
1967 int err;
1968
1969 if (imx_data->socdata->flags & ESDHC_FLAG_PMQOS)
1970 cpu_latency_qos_add_request(&imx_data->pm_qos_req, 0);
1971
1972 if (imx_data->socdata->flags & ESDHC_FLAG_CLK_RATE_LOST_IN_PM_RUNTIME)
1973 clk_set_rate(imx_data->clk_per, pltfm_host->clock);
1974
1975 err = clk_prepare_enable(imx_data->clk_ahb);
1976 if (err)
1977 goto remove_pm_qos_request;
1978
1979 err = clk_prepare_enable(imx_data->clk_per);
1980 if (err)
1981 goto disable_ahb_clk;
1982
1983 err = clk_prepare_enable(imx_data->clk_ipg);
1984 if (err)
1985 goto disable_per_clk;
1986
1987 esdhc_pltfm_set_clock(host, imx_data->actual_clock);
1988
1989 err = sdhci_runtime_resume_host(host, 0);
1990 if (err)
1991 goto disable_ipg_clk;
1992
1993 if (host->mmc->caps2 & MMC_CAP2_CQE)
1994 err = cqhci_resume(host->mmc);
1995
1996 return err;
1997
1998 disable_ipg_clk:
1999 clk_disable_unprepare(imx_data->clk_ipg);
2000 disable_per_clk:
2001 clk_disable_unprepare(imx_data->clk_per);
2002 disable_ahb_clk:
2003 clk_disable_unprepare(imx_data->clk_ahb);
2004 remove_pm_qos_request:
2005 if (imx_data->socdata->flags & ESDHC_FLAG_PMQOS)
2006 cpu_latency_qos_remove_request(&imx_data->pm_qos_req);
2007 return err;
2008 }
2009 #endif
2010
2011 static const struct dev_pm_ops sdhci_esdhc_pmops = {
2012 SET_SYSTEM_SLEEP_PM_OPS(sdhci_esdhc_suspend, sdhci_esdhc_resume)
2013 SET_RUNTIME_PM_OPS(sdhci_esdhc_runtime_suspend,
2014 sdhci_esdhc_runtime_resume, NULL)
2015 };
2016
2017 static struct platform_driver sdhci_esdhc_imx_driver = {
2018 .driver = {
2019 .name = "sdhci-esdhc-imx",
2020 .probe_type = PROBE_PREFER_ASYNCHRONOUS,
2021 .of_match_table = imx_esdhc_dt_ids,
2022 .pm = &sdhci_esdhc_pmops,
2023 },
2024 .probe = sdhci_esdhc_imx_probe,
2025 .remove_new = sdhci_esdhc_imx_remove,
2026 };
2027
2028 module_platform_driver(sdhci_esdhc_imx_driver);
2029
2030 MODULE_DESCRIPTION("SDHCI driver for Freescale i.MX eSDHC");
2031 MODULE_AUTHOR("Wolfram Sang <kernel@pengutronix.de>");
2032 MODULE_LICENSE("GPL v2");
2033