1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Driver for Synopsys DesignWare Cores Mobile Storage Host Controller
4 *
5 * Copyright (C) 2018 Synaptics Incorporated
6 *
7 * Author: Jisheng Zhang <jszhang@kernel.org>
8 */
9
10 #include <linux/acpi.h>
11 #include <linux/arm-smccc.h>
12 #include <linux/bitfield.h>
13 #include <linux/clk.h>
14 #include <linux/dma-mapping.h>
15 #include <linux/iopoll.h>
16 #include <linux/kernel.h>
17 #include <linux/module.h>
18 #include <linux/of.h>
19 #include <linux/platform_device.h>
20 #include <linux/pm_domain.h>
21 #include <linux/pm_runtime.h>
22 #include <linux/reset.h>
23 #include <linux/sizes.h>
24
25 #include "sdhci-pltfm.h"
26 #include "cqhci.h"
27
28 #define SDHCI_DWCMSHC_ARG2_STUFF GENMASK(31, 16)
29
30 /* DWCMSHC specific Mode Select value */
31 #define DWCMSHC_CTRL_HS400 0x7
32
33 /* DWC IP vendor area 1 pointer */
34 #define DWCMSHC_P_VENDOR_AREA1 0xe8
35 #define DWCMSHC_AREA1_MASK GENMASK(11, 0)
36 /* Offset inside the vendor area 1 */
37 #define DWCMSHC_HOST_CTRL3 0x8
38 #define DWCMSHC_EMMC_CONTROL 0x2c
39 #define DWCMSHC_CARD_IS_EMMC BIT(0)
40 #define DWCMSHC_ENHANCED_STROBE BIT(8)
41 #define DWCMSHC_EMMC_ATCTRL 0x40
42 /* Tuning and auto-tuning fields in AT_CTRL_R control register */
43 #define AT_CTRL_AT_EN BIT(0) /* autotuning is enabled */
44 #define AT_CTRL_CI_SEL BIT(1) /* interval to drive center phase select */
45 #define AT_CTRL_SWIN_TH_EN BIT(2) /* sampling window threshold enable */
46 #define AT_CTRL_RPT_TUNE_ERR BIT(3) /* enable reporting framing errors */
47 #define AT_CTRL_SW_TUNE_EN BIT(4) /* enable software managed tuning */
48 #define AT_CTRL_WIN_EDGE_SEL_MASK GENMASK(11, 8) /* bits [11:8] */
49 #define AT_CTRL_WIN_EDGE_SEL 0xf /* sampling window edge select */
50 #define AT_CTRL_TUNE_CLK_STOP_EN BIT(16) /* clocks stopped during phase code change */
51 #define AT_CTRL_PRE_CHANGE_DLY_MASK GENMASK(18, 17) /* bits [18:17] */
52 #define AT_CTRL_PRE_CHANGE_DLY 0x1 /* 2-cycle latency */
53 #define AT_CTRL_POST_CHANGE_DLY_MASK GENMASK(20, 19) /* bits [20:19] */
54 #define AT_CTRL_POST_CHANGE_DLY 0x3 /* 4-cycle latency */
55 #define AT_CTRL_SWIN_TH_VAL_MASK GENMASK(31, 24) /* bits [31:24] */
56 #define AT_CTRL_SWIN_TH_VAL 0x9 /* sampling window threshold */
57
58 /* DWC IP vendor area 2 pointer */
59 #define DWCMSHC_P_VENDOR_AREA2 0xea
60
61 /* Sophgo CV18XX specific Registers */
62 #define CV18XX_SDHCI_MSHC_CTRL 0x00
63 #define CV18XX_EMMC_FUNC_EN BIT(0)
64 #define CV18XX_LATANCY_1T BIT(1)
65 #define CV18XX_SDHCI_PHY_TX_RX_DLY 0x40
66 #define CV18XX_PHY_TX_DLY_MSK GENMASK(6, 0)
67 #define CV18XX_PHY_TX_SRC_MSK GENMASK(9, 8)
68 #define CV18XX_PHY_TX_SRC_INVERT_CLK_TX 0x1
69 #define CV18XX_PHY_RX_DLY_MSK GENMASK(22, 16)
70 #define CV18XX_PHY_RX_SRC_MSK GENMASK(25, 24)
71 #define CV18XX_PHY_RX_SRC_INVERT_RX_CLK 0x1
72 #define CV18XX_SDHCI_PHY_CONFIG 0x4c
73 #define CV18XX_PHY_TX_BPS BIT(0)
74
75 #define CV18XX_TUNE_MAX 128
76 #define CV18XX_TUNE_STEP 1
77 #define CV18XX_RETRY_TUNING_MAX 50
78
79 /* Rockchip specific Registers */
80 #define DWCMSHC_EMMC_DLL_CTRL 0x800
81 #define DWCMSHC_EMMC_DLL_RXCLK 0x804
82 #define DWCMSHC_EMMC_DLL_TXCLK 0x808
83 #define DWCMSHC_EMMC_DLL_STRBIN 0x80c
84 #define DECMSHC_EMMC_DLL_CMDOUT 0x810
85 #define DWCMSHC_EMMC_DLL_STATUS0 0x840
86 #define DWCMSHC_EMMC_DLL_START BIT(0)
87 #define DWCMSHC_EMMC_DLL_LOCKED BIT(8)
88 #define DWCMSHC_EMMC_DLL_TIMEOUT BIT(9)
89 #define DWCMSHC_EMMC_DLL_RXCLK_SRCSEL 29
90 #define DWCMSHC_EMMC_DLL_START_POINT 16
91 #define DWCMSHC_EMMC_DLL_INC 8
92 #define DWCMSHC_EMMC_DLL_BYPASS BIT(24)
93 #define DWCMSHC_EMMC_DLL_DLYENA BIT(27)
94 #define DLL_TXCLK_TAPNUM_DEFAULT 0x10
95 #define DLL_TXCLK_TAPNUM_90_DEGREES 0xA
96 #define DLL_TXCLK_TAPNUM_FROM_SW BIT(24)
97 #define DLL_STRBIN_TAPNUM_DEFAULT 0x8
98 #define DLL_STRBIN_TAPNUM_FROM_SW BIT(24)
99 #define DLL_STRBIN_DELAY_NUM_SEL BIT(26)
100 #define DLL_STRBIN_DELAY_NUM_OFFSET 16
101 #define DLL_STRBIN_DELAY_NUM_DEFAULT 0x16
102 #define DLL_RXCLK_NO_INVERTER 1
103 #define DLL_RXCLK_INVERTER 0
104 #define DLL_CMDOUT_TAPNUM_90_DEGREES 0x8
105 #define DLL_RXCLK_ORI_GATE BIT(31)
106 #define DLL_CMDOUT_TAPNUM_FROM_SW BIT(24)
107 #define DLL_CMDOUT_SRC_CLK_NEG BIT(28)
108 #define DLL_CMDOUT_EN_SRC_CLK_NEG BIT(29)
109
110 #define DLL_LOCK_WO_TMOUT(x) \
111 ((((x) & DWCMSHC_EMMC_DLL_LOCKED) == DWCMSHC_EMMC_DLL_LOCKED) && \
112 (((x) & DWCMSHC_EMMC_DLL_TIMEOUT) == 0))
113
114 /* PHY register area pointer */
115 #define DWC_MSHC_PTR_PHY_R 0x300
116
117 /* PHY general configuration */
118 #define PHY_CNFG_R (DWC_MSHC_PTR_PHY_R + 0x00)
119 #define PHY_CNFG_RSTN_DEASSERT 0x1 /* Deassert PHY reset */
120 #define PHY_CNFG_PHY_PWRGOOD_MASK BIT_MASK(1) /* bit [1] */
121 #define PHY_CNFG_PAD_SP_MASK GENMASK(19, 16) /* bits [19:16] */
122 #define PHY_CNFG_PAD_SP 0x0c /* PMOS TX drive strength */
123 #define PHY_CNFG_PAD_SP_SG2042 0x09 /* PMOS TX drive strength for SG2042 */
124 #define PHY_CNFG_PAD_SN_MASK GENMASK(23, 20) /* bits [23:20] */
125 #define PHY_CNFG_PAD_SN 0x0c /* NMOS TX drive strength */
126 #define PHY_CNFG_PAD_SN_SG2042 0x08 /* NMOS TX drive strength for SG2042 */
127
128 /* PHY command/response pad settings */
129 #define PHY_CMDPAD_CNFG_R (DWC_MSHC_PTR_PHY_R + 0x04)
130
131 /* PHY data pad settings */
132 #define PHY_DATAPAD_CNFG_R (DWC_MSHC_PTR_PHY_R + 0x06)
133
134 /* PHY clock pad settings */
135 #define PHY_CLKPAD_CNFG_R (DWC_MSHC_PTR_PHY_R + 0x08)
136
137 /* PHY strobe pad settings */
138 #define PHY_STBPAD_CNFG_R (DWC_MSHC_PTR_PHY_R + 0x0a)
139
140 /* PHY reset pad settings */
141 #define PHY_RSTNPAD_CNFG_R (DWC_MSHC_PTR_PHY_R + 0x0c)
142
143 /* Bitfields are common for all pad settings */
144 #define PHY_PAD_RXSEL_1V8 0x1 /* Receiver type select for 1.8V */
145 #define PHY_PAD_RXSEL_3V3 0x2 /* Receiver type select for 3.3V */
146
147 #define PHY_PAD_WEAKPULL_MASK GENMASK(4, 3) /* bits [4:3] */
148 #define PHY_PAD_WEAKPULL_PULLUP 0x1 /* Weak pull up enabled */
149 #define PHY_PAD_WEAKPULL_PULLDOWN 0x2 /* Weak pull down enabled */
150
151 #define PHY_PAD_TXSLEW_CTRL_P_MASK GENMASK(8, 5) /* bits [8:5] */
152 #define PHY_PAD_TXSLEW_CTRL_P 0x3 /* Slew control for P-Type pad TX */
153 #define PHY_PAD_TXSLEW_CTRL_N_MASK GENMASK(12, 9) /* bits [12:9] */
154 #define PHY_PAD_TXSLEW_CTRL_N 0x3 /* Slew control for N-Type pad TX */
155 #define PHY_PAD_TXSLEW_CTRL_N_SG2042 0x2 /* Slew control for N-Type pad TX for SG2042 */
156
157 /* PHY CLK delay line settings */
158 #define PHY_SDCLKDL_CNFG_R (DWC_MSHC_PTR_PHY_R + 0x1d)
159 #define PHY_SDCLKDL_CNFG_EXTDLY_EN BIT(0)
160 #define PHY_SDCLKDL_CNFG_UPDATE BIT(4) /* set before writing to SDCLKDL_DC */
161
162 /* PHY CLK delay line delay code */
163 #define PHY_SDCLKDL_DC_R (DWC_MSHC_PTR_PHY_R + 0x1e)
164 #define PHY_SDCLKDL_DC_INITIAL 0x40 /* initial delay code */
165 #define PHY_SDCLKDL_DC_DEFAULT 0x32 /* default delay code */
166 #define PHY_SDCLKDL_DC_HS400 0x18 /* delay code for HS400 mode */
167
168 #define PHY_SMPLDL_CNFG_R (DWC_MSHC_PTR_PHY_R + 0x20)
169 #define PHY_SMPLDL_CNFG_BYPASS_EN BIT(1)
170
171 /* PHY drift_cclk_rx delay line configuration setting */
172 #define PHY_ATDL_CNFG_R (DWC_MSHC_PTR_PHY_R + 0x21)
173 #define PHY_ATDL_CNFG_INPSEL_MASK GENMASK(3, 2) /* bits [3:2] */
174 #define PHY_ATDL_CNFG_INPSEL 0x3 /* delay line input source */
175 #define PHY_ATDL_CNFG_INPSEL_SG2042 0x2 /* delay line input source for SG2042 */
176
177 /* PHY DLL control settings */
178 #define PHY_DLL_CTRL_R (DWC_MSHC_PTR_PHY_R + 0x24)
179 #define PHY_DLL_CTRL_DISABLE 0x0 /* PHY DLL is enabled */
180 #define PHY_DLL_CTRL_ENABLE 0x1 /* PHY DLL is disabled */
181
182 /* PHY DLL configuration register 1 */
183 #define PHY_DLL_CNFG1_R (DWC_MSHC_PTR_PHY_R + 0x25)
184 #define PHY_DLL_CNFG1_SLVDLY_MASK GENMASK(5, 4) /* bits [5:4] */
185 #define PHY_DLL_CNFG1_SLVDLY 0x2 /* DLL slave update delay input */
186 #define PHY_DLL_CNFG1_WAITCYCLE 0x5 /* DLL wait cycle input */
187
188 /* PHY DLL configuration register 2 */
189 #define PHY_DLL_CNFG2_R (DWC_MSHC_PTR_PHY_R + 0x26)
190 #define PHY_DLL_CNFG2_JUMPSTEP 0xa /* DLL jump step input */
191
192 /* PHY DLL master and slave delay line configuration settings */
193 #define PHY_DLLDL_CNFG_R (DWC_MSHC_PTR_PHY_R + 0x28)
194 #define PHY_DLLDL_CNFG_SLV_INPSEL_MASK GENMASK(6, 5) /* bits [6:5] */
195 #define PHY_DLLDL_CNFG_SLV_INPSEL 0x3 /* clock source select for slave DL */
196
197 #define FLAG_IO_FIXED_1V8 BIT(0)
198
199 #define BOUNDARY_OK(addr, len) \
200 ((addr | (SZ_128M - 1)) == ((addr + len - 1) | (SZ_128M - 1)))
201
202 #define DWCMSHC_SDHCI_CQE_TRNS_MODE (SDHCI_TRNS_MULTI | \
203 SDHCI_TRNS_BLK_CNT_EN | \
204 SDHCI_TRNS_DMA)
205
206 /* SMC call for BlueField-3 eMMC RST_N */
207 #define BLUEFIELD_SMC_SET_EMMC_RST_N 0x82000007
208
209 enum dwcmshc_rk_type {
210 DWCMSHC_RK3568,
211 DWCMSHC_RK3588,
212 };
213
214 struct rk35xx_priv {
215 struct reset_control *reset;
216 enum dwcmshc_rk_type devtype;
217 u8 txclk_tapnum;
218 };
219
220 #define DWCMSHC_MAX_OTHER_CLKS 3
221
222 struct dwcmshc_priv {
223 struct clk *bus_clk;
224 int vendor_specific_area1; /* P_VENDOR_SPECIFIC_AREA1 reg */
225 int vendor_specific_area2; /* P_VENDOR_SPECIFIC_AREA2 reg */
226
227 int num_other_clks;
228 struct clk_bulk_data other_clks[DWCMSHC_MAX_OTHER_CLKS];
229
230 void *priv; /* pointer to SoC private stuff */
231 u16 delay_line;
232 u16 flags;
233 };
234
235 struct dwcmshc_pltfm_data {
236 const struct sdhci_pltfm_data pdata;
237 int (*init)(struct device *dev, struct sdhci_host *host, struct dwcmshc_priv *dwc_priv);
238 void (*postinit)(struct sdhci_host *host, struct dwcmshc_priv *dwc_priv);
239 };
240
dwcmshc_get_enable_other_clks(struct device * dev,struct dwcmshc_priv * priv,int num_clks,const char * const clk_ids[])241 static int dwcmshc_get_enable_other_clks(struct device *dev,
242 struct dwcmshc_priv *priv,
243 int num_clks,
244 const char * const clk_ids[])
245 {
246 int err;
247
248 if (num_clks > DWCMSHC_MAX_OTHER_CLKS)
249 return -EINVAL;
250
251 for (int i = 0; i < num_clks; i++)
252 priv->other_clks[i].id = clk_ids[i];
253
254 err = devm_clk_bulk_get_optional(dev, num_clks, priv->other_clks);
255 if (err) {
256 dev_err(dev, "failed to get clocks %d\n", err);
257 return err;
258 }
259
260 err = clk_bulk_prepare_enable(num_clks, priv->other_clks);
261 if (err)
262 dev_err(dev, "failed to enable clocks %d\n", err);
263
264 priv->num_other_clks = num_clks;
265
266 return err;
267 }
268
269 /*
270 * If DMA addr spans 128MB boundary, we split the DMA transfer into two
271 * so that each DMA transfer doesn't exceed the boundary.
272 */
dwcmshc_adma_write_desc(struct sdhci_host * host,void ** desc,dma_addr_t addr,int len,unsigned int cmd)273 static void dwcmshc_adma_write_desc(struct sdhci_host *host, void **desc,
274 dma_addr_t addr, int len, unsigned int cmd)
275 {
276 int tmplen, offset;
277
278 if (likely(!len || BOUNDARY_OK(addr, len))) {
279 sdhci_adma_write_desc(host, desc, addr, len, cmd);
280 return;
281 }
282
283 offset = addr & (SZ_128M - 1);
284 tmplen = SZ_128M - offset;
285 sdhci_adma_write_desc(host, desc, addr, tmplen, cmd);
286
287 addr += tmplen;
288 len -= tmplen;
289 sdhci_adma_write_desc(host, desc, addr, len, cmd);
290 }
291
dwcmshc_get_max_clock(struct sdhci_host * host)292 static unsigned int dwcmshc_get_max_clock(struct sdhci_host *host)
293 {
294 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
295
296 if (pltfm_host->clk)
297 return sdhci_pltfm_clk_get_max_clock(host);
298 else
299 return pltfm_host->clock;
300 }
301
rk35xx_get_max_clock(struct sdhci_host * host)302 static unsigned int rk35xx_get_max_clock(struct sdhci_host *host)
303 {
304 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
305
306 return clk_round_rate(pltfm_host->clk, ULONG_MAX);
307 }
308
dwcmshc_check_auto_cmd23(struct mmc_host * mmc,struct mmc_request * mrq)309 static void dwcmshc_check_auto_cmd23(struct mmc_host *mmc,
310 struct mmc_request *mrq)
311 {
312 struct sdhci_host *host = mmc_priv(mmc);
313
314 /*
315 * No matter V4 is enabled or not, ARGUMENT2 register is 32-bit
316 * block count register which doesn't support stuff bits of
317 * CMD23 argument on dwcmsch host controller.
318 */
319 if (mrq->sbc && (mrq->sbc->arg & SDHCI_DWCMSHC_ARG2_STUFF))
320 host->flags &= ~SDHCI_AUTO_CMD23;
321 else
322 host->flags |= SDHCI_AUTO_CMD23;
323 }
324
dwcmshc_request(struct mmc_host * mmc,struct mmc_request * mrq)325 static void dwcmshc_request(struct mmc_host *mmc, struct mmc_request *mrq)
326 {
327 dwcmshc_check_auto_cmd23(mmc, mrq);
328
329 sdhci_request(mmc, mrq);
330 }
331
dwcmshc_phy_1_8v_init(struct sdhci_host * host)332 static void dwcmshc_phy_1_8v_init(struct sdhci_host *host)
333 {
334 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
335 struct dwcmshc_priv *priv = sdhci_pltfm_priv(pltfm_host);
336 u32 val;
337
338 /* deassert phy reset & set tx drive strength */
339 val = PHY_CNFG_RSTN_DEASSERT;
340 val |= FIELD_PREP(PHY_CNFG_PAD_SP_MASK, PHY_CNFG_PAD_SP);
341 val |= FIELD_PREP(PHY_CNFG_PAD_SN_MASK, PHY_CNFG_PAD_SN);
342 sdhci_writel(host, val, PHY_CNFG_R);
343
344 /* disable delay line */
345 sdhci_writeb(host, PHY_SDCLKDL_CNFG_UPDATE, PHY_SDCLKDL_CNFG_R);
346
347 /* set delay line */
348 sdhci_writeb(host, priv->delay_line, PHY_SDCLKDL_DC_R);
349 sdhci_writeb(host, PHY_DLL_CNFG2_JUMPSTEP, PHY_DLL_CNFG2_R);
350
351 /* enable delay lane */
352 val = sdhci_readb(host, PHY_SDCLKDL_CNFG_R);
353 val &= ~(PHY_SDCLKDL_CNFG_UPDATE);
354 sdhci_writeb(host, val, PHY_SDCLKDL_CNFG_R);
355
356 /* configure phy pads */
357 val = PHY_PAD_RXSEL_1V8;
358 val |= FIELD_PREP(PHY_PAD_WEAKPULL_MASK, PHY_PAD_WEAKPULL_PULLUP);
359 val |= FIELD_PREP(PHY_PAD_TXSLEW_CTRL_P_MASK, PHY_PAD_TXSLEW_CTRL_P);
360 val |= FIELD_PREP(PHY_PAD_TXSLEW_CTRL_N_MASK, PHY_PAD_TXSLEW_CTRL_N);
361 sdhci_writew(host, val, PHY_CMDPAD_CNFG_R);
362 sdhci_writew(host, val, PHY_DATAPAD_CNFG_R);
363 sdhci_writew(host, val, PHY_RSTNPAD_CNFG_R);
364
365 val = FIELD_PREP(PHY_PAD_TXSLEW_CTRL_P_MASK, PHY_PAD_TXSLEW_CTRL_P);
366 val |= FIELD_PREP(PHY_PAD_TXSLEW_CTRL_N_MASK, PHY_PAD_TXSLEW_CTRL_N);
367 sdhci_writew(host, val, PHY_CLKPAD_CNFG_R);
368
369 val = PHY_PAD_RXSEL_1V8;
370 val |= FIELD_PREP(PHY_PAD_WEAKPULL_MASK, PHY_PAD_WEAKPULL_PULLDOWN);
371 val |= FIELD_PREP(PHY_PAD_TXSLEW_CTRL_P_MASK, PHY_PAD_TXSLEW_CTRL_P);
372 val |= FIELD_PREP(PHY_PAD_TXSLEW_CTRL_N_MASK, PHY_PAD_TXSLEW_CTRL_N);
373 sdhci_writew(host, val, PHY_STBPAD_CNFG_R);
374
375 /* enable data strobe mode */
376 sdhci_writeb(host, FIELD_PREP(PHY_DLLDL_CNFG_SLV_INPSEL_MASK, PHY_DLLDL_CNFG_SLV_INPSEL),
377 PHY_DLLDL_CNFG_R);
378
379 /* enable phy dll */
380 sdhci_writeb(host, PHY_DLL_CTRL_ENABLE, PHY_DLL_CTRL_R);
381 }
382
dwcmshc_phy_3_3v_init(struct sdhci_host * host)383 static void dwcmshc_phy_3_3v_init(struct sdhci_host *host)
384 {
385 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
386 struct dwcmshc_priv *priv = sdhci_pltfm_priv(pltfm_host);
387 u32 val;
388
389 /* deassert phy reset & set tx drive strength */
390 val = PHY_CNFG_RSTN_DEASSERT;
391 val |= FIELD_PREP(PHY_CNFG_PAD_SP_MASK, PHY_CNFG_PAD_SP);
392 val |= FIELD_PREP(PHY_CNFG_PAD_SN_MASK, PHY_CNFG_PAD_SN);
393 sdhci_writel(host, val, PHY_CNFG_R);
394
395 /* disable delay line */
396 sdhci_writeb(host, PHY_SDCLKDL_CNFG_UPDATE, PHY_SDCLKDL_CNFG_R);
397
398 /* set delay line */
399 sdhci_writeb(host, priv->delay_line, PHY_SDCLKDL_DC_R);
400 sdhci_writeb(host, PHY_DLL_CNFG2_JUMPSTEP, PHY_DLL_CNFG2_R);
401
402 /* enable delay lane */
403 val = sdhci_readb(host, PHY_SDCLKDL_CNFG_R);
404 val &= ~(PHY_SDCLKDL_CNFG_UPDATE);
405 sdhci_writeb(host, val, PHY_SDCLKDL_CNFG_R);
406
407 /* configure phy pads */
408 val = PHY_PAD_RXSEL_3V3;
409 val |= FIELD_PREP(PHY_PAD_WEAKPULL_MASK, PHY_PAD_WEAKPULL_PULLUP);
410 val |= FIELD_PREP(PHY_PAD_TXSLEW_CTRL_P_MASK, PHY_PAD_TXSLEW_CTRL_P);
411 val |= FIELD_PREP(PHY_PAD_TXSLEW_CTRL_N_MASK, PHY_PAD_TXSLEW_CTRL_N);
412 sdhci_writew(host, val, PHY_CMDPAD_CNFG_R);
413 sdhci_writew(host, val, PHY_DATAPAD_CNFG_R);
414 sdhci_writew(host, val, PHY_RSTNPAD_CNFG_R);
415
416 val = FIELD_PREP(PHY_PAD_TXSLEW_CTRL_P_MASK, PHY_PAD_TXSLEW_CTRL_P);
417 val |= FIELD_PREP(PHY_PAD_TXSLEW_CTRL_N_MASK, PHY_PAD_TXSLEW_CTRL_N);
418 sdhci_writew(host, val, PHY_CLKPAD_CNFG_R);
419
420 val = PHY_PAD_RXSEL_3V3;
421 val |= FIELD_PREP(PHY_PAD_WEAKPULL_MASK, PHY_PAD_WEAKPULL_PULLDOWN);
422 val |= FIELD_PREP(PHY_PAD_TXSLEW_CTRL_P_MASK, PHY_PAD_TXSLEW_CTRL_P);
423 val |= FIELD_PREP(PHY_PAD_TXSLEW_CTRL_N_MASK, PHY_PAD_TXSLEW_CTRL_N);
424 sdhci_writew(host, val, PHY_STBPAD_CNFG_R);
425
426 /* enable phy dll */
427 sdhci_writeb(host, PHY_DLL_CTRL_ENABLE, PHY_DLL_CTRL_R);
428 }
429
th1520_sdhci_set_phy(struct sdhci_host * host)430 static void th1520_sdhci_set_phy(struct sdhci_host *host)
431 {
432 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
433 struct dwcmshc_priv *priv = sdhci_pltfm_priv(pltfm_host);
434 u32 emmc_caps = MMC_CAP2_NO_SD | MMC_CAP2_NO_SDIO;
435 u16 emmc_ctrl;
436
437 /* Before power on, set PHY configs */
438 if (priv->flags & FLAG_IO_FIXED_1V8)
439 dwcmshc_phy_1_8v_init(host);
440 else
441 dwcmshc_phy_3_3v_init(host);
442
443 if ((host->mmc->caps2 & emmc_caps) == emmc_caps) {
444 emmc_ctrl = sdhci_readw(host, priv->vendor_specific_area1 + DWCMSHC_EMMC_CONTROL);
445 emmc_ctrl |= DWCMSHC_CARD_IS_EMMC;
446 sdhci_writew(host, emmc_ctrl, priv->vendor_specific_area1 + DWCMSHC_EMMC_CONTROL);
447 }
448
449 sdhci_writeb(host, FIELD_PREP(PHY_DLL_CNFG1_SLVDLY_MASK, PHY_DLL_CNFG1_SLVDLY) |
450 PHY_DLL_CNFG1_WAITCYCLE, PHY_DLL_CNFG1_R);
451 }
452
dwcmshc_set_uhs_signaling(struct sdhci_host * host,unsigned int timing)453 static void dwcmshc_set_uhs_signaling(struct sdhci_host *host,
454 unsigned int timing)
455 {
456 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
457 struct dwcmshc_priv *priv = sdhci_pltfm_priv(pltfm_host);
458 u16 ctrl, ctrl_2;
459
460 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
461 /* Select Bus Speed Mode for host */
462 ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
463 if ((timing == MMC_TIMING_MMC_HS200) ||
464 (timing == MMC_TIMING_UHS_SDR104))
465 ctrl_2 |= SDHCI_CTRL_UHS_SDR104;
466 else if (timing == MMC_TIMING_UHS_SDR12)
467 ctrl_2 |= SDHCI_CTRL_UHS_SDR12;
468 else if ((timing == MMC_TIMING_UHS_SDR25) ||
469 (timing == MMC_TIMING_MMC_HS))
470 ctrl_2 |= SDHCI_CTRL_UHS_SDR25;
471 else if (timing == MMC_TIMING_UHS_SDR50)
472 ctrl_2 |= SDHCI_CTRL_UHS_SDR50;
473 else if ((timing == MMC_TIMING_UHS_DDR50) ||
474 (timing == MMC_TIMING_MMC_DDR52))
475 ctrl_2 |= SDHCI_CTRL_UHS_DDR50;
476 else if (timing == MMC_TIMING_MMC_HS400) {
477 /* set CARD_IS_EMMC bit to enable Data Strobe for HS400 */
478 ctrl = sdhci_readw(host, priv->vendor_specific_area1 + DWCMSHC_EMMC_CONTROL);
479 ctrl |= DWCMSHC_CARD_IS_EMMC;
480 sdhci_writew(host, ctrl, priv->vendor_specific_area1 + DWCMSHC_EMMC_CONTROL);
481
482 ctrl_2 |= DWCMSHC_CTRL_HS400;
483 }
484
485 if (priv->flags & FLAG_IO_FIXED_1V8)
486 ctrl_2 |= SDHCI_CTRL_VDD_180;
487 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
488 }
489
th1520_set_uhs_signaling(struct sdhci_host * host,unsigned int timing)490 static void th1520_set_uhs_signaling(struct sdhci_host *host,
491 unsigned int timing)
492 {
493 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
494 struct dwcmshc_priv *priv = sdhci_pltfm_priv(pltfm_host);
495
496 dwcmshc_set_uhs_signaling(host, timing);
497 if (timing == MMC_TIMING_MMC_HS400)
498 priv->delay_line = PHY_SDCLKDL_DC_HS400;
499 else
500 sdhci_writeb(host, 0, PHY_DLLDL_CNFG_R);
501 th1520_sdhci_set_phy(host);
502 }
503
dwcmshc_hs400_enhanced_strobe(struct mmc_host * mmc,struct mmc_ios * ios)504 static void dwcmshc_hs400_enhanced_strobe(struct mmc_host *mmc,
505 struct mmc_ios *ios)
506 {
507 u32 vendor;
508 struct sdhci_host *host = mmc_priv(mmc);
509 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
510 struct dwcmshc_priv *priv = sdhci_pltfm_priv(pltfm_host);
511 int reg = priv->vendor_specific_area1 + DWCMSHC_EMMC_CONTROL;
512
513 vendor = sdhci_readl(host, reg);
514 if (ios->enhanced_strobe)
515 vendor |= DWCMSHC_ENHANCED_STROBE;
516 else
517 vendor &= ~DWCMSHC_ENHANCED_STROBE;
518
519 sdhci_writel(host, vendor, reg);
520 }
521
dwcmshc_execute_tuning(struct mmc_host * mmc,u32 opcode)522 static int dwcmshc_execute_tuning(struct mmc_host *mmc, u32 opcode)
523 {
524 int err = sdhci_execute_tuning(mmc, opcode);
525 struct sdhci_host *host = mmc_priv(mmc);
526
527 if (err)
528 return err;
529
530 /*
531 * Tuning can leave the IP in an active state (Buffer Read Enable bit
532 * set) which prevents the entry to low power states (i.e. S0i3). Data
533 * reset will clear it.
534 */
535 sdhci_reset(host, SDHCI_RESET_DATA);
536
537 return 0;
538 }
539
dwcmshc_cqe_irq_handler(struct sdhci_host * host,u32 intmask)540 static u32 dwcmshc_cqe_irq_handler(struct sdhci_host *host, u32 intmask)
541 {
542 int cmd_error = 0;
543 int data_error = 0;
544
545 if (!sdhci_cqe_irq(host, intmask, &cmd_error, &data_error))
546 return intmask;
547
548 cqhci_irq(host->mmc, intmask, cmd_error, data_error);
549
550 return 0;
551 }
552
dwcmshc_sdhci_cqe_enable(struct mmc_host * mmc)553 static void dwcmshc_sdhci_cqe_enable(struct mmc_host *mmc)
554 {
555 struct sdhci_host *host = mmc_priv(mmc);
556 u8 ctrl;
557
558 sdhci_writew(host, DWCMSHC_SDHCI_CQE_TRNS_MODE, SDHCI_TRANSFER_MODE);
559
560 sdhci_cqe_enable(mmc);
561
562 /*
563 * The "DesignWare Cores Mobile Storage Host Controller
564 * DWC_mshc / DWC_mshc_lite Databook" says:
565 * when Host Version 4 Enable" is 1 in Host Control 2 register,
566 * SDHCI_CTRL_ADMA32 bit means ADMA2 is selected.
567 * Selection of 32-bit/64-bit System Addressing:
568 * either 32-bit or 64-bit system addressing is selected by
569 * 64-bit Addressing bit in Host Control 2 register.
570 *
571 * On the other hand the "DesignWare Cores Mobile Storage Host
572 * Controller DWC_mshc / DWC_mshc_lite User Guide" says, that we have to
573 * set DMA_SEL to ADMA2 _only_ mode in the Host Control 2 register.
574 */
575 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
576 ctrl &= ~SDHCI_CTRL_DMA_MASK;
577 ctrl |= SDHCI_CTRL_ADMA32;
578 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
579 }
580
dwcmshc_set_tran_desc(struct cqhci_host * cq_host,u8 ** desc,dma_addr_t addr,int len,bool end,bool dma64)581 static void dwcmshc_set_tran_desc(struct cqhci_host *cq_host, u8 **desc,
582 dma_addr_t addr, int len, bool end, bool dma64)
583 {
584 int tmplen, offset;
585
586 if (likely(!len || BOUNDARY_OK(addr, len))) {
587 cqhci_set_tran_desc(*desc, addr, len, end, dma64);
588 return;
589 }
590
591 offset = addr & (SZ_128M - 1);
592 tmplen = SZ_128M - offset;
593 cqhci_set_tran_desc(*desc, addr, tmplen, false, dma64);
594
595 addr += tmplen;
596 len -= tmplen;
597 *desc += cq_host->trans_desc_len;
598 cqhci_set_tran_desc(*desc, addr, len, end, dma64);
599 }
600
dwcmshc_cqhci_dumpregs(struct mmc_host * mmc)601 static void dwcmshc_cqhci_dumpregs(struct mmc_host *mmc)
602 {
603 sdhci_dumpregs(mmc_priv(mmc));
604 }
605
dwcmshc_rk3568_set_clock(struct sdhci_host * host,unsigned int clock)606 static void dwcmshc_rk3568_set_clock(struct sdhci_host *host, unsigned int clock)
607 {
608 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
609 struct dwcmshc_priv *dwc_priv = sdhci_pltfm_priv(pltfm_host);
610 struct rk35xx_priv *priv = dwc_priv->priv;
611 u8 txclk_tapnum = DLL_TXCLK_TAPNUM_DEFAULT;
612 u32 extra, reg;
613 int err;
614
615 host->mmc->actual_clock = 0;
616
617 if (clock == 0) {
618 /* Disable interface clock at initial state. */
619 sdhci_set_clock(host, clock);
620 return;
621 }
622
623 /* Rockchip platform only support 375KHz for identify mode */
624 if (clock <= 400000)
625 clock = 375000;
626
627 err = clk_set_rate(pltfm_host->clk, clock);
628 if (err)
629 dev_err(mmc_dev(host->mmc), "fail to set clock %d", clock);
630
631 sdhci_set_clock(host, clock);
632
633 /* Disable cmd conflict check */
634 reg = dwc_priv->vendor_specific_area1 + DWCMSHC_HOST_CTRL3;
635 extra = sdhci_readl(host, reg);
636 extra &= ~BIT(0);
637 sdhci_writel(host, extra, reg);
638
639 if (clock <= 52000000) {
640 /*
641 * Disable DLL and reset both of sample and drive clock.
642 * The bypass bit and start bit need to be set if DLL is not locked.
643 */
644 sdhci_writel(host, DWCMSHC_EMMC_DLL_BYPASS | DWCMSHC_EMMC_DLL_START, DWCMSHC_EMMC_DLL_CTRL);
645 sdhci_writel(host, DLL_RXCLK_ORI_GATE, DWCMSHC_EMMC_DLL_RXCLK);
646 sdhci_writel(host, 0, DWCMSHC_EMMC_DLL_TXCLK);
647 sdhci_writel(host, 0, DECMSHC_EMMC_DLL_CMDOUT);
648 /*
649 * Before switching to hs400es mode, the driver will enable
650 * enhanced strobe first. PHY needs to configure the parameters
651 * of enhanced strobe first.
652 */
653 extra = DWCMSHC_EMMC_DLL_DLYENA |
654 DLL_STRBIN_DELAY_NUM_SEL |
655 DLL_STRBIN_DELAY_NUM_DEFAULT << DLL_STRBIN_DELAY_NUM_OFFSET;
656 sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_STRBIN);
657 return;
658 }
659
660 /* Reset DLL */
661 sdhci_writel(host, BIT(1), DWCMSHC_EMMC_DLL_CTRL);
662 udelay(1);
663 sdhci_writel(host, 0x0, DWCMSHC_EMMC_DLL_CTRL);
664
665 /*
666 * We shouldn't set DLL_RXCLK_NO_INVERTER for identify mode but
667 * we must set it in higher speed mode.
668 */
669 extra = DWCMSHC_EMMC_DLL_DLYENA;
670 if (priv->devtype == DWCMSHC_RK3568)
671 extra |= DLL_RXCLK_NO_INVERTER << DWCMSHC_EMMC_DLL_RXCLK_SRCSEL;
672 sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_RXCLK);
673
674 /* Init DLL settings */
675 extra = 0x5 << DWCMSHC_EMMC_DLL_START_POINT |
676 0x2 << DWCMSHC_EMMC_DLL_INC |
677 DWCMSHC_EMMC_DLL_START;
678 sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_CTRL);
679 err = readl_poll_timeout(host->ioaddr + DWCMSHC_EMMC_DLL_STATUS0,
680 extra, DLL_LOCK_WO_TMOUT(extra), 1,
681 500 * USEC_PER_MSEC);
682 if (err) {
683 dev_err(mmc_dev(host->mmc), "DLL lock timeout!\n");
684 return;
685 }
686
687 extra = 0x1 << 16 | /* tune clock stop en */
688 0x3 << 17 | /* pre-change delay */
689 0x3 << 19; /* post-change delay */
690 sdhci_writel(host, extra, dwc_priv->vendor_specific_area1 + DWCMSHC_EMMC_ATCTRL);
691
692 if (host->mmc->ios.timing == MMC_TIMING_MMC_HS200 ||
693 host->mmc->ios.timing == MMC_TIMING_MMC_HS400)
694 txclk_tapnum = priv->txclk_tapnum;
695
696 if ((priv->devtype == DWCMSHC_RK3588) && host->mmc->ios.timing == MMC_TIMING_MMC_HS400) {
697 txclk_tapnum = DLL_TXCLK_TAPNUM_90_DEGREES;
698
699 extra = DLL_CMDOUT_SRC_CLK_NEG |
700 DLL_CMDOUT_EN_SRC_CLK_NEG |
701 DWCMSHC_EMMC_DLL_DLYENA |
702 DLL_CMDOUT_TAPNUM_90_DEGREES |
703 DLL_CMDOUT_TAPNUM_FROM_SW;
704 sdhci_writel(host, extra, DECMSHC_EMMC_DLL_CMDOUT);
705 }
706
707 extra = DWCMSHC_EMMC_DLL_DLYENA |
708 DLL_TXCLK_TAPNUM_FROM_SW |
709 DLL_RXCLK_NO_INVERTER << DWCMSHC_EMMC_DLL_RXCLK_SRCSEL |
710 txclk_tapnum;
711 sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_TXCLK);
712
713 extra = DWCMSHC_EMMC_DLL_DLYENA |
714 DLL_STRBIN_TAPNUM_DEFAULT |
715 DLL_STRBIN_TAPNUM_FROM_SW;
716 sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_STRBIN);
717 }
718
rk35xx_sdhci_reset(struct sdhci_host * host,u8 mask)719 static void rk35xx_sdhci_reset(struct sdhci_host *host, u8 mask)
720 {
721 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
722 struct dwcmshc_priv *dwc_priv = sdhci_pltfm_priv(pltfm_host);
723 struct rk35xx_priv *priv = dwc_priv->priv;
724
725 if (mask & SDHCI_RESET_ALL && priv->reset) {
726 reset_control_assert(priv->reset);
727 udelay(1);
728 reset_control_deassert(priv->reset);
729 }
730
731 sdhci_reset(host, mask);
732 }
733
dwcmshc_rk35xx_init(struct device * dev,struct sdhci_host * host,struct dwcmshc_priv * dwc_priv)734 static int dwcmshc_rk35xx_init(struct device *dev, struct sdhci_host *host,
735 struct dwcmshc_priv *dwc_priv)
736 {
737 static const char * const clk_ids[] = {"axi", "block", "timer"};
738 struct rk35xx_priv *priv;
739 int err;
740
741 priv = devm_kzalloc(dev, sizeof(struct rk35xx_priv), GFP_KERNEL);
742 if (!priv)
743 return -ENOMEM;
744
745 if (of_device_is_compatible(dev->of_node, "rockchip,rk3588-dwcmshc"))
746 priv->devtype = DWCMSHC_RK3588;
747 else
748 priv->devtype = DWCMSHC_RK3568;
749
750 priv->reset = devm_reset_control_array_get_optional_exclusive(mmc_dev(host->mmc));
751 if (IS_ERR(priv->reset)) {
752 err = PTR_ERR(priv->reset);
753 dev_err(mmc_dev(host->mmc), "failed to get reset control %d\n", err);
754 return err;
755 }
756
757 err = dwcmshc_get_enable_other_clks(mmc_dev(host->mmc), dwc_priv,
758 ARRAY_SIZE(clk_ids), clk_ids);
759 if (err)
760 return err;
761
762 if (of_property_read_u8(mmc_dev(host->mmc)->of_node, "rockchip,txclk-tapnum",
763 &priv->txclk_tapnum))
764 priv->txclk_tapnum = DLL_TXCLK_TAPNUM_DEFAULT;
765
766 /* Disable cmd conflict check */
767 sdhci_writel(host, 0x0, dwc_priv->vendor_specific_area1 + DWCMSHC_HOST_CTRL3);
768 /* Reset previous settings */
769 sdhci_writel(host, 0, DWCMSHC_EMMC_DLL_TXCLK);
770 sdhci_writel(host, 0, DWCMSHC_EMMC_DLL_STRBIN);
771
772 dwc_priv->priv = priv;
773
774 return 0;
775 }
776
dwcmshc_rk35xx_postinit(struct sdhci_host * host,struct dwcmshc_priv * dwc_priv)777 static void dwcmshc_rk35xx_postinit(struct sdhci_host *host, struct dwcmshc_priv *dwc_priv)
778 {
779 /*
780 * Don't support highspeed bus mode with low clk speed as we
781 * cannot use DLL for this condition.
782 */
783 if (host->mmc->f_max <= 52000000) {
784 dev_info(mmc_dev(host->mmc), "Disabling HS200/HS400, frequency too low (%d)\n",
785 host->mmc->f_max);
786 host->mmc->caps2 &= ~(MMC_CAP2_HS200 | MMC_CAP2_HS400);
787 host->mmc->caps &= ~(MMC_CAP_3_3V_DDR | MMC_CAP_1_8V_DDR);
788 }
789 }
790
dwcmshc_rk3576_postinit(struct sdhci_host * host,struct dwcmshc_priv * dwc_priv)791 static void dwcmshc_rk3576_postinit(struct sdhci_host *host, struct dwcmshc_priv *dwc_priv)
792 {
793 struct device *dev = mmc_dev(host->mmc);
794 int ret;
795
796 /*
797 * This works around the design of the RK3576's power domains, which
798 * makes the PD_NVM power domain, which the sdhci controller on the
799 * RK3576 is in, never come back the same way once it's run-time
800 * suspended once. This can happen during early kernel boot if no driver
801 * is using either PD_NVM or its child power domain PD_SDGMAC for a
802 * short moment, leading to it being turned off to save power. By
803 * keeping it on, sdhci suspending won't lead to PD_NVM becoming a
804 * candidate for getting turned off.
805 */
806 ret = dev_pm_genpd_rpm_always_on(dev, true);
807 if (ret && ret != -EOPNOTSUPP)
808 dev_warn(dev, "failed to set PD rpm always on, SoC may hang later: %pe\n",
809 ERR_PTR(ret));
810
811 dwcmshc_rk35xx_postinit(host, dwc_priv);
812 }
813
th1520_execute_tuning(struct sdhci_host * host,u32 opcode)814 static int th1520_execute_tuning(struct sdhci_host *host, u32 opcode)
815 {
816 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
817 struct dwcmshc_priv *priv = sdhci_pltfm_priv(pltfm_host);
818 u32 val = 0;
819
820 if (host->flags & SDHCI_HS400_TUNING)
821 return 0;
822
823 sdhci_writeb(host, FIELD_PREP(PHY_ATDL_CNFG_INPSEL_MASK, PHY_ATDL_CNFG_INPSEL),
824 PHY_ATDL_CNFG_R);
825 val = sdhci_readl(host, priv->vendor_specific_area1 + DWCMSHC_EMMC_ATCTRL);
826
827 /*
828 * configure tuning settings:
829 * - center phase select code driven in block gap interval
830 * - disable reporting of framing errors
831 * - disable software managed tuning
832 * - disable user selection of sampling window edges,
833 * instead tuning calculated edges are used
834 */
835 val &= ~(AT_CTRL_CI_SEL | AT_CTRL_RPT_TUNE_ERR | AT_CTRL_SW_TUNE_EN |
836 FIELD_PREP(AT_CTRL_WIN_EDGE_SEL_MASK, AT_CTRL_WIN_EDGE_SEL));
837
838 /*
839 * configure tuning settings:
840 * - enable auto-tuning
841 * - enable sampling window threshold
842 * - stop clocks during phase code change
843 * - set max latency in cycles between tx and rx clocks
844 * - set max latency in cycles to switch output phase
845 * - set max sampling window threshold value
846 */
847 val |= AT_CTRL_AT_EN | AT_CTRL_SWIN_TH_EN | AT_CTRL_TUNE_CLK_STOP_EN;
848 val |= FIELD_PREP(AT_CTRL_PRE_CHANGE_DLY_MASK, AT_CTRL_PRE_CHANGE_DLY);
849 val |= FIELD_PREP(AT_CTRL_POST_CHANGE_DLY_MASK, AT_CTRL_POST_CHANGE_DLY);
850 val |= FIELD_PREP(AT_CTRL_SWIN_TH_VAL_MASK, AT_CTRL_SWIN_TH_VAL);
851
852 sdhci_writel(host, val, priv->vendor_specific_area1 + DWCMSHC_EMMC_ATCTRL);
853 val = sdhci_readl(host, priv->vendor_specific_area1 + DWCMSHC_EMMC_ATCTRL);
854
855 /* perform tuning */
856 sdhci_start_tuning(host);
857 host->tuning_loop_count = 128;
858 host->tuning_err = __sdhci_execute_tuning(host, opcode);
859 if (host->tuning_err) {
860 /* disable auto-tuning upon tuning error */
861 val &= ~AT_CTRL_AT_EN;
862 sdhci_writel(host, val, priv->vendor_specific_area1 + DWCMSHC_EMMC_ATCTRL);
863 dev_err(mmc_dev(host->mmc), "tuning failed: %d\n", host->tuning_err);
864 return -EIO;
865 }
866 sdhci_end_tuning(host);
867
868 return 0;
869 }
870
th1520_sdhci_reset(struct sdhci_host * host,u8 mask)871 static void th1520_sdhci_reset(struct sdhci_host *host, u8 mask)
872 {
873 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
874 struct dwcmshc_priv *priv = sdhci_pltfm_priv(pltfm_host);
875 u16 ctrl_2;
876
877 sdhci_reset(host, mask);
878
879 /* The T-Head 1520 SoC does not comply with the SDHCI specification
880 * regarding the "Software Reset for CMD line should clear 'Command
881 * Complete' in the Normal Interrupt Status Register." Clear the bit
882 * here to compensate for this quirk.
883 */
884 if (mask & SDHCI_RESET_CMD)
885 sdhci_writel(host, SDHCI_INT_RESPONSE, SDHCI_INT_STATUS);
886
887 if (priv->flags & FLAG_IO_FIXED_1V8) {
888 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
889 if (!(ctrl_2 & SDHCI_CTRL_VDD_180)) {
890 ctrl_2 |= SDHCI_CTRL_VDD_180;
891 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
892 }
893 }
894 }
895
th1520_init(struct device * dev,struct sdhci_host * host,struct dwcmshc_priv * dwc_priv)896 static int th1520_init(struct device *dev,
897 struct sdhci_host *host,
898 struct dwcmshc_priv *dwc_priv)
899 {
900 dwc_priv->delay_line = PHY_SDCLKDL_DC_DEFAULT;
901
902 if (device_property_read_bool(dev, "mmc-ddr-1_8v") ||
903 device_property_read_bool(dev, "mmc-hs200-1_8v") ||
904 device_property_read_bool(dev, "mmc-hs400-1_8v"))
905 dwc_priv->flags |= FLAG_IO_FIXED_1V8;
906 else
907 dwc_priv->flags &= ~FLAG_IO_FIXED_1V8;
908
909 /*
910 * start_signal_voltage_switch() will try 3.3V first
911 * then 1.8V. Use SDHCI_SIGNALING_180 rather than
912 * SDHCI_SIGNALING_330 to avoid setting voltage to 3.3V
913 * in sdhci_start_signal_voltage_switch().
914 */
915 if (dwc_priv->flags & FLAG_IO_FIXED_1V8) {
916 host->flags &= ~SDHCI_SIGNALING_330;
917 host->flags |= SDHCI_SIGNALING_180;
918 }
919
920 sdhci_enable_v4_mode(host);
921
922 return 0;
923 }
924
cv18xx_sdhci_reset(struct sdhci_host * host,u8 mask)925 static void cv18xx_sdhci_reset(struct sdhci_host *host, u8 mask)
926 {
927 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
928 struct dwcmshc_priv *priv = sdhci_pltfm_priv(pltfm_host);
929 u32 val, emmc_caps = MMC_CAP2_NO_SD | MMC_CAP2_NO_SDIO;
930
931 sdhci_reset(host, mask);
932
933 if ((host->mmc->caps2 & emmc_caps) == emmc_caps) {
934 val = sdhci_readl(host, priv->vendor_specific_area1 + CV18XX_SDHCI_MSHC_CTRL);
935 val |= CV18XX_EMMC_FUNC_EN;
936 sdhci_writel(host, val, priv->vendor_specific_area1 + CV18XX_SDHCI_MSHC_CTRL);
937 }
938
939 val = sdhci_readl(host, priv->vendor_specific_area1 + CV18XX_SDHCI_MSHC_CTRL);
940 val |= CV18XX_LATANCY_1T;
941 sdhci_writel(host, val, priv->vendor_specific_area1 + CV18XX_SDHCI_MSHC_CTRL);
942
943 val = sdhci_readl(host, priv->vendor_specific_area1 + CV18XX_SDHCI_PHY_CONFIG);
944 val |= CV18XX_PHY_TX_BPS;
945 sdhci_writel(host, val, priv->vendor_specific_area1 + CV18XX_SDHCI_PHY_CONFIG);
946
947 val = (FIELD_PREP(CV18XX_PHY_TX_DLY_MSK, 0) |
948 FIELD_PREP(CV18XX_PHY_TX_SRC_MSK, CV18XX_PHY_TX_SRC_INVERT_CLK_TX) |
949 FIELD_PREP(CV18XX_PHY_RX_DLY_MSK, 0) |
950 FIELD_PREP(CV18XX_PHY_RX_SRC_MSK, CV18XX_PHY_RX_SRC_INVERT_RX_CLK));
951 sdhci_writel(host, val, priv->vendor_specific_area1 + CV18XX_SDHCI_PHY_TX_RX_DLY);
952 }
953
cv18xx_sdhci_set_tap(struct sdhci_host * host,int tap)954 static void cv18xx_sdhci_set_tap(struct sdhci_host *host, int tap)
955 {
956 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
957 struct dwcmshc_priv *priv = sdhci_pltfm_priv(pltfm_host);
958 u16 clk;
959 u32 val;
960
961 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
962 clk &= ~SDHCI_CLOCK_CARD_EN;
963 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
964
965 val = sdhci_readl(host, priv->vendor_specific_area1 + CV18XX_SDHCI_MSHC_CTRL);
966 val &= ~CV18XX_LATANCY_1T;
967 sdhci_writel(host, val, priv->vendor_specific_area1 + CV18XX_SDHCI_MSHC_CTRL);
968
969 val = (FIELD_PREP(CV18XX_PHY_TX_DLY_MSK, 0) |
970 FIELD_PREP(CV18XX_PHY_TX_SRC_MSK, CV18XX_PHY_TX_SRC_INVERT_CLK_TX) |
971 FIELD_PREP(CV18XX_PHY_RX_DLY_MSK, tap));
972 sdhci_writel(host, val, priv->vendor_specific_area1 + CV18XX_SDHCI_PHY_TX_RX_DLY);
973
974 sdhci_writel(host, 0, priv->vendor_specific_area1 + CV18XX_SDHCI_PHY_CONFIG);
975
976 clk |= SDHCI_CLOCK_CARD_EN;
977 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
978 usleep_range(1000, 2000);
979 }
980
cv18xx_retry_tuning(struct mmc_host * mmc,u32 opcode,int * cmd_error)981 static int cv18xx_retry_tuning(struct mmc_host *mmc, u32 opcode, int *cmd_error)
982 {
983 int ret, retry = 0;
984
985 while (retry < CV18XX_RETRY_TUNING_MAX) {
986 ret = mmc_send_tuning(mmc, opcode, NULL);
987 if (ret)
988 return ret;
989 retry++;
990 }
991
992 return 0;
993 }
994
cv18xx_sdhci_post_tuning(struct sdhci_host * host)995 static void cv18xx_sdhci_post_tuning(struct sdhci_host *host)
996 {
997 u32 val;
998
999 val = sdhci_readl(host, SDHCI_INT_STATUS);
1000 val |= SDHCI_INT_DATA_AVAIL;
1001 sdhci_writel(host, val, SDHCI_INT_STATUS);
1002
1003 sdhci_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
1004 }
1005
cv18xx_sdhci_execute_tuning(struct sdhci_host * host,u32 opcode)1006 static int cv18xx_sdhci_execute_tuning(struct sdhci_host *host, u32 opcode)
1007 {
1008 int min, max, avg, ret;
1009 int win_length, target_min, target_max, target_win_length;
1010
1011 min = max = 0;
1012 target_win_length = 0;
1013
1014 sdhci_reset_tuning(host);
1015
1016 while (max < CV18XX_TUNE_MAX) {
1017 /* find the mininum delay first which can pass tuning */
1018 while (min < CV18XX_TUNE_MAX) {
1019 cv18xx_sdhci_set_tap(host, min);
1020 if (!cv18xx_retry_tuning(host->mmc, opcode, NULL))
1021 break;
1022 min += CV18XX_TUNE_STEP;
1023 }
1024
1025 /* find the maxinum delay which can not pass tuning */
1026 max = min + CV18XX_TUNE_STEP;
1027 while (max < CV18XX_TUNE_MAX) {
1028 cv18xx_sdhci_set_tap(host, max);
1029 if (cv18xx_retry_tuning(host->mmc, opcode, NULL)) {
1030 max -= CV18XX_TUNE_STEP;
1031 break;
1032 }
1033 max += CV18XX_TUNE_STEP;
1034 }
1035
1036 win_length = max - min + 1;
1037 /* get the largest pass window */
1038 if (win_length > target_win_length) {
1039 target_win_length = win_length;
1040 target_min = min;
1041 target_max = max;
1042 }
1043
1044 /* continue to find the next pass window */
1045 min = max + CV18XX_TUNE_STEP;
1046 }
1047
1048 cv18xx_sdhci_post_tuning(host);
1049
1050 /* use average delay to get the best timing */
1051 avg = (target_min + target_max) / 2;
1052 cv18xx_sdhci_set_tap(host, avg);
1053 ret = mmc_send_tuning(host->mmc, opcode, NULL);
1054
1055 dev_dbg(mmc_dev(host->mmc), "tuning %s at 0x%x ret %d\n",
1056 ret ? "failed" : "passed", avg, ret);
1057
1058 return ret;
1059 }
1060
sg2042_sdhci_phy_init(struct sdhci_host * host)1061 static inline void sg2042_sdhci_phy_init(struct sdhci_host *host)
1062 {
1063 u32 val;
1064
1065 /* Asset phy reset & set tx drive strength */
1066 val = sdhci_readl(host, PHY_CNFG_R);
1067 val &= ~PHY_CNFG_RSTN_DEASSERT;
1068 val |= FIELD_PREP(PHY_CNFG_PHY_PWRGOOD_MASK, 1);
1069 val |= FIELD_PREP(PHY_CNFG_PAD_SP_MASK, PHY_CNFG_PAD_SP_SG2042);
1070 val |= FIELD_PREP(PHY_CNFG_PAD_SN_MASK, PHY_CNFG_PAD_SN_SG2042);
1071 sdhci_writel(host, val, PHY_CNFG_R);
1072
1073 /* Configure phy pads */
1074 val = PHY_PAD_RXSEL_3V3;
1075 val |= FIELD_PREP(PHY_PAD_WEAKPULL_MASK, PHY_PAD_WEAKPULL_PULLUP);
1076 val |= FIELD_PREP(PHY_PAD_TXSLEW_CTRL_P_MASK, PHY_PAD_TXSLEW_CTRL_P);
1077 val |= FIELD_PREP(PHY_PAD_TXSLEW_CTRL_N_MASK, PHY_PAD_TXSLEW_CTRL_N_SG2042);
1078 sdhci_writew(host, val, PHY_CMDPAD_CNFG_R);
1079 sdhci_writew(host, val, PHY_DATAPAD_CNFG_R);
1080 sdhci_writew(host, val, PHY_RSTNPAD_CNFG_R);
1081
1082 val = PHY_PAD_RXSEL_3V3;
1083 val |= FIELD_PREP(PHY_PAD_TXSLEW_CTRL_P_MASK, PHY_PAD_TXSLEW_CTRL_P);
1084 val |= FIELD_PREP(PHY_PAD_TXSLEW_CTRL_N_MASK, PHY_PAD_TXSLEW_CTRL_N_SG2042);
1085 sdhci_writew(host, val, PHY_CLKPAD_CNFG_R);
1086
1087 val = PHY_PAD_RXSEL_3V3;
1088 val |= FIELD_PREP(PHY_PAD_WEAKPULL_MASK, PHY_PAD_WEAKPULL_PULLDOWN);
1089 val |= FIELD_PREP(PHY_PAD_TXSLEW_CTRL_P_MASK, PHY_PAD_TXSLEW_CTRL_P);
1090 val |= FIELD_PREP(PHY_PAD_TXSLEW_CTRL_N_MASK, PHY_PAD_TXSLEW_CTRL_N_SG2042);
1091 sdhci_writew(host, val, PHY_STBPAD_CNFG_R);
1092
1093 /* Configure delay line */
1094 /* Enable fixed delay */
1095 sdhci_writeb(host, PHY_SDCLKDL_CNFG_EXTDLY_EN, PHY_SDCLKDL_CNFG_R);
1096 /*
1097 * Set delay line.
1098 * Its recommended that bit UPDATE_DC[4] is 1 when SDCLKDL_DC is being written.
1099 * Ensure UPDATE_DC[4] is '0' when not updating code.
1100 */
1101 val = sdhci_readb(host, PHY_SDCLKDL_CNFG_R);
1102 val |= PHY_SDCLKDL_CNFG_UPDATE;
1103 sdhci_writeb(host, val, PHY_SDCLKDL_CNFG_R);
1104 /* Add 10 * 70ps = 0.7ns for output delay */
1105 sdhci_writeb(host, 10, PHY_SDCLKDL_DC_R);
1106 val = sdhci_readb(host, PHY_SDCLKDL_CNFG_R);
1107 val &= ~(PHY_SDCLKDL_CNFG_UPDATE);
1108 sdhci_writeb(host, val, PHY_SDCLKDL_CNFG_R);
1109
1110 /* Set SMPLDL_CNFG, Bypass */
1111 sdhci_writeb(host, PHY_SMPLDL_CNFG_BYPASS_EN, PHY_SMPLDL_CNFG_R);
1112
1113 /* Set ATDL_CNFG, tuning clk not use for init */
1114 val = FIELD_PREP(PHY_ATDL_CNFG_INPSEL_MASK, PHY_ATDL_CNFG_INPSEL_SG2042);
1115 sdhci_writeb(host, val, PHY_ATDL_CNFG_R);
1116
1117 /* Deasset phy reset */
1118 val = sdhci_readl(host, PHY_CNFG_R);
1119 val |= PHY_CNFG_RSTN_DEASSERT;
1120 sdhci_writel(host, val, PHY_CNFG_R);
1121 }
1122
sg2042_sdhci_reset(struct sdhci_host * host,u8 mask)1123 static void sg2042_sdhci_reset(struct sdhci_host *host, u8 mask)
1124 {
1125 sdhci_reset(host, mask);
1126
1127 if (mask & SDHCI_RESET_ALL)
1128 sg2042_sdhci_phy_init(host);
1129 }
1130
sg2042_init(struct device * dev,struct sdhci_host * host,struct dwcmshc_priv * dwc_priv)1131 static int sg2042_init(struct device *dev, struct sdhci_host *host,
1132 struct dwcmshc_priv *dwc_priv)
1133 {
1134 static const char * const clk_ids[] = {"timer"};
1135
1136 return dwcmshc_get_enable_other_clks(mmc_dev(host->mmc), dwc_priv,
1137 ARRAY_SIZE(clk_ids), clk_ids);
1138 }
1139
1140 static const struct sdhci_ops sdhci_dwcmshc_ops = {
1141 .set_clock = sdhci_set_clock,
1142 .set_bus_width = sdhci_set_bus_width,
1143 .set_uhs_signaling = dwcmshc_set_uhs_signaling,
1144 .get_max_clock = dwcmshc_get_max_clock,
1145 .reset = sdhci_reset,
1146 .adma_write_desc = dwcmshc_adma_write_desc,
1147 .irq = dwcmshc_cqe_irq_handler,
1148 };
1149
1150 #ifdef CONFIG_ACPI
dwcmshc_bf3_hw_reset(struct sdhci_host * host)1151 static void dwcmshc_bf3_hw_reset(struct sdhci_host *host)
1152 {
1153 struct arm_smccc_res res = { 0 };
1154
1155 arm_smccc_smc(BLUEFIELD_SMC_SET_EMMC_RST_N, 0, 0, 0, 0, 0, 0, 0, &res);
1156
1157 if (res.a0)
1158 pr_err("%s: RST_N failed.\n", mmc_hostname(host->mmc));
1159 }
1160
1161 static const struct sdhci_ops sdhci_dwcmshc_bf3_ops = {
1162 .set_clock = sdhci_set_clock,
1163 .set_bus_width = sdhci_set_bus_width,
1164 .set_uhs_signaling = dwcmshc_set_uhs_signaling,
1165 .get_max_clock = dwcmshc_get_max_clock,
1166 .reset = sdhci_reset,
1167 .adma_write_desc = dwcmshc_adma_write_desc,
1168 .irq = dwcmshc_cqe_irq_handler,
1169 .hw_reset = dwcmshc_bf3_hw_reset,
1170 };
1171 #endif
1172
1173 static const struct sdhci_ops sdhci_dwcmshc_rk35xx_ops = {
1174 .set_clock = dwcmshc_rk3568_set_clock,
1175 .set_bus_width = sdhci_set_bus_width,
1176 .set_uhs_signaling = dwcmshc_set_uhs_signaling,
1177 .get_max_clock = rk35xx_get_max_clock,
1178 .reset = rk35xx_sdhci_reset,
1179 .adma_write_desc = dwcmshc_adma_write_desc,
1180 .irq = dwcmshc_cqe_irq_handler,
1181 };
1182
1183 static const struct sdhci_ops sdhci_dwcmshc_th1520_ops = {
1184 .set_clock = sdhci_set_clock,
1185 .set_bus_width = sdhci_set_bus_width,
1186 .set_uhs_signaling = th1520_set_uhs_signaling,
1187 .get_max_clock = dwcmshc_get_max_clock,
1188 .reset = th1520_sdhci_reset,
1189 .adma_write_desc = dwcmshc_adma_write_desc,
1190 .voltage_switch = dwcmshc_phy_1_8v_init,
1191 .platform_execute_tuning = th1520_execute_tuning,
1192 };
1193
1194 static const struct sdhci_ops sdhci_dwcmshc_cv18xx_ops = {
1195 .set_clock = sdhci_set_clock,
1196 .set_bus_width = sdhci_set_bus_width,
1197 .set_uhs_signaling = dwcmshc_set_uhs_signaling,
1198 .get_max_clock = dwcmshc_get_max_clock,
1199 .reset = cv18xx_sdhci_reset,
1200 .adma_write_desc = dwcmshc_adma_write_desc,
1201 .platform_execute_tuning = cv18xx_sdhci_execute_tuning,
1202 };
1203
1204 static const struct sdhci_ops sdhci_dwcmshc_sg2042_ops = {
1205 .set_clock = sdhci_set_clock,
1206 .set_bus_width = sdhci_set_bus_width,
1207 .set_uhs_signaling = dwcmshc_set_uhs_signaling,
1208 .get_max_clock = dwcmshc_get_max_clock,
1209 .reset = sg2042_sdhci_reset,
1210 .adma_write_desc = dwcmshc_adma_write_desc,
1211 .platform_execute_tuning = th1520_execute_tuning,
1212 };
1213
1214 static const struct dwcmshc_pltfm_data sdhci_dwcmshc_pdata = {
1215 .pdata = {
1216 .ops = &sdhci_dwcmshc_ops,
1217 .quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN,
1218 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
1219 },
1220 };
1221
1222 #ifdef CONFIG_ACPI
1223 static const struct dwcmshc_pltfm_data sdhci_dwcmshc_bf3_pdata = {
1224 .pdata = {
1225 .ops = &sdhci_dwcmshc_bf3_ops,
1226 .quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN,
1227 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
1228 SDHCI_QUIRK2_ACMD23_BROKEN,
1229 },
1230 };
1231 #endif
1232
1233 static const struct dwcmshc_pltfm_data sdhci_dwcmshc_rk35xx_pdata = {
1234 .pdata = {
1235 .ops = &sdhci_dwcmshc_rk35xx_ops,
1236 .quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN |
1237 SDHCI_QUIRK_BROKEN_TIMEOUT_VAL,
1238 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
1239 SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN,
1240 },
1241 .init = dwcmshc_rk35xx_init,
1242 .postinit = dwcmshc_rk35xx_postinit,
1243 };
1244
1245 static const struct dwcmshc_pltfm_data sdhci_dwcmshc_rk3576_pdata = {
1246 .pdata = {
1247 .ops = &sdhci_dwcmshc_rk35xx_ops,
1248 .quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN |
1249 SDHCI_QUIRK_BROKEN_TIMEOUT_VAL,
1250 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
1251 SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN,
1252 },
1253 .init = dwcmshc_rk35xx_init,
1254 .postinit = dwcmshc_rk3576_postinit,
1255 };
1256
1257 static const struct dwcmshc_pltfm_data sdhci_dwcmshc_th1520_pdata = {
1258 .pdata = {
1259 .ops = &sdhci_dwcmshc_th1520_ops,
1260 .quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN,
1261 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
1262 },
1263 .init = th1520_init,
1264 };
1265
1266 static const struct dwcmshc_pltfm_data sdhci_dwcmshc_cv18xx_pdata = {
1267 .pdata = {
1268 .ops = &sdhci_dwcmshc_cv18xx_ops,
1269 .quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN,
1270 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
1271 },
1272 };
1273
1274 static const struct dwcmshc_pltfm_data sdhci_dwcmshc_sg2042_pdata = {
1275 .pdata = {
1276 .ops = &sdhci_dwcmshc_sg2042_ops,
1277 .quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN,
1278 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
1279 },
1280 .init = sg2042_init,
1281 };
1282
1283 static const struct cqhci_host_ops dwcmshc_cqhci_ops = {
1284 .enable = dwcmshc_sdhci_cqe_enable,
1285 .disable = sdhci_cqe_disable,
1286 .dumpregs = dwcmshc_cqhci_dumpregs,
1287 .set_tran_desc = dwcmshc_set_tran_desc,
1288 };
1289
dwcmshc_cqhci_init(struct sdhci_host * host,struct platform_device * pdev)1290 static void dwcmshc_cqhci_init(struct sdhci_host *host, struct platform_device *pdev)
1291 {
1292 struct cqhci_host *cq_host;
1293 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1294 struct dwcmshc_priv *priv = sdhci_pltfm_priv(pltfm_host);
1295 bool dma64 = false;
1296 u16 clk;
1297 int err;
1298
1299 host->mmc->caps2 |= MMC_CAP2_CQE | MMC_CAP2_CQE_DCMD;
1300 cq_host = devm_kzalloc(&pdev->dev, sizeof(*cq_host), GFP_KERNEL);
1301 if (!cq_host) {
1302 dev_err(mmc_dev(host->mmc), "Unable to setup CQE: not enough memory\n");
1303 goto dsbl_cqe_caps;
1304 }
1305
1306 /*
1307 * For dwcmshc host controller we have to enable internal clock
1308 * before access to some registers from Vendor Specific Area 2.
1309 */
1310 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1311 clk |= SDHCI_CLOCK_INT_EN;
1312 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1313 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1314 if (!(clk & SDHCI_CLOCK_INT_EN)) {
1315 dev_err(mmc_dev(host->mmc), "Unable to setup CQE: internal clock enable error\n");
1316 goto free_cq_host;
1317 }
1318
1319 cq_host->mmio = host->ioaddr + priv->vendor_specific_area2;
1320 cq_host->ops = &dwcmshc_cqhci_ops;
1321
1322 /* Enable using of 128-bit task descriptors */
1323 dma64 = host->flags & SDHCI_USE_64_BIT_DMA;
1324 if (dma64) {
1325 dev_dbg(mmc_dev(host->mmc), "128-bit task descriptors\n");
1326 cq_host->caps |= CQHCI_TASK_DESC_SZ_128;
1327 }
1328 err = cqhci_init(cq_host, host->mmc, dma64);
1329 if (err) {
1330 dev_err(mmc_dev(host->mmc), "Unable to setup CQE: error %d\n", err);
1331 goto int_clock_disable;
1332 }
1333
1334 dev_dbg(mmc_dev(host->mmc), "CQE init done\n");
1335
1336 return;
1337
1338 int_clock_disable:
1339 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1340 clk &= ~SDHCI_CLOCK_INT_EN;
1341 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1342
1343 free_cq_host:
1344 devm_kfree(&pdev->dev, cq_host);
1345
1346 dsbl_cqe_caps:
1347 host->mmc->caps2 &= ~(MMC_CAP2_CQE | MMC_CAP2_CQE_DCMD);
1348 }
1349
1350 static const struct of_device_id sdhci_dwcmshc_dt_ids[] = {
1351 {
1352 .compatible = "rockchip,rk3588-dwcmshc",
1353 .data = &sdhci_dwcmshc_rk35xx_pdata,
1354 },
1355 {
1356 .compatible = "rockchip,rk3576-dwcmshc",
1357 .data = &sdhci_dwcmshc_rk3576_pdata,
1358 },
1359 {
1360 .compatible = "rockchip,rk3568-dwcmshc",
1361 .data = &sdhci_dwcmshc_rk35xx_pdata,
1362 },
1363 {
1364 .compatible = "snps,dwcmshc-sdhci",
1365 .data = &sdhci_dwcmshc_pdata,
1366 },
1367 {
1368 .compatible = "sophgo,cv1800b-dwcmshc",
1369 .data = &sdhci_dwcmshc_cv18xx_pdata,
1370 },
1371 {
1372 .compatible = "sophgo,sg2002-dwcmshc",
1373 .data = &sdhci_dwcmshc_cv18xx_pdata,
1374 },
1375 {
1376 .compatible = "thead,th1520-dwcmshc",
1377 .data = &sdhci_dwcmshc_th1520_pdata,
1378 },
1379 {
1380 .compatible = "sophgo,sg2042-dwcmshc",
1381 .data = &sdhci_dwcmshc_sg2042_pdata,
1382 },
1383 {},
1384 };
1385 MODULE_DEVICE_TABLE(of, sdhci_dwcmshc_dt_ids);
1386
1387 #ifdef CONFIG_ACPI
1388 static const struct acpi_device_id sdhci_dwcmshc_acpi_ids[] = {
1389 {
1390 .id = "MLNXBF30",
1391 .driver_data = (kernel_ulong_t)&sdhci_dwcmshc_bf3_pdata,
1392 },
1393 {}
1394 };
1395 MODULE_DEVICE_TABLE(acpi, sdhci_dwcmshc_acpi_ids);
1396 #endif
1397
dwcmshc_probe(struct platform_device * pdev)1398 static int dwcmshc_probe(struct platform_device *pdev)
1399 {
1400 struct device *dev = &pdev->dev;
1401 struct sdhci_pltfm_host *pltfm_host;
1402 struct sdhci_host *host;
1403 struct dwcmshc_priv *priv;
1404 const struct dwcmshc_pltfm_data *pltfm_data;
1405 int err;
1406 u32 extra, caps;
1407
1408 pltfm_data = device_get_match_data(&pdev->dev);
1409 if (!pltfm_data) {
1410 dev_err(&pdev->dev, "Error: No device match data found\n");
1411 return -ENODEV;
1412 }
1413
1414 host = sdhci_pltfm_init(pdev, &pltfm_data->pdata,
1415 sizeof(struct dwcmshc_priv));
1416 if (IS_ERR(host))
1417 return PTR_ERR(host);
1418
1419 /*
1420 * extra adma table cnt for cross 128M boundary handling.
1421 */
1422 extra = DIV_ROUND_UP_ULL(dma_get_required_mask(dev), SZ_128M);
1423 if (extra > SDHCI_MAX_SEGS)
1424 extra = SDHCI_MAX_SEGS;
1425 host->adma_table_cnt += extra;
1426
1427 pltfm_host = sdhci_priv(host);
1428 priv = sdhci_pltfm_priv(pltfm_host);
1429
1430 if (dev->of_node) {
1431 pltfm_host->clk = devm_clk_get(dev, "core");
1432 if (IS_ERR(pltfm_host->clk)) {
1433 err = PTR_ERR(pltfm_host->clk);
1434 dev_err(dev, "failed to get core clk: %d\n", err);
1435 goto free_pltfm;
1436 }
1437 err = clk_prepare_enable(pltfm_host->clk);
1438 if (err)
1439 goto free_pltfm;
1440
1441 priv->bus_clk = devm_clk_get(dev, "bus");
1442 if (!IS_ERR(priv->bus_clk))
1443 clk_prepare_enable(priv->bus_clk);
1444 }
1445
1446 err = mmc_of_parse(host->mmc);
1447 if (err)
1448 goto err_clk;
1449
1450 sdhci_get_of_property(pdev);
1451
1452 priv->vendor_specific_area1 =
1453 sdhci_readl(host, DWCMSHC_P_VENDOR_AREA1) & DWCMSHC_AREA1_MASK;
1454
1455 host->mmc_host_ops.request = dwcmshc_request;
1456 host->mmc_host_ops.hs400_enhanced_strobe = dwcmshc_hs400_enhanced_strobe;
1457 host->mmc_host_ops.execute_tuning = dwcmshc_execute_tuning;
1458
1459 if (pltfm_data->init) {
1460 err = pltfm_data->init(&pdev->dev, host, priv);
1461 if (err)
1462 goto err_clk;
1463 }
1464
1465 #ifdef CONFIG_ACPI
1466 if (pltfm_data == &sdhci_dwcmshc_bf3_pdata)
1467 sdhci_enable_v4_mode(host);
1468 #endif
1469
1470 caps = sdhci_readl(host, SDHCI_CAPABILITIES);
1471 if (caps & SDHCI_CAN_64BIT_V4)
1472 sdhci_enable_v4_mode(host);
1473
1474 host->mmc->caps |= MMC_CAP_WAIT_WHILE_BUSY;
1475
1476 pm_runtime_get_noresume(dev);
1477 pm_runtime_set_active(dev);
1478 pm_runtime_enable(dev);
1479
1480 err = sdhci_setup_host(host);
1481 if (err)
1482 goto err_rpm;
1483
1484 /* Setup Command Queue Engine if enabled */
1485 if (device_property_read_bool(&pdev->dev, "supports-cqe")) {
1486 priv->vendor_specific_area2 =
1487 sdhci_readw(host, DWCMSHC_P_VENDOR_AREA2);
1488
1489 dwcmshc_cqhci_init(host, pdev);
1490 }
1491
1492 if (pltfm_data->postinit)
1493 pltfm_data->postinit(host, priv);
1494
1495 err = __sdhci_add_host(host);
1496 if (err)
1497 goto err_setup_host;
1498
1499 pm_runtime_put(dev);
1500
1501 return 0;
1502
1503 err_setup_host:
1504 sdhci_cleanup_host(host);
1505 err_rpm:
1506 pm_runtime_disable(dev);
1507 pm_runtime_put_noidle(dev);
1508 err_clk:
1509 clk_disable_unprepare(pltfm_host->clk);
1510 clk_disable_unprepare(priv->bus_clk);
1511 clk_bulk_disable_unprepare(priv->num_other_clks, priv->other_clks);
1512 free_pltfm:
1513 sdhci_pltfm_free(pdev);
1514 return err;
1515 }
1516
dwcmshc_disable_card_clk(struct sdhci_host * host)1517 static void dwcmshc_disable_card_clk(struct sdhci_host *host)
1518 {
1519 u16 ctrl;
1520
1521 ctrl = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1522 if (ctrl & SDHCI_CLOCK_CARD_EN) {
1523 ctrl &= ~SDHCI_CLOCK_CARD_EN;
1524 sdhci_writew(host, ctrl, SDHCI_CLOCK_CONTROL);
1525 }
1526 }
1527
dwcmshc_remove(struct platform_device * pdev)1528 static void dwcmshc_remove(struct platform_device *pdev)
1529 {
1530 struct sdhci_host *host = platform_get_drvdata(pdev);
1531 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1532 struct dwcmshc_priv *priv = sdhci_pltfm_priv(pltfm_host);
1533
1534 pm_runtime_get_sync(&pdev->dev);
1535 pm_runtime_disable(&pdev->dev);
1536 pm_runtime_put_noidle(&pdev->dev);
1537
1538 sdhci_remove_host(host, 0);
1539
1540 dwcmshc_disable_card_clk(host);
1541
1542 clk_disable_unprepare(pltfm_host->clk);
1543 clk_disable_unprepare(priv->bus_clk);
1544 clk_bulk_disable_unprepare(priv->num_other_clks, priv->other_clks);
1545 sdhci_pltfm_free(pdev);
1546 }
1547
1548 #ifdef CONFIG_PM_SLEEP
dwcmshc_suspend(struct device * dev)1549 static int dwcmshc_suspend(struct device *dev)
1550 {
1551 struct sdhci_host *host = dev_get_drvdata(dev);
1552 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1553 struct dwcmshc_priv *priv = sdhci_pltfm_priv(pltfm_host);
1554 int ret;
1555
1556 pm_runtime_resume(dev);
1557
1558 if (host->mmc->caps2 & MMC_CAP2_CQE) {
1559 ret = cqhci_suspend(host->mmc);
1560 if (ret)
1561 return ret;
1562 }
1563
1564 ret = sdhci_suspend_host(host);
1565 if (ret)
1566 return ret;
1567
1568 clk_disable_unprepare(pltfm_host->clk);
1569 if (!IS_ERR(priv->bus_clk))
1570 clk_disable_unprepare(priv->bus_clk);
1571
1572 clk_bulk_disable_unprepare(priv->num_other_clks, priv->other_clks);
1573
1574 return ret;
1575 }
1576
dwcmshc_resume(struct device * dev)1577 static int dwcmshc_resume(struct device *dev)
1578 {
1579 struct sdhci_host *host = dev_get_drvdata(dev);
1580 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1581 struct dwcmshc_priv *priv = sdhci_pltfm_priv(pltfm_host);
1582 int ret;
1583
1584 ret = clk_prepare_enable(pltfm_host->clk);
1585 if (ret)
1586 return ret;
1587
1588 if (!IS_ERR(priv->bus_clk)) {
1589 ret = clk_prepare_enable(priv->bus_clk);
1590 if (ret)
1591 goto disable_clk;
1592 }
1593
1594 ret = clk_bulk_prepare_enable(priv->num_other_clks, priv->other_clks);
1595 if (ret)
1596 goto disable_bus_clk;
1597
1598 ret = sdhci_resume_host(host);
1599 if (ret)
1600 goto disable_other_clks;
1601
1602 if (host->mmc->caps2 & MMC_CAP2_CQE) {
1603 ret = cqhci_resume(host->mmc);
1604 if (ret)
1605 goto disable_other_clks;
1606 }
1607
1608 return 0;
1609
1610 disable_other_clks:
1611 clk_bulk_disable_unprepare(priv->num_other_clks, priv->other_clks);
1612 disable_bus_clk:
1613 if (!IS_ERR(priv->bus_clk))
1614 clk_disable_unprepare(priv->bus_clk);
1615 disable_clk:
1616 clk_disable_unprepare(pltfm_host->clk);
1617 return ret;
1618 }
1619 #endif
1620
1621 #ifdef CONFIG_PM
1622
dwcmshc_enable_card_clk(struct sdhci_host * host)1623 static void dwcmshc_enable_card_clk(struct sdhci_host *host)
1624 {
1625 u16 ctrl;
1626
1627 ctrl = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1628 if ((ctrl & SDHCI_CLOCK_INT_EN) && !(ctrl & SDHCI_CLOCK_CARD_EN)) {
1629 ctrl |= SDHCI_CLOCK_CARD_EN;
1630 sdhci_writew(host, ctrl, SDHCI_CLOCK_CONTROL);
1631 }
1632 }
1633
dwcmshc_runtime_suspend(struct device * dev)1634 static int dwcmshc_runtime_suspend(struct device *dev)
1635 {
1636 struct sdhci_host *host = dev_get_drvdata(dev);
1637
1638 dwcmshc_disable_card_clk(host);
1639
1640 return 0;
1641 }
1642
dwcmshc_runtime_resume(struct device * dev)1643 static int dwcmshc_runtime_resume(struct device *dev)
1644 {
1645 struct sdhci_host *host = dev_get_drvdata(dev);
1646
1647 dwcmshc_enable_card_clk(host);
1648
1649 return 0;
1650 }
1651
1652 #endif
1653
1654 static const struct dev_pm_ops dwcmshc_pmops = {
1655 SET_SYSTEM_SLEEP_PM_OPS(dwcmshc_suspend, dwcmshc_resume)
1656 SET_RUNTIME_PM_OPS(dwcmshc_runtime_suspend,
1657 dwcmshc_runtime_resume, NULL)
1658 };
1659
1660 static struct platform_driver sdhci_dwcmshc_driver = {
1661 .driver = {
1662 .name = "sdhci-dwcmshc",
1663 .probe_type = PROBE_PREFER_ASYNCHRONOUS,
1664 .of_match_table = sdhci_dwcmshc_dt_ids,
1665 .acpi_match_table = ACPI_PTR(sdhci_dwcmshc_acpi_ids),
1666 .pm = &dwcmshc_pmops,
1667 },
1668 .probe = dwcmshc_probe,
1669 .remove_new = dwcmshc_remove,
1670 };
1671 module_platform_driver(sdhci_dwcmshc_driver);
1672
1673 MODULE_DESCRIPTION("SDHCI platform driver for Synopsys DWC MSHC");
1674 MODULE_AUTHOR("Jisheng Zhang <jszhang@kernel.org>");
1675 MODULE_LICENSE("GPL v2");
1676