1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * sdhci_am654.c - SDHCI driver for TI's AM654 SOCs
4 *
5 * Copyright (C) 2018 Texas Instruments Incorporated - https://www.ti.com
6 *
7 */
8 #include <linux/clk.h>
9 #include <linux/iopoll.h>
10 #include <linux/of.h>
11 #include <linux/module.h>
12 #include <linux/pm_runtime.h>
13 #include <linux/property.h>
14 #include <linux/regmap.h>
15 #include <linux/sys_soc.h>
16
17 #include "cqhci.h"
18 #include "sdhci-cqhci.h"
19 #include "sdhci-pltfm.h"
20
21 /* CTL_CFG Registers */
22 #define CTL_CFG_2 0x14
23 #define CTL_CFG_3 0x18
24
25 #define SLOTTYPE_MASK GENMASK(31, 30)
26 #define SLOTTYPE_EMBEDDED BIT(30)
27 #define TUNINGFORSDR50_MASK BIT(13)
28
29 /* PHY Registers */
30 #define PHY_CTRL1 0x100
31 #define PHY_CTRL2 0x104
32 #define PHY_CTRL3 0x108
33 #define PHY_CTRL4 0x10C
34 #define PHY_CTRL5 0x110
35 #define PHY_CTRL6 0x114
36 #define PHY_STAT1 0x130
37 #define PHY_STAT2 0x134
38
39 #define IOMUX_ENABLE_SHIFT 31
40 #define IOMUX_ENABLE_MASK BIT(IOMUX_ENABLE_SHIFT)
41 #define OTAPDLYENA_SHIFT 20
42 #define OTAPDLYENA_MASK BIT(OTAPDLYENA_SHIFT)
43 #define OTAPDLYSEL_SHIFT 12
44 #define OTAPDLYSEL_MASK GENMASK(15, 12)
45 #define STRBSEL_SHIFT 24
46 #define STRBSEL_4BIT_MASK GENMASK(27, 24)
47 #define STRBSEL_8BIT_MASK GENMASK(31, 24)
48 #define SEL50_SHIFT 8
49 #define SEL50_MASK BIT(SEL50_SHIFT)
50 #define SEL100_SHIFT 9
51 #define SEL100_MASK BIT(SEL100_SHIFT)
52 #define FREQSEL_SHIFT 8
53 #define FREQSEL_MASK GENMASK(10, 8)
54 #define CLKBUFSEL_SHIFT 0
55 #define CLKBUFSEL_MASK GENMASK(2, 0)
56 #define DLL_TRIM_ICP_SHIFT 4
57 #define DLL_TRIM_ICP_MASK GENMASK(7, 4)
58 #define DR_TY_SHIFT 20
59 #define DR_TY_MASK GENMASK(22, 20)
60 #define ENDLL_SHIFT 1
61 #define ENDLL_MASK BIT(ENDLL_SHIFT)
62 #define DLLRDY_SHIFT 0
63 #define DLLRDY_MASK BIT(DLLRDY_SHIFT)
64 #define PDB_SHIFT 0
65 #define PDB_MASK BIT(PDB_SHIFT)
66 #define CALDONE_SHIFT 1
67 #define CALDONE_MASK BIT(CALDONE_SHIFT)
68 #define RETRIM_SHIFT 17
69 #define RETRIM_MASK BIT(RETRIM_SHIFT)
70 #define SELDLYTXCLK_SHIFT 17
71 #define SELDLYTXCLK_MASK BIT(SELDLYTXCLK_SHIFT)
72 #define SELDLYRXCLK_SHIFT 16
73 #define SELDLYRXCLK_MASK BIT(SELDLYRXCLK_SHIFT)
74 #define ITAPDLYSEL_SHIFT 0
75 #define ITAPDLYSEL_MASK GENMASK(4, 0)
76 #define ITAPDLYENA_SHIFT 8
77 #define ITAPDLYENA_MASK BIT(ITAPDLYENA_SHIFT)
78 #define ITAPCHGWIN_SHIFT 9
79 #define ITAPCHGWIN_MASK BIT(ITAPCHGWIN_SHIFT)
80
81 #define DRIVER_STRENGTH_50_OHM 0x0
82 #define DRIVER_STRENGTH_33_OHM 0x1
83 #define DRIVER_STRENGTH_66_OHM 0x2
84 #define DRIVER_STRENGTH_100_OHM 0x3
85 #define DRIVER_STRENGTH_40_OHM 0x4
86
87 #define CLOCK_TOO_SLOW_HZ 50000000
88 #define SDHCI_AM654_AUTOSUSPEND_DELAY -1
89 #define RETRY_TUNING_MAX 10
90
91 /* Command Queue Host Controller Interface Base address */
92 #define SDHCI_AM654_CQE_BASE_ADDR 0x200
93
94 static const struct regmap_config sdhci_am654_regmap_config = {
95 .reg_bits = 32,
96 .val_bits = 32,
97 .reg_stride = 4,
98 .fast_io = true,
99 };
100
101 struct timing_data {
102 const char *otap_binding;
103 const char *itap_binding;
104 u32 capability;
105 };
106
107 static const struct timing_data td[] = {
108 [MMC_TIMING_LEGACY] = {"ti,otap-del-sel-legacy",
109 "ti,itap-del-sel-legacy",
110 0},
111 [MMC_TIMING_MMC_HS] = {"ti,otap-del-sel-mmc-hs",
112 "ti,itap-del-sel-mmc-hs",
113 MMC_CAP_MMC_HIGHSPEED},
114 [MMC_TIMING_SD_HS] = {"ti,otap-del-sel-sd-hs",
115 "ti,itap-del-sel-sd-hs",
116 MMC_CAP_SD_HIGHSPEED},
117 [MMC_TIMING_UHS_SDR12] = {"ti,otap-del-sel-sdr12",
118 "ti,itap-del-sel-sdr12",
119 MMC_CAP_UHS_SDR12},
120 [MMC_TIMING_UHS_SDR25] = {"ti,otap-del-sel-sdr25",
121 "ti,itap-del-sel-sdr25",
122 MMC_CAP_UHS_SDR25},
123 [MMC_TIMING_UHS_SDR50] = {"ti,otap-del-sel-sdr50",
124 NULL,
125 MMC_CAP_UHS_SDR50},
126 [MMC_TIMING_UHS_SDR104] = {"ti,otap-del-sel-sdr104",
127 NULL,
128 MMC_CAP_UHS_SDR104},
129 [MMC_TIMING_UHS_DDR50] = {"ti,otap-del-sel-ddr50",
130 NULL,
131 MMC_CAP_UHS_DDR50},
132 [MMC_TIMING_MMC_DDR52] = {"ti,otap-del-sel-ddr52",
133 "ti,itap-del-sel-ddr52",
134 MMC_CAP_DDR},
135 [MMC_TIMING_MMC_HS200] = {"ti,otap-del-sel-hs200",
136 NULL,
137 MMC_CAP2_HS200},
138 [MMC_TIMING_MMC_HS400] = {"ti,otap-del-sel-hs400",
139 NULL,
140 MMC_CAP2_HS400},
141 };
142
143 struct sdhci_am654_data {
144 struct regmap *base;
145 u32 otap_del_sel[ARRAY_SIZE(td)];
146 u32 itap_del_sel[ARRAY_SIZE(td)];
147 u32 itap_del_ena[ARRAY_SIZE(td)];
148 int clkbuf_sel;
149 int trm_icp;
150 int drv_strength;
151 int strb_sel;
152 u32 flags;
153 u32 quirks;
154 bool dll_enable;
155 u32 tuning_loop;
156
157 #define SDHCI_AM654_QUIRK_FORCE_CDTEST BIT(0)
158 #define SDHCI_AM654_QUIRK_DISABLE_HS400 BIT(1)
159 };
160
161 struct window {
162 u8 start;
163 u8 end;
164 u8 length;
165 };
166
167 struct sdhci_am654_driver_data {
168 const struct sdhci_pltfm_data *pdata;
169 u32 flags;
170 #define IOMUX_PRESENT (1 << 0)
171 #define FREQSEL_2_BIT (1 << 1)
172 #define STRBSEL_4_BIT (1 << 2)
173 #define DLL_PRESENT (1 << 3)
174 #define DLL_CALIB (1 << 4)
175 };
176
sdhci_am654_setup_dll(struct sdhci_host * host,unsigned int clock)177 static void sdhci_am654_setup_dll(struct sdhci_host *host, unsigned int clock)
178 {
179 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
180 struct sdhci_am654_data *sdhci_am654 = sdhci_pltfm_priv(pltfm_host);
181 int sel50, sel100, freqsel;
182 u32 mask, val;
183 int ret;
184
185 /* Disable delay chain mode */
186 regmap_update_bits(sdhci_am654->base, PHY_CTRL5,
187 SELDLYTXCLK_MASK | SELDLYRXCLK_MASK, 0);
188
189 if (sdhci_am654->flags & FREQSEL_2_BIT) {
190 switch (clock) {
191 case 200000000:
192 sel50 = 0;
193 sel100 = 0;
194 break;
195 case 100000000:
196 sel50 = 0;
197 sel100 = 1;
198 break;
199 default:
200 sel50 = 1;
201 sel100 = 0;
202 }
203
204 /* Configure PHY DLL frequency */
205 mask = SEL50_MASK | SEL100_MASK;
206 val = (sel50 << SEL50_SHIFT) | (sel100 << SEL100_SHIFT);
207 regmap_update_bits(sdhci_am654->base, PHY_CTRL5, mask, val);
208
209 } else {
210 switch (clock) {
211 case 200000000:
212 freqsel = 0x0;
213 break;
214 default:
215 freqsel = 0x4;
216 }
217
218 regmap_update_bits(sdhci_am654->base, PHY_CTRL5, FREQSEL_MASK,
219 freqsel << FREQSEL_SHIFT);
220 }
221 /* Configure DLL TRIM */
222 mask = DLL_TRIM_ICP_MASK;
223 val = sdhci_am654->trm_icp << DLL_TRIM_ICP_SHIFT;
224
225 /* Configure DLL driver strength */
226 mask |= DR_TY_MASK;
227 val |= sdhci_am654->drv_strength << DR_TY_SHIFT;
228 regmap_update_bits(sdhci_am654->base, PHY_CTRL1, mask, val);
229
230 /* Enable DLL */
231 regmap_update_bits(sdhci_am654->base, PHY_CTRL1, ENDLL_MASK,
232 0x1 << ENDLL_SHIFT);
233 /*
234 * Poll for DLL ready. Use a one second timeout.
235 * Works in all experiments done so far
236 */
237 ret = regmap_read_poll_timeout(sdhci_am654->base, PHY_STAT1, val,
238 val & DLLRDY_MASK, 1000, 1000000);
239 if (ret) {
240 dev_err(mmc_dev(host->mmc), "DLL failed to relock\n");
241 return;
242 }
243 }
244
sdhci_am654_write_itapdly(struct sdhci_am654_data * sdhci_am654,u32 itapdly,u32 enable)245 static void sdhci_am654_write_itapdly(struct sdhci_am654_data *sdhci_am654,
246 u32 itapdly, u32 enable)
247 {
248 /* Set ITAPCHGWIN before writing to ITAPDLY */
249 regmap_update_bits(sdhci_am654->base, PHY_CTRL4, ITAPCHGWIN_MASK,
250 1 << ITAPCHGWIN_SHIFT);
251 regmap_update_bits(sdhci_am654->base, PHY_CTRL4, ITAPDLYENA_MASK,
252 enable << ITAPDLYENA_SHIFT);
253 regmap_update_bits(sdhci_am654->base, PHY_CTRL4, ITAPDLYSEL_MASK,
254 itapdly << ITAPDLYSEL_SHIFT);
255 regmap_update_bits(sdhci_am654->base, PHY_CTRL4, ITAPCHGWIN_MASK, 0);
256 }
257
sdhci_am654_setup_delay_chain(struct sdhci_am654_data * sdhci_am654,unsigned char timing)258 static void sdhci_am654_setup_delay_chain(struct sdhci_am654_data *sdhci_am654,
259 unsigned char timing)
260 {
261 u32 mask, val;
262
263 regmap_update_bits(sdhci_am654->base, PHY_CTRL1, ENDLL_MASK, 0);
264
265 val = 1 << SELDLYTXCLK_SHIFT | 1 << SELDLYRXCLK_SHIFT;
266 mask = SELDLYTXCLK_MASK | SELDLYRXCLK_MASK;
267 regmap_update_bits(sdhci_am654->base, PHY_CTRL5, mask, val);
268
269 sdhci_am654_write_itapdly(sdhci_am654, sdhci_am654->itap_del_sel[timing],
270 sdhci_am654->itap_del_ena[timing]);
271 }
272
sdhci_am654_set_clock(struct sdhci_host * host,unsigned int clock)273 static void sdhci_am654_set_clock(struct sdhci_host *host, unsigned int clock)
274 {
275 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
276 struct sdhci_am654_data *sdhci_am654 = sdhci_pltfm_priv(pltfm_host);
277 unsigned char timing = host->mmc->ios.timing;
278 u32 otap_del_sel;
279 u32 mask, val;
280
281 regmap_update_bits(sdhci_am654->base, PHY_CTRL1, ENDLL_MASK, 0);
282
283 sdhci_set_clock(host, clock);
284
285 /* Setup Output TAP delay */
286 otap_del_sel = sdhci_am654->otap_del_sel[timing];
287
288 mask = OTAPDLYENA_MASK | OTAPDLYSEL_MASK;
289 val = (0x1 << OTAPDLYENA_SHIFT) |
290 (otap_del_sel << OTAPDLYSEL_SHIFT);
291
292 /* Write to STRBSEL for HS400 speed mode */
293 if (timing == MMC_TIMING_MMC_HS400) {
294 if (sdhci_am654->flags & STRBSEL_4_BIT)
295 mask |= STRBSEL_4BIT_MASK;
296 else
297 mask |= STRBSEL_8BIT_MASK;
298
299 val |= sdhci_am654->strb_sel << STRBSEL_SHIFT;
300 }
301
302 regmap_update_bits(sdhci_am654->base, PHY_CTRL4, mask, val);
303
304 if (timing > MMC_TIMING_UHS_SDR25 && clock >= CLOCK_TOO_SLOW_HZ) {
305 sdhci_am654_setup_dll(host, clock);
306 sdhci_am654->dll_enable = true;
307
308 if (timing == MMC_TIMING_MMC_HS400) {
309 sdhci_am654->itap_del_ena[timing] = 0x1;
310 sdhci_am654->itap_del_sel[timing] = sdhci_am654->itap_del_sel[timing - 1];
311 }
312
313 sdhci_am654_write_itapdly(sdhci_am654, sdhci_am654->itap_del_sel[timing],
314 sdhci_am654->itap_del_ena[timing]);
315 } else {
316 sdhci_am654_setup_delay_chain(sdhci_am654, timing);
317 sdhci_am654->dll_enable = false;
318 }
319
320 regmap_update_bits(sdhci_am654->base, PHY_CTRL5, CLKBUFSEL_MASK,
321 sdhci_am654->clkbuf_sel);
322 }
323
sdhci_j721e_4bit_set_clock(struct sdhci_host * host,unsigned int clock)324 static void sdhci_j721e_4bit_set_clock(struct sdhci_host *host,
325 unsigned int clock)
326 {
327 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
328 struct sdhci_am654_data *sdhci_am654 = sdhci_pltfm_priv(pltfm_host);
329 unsigned char timing = host->mmc->ios.timing;
330 u32 otap_del_sel;
331 u32 itap_del_ena;
332 u32 itap_del_sel;
333 u32 mask, val;
334
335 /* Setup Output TAP delay */
336 otap_del_sel = sdhci_am654->otap_del_sel[timing];
337
338 mask = OTAPDLYENA_MASK | OTAPDLYSEL_MASK;
339 val = (0x1 << OTAPDLYENA_SHIFT) |
340 (otap_del_sel << OTAPDLYSEL_SHIFT);
341
342 /* Setup Input TAP delay */
343 itap_del_ena = sdhci_am654->itap_del_ena[timing];
344 itap_del_sel = sdhci_am654->itap_del_sel[timing];
345
346 mask |= ITAPDLYENA_MASK | ITAPDLYSEL_MASK;
347 val |= (itap_del_ena << ITAPDLYENA_SHIFT) |
348 (itap_del_sel << ITAPDLYSEL_SHIFT);
349
350 regmap_update_bits(sdhci_am654->base, PHY_CTRL4, ITAPCHGWIN_MASK,
351 1 << ITAPCHGWIN_SHIFT);
352 regmap_update_bits(sdhci_am654->base, PHY_CTRL4, mask, val);
353 regmap_update_bits(sdhci_am654->base, PHY_CTRL4, ITAPCHGWIN_MASK, 0);
354 regmap_update_bits(sdhci_am654->base, PHY_CTRL5, CLKBUFSEL_MASK,
355 sdhci_am654->clkbuf_sel);
356
357 sdhci_set_clock(host, clock);
358 }
359
sdhci_am654_write_power_on(struct sdhci_host * host,u8 val,int reg)360 static u8 sdhci_am654_write_power_on(struct sdhci_host *host, u8 val, int reg)
361 {
362 writeb(val, host->ioaddr + reg);
363 usleep_range(1000, 10000);
364 return readb(host->ioaddr + reg);
365 }
366
367 #define MAX_POWER_ON_TIMEOUT 1500000 /* us */
sdhci_am654_write_b(struct sdhci_host * host,u8 val,int reg)368 static void sdhci_am654_write_b(struct sdhci_host *host, u8 val, int reg)
369 {
370 unsigned char timing = host->mmc->ios.timing;
371 u8 pwr;
372 int ret;
373
374 if (reg == SDHCI_HOST_CONTROL) {
375 switch (timing) {
376 /*
377 * According to the data manual, HISPD bit
378 * should not be set in these speed modes.
379 */
380 case MMC_TIMING_SD_HS:
381 case MMC_TIMING_MMC_HS:
382 val &= ~SDHCI_CTRL_HISPD;
383 }
384 }
385
386 writeb(val, host->ioaddr + reg);
387 if (reg == SDHCI_POWER_CONTROL && (val & SDHCI_POWER_ON)) {
388 /*
389 * Power on will not happen until the card detect debounce
390 * timer expires. Wait at least 1.5 seconds for the power on
391 * bit to be set
392 */
393 ret = read_poll_timeout(sdhci_am654_write_power_on, pwr,
394 pwr & SDHCI_POWER_ON, 0,
395 MAX_POWER_ON_TIMEOUT, false, host, val,
396 reg);
397 if (ret)
398 dev_info(mmc_dev(host->mmc), "Power on failed\n");
399 }
400 }
401
sdhci_am654_reset(struct sdhci_host * host,u8 mask)402 static void sdhci_am654_reset(struct sdhci_host *host, u8 mask)
403 {
404 u8 ctrl;
405 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
406 struct sdhci_am654_data *sdhci_am654 = sdhci_pltfm_priv(pltfm_host);
407
408 sdhci_and_cqhci_reset(host, mask);
409
410 if (sdhci_am654->quirks & SDHCI_AM654_QUIRK_FORCE_CDTEST) {
411 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
412 ctrl |= SDHCI_CTRL_CDTEST_INS | SDHCI_CTRL_CDTEST_EN;
413 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
414 }
415 }
416
sdhci_am654_execute_tuning(struct mmc_host * mmc,u32 opcode)417 static int sdhci_am654_execute_tuning(struct mmc_host *mmc, u32 opcode)
418 {
419 struct sdhci_host *host = mmc_priv(mmc);
420 int err = sdhci_execute_tuning(mmc, opcode);
421
422 if (err)
423 return err;
424 /*
425 * Tuning data remains in the buffer after tuning.
426 * Do a command and data reset to get rid of it
427 */
428 sdhci_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
429
430 return 0;
431 }
432
sdhci_am654_cqhci_irq(struct sdhci_host * host,u32 intmask)433 static u32 sdhci_am654_cqhci_irq(struct sdhci_host *host, u32 intmask)
434 {
435 int cmd_error = 0;
436 int data_error = 0;
437
438 if (!sdhci_cqe_irq(host, intmask, &cmd_error, &data_error))
439 return intmask;
440
441 cqhci_irq(host->mmc, intmask, cmd_error, data_error);
442
443 return 0;
444 }
445
446 #define ITAPDLY_LENGTH 32
447 #define ITAPDLY_LAST_INDEX (ITAPDLY_LENGTH - 1)
448
sdhci_am654_calculate_itap(struct sdhci_host * host,struct window * fail_window,u8 num_fails,bool circular_buffer)449 static int sdhci_am654_calculate_itap(struct sdhci_host *host, struct window
450 *fail_window, u8 num_fails, bool circular_buffer)
451 {
452 u8 itap = 0, start_fail = 0, end_fail = 0, pass_length = 0;
453 u8 first_fail_start = 0, last_fail_end = 0;
454 struct device *dev = mmc_dev(host->mmc);
455 struct window pass_window = {0, 0, 0};
456 int prev_fail_end = -1;
457 u8 i;
458
459 if (!num_fails) {
460 /* Retry tuning */
461 dev_dbg(dev, "No failing region found, retry tuning\n");
462 return -1;
463 }
464
465 if (fail_window->length == ITAPDLY_LENGTH) {
466 /* Retry tuning */
467 dev_dbg(dev, "No passing itapdly, retry tuning\n");
468 return -1;
469 }
470
471 first_fail_start = fail_window->start;
472 last_fail_end = fail_window[num_fails - 1].end;
473
474 for (i = 0; i < num_fails; i++) {
475 start_fail = fail_window[i].start;
476 end_fail = fail_window[i].end;
477 pass_length = start_fail - (prev_fail_end + 1);
478
479 if (pass_length > pass_window.length) {
480 pass_window.start = prev_fail_end + 1;
481 pass_window.length = pass_length;
482 }
483 prev_fail_end = end_fail;
484 }
485
486 if (!circular_buffer)
487 pass_length = ITAPDLY_LAST_INDEX - last_fail_end;
488 else
489 pass_length = ITAPDLY_LAST_INDEX - last_fail_end + first_fail_start;
490
491 if (pass_length > pass_window.length) {
492 pass_window.start = last_fail_end + 1;
493 pass_window.length = pass_length;
494 }
495
496 if (!circular_buffer)
497 itap = pass_window.start + (pass_window.length >> 1);
498 else
499 itap = (pass_window.start + (pass_window.length >> 1)) % ITAPDLY_LENGTH;
500
501 return (itap > ITAPDLY_LAST_INDEX) ? ITAPDLY_LAST_INDEX >> 1 : itap;
502 }
503
sdhci_am654_do_tuning(struct sdhci_host * host,u32 opcode)504 static int sdhci_am654_do_tuning(struct sdhci_host *host,
505 u32 opcode)
506 {
507 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
508 struct sdhci_am654_data *sdhci_am654 = sdhci_pltfm_priv(pltfm_host);
509 unsigned char timing = host->mmc->ios.timing;
510 struct window fail_window[ITAPDLY_LENGTH];
511 struct device *dev = mmc_dev(host->mmc);
512 u8 curr_pass, itap;
513 u8 fail_index = 0;
514 u8 prev_pass = 1;
515
516 memset(fail_window, 0, sizeof(fail_window));
517
518 /* Enable ITAPDLY */
519 sdhci_am654->itap_del_ena[timing] = 0x1;
520
521 for (itap = 0; itap < ITAPDLY_LENGTH; itap++) {
522 sdhci_am654_write_itapdly(sdhci_am654, itap, sdhci_am654->itap_del_ena[timing]);
523
524 curr_pass = !mmc_send_tuning(host->mmc, opcode, NULL);
525
526 if (!curr_pass && prev_pass)
527 fail_window[fail_index].start = itap;
528
529 if (!curr_pass) {
530 fail_window[fail_index].end = itap;
531 fail_window[fail_index].length++;
532 dev_dbg(dev, "Failed itapdly=%d\n", itap);
533 }
534
535 if (curr_pass && !prev_pass)
536 fail_index++;
537
538 prev_pass = curr_pass;
539 }
540
541 if (fail_window[fail_index].length != 0)
542 fail_index++;
543
544 return sdhci_am654_calculate_itap(host, fail_window, fail_index,
545 sdhci_am654->dll_enable);
546 }
547
sdhci_am654_platform_execute_tuning(struct sdhci_host * host,u32 opcode)548 static int sdhci_am654_platform_execute_tuning(struct sdhci_host *host,
549 u32 opcode)
550 {
551 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
552 struct sdhci_am654_data *sdhci_am654 = sdhci_pltfm_priv(pltfm_host);
553 unsigned char timing = host->mmc->ios.timing;
554 struct device *dev = mmc_dev(host->mmc);
555 int itapdly;
556
557 do {
558 itapdly = sdhci_am654_do_tuning(host, opcode);
559 if (itapdly >= 0)
560 break;
561 } while (++sdhci_am654->tuning_loop < RETRY_TUNING_MAX);
562
563 if (itapdly < 0) {
564 dev_err(dev, "Failed to find itapdly, fail tuning\n");
565 return -1;
566 }
567
568 dev_dbg(dev, "Passed tuning, final itapdly=%d\n", itapdly);
569 sdhci_am654_write_itapdly(sdhci_am654, itapdly, sdhci_am654->itap_del_ena[timing]);
570 /* Save ITAPDLY */
571 sdhci_am654->itap_del_sel[timing] = itapdly;
572
573 return 0;
574 }
575
576 static const struct sdhci_ops sdhci_am654_ops = {
577 .platform_execute_tuning = sdhci_am654_platform_execute_tuning,
578 .get_max_clock = sdhci_pltfm_clk_get_max_clock,
579 .get_timeout_clock = sdhci_pltfm_clk_get_max_clock,
580 .set_uhs_signaling = sdhci_set_uhs_signaling,
581 .set_bus_width = sdhci_set_bus_width,
582 .set_power = sdhci_set_power_and_bus_voltage,
583 .set_clock = sdhci_am654_set_clock,
584 .write_b = sdhci_am654_write_b,
585 .irq = sdhci_am654_cqhci_irq,
586 .reset = sdhci_and_cqhci_reset,
587 };
588
589 static const struct sdhci_pltfm_data sdhci_am654_pdata = {
590 .ops = &sdhci_am654_ops,
591 .quirks = SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12,
592 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
593 SDHCI_QUIRK2_DISABLE_HW_TIMEOUT,
594 };
595
596 static const struct sdhci_am654_driver_data sdhci_am654_sr1_drvdata = {
597 .pdata = &sdhci_am654_pdata,
598 .flags = IOMUX_PRESENT | FREQSEL_2_BIT | STRBSEL_4_BIT | DLL_PRESENT |
599 DLL_CALIB,
600 };
601
602 static const struct sdhci_am654_driver_data sdhci_am654_drvdata = {
603 .pdata = &sdhci_am654_pdata,
604 .flags = IOMUX_PRESENT | FREQSEL_2_BIT | STRBSEL_4_BIT | DLL_PRESENT,
605 };
606
607 static const struct sdhci_ops sdhci_j721e_8bit_ops = {
608 .platform_execute_tuning = sdhci_am654_platform_execute_tuning,
609 .get_max_clock = sdhci_pltfm_clk_get_max_clock,
610 .get_timeout_clock = sdhci_pltfm_clk_get_max_clock,
611 .set_uhs_signaling = sdhci_set_uhs_signaling,
612 .set_bus_width = sdhci_set_bus_width,
613 .set_power = sdhci_set_power_and_bus_voltage,
614 .set_clock = sdhci_am654_set_clock,
615 .write_b = sdhci_am654_write_b,
616 .irq = sdhci_am654_cqhci_irq,
617 .reset = sdhci_and_cqhci_reset,
618 };
619
620 static const struct sdhci_pltfm_data sdhci_j721e_8bit_pdata = {
621 .ops = &sdhci_j721e_8bit_ops,
622 .quirks = SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12,
623 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
624 SDHCI_QUIRK2_DISABLE_HW_TIMEOUT,
625 };
626
627 static const struct sdhci_am654_driver_data sdhci_j721e_8bit_drvdata = {
628 .pdata = &sdhci_j721e_8bit_pdata,
629 .flags = DLL_PRESENT | DLL_CALIB,
630 };
631
632 static const struct sdhci_ops sdhci_j721e_4bit_ops = {
633 .platform_execute_tuning = sdhci_am654_platform_execute_tuning,
634 .get_max_clock = sdhci_pltfm_clk_get_max_clock,
635 .get_timeout_clock = sdhci_pltfm_clk_get_max_clock,
636 .set_uhs_signaling = sdhci_set_uhs_signaling,
637 .set_bus_width = sdhci_set_bus_width,
638 .set_power = sdhci_set_power_and_bus_voltage,
639 .set_clock = sdhci_j721e_4bit_set_clock,
640 .write_b = sdhci_am654_write_b,
641 .irq = sdhci_am654_cqhci_irq,
642 .reset = sdhci_am654_reset,
643 };
644
645 static const struct sdhci_pltfm_data sdhci_j721e_4bit_pdata = {
646 .ops = &sdhci_j721e_4bit_ops,
647 .quirks = SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12,
648 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
649 SDHCI_QUIRK2_DISABLE_HW_TIMEOUT,
650 };
651
652 static const struct sdhci_am654_driver_data sdhci_j721e_4bit_drvdata = {
653 .pdata = &sdhci_j721e_4bit_pdata,
654 .flags = IOMUX_PRESENT,
655 };
656
657 static const struct soc_device_attribute sdhci_am654_devices[] = {
658 { .family = "AM65X",
659 .revision = "SR1.0",
660 .data = &sdhci_am654_sr1_drvdata
661 },
662 {/* sentinel */}
663 };
664
sdhci_am654_dumpregs(struct mmc_host * mmc)665 static void sdhci_am654_dumpregs(struct mmc_host *mmc)
666 {
667 sdhci_dumpregs(mmc_priv(mmc));
668 }
669
670 static const struct cqhci_host_ops sdhci_am654_cqhci_ops = {
671 .enable = sdhci_cqe_enable,
672 .disable = sdhci_cqe_disable,
673 .dumpregs = sdhci_am654_dumpregs,
674 };
675
sdhci_am654_cqe_add_host(struct sdhci_host * host)676 static int sdhci_am654_cqe_add_host(struct sdhci_host *host)
677 {
678 struct cqhci_host *cq_host;
679
680 cq_host = devm_kzalloc(mmc_dev(host->mmc), sizeof(struct cqhci_host),
681 GFP_KERNEL);
682 if (!cq_host)
683 return -ENOMEM;
684
685 cq_host->mmio = host->ioaddr + SDHCI_AM654_CQE_BASE_ADDR;
686 cq_host->quirks |= CQHCI_QUIRK_SHORT_TXFR_DESC_SZ;
687 cq_host->caps |= CQHCI_TASK_DESC_SZ_128;
688 cq_host->ops = &sdhci_am654_cqhci_ops;
689
690 host->mmc->caps2 |= MMC_CAP2_CQE;
691
692 return cqhci_init(cq_host, host->mmc, 1);
693 }
694
sdhci_am654_get_otap_delay(struct sdhci_host * host,struct sdhci_am654_data * sdhci_am654)695 static int sdhci_am654_get_otap_delay(struct sdhci_host *host,
696 struct sdhci_am654_data *sdhci_am654)
697 {
698 struct device *dev = mmc_dev(host->mmc);
699 int i;
700 int ret;
701
702 for (i = MMC_TIMING_LEGACY; i <= MMC_TIMING_MMC_HS400; i++) {
703
704 ret = device_property_read_u32(dev, td[i].otap_binding,
705 &sdhci_am654->otap_del_sel[i]);
706 if (ret) {
707 if (i == MMC_TIMING_LEGACY) {
708 dev_err(dev, "Couldn't find mandatory ti,otap-del-sel-legacy\n");
709 return ret;
710 }
711 dev_dbg(dev, "Couldn't find %s\n",
712 td[i].otap_binding);
713 /*
714 * Remove the corresponding capability
715 * if an otap-del-sel value is not found
716 */
717 if (i <= MMC_TIMING_MMC_DDR52)
718 host->mmc->caps &= ~td[i].capability;
719 else
720 host->mmc->caps2 &= ~td[i].capability;
721 }
722
723 if (td[i].itap_binding) {
724 ret = device_property_read_u32(dev, td[i].itap_binding,
725 &sdhci_am654->itap_del_sel[i]);
726 if (!ret)
727 sdhci_am654->itap_del_ena[i] = 0x1;
728 }
729 }
730
731 return 0;
732 }
733
sdhci_am654_init(struct sdhci_host * host)734 static int sdhci_am654_init(struct sdhci_host *host)
735 {
736 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
737 struct sdhci_am654_data *sdhci_am654 = sdhci_pltfm_priv(pltfm_host);
738 struct device *dev = mmc_dev(host->mmc);
739 u32 ctl_cfg_2 = 0;
740 u32 mask;
741 u32 val;
742 int ret;
743
744 /* Reset OTAP to default value */
745 mask = OTAPDLYENA_MASK | OTAPDLYSEL_MASK;
746 regmap_update_bits(sdhci_am654->base, PHY_CTRL4, mask, 0x0);
747
748 if (sdhci_am654->flags & DLL_CALIB) {
749 regmap_read(sdhci_am654->base, PHY_STAT1, &val);
750 if (~val & CALDONE_MASK) {
751 /* Calibrate IO lines */
752 regmap_update_bits(sdhci_am654->base, PHY_CTRL1,
753 PDB_MASK, PDB_MASK);
754 ret = regmap_read_poll_timeout(sdhci_am654->base,
755 PHY_STAT1, val,
756 val & CALDONE_MASK,
757 1, 20);
758 if (ret)
759 return ret;
760 }
761 }
762
763 /* Enable pins by setting IO mux to 0 */
764 if (sdhci_am654->flags & IOMUX_PRESENT)
765 regmap_update_bits(sdhci_am654->base, PHY_CTRL1,
766 IOMUX_ENABLE_MASK, 0);
767
768 /* Set slot type based on SD or eMMC */
769 if (host->mmc->caps & MMC_CAP_NONREMOVABLE)
770 ctl_cfg_2 = SLOTTYPE_EMBEDDED;
771
772 regmap_update_bits(sdhci_am654->base, CTL_CFG_2, SLOTTYPE_MASK,
773 ctl_cfg_2);
774
775 /* Enable tuning for SDR50 */
776 regmap_update_bits(sdhci_am654->base, CTL_CFG_3, TUNINGFORSDR50_MASK,
777 TUNINGFORSDR50_MASK);
778
779 /* Use to re-execute tuning */
780 sdhci_am654->tuning_loop = 0;
781
782 ret = sdhci_setup_host(host);
783 if (ret)
784 return ret;
785
786 ret = sdhci_am654_cqe_add_host(host);
787 if (ret)
788 goto err_cleanup_host;
789
790 ret = sdhci_am654_get_otap_delay(host, sdhci_am654);
791 if (ret)
792 goto err_cleanup_host;
793
794 if (sdhci_am654->quirks & SDHCI_AM654_QUIRK_DISABLE_HS400 &&
795 host->mmc->caps2 & (MMC_CAP2_HS400 | MMC_CAP2_HS400_ES)) {
796 dev_info(dev, "HS400 mode not supported on this silicon revision, disabling it\n");
797 host->mmc->caps2 &= ~(MMC_CAP2_HS400 | MMC_CAP2_HS400_ES);
798 }
799
800 ret = __sdhci_add_host(host);
801 if (ret)
802 goto err_cleanup_host;
803
804 return 0;
805
806 err_cleanup_host:
807 sdhci_cleanup_host(host);
808 return ret;
809 }
810
sdhci_am654_get_of_property(struct platform_device * pdev,struct sdhci_am654_data * sdhci_am654)811 static int sdhci_am654_get_of_property(struct platform_device *pdev,
812 struct sdhci_am654_data *sdhci_am654)
813 {
814 struct device *dev = &pdev->dev;
815 int drv_strength;
816 int ret;
817
818 if (sdhci_am654->flags & DLL_PRESENT) {
819 ret = device_property_read_u32(dev, "ti,trm-icp",
820 &sdhci_am654->trm_icp);
821 if (ret)
822 return ret;
823
824 ret = device_property_read_u32(dev, "ti,driver-strength-ohm",
825 &drv_strength);
826 if (ret)
827 return ret;
828
829 switch (drv_strength) {
830 case 50:
831 sdhci_am654->drv_strength = DRIVER_STRENGTH_50_OHM;
832 break;
833 case 33:
834 sdhci_am654->drv_strength = DRIVER_STRENGTH_33_OHM;
835 break;
836 case 66:
837 sdhci_am654->drv_strength = DRIVER_STRENGTH_66_OHM;
838 break;
839 case 100:
840 sdhci_am654->drv_strength = DRIVER_STRENGTH_100_OHM;
841 break;
842 case 40:
843 sdhci_am654->drv_strength = DRIVER_STRENGTH_40_OHM;
844 break;
845 default:
846 dev_err(dev, "Invalid driver strength\n");
847 return -EINVAL;
848 }
849 }
850
851 device_property_read_u32(dev, "ti,strobe-sel", &sdhci_am654->strb_sel);
852 device_property_read_u32(dev, "ti,clkbuf-sel",
853 &sdhci_am654->clkbuf_sel);
854
855 if (device_property_read_bool(dev, "ti,fails-without-test-cd"))
856 sdhci_am654->quirks |= SDHCI_AM654_QUIRK_FORCE_CDTEST;
857
858 sdhci_get_of_property(pdev);
859
860 return 0;
861 }
862
863 static const struct soc_device_attribute sdhci_am654_descope_hs400[] = {
864 { .family = "AM62PX", .revision = "SR1.0" },
865 { .family = "AM62PX", .revision = "SR1.1" },
866 { /* sentinel */ }
867 };
868
869 static const struct of_device_id sdhci_am654_of_match[] = {
870 {
871 .compatible = "ti,am654-sdhci-5.1",
872 .data = &sdhci_am654_drvdata,
873 },
874 {
875 .compatible = "ti,j721e-sdhci-8bit",
876 .data = &sdhci_j721e_8bit_drvdata,
877 },
878 {
879 .compatible = "ti,j721e-sdhci-4bit",
880 .data = &sdhci_j721e_4bit_drvdata,
881 },
882 {
883 .compatible = "ti,am64-sdhci-8bit",
884 .data = &sdhci_j721e_8bit_drvdata,
885 },
886 {
887 .compatible = "ti,am64-sdhci-4bit",
888 .data = &sdhci_j721e_4bit_drvdata,
889 },
890 {
891 .compatible = "ti,am62-sdhci",
892 .data = &sdhci_j721e_4bit_drvdata,
893 },
894 { /* sentinel */ }
895 };
896 MODULE_DEVICE_TABLE(of, sdhci_am654_of_match);
897
sdhci_am654_probe(struct platform_device * pdev)898 static int sdhci_am654_probe(struct platform_device *pdev)
899 {
900 const struct sdhci_am654_driver_data *drvdata;
901 const struct soc_device_attribute *soc;
902 struct sdhci_pltfm_host *pltfm_host;
903 struct sdhci_am654_data *sdhci_am654;
904 const struct of_device_id *match;
905 struct sdhci_host *host;
906 struct clk *clk_xin;
907 struct device *dev = &pdev->dev;
908 void __iomem *base;
909 int ret;
910
911 match = of_match_node(sdhci_am654_of_match, pdev->dev.of_node);
912 drvdata = match->data;
913
914 /* Update drvdata based on SoC revision */
915 soc = soc_device_match(sdhci_am654_devices);
916 if (soc && soc->data)
917 drvdata = soc->data;
918
919 host = sdhci_pltfm_init(pdev, drvdata->pdata, sizeof(*sdhci_am654));
920 if (IS_ERR(host))
921 return PTR_ERR(host);
922
923 pltfm_host = sdhci_priv(host);
924 sdhci_am654 = sdhci_pltfm_priv(pltfm_host);
925 sdhci_am654->flags = drvdata->flags;
926
927 clk_xin = devm_clk_get(dev, "clk_xin");
928 if (IS_ERR(clk_xin)) {
929 dev_err(dev, "clk_xin clock not found.\n");
930 ret = PTR_ERR(clk_xin);
931 goto err_pltfm_free;
932 }
933
934 pltfm_host->clk = clk_xin;
935
936 base = devm_platform_ioremap_resource(pdev, 1);
937 if (IS_ERR(base)) {
938 ret = PTR_ERR(base);
939 goto err_pltfm_free;
940 }
941
942 sdhci_am654->base = devm_regmap_init_mmio(dev, base,
943 &sdhci_am654_regmap_config);
944 if (IS_ERR(sdhci_am654->base)) {
945 dev_err(dev, "Failed to initialize regmap\n");
946 ret = PTR_ERR(sdhci_am654->base);
947 goto err_pltfm_free;
948 }
949
950 ret = sdhci_am654_get_of_property(pdev, sdhci_am654);
951 if (ret)
952 goto err_pltfm_free;
953
954 ret = mmc_of_parse(host->mmc);
955 if (ret) {
956 dev_err_probe(dev, ret, "parsing dt failed\n");
957 goto err_pltfm_free;
958 }
959
960 soc = soc_device_match(sdhci_am654_descope_hs400);
961 if (soc)
962 sdhci_am654->quirks |= SDHCI_AM654_QUIRK_DISABLE_HS400;
963
964 host->mmc_host_ops.execute_tuning = sdhci_am654_execute_tuning;
965
966 pm_runtime_get_noresume(dev);
967 ret = pm_runtime_set_active(dev);
968 if (ret)
969 goto pm_put;
970 pm_runtime_enable(dev);
971 ret = clk_prepare_enable(pltfm_host->clk);
972 if (ret)
973 goto pm_disable;
974
975 ret = sdhci_am654_init(host);
976 if (ret)
977 goto clk_disable;
978
979 /* Setting up autosuspend */
980 pm_runtime_set_autosuspend_delay(dev, SDHCI_AM654_AUTOSUSPEND_DELAY);
981 pm_runtime_use_autosuspend(dev);
982 pm_runtime_mark_last_busy(dev);
983 pm_runtime_put_autosuspend(dev);
984 return 0;
985
986 clk_disable:
987 clk_disable_unprepare(pltfm_host->clk);
988 pm_disable:
989 pm_runtime_disable(dev);
990 pm_put:
991 pm_runtime_put_noidle(dev);
992 err_pltfm_free:
993 sdhci_pltfm_free(pdev);
994 return ret;
995 }
996
sdhci_am654_remove(struct platform_device * pdev)997 static void sdhci_am654_remove(struct platform_device *pdev)
998 {
999 struct sdhci_host *host = platform_get_drvdata(pdev);
1000 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1001 struct device *dev = &pdev->dev;
1002 int ret;
1003
1004 ret = pm_runtime_get_sync(dev);
1005 if (ret < 0)
1006 dev_err(dev, "pm_runtime_get_sync() Failed\n");
1007
1008 sdhci_remove_host(host, true);
1009 clk_disable_unprepare(pltfm_host->clk);
1010 pm_runtime_disable(dev);
1011 pm_runtime_put_noidle(dev);
1012 sdhci_pltfm_free(pdev);
1013 }
1014
1015 #ifdef CONFIG_PM
sdhci_am654_restore(struct sdhci_host * host)1016 static int sdhci_am654_restore(struct sdhci_host *host)
1017 {
1018 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1019 struct sdhci_am654_data *sdhci_am654 = sdhci_pltfm_priv(pltfm_host);
1020 u32 ctl_cfg_2 = 0;
1021 u32 val;
1022 int ret;
1023
1024 if (sdhci_am654->flags & DLL_CALIB) {
1025 regmap_read(sdhci_am654->base, PHY_STAT1, &val);
1026 if (~val & CALDONE_MASK) {
1027 /* Calibrate IO lines */
1028 regmap_update_bits(sdhci_am654->base, PHY_CTRL1,
1029 PDB_MASK, PDB_MASK);
1030 ret = regmap_read_poll_timeout(sdhci_am654->base,
1031 PHY_STAT1, val,
1032 val & CALDONE_MASK,
1033 1, 20);
1034 if (ret)
1035 return ret;
1036 }
1037 }
1038
1039 /* Enable pins by setting IO mux to 0 */
1040 if (sdhci_am654->flags & IOMUX_PRESENT)
1041 regmap_update_bits(sdhci_am654->base, PHY_CTRL1,
1042 IOMUX_ENABLE_MASK, 0);
1043
1044 /* Set slot type based on SD or eMMC */
1045 if (host->mmc->caps & MMC_CAP_NONREMOVABLE)
1046 ctl_cfg_2 = SLOTTYPE_EMBEDDED;
1047
1048 regmap_update_bits(sdhci_am654->base, CTL_CFG_2, SLOTTYPE_MASK,
1049 ctl_cfg_2);
1050
1051 regmap_read(sdhci_am654->base, CTL_CFG_3, &val);
1052 if (~val & TUNINGFORSDR50_MASK)
1053 /* Enable tuning for SDR50 */
1054 regmap_update_bits(sdhci_am654->base, CTL_CFG_3, TUNINGFORSDR50_MASK,
1055 TUNINGFORSDR50_MASK);
1056
1057 return 0;
1058 }
1059
sdhci_am654_runtime_suspend(struct device * dev)1060 static int sdhci_am654_runtime_suspend(struct device *dev)
1061 {
1062 struct sdhci_host *host = dev_get_drvdata(dev);
1063 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1064 int ret;
1065
1066 if (host->tuning_mode != SDHCI_TUNING_MODE_3)
1067 mmc_retune_needed(host->mmc);
1068
1069 ret = cqhci_suspend(host->mmc);
1070 if (ret)
1071 return ret;
1072
1073 ret = sdhci_runtime_suspend_host(host);
1074 if (ret)
1075 return ret;
1076
1077 /* disable the clock */
1078 clk_disable_unprepare(pltfm_host->clk);
1079 return 0;
1080 }
1081
sdhci_am654_runtime_resume(struct device * dev)1082 static int sdhci_am654_runtime_resume(struct device *dev)
1083 {
1084 struct sdhci_host *host = dev_get_drvdata(dev);
1085 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1086 int ret;
1087
1088 /* Enable the clock */
1089 ret = clk_prepare_enable(pltfm_host->clk);
1090 if (ret)
1091 return ret;
1092
1093 ret = sdhci_am654_restore(host);
1094 if (ret)
1095 return ret;
1096
1097 ret = sdhci_runtime_resume_host(host, 0);
1098 if (ret)
1099 return ret;
1100
1101 ret = cqhci_resume(host->mmc);
1102 if (ret)
1103 return ret;
1104
1105 return 0;
1106 }
1107 #endif
1108
1109 static const struct dev_pm_ops sdhci_am654_dev_pm_ops = {
1110 SET_RUNTIME_PM_OPS(sdhci_am654_runtime_suspend,
1111 sdhci_am654_runtime_resume, NULL)
1112 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
1113 pm_runtime_force_resume)
1114 };
1115
1116 static struct platform_driver sdhci_am654_driver = {
1117 .driver = {
1118 .name = "sdhci-am654",
1119 .probe_type = PROBE_PREFER_ASYNCHRONOUS,
1120 .pm = &sdhci_am654_dev_pm_ops,
1121 .of_match_table = sdhci_am654_of_match,
1122 },
1123 .probe = sdhci_am654_probe,
1124 .remove_new = sdhci_am654_remove,
1125 };
1126
1127 module_platform_driver(sdhci_am654_driver);
1128
1129 MODULE_DESCRIPTION("Driver for SDHCI Controller on TI's AM654 devices");
1130 MODULE_AUTHOR("Faiz Abbas <faiz_abbas@ti.com>");
1131 MODULE_LICENSE("GPL");
1132