1 /* 2 * B53 register definitions 3 * 4 * Copyright (C) 2004 Broadcom Corporation 5 * Copyright (C) 2011-2013 Jonas Gorski <jogo@openwrt.org> 6 * 7 * Permission to use, copy, modify, and/or distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 #ifndef __B53_REGS_H 21 #define __B53_REGS_H 22 23 /* Management Port (SMP) Page offsets */ 24 #define B53_CTRL_PAGE 0x00 /* Control */ 25 #define B53_STAT_PAGE 0x01 /* Status */ 26 #define B53_MGMT_PAGE 0x02 /* Management Mode */ 27 #define B53_MIB_AC_PAGE 0x03 /* MIB Autocast */ 28 #define B53_ARLCTRL_PAGE 0x04 /* ARL Control */ 29 #define B53_ARLIO_PAGE 0x05 /* ARL Access */ 30 #define B53_FRAMEBUF_PAGE 0x06 /* Management frame access */ 31 #define B53_MEM_ACCESS_PAGE 0x08 /* Memory access */ 32 33 /* PHY Registers */ 34 #define B53_PORT_MII_PAGE(i) (0x10 + (i)) /* Port i MII Registers */ 35 #define B53_IM_PORT_PAGE 0x18 /* Inverse MII Port (to EMAC) */ 36 #define B53_ALL_PORT_PAGE 0x19 /* All ports MII (broadcast) */ 37 38 /* MIB registers */ 39 #define B53_MIB_PAGE(i) (0x20 + (i)) 40 41 /* Quality of Service (QoS) Registers */ 42 #define B53_QOS_PAGE 0x30 43 44 /* Port VLAN Page */ 45 #define B53_PVLAN_PAGE 0x31 46 47 /* VLAN Registers */ 48 #define B53_VLAN_PAGE 0x34 49 50 /* Jumbo Frame Registers */ 51 #define B53_JUMBO_PAGE 0x40 52 53 /* EAP Registers */ 54 #define B53_EAP_PAGE 0x42 55 56 /* EEE Control Registers Page */ 57 #define B53_EEE_PAGE 0x92 58 59 /* CFP Configuration Registers Page */ 60 #define B53_CFP_PAGE 0xa1 61 62 /************************************************************************* 63 * Control Page registers 64 *************************************************************************/ 65 66 /* Port Control Register (8 bit) */ 67 #define B53_PORT_CTRL(i) (0x00 + (i)) 68 #define PORT_CTRL_RX_DISABLE BIT(0) 69 #define PORT_CTRL_TX_DISABLE BIT(1) 70 #define PORT_CTRL_RX_BCST_EN BIT(2) /* Broadcast RX (P8 only) */ 71 #define PORT_CTRL_RX_MCST_EN BIT(3) /* Multicast RX (P8 only) */ 72 #define PORT_CTRL_RX_UCST_EN BIT(4) /* Unicast RX (P8 only) */ 73 #define PORT_CTRL_STP_STATE_S 5 74 #define PORT_CTRL_NO_STP (0 << PORT_CTRL_STP_STATE_S) 75 #define PORT_CTRL_DIS_STATE (1 << PORT_CTRL_STP_STATE_S) 76 #define PORT_CTRL_BLOCK_STATE (2 << PORT_CTRL_STP_STATE_S) 77 #define PORT_CTRL_LISTEN_STATE (3 << PORT_CTRL_STP_STATE_S) 78 #define PORT_CTRL_LEARN_STATE (4 << PORT_CTRL_STP_STATE_S) 79 #define PORT_CTRL_FWD_STATE (5 << PORT_CTRL_STP_STATE_S) 80 #define PORT_CTRL_STP_STATE_MASK (0x7 << PORT_CTRL_STP_STATE_S) 81 82 /* SMP Control Register (8 bit) */ 83 #define B53_SMP_CTRL 0x0a 84 85 /* Switch Mode Control Register (8 bit) */ 86 #define B53_SWITCH_MODE 0x0b 87 #define SM_SW_FWD_MODE BIT(0) /* 1 = Managed Mode */ 88 #define SM_SW_FWD_EN BIT(1) /* Forwarding Enable */ 89 90 /* IMP Port state override register (8 bit) */ 91 #define B53_PORT_OVERRIDE_CTRL 0x0e 92 #define PORT_OVERRIDE_LINK BIT(0) 93 #define PORT_OVERRIDE_FULL_DUPLEX BIT(1) /* 0 = Half Duplex */ 94 #define PORT_OVERRIDE_SPEED_S 2 95 #define PORT_OVERRIDE_SPEED_10M (0 << PORT_OVERRIDE_SPEED_S) 96 #define PORT_OVERRIDE_SPEED_100M (1 << PORT_OVERRIDE_SPEED_S) 97 #define PORT_OVERRIDE_SPEED_1000M (2 << PORT_OVERRIDE_SPEED_S) 98 #define PORT_OVERRIDE_LP_FLOW_25 BIT(3) /* BCM5325 only */ 99 #define PORT_OVERRIDE_RV_MII_25 BIT(4) /* BCM5325 only */ 100 #define PORT_OVERRIDE_RX_FLOW BIT(4) 101 #define PORT_OVERRIDE_TX_FLOW BIT(5) 102 #define PORT_OVERRIDE_SPEED_2000M BIT(6) /* BCM5301X only, requires setting 1000M */ 103 #define PORT_OVERRIDE_EN BIT(7) /* Use the register contents */ 104 105 /* Power-down mode control (8 bit) */ 106 #define B53_PD_MODE_CTRL_25 0x0f 107 #define PD_MODE_PORT_MASK 0x1f 108 /* Bit 0 also powers down the switch. */ 109 #define PD_MODE_POWER_DOWN_PORT(i) BIT(i) 110 111 /* IP Multicast control (8 bit) */ 112 #define B53_IP_MULTICAST_CTRL 0x21 113 #define B53_IP_MCAST_25 BIT(0) 114 #define B53_IPMC_FWD_EN BIT(1) 115 #define B53_UC_FWD_EN BIT(6) 116 #define B53_MC_FWD_EN BIT(7) 117 118 /* Switch control (8 bit) */ 119 #define B53_SWITCH_CTRL 0x22 120 #define B53_MII_DUMB_FWDG_EN BIT(6) 121 122 /* (16 bit) */ 123 #define B53_UC_FLOOD_MASK 0x32 124 #define B53_MC_FLOOD_MASK 0x34 125 #define B53_IPMC_FLOOD_MASK 0x36 126 #define B53_DIS_LEARNING 0x3c 127 128 /* 129 * Override Ports 0-7 State on devices with xMII interfaces (8 bit) 130 * 131 * For port 8 still use B53_PORT_OVERRIDE_CTRL 132 * Please note that not all ports are available on every hardware, e.g. BCM5301X 133 * don't include overriding port 6, BCM63xx also have some limitations. 134 */ 135 #define B53_GMII_PORT_OVERRIDE_CTRL(i) (0x58 + (i)) 136 #define GMII_PO_LINK BIT(0) 137 #define GMII_PO_FULL_DUPLEX BIT(1) /* 0 = Half Duplex */ 138 #define GMII_PO_SPEED_S 2 139 #define GMII_PO_SPEED_10M (0 << GMII_PO_SPEED_S) 140 #define GMII_PO_SPEED_100M (1 << GMII_PO_SPEED_S) 141 #define GMII_PO_SPEED_1000M (2 << GMII_PO_SPEED_S) 142 #define GMII_PO_RX_FLOW BIT(4) 143 #define GMII_PO_TX_FLOW BIT(5) 144 #define GMII_PO_EN BIT(6) /* Use the register contents */ 145 #define GMII_PO_SPEED_2000M BIT(7) /* BCM5301X only, requires setting 1000M */ 146 147 #define B53_RGMII_CTRL_IMP 0x60 148 #define RGMII_CTRL_ENABLE_GMII BIT(7) 149 #define RGMII_CTRL_MII_OVERRIDE BIT(6) 150 #define RGMII_CTRL_TIMING_SEL BIT(2) 151 #define RGMII_CTRL_DLL_RXC BIT(1) 152 #define RGMII_CTRL_DLL_TXC BIT(0) 153 154 #define B53_RGMII_CTRL_P(i) (B53_RGMII_CTRL_IMP + (i)) 155 156 /* Software reset register (8 bit) */ 157 #define B53_SOFTRESET 0x79 158 #define SW_RST BIT(7) 159 #define EN_CH_RST BIT(6) 160 #define EN_SW_RST BIT(4) 161 162 /* Fast Aging Control register (8 bit) */ 163 #define B53_FAST_AGE_CTRL 0x88 164 #define FAST_AGE_STATIC BIT(0) 165 #define FAST_AGE_DYNAMIC BIT(1) 166 #define FAST_AGE_PORT BIT(2) 167 #define FAST_AGE_VLAN BIT(3) 168 #define FAST_AGE_STP BIT(4) 169 #define FAST_AGE_MC BIT(5) 170 #define FAST_AGE_DONE BIT(7) 171 172 /* Fast Aging Port Control register (8 bit) */ 173 #define B53_FAST_AGE_PORT_CTRL 0x89 174 175 /* Fast Aging VID Control register (16 bit) */ 176 #define B53_FAST_AGE_VID_CTRL 0x8a 177 178 /************************************************************************* 179 * Status Page registers 180 *************************************************************************/ 181 182 /* Link Status Summary Register (16bit) */ 183 #define B53_LINK_STAT 0x00 184 185 /* Link Status Change Register (16 bit) */ 186 #define B53_LINK_STAT_CHANGE 0x02 187 188 /* Port Speed Summary Register (16 bit for FE, 32 bit for GE) */ 189 #define B53_SPEED_STAT 0x04 190 #define SPEED_PORT_FE(reg, port) (((reg) >> (port)) & 1) 191 #define SPEED_PORT_GE(reg, port) (((reg) >> 2 * (port)) & 3) 192 #define SPEED_STAT_10M 0 193 #define SPEED_STAT_100M 1 194 #define SPEED_STAT_1000M 2 195 196 /* Duplex Status Summary (16 bit) */ 197 #define B53_DUPLEX_STAT_FE 0x06 198 #define B53_DUPLEX_STAT_GE 0x08 199 #define B53_DUPLEX_STAT_63XX 0x0c 200 201 /* Revision ID register for BCM5325 */ 202 #define B53_REV_ID_25 0x50 203 204 /* Strap Value (48 bit) */ 205 #define B53_STRAP_VALUE 0x70 206 #define SV_GMII_CTRL_115 BIT(27) 207 208 /************************************************************************* 209 * Management Mode Page Registers 210 *************************************************************************/ 211 212 /* Global Management Config Register (8 bit) */ 213 #define B53_GLOBAL_CONFIG 0x00 214 #define GC_RESET_MIB 0x01 215 #define GC_RX_BPDU_EN 0x02 216 #define GC_MIB_AC_HDR_EN 0x10 217 #define GC_MIB_AC_EN 0x20 218 #define GC_FRM_MGMT_PORT_M 0xC0 219 #define GC_FRM_MGMT_PORT_04 0x00 220 #define GC_FRM_MGMT_PORT_MII 0x80 221 222 /* Broadcom Header control register (8 bit) */ 223 #define B53_BRCM_HDR 0x03 224 #define BRCM_HDR_P8_EN BIT(0) /* Enable tagging on port 8 */ 225 #define BRCM_HDR_P5_EN BIT(1) /* Enable tagging on port 5 */ 226 #define BRCM_HDR_P7_EN BIT(2) /* Enable tagging on port 7 */ 227 228 /* Mirror capture control register (16 bit) */ 229 #define B53_MIR_CAP_CTL 0x10 230 #define CAP_PORT_MASK 0xf 231 #define BLK_NOT_MIR BIT(14) 232 #define MIRROR_EN BIT(15) 233 234 /* Ingress mirror control register (16 bit) */ 235 #define B53_IG_MIR_CTL 0x12 236 #define MIRROR_MASK 0x1ff 237 #define DIV_EN BIT(13) 238 #define MIRROR_FILTER_MASK 0x3 239 #define MIRROR_FILTER_SHIFT 14 240 #define MIRROR_ALL 0 241 #define MIRROR_DA 1 242 #define MIRROR_SA 2 243 244 /* Ingress mirror divider register (16 bit) */ 245 #define B53_IG_MIR_DIV 0x14 246 #define IN_MIRROR_DIV_MASK 0x3ff 247 248 /* Ingress mirror MAC address register (48 bit) */ 249 #define B53_IG_MIR_MAC 0x16 250 251 /* Egress mirror control register (16 bit) */ 252 #define B53_EG_MIR_CTL 0x1C 253 254 /* Egress mirror divider register (16 bit) */ 255 #define B53_EG_MIR_DIV 0x1E 256 257 /* Egress mirror MAC address register (48 bit) */ 258 #define B53_EG_MIR_MAC 0x20 259 260 /* Device ID register (8 or 32 bit) */ 261 #define B53_DEVICE_ID 0x30 262 263 /* Revision ID register (8 bit) */ 264 #define B53_REV_ID 0x40 265 266 /* Broadcom header RX control (16 bit) */ 267 #define B53_BRCM_HDR_RX_DIS 0x60 268 269 /* Broadcom header TX control (16 bit) */ 270 #define B53_BRCM_HDR_TX_DIS 0x62 271 272 /************************************************************************* 273 * ARL Access Page Registers 274 *************************************************************************/ 275 276 /* VLAN Table Access Register (8 bit) */ 277 #define B53_VT_ACCESS 0x80 278 #define B53_VT_ACCESS_9798 0x60 /* for BCM5397/BCM5398 */ 279 #define B53_VT_ACCESS_63XX 0x60 /* for BCM6328/62/68 */ 280 #define VTA_CMD_WRITE 0 281 #define VTA_CMD_READ 1 282 #define VTA_CMD_CLEAR 2 283 #define VTA_START_CMD BIT(7) 284 285 /* VLAN Table Index Register (16 bit) */ 286 #define B53_VT_INDEX 0x81 287 #define B53_VT_INDEX_9798 0x61 288 #define B53_VT_INDEX_63XX 0x62 289 290 /* VLAN Table Entry Register (32 bit) */ 291 #define B53_VT_ENTRY 0x83 292 #define B53_VT_ENTRY_9798 0x63 293 #define B53_VT_ENTRY_63XX 0x64 294 #define VTE_MEMBERS 0x1ff 295 #define VTE_UNTAG_S 9 296 #define VTE_UNTAG (0x1ff << 9) 297 298 /************************************************************************* 299 * ARL I/O Registers 300 *************************************************************************/ 301 302 /* ARL Table Read/Write Register (8 bit) */ 303 #define B53_ARLTBL_RW_CTRL 0x00 304 #define ARLTBL_RW BIT(0) 305 #define ARLTBL_IVL_SVL_SELECT BIT(6) 306 #define ARLTBL_START_DONE BIT(7) 307 308 /* MAC Address Index Register (48 bit) */ 309 #define B53_MAC_ADDR_IDX 0x02 310 311 /* VLAN ID Index Register (16 bit) */ 312 #define B53_VLAN_ID_IDX 0x08 313 314 /* ARL Table MAC/VID Entry N Registers (64 bit) 315 * 316 * BCM5325 and BCM5365 share most definitions below 317 */ 318 #define B53_ARLTBL_MAC_VID_ENTRY(n) ((0x10 * (n)) + 0x10) 319 #define ARLTBL_MAC_MASK 0xffffffffffffULL 320 #define ARLTBL_VID_S 48 321 #define ARLTBL_VID_MASK_25 0xff 322 #define ARLTBL_VID_MASK 0xfff 323 #define ARLTBL_DATA_PORT_ID_S_25 48 324 #define ARLTBL_DATA_PORT_ID_MASK_25 0xf 325 #define ARLTBL_AGE_25 BIT(61) 326 #define ARLTBL_STATIC_25 BIT(62) 327 #define ARLTBL_VALID_25 BIT(63) 328 329 /* ARL Table Data Entry N Registers (32 bit) */ 330 #define B53_ARLTBL_DATA_ENTRY(n) ((0x10 * (n)) + 0x18) 331 #define ARLTBL_DATA_PORT_ID_MASK 0x1ff 332 #define ARLTBL_TC(tc) ((3 & tc) << 11) 333 #define ARLTBL_AGE BIT(14) 334 #define ARLTBL_STATIC BIT(15) 335 #define ARLTBL_VALID BIT(16) 336 337 /* Maximum number of bin entries in the ARL for all switches */ 338 #define B53_ARLTBL_MAX_BIN_ENTRIES 4 339 340 /* ARL Search Control Register (8 bit) */ 341 #define B53_ARL_SRCH_CTL 0x50 342 #define B53_ARL_SRCH_CTL_25 0x20 343 #define ARL_SRCH_VLID BIT(0) 344 #define ARL_SRCH_STDN BIT(7) 345 346 /* ARL Search Address Register (16 bit) */ 347 #define B53_ARL_SRCH_ADDR 0x51 348 #define B53_ARL_SRCH_ADDR_25 0x22 349 #define B53_ARL_SRCH_ADDR_65 0x24 350 #define ARL_ADDR_MASK GENMASK(14, 0) 351 352 /* ARL Search MAC/VID Result (64 bit) */ 353 #define B53_ARL_SRCH_RSTL_0_MACVID 0x60 354 355 /* Single register search result on 5325 */ 356 #define B53_ARL_SRCH_RSTL_0_MACVID_25 0x24 357 /* Single register search result on 5365 */ 358 #define B53_ARL_SRCH_RSTL_0_MACVID_65 0x30 359 360 /* ARL Search Data Result (32 bit) */ 361 #define B53_ARL_SRCH_RSTL_0 0x68 362 363 #define B53_ARL_SRCH_RSTL_MACVID(x) (B53_ARL_SRCH_RSTL_0_MACVID + ((x) * 0x10)) 364 #define B53_ARL_SRCH_RSTL(x) (B53_ARL_SRCH_RSTL_0 + ((x) * 0x10)) 365 366 /************************************************************************* 367 * Port VLAN Registers 368 *************************************************************************/ 369 370 /* Port VLAN mask (16 bit) IMP port is always 8, also on 5325 & co */ 371 #define B53_PVLAN_PORT_MASK(i) ((i) * 2) 372 373 /* Join all VLANs register (16 bit) */ 374 #define B53_JOIN_ALL_VLAN_EN 0x50 375 376 /************************************************************************* 377 * 802.1Q Page Registers 378 *************************************************************************/ 379 380 /* Global QoS Control (8 bit) */ 381 #define B53_QOS_GLOBAL_CTL 0x00 382 383 /* Enable 802.1Q for individual Ports (16 bit) */ 384 #define B53_802_1P_EN 0x04 385 386 /************************************************************************* 387 * VLAN Page Registers 388 *************************************************************************/ 389 390 /* VLAN Control 0 (8 bit) */ 391 #define B53_VLAN_CTRL0 0x00 392 #define VC0_8021PF_CTRL_MASK 0x3 393 #define VC0_8021PF_CTRL_NONE 0x0 394 #define VC0_8021PF_CTRL_CHANGE_PRI 0x1 395 #define VC0_8021PF_CTRL_CHANGE_VID 0x2 396 #define VC0_8021PF_CTRL_CHANGE_BOTH 0x3 397 #define VC0_8021QF_CTRL_MASK 0xc 398 #define VC0_8021QF_CTRL_CHANGE_PRI 0x1 399 #define VC0_8021QF_CTRL_CHANGE_VID 0x2 400 #define VC0_8021QF_CTRL_CHANGE_BOTH 0x3 401 #define VC0_RESERVED_1 BIT(1) 402 #define VC0_DROP_VID_MISS BIT(4) 403 #define VC0_VID_HASH_VID BIT(5) 404 #define VC0_VID_CHK_EN BIT(6) /* Use VID,DA or VID,SA */ 405 #define VC0_VLAN_EN BIT(7) /* 802.1Q VLAN Enabled */ 406 407 /* VLAN Control 1 (8 bit) */ 408 #define B53_VLAN_CTRL1 0x01 409 #define VC1_RX_MCST_TAG_EN BIT(1) 410 #define VC1_RX_MCST_FWD_EN BIT(2) 411 #define VC1_RX_MCST_UNTAG_EN BIT(3) 412 413 /* VLAN Control 2 (8 bit) */ 414 #define B53_VLAN_CTRL2 0x02 415 416 /* VLAN Control 3 (8 bit when BCM5325, 16 bit else) */ 417 #define B53_VLAN_CTRL3 0x03 418 #define B53_VLAN_CTRL3_63XX 0x04 419 #define VC3_MAXSIZE_1532 BIT(6) /* 5325 only */ 420 #define VC3_HIGH_8BIT_EN BIT(7) /* 5325 only */ 421 422 /* VLAN Control 4 (8 bit) */ 423 #define B53_VLAN_CTRL4 0x05 424 #define B53_VLAN_CTRL4_25 0x04 425 #define B53_VLAN_CTRL4_63XX 0x06 426 #define VC4_ING_VID_CHECK_S 6 427 #define VC4_ING_VID_CHECK_MASK (0x3 << VC4_ING_VID_CHECK_S) 428 #define VC4_ING_VID_VIO_FWD 0 /* forward, but do not learn */ 429 #define VC4_ING_VID_VIO_DROP 1 /* drop VID violations */ 430 #define VC4_NO_ING_VID_CHK 2 /* do not check */ 431 #define VC4_ING_VID_VIO_TO_IMP 3 /* redirect to MII port */ 432 433 /* VLAN Control 5 (8 bit) */ 434 #define B53_VLAN_CTRL5 0x06 435 #define B53_VLAN_CTRL5_25 0x05 436 #define B53_VLAN_CTRL5_63XX 0x07 437 #define VC5_VID_FFF_EN BIT(2) 438 #define VC5_DROP_VTABLE_MISS BIT(3) 439 440 /* VLAN Control 6 (8 bit) */ 441 #define B53_VLAN_CTRL6 0x07 442 #define B53_VLAN_CTRL6_63XX 0x08 443 444 /* VLAN Table Access Register (16 bit) */ 445 #define B53_VLAN_TABLE_ACCESS_25 0x06 /* BCM5325E/5350 */ 446 #define B53_VLAN_TABLE_ACCESS_65 0x08 /* BCM5365 */ 447 #define VTA_VID_LOW_MASK_25 0xf 448 #define VTA_VID_LOW_MASK_65 0xff 449 #define VTA_VID_HIGH_S_25 4 450 #define VTA_VID_HIGH_S_65 8 451 #define VTA_VID_HIGH_MASK_25 (0xff << VTA_VID_HIGH_S_25E) 452 #define VTA_VID_HIGH_MASK_65 (0xf << VTA_VID_HIGH_S_65) 453 #define VTA_RW_STATE BIT(12) 454 #define VTA_RW_STATE_RD 0 455 #define VTA_RW_STATE_WR BIT(12) 456 #define VTA_RW_OP_EN BIT(13) 457 458 /* VLAN Read/Write Registers for (16/32 bit) */ 459 #define B53_VLAN_WRITE_25 0x08 460 #define B53_VLAN_WRITE_65 0x0a 461 #define B53_VLAN_READ 0x0c 462 #define VA_MEMBER_MASK 0x3f 463 #define VA_UNTAG_S_25 6 464 #define VA_UNTAG_MASK_25 0x3f 465 #define VA_UNTAG_S_65 7 466 #define VA_UNTAG_MASK_65 0x1f 467 #define VA_VID_HIGH_S 12 468 #define VA_VID_HIGH_MASK (0xffff << VA_VID_HIGH_S) 469 #define VA_VALID_25 BIT(20) 470 #define VA_VALID_25_R4 BIT(24) 471 #define VA_VALID_65 BIT(14) 472 473 /* VLAN Port Default Tag (16 bit) */ 474 #define B53_VLAN_PORT_DEF_TAG(i) (0x10 + 2 * (i)) 475 476 /************************************************************************* 477 * Jumbo Frame Page Registers 478 *************************************************************************/ 479 480 /* Jumbo Enable Port Mask (bit i == port i enabled) (32 bit) */ 481 #define B53_JUMBO_PORT_MASK 0x01 482 #define B53_JUMBO_PORT_MASK_63XX 0x04 483 #define JPM_10_100_JUMBO_EN BIT(24) /* GigE always enabled */ 484 485 /* Good Frame Max Size without 802.1Q TAG (16 bit) */ 486 #define B53_JUMBO_MAX_SIZE 0x05 487 #define B53_JUMBO_MAX_SIZE_63XX 0x08 488 #define JMS_MIN_SIZE 1518 489 #define JMS_MAX_SIZE 9724 490 491 /************************************************************************* 492 * EAP Page Registers 493 *************************************************************************/ 494 #define B53_PORT_EAP_CONF(i) (0x20 + 8 * (i)) 495 #define EAP_MODE_SHIFT 51 496 #define EAP_MODE_SHIFT_63XX 50 497 #define EAP_MODE_MASK (0x3ull << EAP_MODE_SHIFT) 498 #define EAP_MODE_MASK_63XX (0x3ull << EAP_MODE_SHIFT_63XX) 499 #define EAP_MODE_BASIC 0 500 #define EAP_MODE_SIMPLIFIED 3 501 502 /************************************************************************* 503 * EEE Configuration Page Registers 504 *************************************************************************/ 505 506 /* EEE Enable control register (16 bit) */ 507 #define B53_EEE_EN_CTRL 0x00 508 509 /* EEE LPI assert status register (16 bit) */ 510 #define B53_EEE_LPI_ASSERT_STS 0x02 511 512 /* EEE LPI indicate status register (16 bit) */ 513 #define B53_EEE_LPI_INDICATE 0x4 514 515 /* EEE Receiving idle symbols status register (16 bit) */ 516 #define B53_EEE_RX_IDLE_SYM_STS 0x6 517 518 /* EEE Pipeline timer register (32 bit) */ 519 #define B53_EEE_PIP_TIMER 0xC 520 521 /* EEE Sleep timer Gig register (32 bit) */ 522 #define B53_EEE_SLEEP_TIMER_GIG(i) (0x10 + 4 * (i)) 523 524 /* EEE Sleep timer FE register (32 bit) */ 525 #define B53_EEE_SLEEP_TIMER_FE(i) (0x34 + 4 * (i)) 526 527 /* EEE Minimum LP timer Gig register (32 bit) */ 528 #define B53_EEE_MIN_LP_TIMER_GIG(i) (0x58 + 4 * (i)) 529 530 /* EEE Minimum LP timer FE register (32 bit) */ 531 #define B53_EEE_MIN_LP_TIMER_FE(i) (0x7c + 4 * (i)) 532 533 /* EEE Wake timer Gig register (16 bit) */ 534 #define B53_EEE_WAKE_TIMER_GIG(i) (0xa0 + 2 * (i)) 535 536 /* EEE Wake timer FE register (16 bit) */ 537 #define B53_EEE_WAKE_TIMER_FE(i) (0xb2 + 2 * (i)) 538 539 540 /************************************************************************* 541 * CFP Configuration Page Registers 542 *************************************************************************/ 543 544 /* CFP Control Register with ports map (8 bit) */ 545 #define B53_CFP_CTRL 0x00 546 547 #endif /* !__B53_REGS_H */ 548