1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Lantiq / Intel GSWIP switch driver for VRX200, xRX300 and xRX330 SoCs
4 *
5 * Copyright (C) 2010 Lantiq Deutschland
6 * Copyright (C) 2012 John Crispin <john@phrozen.org>
7 * Copyright (C) 2017 - 2019 Hauke Mehrtens <hauke@hauke-m.de>
8 *
9 * The VLAN and bridge model the GSWIP hardware uses does not directly
10 * matches the model DSA uses.
11 *
12 * The hardware has 64 possible table entries for bridges with one VLAN
13 * ID, one flow id and a list of ports for each bridge. All entries which
14 * match the same flow ID are combined in the mac learning table, they
15 * act as one global bridge.
16 * The hardware does not support VLAN filter on the port, but on the
17 * bridge, this driver converts the DSA model to the hardware.
18 *
19 * The CPU gets all the exception frames which do not match any forwarding
20 * rule and the CPU port is also added to all bridges. This makes it possible
21 * to handle all the special cases easily in software.
22 * At the initialization the driver allocates one bridge table entry for
23 * each switch port which is used when the port is used without an
24 * explicit bridge. This prevents the frames from being forwarded
25 * between all LAN ports by default.
26 */
27
28 #include <linux/clk.h>
29 #include <linux/delay.h>
30 #include <linux/etherdevice.h>
31 #include <linux/firmware.h>
32 #include <linux/if_bridge.h>
33 #include <linux/if_vlan.h>
34 #include <linux/iopoll.h>
35 #include <linux/mfd/syscon.h>
36 #include <linux/module.h>
37 #include <linux/of_mdio.h>
38 #include <linux/of_net.h>
39 #include <linux/of_platform.h>
40 #include <linux/phy.h>
41 #include <linux/phylink.h>
42 #include <linux/platform_device.h>
43 #include <linux/regmap.h>
44 #include <linux/reset.h>
45 #include <net/dsa.h>
46 #include <dt-bindings/mips/lantiq_rcu_gphy.h>
47
48 #include "lantiq_pce.h"
49
50 /* GSWIP MDIO Registers */
51 #define GSWIP_MDIO_GLOB 0x00
52 #define GSWIP_MDIO_GLOB_ENABLE BIT(15)
53 #define GSWIP_MDIO_CTRL 0x08
54 #define GSWIP_MDIO_CTRL_BUSY BIT(12)
55 #define GSWIP_MDIO_CTRL_RD BIT(11)
56 #define GSWIP_MDIO_CTRL_WR BIT(10)
57 #define GSWIP_MDIO_CTRL_PHYAD_MASK 0x1f
58 #define GSWIP_MDIO_CTRL_PHYAD_SHIFT 5
59 #define GSWIP_MDIO_CTRL_REGAD_MASK 0x1f
60 #define GSWIP_MDIO_READ 0x09
61 #define GSWIP_MDIO_WRITE 0x0A
62 #define GSWIP_MDIO_MDC_CFG0 0x0B
63 #define GSWIP_MDIO_MDC_CFG1 0x0C
64 #define GSWIP_MDIO_PHYp(p) (0x15 - (p))
65 #define GSWIP_MDIO_PHY_LINK_MASK 0x6000
66 #define GSWIP_MDIO_PHY_LINK_AUTO 0x0000
67 #define GSWIP_MDIO_PHY_LINK_DOWN 0x4000
68 #define GSWIP_MDIO_PHY_LINK_UP 0x2000
69 #define GSWIP_MDIO_PHY_SPEED_MASK 0x1800
70 #define GSWIP_MDIO_PHY_SPEED_AUTO 0x1800
71 #define GSWIP_MDIO_PHY_SPEED_M10 0x0000
72 #define GSWIP_MDIO_PHY_SPEED_M100 0x0800
73 #define GSWIP_MDIO_PHY_SPEED_G1 0x1000
74 #define GSWIP_MDIO_PHY_FDUP_MASK 0x0600
75 #define GSWIP_MDIO_PHY_FDUP_AUTO 0x0000
76 #define GSWIP_MDIO_PHY_FDUP_EN 0x0200
77 #define GSWIP_MDIO_PHY_FDUP_DIS 0x0600
78 #define GSWIP_MDIO_PHY_FCONTX_MASK 0x0180
79 #define GSWIP_MDIO_PHY_FCONTX_AUTO 0x0000
80 #define GSWIP_MDIO_PHY_FCONTX_EN 0x0100
81 #define GSWIP_MDIO_PHY_FCONTX_DIS 0x0180
82 #define GSWIP_MDIO_PHY_FCONRX_MASK 0x0060
83 #define GSWIP_MDIO_PHY_FCONRX_AUTO 0x0000
84 #define GSWIP_MDIO_PHY_FCONRX_EN 0x0020
85 #define GSWIP_MDIO_PHY_FCONRX_DIS 0x0060
86 #define GSWIP_MDIO_PHY_ADDR_MASK 0x001f
87 #define GSWIP_MDIO_PHY_MASK (GSWIP_MDIO_PHY_ADDR_MASK | \
88 GSWIP_MDIO_PHY_FCONRX_MASK | \
89 GSWIP_MDIO_PHY_FCONTX_MASK | \
90 GSWIP_MDIO_PHY_LINK_MASK | \
91 GSWIP_MDIO_PHY_SPEED_MASK | \
92 GSWIP_MDIO_PHY_FDUP_MASK)
93
94 /* GSWIP MII Registers */
95 #define GSWIP_MII_CFGp(p) (0x2 * (p))
96 #define GSWIP_MII_CFG_RESET BIT(15)
97 #define GSWIP_MII_CFG_EN BIT(14)
98 #define GSWIP_MII_CFG_ISOLATE BIT(13)
99 #define GSWIP_MII_CFG_LDCLKDIS BIT(12)
100 #define GSWIP_MII_CFG_RGMII_IBS BIT(8)
101 #define GSWIP_MII_CFG_RMII_CLK BIT(7)
102 #define GSWIP_MII_CFG_MODE_MIIP 0x0
103 #define GSWIP_MII_CFG_MODE_MIIM 0x1
104 #define GSWIP_MII_CFG_MODE_RMIIP 0x2
105 #define GSWIP_MII_CFG_MODE_RMIIM 0x3
106 #define GSWIP_MII_CFG_MODE_RGMII 0x4
107 #define GSWIP_MII_CFG_MODE_GMII 0x9
108 #define GSWIP_MII_CFG_MODE_MASK 0xf
109 #define GSWIP_MII_CFG_RATE_M2P5 0x00
110 #define GSWIP_MII_CFG_RATE_M25 0x10
111 #define GSWIP_MII_CFG_RATE_M125 0x20
112 #define GSWIP_MII_CFG_RATE_M50 0x30
113 #define GSWIP_MII_CFG_RATE_AUTO 0x40
114 #define GSWIP_MII_CFG_RATE_MASK 0x70
115 #define GSWIP_MII_PCDU0 0x01
116 #define GSWIP_MII_PCDU1 0x03
117 #define GSWIP_MII_PCDU5 0x05
118 #define GSWIP_MII_PCDU_TXDLY_MASK GENMASK(2, 0)
119 #define GSWIP_MII_PCDU_RXDLY_MASK GENMASK(9, 7)
120
121 /* GSWIP Core Registers */
122 #define GSWIP_SWRES 0x000
123 #define GSWIP_SWRES_R1 BIT(1) /* GSWIP Software reset */
124 #define GSWIP_SWRES_R0 BIT(0) /* GSWIP Hardware reset */
125 #define GSWIP_VERSION 0x013
126 #define GSWIP_VERSION_REV_SHIFT 0
127 #define GSWIP_VERSION_REV_MASK GENMASK(7, 0)
128 #define GSWIP_VERSION_MOD_SHIFT 8
129 #define GSWIP_VERSION_MOD_MASK GENMASK(15, 8)
130 #define GSWIP_VERSION_2_0 0x100
131 #define GSWIP_VERSION_2_1 0x021
132 #define GSWIP_VERSION_2_2 0x122
133 #define GSWIP_VERSION_2_2_ETC 0x022
134
135 #define GSWIP_BM_RAM_VAL(x) (0x043 - (x))
136 #define GSWIP_BM_RAM_ADDR 0x044
137 #define GSWIP_BM_RAM_CTRL 0x045
138 #define GSWIP_BM_RAM_CTRL_BAS BIT(15)
139 #define GSWIP_BM_RAM_CTRL_OPMOD BIT(5)
140 #define GSWIP_BM_RAM_CTRL_ADDR_MASK GENMASK(4, 0)
141 #define GSWIP_BM_QUEUE_GCTRL 0x04A
142 #define GSWIP_BM_QUEUE_GCTRL_GL_MOD BIT(10)
143 /* buffer management Port Configuration Register */
144 #define GSWIP_BM_PCFGp(p) (0x080 + ((p) * 2))
145 #define GSWIP_BM_PCFG_CNTEN BIT(0) /* RMON Counter Enable */
146 #define GSWIP_BM_PCFG_IGCNT BIT(1) /* Ingres Special Tag RMON count */
147 /* buffer management Port Control Register */
148 #define GSWIP_BM_RMON_CTRLp(p) (0x81 + ((p) * 2))
149 #define GSWIP_BM_CTRL_RMON_RAM1_RES BIT(0) /* Software Reset for RMON RAM 1 */
150 #define GSWIP_BM_CTRL_RMON_RAM2_RES BIT(1) /* Software Reset for RMON RAM 2 */
151
152 /* PCE */
153 #define GSWIP_PCE_TBL_KEY(x) (0x447 - (x))
154 #define GSWIP_PCE_TBL_MASK 0x448
155 #define GSWIP_PCE_TBL_VAL(x) (0x44D - (x))
156 #define GSWIP_PCE_TBL_ADDR 0x44E
157 #define GSWIP_PCE_TBL_CTRL 0x44F
158 #define GSWIP_PCE_TBL_CTRL_BAS BIT(15)
159 #define GSWIP_PCE_TBL_CTRL_TYPE BIT(13)
160 #define GSWIP_PCE_TBL_CTRL_VLD BIT(12)
161 #define GSWIP_PCE_TBL_CTRL_KEYFORM BIT(11)
162 #define GSWIP_PCE_TBL_CTRL_GMAP_MASK GENMASK(10, 7)
163 #define GSWIP_PCE_TBL_CTRL_OPMOD_MASK GENMASK(6, 5)
164 #define GSWIP_PCE_TBL_CTRL_OPMOD_ADRD 0x00
165 #define GSWIP_PCE_TBL_CTRL_OPMOD_ADWR 0x20
166 #define GSWIP_PCE_TBL_CTRL_OPMOD_KSRD 0x40
167 #define GSWIP_PCE_TBL_CTRL_OPMOD_KSWR 0x60
168 #define GSWIP_PCE_TBL_CTRL_ADDR_MASK GENMASK(4, 0)
169 #define GSWIP_PCE_PMAP1 0x453 /* Monitoring port map */
170 #define GSWIP_PCE_PMAP2 0x454 /* Default Multicast port map */
171 #define GSWIP_PCE_PMAP3 0x455 /* Default Unknown Unicast port map */
172 #define GSWIP_PCE_GCTRL_0 0x456
173 #define GSWIP_PCE_GCTRL_0_MTFL BIT(0) /* MAC Table Flushing */
174 #define GSWIP_PCE_GCTRL_0_MC_VALID BIT(3)
175 #define GSWIP_PCE_GCTRL_0_VLAN BIT(14) /* VLAN aware Switching */
176 #define GSWIP_PCE_GCTRL_1 0x457
177 #define GSWIP_PCE_GCTRL_1_MAC_GLOCK BIT(2) /* MAC Address table lock */
178 #define GSWIP_PCE_GCTRL_1_MAC_GLOCK_MOD BIT(3) /* Mac address table lock forwarding mode */
179 #define GSWIP_PCE_PCTRL_0p(p) (0x480 + ((p) * 0xA))
180 #define GSWIP_PCE_PCTRL_0_TVM BIT(5) /* Transparent VLAN mode */
181 #define GSWIP_PCE_PCTRL_0_VREP BIT(6) /* VLAN Replace Mode */
182 #define GSWIP_PCE_PCTRL_0_INGRESS BIT(11) /* Accept special tag in ingress */
183 #define GSWIP_PCE_PCTRL_0_PSTATE_LISTEN 0x0
184 #define GSWIP_PCE_PCTRL_0_PSTATE_RX 0x1
185 #define GSWIP_PCE_PCTRL_0_PSTATE_TX 0x2
186 #define GSWIP_PCE_PCTRL_0_PSTATE_LEARNING 0x3
187 #define GSWIP_PCE_PCTRL_0_PSTATE_FORWARDING 0x7
188 #define GSWIP_PCE_PCTRL_0_PSTATE_MASK GENMASK(2, 0)
189 #define GSWIP_PCE_VCTRL(p) (0x485 + ((p) * 0xA))
190 #define GSWIP_PCE_VCTRL_UVR BIT(0) /* Unknown VLAN Rule */
191 #define GSWIP_PCE_VCTRL_VIMR BIT(3) /* VLAN Ingress Member violation rule */
192 #define GSWIP_PCE_VCTRL_VEMR BIT(4) /* VLAN Egress Member violation rule */
193 #define GSWIP_PCE_VCTRL_VSR BIT(5) /* VLAN Security */
194 #define GSWIP_PCE_VCTRL_VID0 BIT(6) /* Priority Tagged Rule */
195 #define GSWIP_PCE_DEFPVID(p) (0x486 + ((p) * 0xA))
196
197 #define GSWIP_MAC_FLEN 0x8C5
198 #define GSWIP_MAC_CTRL_0p(p) (0x903 + ((p) * 0xC))
199 #define GSWIP_MAC_CTRL_0_PADEN BIT(8)
200 #define GSWIP_MAC_CTRL_0_FCS_EN BIT(7)
201 #define GSWIP_MAC_CTRL_0_FCON_MASK 0x0070
202 #define GSWIP_MAC_CTRL_0_FCON_AUTO 0x0000
203 #define GSWIP_MAC_CTRL_0_FCON_RX 0x0010
204 #define GSWIP_MAC_CTRL_0_FCON_TX 0x0020
205 #define GSWIP_MAC_CTRL_0_FCON_RXTX 0x0030
206 #define GSWIP_MAC_CTRL_0_FCON_NONE 0x0040
207 #define GSWIP_MAC_CTRL_0_FDUP_MASK 0x000C
208 #define GSWIP_MAC_CTRL_0_FDUP_AUTO 0x0000
209 #define GSWIP_MAC_CTRL_0_FDUP_EN 0x0004
210 #define GSWIP_MAC_CTRL_0_FDUP_DIS 0x000C
211 #define GSWIP_MAC_CTRL_0_GMII_MASK 0x0003
212 #define GSWIP_MAC_CTRL_0_GMII_AUTO 0x0000
213 #define GSWIP_MAC_CTRL_0_GMII_MII 0x0001
214 #define GSWIP_MAC_CTRL_0_GMII_RGMII 0x0002
215 #define GSWIP_MAC_CTRL_2p(p) (0x905 + ((p) * 0xC))
216 #define GSWIP_MAC_CTRL_2_LCHKL BIT(2) /* Frame Length Check Long Enable */
217 #define GSWIP_MAC_CTRL_2_MLEN BIT(3) /* Maximum Untagged Frame Lnegth */
218
219 /* Ethernet Switch Fetch DMA Port Control Register */
220 #define GSWIP_FDMA_PCTRLp(p) (0xA80 + ((p) * 0x6))
221 #define GSWIP_FDMA_PCTRL_EN BIT(0) /* FDMA Port Enable */
222 #define GSWIP_FDMA_PCTRL_STEN BIT(1) /* Special Tag Insertion Enable */
223 #define GSWIP_FDMA_PCTRL_VLANMOD_MASK GENMASK(4, 3) /* VLAN Modification Control */
224 #define GSWIP_FDMA_PCTRL_VLANMOD_SHIFT 3 /* VLAN Modification Control */
225 #define GSWIP_FDMA_PCTRL_VLANMOD_DIS (0x0 << GSWIP_FDMA_PCTRL_VLANMOD_SHIFT)
226 #define GSWIP_FDMA_PCTRL_VLANMOD_PRIO (0x1 << GSWIP_FDMA_PCTRL_VLANMOD_SHIFT)
227 #define GSWIP_FDMA_PCTRL_VLANMOD_ID (0x2 << GSWIP_FDMA_PCTRL_VLANMOD_SHIFT)
228 #define GSWIP_FDMA_PCTRL_VLANMOD_BOTH (0x3 << GSWIP_FDMA_PCTRL_VLANMOD_SHIFT)
229
230 /* Ethernet Switch Store DMA Port Control Register */
231 #define GSWIP_SDMA_PCTRLp(p) (0xBC0 + ((p) * 0x6))
232 #define GSWIP_SDMA_PCTRL_EN BIT(0) /* SDMA Port Enable */
233 #define GSWIP_SDMA_PCTRL_FCEN BIT(1) /* Flow Control Enable */
234 #define GSWIP_SDMA_PCTRL_PAUFWD BIT(3) /* Pause Frame Forwarding */
235
236 #define GSWIP_TABLE_ACTIVE_VLAN 0x01
237 #define GSWIP_TABLE_VLAN_MAPPING 0x02
238 #define GSWIP_TABLE_MAC_BRIDGE 0x0b
239 #define GSWIP_TABLE_MAC_BRIDGE_KEY3_FID GENMASK(5, 0) /* Filtering identifier */
240 #define GSWIP_TABLE_MAC_BRIDGE_VAL0_PORT GENMASK(7, 4) /* Port on learned entries */
241 #define GSWIP_TABLE_MAC_BRIDGE_VAL1_STATIC BIT(0) /* Static, non-aging entry */
242
243 #define XRX200_GPHY_FW_ALIGN (16 * 1024)
244
245 /* Maximum packet size supported by the switch. In theory this should be 10240,
246 * but long packets currently cause lock-ups with an MTU of over 2526. Medium
247 * packets are sometimes dropped (e.g. TCP over 2477, UDP over 2516-2519, ICMP
248 * over 2526), hence an MTU value of 2400 seems safe. This issue only affects
249 * packet reception. This is probably caused by the PPA engine, which is on the
250 * RX part of the device. Packet transmission works properly up to 10240.
251 */
252 #define GSWIP_MAX_PACKET_LENGTH 2400
253
254 struct gswip_hw_info {
255 int max_ports;
256 int cpu_port;
257 const struct dsa_switch_ops *ops;
258 };
259
260 struct xway_gphy_match_data {
261 char *fe_firmware_name;
262 char *ge_firmware_name;
263 };
264
265 struct gswip_gphy_fw {
266 struct clk *clk_gate;
267 struct reset_control *reset;
268 u32 fw_addr_offset;
269 char *fw_name;
270 };
271
272 struct gswip_vlan {
273 struct net_device *bridge;
274 u16 vid;
275 u8 fid;
276 };
277
278 struct gswip_priv {
279 __iomem void *gswip;
280 __iomem void *mdio;
281 __iomem void *mii;
282 const struct gswip_hw_info *hw_info;
283 const struct xway_gphy_match_data *gphy_fw_name_cfg;
284 struct dsa_switch *ds;
285 struct device *dev;
286 struct regmap *rcu_regmap;
287 struct gswip_vlan vlans[64];
288 int num_gphy_fw;
289 struct gswip_gphy_fw *gphy_fw;
290 u32 port_vlan_filter;
291 struct mutex pce_table_lock;
292 };
293
294 struct gswip_pce_table_entry {
295 u16 index; // PCE_TBL_ADDR.ADDR = pData->table_index
296 u16 table; // PCE_TBL_CTRL.ADDR = pData->table
297 u16 key[8];
298 u16 val[5];
299 u16 mask;
300 u8 gmap;
301 bool type;
302 bool valid;
303 bool key_mode;
304 };
305
306 struct gswip_rmon_cnt_desc {
307 unsigned int size;
308 unsigned int offset;
309 const char *name;
310 };
311
312 #define MIB_DESC(_size, _offset, _name) {.size = _size, .offset = _offset, .name = _name}
313
314 static const struct gswip_rmon_cnt_desc gswip_rmon_cnt[] = {
315 /** Receive Packet Count (only packets that are accepted and not discarded). */
316 MIB_DESC(1, 0x1F, "RxGoodPkts"),
317 MIB_DESC(1, 0x23, "RxUnicastPkts"),
318 MIB_DESC(1, 0x22, "RxMulticastPkts"),
319 MIB_DESC(1, 0x21, "RxFCSErrorPkts"),
320 MIB_DESC(1, 0x1D, "RxUnderSizeGoodPkts"),
321 MIB_DESC(1, 0x1E, "RxUnderSizeErrorPkts"),
322 MIB_DESC(1, 0x1B, "RxOversizeGoodPkts"),
323 MIB_DESC(1, 0x1C, "RxOversizeErrorPkts"),
324 MIB_DESC(1, 0x20, "RxGoodPausePkts"),
325 MIB_DESC(1, 0x1A, "RxAlignErrorPkts"),
326 MIB_DESC(1, 0x12, "Rx64BytePkts"),
327 MIB_DESC(1, 0x13, "Rx127BytePkts"),
328 MIB_DESC(1, 0x14, "Rx255BytePkts"),
329 MIB_DESC(1, 0x15, "Rx511BytePkts"),
330 MIB_DESC(1, 0x16, "Rx1023BytePkts"),
331 /** Receive Size 1024-1522 (or more, if configured) Packet Count. */
332 MIB_DESC(1, 0x17, "RxMaxBytePkts"),
333 MIB_DESC(1, 0x18, "RxDroppedPkts"),
334 MIB_DESC(1, 0x19, "RxFilteredPkts"),
335 MIB_DESC(2, 0x24, "RxGoodBytes"),
336 MIB_DESC(2, 0x26, "RxBadBytes"),
337 MIB_DESC(1, 0x11, "TxAcmDroppedPkts"),
338 MIB_DESC(1, 0x0C, "TxGoodPkts"),
339 MIB_DESC(1, 0x06, "TxUnicastPkts"),
340 MIB_DESC(1, 0x07, "TxMulticastPkts"),
341 MIB_DESC(1, 0x00, "Tx64BytePkts"),
342 MIB_DESC(1, 0x01, "Tx127BytePkts"),
343 MIB_DESC(1, 0x02, "Tx255BytePkts"),
344 MIB_DESC(1, 0x03, "Tx511BytePkts"),
345 MIB_DESC(1, 0x04, "Tx1023BytePkts"),
346 /** Transmit Size 1024-1522 (or more, if configured) Packet Count. */
347 MIB_DESC(1, 0x05, "TxMaxBytePkts"),
348 MIB_DESC(1, 0x08, "TxSingleCollCount"),
349 MIB_DESC(1, 0x09, "TxMultCollCount"),
350 MIB_DESC(1, 0x0A, "TxLateCollCount"),
351 MIB_DESC(1, 0x0B, "TxExcessCollCount"),
352 MIB_DESC(1, 0x0D, "TxPauseCount"),
353 MIB_DESC(1, 0x10, "TxDroppedPkts"),
354 MIB_DESC(2, 0x0E, "TxGoodBytes"),
355 };
356
gswip_switch_r(struct gswip_priv * priv,u32 offset)357 static u32 gswip_switch_r(struct gswip_priv *priv, u32 offset)
358 {
359 return __raw_readl(priv->gswip + (offset * 4));
360 }
361
gswip_switch_w(struct gswip_priv * priv,u32 val,u32 offset)362 static void gswip_switch_w(struct gswip_priv *priv, u32 val, u32 offset)
363 {
364 __raw_writel(val, priv->gswip + (offset * 4));
365 }
366
gswip_switch_mask(struct gswip_priv * priv,u32 clear,u32 set,u32 offset)367 static void gswip_switch_mask(struct gswip_priv *priv, u32 clear, u32 set,
368 u32 offset)
369 {
370 u32 val = gswip_switch_r(priv, offset);
371
372 val &= ~(clear);
373 val |= set;
374 gswip_switch_w(priv, val, offset);
375 }
376
gswip_switch_r_timeout(struct gswip_priv * priv,u32 offset,u32 cleared)377 static u32 gswip_switch_r_timeout(struct gswip_priv *priv, u32 offset,
378 u32 cleared)
379 {
380 u32 val;
381
382 return readx_poll_timeout(__raw_readl, priv->gswip + (offset * 4), val,
383 (val & cleared) == 0, 20, 50000);
384 }
385
gswip_mdio_r(struct gswip_priv * priv,u32 offset)386 static u32 gswip_mdio_r(struct gswip_priv *priv, u32 offset)
387 {
388 return __raw_readl(priv->mdio + (offset * 4));
389 }
390
gswip_mdio_w(struct gswip_priv * priv,u32 val,u32 offset)391 static void gswip_mdio_w(struct gswip_priv *priv, u32 val, u32 offset)
392 {
393 __raw_writel(val, priv->mdio + (offset * 4));
394 }
395
gswip_mdio_mask(struct gswip_priv * priv,u32 clear,u32 set,u32 offset)396 static void gswip_mdio_mask(struct gswip_priv *priv, u32 clear, u32 set,
397 u32 offset)
398 {
399 u32 val = gswip_mdio_r(priv, offset);
400
401 val &= ~(clear);
402 val |= set;
403 gswip_mdio_w(priv, val, offset);
404 }
405
gswip_mii_r(struct gswip_priv * priv,u32 offset)406 static u32 gswip_mii_r(struct gswip_priv *priv, u32 offset)
407 {
408 return __raw_readl(priv->mii + (offset * 4));
409 }
410
gswip_mii_w(struct gswip_priv * priv,u32 val,u32 offset)411 static void gswip_mii_w(struct gswip_priv *priv, u32 val, u32 offset)
412 {
413 __raw_writel(val, priv->mii + (offset * 4));
414 }
415
gswip_mii_mask(struct gswip_priv * priv,u32 clear,u32 set,u32 offset)416 static void gswip_mii_mask(struct gswip_priv *priv, u32 clear, u32 set,
417 u32 offset)
418 {
419 u32 val = gswip_mii_r(priv, offset);
420
421 val &= ~(clear);
422 val |= set;
423 gswip_mii_w(priv, val, offset);
424 }
425
gswip_mii_mask_cfg(struct gswip_priv * priv,u32 clear,u32 set,int port)426 static void gswip_mii_mask_cfg(struct gswip_priv *priv, u32 clear, u32 set,
427 int port)
428 {
429 /* There's no MII_CFG register for the CPU port */
430 if (!dsa_is_cpu_port(priv->ds, port))
431 gswip_mii_mask(priv, clear, set, GSWIP_MII_CFGp(port));
432 }
433
gswip_mii_mask_pcdu(struct gswip_priv * priv,u32 clear,u32 set,int port)434 static void gswip_mii_mask_pcdu(struct gswip_priv *priv, u32 clear, u32 set,
435 int port)
436 {
437 switch (port) {
438 case 0:
439 gswip_mii_mask(priv, clear, set, GSWIP_MII_PCDU0);
440 break;
441 case 1:
442 gswip_mii_mask(priv, clear, set, GSWIP_MII_PCDU1);
443 break;
444 case 5:
445 gswip_mii_mask(priv, clear, set, GSWIP_MII_PCDU5);
446 break;
447 }
448 }
449
gswip_mdio_poll(struct gswip_priv * priv)450 static int gswip_mdio_poll(struct gswip_priv *priv)
451 {
452 int cnt = 100;
453
454 while (likely(cnt--)) {
455 u32 ctrl = gswip_mdio_r(priv, GSWIP_MDIO_CTRL);
456
457 if ((ctrl & GSWIP_MDIO_CTRL_BUSY) == 0)
458 return 0;
459 usleep_range(20, 40);
460 }
461
462 return -ETIMEDOUT;
463 }
464
gswip_mdio_wr(struct mii_bus * bus,int addr,int reg,u16 val)465 static int gswip_mdio_wr(struct mii_bus *bus, int addr, int reg, u16 val)
466 {
467 struct gswip_priv *priv = bus->priv;
468 int err;
469
470 err = gswip_mdio_poll(priv);
471 if (err) {
472 dev_err(&bus->dev, "waiting for MDIO bus busy timed out\n");
473 return err;
474 }
475
476 gswip_mdio_w(priv, val, GSWIP_MDIO_WRITE);
477 gswip_mdio_w(priv, GSWIP_MDIO_CTRL_BUSY | GSWIP_MDIO_CTRL_WR |
478 ((addr & GSWIP_MDIO_CTRL_PHYAD_MASK) << GSWIP_MDIO_CTRL_PHYAD_SHIFT) |
479 (reg & GSWIP_MDIO_CTRL_REGAD_MASK),
480 GSWIP_MDIO_CTRL);
481
482 return 0;
483 }
484
gswip_mdio_rd(struct mii_bus * bus,int addr,int reg)485 static int gswip_mdio_rd(struct mii_bus *bus, int addr, int reg)
486 {
487 struct gswip_priv *priv = bus->priv;
488 int err;
489
490 err = gswip_mdio_poll(priv);
491 if (err) {
492 dev_err(&bus->dev, "waiting for MDIO bus busy timed out\n");
493 return err;
494 }
495
496 gswip_mdio_w(priv, GSWIP_MDIO_CTRL_BUSY | GSWIP_MDIO_CTRL_RD |
497 ((addr & GSWIP_MDIO_CTRL_PHYAD_MASK) << GSWIP_MDIO_CTRL_PHYAD_SHIFT) |
498 (reg & GSWIP_MDIO_CTRL_REGAD_MASK),
499 GSWIP_MDIO_CTRL);
500
501 err = gswip_mdio_poll(priv);
502 if (err) {
503 dev_err(&bus->dev, "waiting for MDIO bus busy timed out\n");
504 return err;
505 }
506
507 return gswip_mdio_r(priv, GSWIP_MDIO_READ);
508 }
509
gswip_mdio(struct gswip_priv * priv)510 static int gswip_mdio(struct gswip_priv *priv)
511 {
512 struct device_node *mdio_np, *switch_np = priv->dev->of_node;
513 struct device *dev = priv->dev;
514 struct mii_bus *bus;
515 int err = 0;
516
517 mdio_np = of_get_compatible_child(switch_np, "lantiq,xrx200-mdio");
518 if (!of_device_is_available(mdio_np))
519 goto out_put_node;
520
521 bus = devm_mdiobus_alloc(dev);
522 if (!bus) {
523 err = -ENOMEM;
524 goto out_put_node;
525 }
526
527 bus->priv = priv;
528 bus->read = gswip_mdio_rd;
529 bus->write = gswip_mdio_wr;
530 bus->name = "lantiq,xrx200-mdio";
531 snprintf(bus->id, MII_BUS_ID_SIZE, "%s-mii", dev_name(priv->dev));
532 bus->parent = priv->dev;
533
534 err = devm_of_mdiobus_register(dev, bus, mdio_np);
535
536 out_put_node:
537 of_node_put(mdio_np);
538
539 return err;
540 }
541
gswip_pce_table_entry_read(struct gswip_priv * priv,struct gswip_pce_table_entry * tbl)542 static int gswip_pce_table_entry_read(struct gswip_priv *priv,
543 struct gswip_pce_table_entry *tbl)
544 {
545 int i;
546 int err;
547 u16 crtl;
548 u16 addr_mode = tbl->key_mode ? GSWIP_PCE_TBL_CTRL_OPMOD_KSRD :
549 GSWIP_PCE_TBL_CTRL_OPMOD_ADRD;
550
551 mutex_lock(&priv->pce_table_lock);
552
553 err = gswip_switch_r_timeout(priv, GSWIP_PCE_TBL_CTRL,
554 GSWIP_PCE_TBL_CTRL_BAS);
555 if (err) {
556 mutex_unlock(&priv->pce_table_lock);
557 return err;
558 }
559
560 gswip_switch_w(priv, tbl->index, GSWIP_PCE_TBL_ADDR);
561 gswip_switch_mask(priv, GSWIP_PCE_TBL_CTRL_ADDR_MASK |
562 GSWIP_PCE_TBL_CTRL_OPMOD_MASK,
563 tbl->table | addr_mode | GSWIP_PCE_TBL_CTRL_BAS,
564 GSWIP_PCE_TBL_CTRL);
565
566 err = gswip_switch_r_timeout(priv, GSWIP_PCE_TBL_CTRL,
567 GSWIP_PCE_TBL_CTRL_BAS);
568 if (err) {
569 mutex_unlock(&priv->pce_table_lock);
570 return err;
571 }
572
573 for (i = 0; i < ARRAY_SIZE(tbl->key); i++)
574 tbl->key[i] = gswip_switch_r(priv, GSWIP_PCE_TBL_KEY(i));
575
576 for (i = 0; i < ARRAY_SIZE(tbl->val); i++)
577 tbl->val[i] = gswip_switch_r(priv, GSWIP_PCE_TBL_VAL(i));
578
579 tbl->mask = gswip_switch_r(priv, GSWIP_PCE_TBL_MASK);
580
581 crtl = gswip_switch_r(priv, GSWIP_PCE_TBL_CTRL);
582
583 tbl->type = !!(crtl & GSWIP_PCE_TBL_CTRL_TYPE);
584 tbl->valid = !!(crtl & GSWIP_PCE_TBL_CTRL_VLD);
585 tbl->gmap = (crtl & GSWIP_PCE_TBL_CTRL_GMAP_MASK) >> 7;
586
587 mutex_unlock(&priv->pce_table_lock);
588
589 return 0;
590 }
591
gswip_pce_table_entry_write(struct gswip_priv * priv,struct gswip_pce_table_entry * tbl)592 static int gswip_pce_table_entry_write(struct gswip_priv *priv,
593 struct gswip_pce_table_entry *tbl)
594 {
595 int i;
596 int err;
597 u16 crtl;
598 u16 addr_mode = tbl->key_mode ? GSWIP_PCE_TBL_CTRL_OPMOD_KSWR :
599 GSWIP_PCE_TBL_CTRL_OPMOD_ADWR;
600
601 mutex_lock(&priv->pce_table_lock);
602
603 err = gswip_switch_r_timeout(priv, GSWIP_PCE_TBL_CTRL,
604 GSWIP_PCE_TBL_CTRL_BAS);
605 if (err) {
606 mutex_unlock(&priv->pce_table_lock);
607 return err;
608 }
609
610 gswip_switch_w(priv, tbl->index, GSWIP_PCE_TBL_ADDR);
611 gswip_switch_mask(priv, GSWIP_PCE_TBL_CTRL_ADDR_MASK |
612 GSWIP_PCE_TBL_CTRL_OPMOD_MASK,
613 tbl->table | addr_mode,
614 GSWIP_PCE_TBL_CTRL);
615
616 for (i = 0; i < ARRAY_SIZE(tbl->key); i++)
617 gswip_switch_w(priv, tbl->key[i], GSWIP_PCE_TBL_KEY(i));
618
619 for (i = 0; i < ARRAY_SIZE(tbl->val); i++)
620 gswip_switch_w(priv, tbl->val[i], GSWIP_PCE_TBL_VAL(i));
621
622 gswip_switch_mask(priv, GSWIP_PCE_TBL_CTRL_ADDR_MASK |
623 GSWIP_PCE_TBL_CTRL_OPMOD_MASK,
624 tbl->table | addr_mode,
625 GSWIP_PCE_TBL_CTRL);
626
627 gswip_switch_w(priv, tbl->mask, GSWIP_PCE_TBL_MASK);
628
629 crtl = gswip_switch_r(priv, GSWIP_PCE_TBL_CTRL);
630 crtl &= ~(GSWIP_PCE_TBL_CTRL_TYPE | GSWIP_PCE_TBL_CTRL_VLD |
631 GSWIP_PCE_TBL_CTRL_GMAP_MASK);
632 if (tbl->type)
633 crtl |= GSWIP_PCE_TBL_CTRL_TYPE;
634 if (tbl->valid)
635 crtl |= GSWIP_PCE_TBL_CTRL_VLD;
636 crtl |= (tbl->gmap << 7) & GSWIP_PCE_TBL_CTRL_GMAP_MASK;
637 crtl |= GSWIP_PCE_TBL_CTRL_BAS;
638 gswip_switch_w(priv, crtl, GSWIP_PCE_TBL_CTRL);
639
640 err = gswip_switch_r_timeout(priv, GSWIP_PCE_TBL_CTRL,
641 GSWIP_PCE_TBL_CTRL_BAS);
642
643 mutex_unlock(&priv->pce_table_lock);
644
645 return err;
646 }
647
648 /* Add the LAN port into a bridge with the CPU port by
649 * default. This prevents automatic forwarding of
650 * packages between the LAN ports when no explicit
651 * bridge is configured.
652 */
gswip_add_single_port_br(struct gswip_priv * priv,int port,bool add)653 static int gswip_add_single_port_br(struct gswip_priv *priv, int port, bool add)
654 {
655 struct gswip_pce_table_entry vlan_active = {0,};
656 struct gswip_pce_table_entry vlan_mapping = {0,};
657 unsigned int cpu_port = priv->hw_info->cpu_port;
658 int err;
659
660 vlan_active.index = port + 1;
661 vlan_active.table = GSWIP_TABLE_ACTIVE_VLAN;
662 vlan_active.key[0] = 0; /* vid */
663 vlan_active.val[0] = port + 1 /* fid */;
664 vlan_active.valid = add;
665 err = gswip_pce_table_entry_write(priv, &vlan_active);
666 if (err) {
667 dev_err(priv->dev, "failed to write active VLAN: %d\n", err);
668 return err;
669 }
670
671 if (!add)
672 return 0;
673
674 vlan_mapping.index = port + 1;
675 vlan_mapping.table = GSWIP_TABLE_VLAN_MAPPING;
676 vlan_mapping.val[0] = 0 /* vid */;
677 vlan_mapping.val[1] = BIT(port) | BIT(cpu_port);
678 vlan_mapping.val[2] = 0;
679 err = gswip_pce_table_entry_write(priv, &vlan_mapping);
680 if (err) {
681 dev_err(priv->dev, "failed to write VLAN mapping: %d\n", err);
682 return err;
683 }
684
685 return 0;
686 }
687
gswip_port_setup(struct dsa_switch * ds,int port)688 static int gswip_port_setup(struct dsa_switch *ds, int port)
689 {
690 struct gswip_priv *priv = ds->priv;
691 int err;
692
693 if (!dsa_is_cpu_port(ds, port)) {
694 err = gswip_add_single_port_br(priv, port, true);
695 if (err)
696 return err;
697 }
698
699 return 0;
700 }
701
gswip_port_enable(struct dsa_switch * ds,int port,struct phy_device * phydev)702 static int gswip_port_enable(struct dsa_switch *ds, int port,
703 struct phy_device *phydev)
704 {
705 struct gswip_priv *priv = ds->priv;
706
707 if (!dsa_is_cpu_port(ds, port)) {
708 u32 mdio_phy = 0;
709
710 if (phydev)
711 mdio_phy = phydev->mdio.addr & GSWIP_MDIO_PHY_ADDR_MASK;
712
713 gswip_mdio_mask(priv, GSWIP_MDIO_PHY_ADDR_MASK, mdio_phy,
714 GSWIP_MDIO_PHYp(port));
715 }
716
717 /* RMON Counter Enable for port */
718 gswip_switch_w(priv, GSWIP_BM_PCFG_CNTEN, GSWIP_BM_PCFGp(port));
719
720 /* enable port fetch/store dma & VLAN Modification */
721 gswip_switch_mask(priv, 0, GSWIP_FDMA_PCTRL_EN |
722 GSWIP_FDMA_PCTRL_VLANMOD_BOTH,
723 GSWIP_FDMA_PCTRLp(port));
724 gswip_switch_mask(priv, 0, GSWIP_SDMA_PCTRL_EN,
725 GSWIP_SDMA_PCTRLp(port));
726
727 return 0;
728 }
729
gswip_port_disable(struct dsa_switch * ds,int port)730 static void gswip_port_disable(struct dsa_switch *ds, int port)
731 {
732 struct gswip_priv *priv = ds->priv;
733
734 gswip_switch_mask(priv, GSWIP_FDMA_PCTRL_EN, 0,
735 GSWIP_FDMA_PCTRLp(port));
736 gswip_switch_mask(priv, GSWIP_SDMA_PCTRL_EN, 0,
737 GSWIP_SDMA_PCTRLp(port));
738 }
739
gswip_pce_load_microcode(struct gswip_priv * priv)740 static int gswip_pce_load_microcode(struct gswip_priv *priv)
741 {
742 int i;
743 int err;
744
745 gswip_switch_mask(priv, GSWIP_PCE_TBL_CTRL_ADDR_MASK |
746 GSWIP_PCE_TBL_CTRL_OPMOD_MASK,
747 GSWIP_PCE_TBL_CTRL_OPMOD_ADWR, GSWIP_PCE_TBL_CTRL);
748 gswip_switch_w(priv, 0, GSWIP_PCE_TBL_MASK);
749
750 for (i = 0; i < ARRAY_SIZE(gswip_pce_microcode); i++) {
751 gswip_switch_w(priv, i, GSWIP_PCE_TBL_ADDR);
752 gswip_switch_w(priv, gswip_pce_microcode[i].val_0,
753 GSWIP_PCE_TBL_VAL(0));
754 gswip_switch_w(priv, gswip_pce_microcode[i].val_1,
755 GSWIP_PCE_TBL_VAL(1));
756 gswip_switch_w(priv, gswip_pce_microcode[i].val_2,
757 GSWIP_PCE_TBL_VAL(2));
758 gswip_switch_w(priv, gswip_pce_microcode[i].val_3,
759 GSWIP_PCE_TBL_VAL(3));
760
761 /* start the table access: */
762 gswip_switch_mask(priv, 0, GSWIP_PCE_TBL_CTRL_BAS,
763 GSWIP_PCE_TBL_CTRL);
764 err = gswip_switch_r_timeout(priv, GSWIP_PCE_TBL_CTRL,
765 GSWIP_PCE_TBL_CTRL_BAS);
766 if (err)
767 return err;
768 }
769
770 /* tell the switch that the microcode is loaded */
771 gswip_switch_mask(priv, 0, GSWIP_PCE_GCTRL_0_MC_VALID,
772 GSWIP_PCE_GCTRL_0);
773
774 return 0;
775 }
776
gswip_port_vlan_filtering(struct dsa_switch * ds,int port,bool vlan_filtering,struct netlink_ext_ack * extack)777 static int gswip_port_vlan_filtering(struct dsa_switch *ds, int port,
778 bool vlan_filtering,
779 struct netlink_ext_ack *extack)
780 {
781 struct net_device *bridge = dsa_port_bridge_dev_get(dsa_to_port(ds, port));
782 struct gswip_priv *priv = ds->priv;
783
784 /* Do not allow changing the VLAN filtering options while in bridge */
785 if (bridge && !!(priv->port_vlan_filter & BIT(port)) != vlan_filtering) {
786 NL_SET_ERR_MSG_MOD(extack,
787 "Dynamic toggling of vlan_filtering not supported");
788 return -EIO;
789 }
790
791 if (vlan_filtering) {
792 /* Use tag based VLAN */
793 gswip_switch_mask(priv,
794 GSWIP_PCE_VCTRL_VSR,
795 GSWIP_PCE_VCTRL_UVR | GSWIP_PCE_VCTRL_VIMR |
796 GSWIP_PCE_VCTRL_VEMR,
797 GSWIP_PCE_VCTRL(port));
798 gswip_switch_mask(priv, GSWIP_PCE_PCTRL_0_TVM, 0,
799 GSWIP_PCE_PCTRL_0p(port));
800 } else {
801 /* Use port based VLAN */
802 gswip_switch_mask(priv,
803 GSWIP_PCE_VCTRL_UVR | GSWIP_PCE_VCTRL_VIMR |
804 GSWIP_PCE_VCTRL_VEMR,
805 GSWIP_PCE_VCTRL_VSR,
806 GSWIP_PCE_VCTRL(port));
807 gswip_switch_mask(priv, 0, GSWIP_PCE_PCTRL_0_TVM,
808 GSWIP_PCE_PCTRL_0p(port));
809 }
810
811 return 0;
812 }
813
gswip_setup(struct dsa_switch * ds)814 static int gswip_setup(struct dsa_switch *ds)
815 {
816 struct gswip_priv *priv = ds->priv;
817 unsigned int cpu_port = priv->hw_info->cpu_port;
818 int i;
819 int err;
820
821 gswip_switch_w(priv, GSWIP_SWRES_R0, GSWIP_SWRES);
822 usleep_range(5000, 10000);
823 gswip_switch_w(priv, 0, GSWIP_SWRES);
824
825 /* disable port fetch/store dma on all ports */
826 for (i = 0; i < priv->hw_info->max_ports; i++) {
827 gswip_port_disable(ds, i);
828 gswip_port_vlan_filtering(ds, i, false, NULL);
829 }
830
831 /* enable Switch */
832 gswip_mdio_mask(priv, 0, GSWIP_MDIO_GLOB_ENABLE, GSWIP_MDIO_GLOB);
833
834 err = gswip_pce_load_microcode(priv);
835 if (err) {
836 dev_err(priv->dev, "writing PCE microcode failed, %i\n", err);
837 return err;
838 }
839
840 /* Default unknown Broadcast/Multicast/Unicast port maps */
841 gswip_switch_w(priv, BIT(cpu_port), GSWIP_PCE_PMAP1);
842 gswip_switch_w(priv, BIT(cpu_port), GSWIP_PCE_PMAP2);
843 gswip_switch_w(priv, BIT(cpu_port), GSWIP_PCE_PMAP3);
844
845 /* Deactivate MDIO PHY auto polling. Some PHYs as the AR8030 have an
846 * interoperability problem with this auto polling mechanism because
847 * their status registers think that the link is in a different state
848 * than it actually is. For the AR8030 it has the BMSR_ESTATEN bit set
849 * as well as ESTATUS_1000_TFULL and ESTATUS_1000_XFULL. This makes the
850 * auto polling state machine consider the link being negotiated with
851 * 1Gbit/s. Since the PHY itself is a Fast Ethernet RMII PHY this leads
852 * to the switch port being completely dead (RX and TX are both not
853 * working).
854 * Also with various other PHY / port combinations (PHY11G GPHY, PHY22F
855 * GPHY, external RGMII PEF7071/7072) any traffic would stop. Sometimes
856 * it would work fine for a few minutes to hours and then stop, on
857 * other device it would no traffic could be sent or received at all.
858 * Testing shows that when PHY auto polling is disabled these problems
859 * go away.
860 */
861 gswip_mdio_w(priv, 0x0, GSWIP_MDIO_MDC_CFG0);
862
863 /* Configure the MDIO Clock 2.5 MHz */
864 gswip_mdio_mask(priv, 0xff, 0x09, GSWIP_MDIO_MDC_CFG1);
865
866 /* Disable the xMII interface and clear it's isolation bit */
867 for (i = 0; i < priv->hw_info->max_ports; i++)
868 gswip_mii_mask_cfg(priv,
869 GSWIP_MII_CFG_EN | GSWIP_MII_CFG_ISOLATE,
870 0, i);
871
872 /* enable special tag insertion on cpu port */
873 gswip_switch_mask(priv, 0, GSWIP_FDMA_PCTRL_STEN,
874 GSWIP_FDMA_PCTRLp(cpu_port));
875
876 /* accept special tag in ingress direction */
877 gswip_switch_mask(priv, 0, GSWIP_PCE_PCTRL_0_INGRESS,
878 GSWIP_PCE_PCTRL_0p(cpu_port));
879
880 gswip_switch_mask(priv, 0, GSWIP_BM_QUEUE_GCTRL_GL_MOD,
881 GSWIP_BM_QUEUE_GCTRL);
882
883 /* VLAN aware Switching */
884 gswip_switch_mask(priv, 0, GSWIP_PCE_GCTRL_0_VLAN, GSWIP_PCE_GCTRL_0);
885
886 /* Flush MAC Table */
887 gswip_switch_mask(priv, 0, GSWIP_PCE_GCTRL_0_MTFL, GSWIP_PCE_GCTRL_0);
888
889 err = gswip_switch_r_timeout(priv, GSWIP_PCE_GCTRL_0,
890 GSWIP_PCE_GCTRL_0_MTFL);
891 if (err) {
892 dev_err(priv->dev, "MAC flushing didn't finish\n");
893 return err;
894 }
895
896 ds->mtu_enforcement_ingress = true;
897
898 ds->configure_vlan_while_not_filtering = false;
899
900 return 0;
901 }
902
gswip_get_tag_protocol(struct dsa_switch * ds,int port,enum dsa_tag_protocol mp)903 static enum dsa_tag_protocol gswip_get_tag_protocol(struct dsa_switch *ds,
904 int port,
905 enum dsa_tag_protocol mp)
906 {
907 return DSA_TAG_PROTO_GSWIP;
908 }
909
gswip_vlan_active_create(struct gswip_priv * priv,struct net_device * bridge,int fid,u16 vid)910 static int gswip_vlan_active_create(struct gswip_priv *priv,
911 struct net_device *bridge,
912 int fid, u16 vid)
913 {
914 struct gswip_pce_table_entry vlan_active = {0,};
915 unsigned int max_ports = priv->hw_info->max_ports;
916 int idx = -1;
917 int err;
918 int i;
919
920 /* Look for a free slot */
921 for (i = max_ports; i < ARRAY_SIZE(priv->vlans); i++) {
922 if (!priv->vlans[i].bridge) {
923 idx = i;
924 break;
925 }
926 }
927
928 if (idx == -1)
929 return -ENOSPC;
930
931 if (fid == -1)
932 fid = idx;
933
934 vlan_active.index = idx;
935 vlan_active.table = GSWIP_TABLE_ACTIVE_VLAN;
936 vlan_active.key[0] = vid;
937 vlan_active.val[0] = fid;
938 vlan_active.valid = true;
939
940 err = gswip_pce_table_entry_write(priv, &vlan_active);
941 if (err) {
942 dev_err(priv->dev, "failed to write active VLAN: %d\n", err);
943 return err;
944 }
945
946 priv->vlans[idx].bridge = bridge;
947 priv->vlans[idx].vid = vid;
948 priv->vlans[idx].fid = fid;
949
950 return idx;
951 }
952
gswip_vlan_active_remove(struct gswip_priv * priv,int idx)953 static int gswip_vlan_active_remove(struct gswip_priv *priv, int idx)
954 {
955 struct gswip_pce_table_entry vlan_active = {0,};
956 int err;
957
958 vlan_active.index = idx;
959 vlan_active.table = GSWIP_TABLE_ACTIVE_VLAN;
960 vlan_active.valid = false;
961 err = gswip_pce_table_entry_write(priv, &vlan_active);
962 if (err)
963 dev_err(priv->dev, "failed to delete active VLAN: %d\n", err);
964 priv->vlans[idx].bridge = NULL;
965
966 return err;
967 }
968
gswip_vlan_add_unaware(struct gswip_priv * priv,struct net_device * bridge,int port)969 static int gswip_vlan_add_unaware(struct gswip_priv *priv,
970 struct net_device *bridge, int port)
971 {
972 struct gswip_pce_table_entry vlan_mapping = {0,};
973 unsigned int max_ports = priv->hw_info->max_ports;
974 unsigned int cpu_port = priv->hw_info->cpu_port;
975 bool active_vlan_created = false;
976 int idx = -1;
977 int i;
978 int err;
979
980 /* Check if there is already a page for this bridge */
981 for (i = max_ports; i < ARRAY_SIZE(priv->vlans); i++) {
982 if (priv->vlans[i].bridge == bridge) {
983 idx = i;
984 break;
985 }
986 }
987
988 /* If this bridge is not programmed yet, add a Active VLAN table
989 * entry in a free slot and prepare the VLAN mapping table entry.
990 */
991 if (idx == -1) {
992 idx = gswip_vlan_active_create(priv, bridge, -1, 0);
993 if (idx < 0)
994 return idx;
995 active_vlan_created = true;
996
997 vlan_mapping.index = idx;
998 vlan_mapping.table = GSWIP_TABLE_VLAN_MAPPING;
999 /* VLAN ID byte, maps to the VLAN ID of vlan active table */
1000 vlan_mapping.val[0] = 0;
1001 } else {
1002 /* Read the existing VLAN mapping entry from the switch */
1003 vlan_mapping.index = idx;
1004 vlan_mapping.table = GSWIP_TABLE_VLAN_MAPPING;
1005 err = gswip_pce_table_entry_read(priv, &vlan_mapping);
1006 if (err) {
1007 dev_err(priv->dev, "failed to read VLAN mapping: %d\n",
1008 err);
1009 return err;
1010 }
1011 }
1012
1013 /* Update the VLAN mapping entry and write it to the switch */
1014 vlan_mapping.val[1] |= BIT(cpu_port);
1015 vlan_mapping.val[1] |= BIT(port);
1016 err = gswip_pce_table_entry_write(priv, &vlan_mapping);
1017 if (err) {
1018 dev_err(priv->dev, "failed to write VLAN mapping: %d\n", err);
1019 /* In case an Active VLAN was creaetd delete it again */
1020 if (active_vlan_created)
1021 gswip_vlan_active_remove(priv, idx);
1022 return err;
1023 }
1024
1025 gswip_switch_w(priv, 0, GSWIP_PCE_DEFPVID(port));
1026 return 0;
1027 }
1028
gswip_vlan_add_aware(struct gswip_priv * priv,struct net_device * bridge,int port,u16 vid,bool untagged,bool pvid)1029 static int gswip_vlan_add_aware(struct gswip_priv *priv,
1030 struct net_device *bridge, int port,
1031 u16 vid, bool untagged,
1032 bool pvid)
1033 {
1034 struct gswip_pce_table_entry vlan_mapping = {0,};
1035 unsigned int max_ports = priv->hw_info->max_ports;
1036 unsigned int cpu_port = priv->hw_info->cpu_port;
1037 bool active_vlan_created = false;
1038 int idx = -1;
1039 int fid = -1;
1040 int i;
1041 int err;
1042
1043 /* Check if there is already a page for this bridge */
1044 for (i = max_ports; i < ARRAY_SIZE(priv->vlans); i++) {
1045 if (priv->vlans[i].bridge == bridge) {
1046 if (fid != -1 && fid != priv->vlans[i].fid)
1047 dev_err(priv->dev, "one bridge with multiple flow ids\n");
1048 fid = priv->vlans[i].fid;
1049 if (priv->vlans[i].vid == vid) {
1050 idx = i;
1051 break;
1052 }
1053 }
1054 }
1055
1056 /* If this bridge is not programmed yet, add a Active VLAN table
1057 * entry in a free slot and prepare the VLAN mapping table entry.
1058 */
1059 if (idx == -1) {
1060 idx = gswip_vlan_active_create(priv, bridge, fid, vid);
1061 if (idx < 0)
1062 return idx;
1063 active_vlan_created = true;
1064
1065 vlan_mapping.index = idx;
1066 vlan_mapping.table = GSWIP_TABLE_VLAN_MAPPING;
1067 /* VLAN ID byte, maps to the VLAN ID of vlan active table */
1068 vlan_mapping.val[0] = vid;
1069 } else {
1070 /* Read the existing VLAN mapping entry from the switch */
1071 vlan_mapping.index = idx;
1072 vlan_mapping.table = GSWIP_TABLE_VLAN_MAPPING;
1073 err = gswip_pce_table_entry_read(priv, &vlan_mapping);
1074 if (err) {
1075 dev_err(priv->dev, "failed to read VLAN mapping: %d\n",
1076 err);
1077 return err;
1078 }
1079 }
1080
1081 vlan_mapping.val[0] = vid;
1082 /* Update the VLAN mapping entry and write it to the switch */
1083 vlan_mapping.val[1] |= BIT(cpu_port);
1084 vlan_mapping.val[2] |= BIT(cpu_port);
1085 vlan_mapping.val[1] |= BIT(port);
1086 if (untagged)
1087 vlan_mapping.val[2] &= ~BIT(port);
1088 else
1089 vlan_mapping.val[2] |= BIT(port);
1090 err = gswip_pce_table_entry_write(priv, &vlan_mapping);
1091 if (err) {
1092 dev_err(priv->dev, "failed to write VLAN mapping: %d\n", err);
1093 /* In case an Active VLAN was creaetd delete it again */
1094 if (active_vlan_created)
1095 gswip_vlan_active_remove(priv, idx);
1096 return err;
1097 }
1098
1099 if (pvid)
1100 gswip_switch_w(priv, idx, GSWIP_PCE_DEFPVID(port));
1101
1102 return 0;
1103 }
1104
gswip_vlan_remove(struct gswip_priv * priv,struct net_device * bridge,int port,u16 vid,bool pvid,bool vlan_aware)1105 static int gswip_vlan_remove(struct gswip_priv *priv,
1106 struct net_device *bridge, int port,
1107 u16 vid, bool pvid, bool vlan_aware)
1108 {
1109 struct gswip_pce_table_entry vlan_mapping = {0,};
1110 unsigned int max_ports = priv->hw_info->max_ports;
1111 unsigned int cpu_port = priv->hw_info->cpu_port;
1112 int idx = -1;
1113 int i;
1114 int err;
1115
1116 /* Check if there is already a page for this bridge */
1117 for (i = max_ports; i < ARRAY_SIZE(priv->vlans); i++) {
1118 if (priv->vlans[i].bridge == bridge &&
1119 (!vlan_aware || priv->vlans[i].vid == vid)) {
1120 idx = i;
1121 break;
1122 }
1123 }
1124
1125 if (idx == -1) {
1126 dev_err(priv->dev, "bridge to leave does not exists\n");
1127 return -ENOENT;
1128 }
1129
1130 vlan_mapping.index = idx;
1131 vlan_mapping.table = GSWIP_TABLE_VLAN_MAPPING;
1132 err = gswip_pce_table_entry_read(priv, &vlan_mapping);
1133 if (err) {
1134 dev_err(priv->dev, "failed to read VLAN mapping: %d\n", err);
1135 return err;
1136 }
1137
1138 vlan_mapping.val[1] &= ~BIT(port);
1139 vlan_mapping.val[2] &= ~BIT(port);
1140 err = gswip_pce_table_entry_write(priv, &vlan_mapping);
1141 if (err) {
1142 dev_err(priv->dev, "failed to write VLAN mapping: %d\n", err);
1143 return err;
1144 }
1145
1146 /* In case all ports are removed from the bridge, remove the VLAN */
1147 if ((vlan_mapping.val[1] & ~BIT(cpu_port)) == 0) {
1148 err = gswip_vlan_active_remove(priv, idx);
1149 if (err) {
1150 dev_err(priv->dev, "failed to write active VLAN: %d\n",
1151 err);
1152 return err;
1153 }
1154 }
1155
1156 /* GSWIP 2.2 (GRX300) and later program here the VID directly. */
1157 if (pvid)
1158 gswip_switch_w(priv, 0, GSWIP_PCE_DEFPVID(port));
1159
1160 return 0;
1161 }
1162
gswip_port_bridge_join(struct dsa_switch * ds,int port,struct dsa_bridge bridge,bool * tx_fwd_offload,struct netlink_ext_ack * extack)1163 static int gswip_port_bridge_join(struct dsa_switch *ds, int port,
1164 struct dsa_bridge bridge,
1165 bool *tx_fwd_offload,
1166 struct netlink_ext_ack *extack)
1167 {
1168 struct net_device *br = bridge.dev;
1169 struct gswip_priv *priv = ds->priv;
1170 int err;
1171
1172 /* When the bridge uses VLAN filtering we have to configure VLAN
1173 * specific bridges. No bridge is configured here.
1174 */
1175 if (!br_vlan_enabled(br)) {
1176 err = gswip_vlan_add_unaware(priv, br, port);
1177 if (err)
1178 return err;
1179 priv->port_vlan_filter &= ~BIT(port);
1180 } else {
1181 priv->port_vlan_filter |= BIT(port);
1182 }
1183 return gswip_add_single_port_br(priv, port, false);
1184 }
1185
gswip_port_bridge_leave(struct dsa_switch * ds,int port,struct dsa_bridge bridge)1186 static void gswip_port_bridge_leave(struct dsa_switch *ds, int port,
1187 struct dsa_bridge bridge)
1188 {
1189 struct net_device *br = bridge.dev;
1190 struct gswip_priv *priv = ds->priv;
1191
1192 gswip_add_single_port_br(priv, port, true);
1193
1194 /* When the bridge uses VLAN filtering we have to configure VLAN
1195 * specific bridges. No bridge is configured here.
1196 */
1197 if (!br_vlan_enabled(br))
1198 gswip_vlan_remove(priv, br, port, 0, true, false);
1199 }
1200
gswip_port_vlan_prepare(struct dsa_switch * ds,int port,const struct switchdev_obj_port_vlan * vlan,struct netlink_ext_ack * extack)1201 static int gswip_port_vlan_prepare(struct dsa_switch *ds, int port,
1202 const struct switchdev_obj_port_vlan *vlan,
1203 struct netlink_ext_ack *extack)
1204 {
1205 struct net_device *bridge = dsa_port_bridge_dev_get(dsa_to_port(ds, port));
1206 struct gswip_priv *priv = ds->priv;
1207 unsigned int max_ports = priv->hw_info->max_ports;
1208 int pos = max_ports;
1209 int i, idx = -1;
1210
1211 /* We only support VLAN filtering on bridges */
1212 if (!dsa_is_cpu_port(ds, port) && !bridge)
1213 return -EOPNOTSUPP;
1214
1215 /* Check if there is already a page for this VLAN */
1216 for (i = max_ports; i < ARRAY_SIZE(priv->vlans); i++) {
1217 if (priv->vlans[i].bridge == bridge &&
1218 priv->vlans[i].vid == vlan->vid) {
1219 idx = i;
1220 break;
1221 }
1222 }
1223
1224 /* If this VLAN is not programmed yet, we have to reserve
1225 * one entry in the VLAN table. Make sure we start at the
1226 * next position round.
1227 */
1228 if (idx == -1) {
1229 /* Look for a free slot */
1230 for (; pos < ARRAY_SIZE(priv->vlans); pos++) {
1231 if (!priv->vlans[pos].bridge) {
1232 idx = pos;
1233 pos++;
1234 break;
1235 }
1236 }
1237
1238 if (idx == -1) {
1239 NL_SET_ERR_MSG_MOD(extack, "No slot in VLAN table");
1240 return -ENOSPC;
1241 }
1242 }
1243
1244 return 0;
1245 }
1246
gswip_port_vlan_add(struct dsa_switch * ds,int port,const struct switchdev_obj_port_vlan * vlan,struct netlink_ext_ack * extack)1247 static int gswip_port_vlan_add(struct dsa_switch *ds, int port,
1248 const struct switchdev_obj_port_vlan *vlan,
1249 struct netlink_ext_ack *extack)
1250 {
1251 struct net_device *bridge = dsa_port_bridge_dev_get(dsa_to_port(ds, port));
1252 struct gswip_priv *priv = ds->priv;
1253 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
1254 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID;
1255 int err;
1256
1257 err = gswip_port_vlan_prepare(ds, port, vlan, extack);
1258 if (err)
1259 return err;
1260
1261 /* We have to receive all packets on the CPU port and should not
1262 * do any VLAN filtering here. This is also called with bridge
1263 * NULL and then we do not know for which bridge to configure
1264 * this.
1265 */
1266 if (dsa_is_cpu_port(ds, port))
1267 return 0;
1268
1269 return gswip_vlan_add_aware(priv, bridge, port, vlan->vid,
1270 untagged, pvid);
1271 }
1272
gswip_port_vlan_del(struct dsa_switch * ds,int port,const struct switchdev_obj_port_vlan * vlan)1273 static int gswip_port_vlan_del(struct dsa_switch *ds, int port,
1274 const struct switchdev_obj_port_vlan *vlan)
1275 {
1276 struct net_device *bridge = dsa_port_bridge_dev_get(dsa_to_port(ds, port));
1277 struct gswip_priv *priv = ds->priv;
1278 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID;
1279
1280 /* We have to receive all packets on the CPU port and should not
1281 * do any VLAN filtering here. This is also called with bridge
1282 * NULL and then we do not know for which bridge to configure
1283 * this.
1284 */
1285 if (dsa_is_cpu_port(ds, port))
1286 return 0;
1287
1288 return gswip_vlan_remove(priv, bridge, port, vlan->vid, pvid, true);
1289 }
1290
gswip_port_fast_age(struct dsa_switch * ds,int port)1291 static void gswip_port_fast_age(struct dsa_switch *ds, int port)
1292 {
1293 struct gswip_priv *priv = ds->priv;
1294 struct gswip_pce_table_entry mac_bridge = {0,};
1295 int i;
1296 int err;
1297
1298 for (i = 0; i < 2048; i++) {
1299 mac_bridge.table = GSWIP_TABLE_MAC_BRIDGE;
1300 mac_bridge.index = i;
1301
1302 err = gswip_pce_table_entry_read(priv, &mac_bridge);
1303 if (err) {
1304 dev_err(priv->dev, "failed to read mac bridge: %d\n",
1305 err);
1306 return;
1307 }
1308
1309 if (!mac_bridge.valid)
1310 continue;
1311
1312 if (mac_bridge.val[1] & GSWIP_TABLE_MAC_BRIDGE_VAL1_STATIC)
1313 continue;
1314
1315 if (port != FIELD_GET(GSWIP_TABLE_MAC_BRIDGE_VAL0_PORT,
1316 mac_bridge.val[0]))
1317 continue;
1318
1319 mac_bridge.valid = false;
1320 err = gswip_pce_table_entry_write(priv, &mac_bridge);
1321 if (err) {
1322 dev_err(priv->dev, "failed to write mac bridge: %d\n",
1323 err);
1324 return;
1325 }
1326 }
1327 }
1328
gswip_port_stp_state_set(struct dsa_switch * ds,int port,u8 state)1329 static void gswip_port_stp_state_set(struct dsa_switch *ds, int port, u8 state)
1330 {
1331 struct gswip_priv *priv = ds->priv;
1332 u32 stp_state;
1333
1334 switch (state) {
1335 case BR_STATE_DISABLED:
1336 gswip_switch_mask(priv, GSWIP_SDMA_PCTRL_EN, 0,
1337 GSWIP_SDMA_PCTRLp(port));
1338 return;
1339 case BR_STATE_BLOCKING:
1340 case BR_STATE_LISTENING:
1341 stp_state = GSWIP_PCE_PCTRL_0_PSTATE_LISTEN;
1342 break;
1343 case BR_STATE_LEARNING:
1344 stp_state = GSWIP_PCE_PCTRL_0_PSTATE_LEARNING;
1345 break;
1346 case BR_STATE_FORWARDING:
1347 stp_state = GSWIP_PCE_PCTRL_0_PSTATE_FORWARDING;
1348 break;
1349 default:
1350 dev_err(priv->dev, "invalid STP state: %d\n", state);
1351 return;
1352 }
1353
1354 gswip_switch_mask(priv, 0, GSWIP_SDMA_PCTRL_EN,
1355 GSWIP_SDMA_PCTRLp(port));
1356 gswip_switch_mask(priv, GSWIP_PCE_PCTRL_0_PSTATE_MASK, stp_state,
1357 GSWIP_PCE_PCTRL_0p(port));
1358 }
1359
gswip_port_fdb(struct dsa_switch * ds,int port,const unsigned char * addr,u16 vid,bool add)1360 static int gswip_port_fdb(struct dsa_switch *ds, int port,
1361 const unsigned char *addr, u16 vid, bool add)
1362 {
1363 struct net_device *bridge = dsa_port_bridge_dev_get(dsa_to_port(ds, port));
1364 struct gswip_priv *priv = ds->priv;
1365 struct gswip_pce_table_entry mac_bridge = {0,};
1366 unsigned int max_ports = priv->hw_info->max_ports;
1367 int fid = -1;
1368 int i;
1369 int err;
1370
1371 /* Operation not supported on the CPU port, don't throw errors */
1372 if (!bridge)
1373 return 0;
1374
1375 for (i = max_ports; i < ARRAY_SIZE(priv->vlans); i++) {
1376 if (priv->vlans[i].bridge == bridge) {
1377 fid = priv->vlans[i].fid;
1378 break;
1379 }
1380 }
1381
1382 if (fid == -1) {
1383 dev_err(priv->dev, "no FID found for bridge %s\n",
1384 bridge->name);
1385 return -EINVAL;
1386 }
1387
1388 mac_bridge.table = GSWIP_TABLE_MAC_BRIDGE;
1389 mac_bridge.key_mode = true;
1390 mac_bridge.key[0] = addr[5] | (addr[4] << 8);
1391 mac_bridge.key[1] = addr[3] | (addr[2] << 8);
1392 mac_bridge.key[2] = addr[1] | (addr[0] << 8);
1393 mac_bridge.key[3] = FIELD_PREP(GSWIP_TABLE_MAC_BRIDGE_KEY3_FID, fid);
1394 mac_bridge.val[0] = add ? BIT(port) : 0; /* port map */
1395 mac_bridge.val[1] = GSWIP_TABLE_MAC_BRIDGE_VAL1_STATIC;
1396 mac_bridge.valid = add;
1397
1398 err = gswip_pce_table_entry_write(priv, &mac_bridge);
1399 if (err)
1400 dev_err(priv->dev, "failed to write mac bridge: %d\n", err);
1401
1402 return err;
1403 }
1404
gswip_port_fdb_add(struct dsa_switch * ds,int port,const unsigned char * addr,u16 vid,struct dsa_db db)1405 static int gswip_port_fdb_add(struct dsa_switch *ds, int port,
1406 const unsigned char *addr, u16 vid,
1407 struct dsa_db db)
1408 {
1409 return gswip_port_fdb(ds, port, addr, vid, true);
1410 }
1411
gswip_port_fdb_del(struct dsa_switch * ds,int port,const unsigned char * addr,u16 vid,struct dsa_db db)1412 static int gswip_port_fdb_del(struct dsa_switch *ds, int port,
1413 const unsigned char *addr, u16 vid,
1414 struct dsa_db db)
1415 {
1416 return gswip_port_fdb(ds, port, addr, vid, false);
1417 }
1418
gswip_port_fdb_dump(struct dsa_switch * ds,int port,dsa_fdb_dump_cb_t * cb,void * data)1419 static int gswip_port_fdb_dump(struct dsa_switch *ds, int port,
1420 dsa_fdb_dump_cb_t *cb, void *data)
1421 {
1422 struct gswip_priv *priv = ds->priv;
1423 struct gswip_pce_table_entry mac_bridge = {0,};
1424 unsigned char addr[ETH_ALEN];
1425 int i;
1426 int err;
1427
1428 for (i = 0; i < 2048; i++) {
1429 mac_bridge.table = GSWIP_TABLE_MAC_BRIDGE;
1430 mac_bridge.index = i;
1431
1432 err = gswip_pce_table_entry_read(priv, &mac_bridge);
1433 if (err) {
1434 dev_err(priv->dev,
1435 "failed to read mac bridge entry %d: %d\n",
1436 i, err);
1437 return err;
1438 }
1439
1440 if (!mac_bridge.valid)
1441 continue;
1442
1443 addr[5] = mac_bridge.key[0] & 0xff;
1444 addr[4] = (mac_bridge.key[0] >> 8) & 0xff;
1445 addr[3] = mac_bridge.key[1] & 0xff;
1446 addr[2] = (mac_bridge.key[1] >> 8) & 0xff;
1447 addr[1] = mac_bridge.key[2] & 0xff;
1448 addr[0] = (mac_bridge.key[2] >> 8) & 0xff;
1449 if (mac_bridge.val[1] & GSWIP_TABLE_MAC_BRIDGE_VAL1_STATIC) {
1450 if (mac_bridge.val[0] & BIT(port)) {
1451 err = cb(addr, 0, true, data);
1452 if (err)
1453 return err;
1454 }
1455 } else {
1456 if (port == FIELD_GET(GSWIP_TABLE_MAC_BRIDGE_VAL0_PORT,
1457 mac_bridge.val[0])) {
1458 err = cb(addr, 0, false, data);
1459 if (err)
1460 return err;
1461 }
1462 }
1463 }
1464 return 0;
1465 }
1466
gswip_port_max_mtu(struct dsa_switch * ds,int port)1467 static int gswip_port_max_mtu(struct dsa_switch *ds, int port)
1468 {
1469 /* Includes 8 bytes for special header. */
1470 return GSWIP_MAX_PACKET_LENGTH - VLAN_ETH_HLEN - ETH_FCS_LEN;
1471 }
1472
gswip_port_change_mtu(struct dsa_switch * ds,int port,int new_mtu)1473 static int gswip_port_change_mtu(struct dsa_switch *ds, int port, int new_mtu)
1474 {
1475 struct gswip_priv *priv = ds->priv;
1476
1477 /* CPU port always has maximum mtu of user ports, so use it to set
1478 * switch frame size, including 8 byte special header.
1479 */
1480 if (dsa_is_cpu_port(ds, port)) {
1481 new_mtu += 8;
1482 gswip_switch_w(priv, VLAN_ETH_HLEN + new_mtu + ETH_FCS_LEN,
1483 GSWIP_MAC_FLEN);
1484 }
1485
1486 /* Enable MLEN for ports with non-standard MTUs, including the special
1487 * header on the CPU port added above.
1488 */
1489 if (new_mtu != ETH_DATA_LEN)
1490 gswip_switch_mask(priv, 0, GSWIP_MAC_CTRL_2_MLEN,
1491 GSWIP_MAC_CTRL_2p(port));
1492 else
1493 gswip_switch_mask(priv, GSWIP_MAC_CTRL_2_MLEN, 0,
1494 GSWIP_MAC_CTRL_2p(port));
1495
1496 return 0;
1497 }
1498
gswip_xrx200_phylink_get_caps(struct dsa_switch * ds,int port,struct phylink_config * config)1499 static void gswip_xrx200_phylink_get_caps(struct dsa_switch *ds, int port,
1500 struct phylink_config *config)
1501 {
1502 switch (port) {
1503 case 0:
1504 case 1:
1505 phy_interface_set_rgmii(config->supported_interfaces);
1506 __set_bit(PHY_INTERFACE_MODE_MII,
1507 config->supported_interfaces);
1508 __set_bit(PHY_INTERFACE_MODE_REVMII,
1509 config->supported_interfaces);
1510 __set_bit(PHY_INTERFACE_MODE_RMII,
1511 config->supported_interfaces);
1512 break;
1513
1514 case 2:
1515 case 3:
1516 case 4:
1517 case 6:
1518 __set_bit(PHY_INTERFACE_MODE_INTERNAL,
1519 config->supported_interfaces);
1520 break;
1521
1522 case 5:
1523 phy_interface_set_rgmii(config->supported_interfaces);
1524 __set_bit(PHY_INTERFACE_MODE_INTERNAL,
1525 config->supported_interfaces);
1526 break;
1527 }
1528
1529 config->mac_capabilities = MAC_ASYM_PAUSE | MAC_SYM_PAUSE |
1530 MAC_10 | MAC_100 | MAC_1000;
1531 }
1532
gswip_xrx300_phylink_get_caps(struct dsa_switch * ds,int port,struct phylink_config * config)1533 static void gswip_xrx300_phylink_get_caps(struct dsa_switch *ds, int port,
1534 struct phylink_config *config)
1535 {
1536 switch (port) {
1537 case 0:
1538 phy_interface_set_rgmii(config->supported_interfaces);
1539 __set_bit(PHY_INTERFACE_MODE_GMII,
1540 config->supported_interfaces);
1541 __set_bit(PHY_INTERFACE_MODE_RMII,
1542 config->supported_interfaces);
1543 break;
1544
1545 case 1:
1546 case 2:
1547 case 3:
1548 case 4:
1549 case 6:
1550 __set_bit(PHY_INTERFACE_MODE_INTERNAL,
1551 config->supported_interfaces);
1552 break;
1553
1554 case 5:
1555 phy_interface_set_rgmii(config->supported_interfaces);
1556 __set_bit(PHY_INTERFACE_MODE_INTERNAL,
1557 config->supported_interfaces);
1558 __set_bit(PHY_INTERFACE_MODE_RMII,
1559 config->supported_interfaces);
1560 break;
1561 }
1562
1563 config->mac_capabilities = MAC_ASYM_PAUSE | MAC_SYM_PAUSE |
1564 MAC_10 | MAC_100 | MAC_1000;
1565 }
1566
gswip_port_set_link(struct gswip_priv * priv,int port,bool link)1567 static void gswip_port_set_link(struct gswip_priv *priv, int port, bool link)
1568 {
1569 u32 mdio_phy;
1570
1571 if (link)
1572 mdio_phy = GSWIP_MDIO_PHY_LINK_UP;
1573 else
1574 mdio_phy = GSWIP_MDIO_PHY_LINK_DOWN;
1575
1576 gswip_mdio_mask(priv, GSWIP_MDIO_PHY_LINK_MASK, mdio_phy,
1577 GSWIP_MDIO_PHYp(port));
1578 }
1579
gswip_port_set_speed(struct gswip_priv * priv,int port,int speed,phy_interface_t interface)1580 static void gswip_port_set_speed(struct gswip_priv *priv, int port, int speed,
1581 phy_interface_t interface)
1582 {
1583 u32 mdio_phy = 0, mii_cfg = 0, mac_ctrl_0 = 0;
1584
1585 switch (speed) {
1586 case SPEED_10:
1587 mdio_phy = GSWIP_MDIO_PHY_SPEED_M10;
1588
1589 if (interface == PHY_INTERFACE_MODE_RMII)
1590 mii_cfg = GSWIP_MII_CFG_RATE_M50;
1591 else
1592 mii_cfg = GSWIP_MII_CFG_RATE_M2P5;
1593
1594 mac_ctrl_0 = GSWIP_MAC_CTRL_0_GMII_MII;
1595 break;
1596
1597 case SPEED_100:
1598 mdio_phy = GSWIP_MDIO_PHY_SPEED_M100;
1599
1600 if (interface == PHY_INTERFACE_MODE_RMII)
1601 mii_cfg = GSWIP_MII_CFG_RATE_M50;
1602 else
1603 mii_cfg = GSWIP_MII_CFG_RATE_M25;
1604
1605 mac_ctrl_0 = GSWIP_MAC_CTRL_0_GMII_MII;
1606 break;
1607
1608 case SPEED_1000:
1609 mdio_phy = GSWIP_MDIO_PHY_SPEED_G1;
1610
1611 mii_cfg = GSWIP_MII_CFG_RATE_M125;
1612
1613 mac_ctrl_0 = GSWIP_MAC_CTRL_0_GMII_RGMII;
1614 break;
1615 }
1616
1617 gswip_mdio_mask(priv, GSWIP_MDIO_PHY_SPEED_MASK, mdio_phy,
1618 GSWIP_MDIO_PHYp(port));
1619 gswip_mii_mask_cfg(priv, GSWIP_MII_CFG_RATE_MASK, mii_cfg, port);
1620 gswip_switch_mask(priv, GSWIP_MAC_CTRL_0_GMII_MASK, mac_ctrl_0,
1621 GSWIP_MAC_CTRL_0p(port));
1622 }
1623
gswip_port_set_duplex(struct gswip_priv * priv,int port,int duplex)1624 static void gswip_port_set_duplex(struct gswip_priv *priv, int port, int duplex)
1625 {
1626 u32 mac_ctrl_0, mdio_phy;
1627
1628 if (duplex == DUPLEX_FULL) {
1629 mac_ctrl_0 = GSWIP_MAC_CTRL_0_FDUP_EN;
1630 mdio_phy = GSWIP_MDIO_PHY_FDUP_EN;
1631 } else {
1632 mac_ctrl_0 = GSWIP_MAC_CTRL_0_FDUP_DIS;
1633 mdio_phy = GSWIP_MDIO_PHY_FDUP_DIS;
1634 }
1635
1636 gswip_switch_mask(priv, GSWIP_MAC_CTRL_0_FDUP_MASK, mac_ctrl_0,
1637 GSWIP_MAC_CTRL_0p(port));
1638 gswip_mdio_mask(priv, GSWIP_MDIO_PHY_FDUP_MASK, mdio_phy,
1639 GSWIP_MDIO_PHYp(port));
1640 }
1641
gswip_port_set_pause(struct gswip_priv * priv,int port,bool tx_pause,bool rx_pause)1642 static void gswip_port_set_pause(struct gswip_priv *priv, int port,
1643 bool tx_pause, bool rx_pause)
1644 {
1645 u32 mac_ctrl_0, mdio_phy;
1646
1647 if (tx_pause && rx_pause) {
1648 mac_ctrl_0 = GSWIP_MAC_CTRL_0_FCON_RXTX;
1649 mdio_phy = GSWIP_MDIO_PHY_FCONTX_EN |
1650 GSWIP_MDIO_PHY_FCONRX_EN;
1651 } else if (tx_pause) {
1652 mac_ctrl_0 = GSWIP_MAC_CTRL_0_FCON_TX;
1653 mdio_phy = GSWIP_MDIO_PHY_FCONTX_EN |
1654 GSWIP_MDIO_PHY_FCONRX_DIS;
1655 } else if (rx_pause) {
1656 mac_ctrl_0 = GSWIP_MAC_CTRL_0_FCON_RX;
1657 mdio_phy = GSWIP_MDIO_PHY_FCONTX_DIS |
1658 GSWIP_MDIO_PHY_FCONRX_EN;
1659 } else {
1660 mac_ctrl_0 = GSWIP_MAC_CTRL_0_FCON_NONE;
1661 mdio_phy = GSWIP_MDIO_PHY_FCONTX_DIS |
1662 GSWIP_MDIO_PHY_FCONRX_DIS;
1663 }
1664
1665 gswip_switch_mask(priv, GSWIP_MAC_CTRL_0_FCON_MASK,
1666 mac_ctrl_0, GSWIP_MAC_CTRL_0p(port));
1667 gswip_mdio_mask(priv,
1668 GSWIP_MDIO_PHY_FCONTX_MASK |
1669 GSWIP_MDIO_PHY_FCONRX_MASK,
1670 mdio_phy, GSWIP_MDIO_PHYp(port));
1671 }
1672
gswip_phylink_mac_config(struct phylink_config * config,unsigned int mode,const struct phylink_link_state * state)1673 static void gswip_phylink_mac_config(struct phylink_config *config,
1674 unsigned int mode,
1675 const struct phylink_link_state *state)
1676 {
1677 struct dsa_port *dp = dsa_phylink_to_port(config);
1678 struct gswip_priv *priv = dp->ds->priv;
1679 int port = dp->index;
1680 u32 miicfg = 0;
1681
1682 miicfg |= GSWIP_MII_CFG_LDCLKDIS;
1683
1684 switch (state->interface) {
1685 case PHY_INTERFACE_MODE_MII:
1686 case PHY_INTERFACE_MODE_INTERNAL:
1687 miicfg |= GSWIP_MII_CFG_MODE_MIIM;
1688 break;
1689 case PHY_INTERFACE_MODE_REVMII:
1690 miicfg |= GSWIP_MII_CFG_MODE_MIIP;
1691 break;
1692 case PHY_INTERFACE_MODE_RMII:
1693 miicfg |= GSWIP_MII_CFG_MODE_RMIIM;
1694 break;
1695 case PHY_INTERFACE_MODE_RGMII:
1696 case PHY_INTERFACE_MODE_RGMII_ID:
1697 case PHY_INTERFACE_MODE_RGMII_RXID:
1698 case PHY_INTERFACE_MODE_RGMII_TXID:
1699 miicfg |= GSWIP_MII_CFG_MODE_RGMII;
1700 break;
1701 case PHY_INTERFACE_MODE_GMII:
1702 miicfg |= GSWIP_MII_CFG_MODE_GMII;
1703 break;
1704 default:
1705 dev_err(dp->ds->dev,
1706 "Unsupported interface: %d\n", state->interface);
1707 return;
1708 }
1709
1710 gswip_mii_mask_cfg(priv,
1711 GSWIP_MII_CFG_MODE_MASK | GSWIP_MII_CFG_RMII_CLK |
1712 GSWIP_MII_CFG_RGMII_IBS | GSWIP_MII_CFG_LDCLKDIS,
1713 miicfg, port);
1714
1715 switch (state->interface) {
1716 case PHY_INTERFACE_MODE_RGMII_ID:
1717 gswip_mii_mask_pcdu(priv, GSWIP_MII_PCDU_TXDLY_MASK |
1718 GSWIP_MII_PCDU_RXDLY_MASK, 0, port);
1719 break;
1720 case PHY_INTERFACE_MODE_RGMII_RXID:
1721 gswip_mii_mask_pcdu(priv, GSWIP_MII_PCDU_RXDLY_MASK, 0, port);
1722 break;
1723 case PHY_INTERFACE_MODE_RGMII_TXID:
1724 gswip_mii_mask_pcdu(priv, GSWIP_MII_PCDU_TXDLY_MASK, 0, port);
1725 break;
1726 default:
1727 break;
1728 }
1729 }
1730
gswip_phylink_mac_link_down(struct phylink_config * config,unsigned int mode,phy_interface_t interface)1731 static void gswip_phylink_mac_link_down(struct phylink_config *config,
1732 unsigned int mode,
1733 phy_interface_t interface)
1734 {
1735 struct dsa_port *dp = dsa_phylink_to_port(config);
1736 struct gswip_priv *priv = dp->ds->priv;
1737 int port = dp->index;
1738
1739 gswip_mii_mask_cfg(priv, GSWIP_MII_CFG_EN, 0, port);
1740
1741 if (!dsa_port_is_cpu(dp))
1742 gswip_port_set_link(priv, port, false);
1743 }
1744
gswip_phylink_mac_link_up(struct phylink_config * config,struct phy_device * phydev,unsigned int mode,phy_interface_t interface,int speed,int duplex,bool tx_pause,bool rx_pause)1745 static void gswip_phylink_mac_link_up(struct phylink_config *config,
1746 struct phy_device *phydev,
1747 unsigned int mode,
1748 phy_interface_t interface,
1749 int speed, int duplex,
1750 bool tx_pause, bool rx_pause)
1751 {
1752 struct dsa_port *dp = dsa_phylink_to_port(config);
1753 struct gswip_priv *priv = dp->ds->priv;
1754 int port = dp->index;
1755
1756 if (!dsa_port_is_cpu(dp)) {
1757 gswip_port_set_link(priv, port, true);
1758 gswip_port_set_speed(priv, port, speed, interface);
1759 gswip_port_set_duplex(priv, port, duplex);
1760 gswip_port_set_pause(priv, port, tx_pause, rx_pause);
1761 }
1762
1763 gswip_mii_mask_cfg(priv, 0, GSWIP_MII_CFG_EN, port);
1764 }
1765
gswip_get_strings(struct dsa_switch * ds,int port,u32 stringset,uint8_t * data)1766 static void gswip_get_strings(struct dsa_switch *ds, int port, u32 stringset,
1767 uint8_t *data)
1768 {
1769 int i;
1770
1771 if (stringset != ETH_SS_STATS)
1772 return;
1773
1774 for (i = 0; i < ARRAY_SIZE(gswip_rmon_cnt); i++)
1775 ethtool_puts(&data, gswip_rmon_cnt[i].name);
1776 }
1777
gswip_bcm_ram_entry_read(struct gswip_priv * priv,u32 table,u32 index)1778 static u32 gswip_bcm_ram_entry_read(struct gswip_priv *priv, u32 table,
1779 u32 index)
1780 {
1781 u32 result;
1782 int err;
1783
1784 gswip_switch_w(priv, index, GSWIP_BM_RAM_ADDR);
1785 gswip_switch_mask(priv, GSWIP_BM_RAM_CTRL_ADDR_MASK |
1786 GSWIP_BM_RAM_CTRL_OPMOD,
1787 table | GSWIP_BM_RAM_CTRL_BAS,
1788 GSWIP_BM_RAM_CTRL);
1789
1790 err = gswip_switch_r_timeout(priv, GSWIP_BM_RAM_CTRL,
1791 GSWIP_BM_RAM_CTRL_BAS);
1792 if (err) {
1793 dev_err(priv->dev, "timeout while reading table: %u, index: %u\n",
1794 table, index);
1795 return 0;
1796 }
1797
1798 result = gswip_switch_r(priv, GSWIP_BM_RAM_VAL(0));
1799 result |= gswip_switch_r(priv, GSWIP_BM_RAM_VAL(1)) << 16;
1800
1801 return result;
1802 }
1803
gswip_get_ethtool_stats(struct dsa_switch * ds,int port,uint64_t * data)1804 static void gswip_get_ethtool_stats(struct dsa_switch *ds, int port,
1805 uint64_t *data)
1806 {
1807 struct gswip_priv *priv = ds->priv;
1808 const struct gswip_rmon_cnt_desc *rmon_cnt;
1809 int i;
1810 u64 high;
1811
1812 for (i = 0; i < ARRAY_SIZE(gswip_rmon_cnt); i++) {
1813 rmon_cnt = &gswip_rmon_cnt[i];
1814
1815 data[i] = gswip_bcm_ram_entry_read(priv, port,
1816 rmon_cnt->offset);
1817 if (rmon_cnt->size == 2) {
1818 high = gswip_bcm_ram_entry_read(priv, port,
1819 rmon_cnt->offset + 1);
1820 data[i] |= high << 32;
1821 }
1822 }
1823 }
1824
gswip_get_sset_count(struct dsa_switch * ds,int port,int sset)1825 static int gswip_get_sset_count(struct dsa_switch *ds, int port, int sset)
1826 {
1827 if (sset != ETH_SS_STATS)
1828 return 0;
1829
1830 return ARRAY_SIZE(gswip_rmon_cnt);
1831 }
1832
1833 static const struct phylink_mac_ops gswip_phylink_mac_ops = {
1834 .mac_config = gswip_phylink_mac_config,
1835 .mac_link_down = gswip_phylink_mac_link_down,
1836 .mac_link_up = gswip_phylink_mac_link_up,
1837 };
1838
1839 static const struct dsa_switch_ops gswip_xrx200_switch_ops = {
1840 .get_tag_protocol = gswip_get_tag_protocol,
1841 .setup = gswip_setup,
1842 .port_setup = gswip_port_setup,
1843 .port_enable = gswip_port_enable,
1844 .port_disable = gswip_port_disable,
1845 .port_bridge_join = gswip_port_bridge_join,
1846 .port_bridge_leave = gswip_port_bridge_leave,
1847 .port_fast_age = gswip_port_fast_age,
1848 .port_vlan_filtering = gswip_port_vlan_filtering,
1849 .port_vlan_add = gswip_port_vlan_add,
1850 .port_vlan_del = gswip_port_vlan_del,
1851 .port_stp_state_set = gswip_port_stp_state_set,
1852 .port_fdb_add = gswip_port_fdb_add,
1853 .port_fdb_del = gswip_port_fdb_del,
1854 .port_fdb_dump = gswip_port_fdb_dump,
1855 .port_change_mtu = gswip_port_change_mtu,
1856 .port_max_mtu = gswip_port_max_mtu,
1857 .phylink_get_caps = gswip_xrx200_phylink_get_caps,
1858 .get_strings = gswip_get_strings,
1859 .get_ethtool_stats = gswip_get_ethtool_stats,
1860 .get_sset_count = gswip_get_sset_count,
1861 };
1862
1863 static const struct dsa_switch_ops gswip_xrx300_switch_ops = {
1864 .get_tag_protocol = gswip_get_tag_protocol,
1865 .setup = gswip_setup,
1866 .port_enable = gswip_port_enable,
1867 .port_disable = gswip_port_disable,
1868 .port_bridge_join = gswip_port_bridge_join,
1869 .port_bridge_leave = gswip_port_bridge_leave,
1870 .port_fast_age = gswip_port_fast_age,
1871 .port_vlan_filtering = gswip_port_vlan_filtering,
1872 .port_vlan_add = gswip_port_vlan_add,
1873 .port_vlan_del = gswip_port_vlan_del,
1874 .port_stp_state_set = gswip_port_stp_state_set,
1875 .port_fdb_add = gswip_port_fdb_add,
1876 .port_fdb_del = gswip_port_fdb_del,
1877 .port_fdb_dump = gswip_port_fdb_dump,
1878 .port_change_mtu = gswip_port_change_mtu,
1879 .port_max_mtu = gswip_port_max_mtu,
1880 .phylink_get_caps = gswip_xrx300_phylink_get_caps,
1881 .get_strings = gswip_get_strings,
1882 .get_ethtool_stats = gswip_get_ethtool_stats,
1883 .get_sset_count = gswip_get_sset_count,
1884 };
1885
1886 static const struct xway_gphy_match_data xrx200a1x_gphy_data = {
1887 .fe_firmware_name = "lantiq/xrx200_phy22f_a14.bin",
1888 .ge_firmware_name = "lantiq/xrx200_phy11g_a14.bin",
1889 };
1890
1891 static const struct xway_gphy_match_data xrx200a2x_gphy_data = {
1892 .fe_firmware_name = "lantiq/xrx200_phy22f_a22.bin",
1893 .ge_firmware_name = "lantiq/xrx200_phy11g_a22.bin",
1894 };
1895
1896 static const struct xway_gphy_match_data xrx300_gphy_data = {
1897 .fe_firmware_name = "lantiq/xrx300_phy22f_a21.bin",
1898 .ge_firmware_name = "lantiq/xrx300_phy11g_a21.bin",
1899 };
1900
1901 static const struct of_device_id xway_gphy_match[] __maybe_unused = {
1902 { .compatible = "lantiq,xrx200-gphy-fw", .data = NULL },
1903 { .compatible = "lantiq,xrx200a1x-gphy-fw", .data = &xrx200a1x_gphy_data },
1904 { .compatible = "lantiq,xrx200a2x-gphy-fw", .data = &xrx200a2x_gphy_data },
1905 { .compatible = "lantiq,xrx300-gphy-fw", .data = &xrx300_gphy_data },
1906 { .compatible = "lantiq,xrx330-gphy-fw", .data = &xrx300_gphy_data },
1907 {},
1908 };
1909
gswip_gphy_fw_load(struct gswip_priv * priv,struct gswip_gphy_fw * gphy_fw)1910 static int gswip_gphy_fw_load(struct gswip_priv *priv, struct gswip_gphy_fw *gphy_fw)
1911 {
1912 struct device *dev = priv->dev;
1913 const struct firmware *fw;
1914 void *fw_addr;
1915 dma_addr_t dma_addr;
1916 dma_addr_t dev_addr;
1917 size_t size;
1918 int ret;
1919
1920 ret = clk_prepare_enable(gphy_fw->clk_gate);
1921 if (ret)
1922 return ret;
1923
1924 reset_control_assert(gphy_fw->reset);
1925
1926 /* The vendor BSP uses a 200ms delay after asserting the reset line.
1927 * Without this some users are observing that the PHY is not coming up
1928 * on the MDIO bus.
1929 */
1930 msleep(200);
1931
1932 ret = request_firmware(&fw, gphy_fw->fw_name, dev);
1933 if (ret)
1934 return dev_err_probe(dev, ret, "failed to load firmware: %s\n",
1935 gphy_fw->fw_name);
1936
1937 /* GPHY cores need the firmware code in a persistent and contiguous
1938 * memory area with a 16 kB boundary aligned start address.
1939 */
1940 size = fw->size + XRX200_GPHY_FW_ALIGN;
1941
1942 fw_addr = dmam_alloc_coherent(dev, size, &dma_addr, GFP_KERNEL);
1943 if (fw_addr) {
1944 fw_addr = PTR_ALIGN(fw_addr, XRX200_GPHY_FW_ALIGN);
1945 dev_addr = ALIGN(dma_addr, XRX200_GPHY_FW_ALIGN);
1946 memcpy(fw_addr, fw->data, fw->size);
1947 } else {
1948 release_firmware(fw);
1949 return dev_err_probe(dev, -ENOMEM,
1950 "failed to alloc firmware memory\n");
1951 }
1952
1953 release_firmware(fw);
1954
1955 ret = regmap_write(priv->rcu_regmap, gphy_fw->fw_addr_offset, dev_addr);
1956 if (ret)
1957 return ret;
1958
1959 reset_control_deassert(gphy_fw->reset);
1960
1961 return ret;
1962 }
1963
gswip_gphy_fw_probe(struct gswip_priv * priv,struct gswip_gphy_fw * gphy_fw,struct device_node * gphy_fw_np,int i)1964 static int gswip_gphy_fw_probe(struct gswip_priv *priv,
1965 struct gswip_gphy_fw *gphy_fw,
1966 struct device_node *gphy_fw_np, int i)
1967 {
1968 struct device *dev = priv->dev;
1969 u32 gphy_mode;
1970 int ret;
1971 char gphyname[10];
1972
1973 snprintf(gphyname, sizeof(gphyname), "gphy%d", i);
1974
1975 gphy_fw->clk_gate = devm_clk_get(dev, gphyname);
1976 if (IS_ERR(gphy_fw->clk_gate)) {
1977 return dev_err_probe(dev, PTR_ERR(gphy_fw->clk_gate),
1978 "Failed to lookup gate clock\n");
1979 }
1980
1981 ret = of_property_read_u32(gphy_fw_np, "reg", &gphy_fw->fw_addr_offset);
1982 if (ret)
1983 return ret;
1984
1985 ret = of_property_read_u32(gphy_fw_np, "lantiq,gphy-mode", &gphy_mode);
1986 /* Default to GE mode */
1987 if (ret)
1988 gphy_mode = GPHY_MODE_GE;
1989
1990 switch (gphy_mode) {
1991 case GPHY_MODE_FE:
1992 gphy_fw->fw_name = priv->gphy_fw_name_cfg->fe_firmware_name;
1993 break;
1994 case GPHY_MODE_GE:
1995 gphy_fw->fw_name = priv->gphy_fw_name_cfg->ge_firmware_name;
1996 break;
1997 default:
1998 return dev_err_probe(dev, -EINVAL, "Unknown GPHY mode %d\n",
1999 gphy_mode);
2000 }
2001
2002 gphy_fw->reset = of_reset_control_array_get_exclusive(gphy_fw_np);
2003 if (IS_ERR(gphy_fw->reset))
2004 return dev_err_probe(dev, PTR_ERR(gphy_fw->reset),
2005 "Failed to lookup gphy reset\n");
2006
2007 return gswip_gphy_fw_load(priv, gphy_fw);
2008 }
2009
gswip_gphy_fw_remove(struct gswip_priv * priv,struct gswip_gphy_fw * gphy_fw)2010 static void gswip_gphy_fw_remove(struct gswip_priv *priv,
2011 struct gswip_gphy_fw *gphy_fw)
2012 {
2013 int ret;
2014
2015 /* check if the device was fully probed */
2016 if (!gphy_fw->fw_name)
2017 return;
2018
2019 ret = regmap_write(priv->rcu_regmap, gphy_fw->fw_addr_offset, 0);
2020 if (ret)
2021 dev_err(priv->dev, "can not reset GPHY FW pointer\n");
2022
2023 clk_disable_unprepare(gphy_fw->clk_gate);
2024
2025 reset_control_put(gphy_fw->reset);
2026 }
2027
gswip_gphy_fw_list(struct gswip_priv * priv,struct device_node * gphy_fw_list_np,u32 version)2028 static int gswip_gphy_fw_list(struct gswip_priv *priv,
2029 struct device_node *gphy_fw_list_np, u32 version)
2030 {
2031 struct device *dev = priv->dev;
2032 struct device_node *gphy_fw_np;
2033 const struct of_device_id *match;
2034 int err;
2035 int i = 0;
2036
2037 /* The VRX200 rev 1.1 uses the GSWIP 2.0 and needs the older
2038 * GPHY firmware. The VRX200 rev 1.2 uses the GSWIP 2.1 and also
2039 * needs a different GPHY firmware.
2040 */
2041 if (of_device_is_compatible(gphy_fw_list_np, "lantiq,xrx200-gphy-fw")) {
2042 switch (version) {
2043 case GSWIP_VERSION_2_0:
2044 priv->gphy_fw_name_cfg = &xrx200a1x_gphy_data;
2045 break;
2046 case GSWIP_VERSION_2_1:
2047 priv->gphy_fw_name_cfg = &xrx200a2x_gphy_data;
2048 break;
2049 default:
2050 return dev_err_probe(dev, -ENOENT,
2051 "unknown GSWIP version: 0x%x\n",
2052 version);
2053 }
2054 }
2055
2056 match = of_match_node(xway_gphy_match, gphy_fw_list_np);
2057 if (match && match->data)
2058 priv->gphy_fw_name_cfg = match->data;
2059
2060 if (!priv->gphy_fw_name_cfg)
2061 return dev_err_probe(dev, -ENOENT,
2062 "GPHY compatible type not supported\n");
2063
2064 priv->num_gphy_fw = of_get_available_child_count(gphy_fw_list_np);
2065 if (!priv->num_gphy_fw)
2066 return -ENOENT;
2067
2068 priv->rcu_regmap = syscon_regmap_lookup_by_phandle(gphy_fw_list_np,
2069 "lantiq,rcu");
2070 if (IS_ERR(priv->rcu_regmap))
2071 return PTR_ERR(priv->rcu_regmap);
2072
2073 priv->gphy_fw = devm_kmalloc_array(dev, priv->num_gphy_fw,
2074 sizeof(*priv->gphy_fw),
2075 GFP_KERNEL | __GFP_ZERO);
2076 if (!priv->gphy_fw)
2077 return -ENOMEM;
2078
2079 for_each_available_child_of_node(gphy_fw_list_np, gphy_fw_np) {
2080 err = gswip_gphy_fw_probe(priv, &priv->gphy_fw[i],
2081 gphy_fw_np, i);
2082 if (err) {
2083 of_node_put(gphy_fw_np);
2084 goto remove_gphy;
2085 }
2086 i++;
2087 }
2088
2089 /* The standalone PHY11G requires 300ms to be fully
2090 * initialized and ready for any MDIO communication after being
2091 * taken out of reset. For the SoC-internal GPHY variant there
2092 * is no (known) documentation for the minimum time after a
2093 * reset. Use the same value as for the standalone variant as
2094 * some users have reported internal PHYs not being detected
2095 * without any delay.
2096 */
2097 msleep(300);
2098
2099 return 0;
2100
2101 remove_gphy:
2102 for (i = 0; i < priv->num_gphy_fw; i++)
2103 gswip_gphy_fw_remove(priv, &priv->gphy_fw[i]);
2104 return err;
2105 }
2106
gswip_probe(struct platform_device * pdev)2107 static int gswip_probe(struct platform_device *pdev)
2108 {
2109 struct device_node *np, *gphy_fw_np;
2110 struct device *dev = &pdev->dev;
2111 struct gswip_priv *priv;
2112 int err;
2113 int i;
2114 u32 version;
2115
2116 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
2117 if (!priv)
2118 return -ENOMEM;
2119
2120 priv->gswip = devm_platform_ioremap_resource(pdev, 0);
2121 if (IS_ERR(priv->gswip))
2122 return PTR_ERR(priv->gswip);
2123
2124 priv->mdio = devm_platform_ioremap_resource(pdev, 1);
2125 if (IS_ERR(priv->mdio))
2126 return PTR_ERR(priv->mdio);
2127
2128 priv->mii = devm_platform_ioremap_resource(pdev, 2);
2129 if (IS_ERR(priv->mii))
2130 return PTR_ERR(priv->mii);
2131
2132 priv->hw_info = of_device_get_match_data(dev);
2133 if (!priv->hw_info)
2134 return -EINVAL;
2135
2136 priv->ds = devm_kzalloc(dev, sizeof(*priv->ds), GFP_KERNEL);
2137 if (!priv->ds)
2138 return -ENOMEM;
2139
2140 priv->ds->dev = dev;
2141 priv->ds->num_ports = priv->hw_info->max_ports;
2142 priv->ds->priv = priv;
2143 priv->ds->ops = priv->hw_info->ops;
2144 priv->ds->phylink_mac_ops = &gswip_phylink_mac_ops;
2145 priv->dev = dev;
2146 mutex_init(&priv->pce_table_lock);
2147 version = gswip_switch_r(priv, GSWIP_VERSION);
2148
2149 np = dev->of_node;
2150 switch (version) {
2151 case GSWIP_VERSION_2_0:
2152 case GSWIP_VERSION_2_1:
2153 if (!of_device_is_compatible(np, "lantiq,xrx200-gswip"))
2154 return -EINVAL;
2155 break;
2156 case GSWIP_VERSION_2_2:
2157 case GSWIP_VERSION_2_2_ETC:
2158 if (!of_device_is_compatible(np, "lantiq,xrx300-gswip") &&
2159 !of_device_is_compatible(np, "lantiq,xrx330-gswip"))
2160 return -EINVAL;
2161 break;
2162 default:
2163 return dev_err_probe(dev, -ENOENT,
2164 "unknown GSWIP version: 0x%x\n", version);
2165 }
2166
2167 /* bring up the mdio bus */
2168 gphy_fw_np = of_get_compatible_child(dev->of_node, "lantiq,gphy-fw");
2169 if (gphy_fw_np) {
2170 err = gswip_gphy_fw_list(priv, gphy_fw_np, version);
2171 of_node_put(gphy_fw_np);
2172 if (err)
2173 return dev_err_probe(dev, err,
2174 "gphy fw probe failed\n");
2175 }
2176
2177 /* bring up the mdio bus */
2178 err = gswip_mdio(priv);
2179 if (err) {
2180 dev_err_probe(dev, err, "mdio probe failed\n");
2181 goto gphy_fw_remove;
2182 }
2183
2184 err = dsa_register_switch(priv->ds);
2185 if (err) {
2186 dev_err_probe(dev, err, "dsa switch registration failed\n");
2187 goto gphy_fw_remove;
2188 }
2189 if (!dsa_is_cpu_port(priv->ds, priv->hw_info->cpu_port)) {
2190 err = dev_err_probe(dev, -EINVAL,
2191 "wrong CPU port defined, HW only supports port: %i\n",
2192 priv->hw_info->cpu_port);
2193 goto disable_switch;
2194 }
2195
2196 platform_set_drvdata(pdev, priv);
2197
2198 dev_info(dev, "probed GSWIP version %lx mod %lx\n",
2199 (version & GSWIP_VERSION_REV_MASK) >> GSWIP_VERSION_REV_SHIFT,
2200 (version & GSWIP_VERSION_MOD_MASK) >> GSWIP_VERSION_MOD_SHIFT);
2201 return 0;
2202
2203 disable_switch:
2204 gswip_mdio_mask(priv, GSWIP_MDIO_GLOB_ENABLE, 0, GSWIP_MDIO_GLOB);
2205 dsa_unregister_switch(priv->ds);
2206 gphy_fw_remove:
2207 for (i = 0; i < priv->num_gphy_fw; i++)
2208 gswip_gphy_fw_remove(priv, &priv->gphy_fw[i]);
2209 return err;
2210 }
2211
gswip_remove(struct platform_device * pdev)2212 static void gswip_remove(struct platform_device *pdev)
2213 {
2214 struct gswip_priv *priv = platform_get_drvdata(pdev);
2215 int i;
2216
2217 if (!priv)
2218 return;
2219
2220 /* disable the switch */
2221 gswip_mdio_mask(priv, GSWIP_MDIO_GLOB_ENABLE, 0, GSWIP_MDIO_GLOB);
2222
2223 dsa_unregister_switch(priv->ds);
2224
2225 for (i = 0; i < priv->num_gphy_fw; i++)
2226 gswip_gphy_fw_remove(priv, &priv->gphy_fw[i]);
2227 }
2228
gswip_shutdown(struct platform_device * pdev)2229 static void gswip_shutdown(struct platform_device *pdev)
2230 {
2231 struct gswip_priv *priv = platform_get_drvdata(pdev);
2232
2233 if (!priv)
2234 return;
2235
2236 dsa_switch_shutdown(priv->ds);
2237
2238 platform_set_drvdata(pdev, NULL);
2239 }
2240
2241 static const struct gswip_hw_info gswip_xrx200 = {
2242 .max_ports = 7,
2243 .cpu_port = 6,
2244 .ops = &gswip_xrx200_switch_ops,
2245 };
2246
2247 static const struct gswip_hw_info gswip_xrx300 = {
2248 .max_ports = 7,
2249 .cpu_port = 6,
2250 .ops = &gswip_xrx300_switch_ops,
2251 };
2252
2253 static const struct of_device_id gswip_of_match[] = {
2254 { .compatible = "lantiq,xrx200-gswip", .data = &gswip_xrx200 },
2255 { .compatible = "lantiq,xrx300-gswip", .data = &gswip_xrx300 },
2256 { .compatible = "lantiq,xrx330-gswip", .data = &gswip_xrx300 },
2257 {},
2258 };
2259 MODULE_DEVICE_TABLE(of, gswip_of_match);
2260
2261 static struct platform_driver gswip_driver = {
2262 .probe = gswip_probe,
2263 .remove_new = gswip_remove,
2264 .shutdown = gswip_shutdown,
2265 .driver = {
2266 .name = "gswip",
2267 .of_match_table = gswip_of_match,
2268 },
2269 };
2270
2271 module_platform_driver(gswip_driver);
2272
2273 MODULE_FIRMWARE("lantiq/xrx300_phy11g_a21.bin");
2274 MODULE_FIRMWARE("lantiq/xrx300_phy22f_a21.bin");
2275 MODULE_FIRMWARE("lantiq/xrx200_phy11g_a14.bin");
2276 MODULE_FIRMWARE("lantiq/xrx200_phy11g_a22.bin");
2277 MODULE_FIRMWARE("lantiq/xrx200_phy22f_a14.bin");
2278 MODULE_FIRMWARE("lantiq/xrx200_phy22f_a22.bin");
2279 MODULE_AUTHOR("Hauke Mehrtens <hauke@hauke-m.de>");
2280 MODULE_DESCRIPTION("Lantiq / Intel GSWIP driver");
2281 MODULE_LICENSE("GPL v2");
2282