1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * Marvell 88e6xxx Ethernet switch single-chip support
4 *
5 * Copyright (c) 2008 Marvell Semiconductor
6 *
7 * Copyright (c) 2016 Andrew Lunn <andrew@lunn.ch>
8 *
9 * Copyright (c) 2016-2017 Savoir-faire Linux Inc.
10 * Vivien Didelot <vivien.didelot@savoirfairelinux.com>
11 */
12
13 #include <linux/bitfield.h>
14 #include <linux/delay.h>
15 #include <linux/dsa/mv88e6xxx.h>
16 #include <linux/etherdevice.h>
17 #include <linux/ethtool.h>
18 #include <linux/if_bridge.h>
19 #include <linux/interrupt.h>
20 #include <linux/irq.h>
21 #include <linux/irqdomain.h>
22 #include <linux/jiffies.h>
23 #include <linux/list.h>
24 #include <linux/mdio.h>
25 #include <linux/module.h>
26 #include <linux/of.h>
27 #include <linux/of_irq.h>
28 #include <linux/of_mdio.h>
29 #include <linux/platform_data/mv88e6xxx.h>
30 #include <linux/netdevice.h>
31 #include <linux/gpio/consumer.h>
32 #include <linux/phylink.h>
33 #include <net/dsa.h>
34
35 #include "chip.h"
36 #include "devlink.h"
37 #include "global1.h"
38 #include "global2.h"
39 #include "hwtstamp.h"
40 #include "phy.h"
41 #include "port.h"
42 #include "ptp.h"
43 #include "serdes.h"
44 #include "smi.h"
45
assert_reg_lock(struct mv88e6xxx_chip * chip)46 static void assert_reg_lock(struct mv88e6xxx_chip *chip)
47 {
48 if (unlikely(!mutex_is_locked(&chip->reg_lock))) {
49 dev_err(chip->dev, "Switch registers lock not held!\n");
50 dump_stack();
51 }
52 }
53
mv88e6xxx_read(struct mv88e6xxx_chip * chip,int addr,int reg,u16 * val)54 int mv88e6xxx_read(struct mv88e6xxx_chip *chip, int addr, int reg, u16 *val)
55 {
56 int err;
57
58 assert_reg_lock(chip);
59
60 err = mv88e6xxx_smi_read(chip, addr, reg, val);
61 if (err)
62 return err;
63
64 dev_dbg(chip->dev, "<- addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
65 addr, reg, *val);
66
67 return 0;
68 }
69
mv88e6xxx_write(struct mv88e6xxx_chip * chip,int addr,int reg,u16 val)70 int mv88e6xxx_write(struct mv88e6xxx_chip *chip, int addr, int reg, u16 val)
71 {
72 int err;
73
74 assert_reg_lock(chip);
75
76 err = mv88e6xxx_smi_write(chip, addr, reg, val);
77 if (err)
78 return err;
79
80 dev_dbg(chip->dev, "-> addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
81 addr, reg, val);
82
83 return 0;
84 }
85
mv88e6xxx_wait_mask(struct mv88e6xxx_chip * chip,int addr,int reg,u16 mask,u16 val)86 int mv88e6xxx_wait_mask(struct mv88e6xxx_chip *chip, int addr, int reg,
87 u16 mask, u16 val)
88 {
89 const unsigned long timeout = jiffies + msecs_to_jiffies(50);
90 u16 data;
91 int err;
92 int i;
93
94 /* There's no bus specific operation to wait for a mask. Even
95 * if the initial poll takes longer than 50ms, always do at
96 * least one more attempt.
97 */
98 for (i = 0; time_before(jiffies, timeout) || (i < 2); i++) {
99 err = mv88e6xxx_read(chip, addr, reg, &data);
100 if (err)
101 return err;
102
103 if ((data & mask) == val)
104 return 0;
105
106 if (i < 2)
107 cpu_relax();
108 else
109 usleep_range(1000, 2000);
110 }
111
112 err = mv88e6xxx_read(chip, addr, reg, &data);
113 if (err)
114 return err;
115
116 if ((data & mask) == val)
117 return 0;
118
119 dev_err(chip->dev, "Timeout while waiting for switch\n");
120 return -ETIMEDOUT;
121 }
122
mv88e6xxx_wait_bit(struct mv88e6xxx_chip * chip,int addr,int reg,int bit,int val)123 int mv88e6xxx_wait_bit(struct mv88e6xxx_chip *chip, int addr, int reg,
124 int bit, int val)
125 {
126 return mv88e6xxx_wait_mask(chip, addr, reg, BIT(bit),
127 val ? BIT(bit) : 0x0000);
128 }
129
mv88e6xxx_default_mdio_bus(struct mv88e6xxx_chip * chip)130 struct mii_bus *mv88e6xxx_default_mdio_bus(struct mv88e6xxx_chip *chip)
131 {
132 struct mv88e6xxx_mdio_bus *mdio_bus;
133
134 mdio_bus = list_first_entry_or_null(&chip->mdios,
135 struct mv88e6xxx_mdio_bus, list);
136 if (!mdio_bus)
137 return NULL;
138
139 return mdio_bus->bus;
140 }
141
mv88e6xxx_g1_irq_mask(struct irq_data * d)142 static void mv88e6xxx_g1_irq_mask(struct irq_data *d)
143 {
144 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
145 unsigned int n = d->hwirq;
146
147 chip->g1_irq.masked |= (1 << n);
148 }
149
mv88e6xxx_g1_irq_unmask(struct irq_data * d)150 static void mv88e6xxx_g1_irq_unmask(struct irq_data *d)
151 {
152 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
153 unsigned int n = d->hwirq;
154
155 chip->g1_irq.masked &= ~(1 << n);
156 }
157
mv88e6xxx_g1_irq_thread_work(struct mv88e6xxx_chip * chip)158 static irqreturn_t mv88e6xxx_g1_irq_thread_work(struct mv88e6xxx_chip *chip)
159 {
160 unsigned int nhandled = 0;
161 unsigned int sub_irq;
162 unsigned int n;
163 u16 reg;
164 u16 ctl1;
165 int err;
166
167 mv88e6xxx_reg_lock(chip);
168 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, ®);
169 mv88e6xxx_reg_unlock(chip);
170
171 if (err)
172 goto out;
173
174 do {
175 for (n = 0; n < chip->g1_irq.nirqs; ++n) {
176 if (reg & (1 << n)) {
177 sub_irq = irq_find_mapping(chip->g1_irq.domain,
178 n);
179 handle_nested_irq(sub_irq);
180 ++nhandled;
181 }
182 }
183
184 mv88e6xxx_reg_lock(chip);
185 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &ctl1);
186 if (err)
187 goto unlock;
188 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, ®);
189 unlock:
190 mv88e6xxx_reg_unlock(chip);
191 if (err)
192 goto out;
193 ctl1 &= GENMASK(chip->g1_irq.nirqs, 0);
194 } while (reg & ctl1);
195
196 out:
197 return (nhandled > 0 ? IRQ_HANDLED : IRQ_NONE);
198 }
199
mv88e6xxx_g1_irq_thread_fn(int irq,void * dev_id)200 static irqreturn_t mv88e6xxx_g1_irq_thread_fn(int irq, void *dev_id)
201 {
202 struct mv88e6xxx_chip *chip = dev_id;
203
204 return mv88e6xxx_g1_irq_thread_work(chip);
205 }
206
mv88e6xxx_g1_irq_bus_lock(struct irq_data * d)207 static void mv88e6xxx_g1_irq_bus_lock(struct irq_data *d)
208 {
209 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
210
211 mv88e6xxx_reg_lock(chip);
212 }
213
mv88e6xxx_g1_irq_bus_sync_unlock(struct irq_data * d)214 static void mv88e6xxx_g1_irq_bus_sync_unlock(struct irq_data *d)
215 {
216 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
217 u16 mask = GENMASK(chip->g1_irq.nirqs, 0);
218 u16 reg;
219 int err;
220
221 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, ®);
222 if (err)
223 goto out;
224
225 reg &= ~mask;
226 reg |= (~chip->g1_irq.masked & mask);
227
228 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, reg);
229 if (err)
230 goto out;
231
232 out:
233 mv88e6xxx_reg_unlock(chip);
234 }
235
236 static const struct irq_chip mv88e6xxx_g1_irq_chip = {
237 .name = "mv88e6xxx-g1",
238 .irq_mask = mv88e6xxx_g1_irq_mask,
239 .irq_unmask = mv88e6xxx_g1_irq_unmask,
240 .irq_bus_lock = mv88e6xxx_g1_irq_bus_lock,
241 .irq_bus_sync_unlock = mv88e6xxx_g1_irq_bus_sync_unlock,
242 };
243
mv88e6xxx_g1_irq_domain_map(struct irq_domain * d,unsigned int irq,irq_hw_number_t hwirq)244 static int mv88e6xxx_g1_irq_domain_map(struct irq_domain *d,
245 unsigned int irq,
246 irq_hw_number_t hwirq)
247 {
248 struct mv88e6xxx_chip *chip = d->host_data;
249
250 irq_set_chip_data(irq, d->host_data);
251 irq_set_chip_and_handler(irq, &chip->g1_irq.chip, handle_level_irq);
252 irq_set_noprobe(irq);
253
254 return 0;
255 }
256
257 static const struct irq_domain_ops mv88e6xxx_g1_irq_domain_ops = {
258 .map = mv88e6xxx_g1_irq_domain_map,
259 .xlate = irq_domain_xlate_twocell,
260 };
261
262 /* To be called with reg_lock held */
mv88e6xxx_g1_irq_free_common(struct mv88e6xxx_chip * chip)263 static void mv88e6xxx_g1_irq_free_common(struct mv88e6xxx_chip *chip)
264 {
265 int irq, virq;
266 u16 mask;
267
268 mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &mask);
269 mask &= ~GENMASK(chip->g1_irq.nirqs, 0);
270 mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask);
271
272 for (irq = 0; irq < chip->g1_irq.nirqs; irq++) {
273 virq = irq_find_mapping(chip->g1_irq.domain, irq);
274 irq_dispose_mapping(virq);
275 }
276
277 irq_domain_remove(chip->g1_irq.domain);
278 }
279
mv88e6xxx_g1_irq_free(struct mv88e6xxx_chip * chip)280 static void mv88e6xxx_g1_irq_free(struct mv88e6xxx_chip *chip)
281 {
282 /*
283 * free_irq must be called without reg_lock taken because the irq
284 * handler takes this lock, too.
285 */
286 free_irq(chip->irq, chip);
287
288 mv88e6xxx_reg_lock(chip);
289 mv88e6xxx_g1_irq_free_common(chip);
290 mv88e6xxx_reg_unlock(chip);
291 }
292
mv88e6xxx_g1_irq_setup_common(struct mv88e6xxx_chip * chip)293 static int mv88e6xxx_g1_irq_setup_common(struct mv88e6xxx_chip *chip)
294 {
295 int err, irq, virq;
296 u16 reg, mask;
297
298 chip->g1_irq.nirqs = chip->info->g1_irqs;
299 chip->g1_irq.domain = irq_domain_add_simple(
300 NULL, chip->g1_irq.nirqs, 0,
301 &mv88e6xxx_g1_irq_domain_ops, chip);
302 if (!chip->g1_irq.domain)
303 return -ENOMEM;
304
305 for (irq = 0; irq < chip->g1_irq.nirqs; irq++)
306 irq_create_mapping(chip->g1_irq.domain, irq);
307
308 chip->g1_irq.chip = mv88e6xxx_g1_irq_chip;
309 chip->g1_irq.masked = ~0;
310
311 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &mask);
312 if (err)
313 goto out_mapping;
314
315 mask &= ~GENMASK(chip->g1_irq.nirqs, 0);
316
317 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask);
318 if (err)
319 goto out_disable;
320
321 /* Reading the interrupt status clears (most of) them */
322 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, ®);
323 if (err)
324 goto out_disable;
325
326 return 0;
327
328 out_disable:
329 mask &= ~GENMASK(chip->g1_irq.nirqs, 0);
330 mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask);
331
332 out_mapping:
333 for (irq = 0; irq < 16; irq++) {
334 virq = irq_find_mapping(chip->g1_irq.domain, irq);
335 irq_dispose_mapping(virq);
336 }
337
338 irq_domain_remove(chip->g1_irq.domain);
339
340 return err;
341 }
342
mv88e6xxx_g1_irq_setup(struct mv88e6xxx_chip * chip)343 static int mv88e6xxx_g1_irq_setup(struct mv88e6xxx_chip *chip)
344 {
345 static struct lock_class_key lock_key;
346 static struct lock_class_key request_key;
347 int err;
348
349 err = mv88e6xxx_g1_irq_setup_common(chip);
350 if (err)
351 return err;
352
353 /* These lock classes tells lockdep that global 1 irqs are in
354 * a different category than their parent GPIO, so it won't
355 * report false recursion.
356 */
357 irq_set_lockdep_class(chip->irq, &lock_key, &request_key);
358
359 snprintf(chip->irq_name, sizeof(chip->irq_name),
360 "mv88e6xxx-%s", dev_name(chip->dev));
361
362 mv88e6xxx_reg_unlock(chip);
363 err = request_threaded_irq(chip->irq, NULL,
364 mv88e6xxx_g1_irq_thread_fn,
365 IRQF_ONESHOT | IRQF_SHARED,
366 chip->irq_name, chip);
367 mv88e6xxx_reg_lock(chip);
368 if (err)
369 mv88e6xxx_g1_irq_free_common(chip);
370
371 return err;
372 }
373
mv88e6xxx_irq_poll(struct kthread_work * work)374 static void mv88e6xxx_irq_poll(struct kthread_work *work)
375 {
376 struct mv88e6xxx_chip *chip = container_of(work,
377 struct mv88e6xxx_chip,
378 irq_poll_work.work);
379 mv88e6xxx_g1_irq_thread_work(chip);
380
381 kthread_queue_delayed_work(chip->kworker, &chip->irq_poll_work,
382 msecs_to_jiffies(100));
383 }
384
mv88e6xxx_irq_poll_setup(struct mv88e6xxx_chip * chip)385 static int mv88e6xxx_irq_poll_setup(struct mv88e6xxx_chip *chip)
386 {
387 int err;
388
389 err = mv88e6xxx_g1_irq_setup_common(chip);
390 if (err)
391 return err;
392
393 kthread_init_delayed_work(&chip->irq_poll_work,
394 mv88e6xxx_irq_poll);
395
396 chip->kworker = kthread_create_worker(0, "%s", dev_name(chip->dev));
397 if (IS_ERR(chip->kworker))
398 return PTR_ERR(chip->kworker);
399
400 kthread_queue_delayed_work(chip->kworker, &chip->irq_poll_work,
401 msecs_to_jiffies(100));
402
403 return 0;
404 }
405
mv88e6xxx_irq_poll_free(struct mv88e6xxx_chip * chip)406 static void mv88e6xxx_irq_poll_free(struct mv88e6xxx_chip *chip)
407 {
408 kthread_cancel_delayed_work_sync(&chip->irq_poll_work);
409 kthread_destroy_worker(chip->kworker);
410
411 mv88e6xxx_reg_lock(chip);
412 mv88e6xxx_g1_irq_free_common(chip);
413 mv88e6xxx_reg_unlock(chip);
414 }
415
mv88e6xxx_port_config_interface(struct mv88e6xxx_chip * chip,int port,phy_interface_t interface)416 static int mv88e6xxx_port_config_interface(struct mv88e6xxx_chip *chip,
417 int port, phy_interface_t interface)
418 {
419 int err;
420
421 if (chip->info->ops->port_set_rgmii_delay) {
422 err = chip->info->ops->port_set_rgmii_delay(chip, port,
423 interface);
424 if (err && err != -EOPNOTSUPP)
425 return err;
426 }
427
428 if (chip->info->ops->port_set_cmode) {
429 err = chip->info->ops->port_set_cmode(chip, port,
430 interface);
431 if (err && err != -EOPNOTSUPP)
432 return err;
433 }
434
435 return 0;
436 }
437
mv88e6xxx_port_setup_mac(struct mv88e6xxx_chip * chip,int port,int link,int speed,int duplex,int pause,phy_interface_t mode)438 static int mv88e6xxx_port_setup_mac(struct mv88e6xxx_chip *chip, int port,
439 int link, int speed, int duplex, int pause,
440 phy_interface_t mode)
441 {
442 int err;
443
444 if (!chip->info->ops->port_set_link)
445 return 0;
446
447 /* Port's MAC control must not be changed unless the link is down */
448 err = chip->info->ops->port_set_link(chip, port, LINK_FORCED_DOWN);
449 if (err)
450 return err;
451
452 if (chip->info->ops->port_set_speed_duplex) {
453 err = chip->info->ops->port_set_speed_duplex(chip, port,
454 speed, duplex);
455 if (err && err != -EOPNOTSUPP)
456 goto restore_link;
457 }
458
459 if (chip->info->ops->port_set_pause) {
460 err = chip->info->ops->port_set_pause(chip, port, pause);
461 if (err)
462 goto restore_link;
463 }
464
465 err = mv88e6xxx_port_config_interface(chip, port, mode);
466 restore_link:
467 if (chip->info->ops->port_set_link(chip, port, link))
468 dev_err(chip->dev, "p%d: failed to restore MAC's link\n", port);
469
470 return err;
471 }
472
mv88e6xxx_phy_is_internal(struct mv88e6xxx_chip * chip,int port)473 static int mv88e6xxx_phy_is_internal(struct mv88e6xxx_chip *chip, int port)
474 {
475 return port >= chip->info->internal_phys_offset &&
476 port < chip->info->num_internal_phys +
477 chip->info->internal_phys_offset;
478 }
479
mv88e6xxx_port_ppu_updates(struct mv88e6xxx_chip * chip,int port)480 static int mv88e6xxx_port_ppu_updates(struct mv88e6xxx_chip *chip, int port)
481 {
482 u16 reg;
483 int err;
484
485 /* The 88e6250 family does not have the PHY detect bit. Instead,
486 * report whether the port is internal.
487 */
488 if (chip->info->family == MV88E6XXX_FAMILY_6250)
489 return mv88e6xxx_phy_is_internal(chip, port);
490
491 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_STS, ®);
492 if (err) {
493 dev_err(chip->dev,
494 "p%d: %s: failed to read port status\n",
495 port, __func__);
496 return err;
497 }
498
499 return !!(reg & MV88E6XXX_PORT_STS_PHY_DETECT);
500 }
501
502 static const u8 mv88e6185_phy_interface_modes[] = {
503 [MV88E6185_PORT_STS_CMODE_GMII_FD] = PHY_INTERFACE_MODE_GMII,
504 [MV88E6185_PORT_STS_CMODE_MII_100_FD_PS] = PHY_INTERFACE_MODE_MII,
505 [MV88E6185_PORT_STS_CMODE_MII_100] = PHY_INTERFACE_MODE_MII,
506 [MV88E6185_PORT_STS_CMODE_MII_10] = PHY_INTERFACE_MODE_MII,
507 [MV88E6185_PORT_STS_CMODE_SERDES] = PHY_INTERFACE_MODE_1000BASEX,
508 [MV88E6185_PORT_STS_CMODE_1000BASE_X] = PHY_INTERFACE_MODE_1000BASEX,
509 [MV88E6185_PORT_STS_CMODE_PHY] = PHY_INTERFACE_MODE_SGMII,
510 };
511
mv88e6095_phylink_get_caps(struct mv88e6xxx_chip * chip,int port,struct phylink_config * config)512 static void mv88e6095_phylink_get_caps(struct mv88e6xxx_chip *chip, int port,
513 struct phylink_config *config)
514 {
515 u8 cmode = chip->ports[port].cmode;
516
517 config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100;
518
519 if (mv88e6xxx_phy_is_internal(chip, port)) {
520 __set_bit(PHY_INTERFACE_MODE_MII, config->supported_interfaces);
521 } else {
522 if (cmode < ARRAY_SIZE(mv88e6185_phy_interface_modes) &&
523 mv88e6185_phy_interface_modes[cmode])
524 __set_bit(mv88e6185_phy_interface_modes[cmode],
525 config->supported_interfaces);
526
527 config->mac_capabilities |= MAC_1000FD;
528 }
529 }
530
mv88e6185_phylink_get_caps(struct mv88e6xxx_chip * chip,int port,struct phylink_config * config)531 static void mv88e6185_phylink_get_caps(struct mv88e6xxx_chip *chip, int port,
532 struct phylink_config *config)
533 {
534 u8 cmode = chip->ports[port].cmode;
535
536 if (cmode < ARRAY_SIZE(mv88e6185_phy_interface_modes) &&
537 mv88e6185_phy_interface_modes[cmode])
538 __set_bit(mv88e6185_phy_interface_modes[cmode],
539 config->supported_interfaces);
540
541 config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100 |
542 MAC_1000FD;
543 }
544
545 static const u8 mv88e6xxx_phy_interface_modes[] = {
546 [MV88E6XXX_PORT_STS_CMODE_MII_PHY] = PHY_INTERFACE_MODE_REVMII,
547 [MV88E6XXX_PORT_STS_CMODE_MII] = PHY_INTERFACE_MODE_MII,
548 [MV88E6XXX_PORT_STS_CMODE_GMII] = PHY_INTERFACE_MODE_GMII,
549 [MV88E6XXX_PORT_STS_CMODE_RMII_PHY] = PHY_INTERFACE_MODE_REVRMII,
550 [MV88E6XXX_PORT_STS_CMODE_RMII] = PHY_INTERFACE_MODE_RMII,
551 [MV88E6XXX_PORT_STS_CMODE_100BASEX] = PHY_INTERFACE_MODE_100BASEX,
552 [MV88E6XXX_PORT_STS_CMODE_1000BASEX] = PHY_INTERFACE_MODE_1000BASEX,
553 [MV88E6XXX_PORT_STS_CMODE_SGMII] = PHY_INTERFACE_MODE_SGMII,
554 /* higher interface modes are not needed here, since ports supporting
555 * them are writable, and so the supported interfaces are filled in the
556 * corresponding .phylink_set_interfaces() implementation below
557 */
558 };
559
mv88e6xxx_translate_cmode(u8 cmode,unsigned long * supported)560 static void mv88e6xxx_translate_cmode(u8 cmode, unsigned long *supported)
561 {
562 if (cmode < ARRAY_SIZE(mv88e6xxx_phy_interface_modes) &&
563 mv88e6xxx_phy_interface_modes[cmode])
564 __set_bit(mv88e6xxx_phy_interface_modes[cmode], supported);
565 else if (cmode == MV88E6XXX_PORT_STS_CMODE_RGMII)
566 phy_interface_set_rgmii(supported);
567 }
568
569 static void
mv88e6250_setup_supported_interfaces(struct mv88e6xxx_chip * chip,int port,struct phylink_config * config)570 mv88e6250_setup_supported_interfaces(struct mv88e6xxx_chip *chip, int port,
571 struct phylink_config *config)
572 {
573 unsigned long *supported = config->supported_interfaces;
574 int err;
575 u16 reg;
576
577 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_STS, ®);
578 if (err) {
579 dev_err(chip->dev, "p%d: failed to read port status\n", port);
580 return;
581 }
582
583 switch (reg & MV88E6250_PORT_STS_PORTMODE_MASK) {
584 case MV88E6250_PORT_STS_PORTMODE_MII_10_HALF_PHY:
585 case MV88E6250_PORT_STS_PORTMODE_MII_100_HALF_PHY:
586 case MV88E6250_PORT_STS_PORTMODE_MII_10_FULL_PHY:
587 case MV88E6250_PORT_STS_PORTMODE_MII_100_FULL_PHY:
588 __set_bit(PHY_INTERFACE_MODE_REVMII, supported);
589 break;
590
591 case MV88E6250_PORT_STS_PORTMODE_MII_HALF:
592 case MV88E6250_PORT_STS_PORTMODE_MII_FULL:
593 __set_bit(PHY_INTERFACE_MODE_MII, supported);
594 break;
595
596 case MV88E6250_PORT_STS_PORTMODE_MII_DUAL_100_RMII_FULL_PHY:
597 case MV88E6250_PORT_STS_PORTMODE_MII_200_RMII_FULL_PHY:
598 case MV88E6250_PORT_STS_PORTMODE_MII_10_100_RMII_HALF_PHY:
599 case MV88E6250_PORT_STS_PORTMODE_MII_10_100_RMII_FULL_PHY:
600 __set_bit(PHY_INTERFACE_MODE_REVRMII, supported);
601 break;
602
603 case MV88E6250_PORT_STS_PORTMODE_MII_DUAL_100_RMII_FULL:
604 case MV88E6250_PORT_STS_PORTMODE_MII_10_100_RMII_FULL:
605 __set_bit(PHY_INTERFACE_MODE_RMII, supported);
606 break;
607
608 case MV88E6250_PORT_STS_PORTMODE_MII_100_RGMII:
609 __set_bit(PHY_INTERFACE_MODE_RGMII, supported);
610 break;
611
612 default:
613 dev_err(chip->dev,
614 "p%d: invalid port mode in status register: %04x\n",
615 port, reg);
616 }
617 }
618
mv88e6250_phylink_get_caps(struct mv88e6xxx_chip * chip,int port,struct phylink_config * config)619 static void mv88e6250_phylink_get_caps(struct mv88e6xxx_chip *chip, int port,
620 struct phylink_config *config)
621 {
622 if (!mv88e6xxx_phy_is_internal(chip, port))
623 mv88e6250_setup_supported_interfaces(chip, port, config);
624
625 config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100;
626 }
627
mv88e6351_phylink_get_caps(struct mv88e6xxx_chip * chip,int port,struct phylink_config * config)628 static void mv88e6351_phylink_get_caps(struct mv88e6xxx_chip *chip, int port,
629 struct phylink_config *config)
630 {
631 unsigned long *supported = config->supported_interfaces;
632
633 /* Translate the default cmode */
634 mv88e6xxx_translate_cmode(chip->ports[port].cmode, supported);
635
636 config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100 |
637 MAC_1000FD;
638 }
639
mv88e63xx_get_port_serdes_cmode(struct mv88e6xxx_chip * chip,int port)640 static int mv88e63xx_get_port_serdes_cmode(struct mv88e6xxx_chip *chip, int port)
641 {
642 u16 reg, val;
643 int err;
644
645 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_STS, ®);
646 if (err)
647 return err;
648
649 /* If PHY_DETECT is zero, then we are not in auto-media mode */
650 if (!(reg & MV88E6XXX_PORT_STS_PHY_DETECT))
651 return 0xf;
652
653 val = reg & ~MV88E6XXX_PORT_STS_PHY_DETECT;
654 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_STS, val);
655 if (err)
656 return err;
657
658 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_STS, &val);
659 if (err)
660 return err;
661
662 /* Restore PHY_DETECT value */
663 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_STS, reg);
664 if (err)
665 return err;
666
667 return val & MV88E6XXX_PORT_STS_CMODE_MASK;
668 }
669
mv88e6352_phylink_get_caps(struct mv88e6xxx_chip * chip,int port,struct phylink_config * config)670 static void mv88e6352_phylink_get_caps(struct mv88e6xxx_chip *chip, int port,
671 struct phylink_config *config)
672 {
673 unsigned long *supported = config->supported_interfaces;
674 int err, cmode;
675
676 /* Translate the default cmode */
677 mv88e6xxx_translate_cmode(chip->ports[port].cmode, supported);
678
679 config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100 |
680 MAC_1000FD;
681
682 /* Port 4 supports automedia if the serdes is associated with it. */
683 if (port == 4) {
684 err = mv88e6352_g2_scratch_port_has_serdes(chip, port);
685 if (err < 0)
686 dev_err(chip->dev, "p%d: failed to read scratch\n",
687 port);
688 if (err <= 0)
689 return;
690
691 cmode = mv88e63xx_get_port_serdes_cmode(chip, port);
692 if (cmode < 0)
693 dev_err(chip->dev, "p%d: failed to read serdes cmode\n",
694 port);
695 else
696 mv88e6xxx_translate_cmode(cmode, supported);
697 }
698 }
699
mv88e632x_phylink_get_caps(struct mv88e6xxx_chip * chip,int port,struct phylink_config * config)700 static void mv88e632x_phylink_get_caps(struct mv88e6xxx_chip *chip, int port,
701 struct phylink_config *config)
702 {
703 unsigned long *supported = config->supported_interfaces;
704 int cmode;
705
706 /* Translate the default cmode */
707 mv88e6xxx_translate_cmode(chip->ports[port].cmode, supported);
708
709 config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100 |
710 MAC_1000FD;
711
712 /* Port 0/1 are serdes only ports */
713 if (port == 0 || port == 1) {
714 cmode = mv88e63xx_get_port_serdes_cmode(chip, port);
715 if (cmode < 0)
716 dev_err(chip->dev, "p%d: failed to read serdes cmode\n",
717 port);
718 else
719 mv88e6xxx_translate_cmode(cmode, supported);
720 }
721 }
722
mv88e6341_phylink_get_caps(struct mv88e6xxx_chip * chip,int port,struct phylink_config * config)723 static void mv88e6341_phylink_get_caps(struct mv88e6xxx_chip *chip, int port,
724 struct phylink_config *config)
725 {
726 unsigned long *supported = config->supported_interfaces;
727
728 /* Translate the default cmode */
729 mv88e6xxx_translate_cmode(chip->ports[port].cmode, supported);
730
731 /* No ethtool bits for 200Mbps */
732 config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100 |
733 MAC_1000FD;
734
735 /* The C_Mode field is programmable on port 5 */
736 if (port == 5) {
737 __set_bit(PHY_INTERFACE_MODE_SGMII, supported);
738 __set_bit(PHY_INTERFACE_MODE_1000BASEX, supported);
739 __set_bit(PHY_INTERFACE_MODE_2500BASEX, supported);
740
741 config->mac_capabilities |= MAC_2500FD;
742 }
743 }
744
mv88e6390_phylink_get_caps(struct mv88e6xxx_chip * chip,int port,struct phylink_config * config)745 static void mv88e6390_phylink_get_caps(struct mv88e6xxx_chip *chip, int port,
746 struct phylink_config *config)
747 {
748 unsigned long *supported = config->supported_interfaces;
749
750 /* Translate the default cmode */
751 mv88e6xxx_translate_cmode(chip->ports[port].cmode, supported);
752
753 /* No ethtool bits for 200Mbps */
754 config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100 |
755 MAC_1000FD;
756
757 /* The C_Mode field is programmable on ports 9 and 10 */
758 if (port == 9 || port == 10) {
759 __set_bit(PHY_INTERFACE_MODE_SGMII, supported);
760 __set_bit(PHY_INTERFACE_MODE_1000BASEX, supported);
761 __set_bit(PHY_INTERFACE_MODE_2500BASEX, supported);
762
763 config->mac_capabilities |= MAC_2500FD;
764 }
765 }
766
mv88e6390x_phylink_get_caps(struct mv88e6xxx_chip * chip,int port,struct phylink_config * config)767 static void mv88e6390x_phylink_get_caps(struct mv88e6xxx_chip *chip, int port,
768 struct phylink_config *config)
769 {
770 unsigned long *supported = config->supported_interfaces;
771
772 mv88e6390_phylink_get_caps(chip, port, config);
773
774 /* For the 6x90X, ports 2-7 can be in automedia mode.
775 * (Note that 6x90 doesn't support RXAUI nor XAUI).
776 *
777 * Port 2 can also support 1000BASE-X in automedia mode if port 9 is
778 * configured for 1000BASE-X, SGMII or 2500BASE-X.
779 * Port 3-4 can also support 1000BASE-X in automedia mode if port 9 is
780 * configured for RXAUI, 1000BASE-X, SGMII or 2500BASE-X.
781 *
782 * Port 5 can also support 1000BASE-X in automedia mode if port 10 is
783 * configured for 1000BASE-X, SGMII or 2500BASE-X.
784 * Port 6-7 can also support 1000BASE-X in automedia mode if port 10 is
785 * configured for RXAUI, 1000BASE-X, SGMII or 2500BASE-X.
786 *
787 * For now, be permissive (as the old code was) and allow 1000BASE-X
788 * on ports 2..7.
789 */
790 if (port >= 2 && port <= 7)
791 __set_bit(PHY_INTERFACE_MODE_1000BASEX, supported);
792
793 /* The C_Mode field can also be programmed for 10G speeds */
794 if (port == 9 || port == 10) {
795 __set_bit(PHY_INTERFACE_MODE_XAUI, supported);
796 __set_bit(PHY_INTERFACE_MODE_RXAUI, supported);
797
798 config->mac_capabilities |= MAC_10000FD;
799 }
800 }
801
mv88e6393x_phylink_get_caps(struct mv88e6xxx_chip * chip,int port,struct phylink_config * config)802 static void mv88e6393x_phylink_get_caps(struct mv88e6xxx_chip *chip, int port,
803 struct phylink_config *config)
804 {
805 unsigned long *supported = config->supported_interfaces;
806 bool is_6191x =
807 chip->info->prod_num == MV88E6XXX_PORT_SWITCH_ID_PROD_6191X;
808 bool is_6361 =
809 chip->info->prod_num == MV88E6XXX_PORT_SWITCH_ID_PROD_6361;
810
811 mv88e6xxx_translate_cmode(chip->ports[port].cmode, supported);
812
813 config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100 |
814 MAC_1000FD;
815
816 /* The C_Mode field can be programmed for ports 0, 9 and 10 */
817 if (port == 0 || port == 9 || port == 10) {
818 __set_bit(PHY_INTERFACE_MODE_SGMII, supported);
819 __set_bit(PHY_INTERFACE_MODE_1000BASEX, supported);
820
821 /* 6191X supports >1G modes only on port 10 */
822 if (!is_6191x || port == 10) {
823 __set_bit(PHY_INTERFACE_MODE_2500BASEX, supported);
824 config->mac_capabilities |= MAC_2500FD;
825
826 /* 6361 only supports up to 2500BaseX */
827 if (!is_6361) {
828 __set_bit(PHY_INTERFACE_MODE_5GBASER, supported);
829 __set_bit(PHY_INTERFACE_MODE_10GBASER, supported);
830 __set_bit(PHY_INTERFACE_MODE_USXGMII, supported);
831 config->mac_capabilities |= MAC_5000FD |
832 MAC_10000FD;
833 }
834 }
835 }
836
837 if (port == 0) {
838 __set_bit(PHY_INTERFACE_MODE_RMII, supported);
839 __set_bit(PHY_INTERFACE_MODE_RGMII, supported);
840 __set_bit(PHY_INTERFACE_MODE_RGMII_ID, supported);
841 __set_bit(PHY_INTERFACE_MODE_RGMII_RXID, supported);
842 __set_bit(PHY_INTERFACE_MODE_RGMII_TXID, supported);
843 }
844 }
845
mv88e6xxx_get_caps(struct dsa_switch * ds,int port,struct phylink_config * config)846 static void mv88e6xxx_get_caps(struct dsa_switch *ds, int port,
847 struct phylink_config *config)
848 {
849 struct mv88e6xxx_chip *chip = ds->priv;
850
851 mv88e6xxx_reg_lock(chip);
852 chip->info->ops->phylink_get_caps(chip, port, config);
853 mv88e6xxx_reg_unlock(chip);
854
855 if (mv88e6xxx_phy_is_internal(chip, port)) {
856 __set_bit(PHY_INTERFACE_MODE_INTERNAL,
857 config->supported_interfaces);
858 /* Internal ports with no phy-mode need GMII for PHYLIB */
859 __set_bit(PHY_INTERFACE_MODE_GMII,
860 config->supported_interfaces);
861 }
862 }
863
864 static struct phylink_pcs *
mv88e6xxx_mac_select_pcs(struct phylink_config * config,phy_interface_t interface)865 mv88e6xxx_mac_select_pcs(struct phylink_config *config,
866 phy_interface_t interface)
867 {
868 struct dsa_port *dp = dsa_phylink_to_port(config);
869 struct mv88e6xxx_chip *chip = dp->ds->priv;
870 struct phylink_pcs *pcs = ERR_PTR(-EOPNOTSUPP);
871
872 if (chip->info->ops->pcs_ops)
873 pcs = chip->info->ops->pcs_ops->pcs_select(chip, dp->index,
874 interface);
875
876 return pcs;
877 }
878
mv88e6xxx_mac_prepare(struct phylink_config * config,unsigned int mode,phy_interface_t interface)879 static int mv88e6xxx_mac_prepare(struct phylink_config *config,
880 unsigned int mode, phy_interface_t interface)
881 {
882 struct dsa_port *dp = dsa_phylink_to_port(config);
883 struct mv88e6xxx_chip *chip = dp->ds->priv;
884 int port = dp->index;
885 int err = 0;
886
887 /* In inband mode, the link may come up at any time while the link
888 * is not forced down. Force the link down while we reconfigure the
889 * interface mode.
890 */
891 if (mode == MLO_AN_INBAND &&
892 chip->ports[port].interface != interface &&
893 chip->info->ops->port_set_link) {
894 mv88e6xxx_reg_lock(chip);
895 err = chip->info->ops->port_set_link(chip, port,
896 LINK_FORCED_DOWN);
897 mv88e6xxx_reg_unlock(chip);
898 }
899
900 return err;
901 }
902
mv88e6xxx_mac_config(struct phylink_config * config,unsigned int mode,const struct phylink_link_state * state)903 static void mv88e6xxx_mac_config(struct phylink_config *config,
904 unsigned int mode,
905 const struct phylink_link_state *state)
906 {
907 struct dsa_port *dp = dsa_phylink_to_port(config);
908 struct mv88e6xxx_chip *chip = dp->ds->priv;
909 int port = dp->index;
910 int err = 0;
911
912 mv88e6xxx_reg_lock(chip);
913
914 if (mode != MLO_AN_PHY || !mv88e6xxx_phy_is_internal(chip, port)) {
915 err = mv88e6xxx_port_config_interface(chip, port,
916 state->interface);
917 if (err && err != -EOPNOTSUPP)
918 goto err_unlock;
919 }
920
921 err_unlock:
922 mv88e6xxx_reg_unlock(chip);
923
924 if (err && err != -EOPNOTSUPP)
925 dev_err(chip->dev, "p%d: failed to configure MAC/PCS\n", port);
926 }
927
mv88e6xxx_mac_finish(struct phylink_config * config,unsigned int mode,phy_interface_t interface)928 static int mv88e6xxx_mac_finish(struct phylink_config *config,
929 unsigned int mode, phy_interface_t interface)
930 {
931 struct dsa_port *dp = dsa_phylink_to_port(config);
932 struct mv88e6xxx_chip *chip = dp->ds->priv;
933 int port = dp->index;
934 int err = 0;
935
936 /* Undo the forced down state above after completing configuration
937 * irrespective of its state on entry, which allows the link to come
938 * up in the in-band case where there is no separate SERDES. Also
939 * ensure that the link can come up if the PPU is in use and we are
940 * in PHY mode (we treat the PPU as an effective in-band mechanism.)
941 */
942 mv88e6xxx_reg_lock(chip);
943
944 if (chip->info->ops->port_set_link &&
945 ((mode == MLO_AN_INBAND &&
946 chip->ports[port].interface != interface) ||
947 (mode == MLO_AN_PHY && mv88e6xxx_port_ppu_updates(chip, port))))
948 err = chip->info->ops->port_set_link(chip, port, LINK_UNFORCED);
949
950 mv88e6xxx_reg_unlock(chip);
951
952 chip->ports[port].interface = interface;
953
954 return err;
955 }
956
mv88e6xxx_mac_link_down(struct phylink_config * config,unsigned int mode,phy_interface_t interface)957 static void mv88e6xxx_mac_link_down(struct phylink_config *config,
958 unsigned int mode,
959 phy_interface_t interface)
960 {
961 struct dsa_port *dp = dsa_phylink_to_port(config);
962 struct mv88e6xxx_chip *chip = dp->ds->priv;
963 const struct mv88e6xxx_ops *ops;
964 int port = dp->index;
965 int err = 0;
966
967 ops = chip->info->ops;
968
969 mv88e6xxx_reg_lock(chip);
970 /* Force the link down if we know the port may not be automatically
971 * updated by the switch or if we are using fixed-link mode.
972 */
973 if ((!mv88e6xxx_port_ppu_updates(chip, port) ||
974 mode == MLO_AN_FIXED) && ops->port_sync_link)
975 err = ops->port_sync_link(chip, port, mode, false);
976
977 if (!err && ops->port_set_speed_duplex)
978 err = ops->port_set_speed_duplex(chip, port, SPEED_UNFORCED,
979 DUPLEX_UNFORCED);
980 mv88e6xxx_reg_unlock(chip);
981
982 if (err)
983 dev_err(chip->dev,
984 "p%d: failed to force MAC link down\n", port);
985 }
986
mv88e6xxx_mac_link_up(struct phylink_config * config,struct phy_device * phydev,unsigned int mode,phy_interface_t interface,int speed,int duplex,bool tx_pause,bool rx_pause)987 static void mv88e6xxx_mac_link_up(struct phylink_config *config,
988 struct phy_device *phydev,
989 unsigned int mode, phy_interface_t interface,
990 int speed, int duplex,
991 bool tx_pause, bool rx_pause)
992 {
993 struct dsa_port *dp = dsa_phylink_to_port(config);
994 struct mv88e6xxx_chip *chip = dp->ds->priv;
995 const struct mv88e6xxx_ops *ops;
996 int port = dp->index;
997 int err = 0;
998
999 ops = chip->info->ops;
1000
1001 mv88e6xxx_reg_lock(chip);
1002 /* Configure and force the link up if we know that the port may not
1003 * automatically updated by the switch or if we are using fixed-link
1004 * mode.
1005 */
1006 if (!mv88e6xxx_port_ppu_updates(chip, port) ||
1007 mode == MLO_AN_FIXED) {
1008 if (ops->port_set_speed_duplex) {
1009 err = ops->port_set_speed_duplex(chip, port,
1010 speed, duplex);
1011 if (err && err != -EOPNOTSUPP)
1012 goto error;
1013 }
1014
1015 if (ops->port_sync_link)
1016 err = ops->port_sync_link(chip, port, mode, true);
1017 }
1018 error:
1019 mv88e6xxx_reg_unlock(chip);
1020
1021 if (err && err != -EOPNOTSUPP)
1022 dev_err(chip->dev,
1023 "p%d: failed to configure MAC link up\n", port);
1024 }
1025
mv88e6xxx_stats_snapshot(struct mv88e6xxx_chip * chip,int port)1026 static int mv88e6xxx_stats_snapshot(struct mv88e6xxx_chip *chip, int port)
1027 {
1028 int err;
1029
1030 if (!chip->info->ops->stats_snapshot)
1031 return -EOPNOTSUPP;
1032
1033 mv88e6xxx_reg_lock(chip);
1034 err = chip->info->ops->stats_snapshot(chip, port);
1035 mv88e6xxx_reg_unlock(chip);
1036
1037 return err;
1038 }
1039
1040 #define MV88E6XXX_HW_STAT_MAPPER(_fn) \
1041 _fn(in_good_octets, 8, 0x00, STATS_TYPE_BANK0), \
1042 _fn(in_bad_octets, 4, 0x02, STATS_TYPE_BANK0), \
1043 _fn(in_unicast, 4, 0x04, STATS_TYPE_BANK0), \
1044 _fn(in_broadcasts, 4, 0x06, STATS_TYPE_BANK0), \
1045 _fn(in_multicasts, 4, 0x07, STATS_TYPE_BANK0), \
1046 _fn(in_pause, 4, 0x16, STATS_TYPE_BANK0), \
1047 _fn(in_undersize, 4, 0x18, STATS_TYPE_BANK0), \
1048 _fn(in_fragments, 4, 0x19, STATS_TYPE_BANK0), \
1049 _fn(in_oversize, 4, 0x1a, STATS_TYPE_BANK0), \
1050 _fn(in_jabber, 4, 0x1b, STATS_TYPE_BANK0), \
1051 _fn(in_rx_error, 4, 0x1c, STATS_TYPE_BANK0), \
1052 _fn(in_fcs_error, 4, 0x1d, STATS_TYPE_BANK0), \
1053 _fn(out_octets, 8, 0x0e, STATS_TYPE_BANK0), \
1054 _fn(out_unicast, 4, 0x10, STATS_TYPE_BANK0), \
1055 _fn(out_broadcasts, 4, 0x13, STATS_TYPE_BANK0), \
1056 _fn(out_multicasts, 4, 0x12, STATS_TYPE_BANK0), \
1057 _fn(out_pause, 4, 0x15, STATS_TYPE_BANK0), \
1058 _fn(excessive, 4, 0x11, STATS_TYPE_BANK0), \
1059 _fn(collisions, 4, 0x1e, STATS_TYPE_BANK0), \
1060 _fn(deferred, 4, 0x05, STATS_TYPE_BANK0), \
1061 _fn(single, 4, 0x14, STATS_TYPE_BANK0), \
1062 _fn(multiple, 4, 0x17, STATS_TYPE_BANK0), \
1063 _fn(out_fcs_error, 4, 0x03, STATS_TYPE_BANK0), \
1064 _fn(late, 4, 0x1f, STATS_TYPE_BANK0), \
1065 _fn(hist_64bytes, 4, 0x08, STATS_TYPE_BANK0), \
1066 _fn(hist_65_127bytes, 4, 0x09, STATS_TYPE_BANK0), \
1067 _fn(hist_128_255bytes, 4, 0x0a, STATS_TYPE_BANK0), \
1068 _fn(hist_256_511bytes, 4, 0x0b, STATS_TYPE_BANK0), \
1069 _fn(hist_512_1023bytes, 4, 0x0c, STATS_TYPE_BANK0), \
1070 _fn(hist_1024_max_bytes, 4, 0x0d, STATS_TYPE_BANK0), \
1071 _fn(sw_in_discards, 4, 0x10, STATS_TYPE_PORT), \
1072 _fn(sw_in_filtered, 2, 0x12, STATS_TYPE_PORT), \
1073 _fn(sw_out_filtered, 2, 0x13, STATS_TYPE_PORT), \
1074 _fn(in_discards, 4, 0x00, STATS_TYPE_BANK1), \
1075 _fn(in_filtered, 4, 0x01, STATS_TYPE_BANK1), \
1076 _fn(in_accepted, 4, 0x02, STATS_TYPE_BANK1), \
1077 _fn(in_bad_accepted, 4, 0x03, STATS_TYPE_BANK1), \
1078 _fn(in_good_avb_class_a, 4, 0x04, STATS_TYPE_BANK1), \
1079 _fn(in_good_avb_class_b, 4, 0x05, STATS_TYPE_BANK1), \
1080 _fn(in_bad_avb_class_a, 4, 0x06, STATS_TYPE_BANK1), \
1081 _fn(in_bad_avb_class_b, 4, 0x07, STATS_TYPE_BANK1), \
1082 _fn(tcam_counter_0, 4, 0x08, STATS_TYPE_BANK1), \
1083 _fn(tcam_counter_1, 4, 0x09, STATS_TYPE_BANK1), \
1084 _fn(tcam_counter_2, 4, 0x0a, STATS_TYPE_BANK1), \
1085 _fn(tcam_counter_3, 4, 0x0b, STATS_TYPE_BANK1), \
1086 _fn(in_da_unknown, 4, 0x0e, STATS_TYPE_BANK1), \
1087 _fn(in_management, 4, 0x0f, STATS_TYPE_BANK1), \
1088 _fn(out_queue_0, 4, 0x10, STATS_TYPE_BANK1), \
1089 _fn(out_queue_1, 4, 0x11, STATS_TYPE_BANK1), \
1090 _fn(out_queue_2, 4, 0x12, STATS_TYPE_BANK1), \
1091 _fn(out_queue_3, 4, 0x13, STATS_TYPE_BANK1), \
1092 _fn(out_queue_4, 4, 0x14, STATS_TYPE_BANK1), \
1093 _fn(out_queue_5, 4, 0x15, STATS_TYPE_BANK1), \
1094 _fn(out_queue_6, 4, 0x16, STATS_TYPE_BANK1), \
1095 _fn(out_queue_7, 4, 0x17, STATS_TYPE_BANK1), \
1096 _fn(out_cut_through, 4, 0x18, STATS_TYPE_BANK1), \
1097 _fn(out_octets_a, 4, 0x1a, STATS_TYPE_BANK1), \
1098 _fn(out_octets_b, 4, 0x1b, STATS_TYPE_BANK1), \
1099 _fn(out_management, 4, 0x1f, STATS_TYPE_BANK1), \
1100 /* */
1101
1102 #define MV88E6XXX_HW_STAT_ENTRY(_string, _size, _reg, _type) \
1103 { #_string, _size, _reg, _type }
1104 static const struct mv88e6xxx_hw_stat mv88e6xxx_hw_stats[] = {
1105 MV88E6XXX_HW_STAT_MAPPER(MV88E6XXX_HW_STAT_ENTRY)
1106 };
1107
1108 #define MV88E6XXX_HW_STAT_ENUM(_string, _size, _reg, _type) \
1109 MV88E6XXX_HW_STAT_ID_ ## _string
1110 enum mv88e6xxx_hw_stat_id {
1111 MV88E6XXX_HW_STAT_MAPPER(MV88E6XXX_HW_STAT_ENUM)
1112 };
1113
_mv88e6xxx_get_ethtool_stat(struct mv88e6xxx_chip * chip,const struct mv88e6xxx_hw_stat * s,int port,u16 bank1_select,u16 histogram)1114 static uint64_t _mv88e6xxx_get_ethtool_stat(struct mv88e6xxx_chip *chip,
1115 const struct mv88e6xxx_hw_stat *s,
1116 int port, u16 bank1_select,
1117 u16 histogram)
1118 {
1119 u32 low;
1120 u32 high = 0;
1121 u16 reg = 0;
1122 int err;
1123 u64 value;
1124
1125 switch (s->type) {
1126 case STATS_TYPE_PORT:
1127 err = mv88e6xxx_port_read(chip, port, s->reg, ®);
1128 if (err)
1129 return U64_MAX;
1130
1131 low = reg;
1132 if (s->size == 4) {
1133 err = mv88e6xxx_port_read(chip, port, s->reg + 1, ®);
1134 if (err)
1135 return U64_MAX;
1136 low |= ((u32)reg) << 16;
1137 }
1138 break;
1139 case STATS_TYPE_BANK1:
1140 reg = bank1_select;
1141 fallthrough;
1142 case STATS_TYPE_BANK0:
1143 reg |= s->reg | histogram;
1144 mv88e6xxx_g1_stats_read(chip, reg, &low);
1145 if (s->size == 8)
1146 mv88e6xxx_g1_stats_read(chip, reg + 1, &high);
1147 break;
1148 default:
1149 return U64_MAX;
1150 }
1151 value = (((u64)high) << 32) | low;
1152 return value;
1153 }
1154
mv88e6xxx_stats_get_strings(struct mv88e6xxx_chip * chip,uint8_t * data,int types)1155 static int mv88e6xxx_stats_get_strings(struct mv88e6xxx_chip *chip,
1156 uint8_t *data, int types)
1157 {
1158 const struct mv88e6xxx_hw_stat *stat;
1159 int i, j;
1160
1161 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
1162 stat = &mv88e6xxx_hw_stats[i];
1163 if (stat->type & types) {
1164 memcpy(data + j * ETH_GSTRING_LEN, stat->string,
1165 ETH_GSTRING_LEN);
1166 j++;
1167 }
1168 }
1169
1170 return j;
1171 }
1172
mv88e6095_stats_get_strings(struct mv88e6xxx_chip * chip,uint8_t * data)1173 static int mv88e6095_stats_get_strings(struct mv88e6xxx_chip *chip,
1174 uint8_t *data)
1175 {
1176 return mv88e6xxx_stats_get_strings(chip, data,
1177 STATS_TYPE_BANK0 | STATS_TYPE_PORT);
1178 }
1179
mv88e6250_stats_get_strings(struct mv88e6xxx_chip * chip,uint8_t * data)1180 static int mv88e6250_stats_get_strings(struct mv88e6xxx_chip *chip,
1181 uint8_t *data)
1182 {
1183 return mv88e6xxx_stats_get_strings(chip, data, STATS_TYPE_BANK0);
1184 }
1185
mv88e6320_stats_get_strings(struct mv88e6xxx_chip * chip,uint8_t * data)1186 static int mv88e6320_stats_get_strings(struct mv88e6xxx_chip *chip,
1187 uint8_t *data)
1188 {
1189 return mv88e6xxx_stats_get_strings(chip, data,
1190 STATS_TYPE_BANK0 | STATS_TYPE_BANK1);
1191 }
1192
1193 static const uint8_t *mv88e6xxx_atu_vtu_stats_strings[] = {
1194 "atu_member_violation",
1195 "atu_miss_violation",
1196 "atu_full_violation",
1197 "vtu_member_violation",
1198 "vtu_miss_violation",
1199 };
1200
mv88e6xxx_atu_vtu_get_strings(uint8_t * data)1201 static void mv88e6xxx_atu_vtu_get_strings(uint8_t *data)
1202 {
1203 unsigned int i;
1204
1205 for (i = 0; i < ARRAY_SIZE(mv88e6xxx_atu_vtu_stats_strings); i++)
1206 strscpy(data + i * ETH_GSTRING_LEN,
1207 mv88e6xxx_atu_vtu_stats_strings[i],
1208 ETH_GSTRING_LEN);
1209 }
1210
mv88e6xxx_get_strings(struct dsa_switch * ds,int port,u32 stringset,uint8_t * data)1211 static void mv88e6xxx_get_strings(struct dsa_switch *ds, int port,
1212 u32 stringset, uint8_t *data)
1213 {
1214 struct mv88e6xxx_chip *chip = ds->priv;
1215 int count = 0;
1216
1217 if (stringset != ETH_SS_STATS)
1218 return;
1219
1220 mv88e6xxx_reg_lock(chip);
1221
1222 if (chip->info->ops->stats_get_strings)
1223 count = chip->info->ops->stats_get_strings(chip, data);
1224
1225 if (chip->info->ops->serdes_get_strings) {
1226 data += count * ETH_GSTRING_LEN;
1227 count = chip->info->ops->serdes_get_strings(chip, port, data);
1228 }
1229
1230 data += count * ETH_GSTRING_LEN;
1231 mv88e6xxx_atu_vtu_get_strings(data);
1232
1233 mv88e6xxx_reg_unlock(chip);
1234 }
1235
mv88e6xxx_stats_get_sset_count(struct mv88e6xxx_chip * chip,int types)1236 static int mv88e6xxx_stats_get_sset_count(struct mv88e6xxx_chip *chip,
1237 int types)
1238 {
1239 const struct mv88e6xxx_hw_stat *stat;
1240 int i, j;
1241
1242 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
1243 stat = &mv88e6xxx_hw_stats[i];
1244 if (stat->type & types)
1245 j++;
1246 }
1247 return j;
1248 }
1249
mv88e6095_stats_get_sset_count(struct mv88e6xxx_chip * chip)1250 static int mv88e6095_stats_get_sset_count(struct mv88e6xxx_chip *chip)
1251 {
1252 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 |
1253 STATS_TYPE_PORT);
1254 }
1255
mv88e6250_stats_get_sset_count(struct mv88e6xxx_chip * chip)1256 static int mv88e6250_stats_get_sset_count(struct mv88e6xxx_chip *chip)
1257 {
1258 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0);
1259 }
1260
mv88e6320_stats_get_sset_count(struct mv88e6xxx_chip * chip)1261 static int mv88e6320_stats_get_sset_count(struct mv88e6xxx_chip *chip)
1262 {
1263 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 |
1264 STATS_TYPE_BANK1);
1265 }
1266
mv88e6xxx_get_sset_count(struct dsa_switch * ds,int port,int sset)1267 static int mv88e6xxx_get_sset_count(struct dsa_switch *ds, int port, int sset)
1268 {
1269 struct mv88e6xxx_chip *chip = ds->priv;
1270 int serdes_count = 0;
1271 int count = 0;
1272
1273 if (sset != ETH_SS_STATS)
1274 return 0;
1275
1276 mv88e6xxx_reg_lock(chip);
1277 if (chip->info->ops->stats_get_sset_count)
1278 count = chip->info->ops->stats_get_sset_count(chip);
1279 if (count < 0)
1280 goto out;
1281
1282 if (chip->info->ops->serdes_get_sset_count)
1283 serdes_count = chip->info->ops->serdes_get_sset_count(chip,
1284 port);
1285 if (serdes_count < 0) {
1286 count = serdes_count;
1287 goto out;
1288 }
1289 count += serdes_count;
1290 count += ARRAY_SIZE(mv88e6xxx_atu_vtu_stats_strings);
1291
1292 out:
1293 mv88e6xxx_reg_unlock(chip);
1294
1295 return count;
1296 }
1297
mv88e6095_stats_get_stat(struct mv88e6xxx_chip * chip,int port,const struct mv88e6xxx_hw_stat * stat,uint64_t * data)1298 static size_t mv88e6095_stats_get_stat(struct mv88e6xxx_chip *chip, int port,
1299 const struct mv88e6xxx_hw_stat *stat,
1300 uint64_t *data)
1301 {
1302 if (!(stat->type & (STATS_TYPE_BANK0 | STATS_TYPE_PORT)))
1303 return 0;
1304
1305 *data = _mv88e6xxx_get_ethtool_stat(chip, stat, port, 0,
1306 MV88E6XXX_G1_STATS_OP_HIST_RX);
1307 return 1;
1308 }
1309
mv88e6250_stats_get_stat(struct mv88e6xxx_chip * chip,int port,const struct mv88e6xxx_hw_stat * stat,uint64_t * data)1310 static size_t mv88e6250_stats_get_stat(struct mv88e6xxx_chip *chip, int port,
1311 const struct mv88e6xxx_hw_stat *stat,
1312 uint64_t *data)
1313 {
1314 if (!(stat->type & STATS_TYPE_BANK0))
1315 return 0;
1316
1317 *data = _mv88e6xxx_get_ethtool_stat(chip, stat, port, 0,
1318 MV88E6XXX_G1_STATS_OP_HIST_RX);
1319 return 1;
1320 }
1321
mv88e6320_stats_get_stat(struct mv88e6xxx_chip * chip,int port,const struct mv88e6xxx_hw_stat * stat,uint64_t * data)1322 static size_t mv88e6320_stats_get_stat(struct mv88e6xxx_chip *chip, int port,
1323 const struct mv88e6xxx_hw_stat *stat,
1324 uint64_t *data)
1325 {
1326 if (!(stat->type & (STATS_TYPE_BANK0 | STATS_TYPE_BANK1)))
1327 return 0;
1328
1329 *data = _mv88e6xxx_get_ethtool_stat(chip, stat, port,
1330 MV88E6XXX_G1_STATS_OP_BANK_1_BIT_9,
1331 MV88E6XXX_G1_STATS_OP_HIST_RX);
1332 return 1;
1333 }
1334
mv88e6390_stats_get_stat(struct mv88e6xxx_chip * chip,int port,const struct mv88e6xxx_hw_stat * stat,uint64_t * data)1335 static size_t mv88e6390_stats_get_stat(struct mv88e6xxx_chip *chip, int port,
1336 const struct mv88e6xxx_hw_stat *stat,
1337 uint64_t *data)
1338 {
1339 if (!(stat->type & (STATS_TYPE_BANK0 | STATS_TYPE_BANK1)))
1340 return 0;
1341
1342 *data = _mv88e6xxx_get_ethtool_stat(chip, stat, port,
1343 MV88E6XXX_G1_STATS_OP_BANK_1_BIT_10,
1344 0);
1345 return 1;
1346 }
1347
mv88e6xxx_stats_get_stat(struct mv88e6xxx_chip * chip,int port,const struct mv88e6xxx_hw_stat * stat,uint64_t * data)1348 static size_t mv88e6xxx_stats_get_stat(struct mv88e6xxx_chip *chip, int port,
1349 const struct mv88e6xxx_hw_stat *stat,
1350 uint64_t *data)
1351 {
1352 int ret = 0;
1353
1354 if (chip->info->ops->stats_get_stat) {
1355 mv88e6xxx_reg_lock(chip);
1356 ret = chip->info->ops->stats_get_stat(chip, port, stat, data);
1357 mv88e6xxx_reg_unlock(chip);
1358 }
1359
1360 return ret;
1361 }
1362
mv88e6xxx_stats_get_stats(struct mv88e6xxx_chip * chip,int port,uint64_t * data)1363 static size_t mv88e6xxx_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
1364 uint64_t *data)
1365 {
1366 const struct mv88e6xxx_hw_stat *stat;
1367 size_t i, j;
1368
1369 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
1370 stat = &mv88e6xxx_hw_stats[i];
1371 j += mv88e6xxx_stats_get_stat(chip, port, stat, &data[j]);
1372 }
1373 return j;
1374 }
1375
mv88e6xxx_atu_vtu_get_stats(struct mv88e6xxx_chip * chip,int port,uint64_t * data)1376 static void mv88e6xxx_atu_vtu_get_stats(struct mv88e6xxx_chip *chip, int port,
1377 uint64_t *data)
1378 {
1379 *data++ = chip->ports[port].atu_member_violation;
1380 *data++ = chip->ports[port].atu_miss_violation;
1381 *data++ = chip->ports[port].atu_full_violation;
1382 *data++ = chip->ports[port].vtu_member_violation;
1383 *data++ = chip->ports[port].vtu_miss_violation;
1384 }
1385
mv88e6xxx_get_stats(struct mv88e6xxx_chip * chip,int port,uint64_t * data)1386 static void mv88e6xxx_get_stats(struct mv88e6xxx_chip *chip, int port,
1387 uint64_t *data)
1388 {
1389 size_t count;
1390
1391 count = mv88e6xxx_stats_get_stats(chip, port, data);
1392
1393 mv88e6xxx_reg_lock(chip);
1394 if (chip->info->ops->serdes_get_stats) {
1395 data += count;
1396 count = chip->info->ops->serdes_get_stats(chip, port, data);
1397 }
1398 data += count;
1399 mv88e6xxx_atu_vtu_get_stats(chip, port, data);
1400 mv88e6xxx_reg_unlock(chip);
1401 }
1402
mv88e6xxx_get_ethtool_stats(struct dsa_switch * ds,int port,uint64_t * data)1403 static void mv88e6xxx_get_ethtool_stats(struct dsa_switch *ds, int port,
1404 uint64_t *data)
1405 {
1406 struct mv88e6xxx_chip *chip = ds->priv;
1407 int ret;
1408
1409 ret = mv88e6xxx_stats_snapshot(chip, port);
1410 if (ret < 0)
1411 return;
1412
1413 mv88e6xxx_get_stats(chip, port, data);
1414 }
1415
mv88e6xxx_get_eth_mac_stats(struct dsa_switch * ds,int port,struct ethtool_eth_mac_stats * mac_stats)1416 static void mv88e6xxx_get_eth_mac_stats(struct dsa_switch *ds, int port,
1417 struct ethtool_eth_mac_stats *mac_stats)
1418 {
1419 struct mv88e6xxx_chip *chip = ds->priv;
1420 int ret;
1421
1422 ret = mv88e6xxx_stats_snapshot(chip, port);
1423 if (ret < 0)
1424 return;
1425
1426 #define MV88E6XXX_ETH_MAC_STAT_MAP(_id, _member) \
1427 mv88e6xxx_stats_get_stat(chip, port, \
1428 &mv88e6xxx_hw_stats[MV88E6XXX_HW_STAT_ID_ ## _id], \
1429 &mac_stats->stats._member)
1430
1431 MV88E6XXX_ETH_MAC_STAT_MAP(out_unicast, FramesTransmittedOK);
1432 MV88E6XXX_ETH_MAC_STAT_MAP(single, SingleCollisionFrames);
1433 MV88E6XXX_ETH_MAC_STAT_MAP(multiple, MultipleCollisionFrames);
1434 MV88E6XXX_ETH_MAC_STAT_MAP(in_unicast, FramesReceivedOK);
1435 MV88E6XXX_ETH_MAC_STAT_MAP(in_fcs_error, FrameCheckSequenceErrors);
1436 MV88E6XXX_ETH_MAC_STAT_MAP(out_octets, OctetsTransmittedOK);
1437 MV88E6XXX_ETH_MAC_STAT_MAP(deferred, FramesWithDeferredXmissions);
1438 MV88E6XXX_ETH_MAC_STAT_MAP(late, LateCollisions);
1439 MV88E6XXX_ETH_MAC_STAT_MAP(in_good_octets, OctetsReceivedOK);
1440 MV88E6XXX_ETH_MAC_STAT_MAP(out_multicasts, MulticastFramesXmittedOK);
1441 MV88E6XXX_ETH_MAC_STAT_MAP(out_broadcasts, BroadcastFramesXmittedOK);
1442 MV88E6XXX_ETH_MAC_STAT_MAP(excessive, FramesWithExcessiveDeferral);
1443 MV88E6XXX_ETH_MAC_STAT_MAP(in_multicasts, MulticastFramesReceivedOK);
1444 MV88E6XXX_ETH_MAC_STAT_MAP(in_broadcasts, BroadcastFramesReceivedOK);
1445
1446 #undef MV88E6XXX_ETH_MAC_STAT_MAP
1447
1448 mac_stats->stats.FramesTransmittedOK += mac_stats->stats.MulticastFramesXmittedOK;
1449 mac_stats->stats.FramesTransmittedOK += mac_stats->stats.BroadcastFramesXmittedOK;
1450 mac_stats->stats.FramesReceivedOK += mac_stats->stats.MulticastFramesReceivedOK;
1451 mac_stats->stats.FramesReceivedOK += mac_stats->stats.BroadcastFramesReceivedOK;
1452 }
1453
mv88e6xxx_get_rmon_stats(struct dsa_switch * ds,int port,struct ethtool_rmon_stats * rmon_stats,const struct ethtool_rmon_hist_range ** ranges)1454 static void mv88e6xxx_get_rmon_stats(struct dsa_switch *ds, int port,
1455 struct ethtool_rmon_stats *rmon_stats,
1456 const struct ethtool_rmon_hist_range **ranges)
1457 {
1458 static const struct ethtool_rmon_hist_range rmon_ranges[] = {
1459 { 64, 64 },
1460 { 65, 127 },
1461 { 128, 255 },
1462 { 256, 511 },
1463 { 512, 1023 },
1464 { 1024, 65535 },
1465 {}
1466 };
1467 struct mv88e6xxx_chip *chip = ds->priv;
1468 int ret;
1469
1470 ret = mv88e6xxx_stats_snapshot(chip, port);
1471 if (ret < 0)
1472 return;
1473
1474 #define MV88E6XXX_RMON_STAT_MAP(_id, _member) \
1475 mv88e6xxx_stats_get_stat(chip, port, \
1476 &mv88e6xxx_hw_stats[MV88E6XXX_HW_STAT_ID_ ## _id], \
1477 &rmon_stats->stats._member)
1478
1479 MV88E6XXX_RMON_STAT_MAP(in_undersize, undersize_pkts);
1480 MV88E6XXX_RMON_STAT_MAP(in_oversize, oversize_pkts);
1481 MV88E6XXX_RMON_STAT_MAP(in_fragments, fragments);
1482 MV88E6XXX_RMON_STAT_MAP(in_jabber, jabbers);
1483 MV88E6XXX_RMON_STAT_MAP(hist_64bytes, hist[0]);
1484 MV88E6XXX_RMON_STAT_MAP(hist_65_127bytes, hist[1]);
1485 MV88E6XXX_RMON_STAT_MAP(hist_128_255bytes, hist[2]);
1486 MV88E6XXX_RMON_STAT_MAP(hist_256_511bytes, hist[3]);
1487 MV88E6XXX_RMON_STAT_MAP(hist_512_1023bytes, hist[4]);
1488 MV88E6XXX_RMON_STAT_MAP(hist_1024_max_bytes, hist[5]);
1489
1490 #undef MV88E6XXX_RMON_STAT_MAP
1491
1492 *ranges = rmon_ranges;
1493 }
1494
mv88e6xxx_get_regs_len(struct dsa_switch * ds,int port)1495 static int mv88e6xxx_get_regs_len(struct dsa_switch *ds, int port)
1496 {
1497 struct mv88e6xxx_chip *chip = ds->priv;
1498 int len;
1499
1500 len = 32 * sizeof(u16);
1501 if (chip->info->ops->serdes_get_regs_len)
1502 len += chip->info->ops->serdes_get_regs_len(chip, port);
1503
1504 return len;
1505 }
1506
mv88e6xxx_get_regs(struct dsa_switch * ds,int port,struct ethtool_regs * regs,void * _p)1507 static void mv88e6xxx_get_regs(struct dsa_switch *ds, int port,
1508 struct ethtool_regs *regs, void *_p)
1509 {
1510 struct mv88e6xxx_chip *chip = ds->priv;
1511 int err;
1512 u16 reg;
1513 u16 *p = _p;
1514 int i;
1515
1516 regs->version = chip->info->prod_num;
1517
1518 memset(p, 0xff, 32 * sizeof(u16));
1519
1520 mv88e6xxx_reg_lock(chip);
1521
1522 for (i = 0; i < 32; i++) {
1523
1524 err = mv88e6xxx_port_read(chip, port, i, ®);
1525 if (!err)
1526 p[i] = reg;
1527 }
1528
1529 if (chip->info->ops->serdes_get_regs)
1530 chip->info->ops->serdes_get_regs(chip, port, &p[i]);
1531
1532 mv88e6xxx_reg_unlock(chip);
1533 }
1534
mv88e6xxx_get_mac_eee(struct dsa_switch * ds,int port,struct ethtool_keee * e)1535 static int mv88e6xxx_get_mac_eee(struct dsa_switch *ds, int port,
1536 struct ethtool_keee *e)
1537 {
1538 /* Nothing to do on the port's MAC */
1539 return 0;
1540 }
1541
mv88e6xxx_set_mac_eee(struct dsa_switch * ds,int port,struct ethtool_keee * e)1542 static int mv88e6xxx_set_mac_eee(struct dsa_switch *ds, int port,
1543 struct ethtool_keee *e)
1544 {
1545 /* Nothing to do on the port's MAC */
1546 return 0;
1547 }
1548
1549 /* Mask of the local ports allowed to receive frames from a given fabric port */
mv88e6xxx_port_vlan(struct mv88e6xxx_chip * chip,int dev,int port)1550 static u16 mv88e6xxx_port_vlan(struct mv88e6xxx_chip *chip, int dev, int port)
1551 {
1552 struct dsa_switch *ds = chip->ds;
1553 struct dsa_switch_tree *dst = ds->dst;
1554 struct dsa_port *dp, *other_dp;
1555 bool found = false;
1556 u16 pvlan;
1557
1558 /* dev is a physical switch */
1559 if (dev <= dst->last_switch) {
1560 list_for_each_entry(dp, &dst->ports, list) {
1561 if (dp->ds->index == dev && dp->index == port) {
1562 /* dp might be a DSA link or a user port, so it
1563 * might or might not have a bridge.
1564 * Use the "found" variable for both cases.
1565 */
1566 found = true;
1567 break;
1568 }
1569 }
1570 /* dev is a virtual bridge */
1571 } else {
1572 list_for_each_entry(dp, &dst->ports, list) {
1573 unsigned int bridge_num = dsa_port_bridge_num_get(dp);
1574
1575 if (!bridge_num)
1576 continue;
1577
1578 if (bridge_num + dst->last_switch != dev)
1579 continue;
1580
1581 found = true;
1582 break;
1583 }
1584 }
1585
1586 /* Prevent frames from unknown switch or virtual bridge */
1587 if (!found)
1588 return 0;
1589
1590 /* Frames from DSA links and CPU ports can egress any local port */
1591 if (dp->type == DSA_PORT_TYPE_CPU || dp->type == DSA_PORT_TYPE_DSA)
1592 return mv88e6xxx_port_mask(chip);
1593
1594 pvlan = 0;
1595
1596 /* Frames from standalone user ports can only egress on the
1597 * upstream port.
1598 */
1599 if (!dsa_port_bridge_dev_get(dp))
1600 return BIT(dsa_switch_upstream_port(ds));
1601
1602 /* Frames from bridged user ports can egress any local DSA
1603 * links and CPU ports, as well as any local member of their
1604 * bridge group.
1605 */
1606 dsa_switch_for_each_port(other_dp, ds)
1607 if (other_dp->type == DSA_PORT_TYPE_CPU ||
1608 other_dp->type == DSA_PORT_TYPE_DSA ||
1609 dsa_port_bridge_same(dp, other_dp))
1610 pvlan |= BIT(other_dp->index);
1611
1612 return pvlan;
1613 }
1614
mv88e6xxx_port_vlan_map(struct mv88e6xxx_chip * chip,int port)1615 static int mv88e6xxx_port_vlan_map(struct mv88e6xxx_chip *chip, int port)
1616 {
1617 u16 output_ports = mv88e6xxx_port_vlan(chip, chip->ds->index, port);
1618
1619 /* prevent frames from going back out of the port they came in on */
1620 output_ports &= ~BIT(port);
1621
1622 return mv88e6xxx_port_set_vlan_map(chip, port, output_ports);
1623 }
1624
mv88e6xxx_port_stp_state_set(struct dsa_switch * ds,int port,u8 state)1625 static void mv88e6xxx_port_stp_state_set(struct dsa_switch *ds, int port,
1626 u8 state)
1627 {
1628 struct mv88e6xxx_chip *chip = ds->priv;
1629 int err;
1630
1631 mv88e6xxx_reg_lock(chip);
1632 err = mv88e6xxx_port_set_state(chip, port, state);
1633 mv88e6xxx_reg_unlock(chip);
1634
1635 if (err)
1636 dev_err(ds->dev, "p%d: failed to update state\n", port);
1637 }
1638
mv88e6xxx_pri_setup(struct mv88e6xxx_chip * chip)1639 static int mv88e6xxx_pri_setup(struct mv88e6xxx_chip *chip)
1640 {
1641 int err;
1642
1643 if (chip->info->ops->ieee_pri_map) {
1644 err = chip->info->ops->ieee_pri_map(chip);
1645 if (err)
1646 return err;
1647 }
1648
1649 if (chip->info->ops->ip_pri_map) {
1650 err = chip->info->ops->ip_pri_map(chip);
1651 if (err)
1652 return err;
1653 }
1654
1655 return 0;
1656 }
1657
mv88e6xxx_devmap_setup(struct mv88e6xxx_chip * chip)1658 static int mv88e6xxx_devmap_setup(struct mv88e6xxx_chip *chip)
1659 {
1660 struct dsa_switch *ds = chip->ds;
1661 int target, port;
1662 int err;
1663
1664 if (!chip->info->global2_addr)
1665 return 0;
1666
1667 /* Initialize the routing port to the 32 possible target devices */
1668 for (target = 0; target < 32; target++) {
1669 port = dsa_routing_port(ds, target);
1670 if (port == ds->num_ports)
1671 port = 0x1f;
1672
1673 err = mv88e6xxx_g2_device_mapping_write(chip, target, port);
1674 if (err)
1675 return err;
1676 }
1677
1678 if (chip->info->ops->set_cascade_port) {
1679 port = MV88E6XXX_CASCADE_PORT_MULTIPLE;
1680 err = chip->info->ops->set_cascade_port(chip, port);
1681 if (err)
1682 return err;
1683 }
1684
1685 err = mv88e6xxx_g1_set_device_number(chip, chip->ds->index);
1686 if (err)
1687 return err;
1688
1689 return 0;
1690 }
1691
mv88e6xxx_trunk_setup(struct mv88e6xxx_chip * chip)1692 static int mv88e6xxx_trunk_setup(struct mv88e6xxx_chip *chip)
1693 {
1694 /* Clear all trunk masks and mapping */
1695 if (chip->info->global2_addr)
1696 return mv88e6xxx_g2_trunk_clear(chip);
1697
1698 return 0;
1699 }
1700
mv88e6xxx_rmu_setup(struct mv88e6xxx_chip * chip)1701 static int mv88e6xxx_rmu_setup(struct mv88e6xxx_chip *chip)
1702 {
1703 if (chip->info->ops->rmu_disable)
1704 return chip->info->ops->rmu_disable(chip);
1705
1706 return 0;
1707 }
1708
mv88e6xxx_pot_setup(struct mv88e6xxx_chip * chip)1709 static int mv88e6xxx_pot_setup(struct mv88e6xxx_chip *chip)
1710 {
1711 if (chip->info->ops->pot_clear)
1712 return chip->info->ops->pot_clear(chip);
1713
1714 return 0;
1715 }
1716
mv88e6xxx_rsvd2cpu_setup(struct mv88e6xxx_chip * chip)1717 static int mv88e6xxx_rsvd2cpu_setup(struct mv88e6xxx_chip *chip)
1718 {
1719 if (chip->info->ops->mgmt_rsvd2cpu)
1720 return chip->info->ops->mgmt_rsvd2cpu(chip);
1721
1722 return 0;
1723 }
1724
mv88e6xxx_atu_setup(struct mv88e6xxx_chip * chip)1725 static int mv88e6xxx_atu_setup(struct mv88e6xxx_chip *chip)
1726 {
1727 int err;
1728
1729 err = mv88e6xxx_g1_atu_flush(chip, 0, true);
1730 if (err)
1731 return err;
1732
1733 /* The chips that have a "learn2all" bit in Global1, ATU
1734 * Control are precisely those whose port registers have a
1735 * Message Port bit in Port Control 1 and hence implement
1736 * ->port_setup_message_port.
1737 */
1738 if (chip->info->ops->port_setup_message_port) {
1739 err = mv88e6xxx_g1_atu_set_learn2all(chip, true);
1740 if (err)
1741 return err;
1742 }
1743
1744 return mv88e6xxx_g1_atu_set_age_time(chip, 300000);
1745 }
1746
mv88e6xxx_irl_setup(struct mv88e6xxx_chip * chip)1747 static int mv88e6xxx_irl_setup(struct mv88e6xxx_chip *chip)
1748 {
1749 int port;
1750 int err;
1751
1752 if (!chip->info->ops->irl_init_all)
1753 return 0;
1754
1755 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) {
1756 /* Disable ingress rate limiting by resetting all per port
1757 * ingress rate limit resources to their initial state.
1758 */
1759 err = chip->info->ops->irl_init_all(chip, port);
1760 if (err)
1761 return err;
1762 }
1763
1764 return 0;
1765 }
1766
mv88e6xxx_mac_setup(struct mv88e6xxx_chip * chip)1767 static int mv88e6xxx_mac_setup(struct mv88e6xxx_chip *chip)
1768 {
1769 if (chip->info->ops->set_switch_mac) {
1770 u8 addr[ETH_ALEN];
1771
1772 eth_random_addr(addr);
1773
1774 return chip->info->ops->set_switch_mac(chip, addr);
1775 }
1776
1777 return 0;
1778 }
1779
mv88e6xxx_pvt_map(struct mv88e6xxx_chip * chip,int dev,int port)1780 static int mv88e6xxx_pvt_map(struct mv88e6xxx_chip *chip, int dev, int port)
1781 {
1782 struct dsa_switch_tree *dst = chip->ds->dst;
1783 struct dsa_switch *ds;
1784 struct dsa_port *dp;
1785 u16 pvlan = 0;
1786
1787 if (!mv88e6xxx_has_pvt(chip))
1788 return 0;
1789
1790 /* Skip the local source device, which uses in-chip port VLAN */
1791 if (dev != chip->ds->index) {
1792 pvlan = mv88e6xxx_port_vlan(chip, dev, port);
1793
1794 ds = dsa_switch_find(dst->index, dev);
1795 dp = ds ? dsa_to_port(ds, port) : NULL;
1796 if (dp && dp->lag) {
1797 /* As the PVT is used to limit flooding of
1798 * FORWARD frames, which use the LAG ID as the
1799 * source port, we must translate dev/port to
1800 * the special "LAG device" in the PVT, using
1801 * the LAG ID (one-based) as the port number
1802 * (zero-based).
1803 */
1804 dev = MV88E6XXX_G2_PVT_ADDR_DEV_TRUNK;
1805 port = dsa_port_lag_id_get(dp) - 1;
1806 }
1807 }
1808
1809 return mv88e6xxx_g2_pvt_write(chip, dev, port, pvlan);
1810 }
1811
mv88e6xxx_pvt_setup(struct mv88e6xxx_chip * chip)1812 static int mv88e6xxx_pvt_setup(struct mv88e6xxx_chip *chip)
1813 {
1814 int dev, port;
1815 int err;
1816
1817 if (!mv88e6xxx_has_pvt(chip))
1818 return 0;
1819
1820 /* Clear 5 Bit Port for usage with Marvell Link Street devices:
1821 * use 4 bits for the Src_Port/Src_Trunk and 5 bits for the Src_Dev.
1822 */
1823 err = mv88e6xxx_g2_misc_4_bit_port(chip);
1824 if (err)
1825 return err;
1826
1827 for (dev = 0; dev < MV88E6XXX_MAX_PVT_SWITCHES; ++dev) {
1828 for (port = 0; port < MV88E6XXX_MAX_PVT_PORTS; ++port) {
1829 err = mv88e6xxx_pvt_map(chip, dev, port);
1830 if (err)
1831 return err;
1832 }
1833 }
1834
1835 return 0;
1836 }
1837
mv88e6xxx_port_fast_age_fid(struct mv88e6xxx_chip * chip,int port,u16 fid)1838 static int mv88e6xxx_port_fast_age_fid(struct mv88e6xxx_chip *chip, int port,
1839 u16 fid)
1840 {
1841 if (dsa_to_port(chip->ds, port)->lag)
1842 /* Hardware is incapable of fast-aging a LAG through a
1843 * regular ATU move operation. Until we have something
1844 * more fancy in place this is a no-op.
1845 */
1846 return -EOPNOTSUPP;
1847
1848 return mv88e6xxx_g1_atu_remove(chip, fid, port, false);
1849 }
1850
mv88e6xxx_port_fast_age(struct dsa_switch * ds,int port)1851 static void mv88e6xxx_port_fast_age(struct dsa_switch *ds, int port)
1852 {
1853 struct mv88e6xxx_chip *chip = ds->priv;
1854 int err;
1855
1856 mv88e6xxx_reg_lock(chip);
1857 err = mv88e6xxx_port_fast_age_fid(chip, port, 0);
1858 mv88e6xxx_reg_unlock(chip);
1859
1860 if (err)
1861 dev_err(chip->ds->dev, "p%d: failed to flush ATU: %d\n",
1862 port, err);
1863 }
1864
mv88e6xxx_vtu_setup(struct mv88e6xxx_chip * chip)1865 static int mv88e6xxx_vtu_setup(struct mv88e6xxx_chip *chip)
1866 {
1867 if (!mv88e6xxx_max_vid(chip))
1868 return 0;
1869
1870 return mv88e6xxx_g1_vtu_flush(chip);
1871 }
1872
mv88e6xxx_vtu_get(struct mv88e6xxx_chip * chip,u16 vid,struct mv88e6xxx_vtu_entry * entry)1873 static int mv88e6xxx_vtu_get(struct mv88e6xxx_chip *chip, u16 vid,
1874 struct mv88e6xxx_vtu_entry *entry)
1875 {
1876 int err;
1877
1878 if (!chip->info->ops->vtu_getnext)
1879 return -EOPNOTSUPP;
1880
1881 memset(entry, 0, sizeof(*entry));
1882
1883 entry->vid = vid ? vid - 1 : mv88e6xxx_max_vid(chip);
1884 entry->valid = false;
1885
1886 err = chip->info->ops->vtu_getnext(chip, entry);
1887
1888 if (entry->vid != vid)
1889 entry->valid = false;
1890
1891 return err;
1892 }
1893
mv88e6xxx_vtu_walk(struct mv88e6xxx_chip * chip,int (* cb)(struct mv88e6xxx_chip * chip,const struct mv88e6xxx_vtu_entry * entry,void * priv),void * priv)1894 int mv88e6xxx_vtu_walk(struct mv88e6xxx_chip *chip,
1895 int (*cb)(struct mv88e6xxx_chip *chip,
1896 const struct mv88e6xxx_vtu_entry *entry,
1897 void *priv),
1898 void *priv)
1899 {
1900 struct mv88e6xxx_vtu_entry entry = {
1901 .vid = mv88e6xxx_max_vid(chip),
1902 .valid = false,
1903 };
1904 int err;
1905
1906 if (!chip->info->ops->vtu_getnext)
1907 return -EOPNOTSUPP;
1908
1909 do {
1910 err = chip->info->ops->vtu_getnext(chip, &entry);
1911 if (err)
1912 return err;
1913
1914 if (!entry.valid)
1915 break;
1916
1917 err = cb(chip, &entry, priv);
1918 if (err)
1919 return err;
1920 } while (entry.vid < mv88e6xxx_max_vid(chip));
1921
1922 return 0;
1923 }
1924
mv88e6xxx_vtu_loadpurge(struct mv88e6xxx_chip * chip,struct mv88e6xxx_vtu_entry * entry)1925 static int mv88e6xxx_vtu_loadpurge(struct mv88e6xxx_chip *chip,
1926 struct mv88e6xxx_vtu_entry *entry)
1927 {
1928 if (!chip->info->ops->vtu_loadpurge)
1929 return -EOPNOTSUPP;
1930
1931 return chip->info->ops->vtu_loadpurge(chip, entry);
1932 }
1933
mv88e6xxx_fid_map_vlan(struct mv88e6xxx_chip * chip,const struct mv88e6xxx_vtu_entry * entry,void * _fid_bitmap)1934 static int mv88e6xxx_fid_map_vlan(struct mv88e6xxx_chip *chip,
1935 const struct mv88e6xxx_vtu_entry *entry,
1936 void *_fid_bitmap)
1937 {
1938 unsigned long *fid_bitmap = _fid_bitmap;
1939
1940 set_bit(entry->fid, fid_bitmap);
1941 return 0;
1942 }
1943
mv88e6xxx_fid_map(struct mv88e6xxx_chip * chip,unsigned long * fid_bitmap)1944 int mv88e6xxx_fid_map(struct mv88e6xxx_chip *chip, unsigned long *fid_bitmap)
1945 {
1946 bitmap_zero(fid_bitmap, MV88E6XXX_N_FID);
1947
1948 /* Every FID has an associated VID, so walking the VTU
1949 * will discover the full set of FIDs in use.
1950 */
1951 return mv88e6xxx_vtu_walk(chip, mv88e6xxx_fid_map_vlan, fid_bitmap);
1952 }
1953
mv88e6xxx_atu_new(struct mv88e6xxx_chip * chip,u16 * fid)1954 static int mv88e6xxx_atu_new(struct mv88e6xxx_chip *chip, u16 *fid)
1955 {
1956 DECLARE_BITMAP(fid_bitmap, MV88E6XXX_N_FID);
1957 int err;
1958
1959 err = mv88e6xxx_fid_map(chip, fid_bitmap);
1960 if (err)
1961 return err;
1962
1963 *fid = find_first_zero_bit(fid_bitmap, MV88E6XXX_N_FID);
1964 if (unlikely(*fid >= mv88e6xxx_num_databases(chip)))
1965 return -ENOSPC;
1966
1967 /* Clear the database */
1968 return mv88e6xxx_g1_atu_flush(chip, *fid, true);
1969 }
1970
mv88e6xxx_stu_loadpurge(struct mv88e6xxx_chip * chip,struct mv88e6xxx_stu_entry * entry)1971 static int mv88e6xxx_stu_loadpurge(struct mv88e6xxx_chip *chip,
1972 struct mv88e6xxx_stu_entry *entry)
1973 {
1974 if (!chip->info->ops->stu_loadpurge)
1975 return -EOPNOTSUPP;
1976
1977 return chip->info->ops->stu_loadpurge(chip, entry);
1978 }
1979
mv88e6xxx_stu_setup(struct mv88e6xxx_chip * chip)1980 static int mv88e6xxx_stu_setup(struct mv88e6xxx_chip *chip)
1981 {
1982 struct mv88e6xxx_stu_entry stu = {
1983 .valid = true,
1984 .sid = 0
1985 };
1986
1987 if (!mv88e6xxx_has_stu(chip))
1988 return 0;
1989
1990 /* Make sure that SID 0 is always valid. This is used by VTU
1991 * entries that do not make use of the STU, e.g. when creating
1992 * a VLAN upper on a port that is also part of a VLAN
1993 * filtering bridge.
1994 */
1995 return mv88e6xxx_stu_loadpurge(chip, &stu);
1996 }
1997
mv88e6xxx_sid_get(struct mv88e6xxx_chip * chip,u8 * sid)1998 static int mv88e6xxx_sid_get(struct mv88e6xxx_chip *chip, u8 *sid)
1999 {
2000 DECLARE_BITMAP(busy, MV88E6XXX_N_SID) = { 0 };
2001 struct mv88e6xxx_mst *mst;
2002
2003 __set_bit(0, busy);
2004
2005 list_for_each_entry(mst, &chip->msts, node)
2006 __set_bit(mst->stu.sid, busy);
2007
2008 *sid = find_first_zero_bit(busy, MV88E6XXX_N_SID);
2009
2010 return (*sid >= mv88e6xxx_max_sid(chip)) ? -ENOSPC : 0;
2011 }
2012
mv88e6xxx_mst_put(struct mv88e6xxx_chip * chip,u8 sid)2013 static int mv88e6xxx_mst_put(struct mv88e6xxx_chip *chip, u8 sid)
2014 {
2015 struct mv88e6xxx_mst *mst, *tmp;
2016 int err;
2017
2018 /* If the SID is zero, it is for a VLAN mapped to the default MSTI,
2019 * and mv88e6xxx_stu_setup() made sure it is always present, and thus,
2020 * should not be removed here.
2021 *
2022 * If the chip lacks STU support, numerically the "sid" variable will
2023 * happen to also be zero, but we don't want to rely on that fact, so
2024 * we explicitly test that first. In that case, there is also nothing
2025 * to do here.
2026 */
2027 if (!mv88e6xxx_has_stu(chip) || !sid)
2028 return 0;
2029
2030 list_for_each_entry_safe(mst, tmp, &chip->msts, node) {
2031 if (mst->stu.sid != sid)
2032 continue;
2033
2034 if (!refcount_dec_and_test(&mst->refcnt))
2035 return 0;
2036
2037 mst->stu.valid = false;
2038 err = mv88e6xxx_stu_loadpurge(chip, &mst->stu);
2039 if (err) {
2040 refcount_set(&mst->refcnt, 1);
2041 return err;
2042 }
2043
2044 list_del(&mst->node);
2045 kfree(mst);
2046 return 0;
2047 }
2048
2049 return -ENOENT;
2050 }
2051
mv88e6xxx_mst_get(struct mv88e6xxx_chip * chip,struct net_device * br,u16 msti,u8 * sid)2052 static int mv88e6xxx_mst_get(struct mv88e6xxx_chip *chip, struct net_device *br,
2053 u16 msti, u8 *sid)
2054 {
2055 struct mv88e6xxx_mst *mst;
2056 int err, i;
2057
2058 if (!mv88e6xxx_has_stu(chip)) {
2059 err = -EOPNOTSUPP;
2060 goto err;
2061 }
2062
2063 if (!msti) {
2064 *sid = 0;
2065 return 0;
2066 }
2067
2068 list_for_each_entry(mst, &chip->msts, node) {
2069 if (mst->br == br && mst->msti == msti) {
2070 refcount_inc(&mst->refcnt);
2071 *sid = mst->stu.sid;
2072 return 0;
2073 }
2074 }
2075
2076 err = mv88e6xxx_sid_get(chip, sid);
2077 if (err)
2078 goto err;
2079
2080 mst = kzalloc(sizeof(*mst), GFP_KERNEL);
2081 if (!mst) {
2082 err = -ENOMEM;
2083 goto err;
2084 }
2085
2086 INIT_LIST_HEAD(&mst->node);
2087 refcount_set(&mst->refcnt, 1);
2088 mst->br = br;
2089 mst->msti = msti;
2090 mst->stu.valid = true;
2091 mst->stu.sid = *sid;
2092
2093 /* The bridge starts out all ports in the disabled state. But
2094 * a STU state of disabled means to go by the port-global
2095 * state. So we set all user port's initial state to blocking,
2096 * to match the bridge's behavior.
2097 */
2098 for (i = 0; i < mv88e6xxx_num_ports(chip); i++)
2099 mst->stu.state[i] = dsa_is_user_port(chip->ds, i) ?
2100 MV88E6XXX_PORT_CTL0_STATE_BLOCKING :
2101 MV88E6XXX_PORT_CTL0_STATE_DISABLED;
2102
2103 err = mv88e6xxx_stu_loadpurge(chip, &mst->stu);
2104 if (err)
2105 goto err_free;
2106
2107 list_add_tail(&mst->node, &chip->msts);
2108 return 0;
2109
2110 err_free:
2111 kfree(mst);
2112 err:
2113 return err;
2114 }
2115
mv88e6xxx_port_mst_state_set(struct dsa_switch * ds,int port,const struct switchdev_mst_state * st)2116 static int mv88e6xxx_port_mst_state_set(struct dsa_switch *ds, int port,
2117 const struct switchdev_mst_state *st)
2118 {
2119 struct dsa_port *dp = dsa_to_port(ds, port);
2120 struct mv88e6xxx_chip *chip = ds->priv;
2121 struct mv88e6xxx_mst *mst;
2122 u8 state;
2123 int err;
2124
2125 if (!mv88e6xxx_has_stu(chip))
2126 return -EOPNOTSUPP;
2127
2128 switch (st->state) {
2129 case BR_STATE_DISABLED:
2130 case BR_STATE_BLOCKING:
2131 case BR_STATE_LISTENING:
2132 state = MV88E6XXX_PORT_CTL0_STATE_BLOCKING;
2133 break;
2134 case BR_STATE_LEARNING:
2135 state = MV88E6XXX_PORT_CTL0_STATE_LEARNING;
2136 break;
2137 case BR_STATE_FORWARDING:
2138 state = MV88E6XXX_PORT_CTL0_STATE_FORWARDING;
2139 break;
2140 default:
2141 return -EINVAL;
2142 }
2143
2144 list_for_each_entry(mst, &chip->msts, node) {
2145 if (mst->br == dsa_port_bridge_dev_get(dp) &&
2146 mst->msti == st->msti) {
2147 if (mst->stu.state[port] == state)
2148 return 0;
2149
2150 mst->stu.state[port] = state;
2151 mv88e6xxx_reg_lock(chip);
2152 err = mv88e6xxx_stu_loadpurge(chip, &mst->stu);
2153 mv88e6xxx_reg_unlock(chip);
2154 return err;
2155 }
2156 }
2157
2158 return -ENOENT;
2159 }
2160
mv88e6xxx_port_check_hw_vlan(struct dsa_switch * ds,int port,u16 vid)2161 static int mv88e6xxx_port_check_hw_vlan(struct dsa_switch *ds, int port,
2162 u16 vid)
2163 {
2164 struct dsa_port *dp = dsa_to_port(ds, port), *other_dp;
2165 struct mv88e6xxx_chip *chip = ds->priv;
2166 struct mv88e6xxx_vtu_entry vlan;
2167 int err;
2168
2169 /* DSA and CPU ports have to be members of multiple vlans */
2170 if (dsa_port_is_dsa(dp) || dsa_port_is_cpu(dp))
2171 return 0;
2172
2173 err = mv88e6xxx_vtu_get(chip, vid, &vlan);
2174 if (err)
2175 return err;
2176
2177 if (!vlan.valid)
2178 return 0;
2179
2180 dsa_switch_for_each_user_port(other_dp, ds) {
2181 struct net_device *other_br;
2182
2183 if (vlan.member[other_dp->index] ==
2184 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER)
2185 continue;
2186
2187 if (dsa_port_bridge_same(dp, other_dp))
2188 break; /* same bridge, check next VLAN */
2189
2190 other_br = dsa_port_bridge_dev_get(other_dp);
2191 if (!other_br)
2192 continue;
2193
2194 dev_err(ds->dev, "p%d: hw VLAN %d already used by port %d in %s\n",
2195 port, vlan.vid, other_dp->index, netdev_name(other_br));
2196 return -EOPNOTSUPP;
2197 }
2198
2199 return 0;
2200 }
2201
mv88e6xxx_port_commit_pvid(struct mv88e6xxx_chip * chip,int port)2202 static int mv88e6xxx_port_commit_pvid(struct mv88e6xxx_chip *chip, int port)
2203 {
2204 struct dsa_port *dp = dsa_to_port(chip->ds, port);
2205 struct net_device *br = dsa_port_bridge_dev_get(dp);
2206 struct mv88e6xxx_port *p = &chip->ports[port];
2207 u16 pvid = MV88E6XXX_VID_STANDALONE;
2208 bool drop_untagged = false;
2209 int err;
2210
2211 if (br) {
2212 if (br_vlan_enabled(br)) {
2213 pvid = p->bridge_pvid.vid;
2214 drop_untagged = !p->bridge_pvid.valid;
2215 } else {
2216 pvid = MV88E6XXX_VID_BRIDGED;
2217 }
2218 }
2219
2220 err = mv88e6xxx_port_set_pvid(chip, port, pvid);
2221 if (err)
2222 return err;
2223
2224 return mv88e6xxx_port_drop_untagged(chip, port, drop_untagged);
2225 }
2226
mv88e6xxx_port_vlan_filtering(struct dsa_switch * ds,int port,bool vlan_filtering,struct netlink_ext_ack * extack)2227 static int mv88e6xxx_port_vlan_filtering(struct dsa_switch *ds, int port,
2228 bool vlan_filtering,
2229 struct netlink_ext_ack *extack)
2230 {
2231 struct mv88e6xxx_chip *chip = ds->priv;
2232 u16 mode = vlan_filtering ? MV88E6XXX_PORT_CTL2_8021Q_MODE_SECURE :
2233 MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED;
2234 int err;
2235
2236 if (!mv88e6xxx_max_vid(chip))
2237 return -EOPNOTSUPP;
2238
2239 mv88e6xxx_reg_lock(chip);
2240
2241 err = mv88e6xxx_port_set_8021q_mode(chip, port, mode);
2242 if (err)
2243 goto unlock;
2244
2245 err = mv88e6xxx_port_commit_pvid(chip, port);
2246 if (err)
2247 goto unlock;
2248
2249 unlock:
2250 mv88e6xxx_reg_unlock(chip);
2251
2252 return err;
2253 }
2254
2255 static int
mv88e6xxx_port_vlan_prepare(struct dsa_switch * ds,int port,const struct switchdev_obj_port_vlan * vlan)2256 mv88e6xxx_port_vlan_prepare(struct dsa_switch *ds, int port,
2257 const struct switchdev_obj_port_vlan *vlan)
2258 {
2259 struct mv88e6xxx_chip *chip = ds->priv;
2260 int err;
2261
2262 if (!mv88e6xxx_max_vid(chip))
2263 return -EOPNOTSUPP;
2264
2265 /* If the requested port doesn't belong to the same bridge as the VLAN
2266 * members, do not support it (yet) and fallback to software VLAN.
2267 */
2268 mv88e6xxx_reg_lock(chip);
2269 err = mv88e6xxx_port_check_hw_vlan(ds, port, vlan->vid);
2270 mv88e6xxx_reg_unlock(chip);
2271
2272 return err;
2273 }
2274
mv88e6xxx_port_db_get(struct mv88e6xxx_chip * chip,const unsigned char * addr,u16 vid,u16 * fid,struct mv88e6xxx_atu_entry * entry)2275 static int mv88e6xxx_port_db_get(struct mv88e6xxx_chip *chip,
2276 const unsigned char *addr, u16 vid,
2277 u16 *fid, struct mv88e6xxx_atu_entry *entry)
2278 {
2279 struct mv88e6xxx_vtu_entry vlan;
2280 int err;
2281
2282 /* Ports have two private address databases: one for when the port is
2283 * standalone and one for when the port is under a bridge and the
2284 * 802.1Q mode is disabled. When the port is standalone, DSA wants its
2285 * address database to remain 100% empty, so we never load an ATU entry
2286 * into a standalone port's database. Therefore, translate the null
2287 * VLAN ID into the port's database used for VLAN-unaware bridging.
2288 */
2289 if (vid == 0) {
2290 *fid = MV88E6XXX_FID_BRIDGED;
2291 } else {
2292 err = mv88e6xxx_vtu_get(chip, vid, &vlan);
2293 if (err)
2294 return err;
2295
2296 /* switchdev expects -EOPNOTSUPP to honor software VLANs */
2297 if (!vlan.valid)
2298 return -EOPNOTSUPP;
2299
2300 *fid = vlan.fid;
2301 }
2302
2303 entry->state = 0;
2304 ether_addr_copy(entry->mac, addr);
2305 eth_addr_dec(entry->mac);
2306
2307 return mv88e6xxx_g1_atu_getnext(chip, *fid, entry);
2308 }
2309
mv88e6xxx_port_db_find(struct mv88e6xxx_chip * chip,const unsigned char * addr,u16 vid)2310 static bool mv88e6xxx_port_db_find(struct mv88e6xxx_chip *chip,
2311 const unsigned char *addr, u16 vid)
2312 {
2313 struct mv88e6xxx_atu_entry entry;
2314 u16 fid;
2315 int err;
2316
2317 err = mv88e6xxx_port_db_get(chip, addr, vid, &fid, &entry);
2318 if (err)
2319 return false;
2320
2321 return entry.state && ether_addr_equal(entry.mac, addr);
2322 }
2323
mv88e6xxx_port_db_load_purge(struct mv88e6xxx_chip * chip,int port,const unsigned char * addr,u16 vid,u8 state)2324 static int mv88e6xxx_port_db_load_purge(struct mv88e6xxx_chip *chip, int port,
2325 const unsigned char *addr, u16 vid,
2326 u8 state)
2327 {
2328 struct mv88e6xxx_atu_entry entry;
2329 u16 fid;
2330 int err;
2331
2332 err = mv88e6xxx_port_db_get(chip, addr, vid, &fid, &entry);
2333 if (err)
2334 return err;
2335
2336 /* Initialize a fresh ATU entry if it isn't found */
2337 if (!entry.state || !ether_addr_equal(entry.mac, addr)) {
2338 memset(&entry, 0, sizeof(entry));
2339 ether_addr_copy(entry.mac, addr);
2340 }
2341
2342 /* Purge the ATU entry only if no port is using it anymore */
2343 if (!state) {
2344 entry.portvec &= ~BIT(port);
2345 if (!entry.portvec)
2346 entry.state = 0;
2347 } else {
2348 if (state == MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC)
2349 entry.portvec = BIT(port);
2350 else
2351 entry.portvec |= BIT(port);
2352
2353 entry.state = state;
2354 }
2355
2356 return mv88e6xxx_g1_atu_loadpurge(chip, fid, &entry);
2357 }
2358
mv88e6xxx_policy_apply(struct mv88e6xxx_chip * chip,int port,const struct mv88e6xxx_policy * policy)2359 static int mv88e6xxx_policy_apply(struct mv88e6xxx_chip *chip, int port,
2360 const struct mv88e6xxx_policy *policy)
2361 {
2362 enum mv88e6xxx_policy_mapping mapping = policy->mapping;
2363 enum mv88e6xxx_policy_action action = policy->action;
2364 const u8 *addr = policy->addr;
2365 u16 vid = policy->vid;
2366 u8 state;
2367 int err;
2368 int id;
2369
2370 if (!chip->info->ops->port_set_policy)
2371 return -EOPNOTSUPP;
2372
2373 switch (mapping) {
2374 case MV88E6XXX_POLICY_MAPPING_DA:
2375 case MV88E6XXX_POLICY_MAPPING_SA:
2376 if (action == MV88E6XXX_POLICY_ACTION_NORMAL)
2377 state = 0; /* Dissociate the port and address */
2378 else if (action == MV88E6XXX_POLICY_ACTION_DISCARD &&
2379 is_multicast_ether_addr(addr))
2380 state = MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC_POLICY;
2381 else if (action == MV88E6XXX_POLICY_ACTION_DISCARD &&
2382 is_unicast_ether_addr(addr))
2383 state = MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC_POLICY;
2384 else
2385 return -EOPNOTSUPP;
2386
2387 err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid,
2388 state);
2389 if (err)
2390 return err;
2391 break;
2392 default:
2393 return -EOPNOTSUPP;
2394 }
2395
2396 /* Skip the port's policy clearing if the mapping is still in use */
2397 if (action == MV88E6XXX_POLICY_ACTION_NORMAL)
2398 idr_for_each_entry(&chip->policies, policy, id)
2399 if (policy->port == port &&
2400 policy->mapping == mapping &&
2401 policy->action != action)
2402 return 0;
2403
2404 return chip->info->ops->port_set_policy(chip, port, mapping, action);
2405 }
2406
mv88e6xxx_policy_insert(struct mv88e6xxx_chip * chip,int port,struct ethtool_rx_flow_spec * fs)2407 static int mv88e6xxx_policy_insert(struct mv88e6xxx_chip *chip, int port,
2408 struct ethtool_rx_flow_spec *fs)
2409 {
2410 struct ethhdr *mac_entry = &fs->h_u.ether_spec;
2411 struct ethhdr *mac_mask = &fs->m_u.ether_spec;
2412 enum mv88e6xxx_policy_mapping mapping;
2413 enum mv88e6xxx_policy_action action;
2414 struct mv88e6xxx_policy *policy;
2415 u16 vid = 0;
2416 u8 *addr;
2417 int err;
2418 int id;
2419
2420 if (fs->location != RX_CLS_LOC_ANY)
2421 return -EINVAL;
2422
2423 if (fs->ring_cookie == RX_CLS_FLOW_DISC)
2424 action = MV88E6XXX_POLICY_ACTION_DISCARD;
2425 else
2426 return -EOPNOTSUPP;
2427
2428 switch (fs->flow_type & ~FLOW_EXT) {
2429 case ETHER_FLOW:
2430 if (!is_zero_ether_addr(mac_mask->h_dest) &&
2431 is_zero_ether_addr(mac_mask->h_source)) {
2432 mapping = MV88E6XXX_POLICY_MAPPING_DA;
2433 addr = mac_entry->h_dest;
2434 } else if (is_zero_ether_addr(mac_mask->h_dest) &&
2435 !is_zero_ether_addr(mac_mask->h_source)) {
2436 mapping = MV88E6XXX_POLICY_MAPPING_SA;
2437 addr = mac_entry->h_source;
2438 } else {
2439 /* Cannot support DA and SA mapping in the same rule */
2440 return -EOPNOTSUPP;
2441 }
2442 break;
2443 default:
2444 return -EOPNOTSUPP;
2445 }
2446
2447 if ((fs->flow_type & FLOW_EXT) && fs->m_ext.vlan_tci) {
2448 if (fs->m_ext.vlan_tci != htons(0xffff))
2449 return -EOPNOTSUPP;
2450 vid = be16_to_cpu(fs->h_ext.vlan_tci) & VLAN_VID_MASK;
2451 }
2452
2453 idr_for_each_entry(&chip->policies, policy, id) {
2454 if (policy->port == port && policy->mapping == mapping &&
2455 policy->action == action && policy->vid == vid &&
2456 ether_addr_equal(policy->addr, addr))
2457 return -EEXIST;
2458 }
2459
2460 policy = devm_kzalloc(chip->dev, sizeof(*policy), GFP_KERNEL);
2461 if (!policy)
2462 return -ENOMEM;
2463
2464 fs->location = 0;
2465 err = idr_alloc_u32(&chip->policies, policy, &fs->location, 0xffffffff,
2466 GFP_KERNEL);
2467 if (err) {
2468 devm_kfree(chip->dev, policy);
2469 return err;
2470 }
2471
2472 memcpy(&policy->fs, fs, sizeof(*fs));
2473 ether_addr_copy(policy->addr, addr);
2474 policy->mapping = mapping;
2475 policy->action = action;
2476 policy->port = port;
2477 policy->vid = vid;
2478
2479 err = mv88e6xxx_policy_apply(chip, port, policy);
2480 if (err) {
2481 idr_remove(&chip->policies, fs->location);
2482 devm_kfree(chip->dev, policy);
2483 return err;
2484 }
2485
2486 return 0;
2487 }
2488
mv88e6xxx_get_rxnfc(struct dsa_switch * ds,int port,struct ethtool_rxnfc * rxnfc,u32 * rule_locs)2489 static int mv88e6xxx_get_rxnfc(struct dsa_switch *ds, int port,
2490 struct ethtool_rxnfc *rxnfc, u32 *rule_locs)
2491 {
2492 struct ethtool_rx_flow_spec *fs = &rxnfc->fs;
2493 struct mv88e6xxx_chip *chip = ds->priv;
2494 struct mv88e6xxx_policy *policy;
2495 int err;
2496 int id;
2497
2498 mv88e6xxx_reg_lock(chip);
2499
2500 switch (rxnfc->cmd) {
2501 case ETHTOOL_GRXCLSRLCNT:
2502 rxnfc->data = 0;
2503 rxnfc->data |= RX_CLS_LOC_SPECIAL;
2504 rxnfc->rule_cnt = 0;
2505 idr_for_each_entry(&chip->policies, policy, id)
2506 if (policy->port == port)
2507 rxnfc->rule_cnt++;
2508 err = 0;
2509 break;
2510 case ETHTOOL_GRXCLSRULE:
2511 err = -ENOENT;
2512 policy = idr_find(&chip->policies, fs->location);
2513 if (policy) {
2514 memcpy(fs, &policy->fs, sizeof(*fs));
2515 err = 0;
2516 }
2517 break;
2518 case ETHTOOL_GRXCLSRLALL:
2519 rxnfc->data = 0;
2520 rxnfc->rule_cnt = 0;
2521 idr_for_each_entry(&chip->policies, policy, id)
2522 if (policy->port == port)
2523 rule_locs[rxnfc->rule_cnt++] = id;
2524 err = 0;
2525 break;
2526 default:
2527 err = -EOPNOTSUPP;
2528 break;
2529 }
2530
2531 mv88e6xxx_reg_unlock(chip);
2532
2533 return err;
2534 }
2535
mv88e6xxx_set_rxnfc(struct dsa_switch * ds,int port,struct ethtool_rxnfc * rxnfc)2536 static int mv88e6xxx_set_rxnfc(struct dsa_switch *ds, int port,
2537 struct ethtool_rxnfc *rxnfc)
2538 {
2539 struct ethtool_rx_flow_spec *fs = &rxnfc->fs;
2540 struct mv88e6xxx_chip *chip = ds->priv;
2541 struct mv88e6xxx_policy *policy;
2542 int err;
2543
2544 mv88e6xxx_reg_lock(chip);
2545
2546 switch (rxnfc->cmd) {
2547 case ETHTOOL_SRXCLSRLINS:
2548 err = mv88e6xxx_policy_insert(chip, port, fs);
2549 break;
2550 case ETHTOOL_SRXCLSRLDEL:
2551 err = -ENOENT;
2552 policy = idr_remove(&chip->policies, fs->location);
2553 if (policy) {
2554 policy->action = MV88E6XXX_POLICY_ACTION_NORMAL;
2555 err = mv88e6xxx_policy_apply(chip, port, policy);
2556 devm_kfree(chip->dev, policy);
2557 }
2558 break;
2559 default:
2560 err = -EOPNOTSUPP;
2561 break;
2562 }
2563
2564 mv88e6xxx_reg_unlock(chip);
2565
2566 return err;
2567 }
2568
mv88e6xxx_port_add_broadcast(struct mv88e6xxx_chip * chip,int port,u16 vid)2569 static int mv88e6xxx_port_add_broadcast(struct mv88e6xxx_chip *chip, int port,
2570 u16 vid)
2571 {
2572 u8 state = MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC;
2573 u8 broadcast[ETH_ALEN];
2574
2575 eth_broadcast_addr(broadcast);
2576
2577 return mv88e6xxx_port_db_load_purge(chip, port, broadcast, vid, state);
2578 }
2579
mv88e6xxx_broadcast_setup(struct mv88e6xxx_chip * chip,u16 vid)2580 static int mv88e6xxx_broadcast_setup(struct mv88e6xxx_chip *chip, u16 vid)
2581 {
2582 int port;
2583 int err;
2584
2585 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) {
2586 struct dsa_port *dp = dsa_to_port(chip->ds, port);
2587 struct net_device *brport;
2588
2589 if (dsa_is_unused_port(chip->ds, port))
2590 continue;
2591
2592 brport = dsa_port_to_bridge_port(dp);
2593 if (brport && !br_port_flag_is_set(brport, BR_BCAST_FLOOD))
2594 /* Skip bridged user ports where broadcast
2595 * flooding is disabled.
2596 */
2597 continue;
2598
2599 err = mv88e6xxx_port_add_broadcast(chip, port, vid);
2600 if (err)
2601 return err;
2602 }
2603
2604 return 0;
2605 }
2606
2607 struct mv88e6xxx_port_broadcast_sync_ctx {
2608 int port;
2609 bool flood;
2610 };
2611
2612 static int
mv88e6xxx_port_broadcast_sync_vlan(struct mv88e6xxx_chip * chip,const struct mv88e6xxx_vtu_entry * vlan,void * _ctx)2613 mv88e6xxx_port_broadcast_sync_vlan(struct mv88e6xxx_chip *chip,
2614 const struct mv88e6xxx_vtu_entry *vlan,
2615 void *_ctx)
2616 {
2617 struct mv88e6xxx_port_broadcast_sync_ctx *ctx = _ctx;
2618 u8 broadcast[ETH_ALEN];
2619 u8 state;
2620
2621 if (ctx->flood)
2622 state = MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC;
2623 else
2624 state = MV88E6XXX_G1_ATU_DATA_STATE_MC_UNUSED;
2625
2626 eth_broadcast_addr(broadcast);
2627
2628 return mv88e6xxx_port_db_load_purge(chip, ctx->port, broadcast,
2629 vlan->vid, state);
2630 }
2631
mv88e6xxx_port_broadcast_sync(struct mv88e6xxx_chip * chip,int port,bool flood)2632 static int mv88e6xxx_port_broadcast_sync(struct mv88e6xxx_chip *chip, int port,
2633 bool flood)
2634 {
2635 struct mv88e6xxx_port_broadcast_sync_ctx ctx = {
2636 .port = port,
2637 .flood = flood,
2638 };
2639 struct mv88e6xxx_vtu_entry vid0 = {
2640 .vid = 0,
2641 };
2642 int err;
2643
2644 /* Update the port's private database... */
2645 err = mv88e6xxx_port_broadcast_sync_vlan(chip, &vid0, &ctx);
2646 if (err)
2647 return err;
2648
2649 /* ...and the database for all VLANs. */
2650 return mv88e6xxx_vtu_walk(chip, mv88e6xxx_port_broadcast_sync_vlan,
2651 &ctx);
2652 }
2653
mv88e6xxx_port_vlan_join(struct mv88e6xxx_chip * chip,int port,u16 vid,u8 member,bool warn)2654 static int mv88e6xxx_port_vlan_join(struct mv88e6xxx_chip *chip, int port,
2655 u16 vid, u8 member, bool warn)
2656 {
2657 const u8 non_member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER;
2658 struct mv88e6xxx_vtu_entry vlan;
2659 int i, err;
2660
2661 err = mv88e6xxx_vtu_get(chip, vid, &vlan);
2662 if (err)
2663 return err;
2664
2665 if (!vlan.valid) {
2666 memset(&vlan, 0, sizeof(vlan));
2667
2668 if (vid == MV88E6XXX_VID_STANDALONE)
2669 vlan.policy = true;
2670
2671 err = mv88e6xxx_atu_new(chip, &vlan.fid);
2672 if (err)
2673 return err;
2674
2675 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i)
2676 if (i == port)
2677 vlan.member[i] = member;
2678 else
2679 vlan.member[i] = non_member;
2680
2681 vlan.vid = vid;
2682 vlan.valid = true;
2683
2684 err = mv88e6xxx_vtu_loadpurge(chip, &vlan);
2685 if (err)
2686 return err;
2687
2688 err = mv88e6xxx_broadcast_setup(chip, vlan.vid);
2689 if (err)
2690 return err;
2691 } else if (vlan.member[port] != member) {
2692 vlan.member[port] = member;
2693
2694 err = mv88e6xxx_vtu_loadpurge(chip, &vlan);
2695 if (err)
2696 return err;
2697 } else if (warn) {
2698 dev_info(chip->dev, "p%d: already a member of VLAN %d\n",
2699 port, vid);
2700 }
2701
2702 return 0;
2703 }
2704
mv88e6xxx_port_vlan_add(struct dsa_switch * ds,int port,const struct switchdev_obj_port_vlan * vlan,struct netlink_ext_ack * extack)2705 static int mv88e6xxx_port_vlan_add(struct dsa_switch *ds, int port,
2706 const struct switchdev_obj_port_vlan *vlan,
2707 struct netlink_ext_ack *extack)
2708 {
2709 struct mv88e6xxx_chip *chip = ds->priv;
2710 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
2711 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID;
2712 struct mv88e6xxx_port *p = &chip->ports[port];
2713 bool warn;
2714 u8 member;
2715 int err;
2716
2717 if (!vlan->vid)
2718 return 0;
2719
2720 err = mv88e6xxx_port_vlan_prepare(ds, port, vlan);
2721 if (err)
2722 return err;
2723
2724 if (dsa_is_dsa_port(ds, port) || dsa_is_cpu_port(ds, port))
2725 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNMODIFIED;
2726 else if (untagged)
2727 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNTAGGED;
2728 else
2729 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_TAGGED;
2730
2731 /* net/dsa/user.c will call dsa_port_vlan_add() for the affected port
2732 * and then the CPU port. Do not warn for duplicates for the CPU port.
2733 */
2734 warn = !dsa_is_cpu_port(ds, port) && !dsa_is_dsa_port(ds, port);
2735
2736 mv88e6xxx_reg_lock(chip);
2737
2738 err = mv88e6xxx_port_vlan_join(chip, port, vlan->vid, member, warn);
2739 if (err) {
2740 dev_err(ds->dev, "p%d: failed to add VLAN %d%c\n", port,
2741 vlan->vid, untagged ? 'u' : 't');
2742 goto out;
2743 }
2744
2745 if (pvid) {
2746 p->bridge_pvid.vid = vlan->vid;
2747 p->bridge_pvid.valid = true;
2748
2749 err = mv88e6xxx_port_commit_pvid(chip, port);
2750 if (err)
2751 goto out;
2752 } else if (vlan->vid && p->bridge_pvid.vid == vlan->vid) {
2753 /* The old pvid was reinstalled as a non-pvid VLAN */
2754 p->bridge_pvid.valid = false;
2755
2756 err = mv88e6xxx_port_commit_pvid(chip, port);
2757 if (err)
2758 goto out;
2759 }
2760
2761 out:
2762 mv88e6xxx_reg_unlock(chip);
2763
2764 return err;
2765 }
2766
mv88e6xxx_port_vlan_leave(struct mv88e6xxx_chip * chip,int port,u16 vid)2767 static int mv88e6xxx_port_vlan_leave(struct mv88e6xxx_chip *chip,
2768 int port, u16 vid)
2769 {
2770 struct mv88e6xxx_vtu_entry vlan;
2771 int i, err;
2772
2773 if (!vid)
2774 return 0;
2775
2776 err = mv88e6xxx_vtu_get(chip, vid, &vlan);
2777 if (err)
2778 return err;
2779
2780 /* If the VLAN doesn't exist in hardware or the port isn't a member,
2781 * tell switchdev that this VLAN is likely handled in software.
2782 */
2783 if (!vlan.valid ||
2784 vlan.member[port] == MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER)
2785 return -EOPNOTSUPP;
2786
2787 vlan.member[port] = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER;
2788
2789 /* keep the VLAN unless all ports are excluded */
2790 vlan.valid = false;
2791 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
2792 if (vlan.member[i] !=
2793 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER) {
2794 vlan.valid = true;
2795 break;
2796 }
2797 }
2798
2799 err = mv88e6xxx_vtu_loadpurge(chip, &vlan);
2800 if (err)
2801 return err;
2802
2803 if (!vlan.valid) {
2804 err = mv88e6xxx_mst_put(chip, vlan.sid);
2805 if (err)
2806 return err;
2807 }
2808
2809 return mv88e6xxx_g1_atu_remove(chip, vlan.fid, port, false);
2810 }
2811
mv88e6xxx_port_vlan_del(struct dsa_switch * ds,int port,const struct switchdev_obj_port_vlan * vlan)2812 static int mv88e6xxx_port_vlan_del(struct dsa_switch *ds, int port,
2813 const struct switchdev_obj_port_vlan *vlan)
2814 {
2815 struct mv88e6xxx_chip *chip = ds->priv;
2816 struct mv88e6xxx_port *p = &chip->ports[port];
2817 int err = 0;
2818 u16 pvid;
2819
2820 if (!mv88e6xxx_max_vid(chip))
2821 return -EOPNOTSUPP;
2822
2823 /* The ATU removal procedure needs the FID to be mapped in the VTU,
2824 * but FDB deletion runs concurrently with VLAN deletion. Flush the DSA
2825 * switchdev workqueue to ensure that all FDB entries are deleted
2826 * before we remove the VLAN.
2827 */
2828 dsa_flush_workqueue();
2829
2830 mv88e6xxx_reg_lock(chip);
2831
2832 err = mv88e6xxx_port_get_pvid(chip, port, &pvid);
2833 if (err)
2834 goto unlock;
2835
2836 err = mv88e6xxx_port_vlan_leave(chip, port, vlan->vid);
2837 if (err)
2838 goto unlock;
2839
2840 if (vlan->vid == pvid) {
2841 p->bridge_pvid.valid = false;
2842
2843 err = mv88e6xxx_port_commit_pvid(chip, port);
2844 if (err)
2845 goto unlock;
2846 }
2847
2848 unlock:
2849 mv88e6xxx_reg_unlock(chip);
2850
2851 return err;
2852 }
2853
mv88e6xxx_port_vlan_fast_age(struct dsa_switch * ds,int port,u16 vid)2854 static int mv88e6xxx_port_vlan_fast_age(struct dsa_switch *ds, int port, u16 vid)
2855 {
2856 struct mv88e6xxx_chip *chip = ds->priv;
2857 struct mv88e6xxx_vtu_entry vlan;
2858 int err;
2859
2860 mv88e6xxx_reg_lock(chip);
2861
2862 err = mv88e6xxx_vtu_get(chip, vid, &vlan);
2863 if (err)
2864 goto unlock;
2865
2866 err = mv88e6xxx_port_fast_age_fid(chip, port, vlan.fid);
2867
2868 unlock:
2869 mv88e6xxx_reg_unlock(chip);
2870
2871 return err;
2872 }
2873
mv88e6xxx_vlan_msti_set(struct dsa_switch * ds,struct dsa_bridge bridge,const struct switchdev_vlan_msti * msti)2874 static int mv88e6xxx_vlan_msti_set(struct dsa_switch *ds,
2875 struct dsa_bridge bridge,
2876 const struct switchdev_vlan_msti *msti)
2877 {
2878 struct mv88e6xxx_chip *chip = ds->priv;
2879 struct mv88e6xxx_vtu_entry vlan;
2880 u8 old_sid, new_sid;
2881 int err;
2882
2883 if (!mv88e6xxx_has_stu(chip))
2884 return -EOPNOTSUPP;
2885
2886 mv88e6xxx_reg_lock(chip);
2887
2888 err = mv88e6xxx_vtu_get(chip, msti->vid, &vlan);
2889 if (err)
2890 goto unlock;
2891
2892 if (!vlan.valid) {
2893 err = -EINVAL;
2894 goto unlock;
2895 }
2896
2897 old_sid = vlan.sid;
2898
2899 err = mv88e6xxx_mst_get(chip, bridge.dev, msti->msti, &new_sid);
2900 if (err)
2901 goto unlock;
2902
2903 if (new_sid != old_sid) {
2904 vlan.sid = new_sid;
2905
2906 err = mv88e6xxx_vtu_loadpurge(chip, &vlan);
2907 if (err) {
2908 mv88e6xxx_mst_put(chip, new_sid);
2909 goto unlock;
2910 }
2911 }
2912
2913 err = mv88e6xxx_mst_put(chip, old_sid);
2914
2915 unlock:
2916 mv88e6xxx_reg_unlock(chip);
2917 return err;
2918 }
2919
mv88e6xxx_port_fdb_add(struct dsa_switch * ds,int port,const unsigned char * addr,u16 vid,struct dsa_db db)2920 static int mv88e6xxx_port_fdb_add(struct dsa_switch *ds, int port,
2921 const unsigned char *addr, u16 vid,
2922 struct dsa_db db)
2923 {
2924 struct mv88e6xxx_chip *chip = ds->priv;
2925 int err;
2926
2927 mv88e6xxx_reg_lock(chip);
2928 err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid,
2929 MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC);
2930 if (err)
2931 goto out;
2932
2933 if (!mv88e6xxx_port_db_find(chip, addr, vid))
2934 err = -ENOSPC;
2935
2936 out:
2937 mv88e6xxx_reg_unlock(chip);
2938
2939 return err;
2940 }
2941
mv88e6xxx_port_fdb_del(struct dsa_switch * ds,int port,const unsigned char * addr,u16 vid,struct dsa_db db)2942 static int mv88e6xxx_port_fdb_del(struct dsa_switch *ds, int port,
2943 const unsigned char *addr, u16 vid,
2944 struct dsa_db db)
2945 {
2946 struct mv88e6xxx_chip *chip = ds->priv;
2947 int err;
2948
2949 mv88e6xxx_reg_lock(chip);
2950 err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid, 0);
2951 mv88e6xxx_reg_unlock(chip);
2952
2953 return err;
2954 }
2955
mv88e6xxx_port_db_dump_fid(struct mv88e6xxx_chip * chip,u16 fid,u16 vid,int port,dsa_fdb_dump_cb_t * cb,void * data)2956 static int mv88e6xxx_port_db_dump_fid(struct mv88e6xxx_chip *chip,
2957 u16 fid, u16 vid, int port,
2958 dsa_fdb_dump_cb_t *cb, void *data)
2959 {
2960 struct mv88e6xxx_atu_entry addr;
2961 bool is_static;
2962 int err;
2963
2964 addr.state = 0;
2965 eth_broadcast_addr(addr.mac);
2966
2967 do {
2968 err = mv88e6xxx_g1_atu_getnext(chip, fid, &addr);
2969 if (err)
2970 return err;
2971
2972 if (!addr.state)
2973 break;
2974
2975 if (addr.trunk || (addr.portvec & BIT(port)) == 0)
2976 continue;
2977
2978 if (!is_unicast_ether_addr(addr.mac))
2979 continue;
2980
2981 is_static = (addr.state ==
2982 MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC);
2983 err = cb(addr.mac, vid, is_static, data);
2984 if (err)
2985 return err;
2986 } while (!is_broadcast_ether_addr(addr.mac));
2987
2988 return err;
2989 }
2990
2991 struct mv88e6xxx_port_db_dump_vlan_ctx {
2992 int port;
2993 dsa_fdb_dump_cb_t *cb;
2994 void *data;
2995 };
2996
mv88e6xxx_port_db_dump_vlan(struct mv88e6xxx_chip * chip,const struct mv88e6xxx_vtu_entry * entry,void * _data)2997 static int mv88e6xxx_port_db_dump_vlan(struct mv88e6xxx_chip *chip,
2998 const struct mv88e6xxx_vtu_entry *entry,
2999 void *_data)
3000 {
3001 struct mv88e6xxx_port_db_dump_vlan_ctx *ctx = _data;
3002
3003 return mv88e6xxx_port_db_dump_fid(chip, entry->fid, entry->vid,
3004 ctx->port, ctx->cb, ctx->data);
3005 }
3006
mv88e6xxx_port_db_dump(struct mv88e6xxx_chip * chip,int port,dsa_fdb_dump_cb_t * cb,void * data)3007 static int mv88e6xxx_port_db_dump(struct mv88e6xxx_chip *chip, int port,
3008 dsa_fdb_dump_cb_t *cb, void *data)
3009 {
3010 struct mv88e6xxx_port_db_dump_vlan_ctx ctx = {
3011 .port = port,
3012 .cb = cb,
3013 .data = data,
3014 };
3015 u16 fid;
3016 int err;
3017
3018 /* Dump port's default Filtering Information Database (VLAN ID 0) */
3019 err = mv88e6xxx_port_get_fid(chip, port, &fid);
3020 if (err)
3021 return err;
3022
3023 err = mv88e6xxx_port_db_dump_fid(chip, fid, 0, port, cb, data);
3024 if (err)
3025 return err;
3026
3027 return mv88e6xxx_vtu_walk(chip, mv88e6xxx_port_db_dump_vlan, &ctx);
3028 }
3029
mv88e6xxx_port_fdb_dump(struct dsa_switch * ds,int port,dsa_fdb_dump_cb_t * cb,void * data)3030 static int mv88e6xxx_port_fdb_dump(struct dsa_switch *ds, int port,
3031 dsa_fdb_dump_cb_t *cb, void *data)
3032 {
3033 struct mv88e6xxx_chip *chip = ds->priv;
3034 int err;
3035
3036 mv88e6xxx_reg_lock(chip);
3037 err = mv88e6xxx_port_db_dump(chip, port, cb, data);
3038 mv88e6xxx_reg_unlock(chip);
3039
3040 return err;
3041 }
3042
mv88e6xxx_bridge_map(struct mv88e6xxx_chip * chip,struct dsa_bridge bridge)3043 static int mv88e6xxx_bridge_map(struct mv88e6xxx_chip *chip,
3044 struct dsa_bridge bridge)
3045 {
3046 struct dsa_switch *ds = chip->ds;
3047 struct dsa_switch_tree *dst = ds->dst;
3048 struct dsa_port *dp;
3049 int err;
3050
3051 list_for_each_entry(dp, &dst->ports, list) {
3052 if (dsa_port_offloads_bridge(dp, &bridge)) {
3053 if (dp->ds == ds) {
3054 /* This is a local bridge group member,
3055 * remap its Port VLAN Map.
3056 */
3057 err = mv88e6xxx_port_vlan_map(chip, dp->index);
3058 if (err)
3059 return err;
3060 } else {
3061 /* This is an external bridge group member,
3062 * remap its cross-chip Port VLAN Table entry.
3063 */
3064 err = mv88e6xxx_pvt_map(chip, dp->ds->index,
3065 dp->index);
3066 if (err)
3067 return err;
3068 }
3069 }
3070 }
3071
3072 return 0;
3073 }
3074
3075 /* Treat the software bridge as a virtual single-port switch behind the
3076 * CPU and map in the PVT. First dst->last_switch elements are taken by
3077 * physical switches, so start from beyond that range.
3078 */
mv88e6xxx_map_virtual_bridge_to_pvt(struct dsa_switch * ds,unsigned int bridge_num)3079 static int mv88e6xxx_map_virtual_bridge_to_pvt(struct dsa_switch *ds,
3080 unsigned int bridge_num)
3081 {
3082 u8 dev = bridge_num + ds->dst->last_switch;
3083 struct mv88e6xxx_chip *chip = ds->priv;
3084
3085 return mv88e6xxx_pvt_map(chip, dev, 0);
3086 }
3087
mv88e6xxx_port_bridge_join(struct dsa_switch * ds,int port,struct dsa_bridge bridge,bool * tx_fwd_offload,struct netlink_ext_ack * extack)3088 static int mv88e6xxx_port_bridge_join(struct dsa_switch *ds, int port,
3089 struct dsa_bridge bridge,
3090 bool *tx_fwd_offload,
3091 struct netlink_ext_ack *extack)
3092 {
3093 struct mv88e6xxx_chip *chip = ds->priv;
3094 int err;
3095
3096 mv88e6xxx_reg_lock(chip);
3097
3098 err = mv88e6xxx_bridge_map(chip, bridge);
3099 if (err)
3100 goto unlock;
3101
3102 err = mv88e6xxx_port_set_map_da(chip, port, true);
3103 if (err)
3104 goto unlock;
3105
3106 err = mv88e6xxx_port_commit_pvid(chip, port);
3107 if (err)
3108 goto unlock;
3109
3110 if (mv88e6xxx_has_pvt(chip)) {
3111 err = mv88e6xxx_map_virtual_bridge_to_pvt(ds, bridge.num);
3112 if (err)
3113 goto unlock;
3114
3115 *tx_fwd_offload = true;
3116 }
3117
3118 unlock:
3119 mv88e6xxx_reg_unlock(chip);
3120
3121 return err;
3122 }
3123
mv88e6xxx_port_bridge_leave(struct dsa_switch * ds,int port,struct dsa_bridge bridge)3124 static void mv88e6xxx_port_bridge_leave(struct dsa_switch *ds, int port,
3125 struct dsa_bridge bridge)
3126 {
3127 struct mv88e6xxx_chip *chip = ds->priv;
3128 int err;
3129
3130 mv88e6xxx_reg_lock(chip);
3131
3132 if (bridge.tx_fwd_offload &&
3133 mv88e6xxx_map_virtual_bridge_to_pvt(ds, bridge.num))
3134 dev_err(ds->dev, "failed to remap cross-chip Port VLAN\n");
3135
3136 if (mv88e6xxx_bridge_map(chip, bridge) ||
3137 mv88e6xxx_port_vlan_map(chip, port))
3138 dev_err(ds->dev, "failed to remap in-chip Port VLAN\n");
3139
3140 err = mv88e6xxx_port_set_map_da(chip, port, false);
3141 if (err)
3142 dev_err(ds->dev,
3143 "port %d failed to restore map-DA: %pe\n",
3144 port, ERR_PTR(err));
3145
3146 err = mv88e6xxx_port_commit_pvid(chip, port);
3147 if (err)
3148 dev_err(ds->dev,
3149 "port %d failed to restore standalone pvid: %pe\n",
3150 port, ERR_PTR(err));
3151
3152 mv88e6xxx_reg_unlock(chip);
3153 }
3154
mv88e6xxx_crosschip_bridge_join(struct dsa_switch * ds,int tree_index,int sw_index,int port,struct dsa_bridge bridge,struct netlink_ext_ack * extack)3155 static int mv88e6xxx_crosschip_bridge_join(struct dsa_switch *ds,
3156 int tree_index, int sw_index,
3157 int port, struct dsa_bridge bridge,
3158 struct netlink_ext_ack *extack)
3159 {
3160 struct mv88e6xxx_chip *chip = ds->priv;
3161 int err;
3162
3163 if (tree_index != ds->dst->index)
3164 return 0;
3165
3166 mv88e6xxx_reg_lock(chip);
3167 err = mv88e6xxx_pvt_map(chip, sw_index, port);
3168 err = err ? : mv88e6xxx_map_virtual_bridge_to_pvt(ds, bridge.num);
3169 mv88e6xxx_reg_unlock(chip);
3170
3171 return err;
3172 }
3173
mv88e6xxx_crosschip_bridge_leave(struct dsa_switch * ds,int tree_index,int sw_index,int port,struct dsa_bridge bridge)3174 static void mv88e6xxx_crosschip_bridge_leave(struct dsa_switch *ds,
3175 int tree_index, int sw_index,
3176 int port, struct dsa_bridge bridge)
3177 {
3178 struct mv88e6xxx_chip *chip = ds->priv;
3179
3180 if (tree_index != ds->dst->index)
3181 return;
3182
3183 mv88e6xxx_reg_lock(chip);
3184 if (mv88e6xxx_pvt_map(chip, sw_index, port) ||
3185 mv88e6xxx_map_virtual_bridge_to_pvt(ds, bridge.num))
3186 dev_err(ds->dev, "failed to remap cross-chip Port VLAN\n");
3187 mv88e6xxx_reg_unlock(chip);
3188 }
3189
mv88e6xxx_software_reset(struct mv88e6xxx_chip * chip)3190 static int mv88e6xxx_software_reset(struct mv88e6xxx_chip *chip)
3191 {
3192 if (chip->info->ops->reset)
3193 return chip->info->ops->reset(chip);
3194
3195 return 0;
3196 }
3197
mv88e6xxx_hardware_reset(struct mv88e6xxx_chip * chip)3198 static void mv88e6xxx_hardware_reset(struct mv88e6xxx_chip *chip)
3199 {
3200 struct gpio_desc *gpiod = chip->reset;
3201 int err;
3202
3203 /* If there is a GPIO connected to the reset pin, toggle it */
3204 if (gpiod) {
3205 /* If the switch has just been reset and not yet completed
3206 * loading EEPROM, the reset may interrupt the I2C transaction
3207 * mid-byte, causing the first EEPROM read after the reset
3208 * from the wrong location resulting in the switch booting
3209 * to wrong mode and inoperable.
3210 * For this reason, switch families with EEPROM support
3211 * generally wait for EEPROM loads to complete as their pre-
3212 * and post-reset handlers.
3213 */
3214 if (chip->info->ops->hardware_reset_pre) {
3215 err = chip->info->ops->hardware_reset_pre(chip);
3216 if (err)
3217 dev_err(chip->dev, "pre-reset error: %d\n", err);
3218 }
3219
3220 gpiod_set_value_cansleep(gpiod, 1);
3221 usleep_range(10000, 20000);
3222 gpiod_set_value_cansleep(gpiod, 0);
3223 usleep_range(10000, 20000);
3224
3225 if (chip->info->ops->hardware_reset_post) {
3226 err = chip->info->ops->hardware_reset_post(chip);
3227 if (err)
3228 dev_err(chip->dev, "post-reset error: %d\n", err);
3229 }
3230 }
3231 }
3232
mv88e6xxx_disable_ports(struct mv88e6xxx_chip * chip)3233 static int mv88e6xxx_disable_ports(struct mv88e6xxx_chip *chip)
3234 {
3235 int i, err;
3236
3237 /* Set all ports to the Disabled state */
3238 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) {
3239 err = mv88e6xxx_port_set_state(chip, i, BR_STATE_DISABLED);
3240 if (err)
3241 return err;
3242 }
3243
3244 /* Wait for transmit queues to drain,
3245 * i.e. 2ms for a maximum frame to be transmitted at 10 Mbps.
3246 */
3247 usleep_range(2000, 4000);
3248
3249 return 0;
3250 }
3251
mv88e6xxx_switch_reset(struct mv88e6xxx_chip * chip)3252 static int mv88e6xxx_switch_reset(struct mv88e6xxx_chip *chip)
3253 {
3254 int err;
3255
3256 err = mv88e6xxx_disable_ports(chip);
3257 if (err)
3258 return err;
3259
3260 mv88e6xxx_hardware_reset(chip);
3261
3262 return mv88e6xxx_software_reset(chip);
3263 }
3264
mv88e6xxx_set_port_mode(struct mv88e6xxx_chip * chip,int port,enum mv88e6xxx_frame_mode frame,enum mv88e6xxx_egress_mode egress,u16 etype)3265 static int mv88e6xxx_set_port_mode(struct mv88e6xxx_chip *chip, int port,
3266 enum mv88e6xxx_frame_mode frame,
3267 enum mv88e6xxx_egress_mode egress, u16 etype)
3268 {
3269 int err;
3270
3271 if (!chip->info->ops->port_set_frame_mode)
3272 return -EOPNOTSUPP;
3273
3274 err = mv88e6xxx_port_set_egress_mode(chip, port, egress);
3275 if (err)
3276 return err;
3277
3278 err = chip->info->ops->port_set_frame_mode(chip, port, frame);
3279 if (err)
3280 return err;
3281
3282 if (chip->info->ops->port_set_ether_type)
3283 return chip->info->ops->port_set_ether_type(chip, port, etype);
3284
3285 return 0;
3286 }
3287
mv88e6xxx_set_port_mode_normal(struct mv88e6xxx_chip * chip,int port)3288 static int mv88e6xxx_set_port_mode_normal(struct mv88e6xxx_chip *chip, int port)
3289 {
3290 return mv88e6xxx_set_port_mode(chip, port, MV88E6XXX_FRAME_MODE_NORMAL,
3291 MV88E6XXX_EGRESS_MODE_UNMODIFIED,
3292 MV88E6XXX_PORT_ETH_TYPE_DEFAULT);
3293 }
3294
mv88e6xxx_set_port_mode_dsa(struct mv88e6xxx_chip * chip,int port)3295 static int mv88e6xxx_set_port_mode_dsa(struct mv88e6xxx_chip *chip, int port)
3296 {
3297 return mv88e6xxx_set_port_mode(chip, port, MV88E6XXX_FRAME_MODE_DSA,
3298 MV88E6XXX_EGRESS_MODE_UNMODIFIED,
3299 MV88E6XXX_PORT_ETH_TYPE_DEFAULT);
3300 }
3301
mv88e6xxx_set_port_mode_edsa(struct mv88e6xxx_chip * chip,int port)3302 static int mv88e6xxx_set_port_mode_edsa(struct mv88e6xxx_chip *chip, int port)
3303 {
3304 return mv88e6xxx_set_port_mode(chip, port,
3305 MV88E6XXX_FRAME_MODE_ETHERTYPE,
3306 MV88E6XXX_EGRESS_MODE_ETHERTYPE,
3307 ETH_P_EDSA);
3308 }
3309
mv88e6xxx_setup_port_mode(struct mv88e6xxx_chip * chip,int port)3310 static int mv88e6xxx_setup_port_mode(struct mv88e6xxx_chip *chip, int port)
3311 {
3312 if (dsa_is_dsa_port(chip->ds, port))
3313 return mv88e6xxx_set_port_mode_dsa(chip, port);
3314
3315 if (dsa_is_user_port(chip->ds, port))
3316 return mv88e6xxx_set_port_mode_normal(chip, port);
3317
3318 /* Setup CPU port mode depending on its supported tag format */
3319 if (chip->tag_protocol == DSA_TAG_PROTO_DSA)
3320 return mv88e6xxx_set_port_mode_dsa(chip, port);
3321
3322 if (chip->tag_protocol == DSA_TAG_PROTO_EDSA)
3323 return mv88e6xxx_set_port_mode_edsa(chip, port);
3324
3325 return -EINVAL;
3326 }
3327
mv88e6xxx_setup_message_port(struct mv88e6xxx_chip * chip,int port)3328 static int mv88e6xxx_setup_message_port(struct mv88e6xxx_chip *chip, int port)
3329 {
3330 bool message = dsa_is_dsa_port(chip->ds, port);
3331
3332 return mv88e6xxx_port_set_message_port(chip, port, message);
3333 }
3334
mv88e6xxx_setup_egress_floods(struct mv88e6xxx_chip * chip,int port)3335 static int mv88e6xxx_setup_egress_floods(struct mv88e6xxx_chip *chip, int port)
3336 {
3337 int err;
3338
3339 if (chip->info->ops->port_set_ucast_flood) {
3340 err = chip->info->ops->port_set_ucast_flood(chip, port, true);
3341 if (err)
3342 return err;
3343 }
3344 if (chip->info->ops->port_set_mcast_flood) {
3345 err = chip->info->ops->port_set_mcast_flood(chip, port, true);
3346 if (err)
3347 return err;
3348 }
3349
3350 return 0;
3351 }
3352
mv88e6xxx_set_egress_port(struct mv88e6xxx_chip * chip,enum mv88e6xxx_egress_direction direction,int port)3353 static int mv88e6xxx_set_egress_port(struct mv88e6xxx_chip *chip,
3354 enum mv88e6xxx_egress_direction direction,
3355 int port)
3356 {
3357 int err;
3358
3359 if (!chip->info->ops->set_egress_port)
3360 return -EOPNOTSUPP;
3361
3362 err = chip->info->ops->set_egress_port(chip, direction, port);
3363 if (err)
3364 return err;
3365
3366 if (direction == MV88E6XXX_EGRESS_DIR_INGRESS)
3367 chip->ingress_dest_port = port;
3368 else
3369 chip->egress_dest_port = port;
3370
3371 return 0;
3372 }
3373
mv88e6xxx_setup_upstream_port(struct mv88e6xxx_chip * chip,int port)3374 static int mv88e6xxx_setup_upstream_port(struct mv88e6xxx_chip *chip, int port)
3375 {
3376 struct dsa_switch *ds = chip->ds;
3377 int upstream_port;
3378 int err;
3379
3380 upstream_port = dsa_upstream_port(ds, port);
3381 if (chip->info->ops->port_set_upstream_port) {
3382 err = chip->info->ops->port_set_upstream_port(chip, port,
3383 upstream_port);
3384 if (err)
3385 return err;
3386 }
3387
3388 if (port == upstream_port) {
3389 if (chip->info->ops->set_cpu_port) {
3390 err = chip->info->ops->set_cpu_port(chip,
3391 upstream_port);
3392 if (err)
3393 return err;
3394 }
3395
3396 err = mv88e6xxx_set_egress_port(chip,
3397 MV88E6XXX_EGRESS_DIR_INGRESS,
3398 upstream_port);
3399 if (err && err != -EOPNOTSUPP)
3400 return err;
3401
3402 err = mv88e6xxx_set_egress_port(chip,
3403 MV88E6XXX_EGRESS_DIR_EGRESS,
3404 upstream_port);
3405 if (err && err != -EOPNOTSUPP)
3406 return err;
3407 }
3408
3409 return 0;
3410 }
3411
mv88e6xxx_setup_port(struct mv88e6xxx_chip * chip,int port)3412 static int mv88e6xxx_setup_port(struct mv88e6xxx_chip *chip, int port)
3413 {
3414 struct device_node *phy_handle = NULL;
3415 struct dsa_switch *ds = chip->ds;
3416 struct dsa_port *dp;
3417 int tx_amp;
3418 int err;
3419 u16 reg;
3420
3421 chip->ports[port].chip = chip;
3422 chip->ports[port].port = port;
3423
3424 err = mv88e6xxx_port_setup_mac(chip, port, LINK_UNFORCED,
3425 SPEED_UNFORCED, DUPLEX_UNFORCED,
3426 PAUSE_ON, PHY_INTERFACE_MODE_NA);
3427 if (err)
3428 return err;
3429
3430 /* Port Control: disable Drop-on-Unlock, disable Drop-on-Lock,
3431 * disable Header mode, enable IGMP/MLD snooping, disable VLAN
3432 * tunneling, determine priority by looking at 802.1p and IP
3433 * priority fields (IP prio has precedence), and set STP state
3434 * to Forwarding.
3435 *
3436 * If this is the CPU link, use DSA or EDSA tagging depending
3437 * on which tagging mode was configured.
3438 *
3439 * If this is a link to another switch, use DSA tagging mode.
3440 *
3441 * If this is the upstream port for this switch, enable
3442 * forwarding of unknown unicasts and multicasts.
3443 */
3444 reg = MV88E6185_PORT_CTL0_USE_TAG | MV88E6185_PORT_CTL0_USE_IP |
3445 MV88E6XXX_PORT_CTL0_STATE_FORWARDING;
3446 /* Forward any IPv4 IGMP or IPv6 MLD frames received
3447 * by a USER port to the CPU port to allow snooping.
3448 */
3449 if (dsa_is_user_port(ds, port))
3450 reg |= MV88E6XXX_PORT_CTL0_IGMP_MLD_SNOOP;
3451
3452 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg);
3453 if (err)
3454 return err;
3455
3456 err = mv88e6xxx_setup_port_mode(chip, port);
3457 if (err)
3458 return err;
3459
3460 err = mv88e6xxx_setup_egress_floods(chip, port);
3461 if (err)
3462 return err;
3463
3464 /* Port Control 2: don't force a good FCS, set the MTU size to
3465 * 10222 bytes, disable 802.1q tags checking, don't discard
3466 * tagged or untagged frames on this port, skip destination
3467 * address lookup on user ports, disable ARP mirroring and don't
3468 * send a copy of all transmitted/received frames on this port
3469 * to the CPU.
3470 */
3471 err = mv88e6xxx_port_set_map_da(chip, port, !dsa_is_user_port(ds, port));
3472 if (err)
3473 return err;
3474
3475 err = mv88e6xxx_setup_upstream_port(chip, port);
3476 if (err)
3477 return err;
3478
3479 /* On chips that support it, set all downstream DSA ports'
3480 * VLAN policy to TRAP. In combination with loading
3481 * MV88E6XXX_VID_STANDALONE as a policy entry in the VTU, this
3482 * provides a better isolation barrier between standalone
3483 * ports, as the ATU is bypassed on any intermediate switches
3484 * between the incoming port and the CPU.
3485 */
3486 if (dsa_is_downstream_port(ds, port) &&
3487 chip->info->ops->port_set_policy) {
3488 err = chip->info->ops->port_set_policy(chip, port,
3489 MV88E6XXX_POLICY_MAPPING_VTU,
3490 MV88E6XXX_POLICY_ACTION_TRAP);
3491 if (err)
3492 return err;
3493 }
3494
3495 /* User ports start out in standalone mode and 802.1Q is
3496 * therefore disabled. On DSA ports, all valid VIDs are always
3497 * loaded in the VTU - therefore, enable 802.1Q in order to take
3498 * advantage of VLAN policy on chips that supports it.
3499 */
3500 err = mv88e6xxx_port_set_8021q_mode(chip, port,
3501 dsa_is_user_port(ds, port) ?
3502 MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED :
3503 MV88E6XXX_PORT_CTL2_8021Q_MODE_SECURE);
3504 if (err)
3505 return err;
3506
3507 /* Bind MV88E6XXX_VID_STANDALONE to MV88E6XXX_FID_STANDALONE by
3508 * virtue of the fact that mv88e6xxx_atu_new() will pick it as
3509 * the first free FID. This will be used as the private PVID for
3510 * unbridged ports. Shared (DSA and CPU) ports must also be
3511 * members of this VID, in order to trap all frames assigned to
3512 * it to the CPU.
3513 */
3514 err = mv88e6xxx_port_vlan_join(chip, port, MV88E6XXX_VID_STANDALONE,
3515 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNMODIFIED,
3516 false);
3517 if (err)
3518 return err;
3519
3520 /* Associate MV88E6XXX_VID_BRIDGED with MV88E6XXX_FID_BRIDGED in the
3521 * ATU by virtue of the fact that mv88e6xxx_atu_new() will pick it as
3522 * the first free FID after MV88E6XXX_FID_STANDALONE. This will be used
3523 * as the private PVID on ports under a VLAN-unaware bridge.
3524 * Shared (DSA and CPU) ports must also be members of it, to translate
3525 * the VID from the DSA tag into MV88E6XXX_FID_BRIDGED, instead of
3526 * relying on their port default FID.
3527 */
3528 err = mv88e6xxx_port_vlan_join(chip, port, MV88E6XXX_VID_BRIDGED,
3529 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNMODIFIED,
3530 false);
3531 if (err)
3532 return err;
3533
3534 if (chip->info->ops->port_set_jumbo_size) {
3535 err = chip->info->ops->port_set_jumbo_size(chip, port, 10218);
3536 if (err)
3537 return err;
3538 }
3539
3540 /* Port Association Vector: disable automatic address learning
3541 * on all user ports since they start out in standalone
3542 * mode. When joining a bridge, learning will be configured to
3543 * match the bridge port settings. Enable learning on all
3544 * DSA/CPU ports. NOTE: FROM_CPU frames always bypass the
3545 * learning process.
3546 *
3547 * Disable HoldAt1, IntOnAgeOut, LockedPort, IgnoreWrongData,
3548 * and RefreshLocked. I.e. setup standard automatic learning.
3549 */
3550 if (dsa_is_user_port(ds, port))
3551 reg = 0;
3552 else
3553 reg = 1 << port;
3554
3555 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_ASSOC_VECTOR,
3556 reg);
3557 if (err)
3558 return err;
3559
3560 /* Egress rate control 2: disable egress rate control. */
3561 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_EGRESS_RATE_CTL2,
3562 0x0000);
3563 if (err)
3564 return err;
3565
3566 if (chip->info->ops->port_pause_limit) {
3567 err = chip->info->ops->port_pause_limit(chip, port, 0, 0);
3568 if (err)
3569 return err;
3570 }
3571
3572 if (chip->info->ops->port_disable_learn_limit) {
3573 err = chip->info->ops->port_disable_learn_limit(chip, port);
3574 if (err)
3575 return err;
3576 }
3577
3578 if (chip->info->ops->port_disable_pri_override) {
3579 err = chip->info->ops->port_disable_pri_override(chip, port);
3580 if (err)
3581 return err;
3582 }
3583
3584 if (chip->info->ops->port_tag_remap) {
3585 err = chip->info->ops->port_tag_remap(chip, port);
3586 if (err)
3587 return err;
3588 }
3589
3590 if (chip->info->ops->port_egress_rate_limiting) {
3591 err = chip->info->ops->port_egress_rate_limiting(chip, port);
3592 if (err)
3593 return err;
3594 }
3595
3596 if (chip->info->ops->port_setup_message_port) {
3597 err = chip->info->ops->port_setup_message_port(chip, port);
3598 if (err)
3599 return err;
3600 }
3601
3602 if (chip->info->ops->serdes_set_tx_amplitude) {
3603 dp = dsa_to_port(ds, port);
3604 if (dp)
3605 phy_handle = of_parse_phandle(dp->dn, "phy-handle", 0);
3606
3607 if (phy_handle && !of_property_read_u32(phy_handle,
3608 "tx-p2p-microvolt",
3609 &tx_amp))
3610 err = chip->info->ops->serdes_set_tx_amplitude(chip,
3611 port, tx_amp);
3612 if (phy_handle) {
3613 of_node_put(phy_handle);
3614 if (err)
3615 return err;
3616 }
3617 }
3618
3619 /* Port based VLAN map: give each port the same default address
3620 * database, and allow bidirectional communication between the
3621 * CPU and DSA port(s), and the other ports.
3622 */
3623 err = mv88e6xxx_port_set_fid(chip, port, MV88E6XXX_FID_STANDALONE);
3624 if (err)
3625 return err;
3626
3627 err = mv88e6xxx_port_vlan_map(chip, port);
3628 if (err)
3629 return err;
3630
3631 /* Default VLAN ID and priority: don't set a default VLAN
3632 * ID, and set the default packet priority to zero.
3633 */
3634 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_DEFAULT_VLAN, 0);
3635 }
3636
mv88e6xxx_get_max_mtu(struct dsa_switch * ds,int port)3637 static int mv88e6xxx_get_max_mtu(struct dsa_switch *ds, int port)
3638 {
3639 struct mv88e6xxx_chip *chip = ds->priv;
3640
3641 if (chip->info->ops->port_set_jumbo_size)
3642 return 10240 - VLAN_ETH_HLEN - EDSA_HLEN - ETH_FCS_LEN;
3643 else if (chip->info->ops->set_max_frame_size)
3644 return 1632 - VLAN_ETH_HLEN - EDSA_HLEN - ETH_FCS_LEN;
3645 return ETH_DATA_LEN;
3646 }
3647
mv88e6xxx_change_mtu(struct dsa_switch * ds,int port,int new_mtu)3648 static int mv88e6xxx_change_mtu(struct dsa_switch *ds, int port, int new_mtu)
3649 {
3650 struct mv88e6xxx_chip *chip = ds->priv;
3651 int ret = 0;
3652
3653 /* For families where we don't know how to alter the MTU,
3654 * just accept any value up to ETH_DATA_LEN
3655 */
3656 if (!chip->info->ops->port_set_jumbo_size &&
3657 !chip->info->ops->set_max_frame_size) {
3658 if (new_mtu > ETH_DATA_LEN)
3659 return -EINVAL;
3660
3661 return 0;
3662 }
3663
3664 if (dsa_is_dsa_port(ds, port) || dsa_is_cpu_port(ds, port))
3665 new_mtu += EDSA_HLEN;
3666
3667 mv88e6xxx_reg_lock(chip);
3668 if (chip->info->ops->port_set_jumbo_size)
3669 ret = chip->info->ops->port_set_jumbo_size(chip, port, new_mtu);
3670 else if (chip->info->ops->set_max_frame_size &&
3671 dsa_is_cpu_port(ds, port))
3672 ret = chip->info->ops->set_max_frame_size(chip, new_mtu);
3673 mv88e6xxx_reg_unlock(chip);
3674
3675 return ret;
3676 }
3677
mv88e6xxx_set_ageing_time(struct dsa_switch * ds,unsigned int ageing_time)3678 static int mv88e6xxx_set_ageing_time(struct dsa_switch *ds,
3679 unsigned int ageing_time)
3680 {
3681 struct mv88e6xxx_chip *chip = ds->priv;
3682 int err;
3683
3684 mv88e6xxx_reg_lock(chip);
3685 err = mv88e6xxx_g1_atu_set_age_time(chip, ageing_time);
3686 mv88e6xxx_reg_unlock(chip);
3687
3688 return err;
3689 }
3690
mv88e6xxx_stats_setup(struct mv88e6xxx_chip * chip)3691 static int mv88e6xxx_stats_setup(struct mv88e6xxx_chip *chip)
3692 {
3693 int err;
3694
3695 /* Initialize the statistics unit */
3696 if (chip->info->ops->stats_set_histogram) {
3697 err = chip->info->ops->stats_set_histogram(chip);
3698 if (err)
3699 return err;
3700 }
3701
3702 return mv88e6xxx_g1_stats_clear(chip);
3703 }
3704
mv88e6320_setup_errata(struct mv88e6xxx_chip * chip)3705 static int mv88e6320_setup_errata(struct mv88e6xxx_chip *chip)
3706 {
3707 u16 dummy;
3708 int err;
3709
3710 /* Workaround for erratum
3711 * 3.3 RGMII timing may be out of spec when transmit delay is enabled
3712 */
3713 err = mv88e6xxx_port_hidden_write(chip, 0, 0xf, 0x7, 0xe000);
3714 if (err)
3715 return err;
3716
3717 return mv88e6xxx_port_hidden_read(chip, 0, 0xf, 0x7, &dummy);
3718 }
3719
3720 /* Check if the errata has already been applied. */
mv88e6390_setup_errata_applied(struct mv88e6xxx_chip * chip)3721 static bool mv88e6390_setup_errata_applied(struct mv88e6xxx_chip *chip)
3722 {
3723 int port;
3724 int err;
3725 u16 val;
3726
3727 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) {
3728 err = mv88e6xxx_port_hidden_read(chip, 0xf, port, 0, &val);
3729 if (err) {
3730 dev_err(chip->dev,
3731 "Error reading hidden register: %d\n", err);
3732 return false;
3733 }
3734 if (val != 0x01c0)
3735 return false;
3736 }
3737
3738 return true;
3739 }
3740
3741 /* The 6390 copper ports have an errata which require poking magic
3742 * values into undocumented hidden registers and then performing a
3743 * software reset.
3744 */
mv88e6390_setup_errata(struct mv88e6xxx_chip * chip)3745 static int mv88e6390_setup_errata(struct mv88e6xxx_chip *chip)
3746 {
3747 int port;
3748 int err;
3749
3750 if (mv88e6390_setup_errata_applied(chip))
3751 return 0;
3752
3753 /* Set the ports into blocking mode */
3754 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) {
3755 err = mv88e6xxx_port_set_state(chip, port, BR_STATE_DISABLED);
3756 if (err)
3757 return err;
3758 }
3759
3760 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) {
3761 err = mv88e6xxx_port_hidden_write(chip, 0xf, port, 0, 0x01c0);
3762 if (err)
3763 return err;
3764 }
3765
3766 return mv88e6xxx_software_reset(chip);
3767 }
3768
3769 /* prod_id for switch families which do not have a PHY model number */
3770 static const u16 family_prod_id_table[] = {
3771 [MV88E6XXX_FAMILY_6341] = MV88E6XXX_PORT_SWITCH_ID_PROD_6341,
3772 [MV88E6XXX_FAMILY_6390] = MV88E6XXX_PORT_SWITCH_ID_PROD_6390,
3773 [MV88E6XXX_FAMILY_6393] = MV88E6XXX_PORT_SWITCH_ID_PROD_6393X,
3774 };
3775
mv88e6xxx_mdio_read(struct mii_bus * bus,int phy,int reg)3776 static int mv88e6xxx_mdio_read(struct mii_bus *bus, int phy, int reg)
3777 {
3778 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv;
3779 struct mv88e6xxx_chip *chip = mdio_bus->chip;
3780 u16 prod_id;
3781 u16 val;
3782 int err;
3783
3784 if (!chip->info->ops->phy_read)
3785 return -EOPNOTSUPP;
3786
3787 mv88e6xxx_reg_lock(chip);
3788 err = chip->info->ops->phy_read(chip, bus, phy, reg, &val);
3789 mv88e6xxx_reg_unlock(chip);
3790
3791 /* Some internal PHYs don't have a model number. */
3792 if (reg == MII_PHYSID2 && !(val & 0x3f0) &&
3793 chip->info->family < ARRAY_SIZE(family_prod_id_table)) {
3794 prod_id = family_prod_id_table[chip->info->family];
3795 if (prod_id)
3796 val |= prod_id >> 4;
3797 }
3798
3799 return err ? err : val;
3800 }
3801
mv88e6xxx_mdio_read_c45(struct mii_bus * bus,int phy,int devad,int reg)3802 static int mv88e6xxx_mdio_read_c45(struct mii_bus *bus, int phy, int devad,
3803 int reg)
3804 {
3805 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv;
3806 struct mv88e6xxx_chip *chip = mdio_bus->chip;
3807 u16 val;
3808 int err;
3809
3810 if (!chip->info->ops->phy_read_c45)
3811 return -ENODEV;
3812
3813 mv88e6xxx_reg_lock(chip);
3814 err = chip->info->ops->phy_read_c45(chip, bus, phy, devad, reg, &val);
3815 mv88e6xxx_reg_unlock(chip);
3816
3817 return err ? err : val;
3818 }
3819
mv88e6xxx_mdio_write(struct mii_bus * bus,int phy,int reg,u16 val)3820 static int mv88e6xxx_mdio_write(struct mii_bus *bus, int phy, int reg, u16 val)
3821 {
3822 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv;
3823 struct mv88e6xxx_chip *chip = mdio_bus->chip;
3824 int err;
3825
3826 if (!chip->info->ops->phy_write)
3827 return -EOPNOTSUPP;
3828
3829 mv88e6xxx_reg_lock(chip);
3830 err = chip->info->ops->phy_write(chip, bus, phy, reg, val);
3831 mv88e6xxx_reg_unlock(chip);
3832
3833 return err;
3834 }
3835
mv88e6xxx_mdio_write_c45(struct mii_bus * bus,int phy,int devad,int reg,u16 val)3836 static int mv88e6xxx_mdio_write_c45(struct mii_bus *bus, int phy, int devad,
3837 int reg, u16 val)
3838 {
3839 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv;
3840 struct mv88e6xxx_chip *chip = mdio_bus->chip;
3841 int err;
3842
3843 if (!chip->info->ops->phy_write_c45)
3844 return -EOPNOTSUPP;
3845
3846 mv88e6xxx_reg_lock(chip);
3847 err = chip->info->ops->phy_write_c45(chip, bus, phy, devad, reg, val);
3848 mv88e6xxx_reg_unlock(chip);
3849
3850 return err;
3851 }
3852
mv88e6xxx_mdio_register(struct mv88e6xxx_chip * chip,struct device_node * np,bool external)3853 static int mv88e6xxx_mdio_register(struct mv88e6xxx_chip *chip,
3854 struct device_node *np,
3855 bool external)
3856 {
3857 static int index;
3858 struct mv88e6xxx_mdio_bus *mdio_bus;
3859 struct mii_bus *bus;
3860 int err;
3861
3862 if (external) {
3863 mv88e6xxx_reg_lock(chip);
3864 if (chip->info->family == MV88E6XXX_FAMILY_6393)
3865 err = mv88e6393x_g2_scratch_gpio_set_smi(chip, true);
3866 else
3867 err = mv88e6390_g2_scratch_gpio_set_smi(chip, true);
3868 mv88e6xxx_reg_unlock(chip);
3869
3870 if (err)
3871 return err;
3872 }
3873
3874 bus = mdiobus_alloc_size(sizeof(*mdio_bus));
3875 if (!bus)
3876 return -ENOMEM;
3877
3878 mdio_bus = bus->priv;
3879 mdio_bus->bus = bus;
3880 mdio_bus->chip = chip;
3881 INIT_LIST_HEAD(&mdio_bus->list);
3882 mdio_bus->external = external;
3883
3884 if (np) {
3885 bus->name = np->full_name;
3886 snprintf(bus->id, MII_BUS_ID_SIZE, "%pOF", np);
3887 } else {
3888 bus->name = "mv88e6xxx SMI";
3889 snprintf(bus->id, MII_BUS_ID_SIZE, "mv88e6xxx-%d", index++);
3890 }
3891
3892 bus->read = mv88e6xxx_mdio_read;
3893 bus->write = mv88e6xxx_mdio_write;
3894 bus->read_c45 = mv88e6xxx_mdio_read_c45;
3895 bus->write_c45 = mv88e6xxx_mdio_write_c45;
3896 bus->parent = chip->dev;
3897 bus->phy_mask = ~GENMASK(chip->info->phy_base_addr +
3898 mv88e6xxx_num_ports(chip) - 1,
3899 chip->info->phy_base_addr);
3900
3901 if (!external) {
3902 err = mv88e6xxx_g2_irq_mdio_setup(chip, bus);
3903 if (err)
3904 goto out;
3905 }
3906
3907 err = of_mdiobus_register(bus, np);
3908 if (err) {
3909 dev_err(chip->dev, "Cannot register MDIO bus (%d)\n", err);
3910 mv88e6xxx_g2_irq_mdio_free(chip, bus);
3911 goto out;
3912 }
3913
3914 if (external)
3915 list_add_tail(&mdio_bus->list, &chip->mdios);
3916 else
3917 list_add(&mdio_bus->list, &chip->mdios);
3918
3919 return 0;
3920
3921 out:
3922 mdiobus_free(bus);
3923 return err;
3924 }
3925
mv88e6xxx_mdios_unregister(struct mv88e6xxx_chip * chip)3926 static void mv88e6xxx_mdios_unregister(struct mv88e6xxx_chip *chip)
3927
3928 {
3929 struct mv88e6xxx_mdio_bus *mdio_bus, *p;
3930 struct mii_bus *bus;
3931
3932 list_for_each_entry_safe(mdio_bus, p, &chip->mdios, list) {
3933 bus = mdio_bus->bus;
3934
3935 if (!mdio_bus->external)
3936 mv88e6xxx_g2_irq_mdio_free(chip, bus);
3937
3938 mdiobus_unregister(bus);
3939 mdiobus_free(bus);
3940 }
3941 }
3942
mv88e6xxx_mdios_register(struct mv88e6xxx_chip * chip)3943 static int mv88e6xxx_mdios_register(struct mv88e6xxx_chip *chip)
3944 {
3945 struct device_node *np = chip->dev->of_node;
3946 struct device_node *child;
3947 int err;
3948
3949 /* Always register one mdio bus for the internal/default mdio
3950 * bus. This maybe represented in the device tree, but is
3951 * optional.
3952 */
3953 child = of_get_child_by_name(np, "mdio");
3954 err = mv88e6xxx_mdio_register(chip, child, false);
3955 of_node_put(child);
3956 if (err)
3957 return err;
3958
3959 /* Walk the device tree, and see if there are any other nodes
3960 * which say they are compatible with the external mdio
3961 * bus.
3962 */
3963 for_each_available_child_of_node(np, child) {
3964 if (of_device_is_compatible(
3965 child, "marvell,mv88e6xxx-mdio-external")) {
3966 err = mv88e6xxx_mdio_register(chip, child, true);
3967 if (err) {
3968 mv88e6xxx_mdios_unregister(chip);
3969 of_node_put(child);
3970 return err;
3971 }
3972 }
3973 }
3974
3975 return 0;
3976 }
3977
mv88e6xxx_teardown(struct dsa_switch * ds)3978 static void mv88e6xxx_teardown(struct dsa_switch *ds)
3979 {
3980 struct mv88e6xxx_chip *chip = ds->priv;
3981
3982 mv88e6xxx_teardown_devlink_params(ds);
3983 dsa_devlink_resources_unregister(ds);
3984 mv88e6xxx_teardown_devlink_regions_global(ds);
3985 mv88e6xxx_mdios_unregister(chip);
3986 }
3987
mv88e6xxx_setup(struct dsa_switch * ds)3988 static int mv88e6xxx_setup(struct dsa_switch *ds)
3989 {
3990 struct mv88e6xxx_chip *chip = ds->priv;
3991 u8 cmode;
3992 int err;
3993 int i;
3994
3995 err = mv88e6xxx_mdios_register(chip);
3996 if (err)
3997 return err;
3998
3999 chip->ds = ds;
4000 ds->user_mii_bus = mv88e6xxx_default_mdio_bus(chip);
4001
4002 /* Since virtual bridges are mapped in the PVT, the number we support
4003 * depends on the physical switch topology. We need to let DSA figure
4004 * that out and therefore we cannot set this at dsa_register_switch()
4005 * time.
4006 */
4007 if (mv88e6xxx_has_pvt(chip))
4008 ds->max_num_bridges = MV88E6XXX_MAX_PVT_SWITCHES -
4009 ds->dst->last_switch - 1;
4010
4011 mv88e6xxx_reg_lock(chip);
4012
4013 if (chip->info->ops->setup_errata) {
4014 err = chip->info->ops->setup_errata(chip);
4015 if (err)
4016 goto unlock;
4017 }
4018
4019 /* Cache the cmode of each port. */
4020 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) {
4021 if (chip->info->ops->port_get_cmode) {
4022 err = chip->info->ops->port_get_cmode(chip, i, &cmode);
4023 if (err)
4024 goto unlock;
4025
4026 chip->ports[i].cmode = cmode;
4027 }
4028 }
4029
4030 err = mv88e6xxx_vtu_setup(chip);
4031 if (err)
4032 goto unlock;
4033
4034 /* Must be called after mv88e6xxx_vtu_setup (which flushes the
4035 * VTU, thereby also flushing the STU).
4036 */
4037 err = mv88e6xxx_stu_setup(chip);
4038 if (err)
4039 goto unlock;
4040
4041 /* Setup Switch Port Registers */
4042 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) {
4043 if (dsa_is_unused_port(ds, i))
4044 continue;
4045
4046 /* Prevent the use of an invalid port. */
4047 if (mv88e6xxx_is_invalid_port(chip, i)) {
4048 dev_err(chip->dev, "port %d is invalid\n", i);
4049 err = -EINVAL;
4050 goto unlock;
4051 }
4052
4053 err = mv88e6xxx_setup_port(chip, i);
4054 if (err)
4055 goto unlock;
4056 }
4057
4058 err = mv88e6xxx_irl_setup(chip);
4059 if (err)
4060 goto unlock;
4061
4062 err = mv88e6xxx_mac_setup(chip);
4063 if (err)
4064 goto unlock;
4065
4066 err = mv88e6xxx_phy_setup(chip);
4067 if (err)
4068 goto unlock;
4069
4070 err = mv88e6xxx_pvt_setup(chip);
4071 if (err)
4072 goto unlock;
4073
4074 err = mv88e6xxx_atu_setup(chip);
4075 if (err)
4076 goto unlock;
4077
4078 err = mv88e6xxx_broadcast_setup(chip, 0);
4079 if (err)
4080 goto unlock;
4081
4082 err = mv88e6xxx_pot_setup(chip);
4083 if (err)
4084 goto unlock;
4085
4086 err = mv88e6xxx_rmu_setup(chip);
4087 if (err)
4088 goto unlock;
4089
4090 err = mv88e6xxx_rsvd2cpu_setup(chip);
4091 if (err)
4092 goto unlock;
4093
4094 err = mv88e6xxx_trunk_setup(chip);
4095 if (err)
4096 goto unlock;
4097
4098 err = mv88e6xxx_devmap_setup(chip);
4099 if (err)
4100 goto unlock;
4101
4102 err = mv88e6xxx_pri_setup(chip);
4103 if (err)
4104 goto unlock;
4105
4106 /* Setup PTP Hardware Clock and timestamping */
4107 if (chip->info->ptp_support) {
4108 err = mv88e6xxx_ptp_setup(chip);
4109 if (err)
4110 goto unlock;
4111
4112 err = mv88e6xxx_hwtstamp_setup(chip);
4113 if (err)
4114 goto unlock;
4115 }
4116
4117 err = mv88e6xxx_stats_setup(chip);
4118 if (err)
4119 goto unlock;
4120
4121 unlock:
4122 mv88e6xxx_reg_unlock(chip);
4123
4124 if (err)
4125 goto out_mdios;
4126
4127 /* Have to be called without holding the register lock, since
4128 * they take the devlink lock, and we later take the locks in
4129 * the reverse order when getting/setting parameters or
4130 * resource occupancy.
4131 */
4132 err = mv88e6xxx_setup_devlink_resources(ds);
4133 if (err)
4134 goto out_mdios;
4135
4136 err = mv88e6xxx_setup_devlink_params(ds);
4137 if (err)
4138 goto out_resources;
4139
4140 err = mv88e6xxx_setup_devlink_regions_global(ds);
4141 if (err)
4142 goto out_params;
4143
4144 return 0;
4145
4146 out_params:
4147 mv88e6xxx_teardown_devlink_params(ds);
4148 out_resources:
4149 dsa_devlink_resources_unregister(ds);
4150 out_mdios:
4151 mv88e6xxx_mdios_unregister(chip);
4152
4153 return err;
4154 }
4155
mv88e6xxx_port_setup(struct dsa_switch * ds,int port)4156 static int mv88e6xxx_port_setup(struct dsa_switch *ds, int port)
4157 {
4158 struct mv88e6xxx_chip *chip = ds->priv;
4159 int err;
4160
4161 if (chip->info->ops->pcs_ops &&
4162 chip->info->ops->pcs_ops->pcs_init) {
4163 err = chip->info->ops->pcs_ops->pcs_init(chip, port);
4164 if (err)
4165 return err;
4166 }
4167
4168 return mv88e6xxx_setup_devlink_regions_port(ds, port);
4169 }
4170
mv88e6xxx_port_teardown(struct dsa_switch * ds,int port)4171 static void mv88e6xxx_port_teardown(struct dsa_switch *ds, int port)
4172 {
4173 struct mv88e6xxx_chip *chip = ds->priv;
4174
4175 mv88e6xxx_teardown_devlink_regions_port(ds, port);
4176
4177 if (chip->info->ops->pcs_ops &&
4178 chip->info->ops->pcs_ops->pcs_teardown)
4179 chip->info->ops->pcs_ops->pcs_teardown(chip, port);
4180 }
4181
mv88e6xxx_get_eeprom_len(struct dsa_switch * ds)4182 static int mv88e6xxx_get_eeprom_len(struct dsa_switch *ds)
4183 {
4184 struct mv88e6xxx_chip *chip = ds->priv;
4185
4186 return chip->eeprom_len;
4187 }
4188
mv88e6xxx_get_eeprom(struct dsa_switch * ds,struct ethtool_eeprom * eeprom,u8 * data)4189 static int mv88e6xxx_get_eeprom(struct dsa_switch *ds,
4190 struct ethtool_eeprom *eeprom, u8 *data)
4191 {
4192 struct mv88e6xxx_chip *chip = ds->priv;
4193 int err;
4194
4195 if (!chip->info->ops->get_eeprom)
4196 return -EOPNOTSUPP;
4197
4198 mv88e6xxx_reg_lock(chip);
4199 err = chip->info->ops->get_eeprom(chip, eeprom, data);
4200 mv88e6xxx_reg_unlock(chip);
4201
4202 if (err)
4203 return err;
4204
4205 eeprom->magic = 0xc3ec4951;
4206
4207 return 0;
4208 }
4209
mv88e6xxx_set_eeprom(struct dsa_switch * ds,struct ethtool_eeprom * eeprom,u8 * data)4210 static int mv88e6xxx_set_eeprom(struct dsa_switch *ds,
4211 struct ethtool_eeprom *eeprom, u8 *data)
4212 {
4213 struct mv88e6xxx_chip *chip = ds->priv;
4214 int err;
4215
4216 if (!chip->info->ops->set_eeprom)
4217 return -EOPNOTSUPP;
4218
4219 if (eeprom->magic != 0xc3ec4951)
4220 return -EINVAL;
4221
4222 mv88e6xxx_reg_lock(chip);
4223 err = chip->info->ops->set_eeprom(chip, eeprom, data);
4224 mv88e6xxx_reg_unlock(chip);
4225
4226 return err;
4227 }
4228
4229 static const struct mv88e6xxx_ops mv88e6085_ops = {
4230 /* MV88E6XXX_FAMILY_6097 */
4231 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4232 .ip_pri_map = mv88e6085_g1_ip_pri_map,
4233 .irl_init_all = mv88e6352_g2_irl_init_all,
4234 .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
4235 .phy_read = mv88e6185_phy_ppu_read,
4236 .phy_write = mv88e6185_phy_ppu_write,
4237 .port_set_link = mv88e6xxx_port_set_link,
4238 .port_sync_link = mv88e6xxx_port_sync_link,
4239 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
4240 .port_tag_remap = mv88e6095_port_tag_remap,
4241 .port_set_policy = mv88e6352_port_set_policy,
4242 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4243 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4244 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
4245 .port_set_ether_type = mv88e6351_port_set_ether_type,
4246 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
4247 .port_pause_limit = mv88e6097_port_pause_limit,
4248 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4249 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4250 .port_get_cmode = mv88e6185_port_get_cmode,
4251 .port_setup_message_port = mv88e6xxx_setup_message_port,
4252 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
4253 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4254 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
4255 .stats_get_strings = mv88e6095_stats_get_strings,
4256 .stats_get_stat = mv88e6095_stats_get_stat,
4257 .set_cpu_port = mv88e6095_g1_set_cpu_port,
4258 .set_egress_port = mv88e6095_g1_set_egress_port,
4259 .watchdog_ops = &mv88e6097_watchdog_ops,
4260 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
4261 .pot_clear = mv88e6xxx_g2_pot_clear,
4262 .ppu_enable = mv88e6185_g1_ppu_enable,
4263 .ppu_disable = mv88e6185_g1_ppu_disable,
4264 .reset = mv88e6185_g1_reset,
4265 .rmu_disable = mv88e6085_g1_rmu_disable,
4266 .vtu_getnext = mv88e6352_g1_vtu_getnext,
4267 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
4268 .stu_getnext = mv88e6352_g1_stu_getnext,
4269 .stu_loadpurge = mv88e6352_g1_stu_loadpurge,
4270 .phylink_get_caps = mv88e6185_phylink_get_caps,
4271 .set_max_frame_size = mv88e6185_g1_set_max_frame_size,
4272 };
4273
4274 static const struct mv88e6xxx_ops mv88e6095_ops = {
4275 /* MV88E6XXX_FAMILY_6095 */
4276 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4277 .ip_pri_map = mv88e6085_g1_ip_pri_map,
4278 .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
4279 .phy_read = mv88e6185_phy_ppu_read,
4280 .phy_write = mv88e6185_phy_ppu_write,
4281 .port_set_link = mv88e6xxx_port_set_link,
4282 .port_sync_link = mv88e6185_port_sync_link,
4283 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
4284 .port_set_frame_mode = mv88e6085_port_set_frame_mode,
4285 .port_set_ucast_flood = mv88e6185_port_set_forward_unknown,
4286 .port_set_mcast_flood = mv88e6185_port_set_default_forward,
4287 .port_set_upstream_port = mv88e6095_port_set_upstream_port,
4288 .port_get_cmode = mv88e6185_port_get_cmode,
4289 .port_setup_message_port = mv88e6xxx_setup_message_port,
4290 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
4291 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4292 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
4293 .stats_get_strings = mv88e6095_stats_get_strings,
4294 .stats_get_stat = mv88e6095_stats_get_stat,
4295 .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu,
4296 .ppu_enable = mv88e6185_g1_ppu_enable,
4297 .ppu_disable = mv88e6185_g1_ppu_disable,
4298 .reset = mv88e6185_g1_reset,
4299 .vtu_getnext = mv88e6185_g1_vtu_getnext,
4300 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
4301 .phylink_get_caps = mv88e6095_phylink_get_caps,
4302 .pcs_ops = &mv88e6185_pcs_ops,
4303 .set_max_frame_size = mv88e6185_g1_set_max_frame_size,
4304 };
4305
4306 static const struct mv88e6xxx_ops mv88e6097_ops = {
4307 /* MV88E6XXX_FAMILY_6097 */
4308 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4309 .ip_pri_map = mv88e6085_g1_ip_pri_map,
4310 .irl_init_all = mv88e6352_g2_irl_init_all,
4311 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4312 .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
4313 .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
4314 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
4315 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
4316 .port_set_link = mv88e6xxx_port_set_link,
4317 .port_sync_link = mv88e6185_port_sync_link,
4318 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
4319 .port_tag_remap = mv88e6095_port_tag_remap,
4320 .port_set_policy = mv88e6352_port_set_policy,
4321 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4322 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4323 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
4324 .port_set_ether_type = mv88e6351_port_set_ether_type,
4325 .port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting,
4326 .port_pause_limit = mv88e6097_port_pause_limit,
4327 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4328 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4329 .port_get_cmode = mv88e6185_port_get_cmode,
4330 .port_setup_message_port = mv88e6xxx_setup_message_port,
4331 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
4332 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4333 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
4334 .stats_get_strings = mv88e6095_stats_get_strings,
4335 .stats_get_stat = mv88e6095_stats_get_stat,
4336 .set_cpu_port = mv88e6095_g1_set_cpu_port,
4337 .set_egress_port = mv88e6095_g1_set_egress_port,
4338 .watchdog_ops = &mv88e6097_watchdog_ops,
4339 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
4340 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
4341 .pot_clear = mv88e6xxx_g2_pot_clear,
4342 .reset = mv88e6352_g1_reset,
4343 .rmu_disable = mv88e6085_g1_rmu_disable,
4344 .vtu_getnext = mv88e6352_g1_vtu_getnext,
4345 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
4346 .phylink_get_caps = mv88e6095_phylink_get_caps,
4347 .pcs_ops = &mv88e6185_pcs_ops,
4348 .stu_getnext = mv88e6352_g1_stu_getnext,
4349 .stu_loadpurge = mv88e6352_g1_stu_loadpurge,
4350 .set_max_frame_size = mv88e6185_g1_set_max_frame_size,
4351 };
4352
4353 static const struct mv88e6xxx_ops mv88e6123_ops = {
4354 /* MV88E6XXX_FAMILY_6165 */
4355 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4356 .ip_pri_map = mv88e6085_g1_ip_pri_map,
4357 .irl_init_all = mv88e6352_g2_irl_init_all,
4358 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4359 .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
4360 .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
4361 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
4362 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
4363 .port_set_link = mv88e6xxx_port_set_link,
4364 .port_sync_link = mv88e6xxx_port_sync_link,
4365 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
4366 .port_set_frame_mode = mv88e6085_port_set_frame_mode,
4367 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4368 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
4369 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4370 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4371 .port_get_cmode = mv88e6185_port_get_cmode,
4372 .port_setup_message_port = mv88e6xxx_setup_message_port,
4373 .stats_snapshot = mv88e6320_g1_stats_snapshot,
4374 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4375 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
4376 .stats_get_strings = mv88e6095_stats_get_strings,
4377 .stats_get_stat = mv88e6095_stats_get_stat,
4378 .set_cpu_port = mv88e6095_g1_set_cpu_port,
4379 .set_egress_port = mv88e6095_g1_set_egress_port,
4380 .watchdog_ops = &mv88e6097_watchdog_ops,
4381 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
4382 .pot_clear = mv88e6xxx_g2_pot_clear,
4383 .reset = mv88e6352_g1_reset,
4384 .atu_get_hash = mv88e6165_g1_atu_get_hash,
4385 .atu_set_hash = mv88e6165_g1_atu_set_hash,
4386 .vtu_getnext = mv88e6352_g1_vtu_getnext,
4387 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
4388 .stu_getnext = mv88e6352_g1_stu_getnext,
4389 .stu_loadpurge = mv88e6352_g1_stu_loadpurge,
4390 .phylink_get_caps = mv88e6185_phylink_get_caps,
4391 .set_max_frame_size = mv88e6185_g1_set_max_frame_size,
4392 };
4393
4394 static const struct mv88e6xxx_ops mv88e6131_ops = {
4395 /* MV88E6XXX_FAMILY_6185 */
4396 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4397 .ip_pri_map = mv88e6085_g1_ip_pri_map,
4398 .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
4399 .phy_read = mv88e6185_phy_ppu_read,
4400 .phy_write = mv88e6185_phy_ppu_write,
4401 .port_set_link = mv88e6xxx_port_set_link,
4402 .port_sync_link = mv88e6xxx_port_sync_link,
4403 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
4404 .port_tag_remap = mv88e6095_port_tag_remap,
4405 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4406 .port_set_ucast_flood = mv88e6185_port_set_forward_unknown,
4407 .port_set_mcast_flood = mv88e6185_port_set_default_forward,
4408 .port_set_ether_type = mv88e6351_port_set_ether_type,
4409 .port_set_upstream_port = mv88e6095_port_set_upstream_port,
4410 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
4411 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
4412 .port_pause_limit = mv88e6097_port_pause_limit,
4413 .port_set_pause = mv88e6185_port_set_pause,
4414 .port_get_cmode = mv88e6185_port_get_cmode,
4415 .port_setup_message_port = mv88e6xxx_setup_message_port,
4416 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
4417 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4418 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
4419 .stats_get_strings = mv88e6095_stats_get_strings,
4420 .stats_get_stat = mv88e6095_stats_get_stat,
4421 .set_cpu_port = mv88e6095_g1_set_cpu_port,
4422 .set_egress_port = mv88e6095_g1_set_egress_port,
4423 .watchdog_ops = &mv88e6097_watchdog_ops,
4424 .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu,
4425 .ppu_enable = mv88e6185_g1_ppu_enable,
4426 .set_cascade_port = mv88e6185_g1_set_cascade_port,
4427 .ppu_disable = mv88e6185_g1_ppu_disable,
4428 .reset = mv88e6185_g1_reset,
4429 .vtu_getnext = mv88e6185_g1_vtu_getnext,
4430 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
4431 .phylink_get_caps = mv88e6185_phylink_get_caps,
4432 };
4433
4434 static const struct mv88e6xxx_ops mv88e6141_ops = {
4435 /* MV88E6XXX_FAMILY_6341 */
4436 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4437 .ip_pri_map = mv88e6085_g1_ip_pri_map,
4438 .irl_init_all = mv88e6352_g2_irl_init_all,
4439 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
4440 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
4441 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4442 .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
4443 .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
4444 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
4445 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
4446 .port_set_link = mv88e6xxx_port_set_link,
4447 .port_sync_link = mv88e6xxx_port_sync_link,
4448 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
4449 .port_set_speed_duplex = mv88e6341_port_set_speed_duplex,
4450 .port_max_speed_mode = mv88e6341_port_max_speed_mode,
4451 .port_tag_remap = mv88e6095_port_tag_remap,
4452 .port_set_policy = mv88e6352_port_set_policy,
4453 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4454 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4455 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
4456 .port_set_ether_type = mv88e6351_port_set_ether_type,
4457 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
4458 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
4459 .port_pause_limit = mv88e6097_port_pause_limit,
4460 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4461 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4462 .port_get_cmode = mv88e6352_port_get_cmode,
4463 .port_set_cmode = mv88e6341_port_set_cmode,
4464 .port_setup_message_port = mv88e6xxx_setup_message_port,
4465 .stats_snapshot = mv88e6390_g1_stats_snapshot,
4466 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
4467 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
4468 .stats_get_strings = mv88e6320_stats_get_strings,
4469 .stats_get_stat = mv88e6390_stats_get_stat,
4470 .set_cpu_port = mv88e6390_g1_set_cpu_port,
4471 .set_egress_port = mv88e6390_g1_set_egress_port,
4472 .watchdog_ops = &mv88e6390_watchdog_ops,
4473 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
4474 .pot_clear = mv88e6xxx_g2_pot_clear,
4475 .hardware_reset_pre = mv88e6xxx_g2_eeprom_wait,
4476 .hardware_reset_post = mv88e6xxx_g2_eeprom_wait,
4477 .reset = mv88e6352_g1_reset,
4478 .rmu_disable = mv88e6390_g1_rmu_disable,
4479 .atu_get_hash = mv88e6165_g1_atu_get_hash,
4480 .atu_set_hash = mv88e6165_g1_atu_set_hash,
4481 .vtu_getnext = mv88e6352_g1_vtu_getnext,
4482 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
4483 .stu_getnext = mv88e6352_g1_stu_getnext,
4484 .stu_loadpurge = mv88e6352_g1_stu_loadpurge,
4485 .serdes_get_lane = mv88e6341_serdes_get_lane,
4486 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
4487 .gpio_ops = &mv88e6352_gpio_ops,
4488 .serdes_get_sset_count = mv88e6390_serdes_get_sset_count,
4489 .serdes_get_strings = mv88e6390_serdes_get_strings,
4490 .serdes_get_stats = mv88e6390_serdes_get_stats,
4491 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len,
4492 .serdes_get_regs = mv88e6390_serdes_get_regs,
4493 .phylink_get_caps = mv88e6341_phylink_get_caps,
4494 .pcs_ops = &mv88e6390_pcs_ops,
4495 };
4496
4497 static const struct mv88e6xxx_ops mv88e6161_ops = {
4498 /* MV88E6XXX_FAMILY_6165 */
4499 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4500 .ip_pri_map = mv88e6085_g1_ip_pri_map,
4501 .irl_init_all = mv88e6352_g2_irl_init_all,
4502 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4503 .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
4504 .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
4505 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
4506 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
4507 .port_set_link = mv88e6xxx_port_set_link,
4508 .port_sync_link = mv88e6xxx_port_sync_link,
4509 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
4510 .port_tag_remap = mv88e6095_port_tag_remap,
4511 .port_set_policy = mv88e6352_port_set_policy,
4512 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4513 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4514 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
4515 .port_set_ether_type = mv88e6351_port_set_ether_type,
4516 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
4517 .port_pause_limit = mv88e6097_port_pause_limit,
4518 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4519 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4520 .port_get_cmode = mv88e6185_port_get_cmode,
4521 .port_setup_message_port = mv88e6xxx_setup_message_port,
4522 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
4523 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4524 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
4525 .stats_get_strings = mv88e6095_stats_get_strings,
4526 .stats_get_stat = mv88e6095_stats_get_stat,
4527 .set_cpu_port = mv88e6095_g1_set_cpu_port,
4528 .set_egress_port = mv88e6095_g1_set_egress_port,
4529 .watchdog_ops = &mv88e6097_watchdog_ops,
4530 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
4531 .pot_clear = mv88e6xxx_g2_pot_clear,
4532 .reset = mv88e6352_g1_reset,
4533 .atu_get_hash = mv88e6165_g1_atu_get_hash,
4534 .atu_set_hash = mv88e6165_g1_atu_set_hash,
4535 .vtu_getnext = mv88e6352_g1_vtu_getnext,
4536 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
4537 .stu_getnext = mv88e6352_g1_stu_getnext,
4538 .stu_loadpurge = mv88e6352_g1_stu_loadpurge,
4539 .avb_ops = &mv88e6165_avb_ops,
4540 .ptp_ops = &mv88e6165_ptp_ops,
4541 .phylink_get_caps = mv88e6185_phylink_get_caps,
4542 .set_max_frame_size = mv88e6185_g1_set_max_frame_size,
4543 };
4544
4545 static const struct mv88e6xxx_ops mv88e6165_ops = {
4546 /* MV88E6XXX_FAMILY_6165 */
4547 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4548 .ip_pri_map = mv88e6085_g1_ip_pri_map,
4549 .irl_init_all = mv88e6352_g2_irl_init_all,
4550 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4551 .phy_read = mv88e6165_phy_read,
4552 .phy_write = mv88e6165_phy_write,
4553 .port_set_link = mv88e6xxx_port_set_link,
4554 .port_sync_link = mv88e6xxx_port_sync_link,
4555 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
4556 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4557 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4558 .port_get_cmode = mv88e6185_port_get_cmode,
4559 .port_setup_message_port = mv88e6xxx_setup_message_port,
4560 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
4561 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4562 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
4563 .stats_get_strings = mv88e6095_stats_get_strings,
4564 .stats_get_stat = mv88e6095_stats_get_stat,
4565 .set_cpu_port = mv88e6095_g1_set_cpu_port,
4566 .set_egress_port = mv88e6095_g1_set_egress_port,
4567 .watchdog_ops = &mv88e6097_watchdog_ops,
4568 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
4569 .pot_clear = mv88e6xxx_g2_pot_clear,
4570 .reset = mv88e6352_g1_reset,
4571 .atu_get_hash = mv88e6165_g1_atu_get_hash,
4572 .atu_set_hash = mv88e6165_g1_atu_set_hash,
4573 .vtu_getnext = mv88e6352_g1_vtu_getnext,
4574 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
4575 .stu_getnext = mv88e6352_g1_stu_getnext,
4576 .stu_loadpurge = mv88e6352_g1_stu_loadpurge,
4577 .avb_ops = &mv88e6165_avb_ops,
4578 .ptp_ops = &mv88e6165_ptp_ops,
4579 .phylink_get_caps = mv88e6185_phylink_get_caps,
4580 };
4581
4582 static const struct mv88e6xxx_ops mv88e6171_ops = {
4583 /* MV88E6XXX_FAMILY_6351 */
4584 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4585 .ip_pri_map = mv88e6085_g1_ip_pri_map,
4586 .irl_init_all = mv88e6352_g2_irl_init_all,
4587 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4588 .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
4589 .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
4590 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
4591 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
4592 .port_set_link = mv88e6xxx_port_set_link,
4593 .port_sync_link = mv88e6xxx_port_sync_link,
4594 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
4595 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
4596 .port_tag_remap = mv88e6095_port_tag_remap,
4597 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4598 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4599 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
4600 .port_set_ether_type = mv88e6351_port_set_ether_type,
4601 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
4602 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
4603 .port_pause_limit = mv88e6097_port_pause_limit,
4604 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4605 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4606 .port_get_cmode = mv88e6352_port_get_cmode,
4607 .port_setup_message_port = mv88e6xxx_setup_message_port,
4608 .stats_snapshot = mv88e6320_g1_stats_snapshot,
4609 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4610 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
4611 .stats_get_strings = mv88e6095_stats_get_strings,
4612 .stats_get_stat = mv88e6095_stats_get_stat,
4613 .set_cpu_port = mv88e6095_g1_set_cpu_port,
4614 .set_egress_port = mv88e6095_g1_set_egress_port,
4615 .watchdog_ops = &mv88e6097_watchdog_ops,
4616 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
4617 .pot_clear = mv88e6xxx_g2_pot_clear,
4618 .reset = mv88e6352_g1_reset,
4619 .atu_get_hash = mv88e6165_g1_atu_get_hash,
4620 .atu_set_hash = mv88e6165_g1_atu_set_hash,
4621 .vtu_getnext = mv88e6352_g1_vtu_getnext,
4622 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
4623 .stu_getnext = mv88e6352_g1_stu_getnext,
4624 .stu_loadpurge = mv88e6352_g1_stu_loadpurge,
4625 .phylink_get_caps = mv88e6351_phylink_get_caps,
4626 };
4627
4628 static const struct mv88e6xxx_ops mv88e6172_ops = {
4629 /* MV88E6XXX_FAMILY_6352 */
4630 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4631 .ip_pri_map = mv88e6085_g1_ip_pri_map,
4632 .irl_init_all = mv88e6352_g2_irl_init_all,
4633 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
4634 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
4635 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4636 .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
4637 .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
4638 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
4639 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
4640 .port_set_link = mv88e6xxx_port_set_link,
4641 .port_sync_link = mv88e6xxx_port_sync_link,
4642 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
4643 .port_set_speed_duplex = mv88e6352_port_set_speed_duplex,
4644 .port_tag_remap = mv88e6095_port_tag_remap,
4645 .port_set_policy = mv88e6352_port_set_policy,
4646 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4647 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4648 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
4649 .port_set_ether_type = mv88e6351_port_set_ether_type,
4650 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
4651 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
4652 .port_pause_limit = mv88e6097_port_pause_limit,
4653 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4654 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4655 .port_get_cmode = mv88e6352_port_get_cmode,
4656 .port_setup_message_port = mv88e6xxx_setup_message_port,
4657 .stats_snapshot = mv88e6320_g1_stats_snapshot,
4658 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4659 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
4660 .stats_get_strings = mv88e6095_stats_get_strings,
4661 .stats_get_stat = mv88e6095_stats_get_stat,
4662 .set_cpu_port = mv88e6095_g1_set_cpu_port,
4663 .set_egress_port = mv88e6095_g1_set_egress_port,
4664 .watchdog_ops = &mv88e6097_watchdog_ops,
4665 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
4666 .pot_clear = mv88e6xxx_g2_pot_clear,
4667 .hardware_reset_pre = mv88e6xxx_g2_eeprom_wait,
4668 .hardware_reset_post = mv88e6xxx_g2_eeprom_wait,
4669 .reset = mv88e6352_g1_reset,
4670 .rmu_disable = mv88e6352_g1_rmu_disable,
4671 .atu_get_hash = mv88e6165_g1_atu_get_hash,
4672 .atu_set_hash = mv88e6165_g1_atu_set_hash,
4673 .vtu_getnext = mv88e6352_g1_vtu_getnext,
4674 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
4675 .stu_getnext = mv88e6352_g1_stu_getnext,
4676 .stu_loadpurge = mv88e6352_g1_stu_loadpurge,
4677 .serdes_get_regs_len = mv88e6352_serdes_get_regs_len,
4678 .serdes_get_regs = mv88e6352_serdes_get_regs,
4679 .gpio_ops = &mv88e6352_gpio_ops,
4680 .phylink_get_caps = mv88e6352_phylink_get_caps,
4681 .pcs_ops = &mv88e6352_pcs_ops,
4682 };
4683
4684 static const struct mv88e6xxx_ops mv88e6175_ops = {
4685 /* MV88E6XXX_FAMILY_6351 */
4686 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4687 .ip_pri_map = mv88e6085_g1_ip_pri_map,
4688 .irl_init_all = mv88e6352_g2_irl_init_all,
4689 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4690 .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
4691 .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
4692 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
4693 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
4694 .port_set_link = mv88e6xxx_port_set_link,
4695 .port_sync_link = mv88e6xxx_port_sync_link,
4696 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
4697 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
4698 .port_tag_remap = mv88e6095_port_tag_remap,
4699 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4700 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4701 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
4702 .port_set_ether_type = mv88e6351_port_set_ether_type,
4703 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
4704 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
4705 .port_pause_limit = mv88e6097_port_pause_limit,
4706 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4707 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4708 .port_get_cmode = mv88e6352_port_get_cmode,
4709 .port_setup_message_port = mv88e6xxx_setup_message_port,
4710 .stats_snapshot = mv88e6320_g1_stats_snapshot,
4711 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4712 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
4713 .stats_get_strings = mv88e6095_stats_get_strings,
4714 .stats_get_stat = mv88e6095_stats_get_stat,
4715 .set_cpu_port = mv88e6095_g1_set_cpu_port,
4716 .set_egress_port = mv88e6095_g1_set_egress_port,
4717 .watchdog_ops = &mv88e6097_watchdog_ops,
4718 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
4719 .pot_clear = mv88e6xxx_g2_pot_clear,
4720 .reset = mv88e6352_g1_reset,
4721 .atu_get_hash = mv88e6165_g1_atu_get_hash,
4722 .atu_set_hash = mv88e6165_g1_atu_set_hash,
4723 .vtu_getnext = mv88e6352_g1_vtu_getnext,
4724 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
4725 .stu_getnext = mv88e6352_g1_stu_getnext,
4726 .stu_loadpurge = mv88e6352_g1_stu_loadpurge,
4727 .phylink_get_caps = mv88e6351_phylink_get_caps,
4728 };
4729
4730 static const struct mv88e6xxx_ops mv88e6176_ops = {
4731 /* MV88E6XXX_FAMILY_6352 */
4732 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4733 .ip_pri_map = mv88e6085_g1_ip_pri_map,
4734 .irl_init_all = mv88e6352_g2_irl_init_all,
4735 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
4736 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
4737 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4738 .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
4739 .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
4740 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
4741 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
4742 .port_set_link = mv88e6xxx_port_set_link,
4743 .port_sync_link = mv88e6xxx_port_sync_link,
4744 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
4745 .port_set_speed_duplex = mv88e6352_port_set_speed_duplex,
4746 .port_tag_remap = mv88e6095_port_tag_remap,
4747 .port_set_policy = mv88e6352_port_set_policy,
4748 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4749 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4750 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
4751 .port_set_ether_type = mv88e6351_port_set_ether_type,
4752 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
4753 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
4754 .port_pause_limit = mv88e6097_port_pause_limit,
4755 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4756 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4757 .port_get_cmode = mv88e6352_port_get_cmode,
4758 .port_setup_message_port = mv88e6xxx_setup_message_port,
4759 .stats_snapshot = mv88e6320_g1_stats_snapshot,
4760 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4761 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
4762 .stats_get_strings = mv88e6095_stats_get_strings,
4763 .stats_get_stat = mv88e6095_stats_get_stat,
4764 .set_cpu_port = mv88e6095_g1_set_cpu_port,
4765 .set_egress_port = mv88e6095_g1_set_egress_port,
4766 .watchdog_ops = &mv88e6097_watchdog_ops,
4767 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
4768 .pot_clear = mv88e6xxx_g2_pot_clear,
4769 .hardware_reset_pre = mv88e6xxx_g2_eeprom_wait,
4770 .hardware_reset_post = mv88e6xxx_g2_eeprom_wait,
4771 .reset = mv88e6352_g1_reset,
4772 .rmu_disable = mv88e6352_g1_rmu_disable,
4773 .atu_get_hash = mv88e6165_g1_atu_get_hash,
4774 .atu_set_hash = mv88e6165_g1_atu_set_hash,
4775 .vtu_getnext = mv88e6352_g1_vtu_getnext,
4776 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
4777 .stu_getnext = mv88e6352_g1_stu_getnext,
4778 .stu_loadpurge = mv88e6352_g1_stu_loadpurge,
4779 .serdes_irq_mapping = mv88e6352_serdes_irq_mapping,
4780 .serdes_get_regs_len = mv88e6352_serdes_get_regs_len,
4781 .serdes_get_regs = mv88e6352_serdes_get_regs,
4782 .serdes_set_tx_amplitude = mv88e6352_serdes_set_tx_amplitude,
4783 .gpio_ops = &mv88e6352_gpio_ops,
4784 .phylink_get_caps = mv88e6352_phylink_get_caps,
4785 .pcs_ops = &mv88e6352_pcs_ops,
4786 };
4787
4788 static const struct mv88e6xxx_ops mv88e6185_ops = {
4789 /* MV88E6XXX_FAMILY_6185 */
4790 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4791 .ip_pri_map = mv88e6085_g1_ip_pri_map,
4792 .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
4793 .phy_read = mv88e6185_phy_ppu_read,
4794 .phy_write = mv88e6185_phy_ppu_write,
4795 .port_set_link = mv88e6xxx_port_set_link,
4796 .port_sync_link = mv88e6185_port_sync_link,
4797 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
4798 .port_set_frame_mode = mv88e6085_port_set_frame_mode,
4799 .port_set_ucast_flood = mv88e6185_port_set_forward_unknown,
4800 .port_set_mcast_flood = mv88e6185_port_set_default_forward,
4801 .port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting,
4802 .port_set_upstream_port = mv88e6095_port_set_upstream_port,
4803 .port_set_pause = mv88e6185_port_set_pause,
4804 .port_get_cmode = mv88e6185_port_get_cmode,
4805 .port_setup_message_port = mv88e6xxx_setup_message_port,
4806 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
4807 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4808 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
4809 .stats_get_strings = mv88e6095_stats_get_strings,
4810 .stats_get_stat = mv88e6095_stats_get_stat,
4811 .set_cpu_port = mv88e6095_g1_set_cpu_port,
4812 .set_egress_port = mv88e6095_g1_set_egress_port,
4813 .watchdog_ops = &mv88e6097_watchdog_ops,
4814 .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu,
4815 .set_cascade_port = mv88e6185_g1_set_cascade_port,
4816 .ppu_enable = mv88e6185_g1_ppu_enable,
4817 .ppu_disable = mv88e6185_g1_ppu_disable,
4818 .reset = mv88e6185_g1_reset,
4819 .vtu_getnext = mv88e6185_g1_vtu_getnext,
4820 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
4821 .phylink_get_caps = mv88e6185_phylink_get_caps,
4822 .pcs_ops = &mv88e6185_pcs_ops,
4823 .set_max_frame_size = mv88e6185_g1_set_max_frame_size,
4824 };
4825
4826 static const struct mv88e6xxx_ops mv88e6190_ops = {
4827 /* MV88E6XXX_FAMILY_6390 */
4828 .setup_errata = mv88e6390_setup_errata,
4829 .irl_init_all = mv88e6390_g2_irl_init_all,
4830 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
4831 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
4832 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4833 .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
4834 .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
4835 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
4836 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
4837 .port_set_link = mv88e6xxx_port_set_link,
4838 .port_sync_link = mv88e6xxx_port_sync_link,
4839 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
4840 .port_set_speed_duplex = mv88e6390_port_set_speed_duplex,
4841 .port_max_speed_mode = mv88e6390_port_max_speed_mode,
4842 .port_tag_remap = mv88e6390_port_tag_remap,
4843 .port_set_policy = mv88e6352_port_set_policy,
4844 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4845 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4846 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
4847 .port_set_ether_type = mv88e6351_port_set_ether_type,
4848 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
4849 .port_pause_limit = mv88e6390_port_pause_limit,
4850 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4851 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4852 .port_get_cmode = mv88e6352_port_get_cmode,
4853 .port_set_cmode = mv88e6390_port_set_cmode,
4854 .port_setup_message_port = mv88e6xxx_setup_message_port,
4855 .stats_snapshot = mv88e6390_g1_stats_snapshot,
4856 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
4857 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
4858 .stats_get_strings = mv88e6320_stats_get_strings,
4859 .stats_get_stat = mv88e6390_stats_get_stat,
4860 .set_cpu_port = mv88e6390_g1_set_cpu_port,
4861 .set_egress_port = mv88e6390_g1_set_egress_port,
4862 .watchdog_ops = &mv88e6390_watchdog_ops,
4863 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
4864 .pot_clear = mv88e6xxx_g2_pot_clear,
4865 .hardware_reset_pre = mv88e6xxx_g2_eeprom_wait,
4866 .hardware_reset_post = mv88e6xxx_g2_eeprom_wait,
4867 .reset = mv88e6352_g1_reset,
4868 .rmu_disable = mv88e6390_g1_rmu_disable,
4869 .atu_get_hash = mv88e6165_g1_atu_get_hash,
4870 .atu_set_hash = mv88e6165_g1_atu_set_hash,
4871 .vtu_getnext = mv88e6390_g1_vtu_getnext,
4872 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
4873 .stu_getnext = mv88e6390_g1_stu_getnext,
4874 .stu_loadpurge = mv88e6390_g1_stu_loadpurge,
4875 .serdes_get_lane = mv88e6390_serdes_get_lane,
4876 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
4877 .serdes_get_strings = mv88e6390_serdes_get_strings,
4878 .serdes_get_stats = mv88e6390_serdes_get_stats,
4879 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len,
4880 .serdes_get_regs = mv88e6390_serdes_get_regs,
4881 .gpio_ops = &mv88e6352_gpio_ops,
4882 .phylink_get_caps = mv88e6390_phylink_get_caps,
4883 .pcs_ops = &mv88e6390_pcs_ops,
4884 };
4885
4886 static const struct mv88e6xxx_ops mv88e6190x_ops = {
4887 /* MV88E6XXX_FAMILY_6390 */
4888 .setup_errata = mv88e6390_setup_errata,
4889 .irl_init_all = mv88e6390_g2_irl_init_all,
4890 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
4891 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
4892 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4893 .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
4894 .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
4895 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
4896 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
4897 .port_set_link = mv88e6xxx_port_set_link,
4898 .port_sync_link = mv88e6xxx_port_sync_link,
4899 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
4900 .port_set_speed_duplex = mv88e6390x_port_set_speed_duplex,
4901 .port_max_speed_mode = mv88e6390x_port_max_speed_mode,
4902 .port_tag_remap = mv88e6390_port_tag_remap,
4903 .port_set_policy = mv88e6352_port_set_policy,
4904 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4905 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4906 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
4907 .port_set_ether_type = mv88e6351_port_set_ether_type,
4908 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
4909 .port_pause_limit = mv88e6390_port_pause_limit,
4910 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4911 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4912 .port_get_cmode = mv88e6352_port_get_cmode,
4913 .port_set_cmode = mv88e6390x_port_set_cmode,
4914 .port_setup_message_port = mv88e6xxx_setup_message_port,
4915 .stats_snapshot = mv88e6390_g1_stats_snapshot,
4916 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
4917 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
4918 .stats_get_strings = mv88e6320_stats_get_strings,
4919 .stats_get_stat = mv88e6390_stats_get_stat,
4920 .set_cpu_port = mv88e6390_g1_set_cpu_port,
4921 .set_egress_port = mv88e6390_g1_set_egress_port,
4922 .watchdog_ops = &mv88e6390_watchdog_ops,
4923 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
4924 .pot_clear = mv88e6xxx_g2_pot_clear,
4925 .hardware_reset_pre = mv88e6xxx_g2_eeprom_wait,
4926 .hardware_reset_post = mv88e6xxx_g2_eeprom_wait,
4927 .reset = mv88e6352_g1_reset,
4928 .rmu_disable = mv88e6390_g1_rmu_disable,
4929 .atu_get_hash = mv88e6165_g1_atu_get_hash,
4930 .atu_set_hash = mv88e6165_g1_atu_set_hash,
4931 .vtu_getnext = mv88e6390_g1_vtu_getnext,
4932 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
4933 .stu_getnext = mv88e6390_g1_stu_getnext,
4934 .stu_loadpurge = mv88e6390_g1_stu_loadpurge,
4935 .serdes_get_lane = mv88e6390x_serdes_get_lane,
4936 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
4937 .serdes_get_strings = mv88e6390_serdes_get_strings,
4938 .serdes_get_stats = mv88e6390_serdes_get_stats,
4939 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len,
4940 .serdes_get_regs = mv88e6390_serdes_get_regs,
4941 .gpio_ops = &mv88e6352_gpio_ops,
4942 .phylink_get_caps = mv88e6390x_phylink_get_caps,
4943 .pcs_ops = &mv88e6390_pcs_ops,
4944 };
4945
4946 static const struct mv88e6xxx_ops mv88e6191_ops = {
4947 /* MV88E6XXX_FAMILY_6390 */
4948 .setup_errata = mv88e6390_setup_errata,
4949 .irl_init_all = mv88e6390_g2_irl_init_all,
4950 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
4951 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
4952 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4953 .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
4954 .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
4955 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
4956 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
4957 .port_set_link = mv88e6xxx_port_set_link,
4958 .port_sync_link = mv88e6xxx_port_sync_link,
4959 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
4960 .port_set_speed_duplex = mv88e6390_port_set_speed_duplex,
4961 .port_max_speed_mode = mv88e6390_port_max_speed_mode,
4962 .port_tag_remap = mv88e6390_port_tag_remap,
4963 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4964 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4965 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
4966 .port_set_ether_type = mv88e6351_port_set_ether_type,
4967 .port_pause_limit = mv88e6390_port_pause_limit,
4968 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4969 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4970 .port_get_cmode = mv88e6352_port_get_cmode,
4971 .port_set_cmode = mv88e6390_port_set_cmode,
4972 .port_setup_message_port = mv88e6xxx_setup_message_port,
4973 .stats_snapshot = mv88e6390_g1_stats_snapshot,
4974 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
4975 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
4976 .stats_get_strings = mv88e6320_stats_get_strings,
4977 .stats_get_stat = mv88e6390_stats_get_stat,
4978 .set_cpu_port = mv88e6390_g1_set_cpu_port,
4979 .set_egress_port = mv88e6390_g1_set_egress_port,
4980 .watchdog_ops = &mv88e6390_watchdog_ops,
4981 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
4982 .pot_clear = mv88e6xxx_g2_pot_clear,
4983 .hardware_reset_pre = mv88e6xxx_g2_eeprom_wait,
4984 .hardware_reset_post = mv88e6xxx_g2_eeprom_wait,
4985 .reset = mv88e6352_g1_reset,
4986 .rmu_disable = mv88e6390_g1_rmu_disable,
4987 .atu_get_hash = mv88e6165_g1_atu_get_hash,
4988 .atu_set_hash = mv88e6165_g1_atu_set_hash,
4989 .vtu_getnext = mv88e6390_g1_vtu_getnext,
4990 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
4991 .stu_getnext = mv88e6390_g1_stu_getnext,
4992 .stu_loadpurge = mv88e6390_g1_stu_loadpurge,
4993 .serdes_get_lane = mv88e6390_serdes_get_lane,
4994 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
4995 .serdes_get_strings = mv88e6390_serdes_get_strings,
4996 .serdes_get_stats = mv88e6390_serdes_get_stats,
4997 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len,
4998 .serdes_get_regs = mv88e6390_serdes_get_regs,
4999 .avb_ops = &mv88e6390_avb_ops,
5000 .ptp_ops = &mv88e6352_ptp_ops,
5001 .phylink_get_caps = mv88e6390_phylink_get_caps,
5002 .pcs_ops = &mv88e6390_pcs_ops,
5003 };
5004
5005 static const struct mv88e6xxx_ops mv88e6240_ops = {
5006 /* MV88E6XXX_FAMILY_6352 */
5007 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
5008 .ip_pri_map = mv88e6085_g1_ip_pri_map,
5009 .irl_init_all = mv88e6352_g2_irl_init_all,
5010 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
5011 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
5012 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
5013 .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
5014 .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
5015 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
5016 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
5017 .port_set_link = mv88e6xxx_port_set_link,
5018 .port_sync_link = mv88e6xxx_port_sync_link,
5019 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
5020 .port_set_speed_duplex = mv88e6352_port_set_speed_duplex,
5021 .port_tag_remap = mv88e6095_port_tag_remap,
5022 .port_set_policy = mv88e6352_port_set_policy,
5023 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
5024 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
5025 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
5026 .port_set_ether_type = mv88e6351_port_set_ether_type,
5027 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
5028 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
5029 .port_pause_limit = mv88e6097_port_pause_limit,
5030 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
5031 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
5032 .port_get_cmode = mv88e6352_port_get_cmode,
5033 .port_setup_message_port = mv88e6xxx_setup_message_port,
5034 .stats_snapshot = mv88e6320_g1_stats_snapshot,
5035 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
5036 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
5037 .stats_get_strings = mv88e6095_stats_get_strings,
5038 .stats_get_stat = mv88e6095_stats_get_stat,
5039 .set_cpu_port = mv88e6095_g1_set_cpu_port,
5040 .set_egress_port = mv88e6095_g1_set_egress_port,
5041 .watchdog_ops = &mv88e6097_watchdog_ops,
5042 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
5043 .pot_clear = mv88e6xxx_g2_pot_clear,
5044 .hardware_reset_pre = mv88e6xxx_g2_eeprom_wait,
5045 .hardware_reset_post = mv88e6xxx_g2_eeprom_wait,
5046 .reset = mv88e6352_g1_reset,
5047 .rmu_disable = mv88e6352_g1_rmu_disable,
5048 .atu_get_hash = mv88e6165_g1_atu_get_hash,
5049 .atu_set_hash = mv88e6165_g1_atu_set_hash,
5050 .vtu_getnext = mv88e6352_g1_vtu_getnext,
5051 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
5052 .stu_getnext = mv88e6352_g1_stu_getnext,
5053 .stu_loadpurge = mv88e6352_g1_stu_loadpurge,
5054 .serdes_irq_mapping = mv88e6352_serdes_irq_mapping,
5055 .serdes_get_regs_len = mv88e6352_serdes_get_regs_len,
5056 .serdes_get_regs = mv88e6352_serdes_get_regs,
5057 .serdes_set_tx_amplitude = mv88e6352_serdes_set_tx_amplitude,
5058 .gpio_ops = &mv88e6352_gpio_ops,
5059 .avb_ops = &mv88e6352_avb_ops,
5060 .ptp_ops = &mv88e6352_ptp_ops,
5061 .phylink_get_caps = mv88e6352_phylink_get_caps,
5062 .pcs_ops = &mv88e6352_pcs_ops,
5063 };
5064
5065 static const struct mv88e6xxx_ops mv88e6250_ops = {
5066 /* MV88E6XXX_FAMILY_6250 */
5067 .ieee_pri_map = mv88e6250_g1_ieee_pri_map,
5068 .ip_pri_map = mv88e6085_g1_ip_pri_map,
5069 .irl_init_all = mv88e6352_g2_irl_init_all,
5070 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
5071 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
5072 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
5073 .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
5074 .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
5075 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
5076 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
5077 .port_set_link = mv88e6xxx_port_set_link,
5078 .port_sync_link = mv88e6xxx_port_sync_link,
5079 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
5080 .port_set_speed_duplex = mv88e6250_port_set_speed_duplex,
5081 .port_tag_remap = mv88e6095_port_tag_remap,
5082 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
5083 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
5084 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
5085 .port_set_ether_type = mv88e6351_port_set_ether_type,
5086 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
5087 .port_pause_limit = mv88e6097_port_pause_limit,
5088 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
5089 .stats_snapshot = mv88e6320_g1_stats_snapshot,
5090 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
5091 .stats_get_sset_count = mv88e6250_stats_get_sset_count,
5092 .stats_get_strings = mv88e6250_stats_get_strings,
5093 .stats_get_stat = mv88e6250_stats_get_stat,
5094 .set_cpu_port = mv88e6095_g1_set_cpu_port,
5095 .set_egress_port = mv88e6095_g1_set_egress_port,
5096 .watchdog_ops = &mv88e6250_watchdog_ops,
5097 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
5098 .pot_clear = mv88e6xxx_g2_pot_clear,
5099 .hardware_reset_pre = mv88e6250_g1_wait_eeprom_done_prereset,
5100 .hardware_reset_post = mv88e6xxx_g1_wait_eeprom_done,
5101 .reset = mv88e6250_g1_reset,
5102 .vtu_getnext = mv88e6185_g1_vtu_getnext,
5103 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
5104 .avb_ops = &mv88e6352_avb_ops,
5105 .ptp_ops = &mv88e6250_ptp_ops,
5106 .phylink_get_caps = mv88e6250_phylink_get_caps,
5107 .set_max_frame_size = mv88e6185_g1_set_max_frame_size,
5108 };
5109
5110 static const struct mv88e6xxx_ops mv88e6290_ops = {
5111 /* MV88E6XXX_FAMILY_6390 */
5112 .setup_errata = mv88e6390_setup_errata,
5113 .irl_init_all = mv88e6390_g2_irl_init_all,
5114 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
5115 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
5116 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
5117 .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
5118 .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
5119 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
5120 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
5121 .port_set_link = mv88e6xxx_port_set_link,
5122 .port_sync_link = mv88e6xxx_port_sync_link,
5123 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
5124 .port_set_speed_duplex = mv88e6390_port_set_speed_duplex,
5125 .port_max_speed_mode = mv88e6390_port_max_speed_mode,
5126 .port_tag_remap = mv88e6390_port_tag_remap,
5127 .port_set_policy = mv88e6352_port_set_policy,
5128 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
5129 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
5130 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
5131 .port_set_ether_type = mv88e6351_port_set_ether_type,
5132 .port_pause_limit = mv88e6390_port_pause_limit,
5133 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
5134 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
5135 .port_get_cmode = mv88e6352_port_get_cmode,
5136 .port_set_cmode = mv88e6390_port_set_cmode,
5137 .port_setup_message_port = mv88e6xxx_setup_message_port,
5138 .stats_snapshot = mv88e6390_g1_stats_snapshot,
5139 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
5140 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
5141 .stats_get_strings = mv88e6320_stats_get_strings,
5142 .stats_get_stat = mv88e6390_stats_get_stat,
5143 .set_cpu_port = mv88e6390_g1_set_cpu_port,
5144 .set_egress_port = mv88e6390_g1_set_egress_port,
5145 .watchdog_ops = &mv88e6390_watchdog_ops,
5146 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
5147 .pot_clear = mv88e6xxx_g2_pot_clear,
5148 .hardware_reset_pre = mv88e6xxx_g2_eeprom_wait,
5149 .hardware_reset_post = mv88e6xxx_g2_eeprom_wait,
5150 .reset = mv88e6352_g1_reset,
5151 .rmu_disable = mv88e6390_g1_rmu_disable,
5152 .atu_get_hash = mv88e6165_g1_atu_get_hash,
5153 .atu_set_hash = mv88e6165_g1_atu_set_hash,
5154 .vtu_getnext = mv88e6390_g1_vtu_getnext,
5155 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
5156 .stu_getnext = mv88e6390_g1_stu_getnext,
5157 .stu_loadpurge = mv88e6390_g1_stu_loadpurge,
5158 .serdes_get_lane = mv88e6390_serdes_get_lane,
5159 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
5160 .serdes_get_strings = mv88e6390_serdes_get_strings,
5161 .serdes_get_stats = mv88e6390_serdes_get_stats,
5162 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len,
5163 .serdes_get_regs = mv88e6390_serdes_get_regs,
5164 .gpio_ops = &mv88e6352_gpio_ops,
5165 .avb_ops = &mv88e6390_avb_ops,
5166 .ptp_ops = &mv88e6390_ptp_ops,
5167 .phylink_get_caps = mv88e6390_phylink_get_caps,
5168 .pcs_ops = &mv88e6390_pcs_ops,
5169 };
5170
5171 static const struct mv88e6xxx_ops mv88e6320_ops = {
5172 /* MV88E6XXX_FAMILY_6320 */
5173 .setup_errata = mv88e6320_setup_errata,
5174 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
5175 .ip_pri_map = mv88e6085_g1_ip_pri_map,
5176 .irl_init_all = mv88e6352_g2_irl_init_all,
5177 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
5178 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
5179 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
5180 .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
5181 .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
5182 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
5183 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
5184 .port_set_link = mv88e6xxx_port_set_link,
5185 .port_sync_link = mv88e6xxx_port_sync_link,
5186 .port_set_rgmii_delay = mv88e6320_port_set_rgmii_delay,
5187 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
5188 .port_tag_remap = mv88e6095_port_tag_remap,
5189 .port_set_policy = mv88e6352_port_set_policy,
5190 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
5191 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
5192 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
5193 .port_set_ether_type = mv88e6351_port_set_ether_type,
5194 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
5195 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
5196 .port_pause_limit = mv88e6097_port_pause_limit,
5197 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
5198 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
5199 .port_get_cmode = mv88e6352_port_get_cmode,
5200 .port_setup_message_port = mv88e6xxx_setup_message_port,
5201 .stats_snapshot = mv88e6320_g1_stats_snapshot,
5202 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
5203 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
5204 .stats_get_strings = mv88e6320_stats_get_strings,
5205 .stats_get_stat = mv88e6320_stats_get_stat,
5206 .set_cpu_port = mv88e6095_g1_set_cpu_port,
5207 .set_egress_port = mv88e6095_g1_set_egress_port,
5208 .watchdog_ops = &mv88e6390_watchdog_ops,
5209 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
5210 .pot_clear = mv88e6xxx_g2_pot_clear,
5211 .hardware_reset_pre = mv88e6xxx_g2_eeprom_wait,
5212 .hardware_reset_post = mv88e6xxx_g2_eeprom_wait,
5213 .reset = mv88e6352_g1_reset,
5214 .vtu_getnext = mv88e6352_g1_vtu_getnext,
5215 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
5216 .stu_getnext = mv88e6352_g1_stu_getnext,
5217 .stu_loadpurge = mv88e6352_g1_stu_loadpurge,
5218 .gpio_ops = &mv88e6352_gpio_ops,
5219 .avb_ops = &mv88e6352_avb_ops,
5220 .ptp_ops = &mv88e6352_ptp_ops,
5221 .phylink_get_caps = mv88e632x_phylink_get_caps,
5222 };
5223
5224 static const struct mv88e6xxx_ops mv88e6321_ops = {
5225 /* MV88E6XXX_FAMILY_6320 */
5226 .setup_errata = mv88e6320_setup_errata,
5227 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
5228 .ip_pri_map = mv88e6085_g1_ip_pri_map,
5229 .irl_init_all = mv88e6352_g2_irl_init_all,
5230 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
5231 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
5232 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
5233 .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
5234 .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
5235 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
5236 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
5237 .port_set_link = mv88e6xxx_port_set_link,
5238 .port_sync_link = mv88e6xxx_port_sync_link,
5239 .port_set_rgmii_delay = mv88e6320_port_set_rgmii_delay,
5240 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
5241 .port_tag_remap = mv88e6095_port_tag_remap,
5242 .port_set_policy = mv88e6352_port_set_policy,
5243 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
5244 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
5245 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
5246 .port_set_ether_type = mv88e6351_port_set_ether_type,
5247 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
5248 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
5249 .port_pause_limit = mv88e6097_port_pause_limit,
5250 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
5251 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
5252 .port_get_cmode = mv88e6352_port_get_cmode,
5253 .port_setup_message_port = mv88e6xxx_setup_message_port,
5254 .stats_snapshot = mv88e6320_g1_stats_snapshot,
5255 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
5256 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
5257 .stats_get_strings = mv88e6320_stats_get_strings,
5258 .stats_get_stat = mv88e6320_stats_get_stat,
5259 .set_cpu_port = mv88e6095_g1_set_cpu_port,
5260 .set_egress_port = mv88e6095_g1_set_egress_port,
5261 .watchdog_ops = &mv88e6390_watchdog_ops,
5262 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
5263 .hardware_reset_pre = mv88e6xxx_g2_eeprom_wait,
5264 .hardware_reset_post = mv88e6xxx_g2_eeprom_wait,
5265 .reset = mv88e6352_g1_reset,
5266 .vtu_getnext = mv88e6352_g1_vtu_getnext,
5267 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
5268 .stu_getnext = mv88e6352_g1_stu_getnext,
5269 .stu_loadpurge = mv88e6352_g1_stu_loadpurge,
5270 .gpio_ops = &mv88e6352_gpio_ops,
5271 .avb_ops = &mv88e6352_avb_ops,
5272 .ptp_ops = &mv88e6352_ptp_ops,
5273 .phylink_get_caps = mv88e632x_phylink_get_caps,
5274 };
5275
5276 static const struct mv88e6xxx_ops mv88e6341_ops = {
5277 /* MV88E6XXX_FAMILY_6341 */
5278 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
5279 .ip_pri_map = mv88e6085_g1_ip_pri_map,
5280 .irl_init_all = mv88e6352_g2_irl_init_all,
5281 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
5282 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
5283 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
5284 .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
5285 .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
5286 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
5287 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
5288 .port_set_link = mv88e6xxx_port_set_link,
5289 .port_sync_link = mv88e6xxx_port_sync_link,
5290 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
5291 .port_set_speed_duplex = mv88e6341_port_set_speed_duplex,
5292 .port_max_speed_mode = mv88e6341_port_max_speed_mode,
5293 .port_tag_remap = mv88e6095_port_tag_remap,
5294 .port_set_policy = mv88e6352_port_set_policy,
5295 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
5296 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
5297 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
5298 .port_set_ether_type = mv88e6351_port_set_ether_type,
5299 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
5300 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
5301 .port_pause_limit = mv88e6097_port_pause_limit,
5302 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
5303 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
5304 .port_get_cmode = mv88e6352_port_get_cmode,
5305 .port_set_cmode = mv88e6341_port_set_cmode,
5306 .port_setup_message_port = mv88e6xxx_setup_message_port,
5307 .stats_snapshot = mv88e6390_g1_stats_snapshot,
5308 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
5309 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
5310 .stats_get_strings = mv88e6320_stats_get_strings,
5311 .stats_get_stat = mv88e6390_stats_get_stat,
5312 .set_cpu_port = mv88e6390_g1_set_cpu_port,
5313 .set_egress_port = mv88e6390_g1_set_egress_port,
5314 .watchdog_ops = &mv88e6390_watchdog_ops,
5315 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
5316 .pot_clear = mv88e6xxx_g2_pot_clear,
5317 .hardware_reset_pre = mv88e6xxx_g2_eeprom_wait,
5318 .hardware_reset_post = mv88e6xxx_g2_eeprom_wait,
5319 .reset = mv88e6352_g1_reset,
5320 .rmu_disable = mv88e6390_g1_rmu_disable,
5321 .atu_get_hash = mv88e6165_g1_atu_get_hash,
5322 .atu_set_hash = mv88e6165_g1_atu_set_hash,
5323 .vtu_getnext = mv88e6352_g1_vtu_getnext,
5324 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
5325 .stu_getnext = mv88e6352_g1_stu_getnext,
5326 .stu_loadpurge = mv88e6352_g1_stu_loadpurge,
5327 .serdes_get_lane = mv88e6341_serdes_get_lane,
5328 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
5329 .gpio_ops = &mv88e6352_gpio_ops,
5330 .avb_ops = &mv88e6390_avb_ops,
5331 .ptp_ops = &mv88e6352_ptp_ops,
5332 .serdes_get_sset_count = mv88e6390_serdes_get_sset_count,
5333 .serdes_get_strings = mv88e6390_serdes_get_strings,
5334 .serdes_get_stats = mv88e6390_serdes_get_stats,
5335 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len,
5336 .serdes_get_regs = mv88e6390_serdes_get_regs,
5337 .phylink_get_caps = mv88e6341_phylink_get_caps,
5338 .pcs_ops = &mv88e6390_pcs_ops,
5339 };
5340
5341 static const struct mv88e6xxx_ops mv88e6350_ops = {
5342 /* MV88E6XXX_FAMILY_6351 */
5343 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
5344 .ip_pri_map = mv88e6085_g1_ip_pri_map,
5345 .irl_init_all = mv88e6352_g2_irl_init_all,
5346 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
5347 .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
5348 .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
5349 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
5350 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
5351 .port_set_link = mv88e6xxx_port_set_link,
5352 .port_sync_link = mv88e6xxx_port_sync_link,
5353 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
5354 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
5355 .port_tag_remap = mv88e6095_port_tag_remap,
5356 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
5357 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
5358 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
5359 .port_set_ether_type = mv88e6351_port_set_ether_type,
5360 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
5361 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
5362 .port_pause_limit = mv88e6097_port_pause_limit,
5363 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
5364 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
5365 .port_get_cmode = mv88e6352_port_get_cmode,
5366 .port_setup_message_port = mv88e6xxx_setup_message_port,
5367 .stats_snapshot = mv88e6320_g1_stats_snapshot,
5368 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
5369 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
5370 .stats_get_strings = mv88e6095_stats_get_strings,
5371 .stats_get_stat = mv88e6095_stats_get_stat,
5372 .set_cpu_port = mv88e6095_g1_set_cpu_port,
5373 .set_egress_port = mv88e6095_g1_set_egress_port,
5374 .watchdog_ops = &mv88e6097_watchdog_ops,
5375 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
5376 .pot_clear = mv88e6xxx_g2_pot_clear,
5377 .reset = mv88e6352_g1_reset,
5378 .atu_get_hash = mv88e6165_g1_atu_get_hash,
5379 .atu_set_hash = mv88e6165_g1_atu_set_hash,
5380 .vtu_getnext = mv88e6352_g1_vtu_getnext,
5381 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
5382 .stu_getnext = mv88e6352_g1_stu_getnext,
5383 .stu_loadpurge = mv88e6352_g1_stu_loadpurge,
5384 .phylink_get_caps = mv88e6351_phylink_get_caps,
5385 };
5386
5387 static const struct mv88e6xxx_ops mv88e6351_ops = {
5388 /* MV88E6XXX_FAMILY_6351 */
5389 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
5390 .ip_pri_map = mv88e6085_g1_ip_pri_map,
5391 .irl_init_all = mv88e6352_g2_irl_init_all,
5392 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
5393 .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
5394 .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
5395 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
5396 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
5397 .port_set_link = mv88e6xxx_port_set_link,
5398 .port_sync_link = mv88e6xxx_port_sync_link,
5399 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
5400 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
5401 .port_tag_remap = mv88e6095_port_tag_remap,
5402 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
5403 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
5404 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
5405 .port_set_ether_type = mv88e6351_port_set_ether_type,
5406 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
5407 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
5408 .port_pause_limit = mv88e6097_port_pause_limit,
5409 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
5410 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
5411 .port_get_cmode = mv88e6352_port_get_cmode,
5412 .port_setup_message_port = mv88e6xxx_setup_message_port,
5413 .stats_snapshot = mv88e6320_g1_stats_snapshot,
5414 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
5415 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
5416 .stats_get_strings = mv88e6095_stats_get_strings,
5417 .stats_get_stat = mv88e6095_stats_get_stat,
5418 .set_cpu_port = mv88e6095_g1_set_cpu_port,
5419 .set_egress_port = mv88e6095_g1_set_egress_port,
5420 .watchdog_ops = &mv88e6097_watchdog_ops,
5421 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
5422 .pot_clear = mv88e6xxx_g2_pot_clear,
5423 .reset = mv88e6352_g1_reset,
5424 .atu_get_hash = mv88e6165_g1_atu_get_hash,
5425 .atu_set_hash = mv88e6165_g1_atu_set_hash,
5426 .vtu_getnext = mv88e6352_g1_vtu_getnext,
5427 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
5428 .stu_getnext = mv88e6352_g1_stu_getnext,
5429 .stu_loadpurge = mv88e6352_g1_stu_loadpurge,
5430 .avb_ops = &mv88e6352_avb_ops,
5431 .ptp_ops = &mv88e6352_ptp_ops,
5432 .phylink_get_caps = mv88e6351_phylink_get_caps,
5433 };
5434
5435 static const struct mv88e6xxx_ops mv88e6352_ops = {
5436 /* MV88E6XXX_FAMILY_6352 */
5437 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
5438 .ip_pri_map = mv88e6085_g1_ip_pri_map,
5439 .irl_init_all = mv88e6352_g2_irl_init_all,
5440 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
5441 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
5442 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
5443 .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
5444 .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
5445 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
5446 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
5447 .port_set_link = mv88e6xxx_port_set_link,
5448 .port_sync_link = mv88e6xxx_port_sync_link,
5449 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
5450 .port_set_speed_duplex = mv88e6352_port_set_speed_duplex,
5451 .port_tag_remap = mv88e6095_port_tag_remap,
5452 .port_set_policy = mv88e6352_port_set_policy,
5453 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
5454 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
5455 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
5456 .port_set_ether_type = mv88e6351_port_set_ether_type,
5457 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
5458 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
5459 .port_pause_limit = mv88e6097_port_pause_limit,
5460 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
5461 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
5462 .port_get_cmode = mv88e6352_port_get_cmode,
5463 .port_setup_message_port = mv88e6xxx_setup_message_port,
5464 .stats_snapshot = mv88e6320_g1_stats_snapshot,
5465 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
5466 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
5467 .stats_get_strings = mv88e6095_stats_get_strings,
5468 .stats_get_stat = mv88e6095_stats_get_stat,
5469 .set_cpu_port = mv88e6095_g1_set_cpu_port,
5470 .set_egress_port = mv88e6095_g1_set_egress_port,
5471 .watchdog_ops = &mv88e6097_watchdog_ops,
5472 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
5473 .pot_clear = mv88e6xxx_g2_pot_clear,
5474 .hardware_reset_pre = mv88e6xxx_g2_eeprom_wait,
5475 .hardware_reset_post = mv88e6xxx_g2_eeprom_wait,
5476 .reset = mv88e6352_g1_reset,
5477 .rmu_disable = mv88e6352_g1_rmu_disable,
5478 .atu_get_hash = mv88e6165_g1_atu_get_hash,
5479 .atu_set_hash = mv88e6165_g1_atu_set_hash,
5480 .vtu_getnext = mv88e6352_g1_vtu_getnext,
5481 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
5482 .stu_getnext = mv88e6352_g1_stu_getnext,
5483 .stu_loadpurge = mv88e6352_g1_stu_loadpurge,
5484 .serdes_irq_mapping = mv88e6352_serdes_irq_mapping,
5485 .gpio_ops = &mv88e6352_gpio_ops,
5486 .avb_ops = &mv88e6352_avb_ops,
5487 .ptp_ops = &mv88e6352_ptp_ops,
5488 .serdes_get_sset_count = mv88e6352_serdes_get_sset_count,
5489 .serdes_get_strings = mv88e6352_serdes_get_strings,
5490 .serdes_get_stats = mv88e6352_serdes_get_stats,
5491 .serdes_get_regs_len = mv88e6352_serdes_get_regs_len,
5492 .serdes_get_regs = mv88e6352_serdes_get_regs,
5493 .serdes_set_tx_amplitude = mv88e6352_serdes_set_tx_amplitude,
5494 .phylink_get_caps = mv88e6352_phylink_get_caps,
5495 .pcs_ops = &mv88e6352_pcs_ops,
5496 };
5497
5498 static const struct mv88e6xxx_ops mv88e6390_ops = {
5499 /* MV88E6XXX_FAMILY_6390 */
5500 .setup_errata = mv88e6390_setup_errata,
5501 .irl_init_all = mv88e6390_g2_irl_init_all,
5502 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
5503 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
5504 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
5505 .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
5506 .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
5507 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
5508 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
5509 .port_set_link = mv88e6xxx_port_set_link,
5510 .port_sync_link = mv88e6xxx_port_sync_link,
5511 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
5512 .port_set_speed_duplex = mv88e6390_port_set_speed_duplex,
5513 .port_max_speed_mode = mv88e6390_port_max_speed_mode,
5514 .port_tag_remap = mv88e6390_port_tag_remap,
5515 .port_set_policy = mv88e6352_port_set_policy,
5516 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
5517 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
5518 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
5519 .port_set_ether_type = mv88e6351_port_set_ether_type,
5520 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
5521 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
5522 .port_pause_limit = mv88e6390_port_pause_limit,
5523 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
5524 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
5525 .port_get_cmode = mv88e6352_port_get_cmode,
5526 .port_set_cmode = mv88e6390_port_set_cmode,
5527 .port_setup_message_port = mv88e6xxx_setup_message_port,
5528 .stats_snapshot = mv88e6390_g1_stats_snapshot,
5529 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
5530 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
5531 .stats_get_strings = mv88e6320_stats_get_strings,
5532 .stats_get_stat = mv88e6390_stats_get_stat,
5533 .set_cpu_port = mv88e6390_g1_set_cpu_port,
5534 .set_egress_port = mv88e6390_g1_set_egress_port,
5535 .watchdog_ops = &mv88e6390_watchdog_ops,
5536 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
5537 .pot_clear = mv88e6xxx_g2_pot_clear,
5538 .hardware_reset_pre = mv88e6xxx_g2_eeprom_wait,
5539 .hardware_reset_post = mv88e6xxx_g2_eeprom_wait,
5540 .reset = mv88e6352_g1_reset,
5541 .rmu_disable = mv88e6390_g1_rmu_disable,
5542 .atu_get_hash = mv88e6165_g1_atu_get_hash,
5543 .atu_set_hash = mv88e6165_g1_atu_set_hash,
5544 .vtu_getnext = mv88e6390_g1_vtu_getnext,
5545 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
5546 .stu_getnext = mv88e6390_g1_stu_getnext,
5547 .stu_loadpurge = mv88e6390_g1_stu_loadpurge,
5548 .serdes_get_lane = mv88e6390_serdes_get_lane,
5549 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
5550 .gpio_ops = &mv88e6352_gpio_ops,
5551 .avb_ops = &mv88e6390_avb_ops,
5552 .ptp_ops = &mv88e6390_ptp_ops,
5553 .serdes_get_sset_count = mv88e6390_serdes_get_sset_count,
5554 .serdes_get_strings = mv88e6390_serdes_get_strings,
5555 .serdes_get_stats = mv88e6390_serdes_get_stats,
5556 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len,
5557 .serdes_get_regs = mv88e6390_serdes_get_regs,
5558 .phylink_get_caps = mv88e6390_phylink_get_caps,
5559 .pcs_ops = &mv88e6390_pcs_ops,
5560 };
5561
5562 static const struct mv88e6xxx_ops mv88e6390x_ops = {
5563 /* MV88E6XXX_FAMILY_6390 */
5564 .setup_errata = mv88e6390_setup_errata,
5565 .irl_init_all = mv88e6390_g2_irl_init_all,
5566 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
5567 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
5568 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
5569 .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
5570 .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
5571 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
5572 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
5573 .port_set_link = mv88e6xxx_port_set_link,
5574 .port_sync_link = mv88e6xxx_port_sync_link,
5575 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
5576 .port_set_speed_duplex = mv88e6390x_port_set_speed_duplex,
5577 .port_max_speed_mode = mv88e6390x_port_max_speed_mode,
5578 .port_tag_remap = mv88e6390_port_tag_remap,
5579 .port_set_policy = mv88e6352_port_set_policy,
5580 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
5581 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
5582 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
5583 .port_set_ether_type = mv88e6351_port_set_ether_type,
5584 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
5585 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
5586 .port_pause_limit = mv88e6390_port_pause_limit,
5587 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
5588 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
5589 .port_get_cmode = mv88e6352_port_get_cmode,
5590 .port_set_cmode = mv88e6390x_port_set_cmode,
5591 .port_setup_message_port = mv88e6xxx_setup_message_port,
5592 .stats_snapshot = mv88e6390_g1_stats_snapshot,
5593 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
5594 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
5595 .stats_get_strings = mv88e6320_stats_get_strings,
5596 .stats_get_stat = mv88e6390_stats_get_stat,
5597 .set_cpu_port = mv88e6390_g1_set_cpu_port,
5598 .set_egress_port = mv88e6390_g1_set_egress_port,
5599 .watchdog_ops = &mv88e6390_watchdog_ops,
5600 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
5601 .pot_clear = mv88e6xxx_g2_pot_clear,
5602 .hardware_reset_pre = mv88e6xxx_g2_eeprom_wait,
5603 .hardware_reset_post = mv88e6xxx_g2_eeprom_wait,
5604 .reset = mv88e6352_g1_reset,
5605 .rmu_disable = mv88e6390_g1_rmu_disable,
5606 .atu_get_hash = mv88e6165_g1_atu_get_hash,
5607 .atu_set_hash = mv88e6165_g1_atu_set_hash,
5608 .vtu_getnext = mv88e6390_g1_vtu_getnext,
5609 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
5610 .stu_getnext = mv88e6390_g1_stu_getnext,
5611 .stu_loadpurge = mv88e6390_g1_stu_loadpurge,
5612 .serdes_get_lane = mv88e6390x_serdes_get_lane,
5613 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
5614 .serdes_get_sset_count = mv88e6390_serdes_get_sset_count,
5615 .serdes_get_strings = mv88e6390_serdes_get_strings,
5616 .serdes_get_stats = mv88e6390_serdes_get_stats,
5617 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len,
5618 .serdes_get_regs = mv88e6390_serdes_get_regs,
5619 .gpio_ops = &mv88e6352_gpio_ops,
5620 .avb_ops = &mv88e6390_avb_ops,
5621 .ptp_ops = &mv88e6390_ptp_ops,
5622 .phylink_get_caps = mv88e6390x_phylink_get_caps,
5623 .pcs_ops = &mv88e6390_pcs_ops,
5624 };
5625
5626 static const struct mv88e6xxx_ops mv88e6393x_ops = {
5627 /* MV88E6XXX_FAMILY_6393 */
5628 .irl_init_all = mv88e6390_g2_irl_init_all,
5629 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
5630 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
5631 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
5632 .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
5633 .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
5634 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
5635 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
5636 .port_set_link = mv88e6xxx_port_set_link,
5637 .port_sync_link = mv88e6xxx_port_sync_link,
5638 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
5639 .port_set_speed_duplex = mv88e6393x_port_set_speed_duplex,
5640 .port_max_speed_mode = mv88e6393x_port_max_speed_mode,
5641 .port_tag_remap = mv88e6390_port_tag_remap,
5642 .port_set_policy = mv88e6393x_port_set_policy,
5643 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
5644 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
5645 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
5646 .port_set_ether_type = mv88e6393x_port_set_ether_type,
5647 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
5648 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
5649 .port_pause_limit = mv88e6390_port_pause_limit,
5650 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
5651 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
5652 .port_get_cmode = mv88e6352_port_get_cmode,
5653 .port_set_cmode = mv88e6393x_port_set_cmode,
5654 .port_setup_message_port = mv88e6xxx_setup_message_port,
5655 .port_set_upstream_port = mv88e6393x_port_set_upstream_port,
5656 .stats_snapshot = mv88e6390_g1_stats_snapshot,
5657 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
5658 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
5659 .stats_get_strings = mv88e6320_stats_get_strings,
5660 .stats_get_stat = mv88e6390_stats_get_stat,
5661 /* .set_cpu_port is missing because this family does not support a global
5662 * CPU port, only per port CPU port which is set via
5663 * .port_set_upstream_port method.
5664 */
5665 .set_egress_port = mv88e6393x_set_egress_port,
5666 .watchdog_ops = &mv88e6393x_watchdog_ops,
5667 .mgmt_rsvd2cpu = mv88e6393x_port_mgmt_rsvd2cpu,
5668 .pot_clear = mv88e6xxx_g2_pot_clear,
5669 .hardware_reset_pre = mv88e6xxx_g2_eeprom_wait,
5670 .hardware_reset_post = mv88e6xxx_g2_eeprom_wait,
5671 .reset = mv88e6352_g1_reset,
5672 .rmu_disable = mv88e6390_g1_rmu_disable,
5673 .atu_get_hash = mv88e6165_g1_atu_get_hash,
5674 .atu_set_hash = mv88e6165_g1_atu_set_hash,
5675 .vtu_getnext = mv88e6390_g1_vtu_getnext,
5676 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
5677 .stu_getnext = mv88e6390_g1_stu_getnext,
5678 .stu_loadpurge = mv88e6390_g1_stu_loadpurge,
5679 .serdes_get_lane = mv88e6393x_serdes_get_lane,
5680 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
5681 /* TODO: serdes stats */
5682 .gpio_ops = &mv88e6352_gpio_ops,
5683 .avb_ops = &mv88e6390_avb_ops,
5684 .ptp_ops = &mv88e6352_ptp_ops,
5685 .phylink_get_caps = mv88e6393x_phylink_get_caps,
5686 .pcs_ops = &mv88e6393x_pcs_ops,
5687 };
5688
5689 static const struct mv88e6xxx_info mv88e6xxx_table[] = {
5690 [MV88E6020] = {
5691 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6020,
5692 .family = MV88E6XXX_FAMILY_6250,
5693 .name = "Marvell 88E6020",
5694 .num_databases = 64,
5695 /* Ports 2-4 are not routed to pins
5696 * => usable ports 0, 1, 5, 6
5697 */
5698 .num_ports = 7,
5699 .num_internal_phys = 2,
5700 .invalid_port_mask = BIT(2) | BIT(3) | BIT(4),
5701 .max_vid = 4095,
5702 .port_base_addr = 0x8,
5703 .phy_base_addr = 0x0,
5704 .global1_addr = 0xf,
5705 .global2_addr = 0x7,
5706 .age_time_coeff = 15000,
5707 .g1_irqs = 9,
5708 .g2_irqs = 5,
5709 .atu_move_port_mask = 0xf,
5710 .dual_chip = true,
5711 .ops = &mv88e6250_ops,
5712 },
5713
5714 [MV88E6071] = {
5715 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6071,
5716 .family = MV88E6XXX_FAMILY_6250,
5717 .name = "Marvell 88E6071",
5718 .num_databases = 64,
5719 .num_ports = 7,
5720 .num_internal_phys = 5,
5721 .max_vid = 4095,
5722 .port_base_addr = 0x08,
5723 .phy_base_addr = 0x00,
5724 .global1_addr = 0x0f,
5725 .global2_addr = 0x07,
5726 .age_time_coeff = 15000,
5727 .g1_irqs = 9,
5728 .g2_irqs = 5,
5729 .atu_move_port_mask = 0xf,
5730 .dual_chip = true,
5731 .ops = &mv88e6250_ops,
5732 },
5733
5734 [MV88E6085] = {
5735 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6085,
5736 .family = MV88E6XXX_FAMILY_6097,
5737 .name = "Marvell 88E6085",
5738 .num_databases = 4096,
5739 .num_macs = 8192,
5740 .num_ports = 10,
5741 .num_internal_phys = 5,
5742 .max_vid = 4095,
5743 .max_sid = 63,
5744 .port_base_addr = 0x10,
5745 .phy_base_addr = 0x0,
5746 .global1_addr = 0x1b,
5747 .global2_addr = 0x1c,
5748 .age_time_coeff = 15000,
5749 .g1_irqs = 8,
5750 .g2_irqs = 10,
5751 .atu_move_port_mask = 0xf,
5752 .pvt = true,
5753 .multi_chip = true,
5754 .ops = &mv88e6085_ops,
5755 },
5756
5757 [MV88E6095] = {
5758 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6095,
5759 .family = MV88E6XXX_FAMILY_6095,
5760 .name = "Marvell 88E6095/88E6095F",
5761 .num_databases = 256,
5762 .num_macs = 8192,
5763 .num_ports = 11,
5764 .num_internal_phys = 0,
5765 .max_vid = 4095,
5766 .port_base_addr = 0x10,
5767 .phy_base_addr = 0x0,
5768 .global1_addr = 0x1b,
5769 .global2_addr = 0x1c,
5770 .age_time_coeff = 15000,
5771 .g1_irqs = 8,
5772 .atu_move_port_mask = 0xf,
5773 .multi_chip = true,
5774 .ops = &mv88e6095_ops,
5775 },
5776
5777 [MV88E6097] = {
5778 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6097,
5779 .family = MV88E6XXX_FAMILY_6097,
5780 .name = "Marvell 88E6097/88E6097F",
5781 .num_databases = 4096,
5782 .num_macs = 8192,
5783 .num_ports = 11,
5784 .num_internal_phys = 8,
5785 .max_vid = 4095,
5786 .max_sid = 63,
5787 .port_base_addr = 0x10,
5788 .phy_base_addr = 0x0,
5789 .global1_addr = 0x1b,
5790 .global2_addr = 0x1c,
5791 .age_time_coeff = 15000,
5792 .g1_irqs = 8,
5793 .g2_irqs = 10,
5794 .atu_move_port_mask = 0xf,
5795 .pvt = true,
5796 .multi_chip = true,
5797 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
5798 .ops = &mv88e6097_ops,
5799 },
5800
5801 [MV88E6123] = {
5802 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6123,
5803 .family = MV88E6XXX_FAMILY_6165,
5804 .name = "Marvell 88E6123",
5805 .num_databases = 4096,
5806 .num_macs = 1024,
5807 .num_ports = 3,
5808 .num_internal_phys = 5,
5809 .max_vid = 4095,
5810 .max_sid = 63,
5811 .port_base_addr = 0x10,
5812 .phy_base_addr = 0x0,
5813 .global1_addr = 0x1b,
5814 .global2_addr = 0x1c,
5815 .age_time_coeff = 15000,
5816 .g1_irqs = 9,
5817 .g2_irqs = 10,
5818 .atu_move_port_mask = 0xf,
5819 .pvt = true,
5820 .multi_chip = true,
5821 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
5822 .ops = &mv88e6123_ops,
5823 },
5824
5825 [MV88E6131] = {
5826 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6131,
5827 .family = MV88E6XXX_FAMILY_6185,
5828 .name = "Marvell 88E6131",
5829 .num_databases = 256,
5830 .num_macs = 8192,
5831 .num_ports = 8,
5832 .num_internal_phys = 0,
5833 .max_vid = 4095,
5834 .port_base_addr = 0x10,
5835 .phy_base_addr = 0x0,
5836 .global1_addr = 0x1b,
5837 .global2_addr = 0x1c,
5838 .age_time_coeff = 15000,
5839 .g1_irqs = 9,
5840 .atu_move_port_mask = 0xf,
5841 .multi_chip = true,
5842 .ops = &mv88e6131_ops,
5843 },
5844
5845 [MV88E6141] = {
5846 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6141,
5847 .family = MV88E6XXX_FAMILY_6341,
5848 .name = "Marvell 88E6141",
5849 .num_databases = 256,
5850 .num_macs = 2048,
5851 .num_ports = 6,
5852 .num_internal_phys = 5,
5853 .num_gpio = 11,
5854 .max_vid = 4095,
5855 .max_sid = 63,
5856 .port_base_addr = 0x10,
5857 .phy_base_addr = 0x10,
5858 .global1_addr = 0x1b,
5859 .global2_addr = 0x1c,
5860 .age_time_coeff = 3750,
5861 .atu_move_port_mask = 0xf,
5862 .g1_irqs = 9,
5863 .g2_irqs = 10,
5864 .pvt = true,
5865 .multi_chip = true,
5866 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
5867 .ops = &mv88e6141_ops,
5868 },
5869
5870 [MV88E6161] = {
5871 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6161,
5872 .family = MV88E6XXX_FAMILY_6165,
5873 .name = "Marvell 88E6161",
5874 .num_databases = 4096,
5875 .num_macs = 1024,
5876 .num_ports = 6,
5877 .num_internal_phys = 5,
5878 .max_vid = 4095,
5879 .max_sid = 63,
5880 .port_base_addr = 0x10,
5881 .phy_base_addr = 0x0,
5882 .global1_addr = 0x1b,
5883 .global2_addr = 0x1c,
5884 .age_time_coeff = 15000,
5885 .g1_irqs = 9,
5886 .g2_irqs = 10,
5887 .atu_move_port_mask = 0xf,
5888 .pvt = true,
5889 .multi_chip = true,
5890 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
5891 .ptp_support = true,
5892 .ops = &mv88e6161_ops,
5893 },
5894
5895 [MV88E6165] = {
5896 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6165,
5897 .family = MV88E6XXX_FAMILY_6165,
5898 .name = "Marvell 88E6165",
5899 .num_databases = 4096,
5900 .num_macs = 8192,
5901 .num_ports = 6,
5902 .num_internal_phys = 0,
5903 .max_vid = 4095,
5904 .max_sid = 63,
5905 .port_base_addr = 0x10,
5906 .phy_base_addr = 0x0,
5907 .global1_addr = 0x1b,
5908 .global2_addr = 0x1c,
5909 .age_time_coeff = 15000,
5910 .g1_irqs = 9,
5911 .g2_irqs = 10,
5912 .atu_move_port_mask = 0xf,
5913 .pvt = true,
5914 .multi_chip = true,
5915 .ptp_support = true,
5916 .ops = &mv88e6165_ops,
5917 },
5918
5919 [MV88E6171] = {
5920 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6171,
5921 .family = MV88E6XXX_FAMILY_6351,
5922 .name = "Marvell 88E6171",
5923 .num_databases = 4096,
5924 .num_macs = 8192,
5925 .num_ports = 7,
5926 .num_internal_phys = 5,
5927 .max_vid = 4095,
5928 .max_sid = 63,
5929 .port_base_addr = 0x10,
5930 .phy_base_addr = 0x0,
5931 .global1_addr = 0x1b,
5932 .global2_addr = 0x1c,
5933 .age_time_coeff = 15000,
5934 .g1_irqs = 9,
5935 .g2_irqs = 10,
5936 .atu_move_port_mask = 0xf,
5937 .pvt = true,
5938 .multi_chip = true,
5939 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
5940 .ops = &mv88e6171_ops,
5941 },
5942
5943 [MV88E6172] = {
5944 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6172,
5945 .family = MV88E6XXX_FAMILY_6352,
5946 .name = "Marvell 88E6172",
5947 .num_databases = 4096,
5948 .num_macs = 8192,
5949 .num_ports = 7,
5950 .num_internal_phys = 5,
5951 .num_gpio = 15,
5952 .max_vid = 4095,
5953 .max_sid = 63,
5954 .port_base_addr = 0x10,
5955 .phy_base_addr = 0x0,
5956 .global1_addr = 0x1b,
5957 .global2_addr = 0x1c,
5958 .age_time_coeff = 15000,
5959 .g1_irqs = 9,
5960 .g2_irqs = 10,
5961 .atu_move_port_mask = 0xf,
5962 .pvt = true,
5963 .multi_chip = true,
5964 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
5965 .ops = &mv88e6172_ops,
5966 },
5967
5968 [MV88E6175] = {
5969 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6175,
5970 .family = MV88E6XXX_FAMILY_6351,
5971 .name = "Marvell 88E6175",
5972 .num_databases = 4096,
5973 .num_macs = 8192,
5974 .num_ports = 7,
5975 .num_internal_phys = 5,
5976 .max_vid = 4095,
5977 .max_sid = 63,
5978 .port_base_addr = 0x10,
5979 .phy_base_addr = 0x0,
5980 .global1_addr = 0x1b,
5981 .global2_addr = 0x1c,
5982 .age_time_coeff = 15000,
5983 .g1_irqs = 9,
5984 .g2_irqs = 10,
5985 .atu_move_port_mask = 0xf,
5986 .pvt = true,
5987 .multi_chip = true,
5988 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
5989 .ops = &mv88e6175_ops,
5990 },
5991
5992 [MV88E6176] = {
5993 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6176,
5994 .family = MV88E6XXX_FAMILY_6352,
5995 .name = "Marvell 88E6176",
5996 .num_databases = 4096,
5997 .num_macs = 8192,
5998 .num_ports = 7,
5999 .num_internal_phys = 5,
6000 .num_gpio = 15,
6001 .max_vid = 4095,
6002 .max_sid = 63,
6003 .port_base_addr = 0x10,
6004 .phy_base_addr = 0x0,
6005 .global1_addr = 0x1b,
6006 .global2_addr = 0x1c,
6007 .age_time_coeff = 15000,
6008 .g1_irqs = 9,
6009 .g2_irqs = 10,
6010 .atu_move_port_mask = 0xf,
6011 .pvt = true,
6012 .multi_chip = true,
6013 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
6014 .ops = &mv88e6176_ops,
6015 },
6016
6017 [MV88E6185] = {
6018 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6185,
6019 .family = MV88E6XXX_FAMILY_6185,
6020 .name = "Marvell 88E6185",
6021 .num_databases = 256,
6022 .num_macs = 8192,
6023 .num_ports = 10,
6024 .num_internal_phys = 0,
6025 .max_vid = 4095,
6026 .port_base_addr = 0x10,
6027 .phy_base_addr = 0x0,
6028 .global1_addr = 0x1b,
6029 .global2_addr = 0x1c,
6030 .age_time_coeff = 15000,
6031 .g1_irqs = 8,
6032 .atu_move_port_mask = 0xf,
6033 .multi_chip = true,
6034 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
6035 .ops = &mv88e6185_ops,
6036 },
6037
6038 [MV88E6190] = {
6039 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6190,
6040 .family = MV88E6XXX_FAMILY_6390,
6041 .name = "Marvell 88E6190",
6042 .num_databases = 4096,
6043 .num_macs = 16384,
6044 .num_ports = 11, /* 10 + Z80 */
6045 .num_internal_phys = 9,
6046 .num_gpio = 16,
6047 .max_vid = 8191,
6048 .max_sid = 63,
6049 .port_base_addr = 0x0,
6050 .phy_base_addr = 0x0,
6051 .global1_addr = 0x1b,
6052 .global2_addr = 0x1c,
6053 .age_time_coeff = 3750,
6054 .g1_irqs = 9,
6055 .g2_irqs = 14,
6056 .pvt = true,
6057 .multi_chip = true,
6058 .atu_move_port_mask = 0x1f,
6059 .ops = &mv88e6190_ops,
6060 },
6061
6062 [MV88E6190X] = {
6063 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6190X,
6064 .family = MV88E6XXX_FAMILY_6390,
6065 .name = "Marvell 88E6190X",
6066 .num_databases = 4096,
6067 .num_macs = 16384,
6068 .num_ports = 11, /* 10 + Z80 */
6069 .num_internal_phys = 9,
6070 .num_gpio = 16,
6071 .max_vid = 8191,
6072 .max_sid = 63,
6073 .port_base_addr = 0x0,
6074 .phy_base_addr = 0x0,
6075 .global1_addr = 0x1b,
6076 .global2_addr = 0x1c,
6077 .age_time_coeff = 3750,
6078 .g1_irqs = 9,
6079 .g2_irqs = 14,
6080 .atu_move_port_mask = 0x1f,
6081 .pvt = true,
6082 .multi_chip = true,
6083 .ops = &mv88e6190x_ops,
6084 },
6085
6086 [MV88E6191] = {
6087 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6191,
6088 .family = MV88E6XXX_FAMILY_6390,
6089 .name = "Marvell 88E6191",
6090 .num_databases = 4096,
6091 .num_macs = 16384,
6092 .num_ports = 11, /* 10 + Z80 */
6093 .num_internal_phys = 9,
6094 .max_vid = 8191,
6095 .max_sid = 63,
6096 .port_base_addr = 0x0,
6097 .phy_base_addr = 0x0,
6098 .global1_addr = 0x1b,
6099 .global2_addr = 0x1c,
6100 .age_time_coeff = 3750,
6101 .g1_irqs = 9,
6102 .g2_irqs = 14,
6103 .atu_move_port_mask = 0x1f,
6104 .pvt = true,
6105 .multi_chip = true,
6106 .ptp_support = true,
6107 .ops = &mv88e6191_ops,
6108 },
6109
6110 [MV88E6191X] = {
6111 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6191X,
6112 .family = MV88E6XXX_FAMILY_6393,
6113 .name = "Marvell 88E6191X",
6114 .num_databases = 4096,
6115 .num_ports = 11, /* 10 + Z80 */
6116 .num_internal_phys = 8,
6117 .internal_phys_offset = 1,
6118 .max_vid = 8191,
6119 .max_sid = 63,
6120 .port_base_addr = 0x0,
6121 .phy_base_addr = 0x0,
6122 .global1_addr = 0x1b,
6123 .global2_addr = 0x1c,
6124 .age_time_coeff = 3750,
6125 .g1_irqs = 10,
6126 .g2_irqs = 14,
6127 .atu_move_port_mask = 0x1f,
6128 .pvt = true,
6129 .multi_chip = true,
6130 .ptp_support = true,
6131 .ops = &mv88e6393x_ops,
6132 },
6133
6134 [MV88E6193X] = {
6135 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6193X,
6136 .family = MV88E6XXX_FAMILY_6393,
6137 .name = "Marvell 88E6193X",
6138 .num_databases = 4096,
6139 .num_ports = 11, /* 10 + Z80 */
6140 .num_internal_phys = 8,
6141 .internal_phys_offset = 1,
6142 .max_vid = 8191,
6143 .max_sid = 63,
6144 .port_base_addr = 0x0,
6145 .phy_base_addr = 0x0,
6146 .global1_addr = 0x1b,
6147 .global2_addr = 0x1c,
6148 .age_time_coeff = 3750,
6149 .g1_irqs = 10,
6150 .g2_irqs = 14,
6151 .atu_move_port_mask = 0x1f,
6152 .pvt = true,
6153 .multi_chip = true,
6154 .ptp_support = true,
6155 .ops = &mv88e6393x_ops,
6156 },
6157
6158 [MV88E6220] = {
6159 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6220,
6160 .family = MV88E6XXX_FAMILY_6250,
6161 .name = "Marvell 88E6220",
6162 .num_databases = 64,
6163
6164 /* Ports 2-4 are not routed to pins
6165 * => usable ports 0, 1, 5, 6
6166 */
6167 .num_ports = 7,
6168 .num_internal_phys = 2,
6169 .invalid_port_mask = BIT(2) | BIT(3) | BIT(4),
6170 .max_vid = 4095,
6171 .port_base_addr = 0x08,
6172 .phy_base_addr = 0x00,
6173 .global1_addr = 0x0f,
6174 .global2_addr = 0x07,
6175 .age_time_coeff = 15000,
6176 .g1_irqs = 9,
6177 .g2_irqs = 10,
6178 .atu_move_port_mask = 0xf,
6179 .dual_chip = true,
6180 .ptp_support = true,
6181 .ops = &mv88e6250_ops,
6182 },
6183
6184 [MV88E6240] = {
6185 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6240,
6186 .family = MV88E6XXX_FAMILY_6352,
6187 .name = "Marvell 88E6240",
6188 .num_databases = 4096,
6189 .num_macs = 8192,
6190 .num_ports = 7,
6191 .num_internal_phys = 5,
6192 .num_gpio = 15,
6193 .max_vid = 4095,
6194 .max_sid = 63,
6195 .port_base_addr = 0x10,
6196 .phy_base_addr = 0x0,
6197 .global1_addr = 0x1b,
6198 .global2_addr = 0x1c,
6199 .age_time_coeff = 15000,
6200 .g1_irqs = 9,
6201 .g2_irqs = 10,
6202 .atu_move_port_mask = 0xf,
6203 .pvt = true,
6204 .multi_chip = true,
6205 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
6206 .ptp_support = true,
6207 .ops = &mv88e6240_ops,
6208 },
6209
6210 [MV88E6250] = {
6211 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6250,
6212 .family = MV88E6XXX_FAMILY_6250,
6213 .name = "Marvell 88E6250",
6214 .num_databases = 64,
6215 .num_ports = 7,
6216 .num_internal_phys = 5,
6217 .max_vid = 4095,
6218 .port_base_addr = 0x08,
6219 .phy_base_addr = 0x00,
6220 .global1_addr = 0x0f,
6221 .global2_addr = 0x07,
6222 .age_time_coeff = 15000,
6223 .g1_irqs = 9,
6224 .g2_irqs = 10,
6225 .atu_move_port_mask = 0xf,
6226 .dual_chip = true,
6227 .ptp_support = true,
6228 .ops = &mv88e6250_ops,
6229 },
6230
6231 [MV88E6290] = {
6232 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6290,
6233 .family = MV88E6XXX_FAMILY_6390,
6234 .name = "Marvell 88E6290",
6235 .num_databases = 4096,
6236 .num_ports = 11, /* 10 + Z80 */
6237 .num_internal_phys = 9,
6238 .num_gpio = 16,
6239 .max_vid = 8191,
6240 .max_sid = 63,
6241 .port_base_addr = 0x0,
6242 .phy_base_addr = 0x0,
6243 .global1_addr = 0x1b,
6244 .global2_addr = 0x1c,
6245 .age_time_coeff = 3750,
6246 .g1_irqs = 9,
6247 .g2_irqs = 14,
6248 .atu_move_port_mask = 0x1f,
6249 .pvt = true,
6250 .multi_chip = true,
6251 .ptp_support = true,
6252 .ops = &mv88e6290_ops,
6253 },
6254
6255 [MV88E6320] = {
6256 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6320,
6257 .family = MV88E6XXX_FAMILY_6320,
6258 .name = "Marvell 88E6320",
6259 .num_databases = 4096,
6260 .num_macs = 8192,
6261 .num_ports = 7,
6262 .num_internal_phys = 5,
6263 .num_gpio = 15,
6264 .max_vid = 4095,
6265 .max_sid = 63,
6266 .port_base_addr = 0x10,
6267 .phy_base_addr = 0x0,
6268 .global1_addr = 0x1b,
6269 .global2_addr = 0x1c,
6270 .age_time_coeff = 15000,
6271 .g1_irqs = 8,
6272 .g2_irqs = 10,
6273 .atu_move_port_mask = 0xf,
6274 .pvt = true,
6275 .multi_chip = true,
6276 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
6277 .ptp_support = true,
6278 .ops = &mv88e6320_ops,
6279 },
6280
6281 [MV88E6321] = {
6282 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6321,
6283 .family = MV88E6XXX_FAMILY_6320,
6284 .name = "Marvell 88E6321",
6285 .num_databases = 4096,
6286 .num_macs = 8192,
6287 .num_ports = 7,
6288 .num_internal_phys = 5,
6289 .num_gpio = 15,
6290 .max_vid = 4095,
6291 .max_sid = 63,
6292 .port_base_addr = 0x10,
6293 .phy_base_addr = 0x0,
6294 .global1_addr = 0x1b,
6295 .global2_addr = 0x1c,
6296 .age_time_coeff = 15000,
6297 .g1_irqs = 8,
6298 .g2_irqs = 10,
6299 .atu_move_port_mask = 0xf,
6300 .pvt = true,
6301 .multi_chip = true,
6302 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
6303 .ptp_support = true,
6304 .ops = &mv88e6321_ops,
6305 },
6306
6307 [MV88E6341] = {
6308 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6341,
6309 .family = MV88E6XXX_FAMILY_6341,
6310 .name = "Marvell 88E6341",
6311 .num_databases = 256,
6312 .num_macs = 2048,
6313 .num_internal_phys = 5,
6314 .num_ports = 6,
6315 .num_gpio = 11,
6316 .max_vid = 4095,
6317 .max_sid = 63,
6318 .port_base_addr = 0x10,
6319 .phy_base_addr = 0x10,
6320 .global1_addr = 0x1b,
6321 .global2_addr = 0x1c,
6322 .age_time_coeff = 3750,
6323 .atu_move_port_mask = 0xf,
6324 .g1_irqs = 9,
6325 .g2_irqs = 10,
6326 .pvt = true,
6327 .multi_chip = true,
6328 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
6329 .ptp_support = true,
6330 .ops = &mv88e6341_ops,
6331 },
6332
6333 [MV88E6350] = {
6334 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6350,
6335 .family = MV88E6XXX_FAMILY_6351,
6336 .name = "Marvell 88E6350",
6337 .num_databases = 4096,
6338 .num_macs = 8192,
6339 .num_ports = 7,
6340 .num_internal_phys = 5,
6341 .max_vid = 4095,
6342 .max_sid = 63,
6343 .port_base_addr = 0x10,
6344 .phy_base_addr = 0x0,
6345 .global1_addr = 0x1b,
6346 .global2_addr = 0x1c,
6347 .age_time_coeff = 15000,
6348 .g1_irqs = 9,
6349 .g2_irqs = 10,
6350 .atu_move_port_mask = 0xf,
6351 .pvt = true,
6352 .multi_chip = true,
6353 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
6354 .ops = &mv88e6350_ops,
6355 },
6356
6357 [MV88E6351] = {
6358 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6351,
6359 .family = MV88E6XXX_FAMILY_6351,
6360 .name = "Marvell 88E6351",
6361 .num_databases = 4096,
6362 .num_macs = 8192,
6363 .num_ports = 7,
6364 .num_internal_phys = 5,
6365 .max_vid = 4095,
6366 .max_sid = 63,
6367 .port_base_addr = 0x10,
6368 .phy_base_addr = 0x0,
6369 .global1_addr = 0x1b,
6370 .global2_addr = 0x1c,
6371 .age_time_coeff = 15000,
6372 .g1_irqs = 9,
6373 .g2_irqs = 10,
6374 .atu_move_port_mask = 0xf,
6375 .pvt = true,
6376 .multi_chip = true,
6377 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
6378 .ops = &mv88e6351_ops,
6379 },
6380
6381 [MV88E6352] = {
6382 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6352,
6383 .family = MV88E6XXX_FAMILY_6352,
6384 .name = "Marvell 88E6352",
6385 .num_databases = 4096,
6386 .num_macs = 8192,
6387 .num_ports = 7,
6388 .num_internal_phys = 5,
6389 .num_gpio = 15,
6390 .max_vid = 4095,
6391 .max_sid = 63,
6392 .port_base_addr = 0x10,
6393 .phy_base_addr = 0x0,
6394 .global1_addr = 0x1b,
6395 .global2_addr = 0x1c,
6396 .age_time_coeff = 15000,
6397 .g1_irqs = 9,
6398 .g2_irqs = 10,
6399 .atu_move_port_mask = 0xf,
6400 .pvt = true,
6401 .multi_chip = true,
6402 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
6403 .ptp_support = true,
6404 .ops = &mv88e6352_ops,
6405 },
6406 [MV88E6361] = {
6407 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6361,
6408 .family = MV88E6XXX_FAMILY_6393,
6409 .name = "Marvell 88E6361",
6410 .num_databases = 4096,
6411 .num_macs = 16384,
6412 .num_ports = 11,
6413 /* Ports 1, 2 and 8 are not routed */
6414 .invalid_port_mask = BIT(1) | BIT(2) | BIT(8),
6415 .num_internal_phys = 5,
6416 .internal_phys_offset = 3,
6417 .max_vid = 8191,
6418 .max_sid = 63,
6419 .port_base_addr = 0x0,
6420 .phy_base_addr = 0x0,
6421 .global1_addr = 0x1b,
6422 .global2_addr = 0x1c,
6423 .age_time_coeff = 3750,
6424 .g1_irqs = 10,
6425 .g2_irqs = 14,
6426 .atu_move_port_mask = 0x1f,
6427 .pvt = true,
6428 .multi_chip = true,
6429 .ptp_support = true,
6430 .ops = &mv88e6393x_ops,
6431 },
6432 [MV88E6390] = {
6433 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6390,
6434 .family = MV88E6XXX_FAMILY_6390,
6435 .name = "Marvell 88E6390",
6436 .num_databases = 4096,
6437 .num_macs = 16384,
6438 .num_ports = 11, /* 10 + Z80 */
6439 .num_internal_phys = 9,
6440 .num_gpio = 16,
6441 .max_vid = 8191,
6442 .max_sid = 63,
6443 .port_base_addr = 0x0,
6444 .phy_base_addr = 0x0,
6445 .global1_addr = 0x1b,
6446 .global2_addr = 0x1c,
6447 .age_time_coeff = 3750,
6448 .g1_irqs = 9,
6449 .g2_irqs = 14,
6450 .atu_move_port_mask = 0x1f,
6451 .pvt = true,
6452 .multi_chip = true,
6453 .edsa_support = MV88E6XXX_EDSA_UNDOCUMENTED,
6454 .ptp_support = true,
6455 .ops = &mv88e6390_ops,
6456 },
6457 [MV88E6390X] = {
6458 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6390X,
6459 .family = MV88E6XXX_FAMILY_6390,
6460 .name = "Marvell 88E6390X",
6461 .num_databases = 4096,
6462 .num_macs = 16384,
6463 .num_ports = 11, /* 10 + Z80 */
6464 .num_internal_phys = 9,
6465 .num_gpio = 16,
6466 .max_vid = 8191,
6467 .max_sid = 63,
6468 .port_base_addr = 0x0,
6469 .phy_base_addr = 0x0,
6470 .global1_addr = 0x1b,
6471 .global2_addr = 0x1c,
6472 .age_time_coeff = 3750,
6473 .g1_irqs = 9,
6474 .g2_irqs = 14,
6475 .atu_move_port_mask = 0x1f,
6476 .pvt = true,
6477 .multi_chip = true,
6478 .edsa_support = MV88E6XXX_EDSA_UNDOCUMENTED,
6479 .ptp_support = true,
6480 .ops = &mv88e6390x_ops,
6481 },
6482
6483 [MV88E6393X] = {
6484 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6393X,
6485 .family = MV88E6XXX_FAMILY_6393,
6486 .name = "Marvell 88E6393X",
6487 .num_databases = 4096,
6488 .num_ports = 11, /* 10 + Z80 */
6489 .num_internal_phys = 8,
6490 .internal_phys_offset = 1,
6491 .max_vid = 8191,
6492 .max_sid = 63,
6493 .port_base_addr = 0x0,
6494 .phy_base_addr = 0x0,
6495 .global1_addr = 0x1b,
6496 .global2_addr = 0x1c,
6497 .age_time_coeff = 3750,
6498 .g1_irqs = 10,
6499 .g2_irqs = 14,
6500 .atu_move_port_mask = 0x1f,
6501 .pvt = true,
6502 .multi_chip = true,
6503 .ptp_support = true,
6504 .ops = &mv88e6393x_ops,
6505 },
6506 };
6507
mv88e6xxx_lookup_info(unsigned int prod_num)6508 static const struct mv88e6xxx_info *mv88e6xxx_lookup_info(unsigned int prod_num)
6509 {
6510 int i;
6511
6512 for (i = 0; i < ARRAY_SIZE(mv88e6xxx_table); ++i)
6513 if (mv88e6xxx_table[i].prod_num == prod_num)
6514 return &mv88e6xxx_table[i];
6515
6516 return NULL;
6517 }
6518
mv88e6xxx_detect(struct mv88e6xxx_chip * chip)6519 static int mv88e6xxx_detect(struct mv88e6xxx_chip *chip)
6520 {
6521 const struct mv88e6xxx_info *info;
6522 unsigned int prod_num, rev;
6523 u16 id;
6524 int err;
6525
6526 mv88e6xxx_reg_lock(chip);
6527 err = mv88e6xxx_port_read(chip, 0, MV88E6XXX_PORT_SWITCH_ID, &id);
6528 mv88e6xxx_reg_unlock(chip);
6529 if (err)
6530 return err;
6531
6532 prod_num = id & MV88E6XXX_PORT_SWITCH_ID_PROD_MASK;
6533 rev = id & MV88E6XXX_PORT_SWITCH_ID_REV_MASK;
6534
6535 info = mv88e6xxx_lookup_info(prod_num);
6536 if (!info)
6537 return -ENODEV;
6538
6539 /* Update the compatible info with the probed one */
6540 chip->info = info;
6541
6542 dev_info(chip->dev, "switch 0x%x detected: %s, revision %u\n",
6543 chip->info->prod_num, chip->info->name, rev);
6544
6545 return 0;
6546 }
6547
mv88e6xxx_single_chip_detect(struct mv88e6xxx_chip * chip,struct mdio_device * mdiodev)6548 static int mv88e6xxx_single_chip_detect(struct mv88e6xxx_chip *chip,
6549 struct mdio_device *mdiodev)
6550 {
6551 int err;
6552
6553 /* dual_chip takes precedence over single/multi-chip modes */
6554 if (chip->info->dual_chip)
6555 return -EINVAL;
6556
6557 /* If the mdio addr is 16 indicating the first port address of a switch
6558 * (e.g. mv88e6*41) in single chip addressing mode the device may be
6559 * configured in single chip addressing mode. Setup the smi access as
6560 * single chip addressing mode and attempt to detect the model of the
6561 * switch, if this fails the device is not configured in single chip
6562 * addressing mode.
6563 */
6564 if (mdiodev->addr != 16)
6565 return -EINVAL;
6566
6567 err = mv88e6xxx_smi_init(chip, mdiodev->bus, 0);
6568 if (err)
6569 return err;
6570
6571 return mv88e6xxx_detect(chip);
6572 }
6573
mv88e6xxx_alloc_chip(struct device * dev)6574 static struct mv88e6xxx_chip *mv88e6xxx_alloc_chip(struct device *dev)
6575 {
6576 struct mv88e6xxx_chip *chip;
6577
6578 chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL);
6579 if (!chip)
6580 return NULL;
6581
6582 chip->dev = dev;
6583
6584 mutex_init(&chip->reg_lock);
6585 INIT_LIST_HEAD(&chip->mdios);
6586 idr_init(&chip->policies);
6587 INIT_LIST_HEAD(&chip->msts);
6588
6589 return chip;
6590 }
6591
mv88e6xxx_get_tag_protocol(struct dsa_switch * ds,int port,enum dsa_tag_protocol m)6592 static enum dsa_tag_protocol mv88e6xxx_get_tag_protocol(struct dsa_switch *ds,
6593 int port,
6594 enum dsa_tag_protocol m)
6595 {
6596 struct mv88e6xxx_chip *chip = ds->priv;
6597
6598 return chip->tag_protocol;
6599 }
6600
mv88e6xxx_change_tag_protocol(struct dsa_switch * ds,enum dsa_tag_protocol proto)6601 static int mv88e6xxx_change_tag_protocol(struct dsa_switch *ds,
6602 enum dsa_tag_protocol proto)
6603 {
6604 struct mv88e6xxx_chip *chip = ds->priv;
6605 enum dsa_tag_protocol old_protocol;
6606 struct dsa_port *cpu_dp;
6607 int err;
6608
6609 switch (proto) {
6610 case DSA_TAG_PROTO_EDSA:
6611 switch (chip->info->edsa_support) {
6612 case MV88E6XXX_EDSA_UNSUPPORTED:
6613 return -EPROTONOSUPPORT;
6614 case MV88E6XXX_EDSA_UNDOCUMENTED:
6615 dev_warn(chip->dev, "Relying on undocumented EDSA tagging behavior\n");
6616 fallthrough;
6617 case MV88E6XXX_EDSA_SUPPORTED:
6618 break;
6619 }
6620 break;
6621 case DSA_TAG_PROTO_DSA:
6622 break;
6623 default:
6624 return -EPROTONOSUPPORT;
6625 }
6626
6627 old_protocol = chip->tag_protocol;
6628 chip->tag_protocol = proto;
6629
6630 mv88e6xxx_reg_lock(chip);
6631 dsa_switch_for_each_cpu_port(cpu_dp, ds) {
6632 err = mv88e6xxx_setup_port_mode(chip, cpu_dp->index);
6633 if (err) {
6634 mv88e6xxx_reg_unlock(chip);
6635 goto unwind;
6636 }
6637 }
6638 mv88e6xxx_reg_unlock(chip);
6639
6640 return 0;
6641
6642 unwind:
6643 chip->tag_protocol = old_protocol;
6644
6645 mv88e6xxx_reg_lock(chip);
6646 dsa_switch_for_each_cpu_port_continue_reverse(cpu_dp, ds)
6647 mv88e6xxx_setup_port_mode(chip, cpu_dp->index);
6648 mv88e6xxx_reg_unlock(chip);
6649
6650 return err;
6651 }
6652
mv88e6xxx_port_mdb_add(struct dsa_switch * ds,int port,const struct switchdev_obj_port_mdb * mdb,struct dsa_db db)6653 static int mv88e6xxx_port_mdb_add(struct dsa_switch *ds, int port,
6654 const struct switchdev_obj_port_mdb *mdb,
6655 struct dsa_db db)
6656 {
6657 struct mv88e6xxx_chip *chip = ds->priv;
6658 int err;
6659
6660 mv88e6xxx_reg_lock(chip);
6661 err = mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid,
6662 MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC);
6663 if (err)
6664 goto out;
6665
6666 if (!mv88e6xxx_port_db_find(chip, mdb->addr, mdb->vid))
6667 err = -ENOSPC;
6668
6669 out:
6670 mv88e6xxx_reg_unlock(chip);
6671
6672 return err;
6673 }
6674
mv88e6xxx_port_mdb_del(struct dsa_switch * ds,int port,const struct switchdev_obj_port_mdb * mdb,struct dsa_db db)6675 static int mv88e6xxx_port_mdb_del(struct dsa_switch *ds, int port,
6676 const struct switchdev_obj_port_mdb *mdb,
6677 struct dsa_db db)
6678 {
6679 struct mv88e6xxx_chip *chip = ds->priv;
6680 int err;
6681
6682 mv88e6xxx_reg_lock(chip);
6683 err = mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid, 0);
6684 mv88e6xxx_reg_unlock(chip);
6685
6686 return err;
6687 }
6688
mv88e6xxx_port_mirror_add(struct dsa_switch * ds,int port,struct dsa_mall_mirror_tc_entry * mirror,bool ingress,struct netlink_ext_ack * extack)6689 static int mv88e6xxx_port_mirror_add(struct dsa_switch *ds, int port,
6690 struct dsa_mall_mirror_tc_entry *mirror,
6691 bool ingress,
6692 struct netlink_ext_ack *extack)
6693 {
6694 enum mv88e6xxx_egress_direction direction = ingress ?
6695 MV88E6XXX_EGRESS_DIR_INGRESS :
6696 MV88E6XXX_EGRESS_DIR_EGRESS;
6697 struct mv88e6xxx_chip *chip = ds->priv;
6698 bool other_mirrors = false;
6699 int i;
6700 int err;
6701
6702 mutex_lock(&chip->reg_lock);
6703 if ((ingress ? chip->ingress_dest_port : chip->egress_dest_port) !=
6704 mirror->to_local_port) {
6705 for (i = 0; i < mv88e6xxx_num_ports(chip); i++)
6706 other_mirrors |= ingress ?
6707 chip->ports[i].mirror_ingress :
6708 chip->ports[i].mirror_egress;
6709
6710 /* Can't change egress port when other mirror is active */
6711 if (other_mirrors) {
6712 err = -EBUSY;
6713 goto out;
6714 }
6715
6716 err = mv88e6xxx_set_egress_port(chip, direction,
6717 mirror->to_local_port);
6718 if (err)
6719 goto out;
6720 }
6721
6722 err = mv88e6xxx_port_set_mirror(chip, port, direction, true);
6723 out:
6724 mutex_unlock(&chip->reg_lock);
6725
6726 return err;
6727 }
6728
mv88e6xxx_port_mirror_del(struct dsa_switch * ds,int port,struct dsa_mall_mirror_tc_entry * mirror)6729 static void mv88e6xxx_port_mirror_del(struct dsa_switch *ds, int port,
6730 struct dsa_mall_mirror_tc_entry *mirror)
6731 {
6732 enum mv88e6xxx_egress_direction direction = mirror->ingress ?
6733 MV88E6XXX_EGRESS_DIR_INGRESS :
6734 MV88E6XXX_EGRESS_DIR_EGRESS;
6735 struct mv88e6xxx_chip *chip = ds->priv;
6736 bool other_mirrors = false;
6737 int i;
6738
6739 mutex_lock(&chip->reg_lock);
6740 if (mv88e6xxx_port_set_mirror(chip, port, direction, false))
6741 dev_err(ds->dev, "p%d: failed to disable mirroring\n", port);
6742
6743 for (i = 0; i < mv88e6xxx_num_ports(chip); i++)
6744 other_mirrors |= mirror->ingress ?
6745 chip->ports[i].mirror_ingress :
6746 chip->ports[i].mirror_egress;
6747
6748 /* Reset egress port when no other mirror is active */
6749 if (!other_mirrors) {
6750 if (mv88e6xxx_set_egress_port(chip, direction,
6751 dsa_upstream_port(ds, port)))
6752 dev_err(ds->dev, "failed to set egress port\n");
6753 }
6754
6755 mutex_unlock(&chip->reg_lock);
6756 }
6757
mv88e6xxx_port_pre_bridge_flags(struct dsa_switch * ds,int port,struct switchdev_brport_flags flags,struct netlink_ext_ack * extack)6758 static int mv88e6xxx_port_pre_bridge_flags(struct dsa_switch *ds, int port,
6759 struct switchdev_brport_flags flags,
6760 struct netlink_ext_ack *extack)
6761 {
6762 struct mv88e6xxx_chip *chip = ds->priv;
6763 const struct mv88e6xxx_ops *ops;
6764
6765 if (flags.mask & ~(BR_LEARNING | BR_FLOOD | BR_MCAST_FLOOD |
6766 BR_BCAST_FLOOD | BR_PORT_LOCKED | BR_PORT_MAB))
6767 return -EINVAL;
6768
6769 ops = chip->info->ops;
6770
6771 if ((flags.mask & BR_FLOOD) && !ops->port_set_ucast_flood)
6772 return -EINVAL;
6773
6774 if ((flags.mask & BR_MCAST_FLOOD) && !ops->port_set_mcast_flood)
6775 return -EINVAL;
6776
6777 return 0;
6778 }
6779
mv88e6xxx_port_bridge_flags(struct dsa_switch * ds,int port,struct switchdev_brport_flags flags,struct netlink_ext_ack * extack)6780 static int mv88e6xxx_port_bridge_flags(struct dsa_switch *ds, int port,
6781 struct switchdev_brport_flags flags,
6782 struct netlink_ext_ack *extack)
6783 {
6784 struct mv88e6xxx_chip *chip = ds->priv;
6785 int err = 0;
6786
6787 mv88e6xxx_reg_lock(chip);
6788
6789 if (flags.mask & BR_LEARNING) {
6790 bool learning = !!(flags.val & BR_LEARNING);
6791 u16 pav = learning ? (1 << port) : 0;
6792
6793 err = mv88e6xxx_port_set_assoc_vector(chip, port, pav);
6794 if (err)
6795 goto out;
6796 }
6797
6798 if (flags.mask & BR_FLOOD) {
6799 bool unicast = !!(flags.val & BR_FLOOD);
6800
6801 err = chip->info->ops->port_set_ucast_flood(chip, port,
6802 unicast);
6803 if (err)
6804 goto out;
6805 }
6806
6807 if (flags.mask & BR_MCAST_FLOOD) {
6808 bool multicast = !!(flags.val & BR_MCAST_FLOOD);
6809
6810 err = chip->info->ops->port_set_mcast_flood(chip, port,
6811 multicast);
6812 if (err)
6813 goto out;
6814 }
6815
6816 if (flags.mask & BR_BCAST_FLOOD) {
6817 bool broadcast = !!(flags.val & BR_BCAST_FLOOD);
6818
6819 err = mv88e6xxx_port_broadcast_sync(chip, port, broadcast);
6820 if (err)
6821 goto out;
6822 }
6823
6824 if (flags.mask & BR_PORT_MAB) {
6825 bool mab = !!(flags.val & BR_PORT_MAB);
6826
6827 mv88e6xxx_port_set_mab(chip, port, mab);
6828 }
6829
6830 if (flags.mask & BR_PORT_LOCKED) {
6831 bool locked = !!(flags.val & BR_PORT_LOCKED);
6832
6833 err = mv88e6xxx_port_set_lock(chip, port, locked);
6834 if (err)
6835 goto out;
6836 }
6837 out:
6838 mv88e6xxx_reg_unlock(chip);
6839
6840 return err;
6841 }
6842
mv88e6xxx_lag_can_offload(struct dsa_switch * ds,struct dsa_lag lag,struct netdev_lag_upper_info * info,struct netlink_ext_ack * extack)6843 static bool mv88e6xxx_lag_can_offload(struct dsa_switch *ds,
6844 struct dsa_lag lag,
6845 struct netdev_lag_upper_info *info,
6846 struct netlink_ext_ack *extack)
6847 {
6848 struct mv88e6xxx_chip *chip = ds->priv;
6849 struct dsa_port *dp;
6850 int members = 0;
6851
6852 if (!mv88e6xxx_has_lag(chip)) {
6853 NL_SET_ERR_MSG_MOD(extack, "Chip does not support LAG offload");
6854 return false;
6855 }
6856
6857 if (!lag.id)
6858 return false;
6859
6860 dsa_lag_foreach_port(dp, ds->dst, &lag)
6861 /* Includes the port joining the LAG */
6862 members++;
6863
6864 if (members > 8) {
6865 NL_SET_ERR_MSG_MOD(extack,
6866 "Cannot offload more than 8 LAG ports");
6867 return false;
6868 }
6869
6870 /* We could potentially relax this to include active
6871 * backup in the future.
6872 */
6873 if (info->tx_type != NETDEV_LAG_TX_TYPE_HASH) {
6874 NL_SET_ERR_MSG_MOD(extack,
6875 "Can only offload LAG using hash TX type");
6876 return false;
6877 }
6878
6879 /* Ideally we would also validate that the hash type matches
6880 * the hardware. Alas, this is always set to unknown on team
6881 * interfaces.
6882 */
6883 return true;
6884 }
6885
mv88e6xxx_lag_sync_map(struct dsa_switch * ds,struct dsa_lag lag)6886 static int mv88e6xxx_lag_sync_map(struct dsa_switch *ds, struct dsa_lag lag)
6887 {
6888 struct mv88e6xxx_chip *chip = ds->priv;
6889 struct dsa_port *dp;
6890 u16 map = 0;
6891 int id;
6892
6893 /* DSA LAG IDs are one-based, hardware is zero-based */
6894 id = lag.id - 1;
6895
6896 /* Build the map of all ports to distribute flows destined for
6897 * this LAG. This can be either a local user port, or a DSA
6898 * port if the LAG port is on a remote chip.
6899 */
6900 dsa_lag_foreach_port(dp, ds->dst, &lag)
6901 map |= BIT(dsa_towards_port(ds, dp->ds->index, dp->index));
6902
6903 return mv88e6xxx_g2_trunk_mapping_write(chip, id, map);
6904 }
6905
6906 static const u8 mv88e6xxx_lag_mask_table[8][8] = {
6907 /* Row number corresponds to the number of active members in a
6908 * LAG. Each column states which of the eight hash buckets are
6909 * mapped to the column:th port in the LAG.
6910 *
6911 * Example: In a LAG with three active ports, the second port
6912 * ([2][1]) would be selected for traffic mapped to buckets
6913 * 3,4,5 (0x38).
6914 */
6915 { 0xff, 0, 0, 0, 0, 0, 0, 0 },
6916 { 0x0f, 0xf0, 0, 0, 0, 0, 0, 0 },
6917 { 0x07, 0x38, 0xc0, 0, 0, 0, 0, 0 },
6918 { 0x03, 0x0c, 0x30, 0xc0, 0, 0, 0, 0 },
6919 { 0x03, 0x0c, 0x30, 0x40, 0x80, 0, 0, 0 },
6920 { 0x03, 0x0c, 0x10, 0x20, 0x40, 0x80, 0, 0 },
6921 { 0x03, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80, 0 },
6922 { 0x01, 0x02, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80 },
6923 };
6924
mv88e6xxx_lag_set_port_mask(u16 * mask,int port,int num_tx,int nth)6925 static void mv88e6xxx_lag_set_port_mask(u16 *mask, int port,
6926 int num_tx, int nth)
6927 {
6928 u8 active = 0;
6929 int i;
6930
6931 num_tx = num_tx <= 8 ? num_tx : 8;
6932 if (nth < num_tx)
6933 active = mv88e6xxx_lag_mask_table[num_tx - 1][nth];
6934
6935 for (i = 0; i < 8; i++) {
6936 if (BIT(i) & active)
6937 mask[i] |= BIT(port);
6938 }
6939 }
6940
mv88e6xxx_lag_sync_masks(struct dsa_switch * ds)6941 static int mv88e6xxx_lag_sync_masks(struct dsa_switch *ds)
6942 {
6943 struct mv88e6xxx_chip *chip = ds->priv;
6944 unsigned int id, num_tx;
6945 struct dsa_port *dp;
6946 struct dsa_lag *lag;
6947 int i, err, nth;
6948 u16 mask[8];
6949 u16 ivec;
6950
6951 /* Assume no port is a member of any LAG. */
6952 ivec = BIT(mv88e6xxx_num_ports(chip)) - 1;
6953
6954 /* Disable all masks for ports that _are_ members of a LAG. */
6955 dsa_switch_for_each_port(dp, ds) {
6956 if (!dp->lag)
6957 continue;
6958
6959 ivec &= ~BIT(dp->index);
6960 }
6961
6962 for (i = 0; i < 8; i++)
6963 mask[i] = ivec;
6964
6965 /* Enable the correct subset of masks for all LAG ports that
6966 * are in the Tx set.
6967 */
6968 dsa_lags_foreach_id(id, ds->dst) {
6969 lag = dsa_lag_by_id(ds->dst, id);
6970 if (!lag)
6971 continue;
6972
6973 num_tx = 0;
6974 dsa_lag_foreach_port(dp, ds->dst, lag) {
6975 if (dp->lag_tx_enabled)
6976 num_tx++;
6977 }
6978
6979 if (!num_tx)
6980 continue;
6981
6982 nth = 0;
6983 dsa_lag_foreach_port(dp, ds->dst, lag) {
6984 if (!dp->lag_tx_enabled)
6985 continue;
6986
6987 if (dp->ds == ds)
6988 mv88e6xxx_lag_set_port_mask(mask, dp->index,
6989 num_tx, nth);
6990
6991 nth++;
6992 }
6993 }
6994
6995 for (i = 0; i < 8; i++) {
6996 err = mv88e6xxx_g2_trunk_mask_write(chip, i, true, mask[i]);
6997 if (err)
6998 return err;
6999 }
7000
7001 return 0;
7002 }
7003
mv88e6xxx_lag_sync_masks_map(struct dsa_switch * ds,struct dsa_lag lag)7004 static int mv88e6xxx_lag_sync_masks_map(struct dsa_switch *ds,
7005 struct dsa_lag lag)
7006 {
7007 int err;
7008
7009 err = mv88e6xxx_lag_sync_masks(ds);
7010
7011 if (!err)
7012 err = mv88e6xxx_lag_sync_map(ds, lag);
7013
7014 return err;
7015 }
7016
mv88e6xxx_port_lag_change(struct dsa_switch * ds,int port)7017 static int mv88e6xxx_port_lag_change(struct dsa_switch *ds, int port)
7018 {
7019 struct mv88e6xxx_chip *chip = ds->priv;
7020 int err;
7021
7022 mv88e6xxx_reg_lock(chip);
7023 err = mv88e6xxx_lag_sync_masks(ds);
7024 mv88e6xxx_reg_unlock(chip);
7025 return err;
7026 }
7027
mv88e6xxx_port_lag_join(struct dsa_switch * ds,int port,struct dsa_lag lag,struct netdev_lag_upper_info * info,struct netlink_ext_ack * extack)7028 static int mv88e6xxx_port_lag_join(struct dsa_switch *ds, int port,
7029 struct dsa_lag lag,
7030 struct netdev_lag_upper_info *info,
7031 struct netlink_ext_ack *extack)
7032 {
7033 struct mv88e6xxx_chip *chip = ds->priv;
7034 int err, id;
7035
7036 if (!mv88e6xxx_lag_can_offload(ds, lag, info, extack))
7037 return -EOPNOTSUPP;
7038
7039 /* DSA LAG IDs are one-based */
7040 id = lag.id - 1;
7041
7042 mv88e6xxx_reg_lock(chip);
7043
7044 err = mv88e6xxx_port_set_trunk(chip, port, true, id);
7045 if (err)
7046 goto err_unlock;
7047
7048 err = mv88e6xxx_lag_sync_masks_map(ds, lag);
7049 if (err)
7050 goto err_clear_trunk;
7051
7052 mv88e6xxx_reg_unlock(chip);
7053 return 0;
7054
7055 err_clear_trunk:
7056 mv88e6xxx_port_set_trunk(chip, port, false, 0);
7057 err_unlock:
7058 mv88e6xxx_reg_unlock(chip);
7059 return err;
7060 }
7061
mv88e6xxx_port_lag_leave(struct dsa_switch * ds,int port,struct dsa_lag lag)7062 static int mv88e6xxx_port_lag_leave(struct dsa_switch *ds, int port,
7063 struct dsa_lag lag)
7064 {
7065 struct mv88e6xxx_chip *chip = ds->priv;
7066 int err_sync, err_trunk;
7067
7068 mv88e6xxx_reg_lock(chip);
7069 err_sync = mv88e6xxx_lag_sync_masks_map(ds, lag);
7070 err_trunk = mv88e6xxx_port_set_trunk(chip, port, false, 0);
7071 mv88e6xxx_reg_unlock(chip);
7072 return err_sync ? : err_trunk;
7073 }
7074
mv88e6xxx_crosschip_lag_change(struct dsa_switch * ds,int sw_index,int port)7075 static int mv88e6xxx_crosschip_lag_change(struct dsa_switch *ds, int sw_index,
7076 int port)
7077 {
7078 struct mv88e6xxx_chip *chip = ds->priv;
7079 int err;
7080
7081 mv88e6xxx_reg_lock(chip);
7082 err = mv88e6xxx_lag_sync_masks(ds);
7083 mv88e6xxx_reg_unlock(chip);
7084 return err;
7085 }
7086
mv88e6xxx_crosschip_lag_join(struct dsa_switch * ds,int sw_index,int port,struct dsa_lag lag,struct netdev_lag_upper_info * info,struct netlink_ext_ack * extack)7087 static int mv88e6xxx_crosschip_lag_join(struct dsa_switch *ds, int sw_index,
7088 int port, struct dsa_lag lag,
7089 struct netdev_lag_upper_info *info,
7090 struct netlink_ext_ack *extack)
7091 {
7092 struct mv88e6xxx_chip *chip = ds->priv;
7093 int err;
7094
7095 if (!mv88e6xxx_lag_can_offload(ds, lag, info, extack))
7096 return -EOPNOTSUPP;
7097
7098 mv88e6xxx_reg_lock(chip);
7099
7100 err = mv88e6xxx_lag_sync_masks_map(ds, lag);
7101 if (err)
7102 goto unlock;
7103
7104 err = mv88e6xxx_pvt_map(chip, sw_index, port);
7105
7106 unlock:
7107 mv88e6xxx_reg_unlock(chip);
7108 return err;
7109 }
7110
mv88e6xxx_crosschip_lag_leave(struct dsa_switch * ds,int sw_index,int port,struct dsa_lag lag)7111 static int mv88e6xxx_crosschip_lag_leave(struct dsa_switch *ds, int sw_index,
7112 int port, struct dsa_lag lag)
7113 {
7114 struct mv88e6xxx_chip *chip = ds->priv;
7115 int err_sync, err_pvt;
7116
7117 mv88e6xxx_reg_lock(chip);
7118 err_sync = mv88e6xxx_lag_sync_masks_map(ds, lag);
7119 err_pvt = mv88e6xxx_pvt_map(chip, sw_index, port);
7120 mv88e6xxx_reg_unlock(chip);
7121 return err_sync ? : err_pvt;
7122 }
7123
7124 static const struct phylink_mac_ops mv88e6xxx_phylink_mac_ops = {
7125 .mac_select_pcs = mv88e6xxx_mac_select_pcs,
7126 .mac_prepare = mv88e6xxx_mac_prepare,
7127 .mac_config = mv88e6xxx_mac_config,
7128 .mac_finish = mv88e6xxx_mac_finish,
7129 .mac_link_down = mv88e6xxx_mac_link_down,
7130 .mac_link_up = mv88e6xxx_mac_link_up,
7131 };
7132
7133 static const struct dsa_switch_ops mv88e6xxx_switch_ops = {
7134 .get_tag_protocol = mv88e6xxx_get_tag_protocol,
7135 .change_tag_protocol = mv88e6xxx_change_tag_protocol,
7136 .setup = mv88e6xxx_setup,
7137 .teardown = mv88e6xxx_teardown,
7138 .port_setup = mv88e6xxx_port_setup,
7139 .port_teardown = mv88e6xxx_port_teardown,
7140 .phylink_get_caps = mv88e6xxx_get_caps,
7141 .get_strings = mv88e6xxx_get_strings,
7142 .get_ethtool_stats = mv88e6xxx_get_ethtool_stats,
7143 .get_eth_mac_stats = mv88e6xxx_get_eth_mac_stats,
7144 .get_rmon_stats = mv88e6xxx_get_rmon_stats,
7145 .get_sset_count = mv88e6xxx_get_sset_count,
7146 .port_max_mtu = mv88e6xxx_get_max_mtu,
7147 .port_change_mtu = mv88e6xxx_change_mtu,
7148 .get_mac_eee = mv88e6xxx_get_mac_eee,
7149 .set_mac_eee = mv88e6xxx_set_mac_eee,
7150 .get_eeprom_len = mv88e6xxx_get_eeprom_len,
7151 .get_eeprom = mv88e6xxx_get_eeprom,
7152 .set_eeprom = mv88e6xxx_set_eeprom,
7153 .get_regs_len = mv88e6xxx_get_regs_len,
7154 .get_regs = mv88e6xxx_get_regs,
7155 .get_rxnfc = mv88e6xxx_get_rxnfc,
7156 .set_rxnfc = mv88e6xxx_set_rxnfc,
7157 .set_ageing_time = mv88e6xxx_set_ageing_time,
7158 .port_bridge_join = mv88e6xxx_port_bridge_join,
7159 .port_bridge_leave = mv88e6xxx_port_bridge_leave,
7160 .port_pre_bridge_flags = mv88e6xxx_port_pre_bridge_flags,
7161 .port_bridge_flags = mv88e6xxx_port_bridge_flags,
7162 .port_stp_state_set = mv88e6xxx_port_stp_state_set,
7163 .port_mst_state_set = mv88e6xxx_port_mst_state_set,
7164 .port_fast_age = mv88e6xxx_port_fast_age,
7165 .port_vlan_fast_age = mv88e6xxx_port_vlan_fast_age,
7166 .port_vlan_filtering = mv88e6xxx_port_vlan_filtering,
7167 .port_vlan_add = mv88e6xxx_port_vlan_add,
7168 .port_vlan_del = mv88e6xxx_port_vlan_del,
7169 .vlan_msti_set = mv88e6xxx_vlan_msti_set,
7170 .port_fdb_add = mv88e6xxx_port_fdb_add,
7171 .port_fdb_del = mv88e6xxx_port_fdb_del,
7172 .port_fdb_dump = mv88e6xxx_port_fdb_dump,
7173 .port_mdb_add = mv88e6xxx_port_mdb_add,
7174 .port_mdb_del = mv88e6xxx_port_mdb_del,
7175 .port_mirror_add = mv88e6xxx_port_mirror_add,
7176 .port_mirror_del = mv88e6xxx_port_mirror_del,
7177 .crosschip_bridge_join = mv88e6xxx_crosschip_bridge_join,
7178 .crosschip_bridge_leave = mv88e6xxx_crosschip_bridge_leave,
7179 .port_hwtstamp_set = mv88e6xxx_port_hwtstamp_set,
7180 .port_hwtstamp_get = mv88e6xxx_port_hwtstamp_get,
7181 .port_txtstamp = mv88e6xxx_port_txtstamp,
7182 .port_rxtstamp = mv88e6xxx_port_rxtstamp,
7183 .get_ts_info = mv88e6xxx_get_ts_info,
7184 .devlink_param_get = mv88e6xxx_devlink_param_get,
7185 .devlink_param_set = mv88e6xxx_devlink_param_set,
7186 .devlink_info_get = mv88e6xxx_devlink_info_get,
7187 .port_lag_change = mv88e6xxx_port_lag_change,
7188 .port_lag_join = mv88e6xxx_port_lag_join,
7189 .port_lag_leave = mv88e6xxx_port_lag_leave,
7190 .crosschip_lag_change = mv88e6xxx_crosschip_lag_change,
7191 .crosschip_lag_join = mv88e6xxx_crosschip_lag_join,
7192 .crosschip_lag_leave = mv88e6xxx_crosschip_lag_leave,
7193 };
7194
mv88e6xxx_register_switch(struct mv88e6xxx_chip * chip)7195 static int mv88e6xxx_register_switch(struct mv88e6xxx_chip *chip)
7196 {
7197 struct device *dev = chip->dev;
7198 struct dsa_switch *ds;
7199
7200 ds = devm_kzalloc(dev, sizeof(*ds), GFP_KERNEL);
7201 if (!ds)
7202 return -ENOMEM;
7203
7204 ds->dev = dev;
7205 ds->num_ports = mv88e6xxx_num_ports(chip);
7206 ds->priv = chip;
7207 ds->dev = dev;
7208 ds->ops = &mv88e6xxx_switch_ops;
7209 ds->phylink_mac_ops = &mv88e6xxx_phylink_mac_ops;
7210 ds->ageing_time_min = chip->info->age_time_coeff;
7211 ds->ageing_time_max = chip->info->age_time_coeff * U8_MAX;
7212
7213 /* Some chips support up to 32, but that requires enabling the
7214 * 5-bit port mode, which we do not support. 640k^W16 ought to
7215 * be enough for anyone.
7216 */
7217 ds->num_lag_ids = mv88e6xxx_has_lag(chip) ? 16 : 0;
7218
7219 dev_set_drvdata(dev, ds);
7220
7221 return dsa_register_switch(ds);
7222 }
7223
mv88e6xxx_unregister_switch(struct mv88e6xxx_chip * chip)7224 static void mv88e6xxx_unregister_switch(struct mv88e6xxx_chip *chip)
7225 {
7226 dsa_unregister_switch(chip->ds);
7227 }
7228
pdata_device_get_match_data(struct device * dev)7229 static const void *pdata_device_get_match_data(struct device *dev)
7230 {
7231 const struct of_device_id *matches = dev->driver->of_match_table;
7232 const struct dsa_mv88e6xxx_pdata *pdata = dev->platform_data;
7233
7234 for (; matches->name[0] || matches->type[0] || matches->compatible[0];
7235 matches++) {
7236 if (!strcmp(pdata->compatible, matches->compatible))
7237 return matches->data;
7238 }
7239 return NULL;
7240 }
7241
7242 /* There is no suspend to RAM support at DSA level yet, the switch configuration
7243 * would be lost after a power cycle so prevent it to be suspended.
7244 */
mv88e6xxx_suspend(struct device * dev)7245 static int __maybe_unused mv88e6xxx_suspend(struct device *dev)
7246 {
7247 return -EOPNOTSUPP;
7248 }
7249
mv88e6xxx_resume(struct device * dev)7250 static int __maybe_unused mv88e6xxx_resume(struct device *dev)
7251 {
7252 return 0;
7253 }
7254
7255 static SIMPLE_DEV_PM_OPS(mv88e6xxx_pm_ops, mv88e6xxx_suspend, mv88e6xxx_resume);
7256
mv88e6xxx_probe(struct mdio_device * mdiodev)7257 static int mv88e6xxx_probe(struct mdio_device *mdiodev)
7258 {
7259 struct dsa_mv88e6xxx_pdata *pdata = mdiodev->dev.platform_data;
7260 const struct mv88e6xxx_info *compat_info = NULL;
7261 struct device *dev = &mdiodev->dev;
7262 struct device_node *np = dev->of_node;
7263 struct mv88e6xxx_chip *chip;
7264 int port;
7265 int err;
7266
7267 if (!np && !pdata)
7268 return -EINVAL;
7269
7270 if (np)
7271 compat_info = of_device_get_match_data(dev);
7272
7273 if (pdata) {
7274 compat_info = pdata_device_get_match_data(dev);
7275
7276 if (!pdata->netdev)
7277 return -EINVAL;
7278
7279 for (port = 0; port < DSA_MAX_PORTS; port++) {
7280 if (!(pdata->enabled_ports & (1 << port)))
7281 continue;
7282 if (strcmp(pdata->cd.port_names[port], "cpu"))
7283 continue;
7284 pdata->cd.netdev[port] = &pdata->netdev->dev;
7285 break;
7286 }
7287 }
7288
7289 if (!compat_info)
7290 return -EINVAL;
7291
7292 chip = mv88e6xxx_alloc_chip(dev);
7293 if (!chip) {
7294 err = -ENOMEM;
7295 goto out;
7296 }
7297
7298 chip->info = compat_info;
7299
7300 chip->reset = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW);
7301 if (IS_ERR(chip->reset)) {
7302 err = PTR_ERR(chip->reset);
7303 goto out;
7304 }
7305 if (chip->reset)
7306 usleep_range(10000, 20000);
7307
7308 /* Detect if the device is configured in single chip addressing mode,
7309 * otherwise continue with address specific smi init/detection.
7310 */
7311 err = mv88e6xxx_single_chip_detect(chip, mdiodev);
7312 if (err) {
7313 err = mv88e6xxx_smi_init(chip, mdiodev->bus, mdiodev->addr);
7314 if (err)
7315 goto out;
7316
7317 err = mv88e6xxx_detect(chip);
7318 if (err)
7319 goto out;
7320 }
7321
7322 if (chip->info->edsa_support == MV88E6XXX_EDSA_SUPPORTED)
7323 chip->tag_protocol = DSA_TAG_PROTO_EDSA;
7324 else
7325 chip->tag_protocol = DSA_TAG_PROTO_DSA;
7326
7327 mv88e6xxx_phy_init(chip);
7328
7329 if (chip->info->ops->get_eeprom) {
7330 if (np)
7331 of_property_read_u32(np, "eeprom-length",
7332 &chip->eeprom_len);
7333 else
7334 chip->eeprom_len = pdata->eeprom_len;
7335 }
7336
7337 mv88e6xxx_reg_lock(chip);
7338 err = mv88e6xxx_switch_reset(chip);
7339 mv88e6xxx_reg_unlock(chip);
7340 if (err)
7341 goto out_phy;
7342
7343 if (np) {
7344 chip->irq = of_irq_get(np, 0);
7345 if (chip->irq == -EPROBE_DEFER) {
7346 err = chip->irq;
7347 goto out_phy;
7348 }
7349 }
7350
7351 if (pdata)
7352 chip->irq = pdata->irq;
7353
7354 /* Has to be performed before the MDIO bus is created, because
7355 * the PHYs will link their interrupts to these interrupt
7356 * controllers
7357 */
7358 mv88e6xxx_reg_lock(chip);
7359 if (chip->irq > 0)
7360 err = mv88e6xxx_g1_irq_setup(chip);
7361 else
7362 err = mv88e6xxx_irq_poll_setup(chip);
7363 mv88e6xxx_reg_unlock(chip);
7364
7365 if (err)
7366 goto out_phy;
7367
7368 if (chip->info->g2_irqs > 0) {
7369 err = mv88e6xxx_g2_irq_setup(chip);
7370 if (err)
7371 goto out_g1_irq;
7372 }
7373
7374 err = mv88e6xxx_g1_atu_prob_irq_setup(chip);
7375 if (err)
7376 goto out_g2_irq;
7377
7378 err = mv88e6xxx_g1_vtu_prob_irq_setup(chip);
7379 if (err)
7380 goto out_g1_atu_prob_irq;
7381
7382 err = mv88e6xxx_register_switch(chip);
7383 if (err)
7384 goto out_g1_vtu_prob_irq;
7385
7386 return 0;
7387
7388 out_g1_vtu_prob_irq:
7389 mv88e6xxx_g1_vtu_prob_irq_free(chip);
7390 out_g1_atu_prob_irq:
7391 mv88e6xxx_g1_atu_prob_irq_free(chip);
7392 out_g2_irq:
7393 if (chip->info->g2_irqs > 0)
7394 mv88e6xxx_g2_irq_free(chip);
7395 out_g1_irq:
7396 if (chip->irq > 0)
7397 mv88e6xxx_g1_irq_free(chip);
7398 else
7399 mv88e6xxx_irq_poll_free(chip);
7400 out_phy:
7401 mv88e6xxx_phy_destroy(chip);
7402 out:
7403 if (pdata)
7404 dev_put(pdata->netdev);
7405
7406 return err;
7407 }
7408
mv88e6xxx_remove(struct mdio_device * mdiodev)7409 static void mv88e6xxx_remove(struct mdio_device *mdiodev)
7410 {
7411 struct dsa_switch *ds = dev_get_drvdata(&mdiodev->dev);
7412 struct mv88e6xxx_chip *chip;
7413
7414 if (!ds)
7415 return;
7416
7417 chip = ds->priv;
7418
7419 if (chip->info->ptp_support) {
7420 mv88e6xxx_hwtstamp_free(chip);
7421 mv88e6xxx_ptp_free(chip);
7422 }
7423
7424 mv88e6xxx_unregister_switch(chip);
7425
7426 mv88e6xxx_g1_vtu_prob_irq_free(chip);
7427 mv88e6xxx_g1_atu_prob_irq_free(chip);
7428
7429 if (chip->info->g2_irqs > 0)
7430 mv88e6xxx_g2_irq_free(chip);
7431
7432 if (chip->irq > 0)
7433 mv88e6xxx_g1_irq_free(chip);
7434 else
7435 mv88e6xxx_irq_poll_free(chip);
7436
7437 mv88e6xxx_phy_destroy(chip);
7438 }
7439
mv88e6xxx_shutdown(struct mdio_device * mdiodev)7440 static void mv88e6xxx_shutdown(struct mdio_device *mdiodev)
7441 {
7442 struct dsa_switch *ds = dev_get_drvdata(&mdiodev->dev);
7443
7444 if (!ds)
7445 return;
7446
7447 dsa_switch_shutdown(ds);
7448
7449 dev_set_drvdata(&mdiodev->dev, NULL);
7450 }
7451
7452 static const struct of_device_id mv88e6xxx_of_match[] = {
7453 {
7454 .compatible = "marvell,mv88e6085",
7455 .data = &mv88e6xxx_table[MV88E6085],
7456 },
7457 {
7458 .compatible = "marvell,mv88e6190",
7459 .data = &mv88e6xxx_table[MV88E6190],
7460 },
7461 {
7462 .compatible = "marvell,mv88e6250",
7463 .data = &mv88e6xxx_table[MV88E6250],
7464 },
7465 { /* sentinel */ },
7466 };
7467
7468 MODULE_DEVICE_TABLE(of, mv88e6xxx_of_match);
7469
7470 static struct mdio_driver mv88e6xxx_driver = {
7471 .probe = mv88e6xxx_probe,
7472 .remove = mv88e6xxx_remove,
7473 .shutdown = mv88e6xxx_shutdown,
7474 .mdiodrv.driver = {
7475 .name = "mv88e6085",
7476 .of_match_table = mv88e6xxx_of_match,
7477 .pm = &mv88e6xxx_pm_ops,
7478 },
7479 };
7480
7481 mdio_module_driver(mv88e6xxx_driver);
7482
7483 MODULE_AUTHOR("Lennert Buytenhek <buytenh@wantstofly.org>");
7484 MODULE_DESCRIPTION("Driver for Marvell 88E6XXX ethernet switch chips");
7485 MODULE_LICENSE("GPL");
7486