1 // SPDX-License-Identifier: GPL-2.0
2 /* Realtek SMI subdriver for the Realtek RTL8366RB ethernet switch
3 *
4 * This is a sparsely documented chip, the only viable documentation seems
5 * to be a patched up code drop from the vendor that appear in various
6 * GPL source trees.
7 *
8 * Copyright (C) 2017 Linus Walleij <linus.walleij@linaro.org>
9 * Copyright (C) 2009-2010 Gabor Juhos <juhosg@openwrt.org>
10 * Copyright (C) 2010 Antti Seppälä <a.seppala@gmail.com>
11 * Copyright (C) 2010 Roman Yeryomin <roman@advem.lv>
12 * Copyright (C) 2011 Colin Leitner <colin.leitner@googlemail.com>
13 */
14
15 #include <linux/bitops.h>
16 #include <linux/etherdevice.h>
17 #include <linux/if_bridge.h>
18 #include <linux/if_vlan.h>
19 #include <linux/interrupt.h>
20 #include <linux/irqdomain.h>
21 #include <linux/irqchip/chained_irq.h>
22 #include <linux/of_irq.h>
23 #include <linux/regmap.h>
24
25 #include "realtek.h"
26 #include "realtek-smi.h"
27 #include "realtek-mdio.h"
28 #include "rtl83xx.h"
29 #include "rtl8366rb.h"
30
31 /* Switch Global Configuration register */
32 #define RTL8366RB_SGCR 0x0000
33 #define RTL8366RB_SGCR_EN_BC_STORM_CTRL BIT(0)
34 #define RTL8366RB_SGCR_MAX_LENGTH(a) ((a) << 4)
35 #define RTL8366RB_SGCR_MAX_LENGTH_MASK RTL8366RB_SGCR_MAX_LENGTH(0x3)
36 #define RTL8366RB_SGCR_MAX_LENGTH_1522 RTL8366RB_SGCR_MAX_LENGTH(0x0)
37 #define RTL8366RB_SGCR_MAX_LENGTH_1536 RTL8366RB_SGCR_MAX_LENGTH(0x1)
38 #define RTL8366RB_SGCR_MAX_LENGTH_1552 RTL8366RB_SGCR_MAX_LENGTH(0x2)
39 #define RTL8366RB_SGCR_MAX_LENGTH_16000 RTL8366RB_SGCR_MAX_LENGTH(0x3)
40 #define RTL8366RB_SGCR_EN_VLAN BIT(13)
41 #define RTL8366RB_SGCR_EN_VLAN_4KTB BIT(14)
42
43 /* Port Enable Control register */
44 #define RTL8366RB_PECR 0x0001
45
46 /* Switch per-port learning disablement register */
47 #define RTL8366RB_PORT_LEARNDIS_CTRL 0x0002
48
49 /* Security control, actually aging register */
50 #define RTL8366RB_SECURITY_CTRL 0x0003
51
52 #define RTL8366RB_SSCR2 0x0004
53 #define RTL8366RB_SSCR2_DROP_UNKNOWN_DA BIT(0)
54
55 /* Port Mode Control registers */
56 #define RTL8366RB_PMC0 0x0005
57 #define RTL8366RB_PMC0_SPI BIT(0)
58 #define RTL8366RB_PMC0_EN_AUTOLOAD BIT(1)
59 #define RTL8366RB_PMC0_PROBE BIT(2)
60 #define RTL8366RB_PMC0_DIS_BISR BIT(3)
61 #define RTL8366RB_PMC0_ADCTEST BIT(4)
62 #define RTL8366RB_PMC0_SRAM_DIAG BIT(5)
63 #define RTL8366RB_PMC0_EN_SCAN BIT(6)
64 #define RTL8366RB_PMC0_P4_IOMODE_SHIFT 7
65 #define RTL8366RB_PMC0_P4_IOMODE_MASK GENMASK(9, 7)
66 #define RTL8366RB_PMC0_P5_IOMODE_SHIFT 10
67 #define RTL8366RB_PMC0_P5_IOMODE_MASK GENMASK(12, 10)
68 #define RTL8366RB_PMC0_SDSMODE_SHIFT 13
69 #define RTL8366RB_PMC0_SDSMODE_MASK GENMASK(15, 13)
70 #define RTL8366RB_PMC1 0x0006
71
72 /* Port Mirror Control Register */
73 #define RTL8366RB_PMCR 0x0007
74 #define RTL8366RB_PMCR_SOURCE_PORT(a) (a)
75 #define RTL8366RB_PMCR_SOURCE_PORT_MASK 0x000f
76 #define RTL8366RB_PMCR_MONITOR_PORT(a) ((a) << 4)
77 #define RTL8366RB_PMCR_MONITOR_PORT_MASK 0x00f0
78 #define RTL8366RB_PMCR_MIRROR_RX BIT(8)
79 #define RTL8366RB_PMCR_MIRROR_TX BIT(9)
80 #define RTL8366RB_PMCR_MIRROR_SPC BIT(10)
81 #define RTL8366RB_PMCR_MIRROR_ISO BIT(11)
82
83 /* bits 0..7 = port 0, bits 8..15 = port 1 */
84 #define RTL8366RB_PAACR0 0x0010
85 /* bits 0..7 = port 2, bits 8..15 = port 3 */
86 #define RTL8366RB_PAACR1 0x0011
87 /* bits 0..7 = port 4, bits 8..15 = port 5 */
88 #define RTL8366RB_PAACR2 0x0012
89 #define RTL8366RB_PAACR_SPEED_10M 0
90 #define RTL8366RB_PAACR_SPEED_100M 1
91 #define RTL8366RB_PAACR_SPEED_1000M 2
92 #define RTL8366RB_PAACR_FULL_DUPLEX BIT(2)
93 #define RTL8366RB_PAACR_LINK_UP BIT(4)
94 #define RTL8366RB_PAACR_TX_PAUSE BIT(5)
95 #define RTL8366RB_PAACR_RX_PAUSE BIT(6)
96 #define RTL8366RB_PAACR_AN BIT(7)
97
98 /* bits 0..7 = port 0, bits 8..15 = port 1 */
99 #define RTL8366RB_PSTAT0 0x0014
100 /* bits 0..7 = port 2, bits 8..15 = port 3 */
101 #define RTL8366RB_PSTAT1 0x0015
102 /* bits 0..7 = port 4, bits 8..15 = port 5 */
103 #define RTL8366RB_PSTAT2 0x0016
104
105 #define RTL8366RB_POWER_SAVING_REG 0x0021
106
107 /* Spanning tree status (STP) control, two bits per port per FID */
108 #define RTL8366RB_STP_STATE_BASE 0x0050 /* 0x0050..0x0057 */
109 #define RTL8366RB_STP_STATE_DISABLED 0x0
110 #define RTL8366RB_STP_STATE_BLOCKING 0x1
111 #define RTL8366RB_STP_STATE_LEARNING 0x2
112 #define RTL8366RB_STP_STATE_FORWARDING 0x3
113 #define RTL8366RB_STP_MASK GENMASK(1, 0)
114 #define RTL8366RB_STP_STATE(port, state) \
115 ((state) << ((port) * 2))
116 #define RTL8366RB_STP_STATE_MASK(port) \
117 RTL8366RB_STP_STATE((port), RTL8366RB_STP_MASK)
118
119 /* CPU port control reg */
120 #define RTL8366RB_CPU_CTRL_REG 0x0061
121 #define RTL8366RB_CPU_PORTS_MSK 0x00FF
122 /* Disables inserting custom tag length/type 0x8899 */
123 #define RTL8366RB_CPU_NO_TAG BIT(15)
124 #define RTL8366RB_CPU_TAG_SIZE 4
125
126 #define RTL8366RB_SMAR0 0x0070 /* bits 0..15 */
127 #define RTL8366RB_SMAR1 0x0071 /* bits 16..31 */
128 #define RTL8366RB_SMAR2 0x0072 /* bits 32..47 */
129
130 #define RTL8366RB_RESET_CTRL_REG 0x0100
131 #define RTL8366RB_CHIP_CTRL_RESET_HW BIT(0)
132 #define RTL8366RB_CHIP_CTRL_RESET_SW BIT(1)
133
134 #define RTL8366RB_CHIP_ID_REG 0x0509
135 #define RTL8366RB_CHIP_ID_8366 0x5937
136 #define RTL8366RB_CHIP_VERSION_CTRL_REG 0x050A
137 #define RTL8366RB_CHIP_VERSION_MASK 0xf
138
139 /* PHY registers control */
140 #define RTL8366RB_PHY_ACCESS_CTRL_REG 0x8000
141 #define RTL8366RB_PHY_CTRL_READ BIT(0)
142 #define RTL8366RB_PHY_CTRL_WRITE 0
143 #define RTL8366RB_PHY_ACCESS_BUSY_REG 0x8001
144 #define RTL8366RB_PHY_INT_BUSY BIT(0)
145 #define RTL8366RB_PHY_EXT_BUSY BIT(4)
146 #define RTL8366RB_PHY_ACCESS_DATA_REG 0x8002
147 #define RTL8366RB_PHY_EXT_CTRL_REG 0x8010
148 #define RTL8366RB_PHY_EXT_WRDATA_REG 0x8011
149 #define RTL8366RB_PHY_EXT_RDDATA_REG 0x8012
150
151 #define RTL8366RB_PHY_REG_MASK 0x1f
152 #define RTL8366RB_PHY_PAGE_OFFSET 5
153 #define RTL8366RB_PHY_PAGE_MASK (0xf << 5)
154 #define RTL8366RB_PHY_NO_OFFSET 9
155 #define RTL8366RB_PHY_NO_MASK (0x1f << 9)
156
157 /* VLAN Ingress Control Register 1, one bit per port.
158 * bit 0 .. 5 will make the switch drop ingress frames without
159 * VID such as untagged or priority-tagged frames for respective
160 * port.
161 * bit 6 .. 11 will make the switch drop ingress frames carrying
162 * a C-tag with VID != 0 for respective port.
163 */
164 #define RTL8366RB_VLAN_INGRESS_CTRL1_REG 0x037E
165 #define RTL8366RB_VLAN_INGRESS_CTRL1_DROP(port) (BIT((port)) | BIT((port) + 6))
166
167 /* VLAN Ingress Control Register 2, one bit per port.
168 * bit0 .. bit5 will make the switch drop all ingress frames with
169 * a VLAN classification that does not include the port is in its
170 * member set.
171 */
172 #define RTL8366RB_VLAN_INGRESS_CTRL2_REG 0x037f
173
174 #define RTL8366RB_MIB_COUNT 33
175 #define RTL8366RB_GLOBAL_MIB_COUNT 1
176 #define RTL8366RB_MIB_COUNTER_PORT_OFFSET 0x0050
177 #define RTL8366RB_MIB_COUNTER_BASE 0x1000
178 #define RTL8366RB_MIB_CTRL_REG 0x13F0
179 #define RTL8366RB_MIB_CTRL_USER_MASK 0x0FFC
180 #define RTL8366RB_MIB_CTRL_BUSY_MASK BIT(0)
181 #define RTL8366RB_MIB_CTRL_RESET_MASK BIT(1)
182 #define RTL8366RB_MIB_CTRL_PORT_RESET(_p) BIT(2 + (_p))
183 #define RTL8366RB_MIB_CTRL_GLOBAL_RESET BIT(11)
184
185 #define RTL8366RB_PORT_VLAN_CTRL_BASE 0x0063
186 #define RTL8366RB_PORT_VLAN_CTRL_REG(_p) \
187 (RTL8366RB_PORT_VLAN_CTRL_BASE + (_p) / 4)
188 #define RTL8366RB_PORT_VLAN_CTRL_MASK 0xf
189 #define RTL8366RB_PORT_VLAN_CTRL_SHIFT(_p) (4 * ((_p) % 4))
190
191 #define RTL8366RB_VLAN_TABLE_READ_BASE 0x018C
192 #define RTL8366RB_VLAN_TABLE_WRITE_BASE 0x0185
193
194 #define RTL8366RB_TABLE_ACCESS_CTRL_REG 0x0180
195 #define RTL8366RB_TABLE_VLAN_READ_CTRL 0x0E01
196 #define RTL8366RB_TABLE_VLAN_WRITE_CTRL 0x0F01
197
198 #define RTL8366RB_VLAN_MC_BASE(_x) (0x0020 + (_x) * 3)
199
200 #define RTL8366RB_PORT_LINK_STATUS_BASE 0x0014
201 #define RTL8366RB_PORT_STATUS_SPEED_MASK 0x0003
202 #define RTL8366RB_PORT_STATUS_DUPLEX_MASK 0x0004
203 #define RTL8366RB_PORT_STATUS_LINK_MASK 0x0010
204 #define RTL8366RB_PORT_STATUS_TXPAUSE_MASK 0x0020
205 #define RTL8366RB_PORT_STATUS_RXPAUSE_MASK 0x0040
206 #define RTL8366RB_PORT_STATUS_AN_MASK 0x0080
207
208 #define RTL8366RB_NUM_VLANS 16
209 #define RTL8366RB_NUM_VIDS 4096
210 #define RTL8366RB_PRIORITYMAX 7
211 #define RTL8366RB_NUM_FIDS 8
212 #define RTL8366RB_FIDMAX 7
213
214 #define RTL8366RB_PORT_1 BIT(0) /* In userspace port 0 */
215 #define RTL8366RB_PORT_2 BIT(1) /* In userspace port 1 */
216 #define RTL8366RB_PORT_3 BIT(2) /* In userspace port 2 */
217 #define RTL8366RB_PORT_4 BIT(3) /* In userspace port 3 */
218 #define RTL8366RB_PORT_5 BIT(4) /* In userspace port 4 */
219
220 #define RTL8366RB_PORT_CPU BIT(5) /* CPU port */
221
222 #define RTL8366RB_PORT_ALL (RTL8366RB_PORT_1 | \
223 RTL8366RB_PORT_2 | \
224 RTL8366RB_PORT_3 | \
225 RTL8366RB_PORT_4 | \
226 RTL8366RB_PORT_5 | \
227 RTL8366RB_PORT_CPU)
228
229 #define RTL8366RB_PORT_ALL_BUT_CPU (RTL8366RB_PORT_1 | \
230 RTL8366RB_PORT_2 | \
231 RTL8366RB_PORT_3 | \
232 RTL8366RB_PORT_4 | \
233 RTL8366RB_PORT_5)
234
235 #define RTL8366RB_PORT_ALL_EXTERNAL (RTL8366RB_PORT_1 | \
236 RTL8366RB_PORT_2 | \
237 RTL8366RB_PORT_3 | \
238 RTL8366RB_PORT_4)
239
240 #define RTL8366RB_PORT_ALL_INTERNAL RTL8366RB_PORT_CPU
241
242 /* First configuration word per member config, VID and prio */
243 #define RTL8366RB_VLAN_VID_MASK 0xfff
244 #define RTL8366RB_VLAN_PRIORITY_SHIFT 12
245 #define RTL8366RB_VLAN_PRIORITY_MASK 0x7
246 /* Second configuration word per member config, member and untagged */
247 #define RTL8366RB_VLAN_UNTAG_SHIFT 8
248 #define RTL8366RB_VLAN_UNTAG_MASK 0xff
249 #define RTL8366RB_VLAN_MEMBER_MASK 0xff
250 /* Third config word per member config, STAG currently unused */
251 #define RTL8366RB_VLAN_STAG_MBR_MASK 0xff
252 #define RTL8366RB_VLAN_STAG_MBR_SHIFT 8
253 #define RTL8366RB_VLAN_STAG_IDX_MASK 0x7
254 #define RTL8366RB_VLAN_STAG_IDX_SHIFT 5
255 #define RTL8366RB_VLAN_FID_MASK 0x7
256
257 /* Port ingress bandwidth control */
258 #define RTL8366RB_IB_BASE 0x0200
259 #define RTL8366RB_IB_REG(pnum) (RTL8366RB_IB_BASE + (pnum))
260 #define RTL8366RB_IB_BDTH_MASK 0x3fff
261 #define RTL8366RB_IB_PREIFG BIT(14)
262
263 /* Port egress bandwidth control */
264 #define RTL8366RB_EB_BASE 0x02d1
265 #define RTL8366RB_EB_REG(pnum) (RTL8366RB_EB_BASE + (pnum))
266 #define RTL8366RB_EB_BDTH_MASK 0x3fff
267 #define RTL8366RB_EB_PREIFG_REG 0x02f8
268 #define RTL8366RB_EB_PREIFG BIT(9)
269
270 #define RTL8366RB_BDTH_SW_MAX 1048512 /* 1048576? */
271 #define RTL8366RB_BDTH_UNIT 64
272 #define RTL8366RB_BDTH_REG_DEFAULT 16383
273
274 /* QOS */
275 #define RTL8366RB_QOS BIT(15)
276 /* Include/Exclude Preamble and IFG (20 bytes). 0:Exclude, 1:Include. */
277 #define RTL8366RB_QOS_DEFAULT_PREIFG 1
278
279 /* Interrupt handling */
280 #define RTL8366RB_INTERRUPT_CONTROL_REG 0x0440
281 #define RTL8366RB_INTERRUPT_POLARITY BIT(0)
282 #define RTL8366RB_P4_RGMII_LED BIT(2)
283 #define RTL8366RB_INTERRUPT_MASK_REG 0x0441
284 #define RTL8366RB_INTERRUPT_LINK_CHGALL GENMASK(11, 0)
285 #define RTL8366RB_INTERRUPT_ACLEXCEED BIT(8)
286 #define RTL8366RB_INTERRUPT_STORMEXCEED BIT(9)
287 #define RTL8366RB_INTERRUPT_P4_FIBER BIT(12)
288 #define RTL8366RB_INTERRUPT_P4_UTP BIT(13)
289 #define RTL8366RB_INTERRUPT_VALID (RTL8366RB_INTERRUPT_LINK_CHGALL | \
290 RTL8366RB_INTERRUPT_ACLEXCEED | \
291 RTL8366RB_INTERRUPT_STORMEXCEED | \
292 RTL8366RB_INTERRUPT_P4_FIBER | \
293 RTL8366RB_INTERRUPT_P4_UTP)
294 #define RTL8366RB_INTERRUPT_STATUS_REG 0x0442
295 #define RTL8366RB_NUM_INTERRUPT 14 /* 0..13 */
296
297 /* Port isolation registers */
298 #define RTL8366RB_PORT_ISO_BASE 0x0F08
299 #define RTL8366RB_PORT_ISO(pnum) (RTL8366RB_PORT_ISO_BASE + (pnum))
300 #define RTL8366RB_PORT_ISO_EN BIT(0)
301 #define RTL8366RB_PORT_ISO_PORTS_MASK GENMASK(7, 1)
302 #define RTL8366RB_PORT_ISO_PORTS(pmask) ((pmask) << 1)
303
304 /* bits 0..5 enable force when cleared */
305 #define RTL8366RB_MAC_FORCE_CTRL_REG 0x0F11
306
307 #define RTL8366RB_OAM_PARSER_REG 0x0F14
308 #define RTL8366RB_OAM_MULTIPLEXER_REG 0x0F15
309
310 #define RTL8366RB_GREEN_FEATURE_REG 0x0F51
311 #define RTL8366RB_GREEN_FEATURE_MSK 0x0007
312 #define RTL8366RB_GREEN_FEATURE_TX BIT(0)
313 #define RTL8366RB_GREEN_FEATURE_RX BIT(2)
314
315 static struct rtl8366_mib_counter rtl8366rb_mib_counters[] = {
316 { 0, 0, 4, "IfInOctets" },
317 { 0, 4, 4, "EtherStatsOctets" },
318 { 0, 8, 2, "EtherStatsUnderSizePkts" },
319 { 0, 10, 2, "EtherFragments" },
320 { 0, 12, 2, "EtherStatsPkts64Octets" },
321 { 0, 14, 2, "EtherStatsPkts65to127Octets" },
322 { 0, 16, 2, "EtherStatsPkts128to255Octets" },
323 { 0, 18, 2, "EtherStatsPkts256to511Octets" },
324 { 0, 20, 2, "EtherStatsPkts512to1023Octets" },
325 { 0, 22, 2, "EtherStatsPkts1024to1518Octets" },
326 { 0, 24, 2, "EtherOversizeStats" },
327 { 0, 26, 2, "EtherStatsJabbers" },
328 { 0, 28, 2, "IfInUcastPkts" },
329 { 0, 30, 2, "EtherStatsMulticastPkts" },
330 { 0, 32, 2, "EtherStatsBroadcastPkts" },
331 { 0, 34, 2, "EtherStatsDropEvents" },
332 { 0, 36, 2, "Dot3StatsFCSErrors" },
333 { 0, 38, 2, "Dot3StatsSymbolErrors" },
334 { 0, 40, 2, "Dot3InPauseFrames" },
335 { 0, 42, 2, "Dot3ControlInUnknownOpcodes" },
336 { 0, 44, 4, "IfOutOctets" },
337 { 0, 48, 2, "Dot3StatsSingleCollisionFrames" },
338 { 0, 50, 2, "Dot3StatMultipleCollisionFrames" },
339 { 0, 52, 2, "Dot3sDeferredTransmissions" },
340 { 0, 54, 2, "Dot3StatsLateCollisions" },
341 { 0, 56, 2, "EtherStatsCollisions" },
342 { 0, 58, 2, "Dot3StatsExcessiveCollisions" },
343 { 0, 60, 2, "Dot3OutPauseFrames" },
344 { 0, 62, 2, "Dot1dBasePortDelayExceededDiscards" },
345 { 0, 64, 2, "Dot1dTpPortInDiscards" },
346 { 0, 66, 2, "IfOutUcastPkts" },
347 { 0, 68, 2, "IfOutMulticastPkts" },
348 { 0, 70, 2, "IfOutBroadcastPkts" },
349 };
350
rtl8366rb_get_mib_counter(struct realtek_priv * priv,int port,struct rtl8366_mib_counter * mib,u64 * mibvalue)351 static int rtl8366rb_get_mib_counter(struct realtek_priv *priv,
352 int port,
353 struct rtl8366_mib_counter *mib,
354 u64 *mibvalue)
355 {
356 u32 addr, val;
357 int ret;
358 int i;
359
360 addr = RTL8366RB_MIB_COUNTER_BASE +
361 RTL8366RB_MIB_COUNTER_PORT_OFFSET * (port) +
362 mib->offset;
363
364 /* Writing access counter address first
365 * then ASIC will prepare 64bits counter wait for being retrived
366 */
367 ret = regmap_write(priv->map, addr, 0); /* Write whatever */
368 if (ret)
369 return ret;
370
371 /* Read MIB control register */
372 ret = regmap_read(priv->map, RTL8366RB_MIB_CTRL_REG, &val);
373 if (ret)
374 return -EIO;
375
376 if (val & RTL8366RB_MIB_CTRL_BUSY_MASK)
377 return -EBUSY;
378
379 if (val & RTL8366RB_MIB_CTRL_RESET_MASK)
380 return -EIO;
381
382 /* Read each individual MIB 16 bits at the time */
383 *mibvalue = 0;
384 for (i = mib->length; i > 0; i--) {
385 ret = regmap_read(priv->map, addr + (i - 1), &val);
386 if (ret)
387 return ret;
388 *mibvalue = (*mibvalue << 16) | (val & 0xFFFF);
389 }
390 return 0;
391 }
392
rtl8366rb_get_irqmask(struct irq_data * d)393 static u32 rtl8366rb_get_irqmask(struct irq_data *d)
394 {
395 int line = irqd_to_hwirq(d);
396 u32 val;
397
398 /* For line interrupts we combine link down in bits
399 * 6..11 with link up in bits 0..5 into one interrupt.
400 */
401 if (line < 12)
402 val = BIT(line) | BIT(line + 6);
403 else
404 val = BIT(line);
405 return val;
406 }
407
rtl8366rb_mask_irq(struct irq_data * d)408 static void rtl8366rb_mask_irq(struct irq_data *d)
409 {
410 struct realtek_priv *priv = irq_data_get_irq_chip_data(d);
411 int ret;
412
413 ret = regmap_update_bits(priv->map, RTL8366RB_INTERRUPT_MASK_REG,
414 rtl8366rb_get_irqmask(d), 0);
415 if (ret)
416 dev_err(priv->dev, "could not mask IRQ\n");
417 }
418
rtl8366rb_unmask_irq(struct irq_data * d)419 static void rtl8366rb_unmask_irq(struct irq_data *d)
420 {
421 struct realtek_priv *priv = irq_data_get_irq_chip_data(d);
422 int ret;
423
424 ret = regmap_update_bits(priv->map, RTL8366RB_INTERRUPT_MASK_REG,
425 rtl8366rb_get_irqmask(d),
426 rtl8366rb_get_irqmask(d));
427 if (ret)
428 dev_err(priv->dev, "could not unmask IRQ\n");
429 }
430
rtl8366rb_irq(int irq,void * data)431 static irqreturn_t rtl8366rb_irq(int irq, void *data)
432 {
433 struct realtek_priv *priv = data;
434 u32 stat;
435 int ret;
436
437 /* This clears the IRQ status register */
438 ret = regmap_read(priv->map, RTL8366RB_INTERRUPT_STATUS_REG,
439 &stat);
440 if (ret) {
441 dev_err(priv->dev, "can't read interrupt status\n");
442 return IRQ_NONE;
443 }
444 stat &= RTL8366RB_INTERRUPT_VALID;
445 if (!stat)
446 return IRQ_NONE;
447 while (stat) {
448 int line = __ffs(stat);
449 int child_irq;
450
451 stat &= ~BIT(line);
452 /* For line interrupts we combine link down in bits
453 * 6..11 with link up in bits 0..5 into one interrupt.
454 */
455 if (line < 12 && line > 5)
456 line -= 5;
457 child_irq = irq_find_mapping(priv->irqdomain, line);
458 handle_nested_irq(child_irq);
459 }
460 return IRQ_HANDLED;
461 }
462
463 static struct irq_chip rtl8366rb_irq_chip = {
464 .name = "RTL8366RB",
465 .irq_mask = rtl8366rb_mask_irq,
466 .irq_unmask = rtl8366rb_unmask_irq,
467 };
468
rtl8366rb_irq_map(struct irq_domain * domain,unsigned int irq,irq_hw_number_t hwirq)469 static int rtl8366rb_irq_map(struct irq_domain *domain, unsigned int irq,
470 irq_hw_number_t hwirq)
471 {
472 irq_set_chip_data(irq, domain->host_data);
473 irq_set_chip_and_handler(irq, &rtl8366rb_irq_chip, handle_simple_irq);
474 irq_set_nested_thread(irq, 1);
475 irq_set_noprobe(irq);
476
477 return 0;
478 }
479
rtl8366rb_irq_unmap(struct irq_domain * d,unsigned int irq)480 static void rtl8366rb_irq_unmap(struct irq_domain *d, unsigned int irq)
481 {
482 irq_set_nested_thread(irq, 0);
483 irq_set_chip_and_handler(irq, NULL, NULL);
484 irq_set_chip_data(irq, NULL);
485 }
486
487 static const struct irq_domain_ops rtl8366rb_irqdomain_ops = {
488 .map = rtl8366rb_irq_map,
489 .unmap = rtl8366rb_irq_unmap,
490 .xlate = irq_domain_xlate_onecell,
491 };
492
rtl8366rb_setup_cascaded_irq(struct realtek_priv * priv)493 static int rtl8366rb_setup_cascaded_irq(struct realtek_priv *priv)
494 {
495 struct device_node *intc;
496 unsigned long irq_trig;
497 int irq;
498 int ret;
499 u32 val;
500 int i;
501
502 intc = of_get_child_by_name(priv->dev->of_node, "interrupt-controller");
503 if (!intc) {
504 dev_err(priv->dev, "missing child interrupt-controller node\n");
505 return -EINVAL;
506 }
507 /* RB8366RB IRQs cascade off this one */
508 irq = of_irq_get(intc, 0);
509 if (irq <= 0) {
510 dev_err(priv->dev, "failed to get parent IRQ\n");
511 ret = irq ? irq : -EINVAL;
512 goto out_put_node;
513 }
514
515 /* This clears the IRQ status register */
516 ret = regmap_read(priv->map, RTL8366RB_INTERRUPT_STATUS_REG,
517 &val);
518 if (ret) {
519 dev_err(priv->dev, "can't read interrupt status\n");
520 goto out_put_node;
521 }
522
523 /* Fetch IRQ edge information from the descriptor */
524 irq_trig = irq_get_trigger_type(irq);
525 switch (irq_trig) {
526 case IRQF_TRIGGER_RISING:
527 case IRQF_TRIGGER_HIGH:
528 dev_info(priv->dev, "active high/rising IRQ\n");
529 val = 0;
530 break;
531 case IRQF_TRIGGER_FALLING:
532 case IRQF_TRIGGER_LOW:
533 dev_info(priv->dev, "active low/falling IRQ\n");
534 val = RTL8366RB_INTERRUPT_POLARITY;
535 break;
536 }
537 ret = regmap_update_bits(priv->map, RTL8366RB_INTERRUPT_CONTROL_REG,
538 RTL8366RB_INTERRUPT_POLARITY,
539 val);
540 if (ret) {
541 dev_err(priv->dev, "could not configure IRQ polarity\n");
542 goto out_put_node;
543 }
544
545 ret = devm_request_threaded_irq(priv->dev, irq, NULL,
546 rtl8366rb_irq, IRQF_ONESHOT,
547 "RTL8366RB", priv);
548 if (ret) {
549 dev_err(priv->dev, "unable to request irq: %d\n", ret);
550 goto out_put_node;
551 }
552 priv->irqdomain = irq_domain_add_linear(intc,
553 RTL8366RB_NUM_INTERRUPT,
554 &rtl8366rb_irqdomain_ops,
555 priv);
556 if (!priv->irqdomain) {
557 dev_err(priv->dev, "failed to create IRQ domain\n");
558 ret = -EINVAL;
559 goto out_put_node;
560 }
561 for (i = 0; i < priv->num_ports; i++)
562 irq_set_parent(irq_create_mapping(priv->irqdomain, i), irq);
563
564 out_put_node:
565 of_node_put(intc);
566 return ret;
567 }
568
rtl8366rb_set_addr(struct realtek_priv * priv)569 static int rtl8366rb_set_addr(struct realtek_priv *priv)
570 {
571 u8 addr[ETH_ALEN];
572 u16 val;
573 int ret;
574
575 eth_random_addr(addr);
576
577 dev_info(priv->dev, "set MAC: %02X:%02X:%02X:%02X:%02X:%02X\n",
578 addr[0], addr[1], addr[2], addr[3], addr[4], addr[5]);
579 val = addr[0] << 8 | addr[1];
580 ret = regmap_write(priv->map, RTL8366RB_SMAR0, val);
581 if (ret)
582 return ret;
583 val = addr[2] << 8 | addr[3];
584 ret = regmap_write(priv->map, RTL8366RB_SMAR1, val);
585 if (ret)
586 return ret;
587 val = addr[4] << 8 | addr[5];
588 ret = regmap_write(priv->map, RTL8366RB_SMAR2, val);
589 if (ret)
590 return ret;
591
592 return 0;
593 }
594
595 /* Found in a vendor driver */
596
597 /* Struct for handling the jam tables' entries */
598 struct rtl8366rb_jam_tbl_entry {
599 u16 reg;
600 u16 val;
601 };
602
603 /* For the "version 0" early silicon, appear in most source releases */
604 static const struct rtl8366rb_jam_tbl_entry rtl8366rb_init_jam_ver_0[] = {
605 {0x000B, 0x0001}, {0x03A6, 0x0100}, {0x03A7, 0x0001}, {0x02D1, 0x3FFF},
606 {0x02D2, 0x3FFF}, {0x02D3, 0x3FFF}, {0x02D4, 0x3FFF}, {0x02D5, 0x3FFF},
607 {0x02D6, 0x3FFF}, {0x02D7, 0x3FFF}, {0x02D8, 0x3FFF}, {0x022B, 0x0688},
608 {0x022C, 0x0FAC}, {0x03D0, 0x4688}, {0x03D1, 0x01F5}, {0x0000, 0x0830},
609 {0x02F9, 0x0200}, {0x02F7, 0x7FFF}, {0x02F8, 0x03FF}, {0x0080, 0x03E8},
610 {0x0081, 0x00CE}, {0x0082, 0x00DA}, {0x0083, 0x0230}, {0xBE0F, 0x2000},
611 {0x0231, 0x422A}, {0x0232, 0x422A}, {0x0233, 0x422A}, {0x0234, 0x422A},
612 {0x0235, 0x422A}, {0x0236, 0x422A}, {0x0237, 0x422A}, {0x0238, 0x422A},
613 {0x0239, 0x422A}, {0x023A, 0x422A}, {0x023B, 0x422A}, {0x023C, 0x422A},
614 {0x023D, 0x422A}, {0x023E, 0x422A}, {0x023F, 0x422A}, {0x0240, 0x422A},
615 {0x0241, 0x422A}, {0x0242, 0x422A}, {0x0243, 0x422A}, {0x0244, 0x422A},
616 {0x0245, 0x422A}, {0x0246, 0x422A}, {0x0247, 0x422A}, {0x0248, 0x422A},
617 {0x0249, 0x0146}, {0x024A, 0x0146}, {0x024B, 0x0146}, {0xBE03, 0xC961},
618 {0x024D, 0x0146}, {0x024E, 0x0146}, {0x024F, 0x0146}, {0x0250, 0x0146},
619 {0xBE64, 0x0226}, {0x0252, 0x0146}, {0x0253, 0x0146}, {0x024C, 0x0146},
620 {0x0251, 0x0146}, {0x0254, 0x0146}, {0xBE62, 0x3FD0}, {0x0084, 0x0320},
621 {0x0255, 0x0146}, {0x0256, 0x0146}, {0x0257, 0x0146}, {0x0258, 0x0146},
622 {0x0259, 0x0146}, {0x025A, 0x0146}, {0x025B, 0x0146}, {0x025C, 0x0146},
623 {0x025D, 0x0146}, {0x025E, 0x0146}, {0x025F, 0x0146}, {0x0260, 0x0146},
624 {0x0261, 0xA23F}, {0x0262, 0x0294}, {0x0263, 0xA23F}, {0x0264, 0x0294},
625 {0x0265, 0xA23F}, {0x0266, 0x0294}, {0x0267, 0xA23F}, {0x0268, 0x0294},
626 {0x0269, 0xA23F}, {0x026A, 0x0294}, {0x026B, 0xA23F}, {0x026C, 0x0294},
627 {0x026D, 0xA23F}, {0x026E, 0x0294}, {0x026F, 0xA23F}, {0x0270, 0x0294},
628 {0x02F5, 0x0048}, {0xBE09, 0x0E00}, {0xBE1E, 0x0FA0}, {0xBE14, 0x8448},
629 {0xBE15, 0x1007}, {0xBE4A, 0xA284}, {0xC454, 0x3F0B}, {0xC474, 0x3F0B},
630 {0xBE48, 0x3672}, {0xBE4B, 0x17A7}, {0xBE4C, 0x0B15}, {0xBE52, 0x0EDD},
631 {0xBE49, 0x8C00}, {0xBE5B, 0x785C}, {0xBE5C, 0x785C}, {0xBE5D, 0x785C},
632 {0xBE61, 0x368A}, {0xBE63, 0x9B84}, {0xC456, 0xCC13}, {0xC476, 0xCC13},
633 {0xBE65, 0x307D}, {0xBE6D, 0x0005}, {0xBE6E, 0xE120}, {0xBE2E, 0x7BAF},
634 };
635
636 /* This v1 init sequence is from Belkin F5D8235 U-Boot release */
637 static const struct rtl8366rb_jam_tbl_entry rtl8366rb_init_jam_ver_1[] = {
638 {0x0000, 0x0830}, {0x0001, 0x8000}, {0x0400, 0x8130}, {0xBE78, 0x3C3C},
639 {0x0431, 0x5432}, {0xBE37, 0x0CE4}, {0x02FA, 0xFFDF}, {0x02FB, 0xFFE0},
640 {0xC44C, 0x1585}, {0xC44C, 0x1185}, {0xC44C, 0x1585}, {0xC46C, 0x1585},
641 {0xC46C, 0x1185}, {0xC46C, 0x1585}, {0xC451, 0x2135}, {0xC471, 0x2135},
642 {0xBE10, 0x8140}, {0xBE15, 0x0007}, {0xBE6E, 0xE120}, {0xBE69, 0xD20F},
643 {0xBE6B, 0x0320}, {0xBE24, 0xB000}, {0xBE23, 0xFF51}, {0xBE22, 0xDF20},
644 {0xBE21, 0x0140}, {0xBE20, 0x00BB}, {0xBE24, 0xB800}, {0xBE24, 0x0000},
645 {0xBE24, 0x7000}, {0xBE23, 0xFF51}, {0xBE22, 0xDF60}, {0xBE21, 0x0140},
646 {0xBE20, 0x0077}, {0xBE24, 0x7800}, {0xBE24, 0x0000}, {0xBE2E, 0x7B7A},
647 {0xBE36, 0x0CE4}, {0x02F5, 0x0048}, {0xBE77, 0x2940}, {0x000A, 0x83E0},
648 {0xBE79, 0x3C3C}, {0xBE00, 0x1340},
649 };
650
651 /* This v2 init sequence is from Belkin F5D8235 U-Boot release */
652 static const struct rtl8366rb_jam_tbl_entry rtl8366rb_init_jam_ver_2[] = {
653 {0x0450, 0x0000}, {0x0400, 0x8130}, {0x000A, 0x83ED}, {0x0431, 0x5432},
654 {0xC44F, 0x6250}, {0xC46F, 0x6250}, {0xC456, 0x0C14}, {0xC476, 0x0C14},
655 {0xC44C, 0x1C85}, {0xC44C, 0x1885}, {0xC44C, 0x1C85}, {0xC46C, 0x1C85},
656 {0xC46C, 0x1885}, {0xC46C, 0x1C85}, {0xC44C, 0x0885}, {0xC44C, 0x0881},
657 {0xC44C, 0x0885}, {0xC46C, 0x0885}, {0xC46C, 0x0881}, {0xC46C, 0x0885},
658 {0xBE2E, 0x7BA7}, {0xBE36, 0x1000}, {0xBE37, 0x1000}, {0x8000, 0x0001},
659 {0xBE69, 0xD50F}, {0x8000, 0x0000}, {0xBE69, 0xD50F}, {0xBE6E, 0x0320},
660 {0xBE77, 0x2940}, {0xBE78, 0x3C3C}, {0xBE79, 0x3C3C}, {0xBE6E, 0xE120},
661 {0x8000, 0x0001}, {0xBE15, 0x1007}, {0x8000, 0x0000}, {0xBE15, 0x1007},
662 {0xBE14, 0x0448}, {0xBE1E, 0x00A0}, {0xBE10, 0x8160}, {0xBE10, 0x8140},
663 {0xBE00, 0x1340}, {0x0F51, 0x0010},
664 };
665
666 /* Appears in a DDWRT code dump */
667 static const struct rtl8366rb_jam_tbl_entry rtl8366rb_init_jam_ver_3[] = {
668 {0x0000, 0x0830}, {0x0400, 0x8130}, {0x000A, 0x83ED}, {0x0431, 0x5432},
669 {0x0F51, 0x0017}, {0x02F5, 0x0048}, {0x02FA, 0xFFDF}, {0x02FB, 0xFFE0},
670 {0xC456, 0x0C14}, {0xC476, 0x0C14}, {0xC454, 0x3F8B}, {0xC474, 0x3F8B},
671 {0xC450, 0x2071}, {0xC470, 0x2071}, {0xC451, 0x226B}, {0xC471, 0x226B},
672 {0xC452, 0xA293}, {0xC472, 0xA293}, {0xC44C, 0x1585}, {0xC44C, 0x1185},
673 {0xC44C, 0x1585}, {0xC46C, 0x1585}, {0xC46C, 0x1185}, {0xC46C, 0x1585},
674 {0xC44C, 0x0185}, {0xC44C, 0x0181}, {0xC44C, 0x0185}, {0xC46C, 0x0185},
675 {0xC46C, 0x0181}, {0xC46C, 0x0185}, {0xBE24, 0xB000}, {0xBE23, 0xFF51},
676 {0xBE22, 0xDF20}, {0xBE21, 0x0140}, {0xBE20, 0x00BB}, {0xBE24, 0xB800},
677 {0xBE24, 0x0000}, {0xBE24, 0x7000}, {0xBE23, 0xFF51}, {0xBE22, 0xDF60},
678 {0xBE21, 0x0140}, {0xBE20, 0x0077}, {0xBE24, 0x7800}, {0xBE24, 0x0000},
679 {0xBE2E, 0x7BA7}, {0xBE36, 0x1000}, {0xBE37, 0x1000}, {0x8000, 0x0001},
680 {0xBE69, 0xD50F}, {0x8000, 0x0000}, {0xBE69, 0xD50F}, {0xBE6B, 0x0320},
681 {0xBE77, 0x2800}, {0xBE78, 0x3C3C}, {0xBE79, 0x3C3C}, {0xBE6E, 0xE120},
682 {0x8000, 0x0001}, {0xBE10, 0x8140}, {0x8000, 0x0000}, {0xBE10, 0x8140},
683 {0xBE15, 0x1007}, {0xBE14, 0x0448}, {0xBE1E, 0x00A0}, {0xBE10, 0x8160},
684 {0xBE10, 0x8140}, {0xBE00, 0x1340}, {0x0450, 0x0000}, {0x0401, 0x0000},
685 };
686
687 /* Belkin F5D8235 v1, "belkin,f5d8235-v1" */
688 static const struct rtl8366rb_jam_tbl_entry rtl8366rb_init_jam_f5d8235[] = {
689 {0x0242, 0x02BF}, {0x0245, 0x02BF}, {0x0248, 0x02BF}, {0x024B, 0x02BF},
690 {0x024E, 0x02BF}, {0x0251, 0x02BF}, {0x0254, 0x0A3F}, {0x0256, 0x0A3F},
691 {0x0258, 0x0A3F}, {0x025A, 0x0A3F}, {0x025C, 0x0A3F}, {0x025E, 0x0A3F},
692 {0x0263, 0x007C}, {0x0100, 0x0004}, {0xBE5B, 0x3500}, {0x800E, 0x200F},
693 {0xBE1D, 0x0F00}, {0x8001, 0x5011}, {0x800A, 0xA2F4}, {0x800B, 0x17A3},
694 {0xBE4B, 0x17A3}, {0xBE41, 0x5011}, {0xBE17, 0x2100}, {0x8000, 0x8304},
695 {0xBE40, 0x8304}, {0xBE4A, 0xA2F4}, {0x800C, 0xA8D5}, {0x8014, 0x5500},
696 {0x8015, 0x0004}, {0xBE4C, 0xA8D5}, {0xBE59, 0x0008}, {0xBE09, 0x0E00},
697 {0xBE36, 0x1036}, {0xBE37, 0x1036}, {0x800D, 0x00FF}, {0xBE4D, 0x00FF},
698 };
699
700 /* DGN3500, "netgear,dgn3500", "netgear,dgn3500b" */
701 static const struct rtl8366rb_jam_tbl_entry rtl8366rb_init_jam_dgn3500[] = {
702 {0x0000, 0x0830}, {0x0400, 0x8130}, {0x000A, 0x83ED}, {0x0F51, 0x0017},
703 {0x02F5, 0x0048}, {0x02FA, 0xFFDF}, {0x02FB, 0xFFE0}, {0x0450, 0x0000},
704 {0x0401, 0x0000}, {0x0431, 0x0960},
705 };
706
707 /* This jam table activates "green ethernet", which means low power mode
708 * and is claimed to detect the cable length and not use more power than
709 * necessary, and the ports should enter power saving mode 10 seconds after
710 * a cable is disconnected. Seems to always be the same.
711 */
712 static const struct rtl8366rb_jam_tbl_entry rtl8366rb_green_jam[] = {
713 {0xBE78, 0x323C}, {0xBE77, 0x5000}, {0xBE2E, 0x7BA7},
714 {0xBE59, 0x3459}, {0xBE5A, 0x745A}, {0xBE5B, 0x785C},
715 {0xBE5C, 0x785C}, {0xBE6E, 0xE120}, {0xBE79, 0x323C},
716 };
717
718 /* Function that jams the tables in the proper registers */
rtl8366rb_jam_table(const struct rtl8366rb_jam_tbl_entry * jam_table,int jam_size,struct realtek_priv * priv,bool write_dbg)719 static int rtl8366rb_jam_table(const struct rtl8366rb_jam_tbl_entry *jam_table,
720 int jam_size, struct realtek_priv *priv,
721 bool write_dbg)
722 {
723 u32 val;
724 int ret;
725 int i;
726
727 for (i = 0; i < jam_size; i++) {
728 if ((jam_table[i].reg & 0xBE00) == 0xBE00) {
729 ret = regmap_read(priv->map,
730 RTL8366RB_PHY_ACCESS_BUSY_REG,
731 &val);
732 if (ret)
733 return ret;
734 if (!(val & RTL8366RB_PHY_INT_BUSY)) {
735 ret = regmap_write(priv->map,
736 RTL8366RB_PHY_ACCESS_CTRL_REG,
737 RTL8366RB_PHY_CTRL_WRITE);
738 if (ret)
739 return ret;
740 }
741 }
742 if (write_dbg)
743 dev_dbg(priv->dev, "jam %04x into register %04x\n",
744 jam_table[i].val,
745 jam_table[i].reg);
746 ret = regmap_write(priv->map,
747 jam_table[i].reg,
748 jam_table[i].val);
749 if (ret)
750 return ret;
751 }
752 return 0;
753 }
754
755 /* This code is used also with LEDs disabled */
rb8366rb_set_ledgroup_mode(struct realtek_priv * priv,u8 led_group,enum rtl8366_ledgroup_mode mode)756 int rb8366rb_set_ledgroup_mode(struct realtek_priv *priv,
757 u8 led_group,
758 enum rtl8366_ledgroup_mode mode)
759 {
760 int ret;
761 u32 val;
762
763 val = mode << RTL8366RB_LED_CTRL_OFFSET(led_group);
764
765 ret = regmap_update_bits(priv->map,
766 RTL8366RB_LED_CTRL_REG,
767 RTL8366RB_LED_CTRL_MASK(led_group),
768 val);
769 if (ret)
770 return ret;
771
772 return 0;
773 }
774
775 /* This code is used also with LEDs disabled */
rtl8366rb_setup_all_leds_off(struct realtek_priv * priv)776 static int rtl8366rb_setup_all_leds_off(struct realtek_priv *priv)
777 {
778 int ret = 0;
779 int i;
780
781 regmap_update_bits(priv->map,
782 RTL8366RB_INTERRUPT_CONTROL_REG,
783 RTL8366RB_P4_RGMII_LED,
784 0);
785
786 for (i = 0; i < RTL8366RB_NUM_LEDGROUPS; i++) {
787 ret = rb8366rb_set_ledgroup_mode(priv, i,
788 RTL8366RB_LEDGROUP_OFF);
789 if (ret)
790 return ret;
791 }
792
793 return ret;
794 }
795
rtl8366rb_setup(struct dsa_switch * ds)796 static int rtl8366rb_setup(struct dsa_switch *ds)
797 {
798 struct realtek_priv *priv = ds->priv;
799 const struct rtl8366rb_jam_tbl_entry *jam_table;
800 struct rtl8366rb *rb;
801 u32 chip_ver = 0;
802 u32 chip_id = 0;
803 int jam_size;
804 int ret;
805 int i;
806
807 rb = priv->chip_data;
808
809 ret = regmap_read(priv->map, RTL8366RB_CHIP_ID_REG, &chip_id);
810 if (ret) {
811 dev_err(priv->dev, "unable to read chip id\n");
812 return ret;
813 }
814
815 switch (chip_id) {
816 case RTL8366RB_CHIP_ID_8366:
817 break;
818 default:
819 dev_err(priv->dev, "unknown chip id (%04x)\n", chip_id);
820 return -ENODEV;
821 }
822
823 ret = regmap_read(priv->map, RTL8366RB_CHIP_VERSION_CTRL_REG,
824 &chip_ver);
825 if (ret) {
826 dev_err(priv->dev, "unable to read chip version\n");
827 return ret;
828 }
829
830 dev_info(priv->dev, "RTL%04x ver %u chip found\n",
831 chip_id, chip_ver & RTL8366RB_CHIP_VERSION_MASK);
832
833 /* Do the init dance using the right jam table */
834 switch (chip_ver) {
835 case 0:
836 jam_table = rtl8366rb_init_jam_ver_0;
837 jam_size = ARRAY_SIZE(rtl8366rb_init_jam_ver_0);
838 break;
839 case 1:
840 jam_table = rtl8366rb_init_jam_ver_1;
841 jam_size = ARRAY_SIZE(rtl8366rb_init_jam_ver_1);
842 break;
843 case 2:
844 jam_table = rtl8366rb_init_jam_ver_2;
845 jam_size = ARRAY_SIZE(rtl8366rb_init_jam_ver_2);
846 break;
847 default:
848 jam_table = rtl8366rb_init_jam_ver_3;
849 jam_size = ARRAY_SIZE(rtl8366rb_init_jam_ver_3);
850 break;
851 }
852
853 /* Special jam tables for special routers
854 * TODO: are these necessary? Maintainers, please test
855 * without them, using just the off-the-shelf tables.
856 */
857 if (of_machine_is_compatible("belkin,f5d8235-v1")) {
858 jam_table = rtl8366rb_init_jam_f5d8235;
859 jam_size = ARRAY_SIZE(rtl8366rb_init_jam_f5d8235);
860 }
861 if (of_machine_is_compatible("netgear,dgn3500") ||
862 of_machine_is_compatible("netgear,dgn3500b")) {
863 jam_table = rtl8366rb_init_jam_dgn3500;
864 jam_size = ARRAY_SIZE(rtl8366rb_init_jam_dgn3500);
865 }
866
867 ret = rtl8366rb_jam_table(jam_table, jam_size, priv, true);
868 if (ret)
869 return ret;
870
871 /* Isolate all user ports so they can only send packets to itself and the CPU port */
872 for (i = 0; i < RTL8366RB_PORT_NUM_CPU; i++) {
873 ret = regmap_write(priv->map, RTL8366RB_PORT_ISO(i),
874 RTL8366RB_PORT_ISO_PORTS(BIT(RTL8366RB_PORT_NUM_CPU)) |
875 RTL8366RB_PORT_ISO_EN);
876 if (ret)
877 return ret;
878 }
879 /* CPU port can send packets to all ports */
880 ret = regmap_write(priv->map, RTL8366RB_PORT_ISO(RTL8366RB_PORT_NUM_CPU),
881 RTL8366RB_PORT_ISO_PORTS(dsa_user_ports(ds)) |
882 RTL8366RB_PORT_ISO_EN);
883 if (ret)
884 return ret;
885
886 /* Set up the "green ethernet" feature */
887 ret = rtl8366rb_jam_table(rtl8366rb_green_jam,
888 ARRAY_SIZE(rtl8366rb_green_jam), priv, false);
889 if (ret)
890 return ret;
891
892 ret = regmap_write(priv->map,
893 RTL8366RB_GREEN_FEATURE_REG,
894 (chip_ver == 1) ? 0x0007 : 0x0003);
895 if (ret)
896 return ret;
897
898 /* Vendor driver sets 0x240 in registers 0xc and 0xd (undocumented) */
899 ret = regmap_write(priv->map, 0x0c, 0x240);
900 if (ret)
901 return ret;
902 ret = regmap_write(priv->map, 0x0d, 0x240);
903 if (ret)
904 return ret;
905
906 /* Set some random MAC address */
907 ret = rtl8366rb_set_addr(priv);
908 if (ret)
909 return ret;
910
911 /* Enable CPU port with custom DSA tag 8899.
912 *
913 * If you set RTL8366RB_CPU_NO_TAG (bit 15) in this register
914 * the custom tag is turned off.
915 */
916 ret = regmap_update_bits(priv->map, RTL8366RB_CPU_CTRL_REG,
917 0xFFFF,
918 BIT(priv->cpu_port));
919 if (ret)
920 return ret;
921
922 /* Make sure we default-enable the fixed CPU port */
923 ret = regmap_update_bits(priv->map, RTL8366RB_PECR,
924 BIT(priv->cpu_port),
925 0);
926 if (ret)
927 return ret;
928
929 /* Set default maximum packet length to 1536 bytes */
930 ret = regmap_update_bits(priv->map, RTL8366RB_SGCR,
931 RTL8366RB_SGCR_MAX_LENGTH_MASK,
932 RTL8366RB_SGCR_MAX_LENGTH_1536);
933 if (ret)
934 return ret;
935 for (i = 0; i < RTL8366RB_NUM_PORTS; i++) {
936 if (i == priv->cpu_port)
937 /* CPU port need to also accept the tag */
938 rb->max_mtu[i] = ETH_DATA_LEN + RTL8366RB_CPU_TAG_SIZE;
939 else
940 rb->max_mtu[i] = ETH_DATA_LEN;
941 }
942
943 /* Disable learning for all ports */
944 ret = regmap_write(priv->map, RTL8366RB_PORT_LEARNDIS_CTRL,
945 RTL8366RB_PORT_ALL);
946 if (ret)
947 return ret;
948
949 /* Enable auto ageing for all ports */
950 ret = regmap_write(priv->map, RTL8366RB_SECURITY_CTRL, 0);
951 if (ret)
952 return ret;
953
954 /* Port 4 setup: this enables Port 4, usually the WAN port,
955 * common PHY IO mode is apparently mode 0, and this is not what
956 * the port is initialized to. There is no explanation of the
957 * IO modes in the Realtek source code, if your WAN port is
958 * connected to something exotic such as fiber, then this might
959 * be worth experimenting with.
960 */
961 ret = regmap_update_bits(priv->map, RTL8366RB_PMC0,
962 RTL8366RB_PMC0_P4_IOMODE_MASK,
963 0 << RTL8366RB_PMC0_P4_IOMODE_SHIFT);
964 if (ret)
965 return ret;
966
967 /* Accept all packets by default, we enable filtering on-demand */
968 ret = regmap_write(priv->map, RTL8366RB_VLAN_INGRESS_CTRL1_REG,
969 0);
970 if (ret)
971 return ret;
972 ret = regmap_write(priv->map, RTL8366RB_VLAN_INGRESS_CTRL2_REG,
973 0);
974 if (ret)
975 return ret;
976
977 /* Don't drop packets whose DA has not been learned */
978 ret = regmap_update_bits(priv->map, RTL8366RB_SSCR2,
979 RTL8366RB_SSCR2_DROP_UNKNOWN_DA, 0);
980 if (ret)
981 return ret;
982
983 /* Set blinking, used by all LED groups using HW triggers.
984 * TODO: make this configurable
985 */
986 ret = regmap_update_bits(priv->map, RTL8366RB_LED_BLINKRATE_REG,
987 RTL8366RB_LED_BLINKRATE_MASK,
988 RTL8366RB_LED_BLINKRATE_56MS);
989 if (ret)
990 return ret;
991
992 /* Set up LED activity:
993 * Each port has 4 LEDs on fixed groups. Each group shares the same
994 * hardware trigger across all ports. LEDs can only be indiviually
995 * controlled setting the LED group to fixed mode and using the driver
996 * to toggle them LEDs on/off.
997 */
998 if (priv->leds_disabled) {
999 ret = rtl8366rb_setup_all_leds_off(priv);
1000 if (ret)
1001 return ret;
1002 } else {
1003 ret = rtl8366rb_setup_leds(priv);
1004 if (ret)
1005 return ret;
1006 }
1007
1008 ret = rtl8366_reset_vlan(priv);
1009 if (ret)
1010 return ret;
1011
1012 ret = rtl8366rb_setup_cascaded_irq(priv);
1013 if (ret)
1014 dev_info(priv->dev, "no interrupt support\n");
1015
1016 ret = rtl83xx_setup_user_mdio(ds);
1017 if (ret) {
1018 dev_err(priv->dev, "could not set up MDIO bus\n");
1019 return -ENODEV;
1020 }
1021
1022 return 0;
1023 }
1024
rtl8366_get_tag_protocol(struct dsa_switch * ds,int port,enum dsa_tag_protocol mp)1025 static enum dsa_tag_protocol rtl8366_get_tag_protocol(struct dsa_switch *ds,
1026 int port,
1027 enum dsa_tag_protocol mp)
1028 {
1029 /* This switch uses the 4 byte protocol A Realtek DSA tag */
1030 return DSA_TAG_PROTO_RTL4_A;
1031 }
1032
rtl8366rb_phylink_get_caps(struct dsa_switch * ds,int port,struct phylink_config * config)1033 static void rtl8366rb_phylink_get_caps(struct dsa_switch *ds, int port,
1034 struct phylink_config *config)
1035 {
1036 unsigned long *interfaces = config->supported_interfaces;
1037 struct realtek_priv *priv = ds->priv;
1038
1039 if (port == priv->cpu_port) {
1040 __set_bit(PHY_INTERFACE_MODE_MII, interfaces);
1041 __set_bit(PHY_INTERFACE_MODE_GMII, interfaces);
1042 /* REVMII only supports 100M FD */
1043 __set_bit(PHY_INTERFACE_MODE_REVMII, interfaces);
1044 /* RGMII only supports 1G FD */
1045 phy_interface_set_rgmii(interfaces);
1046
1047 config->mac_capabilities = MAC_1000 | MAC_100 |
1048 MAC_SYM_PAUSE;
1049 } else {
1050 /* RSGMII port, but we don't have that, and we don't
1051 * specify in DT, so phylib uses the default of GMII
1052 */
1053 __set_bit(PHY_INTERFACE_MODE_GMII, interfaces);
1054 config->mac_capabilities = MAC_1000 | MAC_100 | MAC_10 |
1055 MAC_SYM_PAUSE | MAC_ASYM_PAUSE;
1056 }
1057 }
1058
1059 static void
rtl8366rb_mac_config(struct phylink_config * config,unsigned int mode,const struct phylink_link_state * state)1060 rtl8366rb_mac_config(struct phylink_config *config, unsigned int mode,
1061 const struct phylink_link_state *state)
1062 {
1063 }
1064
1065 static void
rtl8366rb_mac_link_up(struct phylink_config * config,struct phy_device * phydev,unsigned int mode,phy_interface_t interface,int speed,int duplex,bool tx_pause,bool rx_pause)1066 rtl8366rb_mac_link_up(struct phylink_config *config, struct phy_device *phydev,
1067 unsigned int mode, phy_interface_t interface,
1068 int speed, int duplex, bool tx_pause, bool rx_pause)
1069 {
1070 struct dsa_port *dp = dsa_phylink_to_port(config);
1071 struct realtek_priv *priv = dp->ds->priv;
1072 int port = dp->index;
1073 unsigned int val;
1074 int ret;
1075
1076 /* Allow forcing the mode on the fixed CPU port, no autonegotiation.
1077 * We assume autonegotiation works on the PHY-facing ports.
1078 */
1079 if (port != priv->cpu_port)
1080 return;
1081
1082 dev_dbg(priv->dev, "MAC link up on CPU port (%d)\n", port);
1083
1084 ret = regmap_update_bits(priv->map, RTL8366RB_MAC_FORCE_CTRL_REG,
1085 BIT(port), BIT(port));
1086 if (ret) {
1087 dev_err(priv->dev, "failed to force CPU port\n");
1088 return;
1089 }
1090
1091 /* Conjure port config */
1092 switch (speed) {
1093 case SPEED_10:
1094 val = RTL8366RB_PAACR_SPEED_10M;
1095 break;
1096 case SPEED_100:
1097 val = RTL8366RB_PAACR_SPEED_100M;
1098 break;
1099 case SPEED_1000:
1100 val = RTL8366RB_PAACR_SPEED_1000M;
1101 break;
1102 default:
1103 val = RTL8366RB_PAACR_SPEED_1000M;
1104 break;
1105 }
1106
1107 if (duplex == DUPLEX_FULL)
1108 val |= RTL8366RB_PAACR_FULL_DUPLEX;
1109
1110 if (tx_pause)
1111 val |= RTL8366RB_PAACR_TX_PAUSE;
1112
1113 if (rx_pause)
1114 val |= RTL8366RB_PAACR_RX_PAUSE;
1115
1116 val |= RTL8366RB_PAACR_LINK_UP;
1117
1118 ret = regmap_update_bits(priv->map, RTL8366RB_PAACR2,
1119 0xFF00U,
1120 val << 8);
1121 if (ret) {
1122 dev_err(priv->dev, "failed to set PAACR on CPU port\n");
1123 return;
1124 }
1125
1126 dev_dbg(priv->dev, "set PAACR to %04x\n", val);
1127
1128 /* Enable the CPU port */
1129 ret = regmap_update_bits(priv->map, RTL8366RB_PECR, BIT(port),
1130 0);
1131 if (ret) {
1132 dev_err(priv->dev, "failed to enable the CPU port\n");
1133 return;
1134 }
1135 }
1136
1137 static void
rtl8366rb_mac_link_down(struct phylink_config * config,unsigned int mode,phy_interface_t interface)1138 rtl8366rb_mac_link_down(struct phylink_config *config, unsigned int mode,
1139 phy_interface_t interface)
1140 {
1141 struct dsa_port *dp = dsa_phylink_to_port(config);
1142 struct realtek_priv *priv = dp->ds->priv;
1143 int port = dp->index;
1144 int ret;
1145
1146 if (port != priv->cpu_port)
1147 return;
1148
1149 dev_dbg(priv->dev, "MAC link down on CPU port (%d)\n", port);
1150
1151 /* Disable the CPU port */
1152 ret = regmap_update_bits(priv->map, RTL8366RB_PECR, BIT(port),
1153 BIT(port));
1154 if (ret) {
1155 dev_err(priv->dev, "failed to disable the CPU port\n");
1156 return;
1157 }
1158 }
1159
1160 static int
rtl8366rb_port_enable(struct dsa_switch * ds,int port,struct phy_device * phy)1161 rtl8366rb_port_enable(struct dsa_switch *ds, int port,
1162 struct phy_device *phy)
1163 {
1164 struct realtek_priv *priv = ds->priv;
1165 int ret;
1166
1167 dev_dbg(priv->dev, "enable port %d\n", port);
1168 ret = regmap_update_bits(priv->map, RTL8366RB_PECR, BIT(port),
1169 0);
1170 if (ret)
1171 return ret;
1172
1173 return 0;
1174 }
1175
1176 static void
rtl8366rb_port_disable(struct dsa_switch * ds,int port)1177 rtl8366rb_port_disable(struct dsa_switch *ds, int port)
1178 {
1179 struct realtek_priv *priv = ds->priv;
1180 int ret;
1181
1182 dev_dbg(priv->dev, "disable port %d\n", port);
1183 ret = regmap_update_bits(priv->map, RTL8366RB_PECR, BIT(port),
1184 BIT(port));
1185 if (ret)
1186 return;
1187 }
1188
1189 static int
rtl8366rb_port_bridge_join(struct dsa_switch * ds,int port,struct dsa_bridge bridge,bool * tx_fwd_offload,struct netlink_ext_ack * extack)1190 rtl8366rb_port_bridge_join(struct dsa_switch *ds, int port,
1191 struct dsa_bridge bridge,
1192 bool *tx_fwd_offload,
1193 struct netlink_ext_ack *extack)
1194 {
1195 struct realtek_priv *priv = ds->priv;
1196 unsigned int port_bitmap = 0;
1197 int ret, i;
1198
1199 /* Loop over all other ports than the current one */
1200 for (i = 0; i < RTL8366RB_PORT_NUM_CPU; i++) {
1201 /* Current port handled last */
1202 if (i == port)
1203 continue;
1204 /* Not on this bridge */
1205 if (!dsa_port_offloads_bridge(dsa_to_port(ds, i), &bridge))
1206 continue;
1207 /* Join this port to each other port on the bridge */
1208 ret = regmap_update_bits(priv->map, RTL8366RB_PORT_ISO(i),
1209 RTL8366RB_PORT_ISO_PORTS(BIT(port)),
1210 RTL8366RB_PORT_ISO_PORTS(BIT(port)));
1211 if (ret)
1212 dev_err(priv->dev, "failed to join port %d\n", port);
1213
1214 port_bitmap |= BIT(i);
1215 }
1216
1217 /* Set the bits for the ports we can access */
1218 return regmap_update_bits(priv->map, RTL8366RB_PORT_ISO(port),
1219 RTL8366RB_PORT_ISO_PORTS(port_bitmap),
1220 RTL8366RB_PORT_ISO_PORTS(port_bitmap));
1221 }
1222
1223 static void
rtl8366rb_port_bridge_leave(struct dsa_switch * ds,int port,struct dsa_bridge bridge)1224 rtl8366rb_port_bridge_leave(struct dsa_switch *ds, int port,
1225 struct dsa_bridge bridge)
1226 {
1227 struct realtek_priv *priv = ds->priv;
1228 unsigned int port_bitmap = 0;
1229 int ret, i;
1230
1231 /* Loop over all other ports than this one */
1232 for (i = 0; i < RTL8366RB_PORT_NUM_CPU; i++) {
1233 /* Current port handled last */
1234 if (i == port)
1235 continue;
1236 /* Not on this bridge */
1237 if (!dsa_port_offloads_bridge(dsa_to_port(ds, i), &bridge))
1238 continue;
1239 /* Remove this port from any other port on the bridge */
1240 ret = regmap_update_bits(priv->map, RTL8366RB_PORT_ISO(i),
1241 RTL8366RB_PORT_ISO_PORTS(BIT(port)), 0);
1242 if (ret)
1243 dev_err(priv->dev, "failed to leave port %d\n", port);
1244
1245 port_bitmap |= BIT(i);
1246 }
1247
1248 /* Clear the bits for the ports we can not access, leave ourselves */
1249 regmap_update_bits(priv->map, RTL8366RB_PORT_ISO(port),
1250 RTL8366RB_PORT_ISO_PORTS(port_bitmap), 0);
1251 }
1252
1253 /**
1254 * rtl8366rb_drop_untagged() - make the switch drop untagged and C-tagged frames
1255 * @priv: SMI state container
1256 * @port: the port to drop untagged and C-tagged frames on
1257 * @drop: whether to drop or pass untagged and C-tagged frames
1258 *
1259 * Return: zero for success, a negative number on error.
1260 */
rtl8366rb_drop_untagged(struct realtek_priv * priv,int port,bool drop)1261 static int rtl8366rb_drop_untagged(struct realtek_priv *priv, int port, bool drop)
1262 {
1263 return regmap_update_bits(priv->map, RTL8366RB_VLAN_INGRESS_CTRL1_REG,
1264 RTL8366RB_VLAN_INGRESS_CTRL1_DROP(port),
1265 drop ? RTL8366RB_VLAN_INGRESS_CTRL1_DROP(port) : 0);
1266 }
1267
rtl8366rb_vlan_filtering(struct dsa_switch * ds,int port,bool vlan_filtering,struct netlink_ext_ack * extack)1268 static int rtl8366rb_vlan_filtering(struct dsa_switch *ds, int port,
1269 bool vlan_filtering,
1270 struct netlink_ext_ack *extack)
1271 {
1272 struct realtek_priv *priv = ds->priv;
1273 struct rtl8366rb *rb;
1274 int ret;
1275
1276 rb = priv->chip_data;
1277
1278 dev_dbg(priv->dev, "port %d: %s VLAN filtering\n", port,
1279 vlan_filtering ? "enable" : "disable");
1280
1281 /* If the port is not in the member set, the frame will be dropped */
1282 ret = regmap_update_bits(priv->map, RTL8366RB_VLAN_INGRESS_CTRL2_REG,
1283 BIT(port), vlan_filtering ? BIT(port) : 0);
1284 if (ret)
1285 return ret;
1286
1287 /* If VLAN filtering is enabled and PVID is also enabled, we must
1288 * not drop any untagged or C-tagged frames. If we turn off VLAN
1289 * filtering on a port, we need to accept any frames.
1290 */
1291 if (vlan_filtering)
1292 ret = rtl8366rb_drop_untagged(priv, port, !rb->pvid_enabled[port]);
1293 else
1294 ret = rtl8366rb_drop_untagged(priv, port, false);
1295
1296 return ret;
1297 }
1298
1299 static int
rtl8366rb_port_pre_bridge_flags(struct dsa_switch * ds,int port,struct switchdev_brport_flags flags,struct netlink_ext_ack * extack)1300 rtl8366rb_port_pre_bridge_flags(struct dsa_switch *ds, int port,
1301 struct switchdev_brport_flags flags,
1302 struct netlink_ext_ack *extack)
1303 {
1304 /* We support enabling/disabling learning */
1305 if (flags.mask & ~(BR_LEARNING))
1306 return -EINVAL;
1307
1308 return 0;
1309 }
1310
1311 static int
rtl8366rb_port_bridge_flags(struct dsa_switch * ds,int port,struct switchdev_brport_flags flags,struct netlink_ext_ack * extack)1312 rtl8366rb_port_bridge_flags(struct dsa_switch *ds, int port,
1313 struct switchdev_brport_flags flags,
1314 struct netlink_ext_ack *extack)
1315 {
1316 struct realtek_priv *priv = ds->priv;
1317 int ret;
1318
1319 if (flags.mask & BR_LEARNING) {
1320 ret = regmap_update_bits(priv->map, RTL8366RB_PORT_LEARNDIS_CTRL,
1321 BIT(port),
1322 (flags.val & BR_LEARNING) ? 0 : BIT(port));
1323 if (ret)
1324 return ret;
1325 }
1326
1327 return 0;
1328 }
1329
1330 static void
rtl8366rb_port_stp_state_set(struct dsa_switch * ds,int port,u8 state)1331 rtl8366rb_port_stp_state_set(struct dsa_switch *ds, int port, u8 state)
1332 {
1333 struct realtek_priv *priv = ds->priv;
1334 u32 val;
1335 int i;
1336
1337 switch (state) {
1338 case BR_STATE_DISABLED:
1339 val = RTL8366RB_STP_STATE_DISABLED;
1340 break;
1341 case BR_STATE_BLOCKING:
1342 case BR_STATE_LISTENING:
1343 val = RTL8366RB_STP_STATE_BLOCKING;
1344 break;
1345 case BR_STATE_LEARNING:
1346 val = RTL8366RB_STP_STATE_LEARNING;
1347 break;
1348 case BR_STATE_FORWARDING:
1349 val = RTL8366RB_STP_STATE_FORWARDING;
1350 break;
1351 default:
1352 dev_err(priv->dev, "unknown bridge state requested\n");
1353 return;
1354 }
1355
1356 /* Set the same status for the port on all the FIDs */
1357 for (i = 0; i < RTL8366RB_NUM_FIDS; i++) {
1358 regmap_update_bits(priv->map, RTL8366RB_STP_STATE_BASE + i,
1359 RTL8366RB_STP_STATE_MASK(port),
1360 RTL8366RB_STP_STATE(port, val));
1361 }
1362 }
1363
1364 static void
rtl8366rb_port_fast_age(struct dsa_switch * ds,int port)1365 rtl8366rb_port_fast_age(struct dsa_switch *ds, int port)
1366 {
1367 struct realtek_priv *priv = ds->priv;
1368
1369 /* This will age out any learned L2 entries */
1370 regmap_update_bits(priv->map, RTL8366RB_SECURITY_CTRL,
1371 BIT(port), BIT(port));
1372 /* Restore the normal state of things */
1373 regmap_update_bits(priv->map, RTL8366RB_SECURITY_CTRL,
1374 BIT(port), 0);
1375 }
1376
rtl8366rb_change_mtu(struct dsa_switch * ds,int port,int new_mtu)1377 static int rtl8366rb_change_mtu(struct dsa_switch *ds, int port, int new_mtu)
1378 {
1379 struct realtek_priv *priv = ds->priv;
1380 struct rtl8366rb *rb;
1381 unsigned int max_mtu;
1382 u32 len;
1383 int i;
1384
1385 /* Cache the per-port MTU setting */
1386 rb = priv->chip_data;
1387 rb->max_mtu[port] = new_mtu;
1388
1389 /* Roof out the MTU for the entire switch to the greatest
1390 * common denominator: the biggest set for any one port will
1391 * be the biggest MTU for the switch.
1392 */
1393 max_mtu = ETH_DATA_LEN;
1394 for (i = 0; i < RTL8366RB_NUM_PORTS; i++) {
1395 if (rb->max_mtu[i] > max_mtu)
1396 max_mtu = rb->max_mtu[i];
1397 }
1398
1399 /* Translate to layer 2 size.
1400 * Add ethernet and (possible) VLAN headers, and checksum to the size.
1401 * For ETH_DATA_LEN (1500 bytes) this will add up to 1522 bytes.
1402 */
1403 max_mtu += VLAN_ETH_HLEN;
1404 max_mtu += ETH_FCS_LEN;
1405
1406 if (max_mtu <= 1522)
1407 len = RTL8366RB_SGCR_MAX_LENGTH_1522;
1408 else if (max_mtu > 1522 && max_mtu <= 1536)
1409 /* This will be the most common default if using VLAN and
1410 * CPU tagging on a port as both VLAN and CPU tag will
1411 * result in 1518 + 4 + 4 = 1526 bytes.
1412 */
1413 len = RTL8366RB_SGCR_MAX_LENGTH_1536;
1414 else if (max_mtu > 1536 && max_mtu <= 1552)
1415 len = RTL8366RB_SGCR_MAX_LENGTH_1552;
1416 else
1417 len = RTL8366RB_SGCR_MAX_LENGTH_16000;
1418
1419 return regmap_update_bits(priv->map, RTL8366RB_SGCR,
1420 RTL8366RB_SGCR_MAX_LENGTH_MASK,
1421 len);
1422 }
1423
rtl8366rb_max_mtu(struct dsa_switch * ds,int port)1424 static int rtl8366rb_max_mtu(struct dsa_switch *ds, int port)
1425 {
1426 /* The max MTU is 16000 bytes, so we subtract the ethernet
1427 * headers with VLAN and checksum and arrive at
1428 * 16000 - 18 - 4 = 15978. This does not include the CPU tag
1429 * since that is added to the requested MTU by the DSA framework.
1430 */
1431 return 16000 - VLAN_ETH_HLEN - ETH_FCS_LEN;
1432 }
1433
rtl8366rb_get_vlan_4k(struct realtek_priv * priv,u32 vid,struct rtl8366_vlan_4k * vlan4k)1434 static int rtl8366rb_get_vlan_4k(struct realtek_priv *priv, u32 vid,
1435 struct rtl8366_vlan_4k *vlan4k)
1436 {
1437 u32 data[3];
1438 int ret;
1439 int i;
1440
1441 memset(vlan4k, '\0', sizeof(struct rtl8366_vlan_4k));
1442
1443 if (vid >= RTL8366RB_NUM_VIDS)
1444 return -EINVAL;
1445
1446 /* write VID */
1447 ret = regmap_write(priv->map, RTL8366RB_VLAN_TABLE_WRITE_BASE,
1448 vid & RTL8366RB_VLAN_VID_MASK);
1449 if (ret)
1450 return ret;
1451
1452 /* write table access control word */
1453 ret = regmap_write(priv->map, RTL8366RB_TABLE_ACCESS_CTRL_REG,
1454 RTL8366RB_TABLE_VLAN_READ_CTRL);
1455 if (ret)
1456 return ret;
1457
1458 for (i = 0; i < 3; i++) {
1459 ret = regmap_read(priv->map,
1460 RTL8366RB_VLAN_TABLE_READ_BASE + i,
1461 &data[i]);
1462 if (ret)
1463 return ret;
1464 }
1465
1466 vlan4k->vid = vid;
1467 vlan4k->untag = (data[1] >> RTL8366RB_VLAN_UNTAG_SHIFT) &
1468 RTL8366RB_VLAN_UNTAG_MASK;
1469 vlan4k->member = data[1] & RTL8366RB_VLAN_MEMBER_MASK;
1470 vlan4k->fid = data[2] & RTL8366RB_VLAN_FID_MASK;
1471
1472 return 0;
1473 }
1474
rtl8366rb_set_vlan_4k(struct realtek_priv * priv,const struct rtl8366_vlan_4k * vlan4k)1475 static int rtl8366rb_set_vlan_4k(struct realtek_priv *priv,
1476 const struct rtl8366_vlan_4k *vlan4k)
1477 {
1478 u32 data[3];
1479 int ret;
1480 int i;
1481
1482 if (vlan4k->vid >= RTL8366RB_NUM_VIDS ||
1483 vlan4k->member > RTL8366RB_VLAN_MEMBER_MASK ||
1484 vlan4k->untag > RTL8366RB_VLAN_UNTAG_MASK ||
1485 vlan4k->fid > RTL8366RB_FIDMAX)
1486 return -EINVAL;
1487
1488 data[0] = vlan4k->vid & RTL8366RB_VLAN_VID_MASK;
1489 data[1] = (vlan4k->member & RTL8366RB_VLAN_MEMBER_MASK) |
1490 ((vlan4k->untag & RTL8366RB_VLAN_UNTAG_MASK) <<
1491 RTL8366RB_VLAN_UNTAG_SHIFT);
1492 data[2] = vlan4k->fid & RTL8366RB_VLAN_FID_MASK;
1493
1494 for (i = 0; i < 3; i++) {
1495 ret = regmap_write(priv->map,
1496 RTL8366RB_VLAN_TABLE_WRITE_BASE + i,
1497 data[i]);
1498 if (ret)
1499 return ret;
1500 }
1501
1502 /* write table access control word */
1503 ret = regmap_write(priv->map, RTL8366RB_TABLE_ACCESS_CTRL_REG,
1504 RTL8366RB_TABLE_VLAN_WRITE_CTRL);
1505
1506 return ret;
1507 }
1508
rtl8366rb_get_vlan_mc(struct realtek_priv * priv,u32 index,struct rtl8366_vlan_mc * vlanmc)1509 static int rtl8366rb_get_vlan_mc(struct realtek_priv *priv, u32 index,
1510 struct rtl8366_vlan_mc *vlanmc)
1511 {
1512 u32 data[3];
1513 int ret;
1514 int i;
1515
1516 memset(vlanmc, '\0', sizeof(struct rtl8366_vlan_mc));
1517
1518 if (index >= RTL8366RB_NUM_VLANS)
1519 return -EINVAL;
1520
1521 for (i = 0; i < 3; i++) {
1522 ret = regmap_read(priv->map,
1523 RTL8366RB_VLAN_MC_BASE(index) + i,
1524 &data[i]);
1525 if (ret)
1526 return ret;
1527 }
1528
1529 vlanmc->vid = data[0] & RTL8366RB_VLAN_VID_MASK;
1530 vlanmc->priority = (data[0] >> RTL8366RB_VLAN_PRIORITY_SHIFT) &
1531 RTL8366RB_VLAN_PRIORITY_MASK;
1532 vlanmc->untag = (data[1] >> RTL8366RB_VLAN_UNTAG_SHIFT) &
1533 RTL8366RB_VLAN_UNTAG_MASK;
1534 vlanmc->member = data[1] & RTL8366RB_VLAN_MEMBER_MASK;
1535 vlanmc->fid = data[2] & RTL8366RB_VLAN_FID_MASK;
1536
1537 return 0;
1538 }
1539
rtl8366rb_set_vlan_mc(struct realtek_priv * priv,u32 index,const struct rtl8366_vlan_mc * vlanmc)1540 static int rtl8366rb_set_vlan_mc(struct realtek_priv *priv, u32 index,
1541 const struct rtl8366_vlan_mc *vlanmc)
1542 {
1543 u32 data[3];
1544 int ret;
1545 int i;
1546
1547 if (index >= RTL8366RB_NUM_VLANS ||
1548 vlanmc->vid >= RTL8366RB_NUM_VIDS ||
1549 vlanmc->priority > RTL8366RB_PRIORITYMAX ||
1550 vlanmc->member > RTL8366RB_VLAN_MEMBER_MASK ||
1551 vlanmc->untag > RTL8366RB_VLAN_UNTAG_MASK ||
1552 vlanmc->fid > RTL8366RB_FIDMAX)
1553 return -EINVAL;
1554
1555 data[0] = (vlanmc->vid & RTL8366RB_VLAN_VID_MASK) |
1556 ((vlanmc->priority & RTL8366RB_VLAN_PRIORITY_MASK) <<
1557 RTL8366RB_VLAN_PRIORITY_SHIFT);
1558 data[1] = (vlanmc->member & RTL8366RB_VLAN_MEMBER_MASK) |
1559 ((vlanmc->untag & RTL8366RB_VLAN_UNTAG_MASK) <<
1560 RTL8366RB_VLAN_UNTAG_SHIFT);
1561 data[2] = vlanmc->fid & RTL8366RB_VLAN_FID_MASK;
1562
1563 for (i = 0; i < 3; i++) {
1564 ret = regmap_write(priv->map,
1565 RTL8366RB_VLAN_MC_BASE(index) + i,
1566 data[i]);
1567 if (ret)
1568 return ret;
1569 }
1570
1571 return 0;
1572 }
1573
rtl8366rb_get_mc_index(struct realtek_priv * priv,int port,int * val)1574 static int rtl8366rb_get_mc_index(struct realtek_priv *priv, int port, int *val)
1575 {
1576 u32 data;
1577 int ret;
1578
1579 if (port >= priv->num_ports)
1580 return -EINVAL;
1581
1582 ret = regmap_read(priv->map, RTL8366RB_PORT_VLAN_CTRL_REG(port),
1583 &data);
1584 if (ret)
1585 return ret;
1586
1587 *val = (data >> RTL8366RB_PORT_VLAN_CTRL_SHIFT(port)) &
1588 RTL8366RB_PORT_VLAN_CTRL_MASK;
1589
1590 return 0;
1591 }
1592
rtl8366rb_set_mc_index(struct realtek_priv * priv,int port,int index)1593 static int rtl8366rb_set_mc_index(struct realtek_priv *priv, int port, int index)
1594 {
1595 struct dsa_switch *ds = &priv->ds;
1596 struct rtl8366rb *rb;
1597 bool pvid_enabled;
1598 int ret;
1599
1600 rb = priv->chip_data;
1601 pvid_enabled = !!index;
1602
1603 if (port >= priv->num_ports || index >= RTL8366RB_NUM_VLANS)
1604 return -EINVAL;
1605
1606 ret = regmap_update_bits(priv->map, RTL8366RB_PORT_VLAN_CTRL_REG(port),
1607 RTL8366RB_PORT_VLAN_CTRL_MASK <<
1608 RTL8366RB_PORT_VLAN_CTRL_SHIFT(port),
1609 (index & RTL8366RB_PORT_VLAN_CTRL_MASK) <<
1610 RTL8366RB_PORT_VLAN_CTRL_SHIFT(port));
1611 if (ret)
1612 return ret;
1613
1614 rb->pvid_enabled[port] = pvid_enabled;
1615
1616 /* If VLAN filtering is enabled and PVID is also enabled, we must
1617 * not drop any untagged or C-tagged frames. Make sure to update the
1618 * filtering setting.
1619 */
1620 if (dsa_port_is_vlan_filtering(dsa_to_port(ds, port)))
1621 ret = rtl8366rb_drop_untagged(priv, port, !pvid_enabled);
1622
1623 return ret;
1624 }
1625
rtl8366rb_is_vlan_valid(struct realtek_priv * priv,unsigned int vlan)1626 static bool rtl8366rb_is_vlan_valid(struct realtek_priv *priv, unsigned int vlan)
1627 {
1628 unsigned int max = RTL8366RB_NUM_VLANS - 1;
1629
1630 if (priv->vlan4k_enabled)
1631 max = RTL8366RB_NUM_VIDS - 1;
1632
1633 if (vlan > max)
1634 return false;
1635
1636 return true;
1637 }
1638
rtl8366rb_enable_vlan(struct realtek_priv * priv,bool enable)1639 static int rtl8366rb_enable_vlan(struct realtek_priv *priv, bool enable)
1640 {
1641 dev_dbg(priv->dev, "%s VLAN\n", enable ? "enable" : "disable");
1642 return regmap_update_bits(priv->map,
1643 RTL8366RB_SGCR, RTL8366RB_SGCR_EN_VLAN,
1644 enable ? RTL8366RB_SGCR_EN_VLAN : 0);
1645 }
1646
rtl8366rb_enable_vlan4k(struct realtek_priv * priv,bool enable)1647 static int rtl8366rb_enable_vlan4k(struct realtek_priv *priv, bool enable)
1648 {
1649 dev_dbg(priv->dev, "%s VLAN 4k\n", enable ? "enable" : "disable");
1650 return regmap_update_bits(priv->map, RTL8366RB_SGCR,
1651 RTL8366RB_SGCR_EN_VLAN_4KTB,
1652 enable ? RTL8366RB_SGCR_EN_VLAN_4KTB : 0);
1653 }
1654
rtl8366rb_phy_read(struct realtek_priv * priv,int phy,int regnum)1655 static int rtl8366rb_phy_read(struct realtek_priv *priv, int phy, int regnum)
1656 {
1657 u32 val;
1658 u32 reg;
1659 int ret;
1660
1661 if (phy > RTL8366RB_PHY_NO_MAX)
1662 return -EINVAL;
1663
1664 rtl83xx_lock(priv);
1665
1666 ret = regmap_write(priv->map_nolock, RTL8366RB_PHY_ACCESS_CTRL_REG,
1667 RTL8366RB_PHY_CTRL_READ);
1668 if (ret)
1669 goto out;
1670
1671 reg = 0x8000 | (1 << (phy + RTL8366RB_PHY_NO_OFFSET)) | regnum;
1672
1673 ret = regmap_write(priv->map_nolock, reg, 0);
1674 if (ret) {
1675 dev_err(priv->dev,
1676 "failed to write PHY%d reg %04x @ %04x, ret %d\n",
1677 phy, regnum, reg, ret);
1678 goto out;
1679 }
1680
1681 ret = regmap_read(priv->map_nolock, RTL8366RB_PHY_ACCESS_DATA_REG,
1682 &val);
1683 if (ret)
1684 goto out;
1685
1686 ret = val;
1687
1688 dev_dbg(priv->dev, "read PHY%d register 0x%04x @ %08x, val <- %04x\n",
1689 phy, regnum, reg, val);
1690
1691 out:
1692 rtl83xx_unlock(priv);
1693
1694 return ret;
1695 }
1696
rtl8366rb_phy_write(struct realtek_priv * priv,int phy,int regnum,u16 val)1697 static int rtl8366rb_phy_write(struct realtek_priv *priv, int phy, int regnum,
1698 u16 val)
1699 {
1700 u32 reg;
1701 int ret;
1702
1703 if (phy > RTL8366RB_PHY_NO_MAX)
1704 return -EINVAL;
1705
1706 rtl83xx_lock(priv);
1707
1708 ret = regmap_write(priv->map_nolock, RTL8366RB_PHY_ACCESS_CTRL_REG,
1709 RTL8366RB_PHY_CTRL_WRITE);
1710 if (ret)
1711 goto out;
1712
1713 reg = 0x8000 | (1 << (phy + RTL8366RB_PHY_NO_OFFSET)) | regnum;
1714
1715 dev_dbg(priv->dev, "write PHY%d register 0x%04x @ %04x, val -> %04x\n",
1716 phy, regnum, reg, val);
1717
1718 ret = regmap_write(priv->map_nolock, reg, val);
1719 if (ret)
1720 goto out;
1721
1722 out:
1723 rtl83xx_unlock(priv);
1724
1725 return ret;
1726 }
1727
rtl8366rb_reset_chip(struct realtek_priv * priv)1728 static int rtl8366rb_reset_chip(struct realtek_priv *priv)
1729 {
1730 int timeout = 10;
1731 u32 val;
1732 int ret;
1733
1734 priv->write_reg_noack(priv, RTL8366RB_RESET_CTRL_REG,
1735 RTL8366RB_CHIP_CTRL_RESET_HW);
1736 do {
1737 usleep_range(20000, 25000);
1738 ret = regmap_read(priv->map, RTL8366RB_RESET_CTRL_REG, &val);
1739 if (ret)
1740 return ret;
1741
1742 if (!(val & RTL8366RB_CHIP_CTRL_RESET_HW))
1743 break;
1744 } while (--timeout);
1745
1746 if (!timeout) {
1747 dev_err(priv->dev, "timeout waiting for the switch to reset\n");
1748 return -EIO;
1749 }
1750
1751 return 0;
1752 }
1753
rtl8366rb_detect(struct realtek_priv * priv)1754 static int rtl8366rb_detect(struct realtek_priv *priv)
1755 {
1756 struct device *dev = priv->dev;
1757 int ret;
1758 u32 val;
1759
1760 /* Detect device */
1761 ret = regmap_read(priv->map, 0x5c, &val);
1762 if (ret) {
1763 dev_err(dev, "can't get chip ID (%d)\n", ret);
1764 return ret;
1765 }
1766
1767 switch (val) {
1768 case 0x6027:
1769 dev_info(dev, "found an RTL8366S switch\n");
1770 dev_err(dev, "this switch is not yet supported, submit patches!\n");
1771 return -ENODEV;
1772 case 0x5937:
1773 dev_info(dev, "found an RTL8366RB switch\n");
1774 priv->cpu_port = RTL8366RB_PORT_NUM_CPU;
1775 priv->num_ports = RTL8366RB_NUM_PORTS;
1776 priv->num_vlan_mc = RTL8366RB_NUM_VLANS;
1777 priv->mib_counters = rtl8366rb_mib_counters;
1778 priv->num_mib_counters = ARRAY_SIZE(rtl8366rb_mib_counters);
1779 break;
1780 default:
1781 dev_info(dev, "found an Unknown Realtek switch (id=0x%04x)\n",
1782 val);
1783 break;
1784 }
1785
1786 ret = rtl8366rb_reset_chip(priv);
1787 if (ret)
1788 return ret;
1789
1790 return 0;
1791 }
1792
1793 static const struct phylink_mac_ops rtl8366rb_phylink_mac_ops = {
1794 .mac_config = rtl8366rb_mac_config,
1795 .mac_link_down = rtl8366rb_mac_link_down,
1796 .mac_link_up = rtl8366rb_mac_link_up,
1797 };
1798
1799 static const struct dsa_switch_ops rtl8366rb_switch_ops = {
1800 .get_tag_protocol = rtl8366_get_tag_protocol,
1801 .setup = rtl8366rb_setup,
1802 .phylink_get_caps = rtl8366rb_phylink_get_caps,
1803 .get_strings = rtl8366_get_strings,
1804 .get_ethtool_stats = rtl8366_get_ethtool_stats,
1805 .get_sset_count = rtl8366_get_sset_count,
1806 .port_bridge_join = rtl8366rb_port_bridge_join,
1807 .port_bridge_leave = rtl8366rb_port_bridge_leave,
1808 .port_vlan_filtering = rtl8366rb_vlan_filtering,
1809 .port_vlan_add = rtl8366_vlan_add,
1810 .port_vlan_del = rtl8366_vlan_del,
1811 .port_enable = rtl8366rb_port_enable,
1812 .port_disable = rtl8366rb_port_disable,
1813 .port_pre_bridge_flags = rtl8366rb_port_pre_bridge_flags,
1814 .port_bridge_flags = rtl8366rb_port_bridge_flags,
1815 .port_stp_state_set = rtl8366rb_port_stp_state_set,
1816 .port_fast_age = rtl8366rb_port_fast_age,
1817 .port_change_mtu = rtl8366rb_change_mtu,
1818 .port_max_mtu = rtl8366rb_max_mtu,
1819 };
1820
1821 static const struct realtek_ops rtl8366rb_ops = {
1822 .detect = rtl8366rb_detect,
1823 .get_vlan_mc = rtl8366rb_get_vlan_mc,
1824 .set_vlan_mc = rtl8366rb_set_vlan_mc,
1825 .get_vlan_4k = rtl8366rb_get_vlan_4k,
1826 .set_vlan_4k = rtl8366rb_set_vlan_4k,
1827 .get_mc_index = rtl8366rb_get_mc_index,
1828 .set_mc_index = rtl8366rb_set_mc_index,
1829 .get_mib_counter = rtl8366rb_get_mib_counter,
1830 .is_vlan_valid = rtl8366rb_is_vlan_valid,
1831 .enable_vlan = rtl8366rb_enable_vlan,
1832 .enable_vlan4k = rtl8366rb_enable_vlan4k,
1833 .phy_read = rtl8366rb_phy_read,
1834 .phy_write = rtl8366rb_phy_write,
1835 };
1836
1837 const struct realtek_variant rtl8366rb_variant = {
1838 .ds_ops = &rtl8366rb_switch_ops,
1839 .ops = &rtl8366rb_ops,
1840 .phylink_mac_ops = &rtl8366rb_phylink_mac_ops,
1841 .clk_delay = 10,
1842 .cmd_read = 0xa9,
1843 .cmd_write = 0xa8,
1844 .chip_data_sz = sizeof(struct rtl8366rb),
1845 };
1846
1847 static const struct of_device_id rtl8366rb_of_match[] = {
1848 { .compatible = "realtek,rtl8366rb", .data = &rtl8366rb_variant, },
1849 { /* sentinel */ },
1850 };
1851 MODULE_DEVICE_TABLE(of, rtl8366rb_of_match);
1852
1853 static struct platform_driver rtl8366rb_smi_driver = {
1854 .driver = {
1855 .name = "rtl8366rb-smi",
1856 .of_match_table = rtl8366rb_of_match,
1857 },
1858 .probe = realtek_smi_probe,
1859 .remove_new = realtek_smi_remove,
1860 .shutdown = realtek_smi_shutdown,
1861 };
1862
1863 static struct mdio_driver rtl8366rb_mdio_driver = {
1864 .mdiodrv.driver = {
1865 .name = "rtl8366rb-mdio",
1866 .of_match_table = rtl8366rb_of_match,
1867 },
1868 .probe = realtek_mdio_probe,
1869 .remove = realtek_mdio_remove,
1870 .shutdown = realtek_mdio_shutdown,
1871 };
1872
rtl8366rb_init(void)1873 static int rtl8366rb_init(void)
1874 {
1875 int ret;
1876
1877 ret = realtek_mdio_driver_register(&rtl8366rb_mdio_driver);
1878 if (ret)
1879 return ret;
1880
1881 ret = realtek_smi_driver_register(&rtl8366rb_smi_driver);
1882 if (ret) {
1883 realtek_mdio_driver_unregister(&rtl8366rb_mdio_driver);
1884 return ret;
1885 }
1886
1887 return 0;
1888 }
1889 module_init(rtl8366rb_init);
1890
rtl8366rb_exit(void)1891 static void __exit rtl8366rb_exit(void)
1892 {
1893 realtek_smi_driver_unregister(&rtl8366rb_smi_driver);
1894 realtek_mdio_driver_unregister(&rtl8366rb_mdio_driver);
1895 }
1896 module_exit(rtl8366rb_exit);
1897
1898 MODULE_AUTHOR("Linus Walleij <linus.walleij@linaro.org>");
1899 MODULE_DESCRIPTION("Driver for RTL8366RB ethernet switch");
1900 MODULE_LICENSE("GPL");
1901 MODULE_IMPORT_NS(REALTEK_DSA);
1902