1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright (c) 2018-2023, Intel Corporation. */
3
4 #include "ice_common.h"
5 #include "ice_sched.h"
6 #include "ice_adminq_cmd.h"
7 #include "ice_flow.h"
8 #include "ice_ptp_hw.h"
9
10 #define ICE_PF_RESET_WAIT_COUNT 300
11 #define ICE_MAX_NETLIST_SIZE 10
12
13 static const char * const ice_link_mode_str_low[] = {
14 [0] = "100BASE_TX",
15 [1] = "100M_SGMII",
16 [2] = "1000BASE_T",
17 [3] = "1000BASE_SX",
18 [4] = "1000BASE_LX",
19 [5] = "1000BASE_KX",
20 [6] = "1G_SGMII",
21 [7] = "2500BASE_T",
22 [8] = "2500BASE_X",
23 [9] = "2500BASE_KX",
24 [10] = "5GBASE_T",
25 [11] = "5GBASE_KR",
26 [12] = "10GBASE_T",
27 [13] = "10G_SFI_DA",
28 [14] = "10GBASE_SR",
29 [15] = "10GBASE_LR",
30 [16] = "10GBASE_KR_CR1",
31 [17] = "10G_SFI_AOC_ACC",
32 [18] = "10G_SFI_C2C",
33 [19] = "25GBASE_T",
34 [20] = "25GBASE_CR",
35 [21] = "25GBASE_CR_S",
36 [22] = "25GBASE_CR1",
37 [23] = "25GBASE_SR",
38 [24] = "25GBASE_LR",
39 [25] = "25GBASE_KR",
40 [26] = "25GBASE_KR_S",
41 [27] = "25GBASE_KR1",
42 [28] = "25G_AUI_AOC_ACC",
43 [29] = "25G_AUI_C2C",
44 [30] = "40GBASE_CR4",
45 [31] = "40GBASE_SR4",
46 [32] = "40GBASE_LR4",
47 [33] = "40GBASE_KR4",
48 [34] = "40G_XLAUI_AOC_ACC",
49 [35] = "40G_XLAUI",
50 [36] = "50GBASE_CR2",
51 [37] = "50GBASE_SR2",
52 [38] = "50GBASE_LR2",
53 [39] = "50GBASE_KR2",
54 [40] = "50G_LAUI2_AOC_ACC",
55 [41] = "50G_LAUI2",
56 [42] = "50G_AUI2_AOC_ACC",
57 [43] = "50G_AUI2",
58 [44] = "50GBASE_CP",
59 [45] = "50GBASE_SR",
60 [46] = "50GBASE_FR",
61 [47] = "50GBASE_LR",
62 [48] = "50GBASE_KR_PAM4",
63 [49] = "50G_AUI1_AOC_ACC",
64 [50] = "50G_AUI1",
65 [51] = "100GBASE_CR4",
66 [52] = "100GBASE_SR4",
67 [53] = "100GBASE_LR4",
68 [54] = "100GBASE_KR4",
69 [55] = "100G_CAUI4_AOC_ACC",
70 [56] = "100G_CAUI4",
71 [57] = "100G_AUI4_AOC_ACC",
72 [58] = "100G_AUI4",
73 [59] = "100GBASE_CR_PAM4",
74 [60] = "100GBASE_KR_PAM4",
75 [61] = "100GBASE_CP2",
76 [62] = "100GBASE_SR2",
77 [63] = "100GBASE_DR",
78 };
79
80 static const char * const ice_link_mode_str_high[] = {
81 [0] = "100GBASE_KR2_PAM4",
82 [1] = "100G_CAUI2_AOC_ACC",
83 [2] = "100G_CAUI2",
84 [3] = "100G_AUI2_AOC_ACC",
85 [4] = "100G_AUI2",
86 };
87
88 /**
89 * ice_dump_phy_type - helper function to dump phy_type
90 * @hw: pointer to the HW structure
91 * @low: 64 bit value for phy_type_low
92 * @high: 64 bit value for phy_type_high
93 * @prefix: prefix string to differentiate multiple dumps
94 */
95 static void
ice_dump_phy_type(struct ice_hw * hw,u64 low,u64 high,const char * prefix)96 ice_dump_phy_type(struct ice_hw *hw, u64 low, u64 high, const char *prefix)
97 {
98 ice_debug(hw, ICE_DBG_PHY, "%s: phy_type_low: 0x%016llx\n", prefix, low);
99
100 for (u32 i = 0; i < BITS_PER_TYPE(typeof(low)); i++) {
101 if (low & BIT_ULL(i))
102 ice_debug(hw, ICE_DBG_PHY, "%s: bit(%d): %s\n",
103 prefix, i, ice_link_mode_str_low[i]);
104 }
105
106 ice_debug(hw, ICE_DBG_PHY, "%s: phy_type_high: 0x%016llx\n", prefix, high);
107
108 for (u32 i = 0; i < BITS_PER_TYPE(typeof(high)); i++) {
109 if (high & BIT_ULL(i))
110 ice_debug(hw, ICE_DBG_PHY, "%s: bit(%d): %s\n",
111 prefix, i, ice_link_mode_str_high[i]);
112 }
113 }
114
115 /**
116 * ice_set_mac_type - Sets MAC type
117 * @hw: pointer to the HW structure
118 *
119 * This function sets the MAC type of the adapter based on the
120 * vendor ID and device ID stored in the HW structure.
121 */
ice_set_mac_type(struct ice_hw * hw)122 static int ice_set_mac_type(struct ice_hw *hw)
123 {
124 if (hw->vendor_id != PCI_VENDOR_ID_INTEL)
125 return -ENODEV;
126
127 switch (hw->device_id) {
128 case ICE_DEV_ID_E810C_BACKPLANE:
129 case ICE_DEV_ID_E810C_QSFP:
130 case ICE_DEV_ID_E810C_SFP:
131 case ICE_DEV_ID_E810_XXV_BACKPLANE:
132 case ICE_DEV_ID_E810_XXV_QSFP:
133 case ICE_DEV_ID_E810_XXV_SFP:
134 hw->mac_type = ICE_MAC_E810;
135 break;
136 case ICE_DEV_ID_E823C_10G_BASE_T:
137 case ICE_DEV_ID_E823C_BACKPLANE:
138 case ICE_DEV_ID_E823C_QSFP:
139 case ICE_DEV_ID_E823C_SFP:
140 case ICE_DEV_ID_E823C_SGMII:
141 case ICE_DEV_ID_E822C_10G_BASE_T:
142 case ICE_DEV_ID_E822C_BACKPLANE:
143 case ICE_DEV_ID_E822C_QSFP:
144 case ICE_DEV_ID_E822C_SFP:
145 case ICE_DEV_ID_E822C_SGMII:
146 case ICE_DEV_ID_E822L_10G_BASE_T:
147 case ICE_DEV_ID_E822L_BACKPLANE:
148 case ICE_DEV_ID_E822L_SFP:
149 case ICE_DEV_ID_E822L_SGMII:
150 case ICE_DEV_ID_E823L_10G_BASE_T:
151 case ICE_DEV_ID_E823L_1GBE:
152 case ICE_DEV_ID_E823L_BACKPLANE:
153 case ICE_DEV_ID_E823L_QSFP:
154 case ICE_DEV_ID_E823L_SFP:
155 hw->mac_type = ICE_MAC_GENERIC;
156 break;
157 case ICE_DEV_ID_E825C_BACKPLANE:
158 case ICE_DEV_ID_E825C_QSFP:
159 case ICE_DEV_ID_E825C_SFP:
160 case ICE_DEV_ID_E825C_SGMII:
161 hw->mac_type = ICE_MAC_GENERIC_3K_E825;
162 break;
163 case ICE_DEV_ID_E830CC_BACKPLANE:
164 case ICE_DEV_ID_E830CC_QSFP56:
165 case ICE_DEV_ID_E830CC_SFP:
166 case ICE_DEV_ID_E830CC_SFP_DD:
167 case ICE_DEV_ID_E830C_BACKPLANE:
168 case ICE_DEV_ID_E830_XXV_BACKPLANE:
169 case ICE_DEV_ID_E830C_QSFP:
170 case ICE_DEV_ID_E830_XXV_QSFP:
171 case ICE_DEV_ID_E830C_SFP:
172 case ICE_DEV_ID_E830_XXV_SFP:
173 hw->mac_type = ICE_MAC_E830;
174 break;
175 default:
176 hw->mac_type = ICE_MAC_UNKNOWN;
177 break;
178 }
179
180 ice_debug(hw, ICE_DBG_INIT, "mac_type: %d\n", hw->mac_type);
181 return 0;
182 }
183
184 /**
185 * ice_is_generic_mac - check if device's mac_type is generic
186 * @hw: pointer to the hardware structure
187 *
188 * Return: true if mac_type is generic (with SBQ support), false if not
189 */
ice_is_generic_mac(struct ice_hw * hw)190 bool ice_is_generic_mac(struct ice_hw *hw)
191 {
192 return (hw->mac_type == ICE_MAC_GENERIC ||
193 hw->mac_type == ICE_MAC_GENERIC_3K_E825);
194 }
195
196 /**
197 * ice_is_e810
198 * @hw: pointer to the hardware structure
199 *
200 * returns true if the device is E810 based, false if not.
201 */
ice_is_e810(struct ice_hw * hw)202 bool ice_is_e810(struct ice_hw *hw)
203 {
204 return hw->mac_type == ICE_MAC_E810;
205 }
206
207 /**
208 * ice_is_e810t
209 * @hw: pointer to the hardware structure
210 *
211 * returns true if the device is E810T based, false if not.
212 */
ice_is_e810t(struct ice_hw * hw)213 bool ice_is_e810t(struct ice_hw *hw)
214 {
215 switch (hw->device_id) {
216 case ICE_DEV_ID_E810C_SFP:
217 switch (hw->subsystem_device_id) {
218 case ICE_SUBDEV_ID_E810T:
219 case ICE_SUBDEV_ID_E810T2:
220 case ICE_SUBDEV_ID_E810T3:
221 case ICE_SUBDEV_ID_E810T4:
222 case ICE_SUBDEV_ID_E810T6:
223 case ICE_SUBDEV_ID_E810T7:
224 return true;
225 }
226 break;
227 case ICE_DEV_ID_E810C_QSFP:
228 switch (hw->subsystem_device_id) {
229 case ICE_SUBDEV_ID_E810T2:
230 case ICE_SUBDEV_ID_E810T3:
231 case ICE_SUBDEV_ID_E810T5:
232 return true;
233 }
234 break;
235 default:
236 break;
237 }
238
239 return false;
240 }
241
242 /**
243 * ice_is_e822 - Check if a device is E822 family device
244 * @hw: pointer to the hardware structure
245 *
246 * Return: true if the device is E822 based, false if not.
247 */
ice_is_e822(struct ice_hw * hw)248 bool ice_is_e822(struct ice_hw *hw)
249 {
250 switch (hw->device_id) {
251 case ICE_DEV_ID_E822C_BACKPLANE:
252 case ICE_DEV_ID_E822C_QSFP:
253 case ICE_DEV_ID_E822C_SFP:
254 case ICE_DEV_ID_E822C_10G_BASE_T:
255 case ICE_DEV_ID_E822C_SGMII:
256 case ICE_DEV_ID_E822L_BACKPLANE:
257 case ICE_DEV_ID_E822L_SFP:
258 case ICE_DEV_ID_E822L_10G_BASE_T:
259 case ICE_DEV_ID_E822L_SGMII:
260 return true;
261 default:
262 return false;
263 }
264 }
265
266 /**
267 * ice_is_e823
268 * @hw: pointer to the hardware structure
269 *
270 * returns true if the device is E823-L or E823-C based, false if not.
271 */
ice_is_e823(struct ice_hw * hw)272 bool ice_is_e823(struct ice_hw *hw)
273 {
274 switch (hw->device_id) {
275 case ICE_DEV_ID_E823L_BACKPLANE:
276 case ICE_DEV_ID_E823L_SFP:
277 case ICE_DEV_ID_E823L_10G_BASE_T:
278 case ICE_DEV_ID_E823L_1GBE:
279 case ICE_DEV_ID_E823L_QSFP:
280 case ICE_DEV_ID_E823C_BACKPLANE:
281 case ICE_DEV_ID_E823C_QSFP:
282 case ICE_DEV_ID_E823C_SFP:
283 case ICE_DEV_ID_E823C_10G_BASE_T:
284 case ICE_DEV_ID_E823C_SGMII:
285 return true;
286 default:
287 return false;
288 }
289 }
290
291 /**
292 * ice_is_e825c - Check if a device is E825C family device
293 * @hw: pointer to the hardware structure
294 *
295 * Return: true if the device is E825-C based, false if not.
296 */
ice_is_e825c(struct ice_hw * hw)297 bool ice_is_e825c(struct ice_hw *hw)
298 {
299 switch (hw->device_id) {
300 case ICE_DEV_ID_E825C_BACKPLANE:
301 case ICE_DEV_ID_E825C_QSFP:
302 case ICE_DEV_ID_E825C_SFP:
303 case ICE_DEV_ID_E825C_SGMII:
304 return true;
305 default:
306 return false;
307 }
308 }
309
310 /**
311 * ice_clear_pf_cfg - Clear PF configuration
312 * @hw: pointer to the hardware structure
313 *
314 * Clears any existing PF configuration (VSIs, VSI lists, switch rules, port
315 * configuration, flow director filters, etc.).
316 */
ice_clear_pf_cfg(struct ice_hw * hw)317 int ice_clear_pf_cfg(struct ice_hw *hw)
318 {
319 struct ice_aq_desc desc;
320
321 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_clear_pf_cfg);
322
323 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL);
324 }
325
326 /**
327 * ice_aq_manage_mac_read - manage MAC address read command
328 * @hw: pointer to the HW struct
329 * @buf: a virtual buffer to hold the manage MAC read response
330 * @buf_size: Size of the virtual buffer
331 * @cd: pointer to command details structure or NULL
332 *
333 * This function is used to return per PF station MAC address (0x0107).
334 * NOTE: Upon successful completion of this command, MAC address information
335 * is returned in user specified buffer. Please interpret user specified
336 * buffer as "manage_mac_read" response.
337 * Response such as various MAC addresses are stored in HW struct (port.mac)
338 * ice_discover_dev_caps is expected to be called before this function is
339 * called.
340 */
341 static int
ice_aq_manage_mac_read(struct ice_hw * hw,void * buf,u16 buf_size,struct ice_sq_cd * cd)342 ice_aq_manage_mac_read(struct ice_hw *hw, void *buf, u16 buf_size,
343 struct ice_sq_cd *cd)
344 {
345 struct ice_aqc_manage_mac_read_resp *resp;
346 struct ice_aqc_manage_mac_read *cmd;
347 struct ice_aq_desc desc;
348 int status;
349 u16 flags;
350 u8 i;
351
352 cmd = &desc.params.mac_read;
353
354 if (buf_size < sizeof(*resp))
355 return -EINVAL;
356
357 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_manage_mac_read);
358
359 status = ice_aq_send_cmd(hw, &desc, buf, buf_size, cd);
360 if (status)
361 return status;
362
363 resp = buf;
364 flags = le16_to_cpu(cmd->flags) & ICE_AQC_MAN_MAC_READ_M;
365
366 if (!(flags & ICE_AQC_MAN_MAC_LAN_ADDR_VALID)) {
367 ice_debug(hw, ICE_DBG_LAN, "got invalid MAC address\n");
368 return -EIO;
369 }
370
371 /* A single port can report up to two (LAN and WoL) addresses */
372 for (i = 0; i < cmd->num_addr; i++)
373 if (resp[i].addr_type == ICE_AQC_MAN_MAC_ADDR_TYPE_LAN) {
374 ether_addr_copy(hw->port_info->mac.lan_addr,
375 resp[i].mac_addr);
376 ether_addr_copy(hw->port_info->mac.perm_addr,
377 resp[i].mac_addr);
378 break;
379 }
380
381 return 0;
382 }
383
384 /**
385 * ice_aq_get_phy_caps - returns PHY capabilities
386 * @pi: port information structure
387 * @qual_mods: report qualified modules
388 * @report_mode: report mode capabilities
389 * @pcaps: structure for PHY capabilities to be filled
390 * @cd: pointer to command details structure or NULL
391 *
392 * Returns the various PHY capabilities supported on the Port (0x0600)
393 */
394 int
ice_aq_get_phy_caps(struct ice_port_info * pi,bool qual_mods,u8 report_mode,struct ice_aqc_get_phy_caps_data * pcaps,struct ice_sq_cd * cd)395 ice_aq_get_phy_caps(struct ice_port_info *pi, bool qual_mods, u8 report_mode,
396 struct ice_aqc_get_phy_caps_data *pcaps,
397 struct ice_sq_cd *cd)
398 {
399 struct ice_aqc_get_phy_caps *cmd;
400 u16 pcaps_size = sizeof(*pcaps);
401 struct ice_aq_desc desc;
402 const char *prefix;
403 struct ice_hw *hw;
404 int status;
405
406 cmd = &desc.params.get_phy;
407
408 if (!pcaps || (report_mode & ~ICE_AQC_REPORT_MODE_M) || !pi)
409 return -EINVAL;
410 hw = pi->hw;
411
412 if (report_mode == ICE_AQC_REPORT_DFLT_CFG &&
413 !ice_fw_supports_report_dflt_cfg(hw))
414 return -EINVAL;
415
416 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_phy_caps);
417
418 if (qual_mods)
419 cmd->param0 |= cpu_to_le16(ICE_AQC_GET_PHY_RQM);
420
421 cmd->param0 |= cpu_to_le16(report_mode);
422 status = ice_aq_send_cmd(hw, &desc, pcaps, pcaps_size, cd);
423
424 ice_debug(hw, ICE_DBG_LINK, "get phy caps dump\n");
425
426 switch (report_mode) {
427 case ICE_AQC_REPORT_TOPO_CAP_MEDIA:
428 prefix = "phy_caps_media";
429 break;
430 case ICE_AQC_REPORT_TOPO_CAP_NO_MEDIA:
431 prefix = "phy_caps_no_media";
432 break;
433 case ICE_AQC_REPORT_ACTIVE_CFG:
434 prefix = "phy_caps_active";
435 break;
436 case ICE_AQC_REPORT_DFLT_CFG:
437 prefix = "phy_caps_default";
438 break;
439 default:
440 prefix = "phy_caps_invalid";
441 }
442
443 ice_dump_phy_type(hw, le64_to_cpu(pcaps->phy_type_low),
444 le64_to_cpu(pcaps->phy_type_high), prefix);
445
446 ice_debug(hw, ICE_DBG_LINK, "%s: report_mode = 0x%x\n",
447 prefix, report_mode);
448 ice_debug(hw, ICE_DBG_LINK, "%s: caps = 0x%x\n", prefix, pcaps->caps);
449 ice_debug(hw, ICE_DBG_LINK, "%s: low_power_ctrl_an = 0x%x\n", prefix,
450 pcaps->low_power_ctrl_an);
451 ice_debug(hw, ICE_DBG_LINK, "%s: eee_cap = 0x%x\n", prefix,
452 pcaps->eee_cap);
453 ice_debug(hw, ICE_DBG_LINK, "%s: eeer_value = 0x%x\n", prefix,
454 pcaps->eeer_value);
455 ice_debug(hw, ICE_DBG_LINK, "%s: link_fec_options = 0x%x\n", prefix,
456 pcaps->link_fec_options);
457 ice_debug(hw, ICE_DBG_LINK, "%s: module_compliance_enforcement = 0x%x\n",
458 prefix, pcaps->module_compliance_enforcement);
459 ice_debug(hw, ICE_DBG_LINK, "%s: extended_compliance_code = 0x%x\n",
460 prefix, pcaps->extended_compliance_code);
461 ice_debug(hw, ICE_DBG_LINK, "%s: module_type[0] = 0x%x\n", prefix,
462 pcaps->module_type[0]);
463 ice_debug(hw, ICE_DBG_LINK, "%s: module_type[1] = 0x%x\n", prefix,
464 pcaps->module_type[1]);
465 ice_debug(hw, ICE_DBG_LINK, "%s: module_type[2] = 0x%x\n", prefix,
466 pcaps->module_type[2]);
467
468 if (!status && report_mode == ICE_AQC_REPORT_TOPO_CAP_MEDIA) {
469 pi->phy.phy_type_low = le64_to_cpu(pcaps->phy_type_low);
470 pi->phy.phy_type_high = le64_to_cpu(pcaps->phy_type_high);
471 memcpy(pi->phy.link_info.module_type, &pcaps->module_type,
472 sizeof(pi->phy.link_info.module_type));
473 }
474
475 return status;
476 }
477
478 /**
479 * ice_aq_get_link_topo_handle - get link topology node return status
480 * @pi: port information structure
481 * @node_type: requested node type
482 * @cd: pointer to command details structure or NULL
483 *
484 * Get link topology node return status for specified node type (0x06E0)
485 *
486 * Node type cage can be used to determine if cage is present. If AQC
487 * returns error (ENOENT), then no cage present. If no cage present, then
488 * connection type is backplane or BASE-T.
489 */
490 static int
ice_aq_get_link_topo_handle(struct ice_port_info * pi,u8 node_type,struct ice_sq_cd * cd)491 ice_aq_get_link_topo_handle(struct ice_port_info *pi, u8 node_type,
492 struct ice_sq_cd *cd)
493 {
494 struct ice_aqc_get_link_topo *cmd;
495 struct ice_aq_desc desc;
496
497 cmd = &desc.params.get_link_topo;
498
499 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_link_topo);
500
501 cmd->addr.topo_params.node_type_ctx =
502 (ICE_AQC_LINK_TOPO_NODE_CTX_PORT <<
503 ICE_AQC_LINK_TOPO_NODE_CTX_S);
504
505 /* set node type */
506 cmd->addr.topo_params.node_type_ctx |=
507 (ICE_AQC_LINK_TOPO_NODE_TYPE_M & node_type);
508
509 return ice_aq_send_cmd(pi->hw, &desc, NULL, 0, cd);
510 }
511
512 /**
513 * ice_aq_get_netlist_node
514 * @hw: pointer to the hw struct
515 * @cmd: get_link_topo AQ structure
516 * @node_part_number: output node part number if node found
517 * @node_handle: output node handle parameter if node found
518 *
519 * Get netlist node handle.
520 */
521 int
ice_aq_get_netlist_node(struct ice_hw * hw,struct ice_aqc_get_link_topo * cmd,u8 * node_part_number,u16 * node_handle)522 ice_aq_get_netlist_node(struct ice_hw *hw, struct ice_aqc_get_link_topo *cmd,
523 u8 *node_part_number, u16 *node_handle)
524 {
525 struct ice_aq_desc desc;
526
527 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_link_topo);
528 desc.params.get_link_topo = *cmd;
529
530 if (ice_aq_send_cmd(hw, &desc, NULL, 0, NULL))
531 return -EINTR;
532
533 if (node_handle)
534 *node_handle =
535 le16_to_cpu(desc.params.get_link_topo.addr.handle);
536 if (node_part_number)
537 *node_part_number = desc.params.get_link_topo.node_part_num;
538
539 return 0;
540 }
541
542 /**
543 * ice_find_netlist_node
544 * @hw: pointer to the hw struct
545 * @node_type: type of netlist node to look for
546 * @ctx: context of the search
547 * @node_part_number: node part number to look for
548 * @node_handle: output parameter if node found - optional
549 *
550 * Scan the netlist for a node handle of the given node type and part number.
551 *
552 * If node_handle is non-NULL it will be modified on function exit. It is only
553 * valid if the function returns zero, and should be ignored on any non-zero
554 * return value.
555 *
556 * Return:
557 * * 0 if the node is found,
558 * * -ENOENT if no handle was found,
559 * * negative error code on failure to access the AQ.
560 */
ice_find_netlist_node(struct ice_hw * hw,u8 node_type,u8 ctx,u8 node_part_number,u16 * node_handle)561 static int ice_find_netlist_node(struct ice_hw *hw, u8 node_type, u8 ctx,
562 u8 node_part_number, u16 *node_handle)
563 {
564 u8 idx;
565
566 for (idx = 0; idx < ICE_MAX_NETLIST_SIZE; idx++) {
567 struct ice_aqc_get_link_topo cmd = {};
568 u8 rec_node_part_number;
569 int status;
570
571 cmd.addr.topo_params.node_type_ctx =
572 FIELD_PREP(ICE_AQC_LINK_TOPO_NODE_TYPE_M, node_type) |
573 FIELD_PREP(ICE_AQC_LINK_TOPO_NODE_CTX_M, ctx);
574 cmd.addr.topo_params.index = idx;
575
576 status = ice_aq_get_netlist_node(hw, &cmd,
577 &rec_node_part_number,
578 node_handle);
579 if (status)
580 return status;
581
582 if (rec_node_part_number == node_part_number)
583 return 0;
584 }
585
586 return -ENOENT;
587 }
588
589 /**
590 * ice_is_media_cage_present
591 * @pi: port information structure
592 *
593 * Returns true if media cage is present, else false. If no cage, then
594 * media type is backplane or BASE-T.
595 */
ice_is_media_cage_present(struct ice_port_info * pi)596 static bool ice_is_media_cage_present(struct ice_port_info *pi)
597 {
598 /* Node type cage can be used to determine if cage is present. If AQC
599 * returns error (ENOENT), then no cage present. If no cage present then
600 * connection type is backplane or BASE-T.
601 */
602 return !ice_aq_get_link_topo_handle(pi,
603 ICE_AQC_LINK_TOPO_NODE_TYPE_CAGE,
604 NULL);
605 }
606
607 /**
608 * ice_get_media_type - Gets media type
609 * @pi: port information structure
610 */
ice_get_media_type(struct ice_port_info * pi)611 static enum ice_media_type ice_get_media_type(struct ice_port_info *pi)
612 {
613 struct ice_link_status *hw_link_info;
614
615 if (!pi)
616 return ICE_MEDIA_UNKNOWN;
617
618 hw_link_info = &pi->phy.link_info;
619 if (hw_link_info->phy_type_low && hw_link_info->phy_type_high)
620 /* If more than one media type is selected, report unknown */
621 return ICE_MEDIA_UNKNOWN;
622
623 if (hw_link_info->phy_type_low) {
624 /* 1G SGMII is a special case where some DA cable PHYs
625 * may show this as an option when it really shouldn't
626 * be since SGMII is meant to be between a MAC and a PHY
627 * in a backplane. Try to detect this case and handle it
628 */
629 if (hw_link_info->phy_type_low == ICE_PHY_TYPE_LOW_1G_SGMII &&
630 (hw_link_info->module_type[ICE_AQC_MOD_TYPE_IDENT] ==
631 ICE_AQC_MOD_TYPE_BYTE1_SFP_PLUS_CU_ACTIVE ||
632 hw_link_info->module_type[ICE_AQC_MOD_TYPE_IDENT] ==
633 ICE_AQC_MOD_TYPE_BYTE1_SFP_PLUS_CU_PASSIVE))
634 return ICE_MEDIA_DA;
635
636 switch (hw_link_info->phy_type_low) {
637 case ICE_PHY_TYPE_LOW_1000BASE_SX:
638 case ICE_PHY_TYPE_LOW_1000BASE_LX:
639 case ICE_PHY_TYPE_LOW_10GBASE_SR:
640 case ICE_PHY_TYPE_LOW_10GBASE_LR:
641 case ICE_PHY_TYPE_LOW_10G_SFI_C2C:
642 case ICE_PHY_TYPE_LOW_25GBASE_SR:
643 case ICE_PHY_TYPE_LOW_25GBASE_LR:
644 case ICE_PHY_TYPE_LOW_40GBASE_SR4:
645 case ICE_PHY_TYPE_LOW_40GBASE_LR4:
646 case ICE_PHY_TYPE_LOW_50GBASE_SR2:
647 case ICE_PHY_TYPE_LOW_50GBASE_LR2:
648 case ICE_PHY_TYPE_LOW_50GBASE_SR:
649 case ICE_PHY_TYPE_LOW_50GBASE_FR:
650 case ICE_PHY_TYPE_LOW_50GBASE_LR:
651 case ICE_PHY_TYPE_LOW_100GBASE_SR4:
652 case ICE_PHY_TYPE_LOW_100GBASE_LR4:
653 case ICE_PHY_TYPE_LOW_100GBASE_SR2:
654 case ICE_PHY_TYPE_LOW_100GBASE_DR:
655 case ICE_PHY_TYPE_LOW_10G_SFI_AOC_ACC:
656 case ICE_PHY_TYPE_LOW_25G_AUI_AOC_ACC:
657 case ICE_PHY_TYPE_LOW_40G_XLAUI_AOC_ACC:
658 case ICE_PHY_TYPE_LOW_50G_LAUI2_AOC_ACC:
659 case ICE_PHY_TYPE_LOW_50G_AUI2_AOC_ACC:
660 case ICE_PHY_TYPE_LOW_50G_AUI1_AOC_ACC:
661 case ICE_PHY_TYPE_LOW_100G_CAUI4_AOC_ACC:
662 case ICE_PHY_TYPE_LOW_100G_AUI4_AOC_ACC:
663 return ICE_MEDIA_FIBER;
664 case ICE_PHY_TYPE_LOW_100BASE_TX:
665 case ICE_PHY_TYPE_LOW_1000BASE_T:
666 case ICE_PHY_TYPE_LOW_2500BASE_T:
667 case ICE_PHY_TYPE_LOW_5GBASE_T:
668 case ICE_PHY_TYPE_LOW_10GBASE_T:
669 case ICE_PHY_TYPE_LOW_25GBASE_T:
670 return ICE_MEDIA_BASET;
671 case ICE_PHY_TYPE_LOW_10G_SFI_DA:
672 case ICE_PHY_TYPE_LOW_25GBASE_CR:
673 case ICE_PHY_TYPE_LOW_25GBASE_CR_S:
674 case ICE_PHY_TYPE_LOW_25GBASE_CR1:
675 case ICE_PHY_TYPE_LOW_40GBASE_CR4:
676 case ICE_PHY_TYPE_LOW_50GBASE_CR2:
677 case ICE_PHY_TYPE_LOW_50GBASE_CP:
678 case ICE_PHY_TYPE_LOW_100GBASE_CR4:
679 case ICE_PHY_TYPE_LOW_100GBASE_CR_PAM4:
680 case ICE_PHY_TYPE_LOW_100GBASE_CP2:
681 return ICE_MEDIA_DA;
682 case ICE_PHY_TYPE_LOW_25G_AUI_C2C:
683 case ICE_PHY_TYPE_LOW_40G_XLAUI:
684 case ICE_PHY_TYPE_LOW_50G_LAUI2:
685 case ICE_PHY_TYPE_LOW_50G_AUI2:
686 case ICE_PHY_TYPE_LOW_50G_AUI1:
687 case ICE_PHY_TYPE_LOW_100G_AUI4:
688 case ICE_PHY_TYPE_LOW_100G_CAUI4:
689 if (ice_is_media_cage_present(pi))
690 return ICE_MEDIA_DA;
691 fallthrough;
692 case ICE_PHY_TYPE_LOW_1000BASE_KX:
693 case ICE_PHY_TYPE_LOW_2500BASE_KX:
694 case ICE_PHY_TYPE_LOW_2500BASE_X:
695 case ICE_PHY_TYPE_LOW_5GBASE_KR:
696 case ICE_PHY_TYPE_LOW_10GBASE_KR_CR1:
697 case ICE_PHY_TYPE_LOW_25GBASE_KR:
698 case ICE_PHY_TYPE_LOW_25GBASE_KR1:
699 case ICE_PHY_TYPE_LOW_25GBASE_KR_S:
700 case ICE_PHY_TYPE_LOW_40GBASE_KR4:
701 case ICE_PHY_TYPE_LOW_50GBASE_KR_PAM4:
702 case ICE_PHY_TYPE_LOW_50GBASE_KR2:
703 case ICE_PHY_TYPE_LOW_100GBASE_KR4:
704 case ICE_PHY_TYPE_LOW_100GBASE_KR_PAM4:
705 return ICE_MEDIA_BACKPLANE;
706 }
707 } else {
708 switch (hw_link_info->phy_type_high) {
709 case ICE_PHY_TYPE_HIGH_100G_AUI2:
710 case ICE_PHY_TYPE_HIGH_100G_CAUI2:
711 if (ice_is_media_cage_present(pi))
712 return ICE_MEDIA_DA;
713 fallthrough;
714 case ICE_PHY_TYPE_HIGH_100GBASE_KR2_PAM4:
715 return ICE_MEDIA_BACKPLANE;
716 case ICE_PHY_TYPE_HIGH_100G_CAUI2_AOC_ACC:
717 case ICE_PHY_TYPE_HIGH_100G_AUI2_AOC_ACC:
718 return ICE_MEDIA_FIBER;
719 }
720 }
721 return ICE_MEDIA_UNKNOWN;
722 }
723
724 /**
725 * ice_get_link_status_datalen
726 * @hw: pointer to the HW struct
727 *
728 * Returns datalength for the Get Link Status AQ command, which is bigger for
729 * newer adapter families handled by ice driver.
730 */
ice_get_link_status_datalen(struct ice_hw * hw)731 static u16 ice_get_link_status_datalen(struct ice_hw *hw)
732 {
733 switch (hw->mac_type) {
734 case ICE_MAC_E830:
735 return ICE_AQC_LS_DATA_SIZE_V2;
736 case ICE_MAC_E810:
737 default:
738 return ICE_AQC_LS_DATA_SIZE_V1;
739 }
740 }
741
742 /**
743 * ice_aq_get_link_info
744 * @pi: port information structure
745 * @ena_lse: enable/disable LinkStatusEvent reporting
746 * @link: pointer to link status structure - optional
747 * @cd: pointer to command details structure or NULL
748 *
749 * Get Link Status (0x607). Returns the link status of the adapter.
750 */
751 int
ice_aq_get_link_info(struct ice_port_info * pi,bool ena_lse,struct ice_link_status * link,struct ice_sq_cd * cd)752 ice_aq_get_link_info(struct ice_port_info *pi, bool ena_lse,
753 struct ice_link_status *link, struct ice_sq_cd *cd)
754 {
755 struct ice_aqc_get_link_status_data link_data = { 0 };
756 struct ice_aqc_get_link_status *resp;
757 struct ice_link_status *li_old, *li;
758 enum ice_media_type *hw_media_type;
759 struct ice_fc_info *hw_fc_info;
760 bool tx_pause, rx_pause;
761 struct ice_aq_desc desc;
762 struct ice_hw *hw;
763 u16 cmd_flags;
764 int status;
765
766 if (!pi)
767 return -EINVAL;
768 hw = pi->hw;
769 li_old = &pi->phy.link_info_old;
770 hw_media_type = &pi->phy.media_type;
771 li = &pi->phy.link_info;
772 hw_fc_info = &pi->fc;
773
774 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_link_status);
775 cmd_flags = (ena_lse) ? ICE_AQ_LSE_ENA : ICE_AQ_LSE_DIS;
776 resp = &desc.params.get_link_status;
777 resp->cmd_flags = cpu_to_le16(cmd_flags);
778 resp->lport_num = pi->lport;
779
780 status = ice_aq_send_cmd(hw, &desc, &link_data,
781 ice_get_link_status_datalen(hw), cd);
782 if (status)
783 return status;
784
785 /* save off old link status information */
786 *li_old = *li;
787
788 /* update current link status information */
789 li->link_speed = le16_to_cpu(link_data.link_speed);
790 li->phy_type_low = le64_to_cpu(link_data.phy_type_low);
791 li->phy_type_high = le64_to_cpu(link_data.phy_type_high);
792 *hw_media_type = ice_get_media_type(pi);
793 li->link_info = link_data.link_info;
794 li->link_cfg_err = link_data.link_cfg_err;
795 li->an_info = link_data.an_info;
796 li->ext_info = link_data.ext_info;
797 li->max_frame_size = le16_to_cpu(link_data.max_frame_size);
798 li->fec_info = link_data.cfg & ICE_AQ_FEC_MASK;
799 li->topo_media_conflict = link_data.topo_media_conflict;
800 li->pacing = link_data.cfg & (ICE_AQ_CFG_PACING_M |
801 ICE_AQ_CFG_PACING_TYPE_M);
802
803 /* update fc info */
804 tx_pause = !!(link_data.an_info & ICE_AQ_LINK_PAUSE_TX);
805 rx_pause = !!(link_data.an_info & ICE_AQ_LINK_PAUSE_RX);
806 if (tx_pause && rx_pause)
807 hw_fc_info->current_mode = ICE_FC_FULL;
808 else if (tx_pause)
809 hw_fc_info->current_mode = ICE_FC_TX_PAUSE;
810 else if (rx_pause)
811 hw_fc_info->current_mode = ICE_FC_RX_PAUSE;
812 else
813 hw_fc_info->current_mode = ICE_FC_NONE;
814
815 li->lse_ena = !!(resp->cmd_flags & cpu_to_le16(ICE_AQ_LSE_IS_ENABLED));
816
817 ice_debug(hw, ICE_DBG_LINK, "get link info\n");
818 ice_debug(hw, ICE_DBG_LINK, " link_speed = 0x%x\n", li->link_speed);
819 ice_debug(hw, ICE_DBG_LINK, " phy_type_low = 0x%llx\n",
820 (unsigned long long)li->phy_type_low);
821 ice_debug(hw, ICE_DBG_LINK, " phy_type_high = 0x%llx\n",
822 (unsigned long long)li->phy_type_high);
823 ice_debug(hw, ICE_DBG_LINK, " media_type = 0x%x\n", *hw_media_type);
824 ice_debug(hw, ICE_DBG_LINK, " link_info = 0x%x\n", li->link_info);
825 ice_debug(hw, ICE_DBG_LINK, " link_cfg_err = 0x%x\n", li->link_cfg_err);
826 ice_debug(hw, ICE_DBG_LINK, " an_info = 0x%x\n", li->an_info);
827 ice_debug(hw, ICE_DBG_LINK, " ext_info = 0x%x\n", li->ext_info);
828 ice_debug(hw, ICE_DBG_LINK, " fec_info = 0x%x\n", li->fec_info);
829 ice_debug(hw, ICE_DBG_LINK, " lse_ena = 0x%x\n", li->lse_ena);
830 ice_debug(hw, ICE_DBG_LINK, " max_frame = 0x%x\n",
831 li->max_frame_size);
832 ice_debug(hw, ICE_DBG_LINK, " pacing = 0x%x\n", li->pacing);
833
834 /* save link status information */
835 if (link)
836 *link = *li;
837
838 /* flag cleared so calling functions don't call AQ again */
839 pi->phy.get_link_info = false;
840
841 return 0;
842 }
843
844 /**
845 * ice_fill_tx_timer_and_fc_thresh
846 * @hw: pointer to the HW struct
847 * @cmd: pointer to MAC cfg structure
848 *
849 * Add Tx timer and FC refresh threshold info to Set MAC Config AQ command
850 * descriptor
851 */
852 static void
ice_fill_tx_timer_and_fc_thresh(struct ice_hw * hw,struct ice_aqc_set_mac_cfg * cmd)853 ice_fill_tx_timer_and_fc_thresh(struct ice_hw *hw,
854 struct ice_aqc_set_mac_cfg *cmd)
855 {
856 u32 val, fc_thres_m;
857
858 /* We read back the transmit timer and FC threshold value of
859 * LFC. Thus, we will use index =
860 * PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA_MAX_INDEX.
861 *
862 * Also, because we are operating on transmit timer and FC
863 * threshold of LFC, we don't turn on any bit in tx_tmr_priority
864 */
865 #define E800_IDX_OF_LFC E800_PRTMAC_HSEC_CTL_TX_PS_QNT_MAX
866 #define E800_REFRESH_TMR E800_PRTMAC_HSEC_CTL_TX_PS_RFSH_TMR
867
868 if (hw->mac_type == ICE_MAC_E830) {
869 /* Retrieve the transmit timer */
870 val = rd32(hw, E830_PRTMAC_CL01_PS_QNT);
871 cmd->tx_tmr_value =
872 le16_encode_bits(val, E830_PRTMAC_CL01_PS_QNT_CL0_M);
873
874 /* Retrieve the fc threshold */
875 val = rd32(hw, E830_PRTMAC_CL01_QNT_THR);
876 fc_thres_m = E830_PRTMAC_CL01_QNT_THR_CL0_M;
877 } else {
878 /* Retrieve the transmit timer */
879 val = rd32(hw,
880 E800_PRTMAC_HSEC_CTL_TX_PS_QNT(E800_IDX_OF_LFC));
881 cmd->tx_tmr_value =
882 le16_encode_bits(val,
883 E800_PRTMAC_HSEC_CTL_TX_PS_QNT_M);
884
885 /* Retrieve the fc threshold */
886 val = rd32(hw,
887 E800_REFRESH_TMR(E800_IDX_OF_LFC));
888 fc_thres_m = E800_PRTMAC_HSEC_CTL_TX_PS_RFSH_TMR_M;
889 }
890 cmd->fc_refresh_threshold = le16_encode_bits(val, fc_thres_m);
891 }
892
893 /**
894 * ice_aq_set_mac_cfg
895 * @hw: pointer to the HW struct
896 * @max_frame_size: Maximum Frame Size to be supported
897 * @cd: pointer to command details structure or NULL
898 *
899 * Set MAC configuration (0x0603)
900 */
901 int
ice_aq_set_mac_cfg(struct ice_hw * hw,u16 max_frame_size,struct ice_sq_cd * cd)902 ice_aq_set_mac_cfg(struct ice_hw *hw, u16 max_frame_size, struct ice_sq_cd *cd)
903 {
904 struct ice_aqc_set_mac_cfg *cmd;
905 struct ice_aq_desc desc;
906
907 cmd = &desc.params.set_mac_cfg;
908
909 if (max_frame_size == 0)
910 return -EINVAL;
911
912 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_mac_cfg);
913
914 cmd->max_frame_size = cpu_to_le16(max_frame_size);
915
916 ice_fill_tx_timer_and_fc_thresh(hw, cmd);
917
918 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
919 }
920
921 /**
922 * ice_init_fltr_mgmt_struct - initializes filter management list and locks
923 * @hw: pointer to the HW struct
924 */
ice_init_fltr_mgmt_struct(struct ice_hw * hw)925 static int ice_init_fltr_mgmt_struct(struct ice_hw *hw)
926 {
927 struct ice_switch_info *sw;
928 int status;
929
930 hw->switch_info = devm_kzalloc(ice_hw_to_dev(hw),
931 sizeof(*hw->switch_info), GFP_KERNEL);
932 sw = hw->switch_info;
933
934 if (!sw)
935 return -ENOMEM;
936
937 INIT_LIST_HEAD(&sw->vsi_list_map_head);
938 sw->prof_res_bm_init = 0;
939
940 /* Initialize recipe count with default recipes read from NVM */
941 sw->recp_cnt = ICE_SW_LKUP_LAST;
942
943 status = ice_init_def_sw_recp(hw);
944 if (status) {
945 devm_kfree(ice_hw_to_dev(hw), hw->switch_info);
946 return status;
947 }
948 return 0;
949 }
950
951 /**
952 * ice_cleanup_fltr_mgmt_struct - cleanup filter management list and locks
953 * @hw: pointer to the HW struct
954 */
ice_cleanup_fltr_mgmt_struct(struct ice_hw * hw)955 static void ice_cleanup_fltr_mgmt_struct(struct ice_hw *hw)
956 {
957 struct ice_switch_info *sw = hw->switch_info;
958 struct ice_vsi_list_map_info *v_pos_map;
959 struct ice_vsi_list_map_info *v_tmp_map;
960 struct ice_sw_recipe *recps;
961 u8 i;
962
963 list_for_each_entry_safe(v_pos_map, v_tmp_map, &sw->vsi_list_map_head,
964 list_entry) {
965 list_del(&v_pos_map->list_entry);
966 devm_kfree(ice_hw_to_dev(hw), v_pos_map);
967 }
968 recps = sw->recp_list;
969 for (i = 0; i < ICE_MAX_NUM_RECIPES; i++) {
970 recps[i].root_rid = i;
971
972 if (recps[i].adv_rule) {
973 struct ice_adv_fltr_mgmt_list_entry *tmp_entry;
974 struct ice_adv_fltr_mgmt_list_entry *lst_itr;
975
976 mutex_destroy(&recps[i].filt_rule_lock);
977 list_for_each_entry_safe(lst_itr, tmp_entry,
978 &recps[i].filt_rules,
979 list_entry) {
980 list_del(&lst_itr->list_entry);
981 devm_kfree(ice_hw_to_dev(hw), lst_itr->lkups);
982 devm_kfree(ice_hw_to_dev(hw), lst_itr);
983 }
984 } else {
985 struct ice_fltr_mgmt_list_entry *lst_itr, *tmp_entry;
986
987 mutex_destroy(&recps[i].filt_rule_lock);
988 list_for_each_entry_safe(lst_itr, tmp_entry,
989 &recps[i].filt_rules,
990 list_entry) {
991 list_del(&lst_itr->list_entry);
992 devm_kfree(ice_hw_to_dev(hw), lst_itr);
993 }
994 }
995 }
996 ice_rm_all_sw_replay_rule_info(hw);
997 devm_kfree(ice_hw_to_dev(hw), sw->recp_list);
998 devm_kfree(ice_hw_to_dev(hw), sw);
999 }
1000
1001 /**
1002 * ice_get_itr_intrl_gran
1003 * @hw: pointer to the HW struct
1004 *
1005 * Determines the ITR/INTRL granularities based on the maximum aggregate
1006 * bandwidth according to the device's configuration during power-on.
1007 */
ice_get_itr_intrl_gran(struct ice_hw * hw)1008 static void ice_get_itr_intrl_gran(struct ice_hw *hw)
1009 {
1010 u8 max_agg_bw = FIELD_GET(GL_PWR_MODE_CTL_CAR_MAX_BW_M,
1011 rd32(hw, GL_PWR_MODE_CTL));
1012
1013 switch (max_agg_bw) {
1014 case ICE_MAX_AGG_BW_200G:
1015 case ICE_MAX_AGG_BW_100G:
1016 case ICE_MAX_AGG_BW_50G:
1017 hw->itr_gran = ICE_ITR_GRAN_ABOVE_25;
1018 hw->intrl_gran = ICE_INTRL_GRAN_ABOVE_25;
1019 break;
1020 case ICE_MAX_AGG_BW_25G:
1021 hw->itr_gran = ICE_ITR_GRAN_MAX_25;
1022 hw->intrl_gran = ICE_INTRL_GRAN_MAX_25;
1023 break;
1024 }
1025 }
1026
1027 /**
1028 * ice_init_hw - main hardware initialization routine
1029 * @hw: pointer to the hardware structure
1030 */
ice_init_hw(struct ice_hw * hw)1031 int ice_init_hw(struct ice_hw *hw)
1032 {
1033 struct ice_aqc_get_phy_caps_data *pcaps __free(kfree) = NULL;
1034 void *mac_buf __free(kfree) = NULL;
1035 u16 mac_buf_len;
1036 int status;
1037
1038 /* Set MAC type based on DeviceID */
1039 status = ice_set_mac_type(hw);
1040 if (status)
1041 return status;
1042
1043 hw->pf_id = FIELD_GET(PF_FUNC_RID_FUNC_NUM_M, rd32(hw, PF_FUNC_RID));
1044
1045 status = ice_reset(hw, ICE_RESET_PFR);
1046 if (status)
1047 return status;
1048
1049 ice_get_itr_intrl_gran(hw);
1050
1051 status = ice_create_all_ctrlq(hw);
1052 if (status)
1053 goto err_unroll_cqinit;
1054
1055 status = ice_fwlog_init(hw);
1056 if (status)
1057 ice_debug(hw, ICE_DBG_FW_LOG, "Error initializing FW logging: %d\n",
1058 status);
1059
1060 status = ice_clear_pf_cfg(hw);
1061 if (status)
1062 goto err_unroll_cqinit;
1063
1064 /* Set bit to enable Flow Director filters */
1065 wr32(hw, PFQF_FD_ENA, PFQF_FD_ENA_FD_ENA_M);
1066 INIT_LIST_HEAD(&hw->fdir_list_head);
1067
1068 ice_clear_pxe_mode(hw);
1069
1070 status = ice_init_nvm(hw);
1071 if (status)
1072 goto err_unroll_cqinit;
1073
1074 status = ice_get_caps(hw);
1075 if (status)
1076 goto err_unroll_cqinit;
1077
1078 if (!hw->port_info)
1079 hw->port_info = devm_kzalloc(ice_hw_to_dev(hw),
1080 sizeof(*hw->port_info),
1081 GFP_KERNEL);
1082 if (!hw->port_info) {
1083 status = -ENOMEM;
1084 goto err_unroll_cqinit;
1085 }
1086
1087 hw->port_info->local_fwd_mode = ICE_LOCAL_FWD_MODE_ENABLED;
1088 /* set the back pointer to HW */
1089 hw->port_info->hw = hw;
1090
1091 /* Initialize port_info struct with switch configuration data */
1092 status = ice_get_initial_sw_cfg(hw);
1093 if (status)
1094 goto err_unroll_alloc;
1095
1096 hw->evb_veb = true;
1097
1098 /* init xarray for identifying scheduling nodes uniquely */
1099 xa_init_flags(&hw->port_info->sched_node_ids, XA_FLAGS_ALLOC);
1100
1101 /* Query the allocated resources for Tx scheduler */
1102 status = ice_sched_query_res_alloc(hw);
1103 if (status) {
1104 ice_debug(hw, ICE_DBG_SCHED, "Failed to get scheduler allocated resources\n");
1105 goto err_unroll_alloc;
1106 }
1107 ice_sched_get_psm_clk_freq(hw);
1108
1109 /* Initialize port_info struct with scheduler data */
1110 status = ice_sched_init_port(hw->port_info);
1111 if (status)
1112 goto err_unroll_sched;
1113
1114 pcaps = kzalloc(sizeof(*pcaps), GFP_KERNEL);
1115 if (!pcaps) {
1116 status = -ENOMEM;
1117 goto err_unroll_sched;
1118 }
1119
1120 /* Initialize port_info struct with PHY capabilities */
1121 status = ice_aq_get_phy_caps(hw->port_info, false,
1122 ICE_AQC_REPORT_TOPO_CAP_MEDIA, pcaps,
1123 NULL);
1124 if (status)
1125 dev_warn(ice_hw_to_dev(hw), "Get PHY capabilities failed status = %d, continuing anyway\n",
1126 status);
1127
1128 /* Initialize port_info struct with link information */
1129 status = ice_aq_get_link_info(hw->port_info, false, NULL, NULL);
1130 if (status)
1131 goto err_unroll_sched;
1132
1133 /* need a valid SW entry point to build a Tx tree */
1134 if (!hw->sw_entry_point_layer) {
1135 ice_debug(hw, ICE_DBG_SCHED, "invalid sw entry point\n");
1136 status = -EIO;
1137 goto err_unroll_sched;
1138 }
1139 INIT_LIST_HEAD(&hw->agg_list);
1140 /* Initialize max burst size */
1141 if (!hw->max_burst_size)
1142 ice_cfg_rl_burst_size(hw, ICE_SCHED_DFLT_BURST_SIZE);
1143
1144 status = ice_init_fltr_mgmt_struct(hw);
1145 if (status)
1146 goto err_unroll_sched;
1147
1148 /* Get MAC information */
1149 /* A single port can report up to two (LAN and WoL) addresses */
1150 mac_buf = kcalloc(2, sizeof(struct ice_aqc_manage_mac_read_resp),
1151 GFP_KERNEL);
1152 if (!mac_buf) {
1153 status = -ENOMEM;
1154 goto err_unroll_fltr_mgmt_struct;
1155 }
1156
1157 mac_buf_len = 2 * sizeof(struct ice_aqc_manage_mac_read_resp);
1158 status = ice_aq_manage_mac_read(hw, mac_buf, mac_buf_len, NULL);
1159
1160 if (status)
1161 goto err_unroll_fltr_mgmt_struct;
1162 /* enable jumbo frame support at MAC level */
1163 status = ice_aq_set_mac_cfg(hw, ICE_AQ_SET_MAC_FRAME_SIZE_MAX, NULL);
1164 if (status)
1165 goto err_unroll_fltr_mgmt_struct;
1166 /* Obtain counter base index which would be used by flow director */
1167 status = ice_alloc_fd_res_cntr(hw, &hw->fd_ctr_base);
1168 if (status)
1169 goto err_unroll_fltr_mgmt_struct;
1170 status = ice_init_hw_tbls(hw);
1171 if (status)
1172 goto err_unroll_fltr_mgmt_struct;
1173 mutex_init(&hw->tnl_lock);
1174 ice_init_chk_recipe_reuse_support(hw);
1175
1176 return 0;
1177
1178 err_unroll_fltr_mgmt_struct:
1179 ice_cleanup_fltr_mgmt_struct(hw);
1180 err_unroll_sched:
1181 ice_sched_cleanup_all(hw);
1182 err_unroll_alloc:
1183 devm_kfree(ice_hw_to_dev(hw), hw->port_info);
1184 err_unroll_cqinit:
1185 ice_destroy_all_ctrlq(hw);
1186 return status;
1187 }
1188
1189 /**
1190 * ice_deinit_hw - unroll initialization operations done by ice_init_hw
1191 * @hw: pointer to the hardware structure
1192 *
1193 * This should be called only during nominal operation, not as a result of
1194 * ice_init_hw() failing since ice_init_hw() will take care of unrolling
1195 * applicable initializations if it fails for any reason.
1196 */
ice_deinit_hw(struct ice_hw * hw)1197 void ice_deinit_hw(struct ice_hw *hw)
1198 {
1199 ice_free_fd_res_cntr(hw, hw->fd_ctr_base);
1200 ice_cleanup_fltr_mgmt_struct(hw);
1201
1202 ice_sched_cleanup_all(hw);
1203 ice_sched_clear_agg(hw);
1204 ice_free_seg(hw);
1205 ice_free_hw_tbls(hw);
1206 mutex_destroy(&hw->tnl_lock);
1207
1208 ice_fwlog_deinit(hw);
1209 ice_destroy_all_ctrlq(hw);
1210
1211 /* Clear VSI contexts if not already cleared */
1212 ice_clear_all_vsi_ctx(hw);
1213 }
1214
1215 /**
1216 * ice_check_reset - Check to see if a global reset is complete
1217 * @hw: pointer to the hardware structure
1218 */
ice_check_reset(struct ice_hw * hw)1219 int ice_check_reset(struct ice_hw *hw)
1220 {
1221 u32 cnt, reg = 0, grst_timeout, uld_mask;
1222
1223 /* Poll for Device Active state in case a recent CORER, GLOBR,
1224 * or EMPR has occurred. The grst delay value is in 100ms units.
1225 * Add 1sec for outstanding AQ commands that can take a long time.
1226 */
1227 grst_timeout = FIELD_GET(GLGEN_RSTCTL_GRSTDEL_M,
1228 rd32(hw, GLGEN_RSTCTL)) + 10;
1229
1230 for (cnt = 0; cnt < grst_timeout; cnt++) {
1231 mdelay(100);
1232 reg = rd32(hw, GLGEN_RSTAT);
1233 if (!(reg & GLGEN_RSTAT_DEVSTATE_M))
1234 break;
1235 }
1236
1237 if (cnt == grst_timeout) {
1238 ice_debug(hw, ICE_DBG_INIT, "Global reset polling failed to complete.\n");
1239 return -EIO;
1240 }
1241
1242 #define ICE_RESET_DONE_MASK (GLNVM_ULD_PCIER_DONE_M |\
1243 GLNVM_ULD_PCIER_DONE_1_M |\
1244 GLNVM_ULD_CORER_DONE_M |\
1245 GLNVM_ULD_GLOBR_DONE_M |\
1246 GLNVM_ULD_POR_DONE_M |\
1247 GLNVM_ULD_POR_DONE_1_M |\
1248 GLNVM_ULD_PCIER_DONE_2_M)
1249
1250 uld_mask = ICE_RESET_DONE_MASK | (hw->func_caps.common_cap.rdma ?
1251 GLNVM_ULD_PE_DONE_M : 0);
1252
1253 /* Device is Active; check Global Reset processes are done */
1254 for (cnt = 0; cnt < ICE_PF_RESET_WAIT_COUNT; cnt++) {
1255 reg = rd32(hw, GLNVM_ULD) & uld_mask;
1256 if (reg == uld_mask) {
1257 ice_debug(hw, ICE_DBG_INIT, "Global reset processes done. %d\n", cnt);
1258 break;
1259 }
1260 mdelay(10);
1261 }
1262
1263 if (cnt == ICE_PF_RESET_WAIT_COUNT) {
1264 ice_debug(hw, ICE_DBG_INIT, "Wait for Reset Done timed out. GLNVM_ULD = 0x%x\n",
1265 reg);
1266 return -EIO;
1267 }
1268
1269 return 0;
1270 }
1271
1272 /**
1273 * ice_pf_reset - Reset the PF
1274 * @hw: pointer to the hardware structure
1275 *
1276 * If a global reset has been triggered, this function checks
1277 * for its completion and then issues the PF reset
1278 */
ice_pf_reset(struct ice_hw * hw)1279 static int ice_pf_reset(struct ice_hw *hw)
1280 {
1281 u32 cnt, reg;
1282
1283 /* If at function entry a global reset was already in progress, i.e.
1284 * state is not 'device active' or any of the reset done bits are not
1285 * set in GLNVM_ULD, there is no need for a PF Reset; poll until the
1286 * global reset is done.
1287 */
1288 if ((rd32(hw, GLGEN_RSTAT) & GLGEN_RSTAT_DEVSTATE_M) ||
1289 (rd32(hw, GLNVM_ULD) & ICE_RESET_DONE_MASK) ^ ICE_RESET_DONE_MASK) {
1290 /* poll on global reset currently in progress until done */
1291 if (ice_check_reset(hw))
1292 return -EIO;
1293
1294 return 0;
1295 }
1296
1297 /* Reset the PF */
1298 reg = rd32(hw, PFGEN_CTRL);
1299
1300 wr32(hw, PFGEN_CTRL, (reg | PFGEN_CTRL_PFSWR_M));
1301
1302 /* Wait for the PFR to complete. The wait time is the global config lock
1303 * timeout plus the PFR timeout which will account for a possible reset
1304 * that is occurring during a download package operation.
1305 */
1306 for (cnt = 0; cnt < ICE_GLOBAL_CFG_LOCK_TIMEOUT +
1307 ICE_PF_RESET_WAIT_COUNT; cnt++) {
1308 reg = rd32(hw, PFGEN_CTRL);
1309 if (!(reg & PFGEN_CTRL_PFSWR_M))
1310 break;
1311
1312 mdelay(1);
1313 }
1314
1315 if (cnt == ICE_PF_RESET_WAIT_COUNT) {
1316 ice_debug(hw, ICE_DBG_INIT, "PF reset polling failed to complete.\n");
1317 return -EIO;
1318 }
1319
1320 return 0;
1321 }
1322
1323 /**
1324 * ice_reset - Perform different types of reset
1325 * @hw: pointer to the hardware structure
1326 * @req: reset request
1327 *
1328 * This function triggers a reset as specified by the req parameter.
1329 *
1330 * Note:
1331 * If anything other than a PF reset is triggered, PXE mode is restored.
1332 * This has to be cleared using ice_clear_pxe_mode again, once the AQ
1333 * interface has been restored in the rebuild flow.
1334 */
ice_reset(struct ice_hw * hw,enum ice_reset_req req)1335 int ice_reset(struct ice_hw *hw, enum ice_reset_req req)
1336 {
1337 u32 val = 0;
1338
1339 switch (req) {
1340 case ICE_RESET_PFR:
1341 return ice_pf_reset(hw);
1342 case ICE_RESET_CORER:
1343 ice_debug(hw, ICE_DBG_INIT, "CoreR requested\n");
1344 val = GLGEN_RTRIG_CORER_M;
1345 break;
1346 case ICE_RESET_GLOBR:
1347 ice_debug(hw, ICE_DBG_INIT, "GlobalR requested\n");
1348 val = GLGEN_RTRIG_GLOBR_M;
1349 break;
1350 default:
1351 return -EINVAL;
1352 }
1353
1354 val |= rd32(hw, GLGEN_RTRIG);
1355 wr32(hw, GLGEN_RTRIG, val);
1356 ice_flush(hw);
1357
1358 /* wait for the FW to be ready */
1359 return ice_check_reset(hw);
1360 }
1361
1362 /**
1363 * ice_copy_rxq_ctx_to_hw
1364 * @hw: pointer to the hardware structure
1365 * @ice_rxq_ctx: pointer to the rxq context
1366 * @rxq_index: the index of the Rx queue
1367 *
1368 * Copies rxq context from dense structure to HW register space
1369 */
1370 static int
ice_copy_rxq_ctx_to_hw(struct ice_hw * hw,u8 * ice_rxq_ctx,u32 rxq_index)1371 ice_copy_rxq_ctx_to_hw(struct ice_hw *hw, u8 *ice_rxq_ctx, u32 rxq_index)
1372 {
1373 u8 i;
1374
1375 if (!ice_rxq_ctx)
1376 return -EINVAL;
1377
1378 if (rxq_index > QRX_CTRL_MAX_INDEX)
1379 return -EINVAL;
1380
1381 /* Copy each dword separately to HW */
1382 for (i = 0; i < ICE_RXQ_CTX_SIZE_DWORDS; i++) {
1383 wr32(hw, QRX_CONTEXT(i, rxq_index),
1384 *((u32 *)(ice_rxq_ctx + (i * sizeof(u32)))));
1385
1386 ice_debug(hw, ICE_DBG_QCTX, "qrxdata[%d]: %08X\n", i,
1387 *((u32 *)(ice_rxq_ctx + (i * sizeof(u32)))));
1388 }
1389
1390 return 0;
1391 }
1392
1393 /* LAN Rx Queue Context */
1394 static const struct ice_ctx_ele ice_rlan_ctx_info[] = {
1395 /* Field Width LSB */
1396 ICE_CTX_STORE(ice_rlan_ctx, head, 13, 0),
1397 ICE_CTX_STORE(ice_rlan_ctx, cpuid, 8, 13),
1398 ICE_CTX_STORE(ice_rlan_ctx, base, 57, 32),
1399 ICE_CTX_STORE(ice_rlan_ctx, qlen, 13, 89),
1400 ICE_CTX_STORE(ice_rlan_ctx, dbuf, 7, 102),
1401 ICE_CTX_STORE(ice_rlan_ctx, hbuf, 5, 109),
1402 ICE_CTX_STORE(ice_rlan_ctx, dtype, 2, 114),
1403 ICE_CTX_STORE(ice_rlan_ctx, dsize, 1, 116),
1404 ICE_CTX_STORE(ice_rlan_ctx, crcstrip, 1, 117),
1405 ICE_CTX_STORE(ice_rlan_ctx, l2tsel, 1, 119),
1406 ICE_CTX_STORE(ice_rlan_ctx, hsplit_0, 4, 120),
1407 ICE_CTX_STORE(ice_rlan_ctx, hsplit_1, 2, 124),
1408 ICE_CTX_STORE(ice_rlan_ctx, showiv, 1, 127),
1409 ICE_CTX_STORE(ice_rlan_ctx, rxmax, 14, 174),
1410 ICE_CTX_STORE(ice_rlan_ctx, tphrdesc_ena, 1, 193),
1411 ICE_CTX_STORE(ice_rlan_ctx, tphwdesc_ena, 1, 194),
1412 ICE_CTX_STORE(ice_rlan_ctx, tphdata_ena, 1, 195),
1413 ICE_CTX_STORE(ice_rlan_ctx, tphhead_ena, 1, 196),
1414 ICE_CTX_STORE(ice_rlan_ctx, lrxqthresh, 3, 198),
1415 ICE_CTX_STORE(ice_rlan_ctx, prefena, 1, 201),
1416 { 0 }
1417 };
1418
1419 /**
1420 * ice_write_rxq_ctx
1421 * @hw: pointer to the hardware structure
1422 * @rlan_ctx: pointer to the rxq context
1423 * @rxq_index: the index of the Rx queue
1424 *
1425 * Converts rxq context from sparse to dense structure and then writes
1426 * it to HW register space and enables the hardware to prefetch descriptors
1427 * instead of only fetching them on demand
1428 */
ice_write_rxq_ctx(struct ice_hw * hw,struct ice_rlan_ctx * rlan_ctx,u32 rxq_index)1429 int ice_write_rxq_ctx(struct ice_hw *hw, struct ice_rlan_ctx *rlan_ctx,
1430 u32 rxq_index)
1431 {
1432 u8 ctx_buf[ICE_RXQ_CTX_SZ] = { 0 };
1433
1434 if (!rlan_ctx)
1435 return -EINVAL;
1436
1437 rlan_ctx->prefena = 1;
1438
1439 ice_set_ctx(hw, (u8 *)rlan_ctx, ctx_buf, ice_rlan_ctx_info);
1440 return ice_copy_rxq_ctx_to_hw(hw, ctx_buf, rxq_index);
1441 }
1442
1443 /* LAN Tx Queue Context */
1444 const struct ice_ctx_ele ice_tlan_ctx_info[] = {
1445 /* Field Width LSB */
1446 ICE_CTX_STORE(ice_tlan_ctx, base, 57, 0),
1447 ICE_CTX_STORE(ice_tlan_ctx, port_num, 3, 57),
1448 ICE_CTX_STORE(ice_tlan_ctx, cgd_num, 5, 60),
1449 ICE_CTX_STORE(ice_tlan_ctx, pf_num, 3, 65),
1450 ICE_CTX_STORE(ice_tlan_ctx, vmvf_num, 10, 68),
1451 ICE_CTX_STORE(ice_tlan_ctx, vmvf_type, 2, 78),
1452 ICE_CTX_STORE(ice_tlan_ctx, src_vsi, 10, 80),
1453 ICE_CTX_STORE(ice_tlan_ctx, tsyn_ena, 1, 90),
1454 ICE_CTX_STORE(ice_tlan_ctx, internal_usage_flag, 1, 91),
1455 ICE_CTX_STORE(ice_tlan_ctx, alt_vlan, 1, 92),
1456 ICE_CTX_STORE(ice_tlan_ctx, cpuid, 8, 93),
1457 ICE_CTX_STORE(ice_tlan_ctx, wb_mode, 1, 101),
1458 ICE_CTX_STORE(ice_tlan_ctx, tphrd_desc, 1, 102),
1459 ICE_CTX_STORE(ice_tlan_ctx, tphrd, 1, 103),
1460 ICE_CTX_STORE(ice_tlan_ctx, tphwr_desc, 1, 104),
1461 ICE_CTX_STORE(ice_tlan_ctx, cmpq_id, 9, 105),
1462 ICE_CTX_STORE(ice_tlan_ctx, qnum_in_func, 14, 114),
1463 ICE_CTX_STORE(ice_tlan_ctx, itr_notification_mode, 1, 128),
1464 ICE_CTX_STORE(ice_tlan_ctx, adjust_prof_id, 6, 129),
1465 ICE_CTX_STORE(ice_tlan_ctx, qlen, 13, 135),
1466 ICE_CTX_STORE(ice_tlan_ctx, quanta_prof_idx, 4, 148),
1467 ICE_CTX_STORE(ice_tlan_ctx, tso_ena, 1, 152),
1468 ICE_CTX_STORE(ice_tlan_ctx, tso_qnum, 11, 153),
1469 ICE_CTX_STORE(ice_tlan_ctx, legacy_int, 1, 164),
1470 ICE_CTX_STORE(ice_tlan_ctx, drop_ena, 1, 165),
1471 ICE_CTX_STORE(ice_tlan_ctx, cache_prof_idx, 2, 166),
1472 ICE_CTX_STORE(ice_tlan_ctx, pkt_shaper_prof_idx, 3, 168),
1473 ICE_CTX_STORE(ice_tlan_ctx, int_q_state, 122, 171),
1474 { 0 }
1475 };
1476
1477 /* Sideband Queue command wrappers */
1478
1479 /**
1480 * ice_sbq_send_cmd - send Sideband Queue command to Sideband Queue
1481 * @hw: pointer to the HW struct
1482 * @desc: descriptor describing the command
1483 * @buf: buffer to use for indirect commands (NULL for direct commands)
1484 * @buf_size: size of buffer for indirect commands (0 for direct commands)
1485 * @cd: pointer to command details structure
1486 */
1487 static int
ice_sbq_send_cmd(struct ice_hw * hw,struct ice_sbq_cmd_desc * desc,void * buf,u16 buf_size,struct ice_sq_cd * cd)1488 ice_sbq_send_cmd(struct ice_hw *hw, struct ice_sbq_cmd_desc *desc,
1489 void *buf, u16 buf_size, struct ice_sq_cd *cd)
1490 {
1491 return ice_sq_send_cmd(hw, ice_get_sbq(hw),
1492 (struct ice_aq_desc *)desc, buf, buf_size, cd);
1493 }
1494
1495 /**
1496 * ice_sbq_rw_reg - Fill Sideband Queue command
1497 * @hw: pointer to the HW struct
1498 * @in: message info to be filled in descriptor
1499 * @flags: control queue descriptor flags
1500 */
ice_sbq_rw_reg(struct ice_hw * hw,struct ice_sbq_msg_input * in,u16 flags)1501 int ice_sbq_rw_reg(struct ice_hw *hw, struct ice_sbq_msg_input *in, u16 flags)
1502 {
1503 struct ice_sbq_cmd_desc desc = {0};
1504 struct ice_sbq_msg_req msg = {0};
1505 u16 msg_len;
1506 int status;
1507
1508 msg_len = sizeof(msg);
1509
1510 msg.dest_dev = in->dest_dev;
1511 msg.opcode = in->opcode;
1512 msg.flags = ICE_SBQ_MSG_FLAGS;
1513 msg.sbe_fbe = ICE_SBQ_MSG_SBE_FBE;
1514 msg.msg_addr_low = cpu_to_le16(in->msg_addr_low);
1515 msg.msg_addr_high = cpu_to_le32(in->msg_addr_high);
1516
1517 if (in->opcode)
1518 msg.data = cpu_to_le32(in->data);
1519 else
1520 /* data read comes back in completion, so shorten the struct by
1521 * sizeof(msg.data)
1522 */
1523 msg_len -= sizeof(msg.data);
1524
1525 desc.flags = cpu_to_le16(flags);
1526 desc.opcode = cpu_to_le16(ice_sbq_opc_neigh_dev_req);
1527 desc.param0.cmd_len = cpu_to_le16(msg_len);
1528 status = ice_sbq_send_cmd(hw, &desc, &msg, msg_len, NULL);
1529 if (!status && !in->opcode)
1530 in->data = le32_to_cpu
1531 (((struct ice_sbq_msg_cmpl *)&msg)->data);
1532 return status;
1533 }
1534
1535 /* FW Admin Queue command wrappers */
1536
1537 /* Software lock/mutex that is meant to be held while the Global Config Lock
1538 * in firmware is acquired by the software to prevent most (but not all) types
1539 * of AQ commands from being sent to FW
1540 */
1541 DEFINE_MUTEX(ice_global_cfg_lock_sw);
1542
1543 /**
1544 * ice_should_retry_sq_send_cmd
1545 * @opcode: AQ opcode
1546 *
1547 * Decide if we should retry the send command routine for the ATQ, depending
1548 * on the opcode.
1549 */
ice_should_retry_sq_send_cmd(u16 opcode)1550 static bool ice_should_retry_sq_send_cmd(u16 opcode)
1551 {
1552 switch (opcode) {
1553 case ice_aqc_opc_get_link_topo:
1554 case ice_aqc_opc_lldp_stop:
1555 case ice_aqc_opc_lldp_start:
1556 case ice_aqc_opc_lldp_filter_ctrl:
1557 return true;
1558 }
1559
1560 return false;
1561 }
1562
1563 /**
1564 * ice_sq_send_cmd_retry - send command to Control Queue (ATQ)
1565 * @hw: pointer to the HW struct
1566 * @cq: pointer to the specific Control queue
1567 * @desc: prefilled descriptor describing the command
1568 * @buf: buffer to use for indirect commands (or NULL for direct commands)
1569 * @buf_size: size of buffer for indirect commands (or 0 for direct commands)
1570 * @cd: pointer to command details structure
1571 *
1572 * Retry sending the FW Admin Queue command, multiple times, to the FW Admin
1573 * Queue if the EBUSY AQ error is returned.
1574 */
1575 static int
ice_sq_send_cmd_retry(struct ice_hw * hw,struct ice_ctl_q_info * cq,struct ice_aq_desc * desc,void * buf,u16 buf_size,struct ice_sq_cd * cd)1576 ice_sq_send_cmd_retry(struct ice_hw *hw, struct ice_ctl_q_info *cq,
1577 struct ice_aq_desc *desc, void *buf, u16 buf_size,
1578 struct ice_sq_cd *cd)
1579 {
1580 struct ice_aq_desc desc_cpy;
1581 bool is_cmd_for_retry;
1582 u8 idx = 0;
1583 u16 opcode;
1584 int status;
1585
1586 opcode = le16_to_cpu(desc->opcode);
1587 is_cmd_for_retry = ice_should_retry_sq_send_cmd(opcode);
1588 memset(&desc_cpy, 0, sizeof(desc_cpy));
1589
1590 if (is_cmd_for_retry) {
1591 /* All retryable cmds are direct, without buf. */
1592 WARN_ON(buf);
1593
1594 memcpy(&desc_cpy, desc, sizeof(desc_cpy));
1595 }
1596
1597 do {
1598 status = ice_sq_send_cmd(hw, cq, desc, buf, buf_size, cd);
1599
1600 if (!is_cmd_for_retry || !status ||
1601 hw->adminq.sq_last_status != ICE_AQ_RC_EBUSY)
1602 break;
1603
1604 memcpy(desc, &desc_cpy, sizeof(desc_cpy));
1605
1606 msleep(ICE_SQ_SEND_DELAY_TIME_MS);
1607
1608 } while (++idx < ICE_SQ_SEND_MAX_EXECUTE);
1609
1610 return status;
1611 }
1612
1613 /**
1614 * ice_aq_send_cmd - send FW Admin Queue command to FW Admin Queue
1615 * @hw: pointer to the HW struct
1616 * @desc: descriptor describing the command
1617 * @buf: buffer to use for indirect commands (NULL for direct commands)
1618 * @buf_size: size of buffer for indirect commands (0 for direct commands)
1619 * @cd: pointer to command details structure
1620 *
1621 * Helper function to send FW Admin Queue commands to the FW Admin Queue.
1622 */
1623 int
ice_aq_send_cmd(struct ice_hw * hw,struct ice_aq_desc * desc,void * buf,u16 buf_size,struct ice_sq_cd * cd)1624 ice_aq_send_cmd(struct ice_hw *hw, struct ice_aq_desc *desc, void *buf,
1625 u16 buf_size, struct ice_sq_cd *cd)
1626 {
1627 struct ice_aqc_req_res *cmd = &desc->params.res_owner;
1628 bool lock_acquired = false;
1629 int status;
1630
1631 /* When a package download is in process (i.e. when the firmware's
1632 * Global Configuration Lock resource is held), only the Download
1633 * Package, Get Version, Get Package Info List, Upload Section,
1634 * Update Package, Set Port Parameters, Get/Set VLAN Mode Parameters,
1635 * Add Recipe, Set Recipes to Profile Association, Get Recipe, and Get
1636 * Recipes to Profile Association, and Release Resource (with resource
1637 * ID set to Global Config Lock) AdminQ commands are allowed; all others
1638 * must block until the package download completes and the Global Config
1639 * Lock is released. See also ice_acquire_global_cfg_lock().
1640 */
1641 switch (le16_to_cpu(desc->opcode)) {
1642 case ice_aqc_opc_download_pkg:
1643 case ice_aqc_opc_get_pkg_info_list:
1644 case ice_aqc_opc_get_ver:
1645 case ice_aqc_opc_upload_section:
1646 case ice_aqc_opc_update_pkg:
1647 case ice_aqc_opc_set_port_params:
1648 case ice_aqc_opc_get_vlan_mode_parameters:
1649 case ice_aqc_opc_set_vlan_mode_parameters:
1650 case ice_aqc_opc_set_tx_topo:
1651 case ice_aqc_opc_get_tx_topo:
1652 case ice_aqc_opc_add_recipe:
1653 case ice_aqc_opc_recipe_to_profile:
1654 case ice_aqc_opc_get_recipe:
1655 case ice_aqc_opc_get_recipe_to_profile:
1656 break;
1657 case ice_aqc_opc_release_res:
1658 if (le16_to_cpu(cmd->res_id) == ICE_AQC_RES_ID_GLBL_LOCK)
1659 break;
1660 fallthrough;
1661 default:
1662 mutex_lock(&ice_global_cfg_lock_sw);
1663 lock_acquired = true;
1664 break;
1665 }
1666
1667 status = ice_sq_send_cmd_retry(hw, &hw->adminq, desc, buf, buf_size, cd);
1668 if (lock_acquired)
1669 mutex_unlock(&ice_global_cfg_lock_sw);
1670
1671 return status;
1672 }
1673
1674 /**
1675 * ice_aq_get_fw_ver
1676 * @hw: pointer to the HW struct
1677 * @cd: pointer to command details structure or NULL
1678 *
1679 * Get the firmware version (0x0001) from the admin queue commands
1680 */
ice_aq_get_fw_ver(struct ice_hw * hw,struct ice_sq_cd * cd)1681 int ice_aq_get_fw_ver(struct ice_hw *hw, struct ice_sq_cd *cd)
1682 {
1683 struct ice_aqc_get_ver *resp;
1684 struct ice_aq_desc desc;
1685 int status;
1686
1687 resp = &desc.params.get_ver;
1688
1689 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_ver);
1690
1691 status = ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
1692
1693 if (!status) {
1694 hw->fw_branch = resp->fw_branch;
1695 hw->fw_maj_ver = resp->fw_major;
1696 hw->fw_min_ver = resp->fw_minor;
1697 hw->fw_patch = resp->fw_patch;
1698 hw->fw_build = le32_to_cpu(resp->fw_build);
1699 hw->api_branch = resp->api_branch;
1700 hw->api_maj_ver = resp->api_major;
1701 hw->api_min_ver = resp->api_minor;
1702 hw->api_patch = resp->api_patch;
1703 }
1704
1705 return status;
1706 }
1707
1708 /**
1709 * ice_aq_send_driver_ver
1710 * @hw: pointer to the HW struct
1711 * @dv: driver's major, minor version
1712 * @cd: pointer to command details structure or NULL
1713 *
1714 * Send the driver version (0x0002) to the firmware
1715 */
1716 int
ice_aq_send_driver_ver(struct ice_hw * hw,struct ice_driver_ver * dv,struct ice_sq_cd * cd)1717 ice_aq_send_driver_ver(struct ice_hw *hw, struct ice_driver_ver *dv,
1718 struct ice_sq_cd *cd)
1719 {
1720 struct ice_aqc_driver_ver *cmd;
1721 struct ice_aq_desc desc;
1722 u16 len;
1723
1724 cmd = &desc.params.driver_ver;
1725
1726 if (!dv)
1727 return -EINVAL;
1728
1729 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_driver_ver);
1730
1731 desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD);
1732 cmd->major_ver = dv->major_ver;
1733 cmd->minor_ver = dv->minor_ver;
1734 cmd->build_ver = dv->build_ver;
1735 cmd->subbuild_ver = dv->subbuild_ver;
1736
1737 len = 0;
1738 while (len < sizeof(dv->driver_string) &&
1739 isascii(dv->driver_string[len]) && dv->driver_string[len])
1740 len++;
1741
1742 return ice_aq_send_cmd(hw, &desc, dv->driver_string, len, cd);
1743 }
1744
1745 /**
1746 * ice_aq_q_shutdown
1747 * @hw: pointer to the HW struct
1748 * @unloading: is the driver unloading itself
1749 *
1750 * Tell the Firmware that we're shutting down the AdminQ and whether
1751 * or not the driver is unloading as well (0x0003).
1752 */
ice_aq_q_shutdown(struct ice_hw * hw,bool unloading)1753 int ice_aq_q_shutdown(struct ice_hw *hw, bool unloading)
1754 {
1755 struct ice_aqc_q_shutdown *cmd;
1756 struct ice_aq_desc desc;
1757
1758 cmd = &desc.params.q_shutdown;
1759
1760 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_q_shutdown);
1761
1762 if (unloading)
1763 cmd->driver_unloading = ICE_AQC_DRIVER_UNLOADING;
1764
1765 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL);
1766 }
1767
1768 /**
1769 * ice_aq_req_res
1770 * @hw: pointer to the HW struct
1771 * @res: resource ID
1772 * @access: access type
1773 * @sdp_number: resource number
1774 * @timeout: the maximum time in ms that the driver may hold the resource
1775 * @cd: pointer to command details structure or NULL
1776 *
1777 * Requests common resource using the admin queue commands (0x0008).
1778 * When attempting to acquire the Global Config Lock, the driver can
1779 * learn of three states:
1780 * 1) 0 - acquired lock, and can perform download package
1781 * 2) -EIO - did not get lock, driver should fail to load
1782 * 3) -EALREADY - did not get lock, but another driver has
1783 * successfully downloaded the package; the driver does
1784 * not have to download the package and can continue
1785 * loading
1786 *
1787 * Note that if the caller is in an acquire lock, perform action, release lock
1788 * phase of operation, it is possible that the FW may detect a timeout and issue
1789 * a CORER. In this case, the driver will receive a CORER interrupt and will
1790 * have to determine its cause. The calling thread that is handling this flow
1791 * will likely get an error propagated back to it indicating the Download
1792 * Package, Update Package or the Release Resource AQ commands timed out.
1793 */
1794 static int
ice_aq_req_res(struct ice_hw * hw,enum ice_aq_res_ids res,enum ice_aq_res_access_type access,u8 sdp_number,u32 * timeout,struct ice_sq_cd * cd)1795 ice_aq_req_res(struct ice_hw *hw, enum ice_aq_res_ids res,
1796 enum ice_aq_res_access_type access, u8 sdp_number, u32 *timeout,
1797 struct ice_sq_cd *cd)
1798 {
1799 struct ice_aqc_req_res *cmd_resp;
1800 struct ice_aq_desc desc;
1801 int status;
1802
1803 cmd_resp = &desc.params.res_owner;
1804
1805 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_req_res);
1806
1807 cmd_resp->res_id = cpu_to_le16(res);
1808 cmd_resp->access_type = cpu_to_le16(access);
1809 cmd_resp->res_number = cpu_to_le32(sdp_number);
1810 cmd_resp->timeout = cpu_to_le32(*timeout);
1811 *timeout = 0;
1812
1813 status = ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
1814
1815 /* The completion specifies the maximum time in ms that the driver
1816 * may hold the resource in the Timeout field.
1817 */
1818
1819 /* Global config lock response utilizes an additional status field.
1820 *
1821 * If the Global config lock resource is held by some other driver, the
1822 * command completes with ICE_AQ_RES_GLBL_IN_PROG in the status field
1823 * and the timeout field indicates the maximum time the current owner
1824 * of the resource has to free it.
1825 */
1826 if (res == ICE_GLOBAL_CFG_LOCK_RES_ID) {
1827 if (le16_to_cpu(cmd_resp->status) == ICE_AQ_RES_GLBL_SUCCESS) {
1828 *timeout = le32_to_cpu(cmd_resp->timeout);
1829 return 0;
1830 } else if (le16_to_cpu(cmd_resp->status) ==
1831 ICE_AQ_RES_GLBL_IN_PROG) {
1832 *timeout = le32_to_cpu(cmd_resp->timeout);
1833 return -EIO;
1834 } else if (le16_to_cpu(cmd_resp->status) ==
1835 ICE_AQ_RES_GLBL_DONE) {
1836 return -EALREADY;
1837 }
1838
1839 /* invalid FW response, force a timeout immediately */
1840 *timeout = 0;
1841 return -EIO;
1842 }
1843
1844 /* If the resource is held by some other driver, the command completes
1845 * with a busy return value and the timeout field indicates the maximum
1846 * time the current owner of the resource has to free it.
1847 */
1848 if (!status || hw->adminq.sq_last_status == ICE_AQ_RC_EBUSY)
1849 *timeout = le32_to_cpu(cmd_resp->timeout);
1850
1851 return status;
1852 }
1853
1854 /**
1855 * ice_aq_release_res
1856 * @hw: pointer to the HW struct
1857 * @res: resource ID
1858 * @sdp_number: resource number
1859 * @cd: pointer to command details structure or NULL
1860 *
1861 * release common resource using the admin queue commands (0x0009)
1862 */
1863 static int
ice_aq_release_res(struct ice_hw * hw,enum ice_aq_res_ids res,u8 sdp_number,struct ice_sq_cd * cd)1864 ice_aq_release_res(struct ice_hw *hw, enum ice_aq_res_ids res, u8 sdp_number,
1865 struct ice_sq_cd *cd)
1866 {
1867 struct ice_aqc_req_res *cmd;
1868 struct ice_aq_desc desc;
1869
1870 cmd = &desc.params.res_owner;
1871
1872 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_release_res);
1873
1874 cmd->res_id = cpu_to_le16(res);
1875 cmd->res_number = cpu_to_le32(sdp_number);
1876
1877 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
1878 }
1879
1880 /**
1881 * ice_acquire_res
1882 * @hw: pointer to the HW structure
1883 * @res: resource ID
1884 * @access: access type (read or write)
1885 * @timeout: timeout in milliseconds
1886 *
1887 * This function will attempt to acquire the ownership of a resource.
1888 */
1889 int
ice_acquire_res(struct ice_hw * hw,enum ice_aq_res_ids res,enum ice_aq_res_access_type access,u32 timeout)1890 ice_acquire_res(struct ice_hw *hw, enum ice_aq_res_ids res,
1891 enum ice_aq_res_access_type access, u32 timeout)
1892 {
1893 #define ICE_RES_POLLING_DELAY_MS 10
1894 u32 delay = ICE_RES_POLLING_DELAY_MS;
1895 u32 time_left = timeout;
1896 int status;
1897
1898 status = ice_aq_req_res(hw, res, access, 0, &time_left, NULL);
1899
1900 /* A return code of -EALREADY means that another driver has
1901 * previously acquired the resource and performed any necessary updates;
1902 * in this case the caller does not obtain the resource and has no
1903 * further work to do.
1904 */
1905 if (status == -EALREADY)
1906 goto ice_acquire_res_exit;
1907
1908 if (status)
1909 ice_debug(hw, ICE_DBG_RES, "resource %d acquire type %d failed.\n", res, access);
1910
1911 /* If necessary, poll until the current lock owner timeouts */
1912 timeout = time_left;
1913 while (status && timeout && time_left) {
1914 mdelay(delay);
1915 timeout = (timeout > delay) ? timeout - delay : 0;
1916 status = ice_aq_req_res(hw, res, access, 0, &time_left, NULL);
1917
1918 if (status == -EALREADY)
1919 /* lock free, but no work to do */
1920 break;
1921
1922 if (!status)
1923 /* lock acquired */
1924 break;
1925 }
1926 if (status && status != -EALREADY)
1927 ice_debug(hw, ICE_DBG_RES, "resource acquire timed out.\n");
1928
1929 ice_acquire_res_exit:
1930 if (status == -EALREADY) {
1931 if (access == ICE_RES_WRITE)
1932 ice_debug(hw, ICE_DBG_RES, "resource indicates no work to do.\n");
1933 else
1934 ice_debug(hw, ICE_DBG_RES, "Warning: -EALREADY not expected\n");
1935 }
1936 return status;
1937 }
1938
1939 /**
1940 * ice_release_res
1941 * @hw: pointer to the HW structure
1942 * @res: resource ID
1943 *
1944 * This function will release a resource using the proper Admin Command.
1945 */
ice_release_res(struct ice_hw * hw,enum ice_aq_res_ids res)1946 void ice_release_res(struct ice_hw *hw, enum ice_aq_res_ids res)
1947 {
1948 unsigned long timeout;
1949 int status;
1950
1951 /* there are some rare cases when trying to release the resource
1952 * results in an admin queue timeout, so handle them correctly
1953 */
1954 timeout = jiffies + 10 * ICE_CTL_Q_SQ_CMD_TIMEOUT;
1955 do {
1956 status = ice_aq_release_res(hw, res, 0, NULL);
1957 if (status != -EIO)
1958 break;
1959 usleep_range(1000, 2000);
1960 } while (time_before(jiffies, timeout));
1961 }
1962
1963 /**
1964 * ice_aq_alloc_free_res - command to allocate/free resources
1965 * @hw: pointer to the HW struct
1966 * @buf: Indirect buffer to hold data parameters and response
1967 * @buf_size: size of buffer for indirect commands
1968 * @opc: pass in the command opcode
1969 *
1970 * Helper function to allocate/free resources using the admin queue commands
1971 */
ice_aq_alloc_free_res(struct ice_hw * hw,struct ice_aqc_alloc_free_res_elem * buf,u16 buf_size,enum ice_adminq_opc opc)1972 int ice_aq_alloc_free_res(struct ice_hw *hw,
1973 struct ice_aqc_alloc_free_res_elem *buf, u16 buf_size,
1974 enum ice_adminq_opc opc)
1975 {
1976 struct ice_aqc_alloc_free_res_cmd *cmd;
1977 struct ice_aq_desc desc;
1978
1979 cmd = &desc.params.sw_res_ctrl;
1980
1981 if (!buf || buf_size < flex_array_size(buf, elem, 1))
1982 return -EINVAL;
1983
1984 ice_fill_dflt_direct_cmd_desc(&desc, opc);
1985
1986 desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD);
1987
1988 cmd->num_entries = cpu_to_le16(1);
1989
1990 return ice_aq_send_cmd(hw, &desc, buf, buf_size, NULL);
1991 }
1992
1993 /**
1994 * ice_alloc_hw_res - allocate resource
1995 * @hw: pointer to the HW struct
1996 * @type: type of resource
1997 * @num: number of resources to allocate
1998 * @btm: allocate from bottom
1999 * @res: pointer to array that will receive the resources
2000 */
2001 int
ice_alloc_hw_res(struct ice_hw * hw,u16 type,u16 num,bool btm,u16 * res)2002 ice_alloc_hw_res(struct ice_hw *hw, u16 type, u16 num, bool btm, u16 *res)
2003 {
2004 struct ice_aqc_alloc_free_res_elem *buf;
2005 u16 buf_len;
2006 int status;
2007
2008 buf_len = struct_size(buf, elem, num);
2009 buf = kzalloc(buf_len, GFP_KERNEL);
2010 if (!buf)
2011 return -ENOMEM;
2012
2013 /* Prepare buffer to allocate resource. */
2014 buf->num_elems = cpu_to_le16(num);
2015 buf->res_type = cpu_to_le16(type | ICE_AQC_RES_TYPE_FLAG_DEDICATED |
2016 ICE_AQC_RES_TYPE_FLAG_IGNORE_INDEX);
2017 if (btm)
2018 buf->res_type |= cpu_to_le16(ICE_AQC_RES_TYPE_FLAG_SCAN_BOTTOM);
2019
2020 status = ice_aq_alloc_free_res(hw, buf, buf_len, ice_aqc_opc_alloc_res);
2021 if (status)
2022 goto ice_alloc_res_exit;
2023
2024 memcpy(res, buf->elem, sizeof(*buf->elem) * num);
2025
2026 ice_alloc_res_exit:
2027 kfree(buf);
2028 return status;
2029 }
2030
2031 /**
2032 * ice_free_hw_res - free allocated HW resource
2033 * @hw: pointer to the HW struct
2034 * @type: type of resource to free
2035 * @num: number of resources
2036 * @res: pointer to array that contains the resources to free
2037 */
ice_free_hw_res(struct ice_hw * hw,u16 type,u16 num,u16 * res)2038 int ice_free_hw_res(struct ice_hw *hw, u16 type, u16 num, u16 *res)
2039 {
2040 struct ice_aqc_alloc_free_res_elem *buf;
2041 u16 buf_len;
2042 int status;
2043
2044 buf_len = struct_size(buf, elem, num);
2045 buf = kzalloc(buf_len, GFP_KERNEL);
2046 if (!buf)
2047 return -ENOMEM;
2048
2049 /* Prepare buffer to free resource. */
2050 buf->num_elems = cpu_to_le16(num);
2051 buf->res_type = cpu_to_le16(type);
2052 memcpy(buf->elem, res, sizeof(*buf->elem) * num);
2053
2054 status = ice_aq_alloc_free_res(hw, buf, buf_len, ice_aqc_opc_free_res);
2055 if (status)
2056 ice_debug(hw, ICE_DBG_SW, "CQ CMD Buffer:\n");
2057
2058 kfree(buf);
2059 return status;
2060 }
2061
2062 /**
2063 * ice_get_num_per_func - determine number of resources per PF
2064 * @hw: pointer to the HW structure
2065 * @max: value to be evenly split between each PF
2066 *
2067 * Determine the number of valid functions by going through the bitmap returned
2068 * from parsing capabilities and use this to calculate the number of resources
2069 * per PF based on the max value passed in.
2070 */
ice_get_num_per_func(struct ice_hw * hw,u32 max)2071 static u32 ice_get_num_per_func(struct ice_hw *hw, u32 max)
2072 {
2073 u8 funcs;
2074
2075 #define ICE_CAPS_VALID_FUNCS_M 0xFF
2076 funcs = hweight8(hw->dev_caps.common_cap.valid_functions &
2077 ICE_CAPS_VALID_FUNCS_M);
2078
2079 if (!funcs)
2080 return 0;
2081
2082 return max / funcs;
2083 }
2084
2085 /**
2086 * ice_parse_common_caps - parse common device/function capabilities
2087 * @hw: pointer to the HW struct
2088 * @caps: pointer to common capabilities structure
2089 * @elem: the capability element to parse
2090 * @prefix: message prefix for tracing capabilities
2091 *
2092 * Given a capability element, extract relevant details into the common
2093 * capability structure.
2094 *
2095 * Returns: true if the capability matches one of the common capability ids,
2096 * false otherwise.
2097 */
2098 static bool
ice_parse_common_caps(struct ice_hw * hw,struct ice_hw_common_caps * caps,struct ice_aqc_list_caps_elem * elem,const char * prefix)2099 ice_parse_common_caps(struct ice_hw *hw, struct ice_hw_common_caps *caps,
2100 struct ice_aqc_list_caps_elem *elem, const char *prefix)
2101 {
2102 u32 logical_id = le32_to_cpu(elem->logical_id);
2103 u32 phys_id = le32_to_cpu(elem->phys_id);
2104 u32 number = le32_to_cpu(elem->number);
2105 u16 cap = le16_to_cpu(elem->cap);
2106 bool found = true;
2107
2108 switch (cap) {
2109 case ICE_AQC_CAPS_VALID_FUNCTIONS:
2110 caps->valid_functions = number;
2111 ice_debug(hw, ICE_DBG_INIT, "%s: valid_functions (bitmap) = %d\n", prefix,
2112 caps->valid_functions);
2113 break;
2114 case ICE_AQC_CAPS_SRIOV:
2115 caps->sr_iov_1_1 = (number == 1);
2116 ice_debug(hw, ICE_DBG_INIT, "%s: sr_iov_1_1 = %d\n", prefix,
2117 caps->sr_iov_1_1);
2118 break;
2119 case ICE_AQC_CAPS_DCB:
2120 caps->dcb = (number == 1);
2121 caps->active_tc_bitmap = logical_id;
2122 caps->maxtc = phys_id;
2123 ice_debug(hw, ICE_DBG_INIT, "%s: dcb = %d\n", prefix, caps->dcb);
2124 ice_debug(hw, ICE_DBG_INIT, "%s: active_tc_bitmap = %d\n", prefix,
2125 caps->active_tc_bitmap);
2126 ice_debug(hw, ICE_DBG_INIT, "%s: maxtc = %d\n", prefix, caps->maxtc);
2127 break;
2128 case ICE_AQC_CAPS_RSS:
2129 caps->rss_table_size = number;
2130 caps->rss_table_entry_width = logical_id;
2131 ice_debug(hw, ICE_DBG_INIT, "%s: rss_table_size = %d\n", prefix,
2132 caps->rss_table_size);
2133 ice_debug(hw, ICE_DBG_INIT, "%s: rss_table_entry_width = %d\n", prefix,
2134 caps->rss_table_entry_width);
2135 break;
2136 case ICE_AQC_CAPS_RXQS:
2137 caps->num_rxq = number;
2138 caps->rxq_first_id = phys_id;
2139 ice_debug(hw, ICE_DBG_INIT, "%s: num_rxq = %d\n", prefix,
2140 caps->num_rxq);
2141 ice_debug(hw, ICE_DBG_INIT, "%s: rxq_first_id = %d\n", prefix,
2142 caps->rxq_first_id);
2143 break;
2144 case ICE_AQC_CAPS_TXQS:
2145 caps->num_txq = number;
2146 caps->txq_first_id = phys_id;
2147 ice_debug(hw, ICE_DBG_INIT, "%s: num_txq = %d\n", prefix,
2148 caps->num_txq);
2149 ice_debug(hw, ICE_DBG_INIT, "%s: txq_first_id = %d\n", prefix,
2150 caps->txq_first_id);
2151 break;
2152 case ICE_AQC_CAPS_MSIX:
2153 caps->num_msix_vectors = number;
2154 caps->msix_vector_first_id = phys_id;
2155 ice_debug(hw, ICE_DBG_INIT, "%s: num_msix_vectors = %d\n", prefix,
2156 caps->num_msix_vectors);
2157 ice_debug(hw, ICE_DBG_INIT, "%s: msix_vector_first_id = %d\n", prefix,
2158 caps->msix_vector_first_id);
2159 break;
2160 case ICE_AQC_CAPS_PENDING_NVM_VER:
2161 caps->nvm_update_pending_nvm = true;
2162 ice_debug(hw, ICE_DBG_INIT, "%s: update_pending_nvm\n", prefix);
2163 break;
2164 case ICE_AQC_CAPS_PENDING_OROM_VER:
2165 caps->nvm_update_pending_orom = true;
2166 ice_debug(hw, ICE_DBG_INIT, "%s: update_pending_orom\n", prefix);
2167 break;
2168 case ICE_AQC_CAPS_PENDING_NET_VER:
2169 caps->nvm_update_pending_netlist = true;
2170 ice_debug(hw, ICE_DBG_INIT, "%s: update_pending_netlist\n", prefix);
2171 break;
2172 case ICE_AQC_CAPS_NVM_MGMT:
2173 caps->nvm_unified_update =
2174 (number & ICE_NVM_MGMT_UNIFIED_UPD_SUPPORT) ?
2175 true : false;
2176 ice_debug(hw, ICE_DBG_INIT, "%s: nvm_unified_update = %d\n", prefix,
2177 caps->nvm_unified_update);
2178 break;
2179 case ICE_AQC_CAPS_RDMA:
2180 caps->rdma = (number == 1);
2181 ice_debug(hw, ICE_DBG_INIT, "%s: rdma = %d\n", prefix, caps->rdma);
2182 break;
2183 case ICE_AQC_CAPS_MAX_MTU:
2184 caps->max_mtu = number;
2185 ice_debug(hw, ICE_DBG_INIT, "%s: max_mtu = %d\n",
2186 prefix, caps->max_mtu);
2187 break;
2188 case ICE_AQC_CAPS_PCIE_RESET_AVOIDANCE:
2189 caps->pcie_reset_avoidance = (number > 0);
2190 ice_debug(hw, ICE_DBG_INIT,
2191 "%s: pcie_reset_avoidance = %d\n", prefix,
2192 caps->pcie_reset_avoidance);
2193 break;
2194 case ICE_AQC_CAPS_POST_UPDATE_RESET_RESTRICT:
2195 caps->reset_restrict_support = (number == 1);
2196 ice_debug(hw, ICE_DBG_INIT,
2197 "%s: reset_restrict_support = %d\n", prefix,
2198 caps->reset_restrict_support);
2199 break;
2200 case ICE_AQC_CAPS_FW_LAG_SUPPORT:
2201 caps->roce_lag = !!(number & ICE_AQC_BIT_ROCEV2_LAG);
2202 ice_debug(hw, ICE_DBG_INIT, "%s: roce_lag = %u\n",
2203 prefix, caps->roce_lag);
2204 caps->sriov_lag = !!(number & ICE_AQC_BIT_SRIOV_LAG);
2205 ice_debug(hw, ICE_DBG_INIT, "%s: sriov_lag = %u\n",
2206 prefix, caps->sriov_lag);
2207 break;
2208 case ICE_AQC_CAPS_TX_SCHED_TOPO_COMP_MODE:
2209 caps->tx_sched_topo_comp_mode_en = (number == 1);
2210 break;
2211 default:
2212 /* Not one of the recognized common capabilities */
2213 found = false;
2214 }
2215
2216 return found;
2217 }
2218
2219 /**
2220 * ice_recalc_port_limited_caps - Recalculate port limited capabilities
2221 * @hw: pointer to the HW structure
2222 * @caps: pointer to capabilities structure to fix
2223 *
2224 * Re-calculate the capabilities that are dependent on the number of physical
2225 * ports; i.e. some features are not supported or function differently on
2226 * devices with more than 4 ports.
2227 */
2228 static void
ice_recalc_port_limited_caps(struct ice_hw * hw,struct ice_hw_common_caps * caps)2229 ice_recalc_port_limited_caps(struct ice_hw *hw, struct ice_hw_common_caps *caps)
2230 {
2231 /* This assumes device capabilities are always scanned before function
2232 * capabilities during the initialization flow.
2233 */
2234 if (hw->dev_caps.num_funcs > 4) {
2235 /* Max 4 TCs per port */
2236 caps->maxtc = 4;
2237 ice_debug(hw, ICE_DBG_INIT, "reducing maxtc to %d (based on #ports)\n",
2238 caps->maxtc);
2239 if (caps->rdma) {
2240 ice_debug(hw, ICE_DBG_INIT, "forcing RDMA off\n");
2241 caps->rdma = 0;
2242 }
2243
2244 /* print message only when processing device capabilities
2245 * during initialization.
2246 */
2247 if (caps == &hw->dev_caps.common_cap)
2248 dev_info(ice_hw_to_dev(hw), "RDMA functionality is not available with the current device configuration.\n");
2249 }
2250 }
2251
2252 /**
2253 * ice_parse_vf_func_caps - Parse ICE_AQC_CAPS_VF function caps
2254 * @hw: pointer to the HW struct
2255 * @func_p: pointer to function capabilities structure
2256 * @cap: pointer to the capability element to parse
2257 *
2258 * Extract function capabilities for ICE_AQC_CAPS_VF.
2259 */
2260 static void
ice_parse_vf_func_caps(struct ice_hw * hw,struct ice_hw_func_caps * func_p,struct ice_aqc_list_caps_elem * cap)2261 ice_parse_vf_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_p,
2262 struct ice_aqc_list_caps_elem *cap)
2263 {
2264 u32 logical_id = le32_to_cpu(cap->logical_id);
2265 u32 number = le32_to_cpu(cap->number);
2266
2267 func_p->num_allocd_vfs = number;
2268 func_p->vf_base_id = logical_id;
2269 ice_debug(hw, ICE_DBG_INIT, "func caps: num_allocd_vfs = %d\n",
2270 func_p->num_allocd_vfs);
2271 ice_debug(hw, ICE_DBG_INIT, "func caps: vf_base_id = %d\n",
2272 func_p->vf_base_id);
2273 }
2274
2275 /**
2276 * ice_parse_vsi_func_caps - Parse ICE_AQC_CAPS_VSI function caps
2277 * @hw: pointer to the HW struct
2278 * @func_p: pointer to function capabilities structure
2279 * @cap: pointer to the capability element to parse
2280 *
2281 * Extract function capabilities for ICE_AQC_CAPS_VSI.
2282 */
2283 static void
ice_parse_vsi_func_caps(struct ice_hw * hw,struct ice_hw_func_caps * func_p,struct ice_aqc_list_caps_elem * cap)2284 ice_parse_vsi_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_p,
2285 struct ice_aqc_list_caps_elem *cap)
2286 {
2287 func_p->guar_num_vsi = ice_get_num_per_func(hw, ICE_MAX_VSI);
2288 ice_debug(hw, ICE_DBG_INIT, "func caps: guar_num_vsi (fw) = %d\n",
2289 le32_to_cpu(cap->number));
2290 ice_debug(hw, ICE_DBG_INIT, "func caps: guar_num_vsi = %d\n",
2291 func_p->guar_num_vsi);
2292 }
2293
2294 /**
2295 * ice_parse_1588_func_caps - Parse ICE_AQC_CAPS_1588 function caps
2296 * @hw: pointer to the HW struct
2297 * @func_p: pointer to function capabilities structure
2298 * @cap: pointer to the capability element to parse
2299 *
2300 * Extract function capabilities for ICE_AQC_CAPS_1588.
2301 */
2302 static void
ice_parse_1588_func_caps(struct ice_hw * hw,struct ice_hw_func_caps * func_p,struct ice_aqc_list_caps_elem * cap)2303 ice_parse_1588_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_p,
2304 struct ice_aqc_list_caps_elem *cap)
2305 {
2306 struct ice_ts_func_info *info = &func_p->ts_func_info;
2307 u32 number = le32_to_cpu(cap->number);
2308
2309 info->ena = ((number & ICE_TS_FUNC_ENA_M) != 0);
2310 func_p->common_cap.ieee_1588 = info->ena;
2311
2312 info->src_tmr_owned = ((number & ICE_TS_SRC_TMR_OWND_M) != 0);
2313 info->tmr_ena = ((number & ICE_TS_TMR_ENA_M) != 0);
2314 info->tmr_index_owned = ((number & ICE_TS_TMR_IDX_OWND_M) != 0);
2315 info->tmr_index_assoc = ((number & ICE_TS_TMR_IDX_ASSOC_M) != 0);
2316
2317 if (!ice_is_e825c(hw)) {
2318 info->clk_freq = FIELD_GET(ICE_TS_CLK_FREQ_M, number);
2319 info->clk_src = ((number & ICE_TS_CLK_SRC_M) != 0);
2320 } else {
2321 info->clk_freq = ICE_TIME_REF_FREQ_156_250;
2322 info->clk_src = ICE_CLK_SRC_TCXO;
2323 }
2324
2325 if (info->clk_freq < NUM_ICE_TIME_REF_FREQ) {
2326 info->time_ref = (enum ice_time_ref_freq)info->clk_freq;
2327 } else {
2328 /* Unknown clock frequency, so assume a (probably incorrect)
2329 * default to avoid out-of-bounds look ups of frequency
2330 * related information.
2331 */
2332 ice_debug(hw, ICE_DBG_INIT, "1588 func caps: unknown clock frequency %u\n",
2333 info->clk_freq);
2334 info->time_ref = ICE_TIME_REF_FREQ_25_000;
2335 }
2336
2337 ice_debug(hw, ICE_DBG_INIT, "func caps: ieee_1588 = %u\n",
2338 func_p->common_cap.ieee_1588);
2339 ice_debug(hw, ICE_DBG_INIT, "func caps: src_tmr_owned = %u\n",
2340 info->src_tmr_owned);
2341 ice_debug(hw, ICE_DBG_INIT, "func caps: tmr_ena = %u\n",
2342 info->tmr_ena);
2343 ice_debug(hw, ICE_DBG_INIT, "func caps: tmr_index_owned = %u\n",
2344 info->tmr_index_owned);
2345 ice_debug(hw, ICE_DBG_INIT, "func caps: tmr_index_assoc = %u\n",
2346 info->tmr_index_assoc);
2347 ice_debug(hw, ICE_DBG_INIT, "func caps: clk_freq = %u\n",
2348 info->clk_freq);
2349 ice_debug(hw, ICE_DBG_INIT, "func caps: clk_src = %u\n",
2350 info->clk_src);
2351 }
2352
2353 /**
2354 * ice_parse_fdir_func_caps - Parse ICE_AQC_CAPS_FD function caps
2355 * @hw: pointer to the HW struct
2356 * @func_p: pointer to function capabilities structure
2357 *
2358 * Extract function capabilities for ICE_AQC_CAPS_FD.
2359 */
2360 static void
ice_parse_fdir_func_caps(struct ice_hw * hw,struct ice_hw_func_caps * func_p)2361 ice_parse_fdir_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_p)
2362 {
2363 u32 reg_val, gsize, bsize;
2364
2365 reg_val = rd32(hw, GLQF_FD_SIZE);
2366 switch (hw->mac_type) {
2367 case ICE_MAC_E830:
2368 gsize = FIELD_GET(E830_GLQF_FD_SIZE_FD_GSIZE_M, reg_val);
2369 bsize = FIELD_GET(E830_GLQF_FD_SIZE_FD_BSIZE_M, reg_val);
2370 break;
2371 case ICE_MAC_E810:
2372 default:
2373 gsize = FIELD_GET(E800_GLQF_FD_SIZE_FD_GSIZE_M, reg_val);
2374 bsize = FIELD_GET(E800_GLQF_FD_SIZE_FD_BSIZE_M, reg_val);
2375 }
2376 func_p->fd_fltr_guar = ice_get_num_per_func(hw, gsize);
2377 func_p->fd_fltr_best_effort = bsize;
2378
2379 ice_debug(hw, ICE_DBG_INIT, "func caps: fd_fltr_guar = %d\n",
2380 func_p->fd_fltr_guar);
2381 ice_debug(hw, ICE_DBG_INIT, "func caps: fd_fltr_best_effort = %d\n",
2382 func_p->fd_fltr_best_effort);
2383 }
2384
2385 /**
2386 * ice_parse_func_caps - Parse function capabilities
2387 * @hw: pointer to the HW struct
2388 * @func_p: pointer to function capabilities structure
2389 * @buf: buffer containing the function capability records
2390 * @cap_count: the number of capabilities
2391 *
2392 * Helper function to parse function (0x000A) capabilities list. For
2393 * capabilities shared between device and function, this relies on
2394 * ice_parse_common_caps.
2395 *
2396 * Loop through the list of provided capabilities and extract the relevant
2397 * data into the function capabilities structured.
2398 */
2399 static void
ice_parse_func_caps(struct ice_hw * hw,struct ice_hw_func_caps * func_p,void * buf,u32 cap_count)2400 ice_parse_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_p,
2401 void *buf, u32 cap_count)
2402 {
2403 struct ice_aqc_list_caps_elem *cap_resp;
2404 u32 i;
2405
2406 cap_resp = buf;
2407
2408 memset(func_p, 0, sizeof(*func_p));
2409
2410 for (i = 0; i < cap_count; i++) {
2411 u16 cap = le16_to_cpu(cap_resp[i].cap);
2412 bool found;
2413
2414 found = ice_parse_common_caps(hw, &func_p->common_cap,
2415 &cap_resp[i], "func caps");
2416
2417 switch (cap) {
2418 case ICE_AQC_CAPS_VF:
2419 ice_parse_vf_func_caps(hw, func_p, &cap_resp[i]);
2420 break;
2421 case ICE_AQC_CAPS_VSI:
2422 ice_parse_vsi_func_caps(hw, func_p, &cap_resp[i]);
2423 break;
2424 case ICE_AQC_CAPS_1588:
2425 ice_parse_1588_func_caps(hw, func_p, &cap_resp[i]);
2426 break;
2427 case ICE_AQC_CAPS_FD:
2428 ice_parse_fdir_func_caps(hw, func_p);
2429 break;
2430 default:
2431 /* Don't list common capabilities as unknown */
2432 if (!found)
2433 ice_debug(hw, ICE_DBG_INIT, "func caps: unknown capability[%d]: 0x%x\n",
2434 i, cap);
2435 break;
2436 }
2437 }
2438
2439 ice_recalc_port_limited_caps(hw, &func_p->common_cap);
2440 }
2441
2442 /**
2443 * ice_parse_valid_functions_cap - Parse ICE_AQC_CAPS_VALID_FUNCTIONS caps
2444 * @hw: pointer to the HW struct
2445 * @dev_p: pointer to device capabilities structure
2446 * @cap: capability element to parse
2447 *
2448 * Parse ICE_AQC_CAPS_VALID_FUNCTIONS for device capabilities.
2449 */
2450 static void
ice_parse_valid_functions_cap(struct ice_hw * hw,struct ice_hw_dev_caps * dev_p,struct ice_aqc_list_caps_elem * cap)2451 ice_parse_valid_functions_cap(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p,
2452 struct ice_aqc_list_caps_elem *cap)
2453 {
2454 u32 number = le32_to_cpu(cap->number);
2455
2456 dev_p->num_funcs = hweight32(number);
2457 ice_debug(hw, ICE_DBG_INIT, "dev caps: num_funcs = %d\n",
2458 dev_p->num_funcs);
2459 }
2460
2461 /**
2462 * ice_parse_vf_dev_caps - Parse ICE_AQC_CAPS_VF device caps
2463 * @hw: pointer to the HW struct
2464 * @dev_p: pointer to device capabilities structure
2465 * @cap: capability element to parse
2466 *
2467 * Parse ICE_AQC_CAPS_VF for device capabilities.
2468 */
2469 static void
ice_parse_vf_dev_caps(struct ice_hw * hw,struct ice_hw_dev_caps * dev_p,struct ice_aqc_list_caps_elem * cap)2470 ice_parse_vf_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p,
2471 struct ice_aqc_list_caps_elem *cap)
2472 {
2473 u32 number = le32_to_cpu(cap->number);
2474
2475 dev_p->num_vfs_exposed = number;
2476 ice_debug(hw, ICE_DBG_INIT, "dev_caps: num_vfs_exposed = %d\n",
2477 dev_p->num_vfs_exposed);
2478 }
2479
2480 /**
2481 * ice_parse_vsi_dev_caps - Parse ICE_AQC_CAPS_VSI device caps
2482 * @hw: pointer to the HW struct
2483 * @dev_p: pointer to device capabilities structure
2484 * @cap: capability element to parse
2485 *
2486 * Parse ICE_AQC_CAPS_VSI for device capabilities.
2487 */
2488 static void
ice_parse_vsi_dev_caps(struct ice_hw * hw,struct ice_hw_dev_caps * dev_p,struct ice_aqc_list_caps_elem * cap)2489 ice_parse_vsi_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p,
2490 struct ice_aqc_list_caps_elem *cap)
2491 {
2492 u32 number = le32_to_cpu(cap->number);
2493
2494 dev_p->num_vsi_allocd_to_host = number;
2495 ice_debug(hw, ICE_DBG_INIT, "dev caps: num_vsi_allocd_to_host = %d\n",
2496 dev_p->num_vsi_allocd_to_host);
2497 }
2498
2499 /**
2500 * ice_parse_1588_dev_caps - Parse ICE_AQC_CAPS_1588 device caps
2501 * @hw: pointer to the HW struct
2502 * @dev_p: pointer to device capabilities structure
2503 * @cap: capability element to parse
2504 *
2505 * Parse ICE_AQC_CAPS_1588 for device capabilities.
2506 */
2507 static void
ice_parse_1588_dev_caps(struct ice_hw * hw,struct ice_hw_dev_caps * dev_p,struct ice_aqc_list_caps_elem * cap)2508 ice_parse_1588_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p,
2509 struct ice_aqc_list_caps_elem *cap)
2510 {
2511 struct ice_ts_dev_info *info = &dev_p->ts_dev_info;
2512 u32 logical_id = le32_to_cpu(cap->logical_id);
2513 u32 phys_id = le32_to_cpu(cap->phys_id);
2514 u32 number = le32_to_cpu(cap->number);
2515
2516 info->ena = ((number & ICE_TS_DEV_ENA_M) != 0);
2517 dev_p->common_cap.ieee_1588 = info->ena;
2518
2519 info->tmr0_owner = number & ICE_TS_TMR0_OWNR_M;
2520 info->tmr0_owned = ((number & ICE_TS_TMR0_OWND_M) != 0);
2521 info->tmr0_ena = ((number & ICE_TS_TMR0_ENA_M) != 0);
2522
2523 info->tmr1_owner = FIELD_GET(ICE_TS_TMR1_OWNR_M, number);
2524 info->tmr1_owned = ((number & ICE_TS_TMR1_OWND_M) != 0);
2525 info->tmr1_ena = ((number & ICE_TS_TMR1_ENA_M) != 0);
2526
2527 info->ts_ll_read = ((number & ICE_TS_LL_TX_TS_READ_M) != 0);
2528 info->ts_ll_int_read = ((number & ICE_TS_LL_TX_TS_INT_READ_M) != 0);
2529
2530 info->ena_ports = logical_id;
2531 info->tmr_own_map = phys_id;
2532
2533 ice_debug(hw, ICE_DBG_INIT, "dev caps: ieee_1588 = %u\n",
2534 dev_p->common_cap.ieee_1588);
2535 ice_debug(hw, ICE_DBG_INIT, "dev caps: tmr0_owner = %u\n",
2536 info->tmr0_owner);
2537 ice_debug(hw, ICE_DBG_INIT, "dev caps: tmr0_owned = %u\n",
2538 info->tmr0_owned);
2539 ice_debug(hw, ICE_DBG_INIT, "dev caps: tmr0_ena = %u\n",
2540 info->tmr0_ena);
2541 ice_debug(hw, ICE_DBG_INIT, "dev caps: tmr1_owner = %u\n",
2542 info->tmr1_owner);
2543 ice_debug(hw, ICE_DBG_INIT, "dev caps: tmr1_owned = %u\n",
2544 info->tmr1_owned);
2545 ice_debug(hw, ICE_DBG_INIT, "dev caps: tmr1_ena = %u\n",
2546 info->tmr1_ena);
2547 ice_debug(hw, ICE_DBG_INIT, "dev caps: ts_ll_read = %u\n",
2548 info->ts_ll_read);
2549 ice_debug(hw, ICE_DBG_INIT, "dev caps: ts_ll_int_read = %u\n",
2550 info->ts_ll_int_read);
2551 ice_debug(hw, ICE_DBG_INIT, "dev caps: ieee_1588 ena_ports = %u\n",
2552 info->ena_ports);
2553 ice_debug(hw, ICE_DBG_INIT, "dev caps: tmr_own_map = %u\n",
2554 info->tmr_own_map);
2555 }
2556
2557 /**
2558 * ice_parse_fdir_dev_caps - Parse ICE_AQC_CAPS_FD device caps
2559 * @hw: pointer to the HW struct
2560 * @dev_p: pointer to device capabilities structure
2561 * @cap: capability element to parse
2562 *
2563 * Parse ICE_AQC_CAPS_FD for device capabilities.
2564 */
2565 static void
ice_parse_fdir_dev_caps(struct ice_hw * hw,struct ice_hw_dev_caps * dev_p,struct ice_aqc_list_caps_elem * cap)2566 ice_parse_fdir_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p,
2567 struct ice_aqc_list_caps_elem *cap)
2568 {
2569 u32 number = le32_to_cpu(cap->number);
2570
2571 dev_p->num_flow_director_fltr = number;
2572 ice_debug(hw, ICE_DBG_INIT, "dev caps: num_flow_director_fltr = %d\n",
2573 dev_p->num_flow_director_fltr);
2574 }
2575
2576 /**
2577 * ice_parse_sensor_reading_cap - Parse ICE_AQC_CAPS_SENSOR_READING cap
2578 * @hw: pointer to the HW struct
2579 * @dev_p: pointer to device capabilities structure
2580 * @cap: capability element to parse
2581 *
2582 * Parse ICE_AQC_CAPS_SENSOR_READING for device capability for reading
2583 * enabled sensors.
2584 */
2585 static void
ice_parse_sensor_reading_cap(struct ice_hw * hw,struct ice_hw_dev_caps * dev_p,struct ice_aqc_list_caps_elem * cap)2586 ice_parse_sensor_reading_cap(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p,
2587 struct ice_aqc_list_caps_elem *cap)
2588 {
2589 dev_p->supported_sensors = le32_to_cpu(cap->number);
2590
2591 ice_debug(hw, ICE_DBG_INIT,
2592 "dev caps: supported sensors (bitmap) = 0x%x\n",
2593 dev_p->supported_sensors);
2594 }
2595
2596 /**
2597 * ice_parse_nac_topo_dev_caps - Parse ICE_AQC_CAPS_NAC_TOPOLOGY cap
2598 * @hw: pointer to the HW struct
2599 * @dev_p: pointer to device capabilities structure
2600 * @cap: capability element to parse
2601 *
2602 * Parse ICE_AQC_CAPS_NAC_TOPOLOGY for device capabilities.
2603 */
ice_parse_nac_topo_dev_caps(struct ice_hw * hw,struct ice_hw_dev_caps * dev_p,struct ice_aqc_list_caps_elem * cap)2604 static void ice_parse_nac_topo_dev_caps(struct ice_hw *hw,
2605 struct ice_hw_dev_caps *dev_p,
2606 struct ice_aqc_list_caps_elem *cap)
2607 {
2608 dev_p->nac_topo.mode = le32_to_cpu(cap->number);
2609 dev_p->nac_topo.id = le32_to_cpu(cap->phys_id) & ICE_NAC_TOPO_ID_M;
2610
2611 dev_info(ice_hw_to_dev(hw),
2612 "PF is configured in %s mode with IP instance ID %d\n",
2613 (dev_p->nac_topo.mode & ICE_NAC_TOPO_PRIMARY_M) ?
2614 "primary" : "secondary", dev_p->nac_topo.id);
2615
2616 ice_debug(hw, ICE_DBG_INIT, "dev caps: nac topology is_primary = %d\n",
2617 !!(dev_p->nac_topo.mode & ICE_NAC_TOPO_PRIMARY_M));
2618 ice_debug(hw, ICE_DBG_INIT, "dev caps: nac topology is_dual = %d\n",
2619 !!(dev_p->nac_topo.mode & ICE_NAC_TOPO_DUAL_M));
2620 ice_debug(hw, ICE_DBG_INIT, "dev caps: nac topology id = %d\n",
2621 dev_p->nac_topo.id);
2622 }
2623
2624 /**
2625 * ice_parse_dev_caps - Parse device capabilities
2626 * @hw: pointer to the HW struct
2627 * @dev_p: pointer to device capabilities structure
2628 * @buf: buffer containing the device capability records
2629 * @cap_count: the number of capabilities
2630 *
2631 * Helper device to parse device (0x000B) capabilities list. For
2632 * capabilities shared between device and function, this relies on
2633 * ice_parse_common_caps.
2634 *
2635 * Loop through the list of provided capabilities and extract the relevant
2636 * data into the device capabilities structured.
2637 */
2638 static void
ice_parse_dev_caps(struct ice_hw * hw,struct ice_hw_dev_caps * dev_p,void * buf,u32 cap_count)2639 ice_parse_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p,
2640 void *buf, u32 cap_count)
2641 {
2642 struct ice_aqc_list_caps_elem *cap_resp;
2643 u32 i;
2644
2645 cap_resp = buf;
2646
2647 memset(dev_p, 0, sizeof(*dev_p));
2648
2649 for (i = 0; i < cap_count; i++) {
2650 u16 cap = le16_to_cpu(cap_resp[i].cap);
2651 bool found;
2652
2653 found = ice_parse_common_caps(hw, &dev_p->common_cap,
2654 &cap_resp[i], "dev caps");
2655
2656 switch (cap) {
2657 case ICE_AQC_CAPS_VALID_FUNCTIONS:
2658 ice_parse_valid_functions_cap(hw, dev_p, &cap_resp[i]);
2659 break;
2660 case ICE_AQC_CAPS_VF:
2661 ice_parse_vf_dev_caps(hw, dev_p, &cap_resp[i]);
2662 break;
2663 case ICE_AQC_CAPS_VSI:
2664 ice_parse_vsi_dev_caps(hw, dev_p, &cap_resp[i]);
2665 break;
2666 case ICE_AQC_CAPS_1588:
2667 ice_parse_1588_dev_caps(hw, dev_p, &cap_resp[i]);
2668 break;
2669 case ICE_AQC_CAPS_FD:
2670 ice_parse_fdir_dev_caps(hw, dev_p, &cap_resp[i]);
2671 break;
2672 case ICE_AQC_CAPS_SENSOR_READING:
2673 ice_parse_sensor_reading_cap(hw, dev_p, &cap_resp[i]);
2674 break;
2675 case ICE_AQC_CAPS_NAC_TOPOLOGY:
2676 ice_parse_nac_topo_dev_caps(hw, dev_p, &cap_resp[i]);
2677 break;
2678 default:
2679 /* Don't list common capabilities as unknown */
2680 if (!found)
2681 ice_debug(hw, ICE_DBG_INIT, "dev caps: unknown capability[%d]: 0x%x\n",
2682 i, cap);
2683 break;
2684 }
2685 }
2686
2687 ice_recalc_port_limited_caps(hw, &dev_p->common_cap);
2688 }
2689
2690 /**
2691 * ice_is_pf_c827 - check if pf contains c827 phy
2692 * @hw: pointer to the hw struct
2693 */
ice_is_pf_c827(struct ice_hw * hw)2694 bool ice_is_pf_c827(struct ice_hw *hw)
2695 {
2696 struct ice_aqc_get_link_topo cmd = {};
2697 u8 node_part_number;
2698 u16 node_handle;
2699 int status;
2700
2701 if (hw->mac_type != ICE_MAC_E810)
2702 return false;
2703
2704 if (hw->device_id != ICE_DEV_ID_E810C_QSFP)
2705 return true;
2706
2707 cmd.addr.topo_params.node_type_ctx =
2708 FIELD_PREP(ICE_AQC_LINK_TOPO_NODE_TYPE_M, ICE_AQC_LINK_TOPO_NODE_TYPE_PHY) |
2709 FIELD_PREP(ICE_AQC_LINK_TOPO_NODE_CTX_M, ICE_AQC_LINK_TOPO_NODE_CTX_PORT);
2710 cmd.addr.topo_params.index = 0;
2711
2712 status = ice_aq_get_netlist_node(hw, &cmd, &node_part_number,
2713 &node_handle);
2714
2715 if (status || node_part_number != ICE_AQC_GET_LINK_TOPO_NODE_NR_C827)
2716 return false;
2717
2718 if (node_handle == E810C_QSFP_C827_0_HANDLE || node_handle == E810C_QSFP_C827_1_HANDLE)
2719 return true;
2720
2721 return false;
2722 }
2723
2724 /**
2725 * ice_is_phy_rclk_in_netlist
2726 * @hw: pointer to the hw struct
2727 *
2728 * Check if the PHY Recovered Clock device is present in the netlist
2729 */
ice_is_phy_rclk_in_netlist(struct ice_hw * hw)2730 bool ice_is_phy_rclk_in_netlist(struct ice_hw *hw)
2731 {
2732 if (ice_find_netlist_node(hw, ICE_AQC_LINK_TOPO_NODE_TYPE_PHY,
2733 ICE_AQC_LINK_TOPO_NODE_CTX_PORT,
2734 ICE_AQC_GET_LINK_TOPO_NODE_NR_C827, NULL) &&
2735 ice_find_netlist_node(hw, ICE_AQC_LINK_TOPO_NODE_TYPE_PHY,
2736 ICE_AQC_LINK_TOPO_NODE_CTX_PORT,
2737 ICE_AQC_GET_LINK_TOPO_NODE_NR_E822_PHY, NULL))
2738 return false;
2739
2740 return true;
2741 }
2742
2743 /**
2744 * ice_is_clock_mux_in_netlist
2745 * @hw: pointer to the hw struct
2746 *
2747 * Check if the Clock Multiplexer device is present in the netlist
2748 */
ice_is_clock_mux_in_netlist(struct ice_hw * hw)2749 bool ice_is_clock_mux_in_netlist(struct ice_hw *hw)
2750 {
2751 if (ice_find_netlist_node(hw, ICE_AQC_LINK_TOPO_NODE_TYPE_CLK_MUX,
2752 ICE_AQC_LINK_TOPO_NODE_CTX_GLOBAL,
2753 ICE_AQC_GET_LINK_TOPO_NODE_NR_GEN_CLK_MUX,
2754 NULL))
2755 return false;
2756
2757 return true;
2758 }
2759
2760 /**
2761 * ice_is_cgu_in_netlist - check for CGU presence
2762 * @hw: pointer to the hw struct
2763 *
2764 * Check if the Clock Generation Unit (CGU) device is present in the netlist.
2765 * Save the CGU part number in the hw structure for later use.
2766 * Return:
2767 * * true - cgu is present
2768 * * false - cgu is not present
2769 */
ice_is_cgu_in_netlist(struct ice_hw * hw)2770 bool ice_is_cgu_in_netlist(struct ice_hw *hw)
2771 {
2772 if (!ice_find_netlist_node(hw, ICE_AQC_LINK_TOPO_NODE_TYPE_CLK_CTRL,
2773 ICE_AQC_LINK_TOPO_NODE_CTX_GLOBAL,
2774 ICE_AQC_GET_LINK_TOPO_NODE_NR_ZL30632_80032,
2775 NULL)) {
2776 hw->cgu_part_number = ICE_AQC_GET_LINK_TOPO_NODE_NR_ZL30632_80032;
2777 return true;
2778 } else if (!ice_find_netlist_node(hw,
2779 ICE_AQC_LINK_TOPO_NODE_TYPE_CLK_CTRL,
2780 ICE_AQC_LINK_TOPO_NODE_CTX_GLOBAL,
2781 ICE_AQC_GET_LINK_TOPO_NODE_NR_SI5383_5384,
2782 NULL)) {
2783 hw->cgu_part_number = ICE_AQC_GET_LINK_TOPO_NODE_NR_SI5383_5384;
2784 return true;
2785 }
2786
2787 return false;
2788 }
2789
2790 /**
2791 * ice_is_gps_in_netlist
2792 * @hw: pointer to the hw struct
2793 *
2794 * Check if the GPS generic device is present in the netlist
2795 */
ice_is_gps_in_netlist(struct ice_hw * hw)2796 bool ice_is_gps_in_netlist(struct ice_hw *hw)
2797 {
2798 if (ice_find_netlist_node(hw, ICE_AQC_LINK_TOPO_NODE_TYPE_GPS,
2799 ICE_AQC_LINK_TOPO_NODE_CTX_GLOBAL,
2800 ICE_AQC_GET_LINK_TOPO_NODE_NR_GEN_GPS, NULL))
2801 return false;
2802
2803 return true;
2804 }
2805
2806 /**
2807 * ice_aq_list_caps - query function/device capabilities
2808 * @hw: pointer to the HW struct
2809 * @buf: a buffer to hold the capabilities
2810 * @buf_size: size of the buffer
2811 * @cap_count: if not NULL, set to the number of capabilities reported
2812 * @opc: capabilities type to discover, device or function
2813 * @cd: pointer to command details structure or NULL
2814 *
2815 * Get the function (0x000A) or device (0x000B) capabilities description from
2816 * firmware and store it in the buffer.
2817 *
2818 * If the cap_count pointer is not NULL, then it is set to the number of
2819 * capabilities firmware will report. Note that if the buffer size is too
2820 * small, it is possible the command will return ICE_AQ_ERR_ENOMEM. The
2821 * cap_count will still be updated in this case. It is recommended that the
2822 * buffer size be set to ICE_AQ_MAX_BUF_LEN (the largest possible buffer that
2823 * firmware could return) to avoid this.
2824 */
2825 int
ice_aq_list_caps(struct ice_hw * hw,void * buf,u16 buf_size,u32 * cap_count,enum ice_adminq_opc opc,struct ice_sq_cd * cd)2826 ice_aq_list_caps(struct ice_hw *hw, void *buf, u16 buf_size, u32 *cap_count,
2827 enum ice_adminq_opc opc, struct ice_sq_cd *cd)
2828 {
2829 struct ice_aqc_list_caps *cmd;
2830 struct ice_aq_desc desc;
2831 int status;
2832
2833 cmd = &desc.params.get_cap;
2834
2835 if (opc != ice_aqc_opc_list_func_caps &&
2836 opc != ice_aqc_opc_list_dev_caps)
2837 return -EINVAL;
2838
2839 ice_fill_dflt_direct_cmd_desc(&desc, opc);
2840 status = ice_aq_send_cmd(hw, &desc, buf, buf_size, cd);
2841
2842 if (cap_count)
2843 *cap_count = le32_to_cpu(cmd->count);
2844
2845 return status;
2846 }
2847
2848 /**
2849 * ice_discover_dev_caps - Read and extract device capabilities
2850 * @hw: pointer to the hardware structure
2851 * @dev_caps: pointer to device capabilities structure
2852 *
2853 * Read the device capabilities and extract them into the dev_caps structure
2854 * for later use.
2855 */
2856 int
ice_discover_dev_caps(struct ice_hw * hw,struct ice_hw_dev_caps * dev_caps)2857 ice_discover_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_caps)
2858 {
2859 u32 cap_count = 0;
2860 void *cbuf;
2861 int status;
2862
2863 cbuf = kzalloc(ICE_AQ_MAX_BUF_LEN, GFP_KERNEL);
2864 if (!cbuf)
2865 return -ENOMEM;
2866
2867 /* Although the driver doesn't know the number of capabilities the
2868 * device will return, we can simply send a 4KB buffer, the maximum
2869 * possible size that firmware can return.
2870 */
2871 cap_count = ICE_AQ_MAX_BUF_LEN / sizeof(struct ice_aqc_list_caps_elem);
2872
2873 status = ice_aq_list_caps(hw, cbuf, ICE_AQ_MAX_BUF_LEN, &cap_count,
2874 ice_aqc_opc_list_dev_caps, NULL);
2875 if (!status)
2876 ice_parse_dev_caps(hw, dev_caps, cbuf, cap_count);
2877 kfree(cbuf);
2878
2879 return status;
2880 }
2881
2882 /**
2883 * ice_discover_func_caps - Read and extract function capabilities
2884 * @hw: pointer to the hardware structure
2885 * @func_caps: pointer to function capabilities structure
2886 *
2887 * Read the function capabilities and extract them into the func_caps structure
2888 * for later use.
2889 */
2890 static int
ice_discover_func_caps(struct ice_hw * hw,struct ice_hw_func_caps * func_caps)2891 ice_discover_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_caps)
2892 {
2893 u32 cap_count = 0;
2894 void *cbuf;
2895 int status;
2896
2897 cbuf = kzalloc(ICE_AQ_MAX_BUF_LEN, GFP_KERNEL);
2898 if (!cbuf)
2899 return -ENOMEM;
2900
2901 /* Although the driver doesn't know the number of capabilities the
2902 * device will return, we can simply send a 4KB buffer, the maximum
2903 * possible size that firmware can return.
2904 */
2905 cap_count = ICE_AQ_MAX_BUF_LEN / sizeof(struct ice_aqc_list_caps_elem);
2906
2907 status = ice_aq_list_caps(hw, cbuf, ICE_AQ_MAX_BUF_LEN, &cap_count,
2908 ice_aqc_opc_list_func_caps, NULL);
2909 if (!status)
2910 ice_parse_func_caps(hw, func_caps, cbuf, cap_count);
2911 kfree(cbuf);
2912
2913 return status;
2914 }
2915
2916 /**
2917 * ice_set_safe_mode_caps - Override dev/func capabilities when in safe mode
2918 * @hw: pointer to the hardware structure
2919 */
ice_set_safe_mode_caps(struct ice_hw * hw)2920 void ice_set_safe_mode_caps(struct ice_hw *hw)
2921 {
2922 struct ice_hw_func_caps *func_caps = &hw->func_caps;
2923 struct ice_hw_dev_caps *dev_caps = &hw->dev_caps;
2924 struct ice_hw_common_caps cached_caps;
2925 u32 num_funcs;
2926
2927 /* cache some func_caps values that should be restored after memset */
2928 cached_caps = func_caps->common_cap;
2929
2930 /* unset func capabilities */
2931 memset(func_caps, 0, sizeof(*func_caps));
2932
2933 #define ICE_RESTORE_FUNC_CAP(name) \
2934 func_caps->common_cap.name = cached_caps.name
2935
2936 /* restore cached values */
2937 ICE_RESTORE_FUNC_CAP(valid_functions);
2938 ICE_RESTORE_FUNC_CAP(txq_first_id);
2939 ICE_RESTORE_FUNC_CAP(rxq_first_id);
2940 ICE_RESTORE_FUNC_CAP(msix_vector_first_id);
2941 ICE_RESTORE_FUNC_CAP(max_mtu);
2942 ICE_RESTORE_FUNC_CAP(nvm_unified_update);
2943 ICE_RESTORE_FUNC_CAP(nvm_update_pending_nvm);
2944 ICE_RESTORE_FUNC_CAP(nvm_update_pending_orom);
2945 ICE_RESTORE_FUNC_CAP(nvm_update_pending_netlist);
2946
2947 /* one Tx and one Rx queue in safe mode */
2948 func_caps->common_cap.num_rxq = 1;
2949 func_caps->common_cap.num_txq = 1;
2950
2951 /* two MSIX vectors, one for traffic and one for misc causes */
2952 func_caps->common_cap.num_msix_vectors = 2;
2953 func_caps->guar_num_vsi = 1;
2954
2955 /* cache some dev_caps values that should be restored after memset */
2956 cached_caps = dev_caps->common_cap;
2957 num_funcs = dev_caps->num_funcs;
2958
2959 /* unset dev capabilities */
2960 memset(dev_caps, 0, sizeof(*dev_caps));
2961
2962 #define ICE_RESTORE_DEV_CAP(name) \
2963 dev_caps->common_cap.name = cached_caps.name
2964
2965 /* restore cached values */
2966 ICE_RESTORE_DEV_CAP(valid_functions);
2967 ICE_RESTORE_DEV_CAP(txq_first_id);
2968 ICE_RESTORE_DEV_CAP(rxq_first_id);
2969 ICE_RESTORE_DEV_CAP(msix_vector_first_id);
2970 ICE_RESTORE_DEV_CAP(max_mtu);
2971 ICE_RESTORE_DEV_CAP(nvm_unified_update);
2972 ICE_RESTORE_DEV_CAP(nvm_update_pending_nvm);
2973 ICE_RESTORE_DEV_CAP(nvm_update_pending_orom);
2974 ICE_RESTORE_DEV_CAP(nvm_update_pending_netlist);
2975 dev_caps->num_funcs = num_funcs;
2976
2977 /* one Tx and one Rx queue per function in safe mode */
2978 dev_caps->common_cap.num_rxq = num_funcs;
2979 dev_caps->common_cap.num_txq = num_funcs;
2980
2981 /* two MSIX vectors per function */
2982 dev_caps->common_cap.num_msix_vectors = 2 * num_funcs;
2983 }
2984
2985 /**
2986 * ice_get_caps - get info about the HW
2987 * @hw: pointer to the hardware structure
2988 */
ice_get_caps(struct ice_hw * hw)2989 int ice_get_caps(struct ice_hw *hw)
2990 {
2991 int status;
2992
2993 status = ice_discover_dev_caps(hw, &hw->dev_caps);
2994 if (status)
2995 return status;
2996
2997 return ice_discover_func_caps(hw, &hw->func_caps);
2998 }
2999
3000 /**
3001 * ice_aq_manage_mac_write - manage MAC address write command
3002 * @hw: pointer to the HW struct
3003 * @mac_addr: MAC address to be written as LAA/LAA+WoL/Port address
3004 * @flags: flags to control write behavior
3005 * @cd: pointer to command details structure or NULL
3006 *
3007 * This function is used to write MAC address to the NVM (0x0108).
3008 */
3009 int
ice_aq_manage_mac_write(struct ice_hw * hw,const u8 * mac_addr,u8 flags,struct ice_sq_cd * cd)3010 ice_aq_manage_mac_write(struct ice_hw *hw, const u8 *mac_addr, u8 flags,
3011 struct ice_sq_cd *cd)
3012 {
3013 struct ice_aqc_manage_mac_write *cmd;
3014 struct ice_aq_desc desc;
3015
3016 cmd = &desc.params.mac_write;
3017 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_manage_mac_write);
3018
3019 cmd->flags = flags;
3020 ether_addr_copy(cmd->mac_addr, mac_addr);
3021
3022 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
3023 }
3024
3025 /**
3026 * ice_aq_clear_pxe_mode
3027 * @hw: pointer to the HW struct
3028 *
3029 * Tell the firmware that the driver is taking over from PXE (0x0110).
3030 */
ice_aq_clear_pxe_mode(struct ice_hw * hw)3031 static int ice_aq_clear_pxe_mode(struct ice_hw *hw)
3032 {
3033 struct ice_aq_desc desc;
3034
3035 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_clear_pxe_mode);
3036 desc.params.clear_pxe.rx_cnt = ICE_AQC_CLEAR_PXE_RX_CNT;
3037
3038 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL);
3039 }
3040
3041 /**
3042 * ice_clear_pxe_mode - clear pxe operations mode
3043 * @hw: pointer to the HW struct
3044 *
3045 * Make sure all PXE mode settings are cleared, including things
3046 * like descriptor fetch/write-back mode.
3047 */
ice_clear_pxe_mode(struct ice_hw * hw)3048 void ice_clear_pxe_mode(struct ice_hw *hw)
3049 {
3050 if (ice_check_sq_alive(hw, &hw->adminq))
3051 ice_aq_clear_pxe_mode(hw);
3052 }
3053
3054 /**
3055 * ice_aq_set_port_params - set physical port parameters.
3056 * @pi: pointer to the port info struct
3057 * @double_vlan: if set double VLAN is enabled
3058 * @cd: pointer to command details structure or NULL
3059 *
3060 * Set Physical port parameters (0x0203)
3061 */
3062 int
ice_aq_set_port_params(struct ice_port_info * pi,bool double_vlan,struct ice_sq_cd * cd)3063 ice_aq_set_port_params(struct ice_port_info *pi, bool double_vlan,
3064 struct ice_sq_cd *cd)
3065
3066 {
3067 struct ice_aqc_set_port_params *cmd;
3068 struct ice_hw *hw = pi->hw;
3069 struct ice_aq_desc desc;
3070 u16 cmd_flags = 0;
3071
3072 cmd = &desc.params.set_port_params;
3073
3074 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_port_params);
3075 if (double_vlan)
3076 cmd_flags |= ICE_AQC_SET_P_PARAMS_DOUBLE_VLAN_ENA;
3077 cmd->cmd_flags = cpu_to_le16(cmd_flags);
3078
3079 cmd->local_fwd_mode = pi->local_fwd_mode |
3080 ICE_AQC_SET_P_PARAMS_LOCAL_FWD_MODE_VALID;
3081
3082 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
3083 }
3084
3085 /**
3086 * ice_is_100m_speed_supported
3087 * @hw: pointer to the HW struct
3088 *
3089 * returns true if 100M speeds are supported by the device,
3090 * false otherwise.
3091 */
ice_is_100m_speed_supported(struct ice_hw * hw)3092 bool ice_is_100m_speed_supported(struct ice_hw *hw)
3093 {
3094 switch (hw->device_id) {
3095 case ICE_DEV_ID_E822C_SGMII:
3096 case ICE_DEV_ID_E822L_SGMII:
3097 case ICE_DEV_ID_E823L_1GBE:
3098 case ICE_DEV_ID_E823C_SGMII:
3099 return true;
3100 default:
3101 return false;
3102 }
3103 }
3104
3105 /**
3106 * ice_get_link_speed_based_on_phy_type - returns link speed
3107 * @phy_type_low: lower part of phy_type
3108 * @phy_type_high: higher part of phy_type
3109 *
3110 * This helper function will convert an entry in PHY type structure
3111 * [phy_type_low, phy_type_high] to its corresponding link speed.
3112 * Note: In the structure of [phy_type_low, phy_type_high], there should
3113 * be one bit set, as this function will convert one PHY type to its
3114 * speed.
3115 *
3116 * Return:
3117 * * PHY speed for recognized PHY type
3118 * * If no bit gets set, ICE_AQ_LINK_SPEED_UNKNOWN will be returned
3119 * * If more than one bit gets set, ICE_AQ_LINK_SPEED_UNKNOWN will be returned
3120 */
ice_get_link_speed_based_on_phy_type(u64 phy_type_low,u64 phy_type_high)3121 u16 ice_get_link_speed_based_on_phy_type(u64 phy_type_low, u64 phy_type_high)
3122 {
3123 u16 speed_phy_type_high = ICE_AQ_LINK_SPEED_UNKNOWN;
3124 u16 speed_phy_type_low = ICE_AQ_LINK_SPEED_UNKNOWN;
3125
3126 switch (phy_type_low) {
3127 case ICE_PHY_TYPE_LOW_100BASE_TX:
3128 case ICE_PHY_TYPE_LOW_100M_SGMII:
3129 speed_phy_type_low = ICE_AQ_LINK_SPEED_100MB;
3130 break;
3131 case ICE_PHY_TYPE_LOW_1000BASE_T:
3132 case ICE_PHY_TYPE_LOW_1000BASE_SX:
3133 case ICE_PHY_TYPE_LOW_1000BASE_LX:
3134 case ICE_PHY_TYPE_LOW_1000BASE_KX:
3135 case ICE_PHY_TYPE_LOW_1G_SGMII:
3136 speed_phy_type_low = ICE_AQ_LINK_SPEED_1000MB;
3137 break;
3138 case ICE_PHY_TYPE_LOW_2500BASE_T:
3139 case ICE_PHY_TYPE_LOW_2500BASE_X:
3140 case ICE_PHY_TYPE_LOW_2500BASE_KX:
3141 speed_phy_type_low = ICE_AQ_LINK_SPEED_2500MB;
3142 break;
3143 case ICE_PHY_TYPE_LOW_5GBASE_T:
3144 case ICE_PHY_TYPE_LOW_5GBASE_KR:
3145 speed_phy_type_low = ICE_AQ_LINK_SPEED_5GB;
3146 break;
3147 case ICE_PHY_TYPE_LOW_10GBASE_T:
3148 case ICE_PHY_TYPE_LOW_10G_SFI_DA:
3149 case ICE_PHY_TYPE_LOW_10GBASE_SR:
3150 case ICE_PHY_TYPE_LOW_10GBASE_LR:
3151 case ICE_PHY_TYPE_LOW_10GBASE_KR_CR1:
3152 case ICE_PHY_TYPE_LOW_10G_SFI_AOC_ACC:
3153 case ICE_PHY_TYPE_LOW_10G_SFI_C2C:
3154 speed_phy_type_low = ICE_AQ_LINK_SPEED_10GB;
3155 break;
3156 case ICE_PHY_TYPE_LOW_25GBASE_T:
3157 case ICE_PHY_TYPE_LOW_25GBASE_CR:
3158 case ICE_PHY_TYPE_LOW_25GBASE_CR_S:
3159 case ICE_PHY_TYPE_LOW_25GBASE_CR1:
3160 case ICE_PHY_TYPE_LOW_25GBASE_SR:
3161 case ICE_PHY_TYPE_LOW_25GBASE_LR:
3162 case ICE_PHY_TYPE_LOW_25GBASE_KR:
3163 case ICE_PHY_TYPE_LOW_25GBASE_KR_S:
3164 case ICE_PHY_TYPE_LOW_25GBASE_KR1:
3165 case ICE_PHY_TYPE_LOW_25G_AUI_AOC_ACC:
3166 case ICE_PHY_TYPE_LOW_25G_AUI_C2C:
3167 speed_phy_type_low = ICE_AQ_LINK_SPEED_25GB;
3168 break;
3169 case ICE_PHY_TYPE_LOW_40GBASE_CR4:
3170 case ICE_PHY_TYPE_LOW_40GBASE_SR4:
3171 case ICE_PHY_TYPE_LOW_40GBASE_LR4:
3172 case ICE_PHY_TYPE_LOW_40GBASE_KR4:
3173 case ICE_PHY_TYPE_LOW_40G_XLAUI_AOC_ACC:
3174 case ICE_PHY_TYPE_LOW_40G_XLAUI:
3175 speed_phy_type_low = ICE_AQ_LINK_SPEED_40GB;
3176 break;
3177 case ICE_PHY_TYPE_LOW_50GBASE_CR2:
3178 case ICE_PHY_TYPE_LOW_50GBASE_SR2:
3179 case ICE_PHY_TYPE_LOW_50GBASE_LR2:
3180 case ICE_PHY_TYPE_LOW_50GBASE_KR2:
3181 case ICE_PHY_TYPE_LOW_50G_LAUI2_AOC_ACC:
3182 case ICE_PHY_TYPE_LOW_50G_LAUI2:
3183 case ICE_PHY_TYPE_LOW_50G_AUI2_AOC_ACC:
3184 case ICE_PHY_TYPE_LOW_50G_AUI2:
3185 case ICE_PHY_TYPE_LOW_50GBASE_CP:
3186 case ICE_PHY_TYPE_LOW_50GBASE_SR:
3187 case ICE_PHY_TYPE_LOW_50GBASE_FR:
3188 case ICE_PHY_TYPE_LOW_50GBASE_LR:
3189 case ICE_PHY_TYPE_LOW_50GBASE_KR_PAM4:
3190 case ICE_PHY_TYPE_LOW_50G_AUI1_AOC_ACC:
3191 case ICE_PHY_TYPE_LOW_50G_AUI1:
3192 speed_phy_type_low = ICE_AQ_LINK_SPEED_50GB;
3193 break;
3194 case ICE_PHY_TYPE_LOW_100GBASE_CR4:
3195 case ICE_PHY_TYPE_LOW_100GBASE_SR4:
3196 case ICE_PHY_TYPE_LOW_100GBASE_LR4:
3197 case ICE_PHY_TYPE_LOW_100GBASE_KR4:
3198 case ICE_PHY_TYPE_LOW_100G_CAUI4_AOC_ACC:
3199 case ICE_PHY_TYPE_LOW_100G_CAUI4:
3200 case ICE_PHY_TYPE_LOW_100G_AUI4_AOC_ACC:
3201 case ICE_PHY_TYPE_LOW_100G_AUI4:
3202 case ICE_PHY_TYPE_LOW_100GBASE_CR_PAM4:
3203 case ICE_PHY_TYPE_LOW_100GBASE_KR_PAM4:
3204 case ICE_PHY_TYPE_LOW_100GBASE_CP2:
3205 case ICE_PHY_TYPE_LOW_100GBASE_SR2:
3206 case ICE_PHY_TYPE_LOW_100GBASE_DR:
3207 speed_phy_type_low = ICE_AQ_LINK_SPEED_100GB;
3208 break;
3209 default:
3210 speed_phy_type_low = ICE_AQ_LINK_SPEED_UNKNOWN;
3211 break;
3212 }
3213
3214 switch (phy_type_high) {
3215 case ICE_PHY_TYPE_HIGH_100GBASE_KR2_PAM4:
3216 case ICE_PHY_TYPE_HIGH_100G_CAUI2_AOC_ACC:
3217 case ICE_PHY_TYPE_HIGH_100G_CAUI2:
3218 case ICE_PHY_TYPE_HIGH_100G_AUI2_AOC_ACC:
3219 case ICE_PHY_TYPE_HIGH_100G_AUI2:
3220 speed_phy_type_high = ICE_AQ_LINK_SPEED_100GB;
3221 break;
3222 case ICE_PHY_TYPE_HIGH_200G_CR4_PAM4:
3223 case ICE_PHY_TYPE_HIGH_200G_SR4:
3224 case ICE_PHY_TYPE_HIGH_200G_FR4:
3225 case ICE_PHY_TYPE_HIGH_200G_LR4:
3226 case ICE_PHY_TYPE_HIGH_200G_DR4:
3227 case ICE_PHY_TYPE_HIGH_200G_KR4_PAM4:
3228 case ICE_PHY_TYPE_HIGH_200G_AUI4_AOC_ACC:
3229 case ICE_PHY_TYPE_HIGH_200G_AUI4:
3230 speed_phy_type_high = ICE_AQ_LINK_SPEED_200GB;
3231 break;
3232 default:
3233 speed_phy_type_high = ICE_AQ_LINK_SPEED_UNKNOWN;
3234 break;
3235 }
3236
3237 if (speed_phy_type_low == ICE_AQ_LINK_SPEED_UNKNOWN &&
3238 speed_phy_type_high == ICE_AQ_LINK_SPEED_UNKNOWN)
3239 return ICE_AQ_LINK_SPEED_UNKNOWN;
3240 else if (speed_phy_type_low != ICE_AQ_LINK_SPEED_UNKNOWN &&
3241 speed_phy_type_high != ICE_AQ_LINK_SPEED_UNKNOWN)
3242 return ICE_AQ_LINK_SPEED_UNKNOWN;
3243 else if (speed_phy_type_low != ICE_AQ_LINK_SPEED_UNKNOWN &&
3244 speed_phy_type_high == ICE_AQ_LINK_SPEED_UNKNOWN)
3245 return speed_phy_type_low;
3246 else
3247 return speed_phy_type_high;
3248 }
3249
3250 /**
3251 * ice_update_phy_type
3252 * @phy_type_low: pointer to the lower part of phy_type
3253 * @phy_type_high: pointer to the higher part of phy_type
3254 * @link_speeds_bitmap: targeted link speeds bitmap
3255 *
3256 * Note: For the link_speeds_bitmap structure, you can check it at
3257 * [ice_aqc_get_link_status->link_speed]. Caller can pass in
3258 * link_speeds_bitmap include multiple speeds.
3259 *
3260 * Each entry in this [phy_type_low, phy_type_high] structure will
3261 * present a certain link speed. This helper function will turn on bits
3262 * in [phy_type_low, phy_type_high] structure based on the value of
3263 * link_speeds_bitmap input parameter.
3264 */
3265 void
ice_update_phy_type(u64 * phy_type_low,u64 * phy_type_high,u16 link_speeds_bitmap)3266 ice_update_phy_type(u64 *phy_type_low, u64 *phy_type_high,
3267 u16 link_speeds_bitmap)
3268 {
3269 u64 pt_high;
3270 u64 pt_low;
3271 int index;
3272 u16 speed;
3273
3274 /* We first check with low part of phy_type */
3275 for (index = 0; index <= ICE_PHY_TYPE_LOW_MAX_INDEX; index++) {
3276 pt_low = BIT_ULL(index);
3277 speed = ice_get_link_speed_based_on_phy_type(pt_low, 0);
3278
3279 if (link_speeds_bitmap & speed)
3280 *phy_type_low |= BIT_ULL(index);
3281 }
3282
3283 /* We then check with high part of phy_type */
3284 for (index = 0; index <= ICE_PHY_TYPE_HIGH_MAX_INDEX; index++) {
3285 pt_high = BIT_ULL(index);
3286 speed = ice_get_link_speed_based_on_phy_type(0, pt_high);
3287
3288 if (link_speeds_bitmap & speed)
3289 *phy_type_high |= BIT_ULL(index);
3290 }
3291 }
3292
3293 /**
3294 * ice_aq_set_phy_cfg
3295 * @hw: pointer to the HW struct
3296 * @pi: port info structure of the interested logical port
3297 * @cfg: structure with PHY configuration data to be set
3298 * @cd: pointer to command details structure or NULL
3299 *
3300 * Set the various PHY configuration parameters supported on the Port.
3301 * One or more of the Set PHY config parameters may be ignored in an MFP
3302 * mode as the PF may not have the privilege to set some of the PHY Config
3303 * parameters. This status will be indicated by the command response (0x0601).
3304 */
3305 int
ice_aq_set_phy_cfg(struct ice_hw * hw,struct ice_port_info * pi,struct ice_aqc_set_phy_cfg_data * cfg,struct ice_sq_cd * cd)3306 ice_aq_set_phy_cfg(struct ice_hw *hw, struct ice_port_info *pi,
3307 struct ice_aqc_set_phy_cfg_data *cfg, struct ice_sq_cd *cd)
3308 {
3309 struct ice_aq_desc desc;
3310 int status;
3311
3312 if (!cfg)
3313 return -EINVAL;
3314
3315 /* Ensure that only valid bits of cfg->caps can be turned on. */
3316 if (cfg->caps & ~ICE_AQ_PHY_ENA_VALID_MASK) {
3317 ice_debug(hw, ICE_DBG_PHY, "Invalid bit is set in ice_aqc_set_phy_cfg_data->caps : 0x%x\n",
3318 cfg->caps);
3319
3320 cfg->caps &= ICE_AQ_PHY_ENA_VALID_MASK;
3321 }
3322
3323 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_phy_cfg);
3324 desc.params.set_phy.lport_num = pi->lport;
3325 desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD);
3326
3327 ice_debug(hw, ICE_DBG_LINK, "set phy cfg\n");
3328 ice_debug(hw, ICE_DBG_LINK, " phy_type_low = 0x%llx\n",
3329 (unsigned long long)le64_to_cpu(cfg->phy_type_low));
3330 ice_debug(hw, ICE_DBG_LINK, " phy_type_high = 0x%llx\n",
3331 (unsigned long long)le64_to_cpu(cfg->phy_type_high));
3332 ice_debug(hw, ICE_DBG_LINK, " caps = 0x%x\n", cfg->caps);
3333 ice_debug(hw, ICE_DBG_LINK, " low_power_ctrl_an = 0x%x\n",
3334 cfg->low_power_ctrl_an);
3335 ice_debug(hw, ICE_DBG_LINK, " eee_cap = 0x%x\n", cfg->eee_cap);
3336 ice_debug(hw, ICE_DBG_LINK, " eeer_value = 0x%x\n", cfg->eeer_value);
3337 ice_debug(hw, ICE_DBG_LINK, " link_fec_opt = 0x%x\n",
3338 cfg->link_fec_opt);
3339
3340 status = ice_aq_send_cmd(hw, &desc, cfg, sizeof(*cfg), cd);
3341 if (hw->adminq.sq_last_status == ICE_AQ_RC_EMODE)
3342 status = 0;
3343
3344 if (!status)
3345 pi->phy.curr_user_phy_cfg = *cfg;
3346
3347 return status;
3348 }
3349
3350 /**
3351 * ice_update_link_info - update status of the HW network link
3352 * @pi: port info structure of the interested logical port
3353 */
ice_update_link_info(struct ice_port_info * pi)3354 int ice_update_link_info(struct ice_port_info *pi)
3355 {
3356 struct ice_link_status *li;
3357 int status;
3358
3359 if (!pi)
3360 return -EINVAL;
3361
3362 li = &pi->phy.link_info;
3363
3364 status = ice_aq_get_link_info(pi, true, NULL, NULL);
3365 if (status)
3366 return status;
3367
3368 if (li->link_info & ICE_AQ_MEDIA_AVAILABLE) {
3369 struct ice_aqc_get_phy_caps_data *pcaps __free(kfree) = NULL;
3370
3371 pcaps = kzalloc(sizeof(*pcaps), GFP_KERNEL);
3372 if (!pcaps)
3373 return -ENOMEM;
3374
3375 status = ice_aq_get_phy_caps(pi, false, ICE_AQC_REPORT_TOPO_CAP_MEDIA,
3376 pcaps, NULL);
3377 }
3378
3379 return status;
3380 }
3381
3382 /**
3383 * ice_aq_get_phy_equalization - function to read serdes equaliser
3384 * value from firmware using admin queue command.
3385 * @hw: pointer to the HW struct
3386 * @data_in: represents the serdes equalization parameter requested
3387 * @op_code: represents the serdes number and flag to represent tx or rx
3388 * @serdes_num: represents the serdes number
3389 * @output: pointer to the caller-supplied buffer to return serdes equaliser
3390 *
3391 * Return: non-zero status on error and 0 on success.
3392 */
ice_aq_get_phy_equalization(struct ice_hw * hw,u16 data_in,u16 op_code,u8 serdes_num,int * output)3393 int ice_aq_get_phy_equalization(struct ice_hw *hw, u16 data_in, u16 op_code,
3394 u8 serdes_num, int *output)
3395 {
3396 struct ice_aqc_dnl_call_command *cmd;
3397 struct ice_aqc_dnl_call buf = {};
3398 struct ice_aq_desc desc;
3399 int err;
3400
3401 buf.sto.txrx_equa_reqs.data_in = cpu_to_le16(data_in);
3402 buf.sto.txrx_equa_reqs.op_code_serdes_sel =
3403 cpu_to_le16(op_code | (serdes_num & 0xF));
3404 cmd = &desc.params.dnl_call;
3405 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_dnl_call);
3406 desc.flags |= cpu_to_le16(ICE_AQ_FLAG_BUF |
3407 ICE_AQ_FLAG_RD |
3408 ICE_AQ_FLAG_SI);
3409 desc.datalen = cpu_to_le16(sizeof(struct ice_aqc_dnl_call));
3410 cmd->activity_id = cpu_to_le16(ICE_AQC_ACT_ID_DNL);
3411
3412 err = ice_aq_send_cmd(hw, &desc, &buf, sizeof(struct ice_aqc_dnl_call),
3413 NULL);
3414 *output = err ? 0 : buf.sto.txrx_equa_resp.val;
3415
3416 return err;
3417 }
3418
3419 #define FEC_REG_PORT(port) { \
3420 FEC_CORR_LOW_REG_PORT##port, \
3421 FEC_CORR_HIGH_REG_PORT##port, \
3422 FEC_UNCORR_LOW_REG_PORT##port, \
3423 FEC_UNCORR_HIGH_REG_PORT##port, \
3424 }
3425
3426 static const u32 fec_reg[][ICE_FEC_MAX] = {
3427 FEC_REG_PORT(0),
3428 FEC_REG_PORT(1),
3429 FEC_REG_PORT(2),
3430 FEC_REG_PORT(3)
3431 };
3432
3433 /**
3434 * ice_aq_get_fec_stats - reads fec stats from phy
3435 * @hw: pointer to the HW struct
3436 * @pcs_quad: represents pcsquad of user input serdes
3437 * @pcs_port: represents the pcs port number part of above pcs quad
3438 * @fec_type: represents FEC stats type
3439 * @output: pointer to the caller-supplied buffer to return requested fec stats
3440 *
3441 * Return: non-zero status on error and 0 on success.
3442 */
ice_aq_get_fec_stats(struct ice_hw * hw,u16 pcs_quad,u16 pcs_port,enum ice_fec_stats_types fec_type,u32 * output)3443 int ice_aq_get_fec_stats(struct ice_hw *hw, u16 pcs_quad, u16 pcs_port,
3444 enum ice_fec_stats_types fec_type, u32 *output)
3445 {
3446 u16 flag = (ICE_AQ_FLAG_RD | ICE_AQ_FLAG_BUF | ICE_AQ_FLAG_SI);
3447 struct ice_sbq_msg_input msg = {};
3448 u32 receiver_id, reg_offset;
3449 int err;
3450
3451 if (pcs_port > 3)
3452 return -EINVAL;
3453
3454 reg_offset = fec_reg[pcs_port][fec_type];
3455
3456 if (pcs_quad == 0)
3457 receiver_id = FEC_RECEIVER_ID_PCS0;
3458 else if (pcs_quad == 1)
3459 receiver_id = FEC_RECEIVER_ID_PCS1;
3460 else
3461 return -EINVAL;
3462
3463 msg.msg_addr_low = lower_16_bits(reg_offset);
3464 msg.msg_addr_high = receiver_id;
3465 msg.opcode = ice_sbq_msg_rd;
3466 msg.dest_dev = rmn_0;
3467
3468 err = ice_sbq_rw_reg(hw, &msg, flag);
3469 if (err)
3470 return err;
3471
3472 *output = msg.data;
3473 return 0;
3474 }
3475
3476 /**
3477 * ice_cache_phy_user_req
3478 * @pi: port information structure
3479 * @cache_data: PHY logging data
3480 * @cache_mode: PHY logging mode
3481 *
3482 * Log the user request on (FC, FEC, SPEED) for later use.
3483 */
3484 static void
ice_cache_phy_user_req(struct ice_port_info * pi,struct ice_phy_cache_mode_data cache_data,enum ice_phy_cache_mode cache_mode)3485 ice_cache_phy_user_req(struct ice_port_info *pi,
3486 struct ice_phy_cache_mode_data cache_data,
3487 enum ice_phy_cache_mode cache_mode)
3488 {
3489 if (!pi)
3490 return;
3491
3492 switch (cache_mode) {
3493 case ICE_FC_MODE:
3494 pi->phy.curr_user_fc_req = cache_data.data.curr_user_fc_req;
3495 break;
3496 case ICE_SPEED_MODE:
3497 pi->phy.curr_user_speed_req =
3498 cache_data.data.curr_user_speed_req;
3499 break;
3500 case ICE_FEC_MODE:
3501 pi->phy.curr_user_fec_req = cache_data.data.curr_user_fec_req;
3502 break;
3503 default:
3504 break;
3505 }
3506 }
3507
3508 /**
3509 * ice_caps_to_fc_mode
3510 * @caps: PHY capabilities
3511 *
3512 * Convert PHY FC capabilities to ice FC mode
3513 */
ice_caps_to_fc_mode(u8 caps)3514 enum ice_fc_mode ice_caps_to_fc_mode(u8 caps)
3515 {
3516 if (caps & ICE_AQC_PHY_EN_TX_LINK_PAUSE &&
3517 caps & ICE_AQC_PHY_EN_RX_LINK_PAUSE)
3518 return ICE_FC_FULL;
3519
3520 if (caps & ICE_AQC_PHY_EN_TX_LINK_PAUSE)
3521 return ICE_FC_TX_PAUSE;
3522
3523 if (caps & ICE_AQC_PHY_EN_RX_LINK_PAUSE)
3524 return ICE_FC_RX_PAUSE;
3525
3526 return ICE_FC_NONE;
3527 }
3528
3529 /**
3530 * ice_caps_to_fec_mode
3531 * @caps: PHY capabilities
3532 * @fec_options: Link FEC options
3533 *
3534 * Convert PHY FEC capabilities to ice FEC mode
3535 */
ice_caps_to_fec_mode(u8 caps,u8 fec_options)3536 enum ice_fec_mode ice_caps_to_fec_mode(u8 caps, u8 fec_options)
3537 {
3538 if (caps & ICE_AQC_PHY_EN_AUTO_FEC)
3539 return ICE_FEC_AUTO;
3540
3541 if (fec_options & (ICE_AQC_PHY_FEC_10G_KR_40G_KR4_EN |
3542 ICE_AQC_PHY_FEC_10G_KR_40G_KR4_REQ |
3543 ICE_AQC_PHY_FEC_25G_KR_CLAUSE74_EN |
3544 ICE_AQC_PHY_FEC_25G_KR_REQ))
3545 return ICE_FEC_BASER;
3546
3547 if (fec_options & (ICE_AQC_PHY_FEC_25G_RS_528_REQ |
3548 ICE_AQC_PHY_FEC_25G_RS_544_REQ |
3549 ICE_AQC_PHY_FEC_25G_RS_CLAUSE91_EN))
3550 return ICE_FEC_RS;
3551
3552 return ICE_FEC_NONE;
3553 }
3554
3555 /**
3556 * ice_cfg_phy_fc - Configure PHY FC data based on FC mode
3557 * @pi: port information structure
3558 * @cfg: PHY configuration data to set FC mode
3559 * @req_mode: FC mode to configure
3560 */
3561 int
ice_cfg_phy_fc(struct ice_port_info * pi,struct ice_aqc_set_phy_cfg_data * cfg,enum ice_fc_mode req_mode)3562 ice_cfg_phy_fc(struct ice_port_info *pi, struct ice_aqc_set_phy_cfg_data *cfg,
3563 enum ice_fc_mode req_mode)
3564 {
3565 struct ice_phy_cache_mode_data cache_data;
3566 u8 pause_mask = 0x0;
3567
3568 if (!pi || !cfg)
3569 return -EINVAL;
3570
3571 switch (req_mode) {
3572 case ICE_FC_FULL:
3573 pause_mask |= ICE_AQC_PHY_EN_TX_LINK_PAUSE;
3574 pause_mask |= ICE_AQC_PHY_EN_RX_LINK_PAUSE;
3575 break;
3576 case ICE_FC_RX_PAUSE:
3577 pause_mask |= ICE_AQC_PHY_EN_RX_LINK_PAUSE;
3578 break;
3579 case ICE_FC_TX_PAUSE:
3580 pause_mask |= ICE_AQC_PHY_EN_TX_LINK_PAUSE;
3581 break;
3582 default:
3583 break;
3584 }
3585
3586 /* clear the old pause settings */
3587 cfg->caps &= ~(ICE_AQC_PHY_EN_TX_LINK_PAUSE |
3588 ICE_AQC_PHY_EN_RX_LINK_PAUSE);
3589
3590 /* set the new capabilities */
3591 cfg->caps |= pause_mask;
3592
3593 /* Cache user FC request */
3594 cache_data.data.curr_user_fc_req = req_mode;
3595 ice_cache_phy_user_req(pi, cache_data, ICE_FC_MODE);
3596
3597 return 0;
3598 }
3599
3600 /**
3601 * ice_set_fc
3602 * @pi: port information structure
3603 * @aq_failures: pointer to status code, specific to ice_set_fc routine
3604 * @ena_auto_link_update: enable automatic link update
3605 *
3606 * Set the requested flow control mode.
3607 */
3608 int
ice_set_fc(struct ice_port_info * pi,u8 * aq_failures,bool ena_auto_link_update)3609 ice_set_fc(struct ice_port_info *pi, u8 *aq_failures, bool ena_auto_link_update)
3610 {
3611 struct ice_aqc_get_phy_caps_data *pcaps __free(kfree) = NULL;
3612 struct ice_aqc_set_phy_cfg_data cfg = { 0 };
3613 struct ice_hw *hw;
3614 int status;
3615
3616 if (!pi || !aq_failures)
3617 return -EINVAL;
3618
3619 *aq_failures = 0;
3620 hw = pi->hw;
3621
3622 pcaps = kzalloc(sizeof(*pcaps), GFP_KERNEL);
3623 if (!pcaps)
3624 return -ENOMEM;
3625
3626 /* Get the current PHY config */
3627 status = ice_aq_get_phy_caps(pi, false, ICE_AQC_REPORT_ACTIVE_CFG,
3628 pcaps, NULL);
3629 if (status) {
3630 *aq_failures = ICE_SET_FC_AQ_FAIL_GET;
3631 goto out;
3632 }
3633
3634 ice_copy_phy_caps_to_cfg(pi, pcaps, &cfg);
3635
3636 /* Configure the set PHY data */
3637 status = ice_cfg_phy_fc(pi, &cfg, pi->fc.req_mode);
3638 if (status)
3639 goto out;
3640
3641 /* If the capabilities have changed, then set the new config */
3642 if (cfg.caps != pcaps->caps) {
3643 int retry_count, retry_max = 10;
3644
3645 /* Auto restart link so settings take effect */
3646 if (ena_auto_link_update)
3647 cfg.caps |= ICE_AQ_PHY_ENA_AUTO_LINK_UPDT;
3648
3649 status = ice_aq_set_phy_cfg(hw, pi, &cfg, NULL);
3650 if (status) {
3651 *aq_failures = ICE_SET_FC_AQ_FAIL_SET;
3652 goto out;
3653 }
3654
3655 /* Update the link info
3656 * It sometimes takes a really long time for link to
3657 * come back from the atomic reset. Thus, we wait a
3658 * little bit.
3659 */
3660 for (retry_count = 0; retry_count < retry_max; retry_count++) {
3661 status = ice_update_link_info(pi);
3662
3663 if (!status)
3664 break;
3665
3666 mdelay(100);
3667 }
3668
3669 if (status)
3670 *aq_failures = ICE_SET_FC_AQ_FAIL_UPDATE;
3671 }
3672
3673 out:
3674 return status;
3675 }
3676
3677 /**
3678 * ice_phy_caps_equals_cfg
3679 * @phy_caps: PHY capabilities
3680 * @phy_cfg: PHY configuration
3681 *
3682 * Helper function to determine if PHY capabilities matches PHY
3683 * configuration
3684 */
3685 bool
ice_phy_caps_equals_cfg(struct ice_aqc_get_phy_caps_data * phy_caps,struct ice_aqc_set_phy_cfg_data * phy_cfg)3686 ice_phy_caps_equals_cfg(struct ice_aqc_get_phy_caps_data *phy_caps,
3687 struct ice_aqc_set_phy_cfg_data *phy_cfg)
3688 {
3689 u8 caps_mask, cfg_mask;
3690
3691 if (!phy_caps || !phy_cfg)
3692 return false;
3693
3694 /* These bits are not common between capabilities and configuration.
3695 * Do not use them to determine equality.
3696 */
3697 caps_mask = ICE_AQC_PHY_CAPS_MASK & ~(ICE_AQC_PHY_AN_MODE |
3698 ICE_AQC_GET_PHY_EN_MOD_QUAL);
3699 cfg_mask = ICE_AQ_PHY_ENA_VALID_MASK & ~ICE_AQ_PHY_ENA_AUTO_LINK_UPDT;
3700
3701 if (phy_caps->phy_type_low != phy_cfg->phy_type_low ||
3702 phy_caps->phy_type_high != phy_cfg->phy_type_high ||
3703 ((phy_caps->caps & caps_mask) != (phy_cfg->caps & cfg_mask)) ||
3704 phy_caps->low_power_ctrl_an != phy_cfg->low_power_ctrl_an ||
3705 phy_caps->eee_cap != phy_cfg->eee_cap ||
3706 phy_caps->eeer_value != phy_cfg->eeer_value ||
3707 phy_caps->link_fec_options != phy_cfg->link_fec_opt)
3708 return false;
3709
3710 return true;
3711 }
3712
3713 /**
3714 * ice_copy_phy_caps_to_cfg - Copy PHY ability data to configuration data
3715 * @pi: port information structure
3716 * @caps: PHY ability structure to copy date from
3717 * @cfg: PHY configuration structure to copy data to
3718 *
3719 * Helper function to copy AQC PHY get ability data to PHY set configuration
3720 * data structure
3721 */
3722 void
ice_copy_phy_caps_to_cfg(struct ice_port_info * pi,struct ice_aqc_get_phy_caps_data * caps,struct ice_aqc_set_phy_cfg_data * cfg)3723 ice_copy_phy_caps_to_cfg(struct ice_port_info *pi,
3724 struct ice_aqc_get_phy_caps_data *caps,
3725 struct ice_aqc_set_phy_cfg_data *cfg)
3726 {
3727 if (!pi || !caps || !cfg)
3728 return;
3729
3730 memset(cfg, 0, sizeof(*cfg));
3731 cfg->phy_type_low = caps->phy_type_low;
3732 cfg->phy_type_high = caps->phy_type_high;
3733 cfg->caps = caps->caps;
3734 cfg->low_power_ctrl_an = caps->low_power_ctrl_an;
3735 cfg->eee_cap = caps->eee_cap;
3736 cfg->eeer_value = caps->eeer_value;
3737 cfg->link_fec_opt = caps->link_fec_options;
3738 cfg->module_compliance_enforcement =
3739 caps->module_compliance_enforcement;
3740 }
3741
3742 /**
3743 * ice_cfg_phy_fec - Configure PHY FEC data based on FEC mode
3744 * @pi: port information structure
3745 * @cfg: PHY configuration data to set FEC mode
3746 * @fec: FEC mode to configure
3747 */
3748 int
ice_cfg_phy_fec(struct ice_port_info * pi,struct ice_aqc_set_phy_cfg_data * cfg,enum ice_fec_mode fec)3749 ice_cfg_phy_fec(struct ice_port_info *pi, struct ice_aqc_set_phy_cfg_data *cfg,
3750 enum ice_fec_mode fec)
3751 {
3752 struct ice_aqc_get_phy_caps_data *pcaps __free(kfree) = NULL;
3753 struct ice_hw *hw;
3754 int status;
3755
3756 if (!pi || !cfg)
3757 return -EINVAL;
3758
3759 hw = pi->hw;
3760
3761 pcaps = kzalloc(sizeof(*pcaps), GFP_KERNEL);
3762 if (!pcaps)
3763 return -ENOMEM;
3764
3765 status = ice_aq_get_phy_caps(pi, false,
3766 (ice_fw_supports_report_dflt_cfg(hw) ?
3767 ICE_AQC_REPORT_DFLT_CFG :
3768 ICE_AQC_REPORT_TOPO_CAP_MEDIA), pcaps, NULL);
3769 if (status)
3770 goto out;
3771
3772 cfg->caps |= pcaps->caps & ICE_AQC_PHY_EN_AUTO_FEC;
3773 cfg->link_fec_opt = pcaps->link_fec_options;
3774
3775 switch (fec) {
3776 case ICE_FEC_BASER:
3777 /* Clear RS bits, and AND BASE-R ability
3778 * bits and OR request bits.
3779 */
3780 cfg->link_fec_opt &= ICE_AQC_PHY_FEC_10G_KR_40G_KR4_EN |
3781 ICE_AQC_PHY_FEC_25G_KR_CLAUSE74_EN;
3782 cfg->link_fec_opt |= ICE_AQC_PHY_FEC_10G_KR_40G_KR4_REQ |
3783 ICE_AQC_PHY_FEC_25G_KR_REQ;
3784 break;
3785 case ICE_FEC_RS:
3786 /* Clear BASE-R bits, and AND RS ability
3787 * bits and OR request bits.
3788 */
3789 cfg->link_fec_opt &= ICE_AQC_PHY_FEC_25G_RS_CLAUSE91_EN;
3790 cfg->link_fec_opt |= ICE_AQC_PHY_FEC_25G_RS_528_REQ |
3791 ICE_AQC_PHY_FEC_25G_RS_544_REQ;
3792 break;
3793 case ICE_FEC_NONE:
3794 /* Clear all FEC option bits. */
3795 cfg->link_fec_opt &= ~ICE_AQC_PHY_FEC_MASK;
3796 break;
3797 case ICE_FEC_AUTO:
3798 /* AND auto FEC bit, and all caps bits. */
3799 cfg->caps &= ICE_AQC_PHY_CAPS_MASK;
3800 cfg->link_fec_opt |= pcaps->link_fec_options;
3801 break;
3802 default:
3803 status = -EINVAL;
3804 break;
3805 }
3806
3807 if (fec == ICE_FEC_AUTO && ice_fw_supports_link_override(hw) &&
3808 !ice_fw_supports_report_dflt_cfg(hw)) {
3809 struct ice_link_default_override_tlv tlv = { 0 };
3810
3811 status = ice_get_link_default_override(&tlv, pi);
3812 if (status)
3813 goto out;
3814
3815 if (!(tlv.options & ICE_LINK_OVERRIDE_STRICT_MODE) &&
3816 (tlv.options & ICE_LINK_OVERRIDE_EN))
3817 cfg->link_fec_opt = tlv.fec_options;
3818 }
3819
3820 out:
3821 return status;
3822 }
3823
3824 /**
3825 * ice_get_link_status - get status of the HW network link
3826 * @pi: port information structure
3827 * @link_up: pointer to bool (true/false = linkup/linkdown)
3828 *
3829 * Variable link_up is true if link is up, false if link is down.
3830 * The variable link_up is invalid if status is non zero. As a
3831 * result of this call, link status reporting becomes enabled
3832 */
ice_get_link_status(struct ice_port_info * pi,bool * link_up)3833 int ice_get_link_status(struct ice_port_info *pi, bool *link_up)
3834 {
3835 struct ice_phy_info *phy_info;
3836 int status = 0;
3837
3838 if (!pi || !link_up)
3839 return -EINVAL;
3840
3841 phy_info = &pi->phy;
3842
3843 if (phy_info->get_link_info) {
3844 status = ice_update_link_info(pi);
3845
3846 if (status)
3847 ice_debug(pi->hw, ICE_DBG_LINK, "get link status error, status = %d\n",
3848 status);
3849 }
3850
3851 *link_up = phy_info->link_info.link_info & ICE_AQ_LINK_UP;
3852
3853 return status;
3854 }
3855
3856 /**
3857 * ice_aq_set_link_restart_an
3858 * @pi: pointer to the port information structure
3859 * @ena_link: if true: enable link, if false: disable link
3860 * @cd: pointer to command details structure or NULL
3861 *
3862 * Sets up the link and restarts the Auto-Negotiation over the link.
3863 */
3864 int
ice_aq_set_link_restart_an(struct ice_port_info * pi,bool ena_link,struct ice_sq_cd * cd)3865 ice_aq_set_link_restart_an(struct ice_port_info *pi, bool ena_link,
3866 struct ice_sq_cd *cd)
3867 {
3868 struct ice_aqc_restart_an *cmd;
3869 struct ice_aq_desc desc;
3870
3871 cmd = &desc.params.restart_an;
3872
3873 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_restart_an);
3874
3875 cmd->cmd_flags = ICE_AQC_RESTART_AN_LINK_RESTART;
3876 cmd->lport_num = pi->lport;
3877 if (ena_link)
3878 cmd->cmd_flags |= ICE_AQC_RESTART_AN_LINK_ENABLE;
3879 else
3880 cmd->cmd_flags &= ~ICE_AQC_RESTART_AN_LINK_ENABLE;
3881
3882 return ice_aq_send_cmd(pi->hw, &desc, NULL, 0, cd);
3883 }
3884
3885 /**
3886 * ice_aq_set_event_mask
3887 * @hw: pointer to the HW struct
3888 * @port_num: port number of the physical function
3889 * @mask: event mask to be set
3890 * @cd: pointer to command details structure or NULL
3891 *
3892 * Set event mask (0x0613)
3893 */
3894 int
ice_aq_set_event_mask(struct ice_hw * hw,u8 port_num,u16 mask,struct ice_sq_cd * cd)3895 ice_aq_set_event_mask(struct ice_hw *hw, u8 port_num, u16 mask,
3896 struct ice_sq_cd *cd)
3897 {
3898 struct ice_aqc_set_event_mask *cmd;
3899 struct ice_aq_desc desc;
3900
3901 cmd = &desc.params.set_event_mask;
3902
3903 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_event_mask);
3904
3905 cmd->lport_num = port_num;
3906
3907 cmd->event_mask = cpu_to_le16(mask);
3908 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
3909 }
3910
3911 /**
3912 * ice_aq_set_mac_loopback
3913 * @hw: pointer to the HW struct
3914 * @ena_lpbk: Enable or Disable loopback
3915 * @cd: pointer to command details structure or NULL
3916 *
3917 * Enable/disable loopback on a given port
3918 */
3919 int
ice_aq_set_mac_loopback(struct ice_hw * hw,bool ena_lpbk,struct ice_sq_cd * cd)3920 ice_aq_set_mac_loopback(struct ice_hw *hw, bool ena_lpbk, struct ice_sq_cd *cd)
3921 {
3922 struct ice_aqc_set_mac_lb *cmd;
3923 struct ice_aq_desc desc;
3924
3925 cmd = &desc.params.set_mac_lb;
3926
3927 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_mac_lb);
3928 if (ena_lpbk)
3929 cmd->lb_mode = ICE_AQ_MAC_LB_EN;
3930
3931 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
3932 }
3933
3934 /**
3935 * ice_aq_set_port_id_led
3936 * @pi: pointer to the port information
3937 * @is_orig_mode: is this LED set to original mode (by the net-list)
3938 * @cd: pointer to command details structure or NULL
3939 *
3940 * Set LED value for the given port (0x06e9)
3941 */
3942 int
ice_aq_set_port_id_led(struct ice_port_info * pi,bool is_orig_mode,struct ice_sq_cd * cd)3943 ice_aq_set_port_id_led(struct ice_port_info *pi, bool is_orig_mode,
3944 struct ice_sq_cd *cd)
3945 {
3946 struct ice_aqc_set_port_id_led *cmd;
3947 struct ice_hw *hw = pi->hw;
3948 struct ice_aq_desc desc;
3949
3950 cmd = &desc.params.set_port_id_led;
3951
3952 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_port_id_led);
3953
3954 if (is_orig_mode)
3955 cmd->ident_mode = ICE_AQC_PORT_IDENT_LED_ORIG;
3956 else
3957 cmd->ident_mode = ICE_AQC_PORT_IDENT_LED_BLINK;
3958
3959 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
3960 }
3961
3962 /**
3963 * ice_aq_get_port_options
3964 * @hw: pointer to the HW struct
3965 * @options: buffer for the resultant port options
3966 * @option_count: input - size of the buffer in port options structures,
3967 * output - number of returned port options
3968 * @lport: logical port to call the command with (optional)
3969 * @lport_valid: when false, FW uses port owned by the PF instead of lport,
3970 * when PF owns more than 1 port it must be true
3971 * @active_option_idx: index of active port option in returned buffer
3972 * @active_option_valid: active option in returned buffer is valid
3973 * @pending_option_idx: index of pending port option in returned buffer
3974 * @pending_option_valid: pending option in returned buffer is valid
3975 *
3976 * Calls Get Port Options AQC (0x06ea) and verifies result.
3977 */
3978 int
ice_aq_get_port_options(struct ice_hw * hw,struct ice_aqc_get_port_options_elem * options,u8 * option_count,u8 lport,bool lport_valid,u8 * active_option_idx,bool * active_option_valid,u8 * pending_option_idx,bool * pending_option_valid)3979 ice_aq_get_port_options(struct ice_hw *hw,
3980 struct ice_aqc_get_port_options_elem *options,
3981 u8 *option_count, u8 lport, bool lport_valid,
3982 u8 *active_option_idx, bool *active_option_valid,
3983 u8 *pending_option_idx, bool *pending_option_valid)
3984 {
3985 struct ice_aqc_get_port_options *cmd;
3986 struct ice_aq_desc desc;
3987 int status;
3988 u8 i;
3989
3990 /* options buffer shall be able to hold max returned options */
3991 if (*option_count < ICE_AQC_PORT_OPT_COUNT_M)
3992 return -EINVAL;
3993
3994 cmd = &desc.params.get_port_options;
3995 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_port_options);
3996
3997 if (lport_valid)
3998 cmd->lport_num = lport;
3999 cmd->lport_num_valid = lport_valid;
4000
4001 status = ice_aq_send_cmd(hw, &desc, options,
4002 *option_count * sizeof(*options), NULL);
4003 if (status)
4004 return status;
4005
4006 /* verify direct FW response & set output parameters */
4007 *option_count = FIELD_GET(ICE_AQC_PORT_OPT_COUNT_M,
4008 cmd->port_options_count);
4009 ice_debug(hw, ICE_DBG_PHY, "options: %x\n", *option_count);
4010 *active_option_valid = FIELD_GET(ICE_AQC_PORT_OPT_VALID,
4011 cmd->port_options);
4012 if (*active_option_valid) {
4013 *active_option_idx = FIELD_GET(ICE_AQC_PORT_OPT_ACTIVE_M,
4014 cmd->port_options);
4015 if (*active_option_idx > (*option_count - 1))
4016 return -EIO;
4017 ice_debug(hw, ICE_DBG_PHY, "active idx: %x\n",
4018 *active_option_idx);
4019 }
4020
4021 *pending_option_valid = FIELD_GET(ICE_AQC_PENDING_PORT_OPT_VALID,
4022 cmd->pending_port_option_status);
4023 if (*pending_option_valid) {
4024 *pending_option_idx = FIELD_GET(ICE_AQC_PENDING_PORT_OPT_IDX_M,
4025 cmd->pending_port_option_status);
4026 if (*pending_option_idx > (*option_count - 1))
4027 return -EIO;
4028 ice_debug(hw, ICE_DBG_PHY, "pending idx: %x\n",
4029 *pending_option_idx);
4030 }
4031
4032 /* mask output options fields */
4033 for (i = 0; i < *option_count; i++) {
4034 options[i].pmd = FIELD_GET(ICE_AQC_PORT_OPT_PMD_COUNT_M,
4035 options[i].pmd);
4036 options[i].max_lane_speed = FIELD_GET(ICE_AQC_PORT_OPT_MAX_LANE_M,
4037 options[i].max_lane_speed);
4038 ice_debug(hw, ICE_DBG_PHY, "pmds: %x max speed: %x\n",
4039 options[i].pmd, options[i].max_lane_speed);
4040 }
4041
4042 return 0;
4043 }
4044
4045 /**
4046 * ice_aq_set_port_option
4047 * @hw: pointer to the HW struct
4048 * @lport: logical port to call the command with
4049 * @lport_valid: when false, FW uses port owned by the PF instead of lport,
4050 * when PF owns more than 1 port it must be true
4051 * @new_option: new port option to be written
4052 *
4053 * Calls Set Port Options AQC (0x06eb).
4054 */
4055 int
ice_aq_set_port_option(struct ice_hw * hw,u8 lport,u8 lport_valid,u8 new_option)4056 ice_aq_set_port_option(struct ice_hw *hw, u8 lport, u8 lport_valid,
4057 u8 new_option)
4058 {
4059 struct ice_aqc_set_port_option *cmd;
4060 struct ice_aq_desc desc;
4061
4062 if (new_option > ICE_AQC_PORT_OPT_COUNT_M)
4063 return -EINVAL;
4064
4065 cmd = &desc.params.set_port_option;
4066 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_port_option);
4067
4068 if (lport_valid)
4069 cmd->lport_num = lport;
4070
4071 cmd->lport_num_valid = lport_valid;
4072 cmd->selected_port_option = new_option;
4073
4074 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL);
4075 }
4076
4077 /**
4078 * ice_get_phy_lane_number - Get PHY lane number for current adapter
4079 * @hw: pointer to the hw struct
4080 *
4081 * Return: PHY lane number on success, negative error code otherwise.
4082 */
ice_get_phy_lane_number(struct ice_hw * hw)4083 int ice_get_phy_lane_number(struct ice_hw *hw)
4084 {
4085 struct ice_aqc_get_port_options_elem *options;
4086 unsigned int lport = 0;
4087 unsigned int lane;
4088 int err;
4089
4090 options = kcalloc(ICE_AQC_PORT_OPT_MAX, sizeof(*options), GFP_KERNEL);
4091 if (!options)
4092 return -ENOMEM;
4093
4094 for (lane = 0; lane < ICE_MAX_PORT_PER_PCI_DEV; lane++) {
4095 u8 options_count = ICE_AQC_PORT_OPT_MAX;
4096 u8 speed, active_idx, pending_idx;
4097 bool active_valid, pending_valid;
4098
4099 err = ice_aq_get_port_options(hw, options, &options_count, lane,
4100 true, &active_idx, &active_valid,
4101 &pending_idx, &pending_valid);
4102 if (err)
4103 goto err;
4104
4105 if (!active_valid)
4106 continue;
4107
4108 speed = options[active_idx].max_lane_speed;
4109 /* If we don't get speed for this lane, it's unoccupied */
4110 if (speed > ICE_AQC_PORT_OPT_MAX_LANE_200G)
4111 continue;
4112
4113 if (hw->pf_id == lport) {
4114 kfree(options);
4115 return lane;
4116 }
4117
4118 lport++;
4119 }
4120
4121 /* PHY lane not found */
4122 err = -ENXIO;
4123 err:
4124 kfree(options);
4125 return err;
4126 }
4127
4128 /**
4129 * ice_aq_sff_eeprom
4130 * @hw: pointer to the HW struct
4131 * @lport: bits [7:0] = logical port, bit [8] = logical port valid
4132 * @bus_addr: I2C bus address of the eeprom (typically 0xA0, 0=topo default)
4133 * @mem_addr: I2C offset. lower 8 bits for address, 8 upper bits zero padding.
4134 * @page: QSFP page
4135 * @set_page: set or ignore the page
4136 * @data: pointer to data buffer to be read/written to the I2C device.
4137 * @length: 1-16 for read, 1 for write.
4138 * @write: 0 read, 1 for write.
4139 * @cd: pointer to command details structure or NULL
4140 *
4141 * Read/Write SFF EEPROM (0x06EE)
4142 */
4143 int
ice_aq_sff_eeprom(struct ice_hw * hw,u16 lport,u8 bus_addr,u16 mem_addr,u8 page,u8 set_page,u8 * data,u8 length,bool write,struct ice_sq_cd * cd)4144 ice_aq_sff_eeprom(struct ice_hw *hw, u16 lport, u8 bus_addr,
4145 u16 mem_addr, u8 page, u8 set_page, u8 *data, u8 length,
4146 bool write, struct ice_sq_cd *cd)
4147 {
4148 struct ice_aqc_sff_eeprom *cmd;
4149 struct ice_aq_desc desc;
4150 u16 i2c_bus_addr;
4151 int status;
4152
4153 if (!data || (mem_addr & 0xff00))
4154 return -EINVAL;
4155
4156 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_sff_eeprom);
4157 cmd = &desc.params.read_write_sff_param;
4158 desc.flags = cpu_to_le16(ICE_AQ_FLAG_RD);
4159 cmd->lport_num = (u8)(lport & 0xff);
4160 cmd->lport_num_valid = (u8)((lport >> 8) & 0x01);
4161 i2c_bus_addr = FIELD_PREP(ICE_AQC_SFF_I2CBUS_7BIT_M, bus_addr >> 1) |
4162 FIELD_PREP(ICE_AQC_SFF_SET_EEPROM_PAGE_M, set_page);
4163 if (write)
4164 i2c_bus_addr |= ICE_AQC_SFF_IS_WRITE;
4165 cmd->i2c_bus_addr = cpu_to_le16(i2c_bus_addr);
4166 cmd->i2c_mem_addr = cpu_to_le16(mem_addr & 0xff);
4167 cmd->eeprom_page = le16_encode_bits(page, ICE_AQC_SFF_EEPROM_PAGE_M);
4168
4169 status = ice_aq_send_cmd(hw, &desc, data, length, cd);
4170 return status;
4171 }
4172
ice_lut_type_to_size(enum ice_lut_type type)4173 static enum ice_lut_size ice_lut_type_to_size(enum ice_lut_type type)
4174 {
4175 switch (type) {
4176 case ICE_LUT_VSI:
4177 return ICE_LUT_VSI_SIZE;
4178 case ICE_LUT_GLOBAL:
4179 return ICE_LUT_GLOBAL_SIZE;
4180 case ICE_LUT_PF:
4181 return ICE_LUT_PF_SIZE;
4182 }
4183 WARN_ONCE(1, "incorrect type passed");
4184 return ICE_LUT_VSI_SIZE;
4185 }
4186
ice_lut_size_to_flag(enum ice_lut_size size)4187 static enum ice_aqc_lut_flags ice_lut_size_to_flag(enum ice_lut_size size)
4188 {
4189 switch (size) {
4190 case ICE_LUT_VSI_SIZE:
4191 return ICE_AQC_LUT_SIZE_SMALL;
4192 case ICE_LUT_GLOBAL_SIZE:
4193 return ICE_AQC_LUT_SIZE_512;
4194 case ICE_LUT_PF_SIZE:
4195 return ICE_AQC_LUT_SIZE_2K;
4196 }
4197 WARN_ONCE(1, "incorrect size passed");
4198 return 0;
4199 }
4200
4201 /**
4202 * __ice_aq_get_set_rss_lut
4203 * @hw: pointer to the hardware structure
4204 * @params: RSS LUT parameters
4205 * @set: set true to set the table, false to get the table
4206 *
4207 * Internal function to get (0x0B05) or set (0x0B03) RSS look up table
4208 */
4209 static int
__ice_aq_get_set_rss_lut(struct ice_hw * hw,struct ice_aq_get_set_rss_lut_params * params,bool set)4210 __ice_aq_get_set_rss_lut(struct ice_hw *hw,
4211 struct ice_aq_get_set_rss_lut_params *params, bool set)
4212 {
4213 u16 opcode, vsi_id, vsi_handle = params->vsi_handle, glob_lut_idx = 0;
4214 enum ice_lut_type lut_type = params->lut_type;
4215 struct ice_aqc_get_set_rss_lut *desc_params;
4216 enum ice_aqc_lut_flags flags;
4217 enum ice_lut_size lut_size;
4218 struct ice_aq_desc desc;
4219 u8 *lut = params->lut;
4220
4221
4222 if (!lut || !ice_is_vsi_valid(hw, vsi_handle))
4223 return -EINVAL;
4224
4225 lut_size = ice_lut_type_to_size(lut_type);
4226 if (lut_size > params->lut_size)
4227 return -EINVAL;
4228 else if (set && lut_size != params->lut_size)
4229 return -EINVAL;
4230
4231 opcode = set ? ice_aqc_opc_set_rss_lut : ice_aqc_opc_get_rss_lut;
4232 ice_fill_dflt_direct_cmd_desc(&desc, opcode);
4233 if (set)
4234 desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD);
4235
4236 desc_params = &desc.params.get_set_rss_lut;
4237 vsi_id = ice_get_hw_vsi_num(hw, vsi_handle);
4238 desc_params->vsi_id = cpu_to_le16(vsi_id | ICE_AQC_RSS_VSI_VALID);
4239
4240 if (lut_type == ICE_LUT_GLOBAL)
4241 glob_lut_idx = FIELD_PREP(ICE_AQC_LUT_GLOBAL_IDX,
4242 params->global_lut_id);
4243
4244 flags = lut_type | glob_lut_idx | ice_lut_size_to_flag(lut_size);
4245 desc_params->flags = cpu_to_le16(flags);
4246
4247 return ice_aq_send_cmd(hw, &desc, lut, lut_size, NULL);
4248 }
4249
4250 /**
4251 * ice_aq_get_rss_lut
4252 * @hw: pointer to the hardware structure
4253 * @get_params: RSS LUT parameters used to specify which RSS LUT to get
4254 *
4255 * get the RSS lookup table, PF or VSI type
4256 */
4257 int
ice_aq_get_rss_lut(struct ice_hw * hw,struct ice_aq_get_set_rss_lut_params * get_params)4258 ice_aq_get_rss_lut(struct ice_hw *hw, struct ice_aq_get_set_rss_lut_params *get_params)
4259 {
4260 return __ice_aq_get_set_rss_lut(hw, get_params, false);
4261 }
4262
4263 /**
4264 * ice_aq_set_rss_lut
4265 * @hw: pointer to the hardware structure
4266 * @set_params: RSS LUT parameters used to specify how to set the RSS LUT
4267 *
4268 * set the RSS lookup table, PF or VSI type
4269 */
4270 int
ice_aq_set_rss_lut(struct ice_hw * hw,struct ice_aq_get_set_rss_lut_params * set_params)4271 ice_aq_set_rss_lut(struct ice_hw *hw, struct ice_aq_get_set_rss_lut_params *set_params)
4272 {
4273 return __ice_aq_get_set_rss_lut(hw, set_params, true);
4274 }
4275
4276 /**
4277 * __ice_aq_get_set_rss_key
4278 * @hw: pointer to the HW struct
4279 * @vsi_id: VSI FW index
4280 * @key: pointer to key info struct
4281 * @set: set true to set the key, false to get the key
4282 *
4283 * get (0x0B04) or set (0x0B02) the RSS key per VSI
4284 */
4285 static int
__ice_aq_get_set_rss_key(struct ice_hw * hw,u16 vsi_id,struct ice_aqc_get_set_rss_keys * key,bool set)4286 __ice_aq_get_set_rss_key(struct ice_hw *hw, u16 vsi_id,
4287 struct ice_aqc_get_set_rss_keys *key, bool set)
4288 {
4289 struct ice_aqc_get_set_rss_key *desc_params;
4290 u16 key_size = sizeof(*key);
4291 struct ice_aq_desc desc;
4292
4293 if (set) {
4294 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_rss_key);
4295 desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD);
4296 } else {
4297 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_rss_key);
4298 }
4299
4300 desc_params = &desc.params.get_set_rss_key;
4301 desc_params->vsi_id = cpu_to_le16(vsi_id | ICE_AQC_RSS_VSI_VALID);
4302
4303 return ice_aq_send_cmd(hw, &desc, key, key_size, NULL);
4304 }
4305
4306 /**
4307 * ice_aq_get_rss_key
4308 * @hw: pointer to the HW struct
4309 * @vsi_handle: software VSI handle
4310 * @key: pointer to key info struct
4311 *
4312 * get the RSS key per VSI
4313 */
4314 int
ice_aq_get_rss_key(struct ice_hw * hw,u16 vsi_handle,struct ice_aqc_get_set_rss_keys * key)4315 ice_aq_get_rss_key(struct ice_hw *hw, u16 vsi_handle,
4316 struct ice_aqc_get_set_rss_keys *key)
4317 {
4318 if (!ice_is_vsi_valid(hw, vsi_handle) || !key)
4319 return -EINVAL;
4320
4321 return __ice_aq_get_set_rss_key(hw, ice_get_hw_vsi_num(hw, vsi_handle),
4322 key, false);
4323 }
4324
4325 /**
4326 * ice_aq_set_rss_key
4327 * @hw: pointer to the HW struct
4328 * @vsi_handle: software VSI handle
4329 * @keys: pointer to key info struct
4330 *
4331 * set the RSS key per VSI
4332 */
4333 int
ice_aq_set_rss_key(struct ice_hw * hw,u16 vsi_handle,struct ice_aqc_get_set_rss_keys * keys)4334 ice_aq_set_rss_key(struct ice_hw *hw, u16 vsi_handle,
4335 struct ice_aqc_get_set_rss_keys *keys)
4336 {
4337 if (!ice_is_vsi_valid(hw, vsi_handle) || !keys)
4338 return -EINVAL;
4339
4340 return __ice_aq_get_set_rss_key(hw, ice_get_hw_vsi_num(hw, vsi_handle),
4341 keys, true);
4342 }
4343
4344 /**
4345 * ice_aq_add_lan_txq
4346 * @hw: pointer to the hardware structure
4347 * @num_qgrps: Number of added queue groups
4348 * @qg_list: list of queue groups to be added
4349 * @buf_size: size of buffer for indirect command
4350 * @cd: pointer to command details structure or NULL
4351 *
4352 * Add Tx LAN queue (0x0C30)
4353 *
4354 * NOTE:
4355 * Prior to calling add Tx LAN queue:
4356 * Initialize the following as part of the Tx queue context:
4357 * Completion queue ID if the queue uses Completion queue, Quanta profile,
4358 * Cache profile and Packet shaper profile.
4359 *
4360 * After add Tx LAN queue AQ command is completed:
4361 * Interrupts should be associated with specific queues,
4362 * Association of Tx queue to Doorbell queue is not part of Add LAN Tx queue
4363 * flow.
4364 */
4365 static int
ice_aq_add_lan_txq(struct ice_hw * hw,u8 num_qgrps,struct ice_aqc_add_tx_qgrp * qg_list,u16 buf_size,struct ice_sq_cd * cd)4366 ice_aq_add_lan_txq(struct ice_hw *hw, u8 num_qgrps,
4367 struct ice_aqc_add_tx_qgrp *qg_list, u16 buf_size,
4368 struct ice_sq_cd *cd)
4369 {
4370 struct ice_aqc_add_tx_qgrp *list;
4371 struct ice_aqc_add_txqs *cmd;
4372 struct ice_aq_desc desc;
4373 u16 i, sum_size = 0;
4374
4375 cmd = &desc.params.add_txqs;
4376
4377 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_add_txqs);
4378
4379 if (!qg_list)
4380 return -EINVAL;
4381
4382 if (num_qgrps > ICE_LAN_TXQ_MAX_QGRPS)
4383 return -EINVAL;
4384
4385 for (i = 0, list = qg_list; i < num_qgrps; i++) {
4386 sum_size += struct_size(list, txqs, list->num_txqs);
4387 list = (struct ice_aqc_add_tx_qgrp *)(list->txqs +
4388 list->num_txqs);
4389 }
4390
4391 if (buf_size != sum_size)
4392 return -EINVAL;
4393
4394 desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD);
4395
4396 cmd->num_qgrps = num_qgrps;
4397
4398 return ice_aq_send_cmd(hw, &desc, qg_list, buf_size, cd);
4399 }
4400
4401 /**
4402 * ice_aq_dis_lan_txq
4403 * @hw: pointer to the hardware structure
4404 * @num_qgrps: number of groups in the list
4405 * @qg_list: the list of groups to disable
4406 * @buf_size: the total size of the qg_list buffer in bytes
4407 * @rst_src: if called due to reset, specifies the reset source
4408 * @vmvf_num: the relative VM or VF number that is undergoing the reset
4409 * @cd: pointer to command details structure or NULL
4410 *
4411 * Disable LAN Tx queue (0x0C31)
4412 */
4413 static int
ice_aq_dis_lan_txq(struct ice_hw * hw,u8 num_qgrps,struct ice_aqc_dis_txq_item * qg_list,u16 buf_size,enum ice_disq_rst_src rst_src,u16 vmvf_num,struct ice_sq_cd * cd)4414 ice_aq_dis_lan_txq(struct ice_hw *hw, u8 num_qgrps,
4415 struct ice_aqc_dis_txq_item *qg_list, u16 buf_size,
4416 enum ice_disq_rst_src rst_src, u16 vmvf_num,
4417 struct ice_sq_cd *cd)
4418 {
4419 struct ice_aqc_dis_txq_item *item;
4420 struct ice_aqc_dis_txqs *cmd;
4421 struct ice_aq_desc desc;
4422 u16 vmvf_and_timeout;
4423 u16 i, sz = 0;
4424 int status;
4425
4426 cmd = &desc.params.dis_txqs;
4427 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_dis_txqs);
4428
4429 /* qg_list can be NULL only in VM/VF reset flow */
4430 if (!qg_list && !rst_src)
4431 return -EINVAL;
4432
4433 if (num_qgrps > ICE_LAN_TXQ_MAX_QGRPS)
4434 return -EINVAL;
4435
4436 cmd->num_entries = num_qgrps;
4437
4438 vmvf_and_timeout = FIELD_PREP(ICE_AQC_Q_DIS_TIMEOUT_M, 5);
4439
4440 switch (rst_src) {
4441 case ICE_VM_RESET:
4442 cmd->cmd_type = ICE_AQC_Q_DIS_CMD_VM_RESET;
4443 vmvf_and_timeout |= vmvf_num & ICE_AQC_Q_DIS_VMVF_NUM_M;
4444 break;
4445 case ICE_VF_RESET:
4446 cmd->cmd_type = ICE_AQC_Q_DIS_CMD_VF_RESET;
4447 /* In this case, FW expects vmvf_num to be absolute VF ID */
4448 vmvf_and_timeout |= (vmvf_num + hw->func_caps.vf_base_id) &
4449 ICE_AQC_Q_DIS_VMVF_NUM_M;
4450 break;
4451 case ICE_NO_RESET:
4452 default:
4453 break;
4454 }
4455
4456 cmd->vmvf_and_timeout = cpu_to_le16(vmvf_and_timeout);
4457
4458 /* flush pipe on time out */
4459 cmd->cmd_type |= ICE_AQC_Q_DIS_CMD_FLUSH_PIPE;
4460 /* If no queue group info, we are in a reset flow. Issue the AQ */
4461 if (!qg_list)
4462 goto do_aq;
4463
4464 /* set RD bit to indicate that command buffer is provided by the driver
4465 * and it needs to be read by the firmware
4466 */
4467 desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD);
4468
4469 for (i = 0, item = qg_list; i < num_qgrps; i++) {
4470 u16 item_size = struct_size(item, q_id, item->num_qs);
4471
4472 /* If the num of queues is even, add 2 bytes of padding */
4473 if ((item->num_qs % 2) == 0)
4474 item_size += 2;
4475
4476 sz += item_size;
4477
4478 item = (struct ice_aqc_dis_txq_item *)((u8 *)item + item_size);
4479 }
4480
4481 if (buf_size != sz)
4482 return -EINVAL;
4483
4484 do_aq:
4485 status = ice_aq_send_cmd(hw, &desc, qg_list, buf_size, cd);
4486 if (status) {
4487 if (!qg_list)
4488 ice_debug(hw, ICE_DBG_SCHED, "VM%d disable failed %d\n",
4489 vmvf_num, hw->adminq.sq_last_status);
4490 else
4491 ice_debug(hw, ICE_DBG_SCHED, "disable queue %d failed %d\n",
4492 le16_to_cpu(qg_list[0].q_id[0]),
4493 hw->adminq.sq_last_status);
4494 }
4495 return status;
4496 }
4497
4498 /**
4499 * ice_aq_cfg_lan_txq
4500 * @hw: pointer to the hardware structure
4501 * @buf: buffer for command
4502 * @buf_size: size of buffer in bytes
4503 * @num_qs: number of queues being configured
4504 * @oldport: origination lport
4505 * @newport: destination lport
4506 * @cd: pointer to command details structure or NULL
4507 *
4508 * Move/Configure LAN Tx queue (0x0C32)
4509 *
4510 * There is a better AQ command to use for moving nodes, so only coding
4511 * this one for configuring the node.
4512 */
4513 int
ice_aq_cfg_lan_txq(struct ice_hw * hw,struct ice_aqc_cfg_txqs_buf * buf,u16 buf_size,u16 num_qs,u8 oldport,u8 newport,struct ice_sq_cd * cd)4514 ice_aq_cfg_lan_txq(struct ice_hw *hw, struct ice_aqc_cfg_txqs_buf *buf,
4515 u16 buf_size, u16 num_qs, u8 oldport, u8 newport,
4516 struct ice_sq_cd *cd)
4517 {
4518 struct ice_aqc_cfg_txqs *cmd;
4519 struct ice_aq_desc desc;
4520 int status;
4521
4522 cmd = &desc.params.cfg_txqs;
4523 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_cfg_txqs);
4524 desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD);
4525
4526 if (!buf)
4527 return -EINVAL;
4528
4529 cmd->cmd_type = ICE_AQC_Q_CFG_TC_CHNG;
4530 cmd->num_qs = num_qs;
4531 cmd->port_num_chng = (oldport & ICE_AQC_Q_CFG_SRC_PRT_M);
4532 cmd->port_num_chng |= FIELD_PREP(ICE_AQC_Q_CFG_DST_PRT_M, newport);
4533 cmd->time_out = FIELD_PREP(ICE_AQC_Q_CFG_TIMEOUT_M, 5);
4534 cmd->blocked_cgds = 0;
4535
4536 status = ice_aq_send_cmd(hw, &desc, buf, buf_size, cd);
4537 if (status)
4538 ice_debug(hw, ICE_DBG_SCHED, "Failed to reconfigure nodes %d\n",
4539 hw->adminq.sq_last_status);
4540 return status;
4541 }
4542
4543 /**
4544 * ice_aq_add_rdma_qsets
4545 * @hw: pointer to the hardware structure
4546 * @num_qset_grps: Number of RDMA Qset groups
4547 * @qset_list: list of Qset groups to be added
4548 * @buf_size: size of buffer for indirect command
4549 * @cd: pointer to command details structure or NULL
4550 *
4551 * Add Tx RDMA Qsets (0x0C33)
4552 */
4553 static int
ice_aq_add_rdma_qsets(struct ice_hw * hw,u8 num_qset_grps,struct ice_aqc_add_rdma_qset_data * qset_list,u16 buf_size,struct ice_sq_cd * cd)4554 ice_aq_add_rdma_qsets(struct ice_hw *hw, u8 num_qset_grps,
4555 struct ice_aqc_add_rdma_qset_data *qset_list,
4556 u16 buf_size, struct ice_sq_cd *cd)
4557 {
4558 struct ice_aqc_add_rdma_qset_data *list;
4559 struct ice_aqc_add_rdma_qset *cmd;
4560 struct ice_aq_desc desc;
4561 u16 i, sum_size = 0;
4562
4563 cmd = &desc.params.add_rdma_qset;
4564
4565 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_add_rdma_qset);
4566
4567 if (num_qset_grps > ICE_LAN_TXQ_MAX_QGRPS)
4568 return -EINVAL;
4569
4570 for (i = 0, list = qset_list; i < num_qset_grps; i++) {
4571 u16 num_qsets = le16_to_cpu(list->num_qsets);
4572
4573 sum_size += struct_size(list, rdma_qsets, num_qsets);
4574 list = (struct ice_aqc_add_rdma_qset_data *)(list->rdma_qsets +
4575 num_qsets);
4576 }
4577
4578 if (buf_size != sum_size)
4579 return -EINVAL;
4580
4581 desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD);
4582
4583 cmd->num_qset_grps = num_qset_grps;
4584
4585 return ice_aq_send_cmd(hw, &desc, qset_list, buf_size, cd);
4586 }
4587
4588 /* End of FW Admin Queue command wrappers */
4589
4590 /**
4591 * ice_pack_ctx_byte - write a byte to a packed context structure
4592 * @src_ctx: unpacked source context structure
4593 * @dest_ctx: packed destination context data
4594 * @ce_info: context element description
4595 */
ice_pack_ctx_byte(u8 * src_ctx,u8 * dest_ctx,const struct ice_ctx_ele * ce_info)4596 static void ice_pack_ctx_byte(u8 *src_ctx, u8 *dest_ctx,
4597 const struct ice_ctx_ele *ce_info)
4598 {
4599 u8 src_byte, dest_byte, mask;
4600 u8 *from, *dest;
4601 u16 shift_width;
4602
4603 /* copy from the next struct field */
4604 from = src_ctx + ce_info->offset;
4605
4606 /* prepare the bits and mask */
4607 shift_width = ce_info->lsb % 8;
4608 mask = GENMASK(ce_info->width - 1 + shift_width, shift_width);
4609
4610 src_byte = *from;
4611 src_byte <<= shift_width;
4612 src_byte &= mask;
4613
4614 /* get the current bits from the target bit string */
4615 dest = dest_ctx + (ce_info->lsb / 8);
4616
4617 memcpy(&dest_byte, dest, sizeof(dest_byte));
4618
4619 dest_byte &= ~mask; /* get the bits not changing */
4620 dest_byte |= src_byte; /* add in the new bits */
4621
4622 /* put it all back */
4623 memcpy(dest, &dest_byte, sizeof(dest_byte));
4624 }
4625
4626 /**
4627 * ice_pack_ctx_word - write a word to a packed context structure
4628 * @src_ctx: unpacked source context structure
4629 * @dest_ctx: packed destination context data
4630 * @ce_info: context element description
4631 */
ice_pack_ctx_word(u8 * src_ctx,u8 * dest_ctx,const struct ice_ctx_ele * ce_info)4632 static void ice_pack_ctx_word(u8 *src_ctx, u8 *dest_ctx,
4633 const struct ice_ctx_ele *ce_info)
4634 {
4635 u16 src_word, mask;
4636 __le16 dest_word;
4637 u8 *from, *dest;
4638 u16 shift_width;
4639
4640 /* copy from the next struct field */
4641 from = src_ctx + ce_info->offset;
4642
4643 /* prepare the bits and mask */
4644 shift_width = ce_info->lsb % 8;
4645 mask = GENMASK(ce_info->width - 1 + shift_width, shift_width);
4646
4647 /* don't swizzle the bits until after the mask because the mask bits
4648 * will be in a different bit position on big endian machines
4649 */
4650 src_word = *(u16 *)from;
4651 src_word <<= shift_width;
4652 src_word &= mask;
4653
4654 /* get the current bits from the target bit string */
4655 dest = dest_ctx + (ce_info->lsb / 8);
4656
4657 memcpy(&dest_word, dest, sizeof(dest_word));
4658
4659 dest_word &= ~(cpu_to_le16(mask)); /* get the bits not changing */
4660 dest_word |= cpu_to_le16(src_word); /* add in the new bits */
4661
4662 /* put it all back */
4663 memcpy(dest, &dest_word, sizeof(dest_word));
4664 }
4665
4666 /**
4667 * ice_pack_ctx_dword - write a dword to a packed context structure
4668 * @src_ctx: unpacked source context structure
4669 * @dest_ctx: packed destination context data
4670 * @ce_info: context element description
4671 */
ice_pack_ctx_dword(u8 * src_ctx,u8 * dest_ctx,const struct ice_ctx_ele * ce_info)4672 static void ice_pack_ctx_dword(u8 *src_ctx, u8 *dest_ctx,
4673 const struct ice_ctx_ele *ce_info)
4674 {
4675 u32 src_dword, mask;
4676 __le32 dest_dword;
4677 u8 *from, *dest;
4678 u16 shift_width;
4679
4680 /* copy from the next struct field */
4681 from = src_ctx + ce_info->offset;
4682
4683 /* prepare the bits and mask */
4684 shift_width = ce_info->lsb % 8;
4685 mask = GENMASK(ce_info->width - 1 + shift_width, shift_width);
4686
4687 /* don't swizzle the bits until after the mask because the mask bits
4688 * will be in a different bit position on big endian machines
4689 */
4690 src_dword = *(u32 *)from;
4691 src_dword <<= shift_width;
4692 src_dword &= mask;
4693
4694 /* get the current bits from the target bit string */
4695 dest = dest_ctx + (ce_info->lsb / 8);
4696
4697 memcpy(&dest_dword, dest, sizeof(dest_dword));
4698
4699 dest_dword &= ~(cpu_to_le32(mask)); /* get the bits not changing */
4700 dest_dword |= cpu_to_le32(src_dword); /* add in the new bits */
4701
4702 /* put it all back */
4703 memcpy(dest, &dest_dword, sizeof(dest_dword));
4704 }
4705
4706 /**
4707 * ice_pack_ctx_qword - write a qword to a packed context structure
4708 * @src_ctx: unpacked source context structure
4709 * @dest_ctx: packed destination context data
4710 * @ce_info: context element description
4711 */
ice_pack_ctx_qword(u8 * src_ctx,u8 * dest_ctx,const struct ice_ctx_ele * ce_info)4712 static void ice_pack_ctx_qword(u8 *src_ctx, u8 *dest_ctx,
4713 const struct ice_ctx_ele *ce_info)
4714 {
4715 u64 src_qword, mask;
4716 __le64 dest_qword;
4717 u8 *from, *dest;
4718 u16 shift_width;
4719
4720 /* copy from the next struct field */
4721 from = src_ctx + ce_info->offset;
4722
4723 /* prepare the bits and mask */
4724 shift_width = ce_info->lsb % 8;
4725 mask = GENMASK_ULL(ce_info->width - 1 + shift_width, shift_width);
4726
4727 /* don't swizzle the bits until after the mask because the mask bits
4728 * will be in a different bit position on big endian machines
4729 */
4730 src_qword = *(u64 *)from;
4731 src_qword <<= shift_width;
4732 src_qword &= mask;
4733
4734 /* get the current bits from the target bit string */
4735 dest = dest_ctx + (ce_info->lsb / 8);
4736
4737 memcpy(&dest_qword, dest, sizeof(dest_qword));
4738
4739 dest_qword &= ~(cpu_to_le64(mask)); /* get the bits not changing */
4740 dest_qword |= cpu_to_le64(src_qword); /* add in the new bits */
4741
4742 /* put it all back */
4743 memcpy(dest, &dest_qword, sizeof(dest_qword));
4744 }
4745
4746 /**
4747 * ice_set_ctx - set context bits in packed structure
4748 * @hw: pointer to the hardware structure
4749 * @src_ctx: pointer to a generic non-packed context structure
4750 * @dest_ctx: pointer to memory for the packed structure
4751 * @ce_info: List of Rx context elements
4752 */
ice_set_ctx(struct ice_hw * hw,u8 * src_ctx,u8 * dest_ctx,const struct ice_ctx_ele * ce_info)4753 int ice_set_ctx(struct ice_hw *hw, u8 *src_ctx, u8 *dest_ctx,
4754 const struct ice_ctx_ele *ce_info)
4755 {
4756 int f;
4757
4758 for (f = 0; ce_info[f].width; f++) {
4759 /* We have to deal with each element of the FW response
4760 * using the correct size so that we are correct regardless
4761 * of the endianness of the machine.
4762 */
4763 if (ce_info[f].width > (ce_info[f].size_of * BITS_PER_BYTE)) {
4764 ice_debug(hw, ICE_DBG_QCTX, "Field %d width of %d bits larger than size of %d byte(s) ... skipping write\n",
4765 f, ce_info[f].width, ce_info[f].size_of);
4766 continue;
4767 }
4768 switch (ce_info[f].size_of) {
4769 case sizeof(u8):
4770 ice_pack_ctx_byte(src_ctx, dest_ctx, &ce_info[f]);
4771 break;
4772 case sizeof(u16):
4773 ice_pack_ctx_word(src_ctx, dest_ctx, &ce_info[f]);
4774 break;
4775 case sizeof(u32):
4776 ice_pack_ctx_dword(src_ctx, dest_ctx, &ce_info[f]);
4777 break;
4778 case sizeof(u64):
4779 ice_pack_ctx_qword(src_ctx, dest_ctx, &ce_info[f]);
4780 break;
4781 default:
4782 return -EINVAL;
4783 }
4784 }
4785
4786 return 0;
4787 }
4788
4789 /**
4790 * ice_get_lan_q_ctx - get the LAN queue context for the given VSI and TC
4791 * @hw: pointer to the HW struct
4792 * @vsi_handle: software VSI handle
4793 * @tc: TC number
4794 * @q_handle: software queue handle
4795 */
4796 struct ice_q_ctx *
ice_get_lan_q_ctx(struct ice_hw * hw,u16 vsi_handle,u8 tc,u16 q_handle)4797 ice_get_lan_q_ctx(struct ice_hw *hw, u16 vsi_handle, u8 tc, u16 q_handle)
4798 {
4799 struct ice_vsi_ctx *vsi;
4800 struct ice_q_ctx *q_ctx;
4801
4802 vsi = ice_get_vsi_ctx(hw, vsi_handle);
4803 if (!vsi)
4804 return NULL;
4805 if (q_handle >= vsi->num_lan_q_entries[tc])
4806 return NULL;
4807 if (!vsi->lan_q_ctx[tc])
4808 return NULL;
4809 q_ctx = vsi->lan_q_ctx[tc];
4810 return &q_ctx[q_handle];
4811 }
4812
4813 /**
4814 * ice_ena_vsi_txq
4815 * @pi: port information structure
4816 * @vsi_handle: software VSI handle
4817 * @tc: TC number
4818 * @q_handle: software queue handle
4819 * @num_qgrps: Number of added queue groups
4820 * @buf: list of queue groups to be added
4821 * @buf_size: size of buffer for indirect command
4822 * @cd: pointer to command details structure or NULL
4823 *
4824 * This function adds one LAN queue
4825 */
4826 int
ice_ena_vsi_txq(struct ice_port_info * pi,u16 vsi_handle,u8 tc,u16 q_handle,u8 num_qgrps,struct ice_aqc_add_tx_qgrp * buf,u16 buf_size,struct ice_sq_cd * cd)4827 ice_ena_vsi_txq(struct ice_port_info *pi, u16 vsi_handle, u8 tc, u16 q_handle,
4828 u8 num_qgrps, struct ice_aqc_add_tx_qgrp *buf, u16 buf_size,
4829 struct ice_sq_cd *cd)
4830 {
4831 struct ice_aqc_txsched_elem_data node = { 0 };
4832 struct ice_sched_node *parent;
4833 struct ice_q_ctx *q_ctx;
4834 struct ice_hw *hw;
4835 int status;
4836
4837 if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY)
4838 return -EIO;
4839
4840 if (num_qgrps > 1 || buf->num_txqs > 1)
4841 return -ENOSPC;
4842
4843 hw = pi->hw;
4844
4845 if (!ice_is_vsi_valid(hw, vsi_handle))
4846 return -EINVAL;
4847
4848 mutex_lock(&pi->sched_lock);
4849
4850 q_ctx = ice_get_lan_q_ctx(hw, vsi_handle, tc, q_handle);
4851 if (!q_ctx) {
4852 ice_debug(hw, ICE_DBG_SCHED, "Enaq: invalid queue handle %d\n",
4853 q_handle);
4854 status = -EINVAL;
4855 goto ena_txq_exit;
4856 }
4857
4858 /* find a parent node */
4859 parent = ice_sched_get_free_qparent(pi, vsi_handle, tc,
4860 ICE_SCHED_NODE_OWNER_LAN);
4861 if (!parent) {
4862 status = -EINVAL;
4863 goto ena_txq_exit;
4864 }
4865
4866 buf->parent_teid = parent->info.node_teid;
4867 node.parent_teid = parent->info.node_teid;
4868 /* Mark that the values in the "generic" section as valid. The default
4869 * value in the "generic" section is zero. This means that :
4870 * - Scheduling mode is Bytes Per Second (BPS), indicated by Bit 0.
4871 * - 0 priority among siblings, indicated by Bit 1-3.
4872 * - WFQ, indicated by Bit 4.
4873 * - 0 Adjustment value is used in PSM credit update flow, indicated by
4874 * Bit 5-6.
4875 * - Bit 7 is reserved.
4876 * Without setting the generic section as valid in valid_sections, the
4877 * Admin queue command will fail with error code ICE_AQ_RC_EINVAL.
4878 */
4879 buf->txqs[0].info.valid_sections =
4880 ICE_AQC_ELEM_VALID_GENERIC | ICE_AQC_ELEM_VALID_CIR |
4881 ICE_AQC_ELEM_VALID_EIR;
4882 buf->txqs[0].info.generic = 0;
4883 buf->txqs[0].info.cir_bw.bw_profile_idx =
4884 cpu_to_le16(ICE_SCHED_DFLT_RL_PROF_ID);
4885 buf->txqs[0].info.cir_bw.bw_alloc =
4886 cpu_to_le16(ICE_SCHED_DFLT_BW_WT);
4887 buf->txqs[0].info.eir_bw.bw_profile_idx =
4888 cpu_to_le16(ICE_SCHED_DFLT_RL_PROF_ID);
4889 buf->txqs[0].info.eir_bw.bw_alloc =
4890 cpu_to_le16(ICE_SCHED_DFLT_BW_WT);
4891
4892 /* add the LAN queue */
4893 status = ice_aq_add_lan_txq(hw, num_qgrps, buf, buf_size, cd);
4894 if (status) {
4895 ice_debug(hw, ICE_DBG_SCHED, "enable queue %d failed %d\n",
4896 le16_to_cpu(buf->txqs[0].txq_id),
4897 hw->adminq.sq_last_status);
4898 goto ena_txq_exit;
4899 }
4900
4901 node.node_teid = buf->txqs[0].q_teid;
4902 node.data.elem_type = ICE_AQC_ELEM_TYPE_LEAF;
4903 q_ctx->q_handle = q_handle;
4904 q_ctx->q_teid = le32_to_cpu(node.node_teid);
4905
4906 /* add a leaf node into scheduler tree queue layer */
4907 status = ice_sched_add_node(pi, hw->num_tx_sched_layers - 1, &node, NULL);
4908 if (!status)
4909 status = ice_sched_replay_q_bw(pi, q_ctx);
4910
4911 ena_txq_exit:
4912 mutex_unlock(&pi->sched_lock);
4913 return status;
4914 }
4915
4916 /**
4917 * ice_dis_vsi_txq
4918 * @pi: port information structure
4919 * @vsi_handle: software VSI handle
4920 * @tc: TC number
4921 * @num_queues: number of queues
4922 * @q_handles: pointer to software queue handle array
4923 * @q_ids: pointer to the q_id array
4924 * @q_teids: pointer to queue node teids
4925 * @rst_src: if called due to reset, specifies the reset source
4926 * @vmvf_num: the relative VM or VF number that is undergoing the reset
4927 * @cd: pointer to command details structure or NULL
4928 *
4929 * This function removes queues and their corresponding nodes in SW DB
4930 */
4931 int
ice_dis_vsi_txq(struct ice_port_info * pi,u16 vsi_handle,u8 tc,u8 num_queues,u16 * q_handles,u16 * q_ids,u32 * q_teids,enum ice_disq_rst_src rst_src,u16 vmvf_num,struct ice_sq_cd * cd)4932 ice_dis_vsi_txq(struct ice_port_info *pi, u16 vsi_handle, u8 tc, u8 num_queues,
4933 u16 *q_handles, u16 *q_ids, u32 *q_teids,
4934 enum ice_disq_rst_src rst_src, u16 vmvf_num,
4935 struct ice_sq_cd *cd)
4936 {
4937 DEFINE_RAW_FLEX(struct ice_aqc_dis_txq_item, qg_list, q_id, 1);
4938 u16 i, buf_size = __struct_size(qg_list);
4939 struct ice_q_ctx *q_ctx;
4940 int status = -ENOENT;
4941 struct ice_hw *hw;
4942
4943 if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY)
4944 return -EIO;
4945
4946 hw = pi->hw;
4947
4948 if (!num_queues) {
4949 /* if queue is disabled already yet the disable queue command
4950 * has to be sent to complete the VF reset, then call
4951 * ice_aq_dis_lan_txq without any queue information
4952 */
4953 if (rst_src)
4954 return ice_aq_dis_lan_txq(hw, 0, NULL, 0, rst_src,
4955 vmvf_num, NULL);
4956 return -EIO;
4957 }
4958
4959 mutex_lock(&pi->sched_lock);
4960
4961 for (i = 0; i < num_queues; i++) {
4962 struct ice_sched_node *node;
4963
4964 node = ice_sched_find_node_by_teid(pi->root, q_teids[i]);
4965 if (!node)
4966 continue;
4967 q_ctx = ice_get_lan_q_ctx(hw, vsi_handle, tc, q_handles[i]);
4968 if (!q_ctx) {
4969 ice_debug(hw, ICE_DBG_SCHED, "invalid queue handle%d\n",
4970 q_handles[i]);
4971 continue;
4972 }
4973 if (q_ctx->q_handle != q_handles[i]) {
4974 ice_debug(hw, ICE_DBG_SCHED, "Err:handles %d %d\n",
4975 q_ctx->q_handle, q_handles[i]);
4976 continue;
4977 }
4978 qg_list->parent_teid = node->info.parent_teid;
4979 qg_list->num_qs = 1;
4980 qg_list->q_id[0] = cpu_to_le16(q_ids[i]);
4981 status = ice_aq_dis_lan_txq(hw, 1, qg_list, buf_size, rst_src,
4982 vmvf_num, cd);
4983
4984 if (status)
4985 break;
4986 ice_free_sched_node(pi, node);
4987 q_ctx->q_handle = ICE_INVAL_Q_HANDLE;
4988 q_ctx->q_teid = ICE_INVAL_TEID;
4989 }
4990 mutex_unlock(&pi->sched_lock);
4991 return status;
4992 }
4993
4994 /**
4995 * ice_cfg_vsi_qs - configure the new/existing VSI queues
4996 * @pi: port information structure
4997 * @vsi_handle: software VSI handle
4998 * @tc_bitmap: TC bitmap
4999 * @maxqs: max queues array per TC
5000 * @owner: LAN or RDMA
5001 *
5002 * This function adds/updates the VSI queues per TC.
5003 */
5004 static int
ice_cfg_vsi_qs(struct ice_port_info * pi,u16 vsi_handle,u8 tc_bitmap,u16 * maxqs,u8 owner)5005 ice_cfg_vsi_qs(struct ice_port_info *pi, u16 vsi_handle, u8 tc_bitmap,
5006 u16 *maxqs, u8 owner)
5007 {
5008 int status = 0;
5009 u8 i;
5010
5011 if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY)
5012 return -EIO;
5013
5014 if (!ice_is_vsi_valid(pi->hw, vsi_handle))
5015 return -EINVAL;
5016
5017 mutex_lock(&pi->sched_lock);
5018
5019 ice_for_each_traffic_class(i) {
5020 /* configuration is possible only if TC node is present */
5021 if (!ice_sched_get_tc_node(pi, i))
5022 continue;
5023
5024 status = ice_sched_cfg_vsi(pi, vsi_handle, i, maxqs[i], owner,
5025 ice_is_tc_ena(tc_bitmap, i));
5026 if (status)
5027 break;
5028 }
5029
5030 mutex_unlock(&pi->sched_lock);
5031 return status;
5032 }
5033
5034 /**
5035 * ice_cfg_vsi_lan - configure VSI LAN queues
5036 * @pi: port information structure
5037 * @vsi_handle: software VSI handle
5038 * @tc_bitmap: TC bitmap
5039 * @max_lanqs: max LAN queues array per TC
5040 *
5041 * This function adds/updates the VSI LAN queues per TC.
5042 */
5043 int
ice_cfg_vsi_lan(struct ice_port_info * pi,u16 vsi_handle,u8 tc_bitmap,u16 * max_lanqs)5044 ice_cfg_vsi_lan(struct ice_port_info *pi, u16 vsi_handle, u8 tc_bitmap,
5045 u16 *max_lanqs)
5046 {
5047 return ice_cfg_vsi_qs(pi, vsi_handle, tc_bitmap, max_lanqs,
5048 ICE_SCHED_NODE_OWNER_LAN);
5049 }
5050
5051 /**
5052 * ice_cfg_vsi_rdma - configure the VSI RDMA queues
5053 * @pi: port information structure
5054 * @vsi_handle: software VSI handle
5055 * @tc_bitmap: TC bitmap
5056 * @max_rdmaqs: max RDMA queues array per TC
5057 *
5058 * This function adds/updates the VSI RDMA queues per TC.
5059 */
5060 int
ice_cfg_vsi_rdma(struct ice_port_info * pi,u16 vsi_handle,u16 tc_bitmap,u16 * max_rdmaqs)5061 ice_cfg_vsi_rdma(struct ice_port_info *pi, u16 vsi_handle, u16 tc_bitmap,
5062 u16 *max_rdmaqs)
5063 {
5064 return ice_cfg_vsi_qs(pi, vsi_handle, tc_bitmap, max_rdmaqs,
5065 ICE_SCHED_NODE_OWNER_RDMA);
5066 }
5067
5068 /**
5069 * ice_ena_vsi_rdma_qset
5070 * @pi: port information structure
5071 * @vsi_handle: software VSI handle
5072 * @tc: TC number
5073 * @rdma_qset: pointer to RDMA Qset
5074 * @num_qsets: number of RDMA Qsets
5075 * @qset_teid: pointer to Qset node TEIDs
5076 *
5077 * This function adds RDMA Qset
5078 */
5079 int
ice_ena_vsi_rdma_qset(struct ice_port_info * pi,u16 vsi_handle,u8 tc,u16 * rdma_qset,u16 num_qsets,u32 * qset_teid)5080 ice_ena_vsi_rdma_qset(struct ice_port_info *pi, u16 vsi_handle, u8 tc,
5081 u16 *rdma_qset, u16 num_qsets, u32 *qset_teid)
5082 {
5083 struct ice_aqc_txsched_elem_data node = { 0 };
5084 struct ice_aqc_add_rdma_qset_data *buf;
5085 struct ice_sched_node *parent;
5086 struct ice_hw *hw;
5087 u16 i, buf_size;
5088 int ret;
5089
5090 if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY)
5091 return -EIO;
5092 hw = pi->hw;
5093
5094 if (!ice_is_vsi_valid(hw, vsi_handle))
5095 return -EINVAL;
5096
5097 buf_size = struct_size(buf, rdma_qsets, num_qsets);
5098 buf = kzalloc(buf_size, GFP_KERNEL);
5099 if (!buf)
5100 return -ENOMEM;
5101 mutex_lock(&pi->sched_lock);
5102
5103 parent = ice_sched_get_free_qparent(pi, vsi_handle, tc,
5104 ICE_SCHED_NODE_OWNER_RDMA);
5105 if (!parent) {
5106 ret = -EINVAL;
5107 goto rdma_error_exit;
5108 }
5109 buf->parent_teid = parent->info.node_teid;
5110 node.parent_teid = parent->info.node_teid;
5111
5112 buf->num_qsets = cpu_to_le16(num_qsets);
5113 for (i = 0; i < num_qsets; i++) {
5114 buf->rdma_qsets[i].tx_qset_id = cpu_to_le16(rdma_qset[i]);
5115 buf->rdma_qsets[i].info.valid_sections =
5116 ICE_AQC_ELEM_VALID_GENERIC | ICE_AQC_ELEM_VALID_CIR |
5117 ICE_AQC_ELEM_VALID_EIR;
5118 buf->rdma_qsets[i].info.generic = 0;
5119 buf->rdma_qsets[i].info.cir_bw.bw_profile_idx =
5120 cpu_to_le16(ICE_SCHED_DFLT_RL_PROF_ID);
5121 buf->rdma_qsets[i].info.cir_bw.bw_alloc =
5122 cpu_to_le16(ICE_SCHED_DFLT_BW_WT);
5123 buf->rdma_qsets[i].info.eir_bw.bw_profile_idx =
5124 cpu_to_le16(ICE_SCHED_DFLT_RL_PROF_ID);
5125 buf->rdma_qsets[i].info.eir_bw.bw_alloc =
5126 cpu_to_le16(ICE_SCHED_DFLT_BW_WT);
5127 }
5128 ret = ice_aq_add_rdma_qsets(hw, 1, buf, buf_size, NULL);
5129 if (ret) {
5130 ice_debug(hw, ICE_DBG_RDMA, "add RDMA qset failed\n");
5131 goto rdma_error_exit;
5132 }
5133 node.data.elem_type = ICE_AQC_ELEM_TYPE_LEAF;
5134 for (i = 0; i < num_qsets; i++) {
5135 node.node_teid = buf->rdma_qsets[i].qset_teid;
5136 ret = ice_sched_add_node(pi, hw->num_tx_sched_layers - 1,
5137 &node, NULL);
5138 if (ret)
5139 break;
5140 qset_teid[i] = le32_to_cpu(node.node_teid);
5141 }
5142 rdma_error_exit:
5143 mutex_unlock(&pi->sched_lock);
5144 kfree(buf);
5145 return ret;
5146 }
5147
5148 /**
5149 * ice_dis_vsi_rdma_qset - free RDMA resources
5150 * @pi: port_info struct
5151 * @count: number of RDMA Qsets to free
5152 * @qset_teid: TEID of Qset node
5153 * @q_id: list of queue IDs being disabled
5154 */
5155 int
ice_dis_vsi_rdma_qset(struct ice_port_info * pi,u16 count,u32 * qset_teid,u16 * q_id)5156 ice_dis_vsi_rdma_qset(struct ice_port_info *pi, u16 count, u32 *qset_teid,
5157 u16 *q_id)
5158 {
5159 DEFINE_RAW_FLEX(struct ice_aqc_dis_txq_item, qg_list, q_id, 1);
5160 u16 qg_size = __struct_size(qg_list);
5161 struct ice_hw *hw;
5162 int status = 0;
5163 int i;
5164
5165 if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY)
5166 return -EIO;
5167
5168 hw = pi->hw;
5169
5170 mutex_lock(&pi->sched_lock);
5171
5172 for (i = 0; i < count; i++) {
5173 struct ice_sched_node *node;
5174
5175 node = ice_sched_find_node_by_teid(pi->root, qset_teid[i]);
5176 if (!node)
5177 continue;
5178
5179 qg_list->parent_teid = node->info.parent_teid;
5180 qg_list->num_qs = 1;
5181 qg_list->q_id[0] =
5182 cpu_to_le16(q_id[i] |
5183 ICE_AQC_Q_DIS_BUF_ELEM_TYPE_RDMA_QSET);
5184
5185 status = ice_aq_dis_lan_txq(hw, 1, qg_list, qg_size,
5186 ICE_NO_RESET, 0, NULL);
5187 if (status)
5188 break;
5189
5190 ice_free_sched_node(pi, node);
5191 }
5192
5193 mutex_unlock(&pi->sched_lock);
5194 return status;
5195 }
5196
5197 /**
5198 * ice_aq_get_cgu_abilities - get cgu abilities
5199 * @hw: pointer to the HW struct
5200 * @abilities: CGU abilities
5201 *
5202 * Get CGU abilities (0x0C61)
5203 * Return: 0 on success or negative value on failure.
5204 */
5205 int
ice_aq_get_cgu_abilities(struct ice_hw * hw,struct ice_aqc_get_cgu_abilities * abilities)5206 ice_aq_get_cgu_abilities(struct ice_hw *hw,
5207 struct ice_aqc_get_cgu_abilities *abilities)
5208 {
5209 struct ice_aq_desc desc;
5210
5211 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_cgu_abilities);
5212 return ice_aq_send_cmd(hw, &desc, abilities, sizeof(*abilities), NULL);
5213 }
5214
5215 /**
5216 * ice_aq_set_input_pin_cfg - set input pin config
5217 * @hw: pointer to the HW struct
5218 * @input_idx: Input index
5219 * @flags1: Input flags
5220 * @flags2: Input flags
5221 * @freq: Frequency in Hz
5222 * @phase_delay: Delay in ps
5223 *
5224 * Set CGU input config (0x0C62)
5225 * Return: 0 on success or negative value on failure.
5226 */
5227 int
ice_aq_set_input_pin_cfg(struct ice_hw * hw,u8 input_idx,u8 flags1,u8 flags2,u32 freq,s32 phase_delay)5228 ice_aq_set_input_pin_cfg(struct ice_hw *hw, u8 input_idx, u8 flags1, u8 flags2,
5229 u32 freq, s32 phase_delay)
5230 {
5231 struct ice_aqc_set_cgu_input_config *cmd;
5232 struct ice_aq_desc desc;
5233
5234 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_cgu_input_config);
5235 cmd = &desc.params.set_cgu_input_config;
5236 cmd->input_idx = input_idx;
5237 cmd->flags1 = flags1;
5238 cmd->flags2 = flags2;
5239 cmd->freq = cpu_to_le32(freq);
5240 cmd->phase_delay = cpu_to_le32(phase_delay);
5241
5242 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL);
5243 }
5244
5245 /**
5246 * ice_aq_get_input_pin_cfg - get input pin config
5247 * @hw: pointer to the HW struct
5248 * @input_idx: Input index
5249 * @status: Pin status
5250 * @type: Pin type
5251 * @flags1: Input flags
5252 * @flags2: Input flags
5253 * @freq: Frequency in Hz
5254 * @phase_delay: Delay in ps
5255 *
5256 * Get CGU input config (0x0C63)
5257 * Return: 0 on success or negative value on failure.
5258 */
5259 int
ice_aq_get_input_pin_cfg(struct ice_hw * hw,u8 input_idx,u8 * status,u8 * type,u8 * flags1,u8 * flags2,u32 * freq,s32 * phase_delay)5260 ice_aq_get_input_pin_cfg(struct ice_hw *hw, u8 input_idx, u8 *status, u8 *type,
5261 u8 *flags1, u8 *flags2, u32 *freq, s32 *phase_delay)
5262 {
5263 struct ice_aqc_get_cgu_input_config *cmd;
5264 struct ice_aq_desc desc;
5265 int ret;
5266
5267 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_cgu_input_config);
5268 cmd = &desc.params.get_cgu_input_config;
5269 cmd->input_idx = input_idx;
5270
5271 ret = ice_aq_send_cmd(hw, &desc, NULL, 0, NULL);
5272 if (!ret) {
5273 if (status)
5274 *status = cmd->status;
5275 if (type)
5276 *type = cmd->type;
5277 if (flags1)
5278 *flags1 = cmd->flags1;
5279 if (flags2)
5280 *flags2 = cmd->flags2;
5281 if (freq)
5282 *freq = le32_to_cpu(cmd->freq);
5283 if (phase_delay)
5284 *phase_delay = le32_to_cpu(cmd->phase_delay);
5285 }
5286
5287 return ret;
5288 }
5289
5290 /**
5291 * ice_aq_set_output_pin_cfg - set output pin config
5292 * @hw: pointer to the HW struct
5293 * @output_idx: Output index
5294 * @flags: Output flags
5295 * @src_sel: Index of DPLL block
5296 * @freq: Output frequency
5297 * @phase_delay: Output phase compensation
5298 *
5299 * Set CGU output config (0x0C64)
5300 * Return: 0 on success or negative value on failure.
5301 */
5302 int
ice_aq_set_output_pin_cfg(struct ice_hw * hw,u8 output_idx,u8 flags,u8 src_sel,u32 freq,s32 phase_delay)5303 ice_aq_set_output_pin_cfg(struct ice_hw *hw, u8 output_idx, u8 flags,
5304 u8 src_sel, u32 freq, s32 phase_delay)
5305 {
5306 struct ice_aqc_set_cgu_output_config *cmd;
5307 struct ice_aq_desc desc;
5308
5309 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_cgu_output_config);
5310 cmd = &desc.params.set_cgu_output_config;
5311 cmd->output_idx = output_idx;
5312 cmd->flags = flags;
5313 cmd->src_sel = src_sel;
5314 cmd->freq = cpu_to_le32(freq);
5315 cmd->phase_delay = cpu_to_le32(phase_delay);
5316
5317 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL);
5318 }
5319
5320 /**
5321 * ice_aq_get_output_pin_cfg - get output pin config
5322 * @hw: pointer to the HW struct
5323 * @output_idx: Output index
5324 * @flags: Output flags
5325 * @src_sel: Internal DPLL source
5326 * @freq: Output frequency
5327 * @src_freq: Source frequency
5328 *
5329 * Get CGU output config (0x0C65)
5330 * Return: 0 on success or negative value on failure.
5331 */
5332 int
ice_aq_get_output_pin_cfg(struct ice_hw * hw,u8 output_idx,u8 * flags,u8 * src_sel,u32 * freq,u32 * src_freq)5333 ice_aq_get_output_pin_cfg(struct ice_hw *hw, u8 output_idx, u8 *flags,
5334 u8 *src_sel, u32 *freq, u32 *src_freq)
5335 {
5336 struct ice_aqc_get_cgu_output_config *cmd;
5337 struct ice_aq_desc desc;
5338 int ret;
5339
5340 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_cgu_output_config);
5341 cmd = &desc.params.get_cgu_output_config;
5342 cmd->output_idx = output_idx;
5343
5344 ret = ice_aq_send_cmd(hw, &desc, NULL, 0, NULL);
5345 if (!ret) {
5346 if (flags)
5347 *flags = cmd->flags;
5348 if (src_sel)
5349 *src_sel = cmd->src_sel;
5350 if (freq)
5351 *freq = le32_to_cpu(cmd->freq);
5352 if (src_freq)
5353 *src_freq = le32_to_cpu(cmd->src_freq);
5354 }
5355
5356 return ret;
5357 }
5358
5359 /**
5360 * ice_aq_get_cgu_dpll_status - get dpll status
5361 * @hw: pointer to the HW struct
5362 * @dpll_num: DPLL index
5363 * @ref_state: Reference clock state
5364 * @config: current DPLL config
5365 * @dpll_state: current DPLL state
5366 * @phase_offset: Phase offset in ns
5367 * @eec_mode: EEC_mode
5368 *
5369 * Get CGU DPLL status (0x0C66)
5370 * Return: 0 on success or negative value on failure.
5371 */
5372 int
ice_aq_get_cgu_dpll_status(struct ice_hw * hw,u8 dpll_num,u8 * ref_state,u8 * dpll_state,u8 * config,s64 * phase_offset,u8 * eec_mode)5373 ice_aq_get_cgu_dpll_status(struct ice_hw *hw, u8 dpll_num, u8 *ref_state,
5374 u8 *dpll_state, u8 *config, s64 *phase_offset,
5375 u8 *eec_mode)
5376 {
5377 struct ice_aqc_get_cgu_dpll_status *cmd;
5378 struct ice_aq_desc desc;
5379 int status;
5380
5381 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_cgu_dpll_status);
5382 cmd = &desc.params.get_cgu_dpll_status;
5383 cmd->dpll_num = dpll_num;
5384
5385 status = ice_aq_send_cmd(hw, &desc, NULL, 0, NULL);
5386 if (!status) {
5387 *ref_state = cmd->ref_state;
5388 *dpll_state = cmd->dpll_state;
5389 *config = cmd->config;
5390 *phase_offset = le32_to_cpu(cmd->phase_offset_h);
5391 *phase_offset <<= 32;
5392 *phase_offset += le32_to_cpu(cmd->phase_offset_l);
5393 *phase_offset = sign_extend64(*phase_offset, 47);
5394 *eec_mode = cmd->eec_mode;
5395 }
5396
5397 return status;
5398 }
5399
5400 /**
5401 * ice_aq_set_cgu_dpll_config - set dpll config
5402 * @hw: pointer to the HW struct
5403 * @dpll_num: DPLL index
5404 * @ref_state: Reference clock state
5405 * @config: DPLL config
5406 * @eec_mode: EEC mode
5407 *
5408 * Set CGU DPLL config (0x0C67)
5409 * Return: 0 on success or negative value on failure.
5410 */
5411 int
ice_aq_set_cgu_dpll_config(struct ice_hw * hw,u8 dpll_num,u8 ref_state,u8 config,u8 eec_mode)5412 ice_aq_set_cgu_dpll_config(struct ice_hw *hw, u8 dpll_num, u8 ref_state,
5413 u8 config, u8 eec_mode)
5414 {
5415 struct ice_aqc_set_cgu_dpll_config *cmd;
5416 struct ice_aq_desc desc;
5417
5418 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_cgu_dpll_config);
5419 cmd = &desc.params.set_cgu_dpll_config;
5420 cmd->dpll_num = dpll_num;
5421 cmd->ref_state = ref_state;
5422 cmd->config = config;
5423 cmd->eec_mode = eec_mode;
5424
5425 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL);
5426 }
5427
5428 /**
5429 * ice_aq_set_cgu_ref_prio - set input reference priority
5430 * @hw: pointer to the HW struct
5431 * @dpll_num: DPLL index
5432 * @ref_idx: Reference pin index
5433 * @ref_priority: Reference input priority
5434 *
5435 * Set CGU reference priority (0x0C68)
5436 * Return: 0 on success or negative value on failure.
5437 */
5438 int
ice_aq_set_cgu_ref_prio(struct ice_hw * hw,u8 dpll_num,u8 ref_idx,u8 ref_priority)5439 ice_aq_set_cgu_ref_prio(struct ice_hw *hw, u8 dpll_num, u8 ref_idx,
5440 u8 ref_priority)
5441 {
5442 struct ice_aqc_set_cgu_ref_prio *cmd;
5443 struct ice_aq_desc desc;
5444
5445 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_cgu_ref_prio);
5446 cmd = &desc.params.set_cgu_ref_prio;
5447 cmd->dpll_num = dpll_num;
5448 cmd->ref_idx = ref_idx;
5449 cmd->ref_priority = ref_priority;
5450
5451 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL);
5452 }
5453
5454 /**
5455 * ice_aq_get_cgu_ref_prio - get input reference priority
5456 * @hw: pointer to the HW struct
5457 * @dpll_num: DPLL index
5458 * @ref_idx: Reference pin index
5459 * @ref_prio: Reference input priority
5460 *
5461 * Get CGU reference priority (0x0C69)
5462 * Return: 0 on success or negative value on failure.
5463 */
5464 int
ice_aq_get_cgu_ref_prio(struct ice_hw * hw,u8 dpll_num,u8 ref_idx,u8 * ref_prio)5465 ice_aq_get_cgu_ref_prio(struct ice_hw *hw, u8 dpll_num, u8 ref_idx,
5466 u8 *ref_prio)
5467 {
5468 struct ice_aqc_get_cgu_ref_prio *cmd;
5469 struct ice_aq_desc desc;
5470 int status;
5471
5472 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_cgu_ref_prio);
5473 cmd = &desc.params.get_cgu_ref_prio;
5474 cmd->dpll_num = dpll_num;
5475 cmd->ref_idx = ref_idx;
5476
5477 status = ice_aq_send_cmd(hw, &desc, NULL, 0, NULL);
5478 if (!status)
5479 *ref_prio = cmd->ref_priority;
5480
5481 return status;
5482 }
5483
5484 /**
5485 * ice_aq_get_cgu_info - get cgu info
5486 * @hw: pointer to the HW struct
5487 * @cgu_id: CGU ID
5488 * @cgu_cfg_ver: CGU config version
5489 * @cgu_fw_ver: CGU firmware version
5490 *
5491 * Get CGU info (0x0C6A)
5492 * Return: 0 on success or negative value on failure.
5493 */
5494 int
ice_aq_get_cgu_info(struct ice_hw * hw,u32 * cgu_id,u32 * cgu_cfg_ver,u32 * cgu_fw_ver)5495 ice_aq_get_cgu_info(struct ice_hw *hw, u32 *cgu_id, u32 *cgu_cfg_ver,
5496 u32 *cgu_fw_ver)
5497 {
5498 struct ice_aqc_get_cgu_info *cmd;
5499 struct ice_aq_desc desc;
5500 int status;
5501
5502 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_cgu_info);
5503 cmd = &desc.params.get_cgu_info;
5504
5505 status = ice_aq_send_cmd(hw, &desc, NULL, 0, NULL);
5506 if (!status) {
5507 *cgu_id = le32_to_cpu(cmd->cgu_id);
5508 *cgu_cfg_ver = le32_to_cpu(cmd->cgu_cfg_ver);
5509 *cgu_fw_ver = le32_to_cpu(cmd->cgu_fw_ver);
5510 }
5511
5512 return status;
5513 }
5514
5515 /**
5516 * ice_aq_set_phy_rec_clk_out - set RCLK phy out
5517 * @hw: pointer to the HW struct
5518 * @phy_output: PHY reference clock output pin
5519 * @enable: GPIO state to be applied
5520 * @freq: PHY output frequency
5521 *
5522 * Set phy recovered clock as reference (0x0630)
5523 * Return: 0 on success or negative value on failure.
5524 */
5525 int
ice_aq_set_phy_rec_clk_out(struct ice_hw * hw,u8 phy_output,bool enable,u32 * freq)5526 ice_aq_set_phy_rec_clk_out(struct ice_hw *hw, u8 phy_output, bool enable,
5527 u32 *freq)
5528 {
5529 struct ice_aqc_set_phy_rec_clk_out *cmd;
5530 struct ice_aq_desc desc;
5531 int status;
5532
5533 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_phy_rec_clk_out);
5534 cmd = &desc.params.set_phy_rec_clk_out;
5535 cmd->phy_output = phy_output;
5536 cmd->port_num = ICE_AQC_SET_PHY_REC_CLK_OUT_CURR_PORT;
5537 cmd->flags = enable & ICE_AQC_SET_PHY_REC_CLK_OUT_OUT_EN;
5538 cmd->freq = cpu_to_le32(*freq);
5539
5540 status = ice_aq_send_cmd(hw, &desc, NULL, 0, NULL);
5541 if (!status)
5542 *freq = le32_to_cpu(cmd->freq);
5543
5544 return status;
5545 }
5546
5547 /**
5548 * ice_aq_get_phy_rec_clk_out - get phy recovered signal info
5549 * @hw: pointer to the HW struct
5550 * @phy_output: PHY reference clock output pin
5551 * @port_num: Port number
5552 * @flags: PHY flags
5553 * @node_handle: PHY output frequency
5554 *
5555 * Get PHY recovered clock output info (0x0631)
5556 * Return: 0 on success or negative value on failure.
5557 */
5558 int
ice_aq_get_phy_rec_clk_out(struct ice_hw * hw,u8 * phy_output,u8 * port_num,u8 * flags,u16 * node_handle)5559 ice_aq_get_phy_rec_clk_out(struct ice_hw *hw, u8 *phy_output, u8 *port_num,
5560 u8 *flags, u16 *node_handle)
5561 {
5562 struct ice_aqc_get_phy_rec_clk_out *cmd;
5563 struct ice_aq_desc desc;
5564 int status;
5565
5566 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_phy_rec_clk_out);
5567 cmd = &desc.params.get_phy_rec_clk_out;
5568 cmd->phy_output = *phy_output;
5569
5570 status = ice_aq_send_cmd(hw, &desc, NULL, 0, NULL);
5571 if (!status) {
5572 *phy_output = cmd->phy_output;
5573 if (port_num)
5574 *port_num = cmd->port_num;
5575 if (flags)
5576 *flags = cmd->flags;
5577 if (node_handle)
5578 *node_handle = le16_to_cpu(cmd->node_handle);
5579 }
5580
5581 return status;
5582 }
5583
5584 /**
5585 * ice_aq_get_sensor_reading
5586 * @hw: pointer to the HW struct
5587 * @data: pointer to data to be read from the sensor
5588 *
5589 * Get sensor reading (0x0632)
5590 */
ice_aq_get_sensor_reading(struct ice_hw * hw,struct ice_aqc_get_sensor_reading_resp * data)5591 int ice_aq_get_sensor_reading(struct ice_hw *hw,
5592 struct ice_aqc_get_sensor_reading_resp *data)
5593 {
5594 struct ice_aqc_get_sensor_reading *cmd;
5595 struct ice_aq_desc desc;
5596 int status;
5597
5598 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_sensor_reading);
5599 cmd = &desc.params.get_sensor_reading;
5600 #define ICE_INTERNAL_TEMP_SENSOR_FORMAT 0
5601 #define ICE_INTERNAL_TEMP_SENSOR 0
5602 cmd->sensor = ICE_INTERNAL_TEMP_SENSOR;
5603 cmd->format = ICE_INTERNAL_TEMP_SENSOR_FORMAT;
5604
5605 status = ice_aq_send_cmd(hw, &desc, NULL, 0, NULL);
5606 if (!status)
5607 memcpy(data, &desc.params.get_sensor_reading_resp,
5608 sizeof(*data));
5609
5610 return status;
5611 }
5612
5613 /**
5614 * ice_replay_pre_init - replay pre initialization
5615 * @hw: pointer to the HW struct
5616 *
5617 * Initializes required config data for VSI, FD, ACL, and RSS before replay.
5618 */
ice_replay_pre_init(struct ice_hw * hw)5619 static int ice_replay_pre_init(struct ice_hw *hw)
5620 {
5621 struct ice_switch_info *sw = hw->switch_info;
5622 u8 i;
5623
5624 /* Delete old entries from replay filter list head if there is any */
5625 ice_rm_all_sw_replay_rule_info(hw);
5626 /* In start of replay, move entries into replay_rules list, it
5627 * will allow adding rules entries back to filt_rules list,
5628 * which is operational list.
5629 */
5630 for (i = 0; i < ICE_MAX_NUM_RECIPES; i++)
5631 list_replace_init(&sw->recp_list[i].filt_rules,
5632 &sw->recp_list[i].filt_replay_rules);
5633 ice_sched_replay_agg_vsi_preinit(hw);
5634
5635 return 0;
5636 }
5637
5638 /**
5639 * ice_replay_vsi - replay VSI configuration
5640 * @hw: pointer to the HW struct
5641 * @vsi_handle: driver VSI handle
5642 *
5643 * Restore all VSI configuration after reset. It is required to call this
5644 * function with main VSI first.
5645 */
ice_replay_vsi(struct ice_hw * hw,u16 vsi_handle)5646 int ice_replay_vsi(struct ice_hw *hw, u16 vsi_handle)
5647 {
5648 int status;
5649
5650 if (!ice_is_vsi_valid(hw, vsi_handle))
5651 return -EINVAL;
5652
5653 /* Replay pre-initialization if there is any */
5654 if (vsi_handle == ICE_MAIN_VSI_HANDLE) {
5655 status = ice_replay_pre_init(hw);
5656 if (status)
5657 return status;
5658 }
5659 /* Replay per VSI all RSS configurations */
5660 status = ice_replay_rss_cfg(hw, vsi_handle);
5661 if (status)
5662 return status;
5663 /* Replay per VSI all filters */
5664 status = ice_replay_vsi_all_fltr(hw, vsi_handle);
5665 if (!status)
5666 status = ice_replay_vsi_agg(hw, vsi_handle);
5667 return status;
5668 }
5669
5670 /**
5671 * ice_replay_post - post replay configuration cleanup
5672 * @hw: pointer to the HW struct
5673 *
5674 * Post replay cleanup.
5675 */
ice_replay_post(struct ice_hw * hw)5676 void ice_replay_post(struct ice_hw *hw)
5677 {
5678 /* Delete old entries from replay filter list head */
5679 ice_rm_all_sw_replay_rule_info(hw);
5680 ice_sched_replay_agg(hw);
5681 }
5682
5683 /**
5684 * ice_stat_update40 - read 40 bit stat from the chip and update stat values
5685 * @hw: ptr to the hardware info
5686 * @reg: offset of 64 bit HW register to read from
5687 * @prev_stat_loaded: bool to specify if previous stats are loaded
5688 * @prev_stat: ptr to previous loaded stat value
5689 * @cur_stat: ptr to current stat value
5690 */
5691 void
ice_stat_update40(struct ice_hw * hw,u32 reg,bool prev_stat_loaded,u64 * prev_stat,u64 * cur_stat)5692 ice_stat_update40(struct ice_hw *hw, u32 reg, bool prev_stat_loaded,
5693 u64 *prev_stat, u64 *cur_stat)
5694 {
5695 u64 new_data = rd64(hw, reg) & (BIT_ULL(40) - 1);
5696
5697 /* device stats are not reset at PFR, they likely will not be zeroed
5698 * when the driver starts. Thus, save the value from the first read
5699 * without adding to the statistic value so that we report stats which
5700 * count up from zero.
5701 */
5702 if (!prev_stat_loaded) {
5703 *prev_stat = new_data;
5704 return;
5705 }
5706
5707 /* Calculate the difference between the new and old values, and then
5708 * add it to the software stat value.
5709 */
5710 if (new_data >= *prev_stat)
5711 *cur_stat += new_data - *prev_stat;
5712 else
5713 /* to manage the potential roll-over */
5714 *cur_stat += (new_data + BIT_ULL(40)) - *prev_stat;
5715
5716 /* Update the previously stored value to prepare for next read */
5717 *prev_stat = new_data;
5718 }
5719
5720 /**
5721 * ice_stat_update32 - read 32 bit stat from the chip and update stat values
5722 * @hw: ptr to the hardware info
5723 * @reg: offset of HW register to read from
5724 * @prev_stat_loaded: bool to specify if previous stats are loaded
5725 * @prev_stat: ptr to previous loaded stat value
5726 * @cur_stat: ptr to current stat value
5727 */
5728 void
ice_stat_update32(struct ice_hw * hw,u32 reg,bool prev_stat_loaded,u64 * prev_stat,u64 * cur_stat)5729 ice_stat_update32(struct ice_hw *hw, u32 reg, bool prev_stat_loaded,
5730 u64 *prev_stat, u64 *cur_stat)
5731 {
5732 u32 new_data;
5733
5734 new_data = rd32(hw, reg);
5735
5736 /* device stats are not reset at PFR, they likely will not be zeroed
5737 * when the driver starts. Thus, save the value from the first read
5738 * without adding to the statistic value so that we report stats which
5739 * count up from zero.
5740 */
5741 if (!prev_stat_loaded) {
5742 *prev_stat = new_data;
5743 return;
5744 }
5745
5746 /* Calculate the difference between the new and old values, and then
5747 * add it to the software stat value.
5748 */
5749 if (new_data >= *prev_stat)
5750 *cur_stat += new_data - *prev_stat;
5751 else
5752 /* to manage the potential roll-over */
5753 *cur_stat += (new_data + BIT_ULL(32)) - *prev_stat;
5754
5755 /* Update the previously stored value to prepare for next read */
5756 *prev_stat = new_data;
5757 }
5758
5759 /**
5760 * ice_sched_query_elem - query element information from HW
5761 * @hw: pointer to the HW struct
5762 * @node_teid: node TEID to be queried
5763 * @buf: buffer to element information
5764 *
5765 * This function queries HW element information
5766 */
5767 int
ice_sched_query_elem(struct ice_hw * hw,u32 node_teid,struct ice_aqc_txsched_elem_data * buf)5768 ice_sched_query_elem(struct ice_hw *hw, u32 node_teid,
5769 struct ice_aqc_txsched_elem_data *buf)
5770 {
5771 u16 buf_size, num_elem_ret = 0;
5772 int status;
5773
5774 buf_size = sizeof(*buf);
5775 memset(buf, 0, buf_size);
5776 buf->node_teid = cpu_to_le32(node_teid);
5777 status = ice_aq_query_sched_elems(hw, 1, buf, buf_size, &num_elem_ret,
5778 NULL);
5779 if (status || num_elem_ret != 1)
5780 ice_debug(hw, ICE_DBG_SCHED, "query element failed\n");
5781 return status;
5782 }
5783
5784 /**
5785 * ice_aq_read_i2c
5786 * @hw: pointer to the hw struct
5787 * @topo_addr: topology address for a device to communicate with
5788 * @bus_addr: 7-bit I2C bus address
5789 * @addr: I2C memory address (I2C offset) with up to 16 bits
5790 * @params: I2C parameters: bit [7] - Repeated start,
5791 * bits [6:5] data offset size,
5792 * bit [4] - I2C address type,
5793 * bits [3:0] - data size to read (0-16 bytes)
5794 * @data: pointer to data (0 to 16 bytes) to be read from the I2C device
5795 * @cd: pointer to command details structure or NULL
5796 *
5797 * Read I2C (0x06E2)
5798 */
5799 int
ice_aq_read_i2c(struct ice_hw * hw,struct ice_aqc_link_topo_addr topo_addr,u16 bus_addr,__le16 addr,u8 params,u8 * data,struct ice_sq_cd * cd)5800 ice_aq_read_i2c(struct ice_hw *hw, struct ice_aqc_link_topo_addr topo_addr,
5801 u16 bus_addr, __le16 addr, u8 params, u8 *data,
5802 struct ice_sq_cd *cd)
5803 {
5804 struct ice_aq_desc desc = { 0 };
5805 struct ice_aqc_i2c *cmd;
5806 u8 data_size;
5807 int status;
5808
5809 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_read_i2c);
5810 cmd = &desc.params.read_write_i2c;
5811
5812 if (!data)
5813 return -EINVAL;
5814
5815 data_size = FIELD_GET(ICE_AQC_I2C_DATA_SIZE_M, params);
5816
5817 cmd->i2c_bus_addr = cpu_to_le16(bus_addr);
5818 cmd->topo_addr = topo_addr;
5819 cmd->i2c_params = params;
5820 cmd->i2c_addr = addr;
5821
5822 status = ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
5823 if (!status) {
5824 struct ice_aqc_read_i2c_resp *resp;
5825 u8 i;
5826
5827 resp = &desc.params.read_i2c_resp;
5828 for (i = 0; i < data_size; i++) {
5829 *data = resp->i2c_data[i];
5830 data++;
5831 }
5832 }
5833
5834 return status;
5835 }
5836
5837 /**
5838 * ice_aq_write_i2c
5839 * @hw: pointer to the hw struct
5840 * @topo_addr: topology address for a device to communicate with
5841 * @bus_addr: 7-bit I2C bus address
5842 * @addr: I2C memory address (I2C offset) with up to 16 bits
5843 * @params: I2C parameters: bit [4] - I2C address type, bits [3:0] - data size to write (0-7 bytes)
5844 * @data: pointer to data (0 to 4 bytes) to be written to the I2C device
5845 * @cd: pointer to command details structure or NULL
5846 *
5847 * Write I2C (0x06E3)
5848 *
5849 * * Return:
5850 * * 0 - Successful write to the i2c device
5851 * * -EINVAL - Data size greater than 4 bytes
5852 * * -EIO - FW error
5853 */
5854 int
ice_aq_write_i2c(struct ice_hw * hw,struct ice_aqc_link_topo_addr topo_addr,u16 bus_addr,__le16 addr,u8 params,const u8 * data,struct ice_sq_cd * cd)5855 ice_aq_write_i2c(struct ice_hw *hw, struct ice_aqc_link_topo_addr topo_addr,
5856 u16 bus_addr, __le16 addr, u8 params, const u8 *data,
5857 struct ice_sq_cd *cd)
5858 {
5859 struct ice_aq_desc desc = { 0 };
5860 struct ice_aqc_i2c *cmd;
5861 u8 data_size;
5862
5863 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_write_i2c);
5864 cmd = &desc.params.read_write_i2c;
5865
5866 data_size = FIELD_GET(ICE_AQC_I2C_DATA_SIZE_M, params);
5867
5868 /* data_size limited to 4 */
5869 if (data_size > 4)
5870 return -EINVAL;
5871
5872 cmd->i2c_bus_addr = cpu_to_le16(bus_addr);
5873 cmd->topo_addr = topo_addr;
5874 cmd->i2c_params = params;
5875 cmd->i2c_addr = addr;
5876
5877 memcpy(cmd->i2c_data, data, data_size);
5878
5879 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
5880 }
5881
5882 /**
5883 * ice_aq_set_gpio
5884 * @hw: pointer to the hw struct
5885 * @gpio_ctrl_handle: GPIO controller node handle
5886 * @pin_idx: IO Number of the GPIO that needs to be set
5887 * @value: SW provide IO value to set in the LSB
5888 * @cd: pointer to command details structure or NULL
5889 *
5890 * Sends 0x06EC AQ command to set the GPIO pin state that's part of the topology
5891 */
5892 int
ice_aq_set_gpio(struct ice_hw * hw,u16 gpio_ctrl_handle,u8 pin_idx,bool value,struct ice_sq_cd * cd)5893 ice_aq_set_gpio(struct ice_hw *hw, u16 gpio_ctrl_handle, u8 pin_idx, bool value,
5894 struct ice_sq_cd *cd)
5895 {
5896 struct ice_aqc_gpio *cmd;
5897 struct ice_aq_desc desc;
5898
5899 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_gpio);
5900 cmd = &desc.params.read_write_gpio;
5901 cmd->gpio_ctrl_handle = cpu_to_le16(gpio_ctrl_handle);
5902 cmd->gpio_num = pin_idx;
5903 cmd->gpio_val = value ? 1 : 0;
5904
5905 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
5906 }
5907
5908 /**
5909 * ice_aq_get_gpio
5910 * @hw: pointer to the hw struct
5911 * @gpio_ctrl_handle: GPIO controller node handle
5912 * @pin_idx: IO Number of the GPIO that needs to be set
5913 * @value: IO value read
5914 * @cd: pointer to command details structure or NULL
5915 *
5916 * Sends 0x06ED AQ command to get the value of a GPIO signal which is part of
5917 * the topology
5918 */
5919 int
ice_aq_get_gpio(struct ice_hw * hw,u16 gpio_ctrl_handle,u8 pin_idx,bool * value,struct ice_sq_cd * cd)5920 ice_aq_get_gpio(struct ice_hw *hw, u16 gpio_ctrl_handle, u8 pin_idx,
5921 bool *value, struct ice_sq_cd *cd)
5922 {
5923 struct ice_aqc_gpio *cmd;
5924 struct ice_aq_desc desc;
5925 int status;
5926
5927 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_gpio);
5928 cmd = &desc.params.read_write_gpio;
5929 cmd->gpio_ctrl_handle = cpu_to_le16(gpio_ctrl_handle);
5930 cmd->gpio_num = pin_idx;
5931
5932 status = ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
5933 if (status)
5934 return status;
5935
5936 *value = !!cmd->gpio_val;
5937 return 0;
5938 }
5939
5940 /**
5941 * ice_is_fw_api_min_ver
5942 * @hw: pointer to the hardware structure
5943 * @maj: major version
5944 * @min: minor version
5945 * @patch: patch version
5946 *
5947 * Checks if the firmware API is minimum version
5948 */
ice_is_fw_api_min_ver(struct ice_hw * hw,u8 maj,u8 min,u8 patch)5949 static bool ice_is_fw_api_min_ver(struct ice_hw *hw, u8 maj, u8 min, u8 patch)
5950 {
5951 if (hw->api_maj_ver == maj) {
5952 if (hw->api_min_ver > min)
5953 return true;
5954 if (hw->api_min_ver == min && hw->api_patch >= patch)
5955 return true;
5956 } else if (hw->api_maj_ver > maj) {
5957 return true;
5958 }
5959
5960 return false;
5961 }
5962
5963 /**
5964 * ice_fw_supports_link_override
5965 * @hw: pointer to the hardware structure
5966 *
5967 * Checks if the firmware supports link override
5968 */
ice_fw_supports_link_override(struct ice_hw * hw)5969 bool ice_fw_supports_link_override(struct ice_hw *hw)
5970 {
5971 return ice_is_fw_api_min_ver(hw, ICE_FW_API_LINK_OVERRIDE_MAJ,
5972 ICE_FW_API_LINK_OVERRIDE_MIN,
5973 ICE_FW_API_LINK_OVERRIDE_PATCH);
5974 }
5975
5976 /**
5977 * ice_get_link_default_override
5978 * @ldo: pointer to the link default override struct
5979 * @pi: pointer to the port info struct
5980 *
5981 * Gets the link default override for a port
5982 */
5983 int
ice_get_link_default_override(struct ice_link_default_override_tlv * ldo,struct ice_port_info * pi)5984 ice_get_link_default_override(struct ice_link_default_override_tlv *ldo,
5985 struct ice_port_info *pi)
5986 {
5987 u16 i, tlv, tlv_len, tlv_start, buf, offset;
5988 struct ice_hw *hw = pi->hw;
5989 int status;
5990
5991 status = ice_get_pfa_module_tlv(hw, &tlv, &tlv_len,
5992 ICE_SR_LINK_DEFAULT_OVERRIDE_PTR);
5993 if (status) {
5994 ice_debug(hw, ICE_DBG_INIT, "Failed to read link override TLV.\n");
5995 return status;
5996 }
5997
5998 /* Each port has its own config; calculate for our port */
5999 tlv_start = tlv + pi->lport * ICE_SR_PFA_LINK_OVERRIDE_WORDS +
6000 ICE_SR_PFA_LINK_OVERRIDE_OFFSET;
6001
6002 /* link options first */
6003 status = ice_read_sr_word(hw, tlv_start, &buf);
6004 if (status) {
6005 ice_debug(hw, ICE_DBG_INIT, "Failed to read override link options.\n");
6006 return status;
6007 }
6008 ldo->options = FIELD_GET(ICE_LINK_OVERRIDE_OPT_M, buf);
6009 ldo->phy_config = (buf & ICE_LINK_OVERRIDE_PHY_CFG_M) >>
6010 ICE_LINK_OVERRIDE_PHY_CFG_S;
6011
6012 /* link PHY config */
6013 offset = tlv_start + ICE_SR_PFA_LINK_OVERRIDE_FEC_OFFSET;
6014 status = ice_read_sr_word(hw, offset, &buf);
6015 if (status) {
6016 ice_debug(hw, ICE_DBG_INIT, "Failed to read override phy config.\n");
6017 return status;
6018 }
6019 ldo->fec_options = buf & ICE_LINK_OVERRIDE_FEC_OPT_M;
6020
6021 /* PHY types low */
6022 offset = tlv_start + ICE_SR_PFA_LINK_OVERRIDE_PHY_OFFSET;
6023 for (i = 0; i < ICE_SR_PFA_LINK_OVERRIDE_PHY_WORDS; i++) {
6024 status = ice_read_sr_word(hw, (offset + i), &buf);
6025 if (status) {
6026 ice_debug(hw, ICE_DBG_INIT, "Failed to read override link options.\n");
6027 return status;
6028 }
6029 /* shift 16 bits at a time to fill 64 bits */
6030 ldo->phy_type_low |= ((u64)buf << (i * 16));
6031 }
6032
6033 /* PHY types high */
6034 offset = tlv_start + ICE_SR_PFA_LINK_OVERRIDE_PHY_OFFSET +
6035 ICE_SR_PFA_LINK_OVERRIDE_PHY_WORDS;
6036 for (i = 0; i < ICE_SR_PFA_LINK_OVERRIDE_PHY_WORDS; i++) {
6037 status = ice_read_sr_word(hw, (offset + i), &buf);
6038 if (status) {
6039 ice_debug(hw, ICE_DBG_INIT, "Failed to read override link options.\n");
6040 return status;
6041 }
6042 /* shift 16 bits at a time to fill 64 bits */
6043 ldo->phy_type_high |= ((u64)buf << (i * 16));
6044 }
6045
6046 return status;
6047 }
6048
6049 /**
6050 * ice_is_phy_caps_an_enabled - check if PHY capabilities autoneg is enabled
6051 * @caps: get PHY capability data
6052 */
ice_is_phy_caps_an_enabled(struct ice_aqc_get_phy_caps_data * caps)6053 bool ice_is_phy_caps_an_enabled(struct ice_aqc_get_phy_caps_data *caps)
6054 {
6055 if (caps->caps & ICE_AQC_PHY_AN_MODE ||
6056 caps->low_power_ctrl_an & (ICE_AQC_PHY_AN_EN_CLAUSE28 |
6057 ICE_AQC_PHY_AN_EN_CLAUSE73 |
6058 ICE_AQC_PHY_AN_EN_CLAUSE37))
6059 return true;
6060
6061 return false;
6062 }
6063
6064 /**
6065 * ice_aq_set_lldp_mib - Set the LLDP MIB
6066 * @hw: pointer to the HW struct
6067 * @mib_type: Local, Remote or both Local and Remote MIBs
6068 * @buf: pointer to the caller-supplied buffer to store the MIB block
6069 * @buf_size: size of the buffer (in bytes)
6070 * @cd: pointer to command details structure or NULL
6071 *
6072 * Set the LLDP MIB. (0x0A08)
6073 */
6074 int
ice_aq_set_lldp_mib(struct ice_hw * hw,u8 mib_type,void * buf,u16 buf_size,struct ice_sq_cd * cd)6075 ice_aq_set_lldp_mib(struct ice_hw *hw, u8 mib_type, void *buf, u16 buf_size,
6076 struct ice_sq_cd *cd)
6077 {
6078 struct ice_aqc_lldp_set_local_mib *cmd;
6079 struct ice_aq_desc desc;
6080
6081 cmd = &desc.params.lldp_set_mib;
6082
6083 if (buf_size == 0 || !buf)
6084 return -EINVAL;
6085
6086 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_lldp_set_local_mib);
6087
6088 desc.flags |= cpu_to_le16((u16)ICE_AQ_FLAG_RD);
6089 desc.datalen = cpu_to_le16(buf_size);
6090
6091 cmd->type = mib_type;
6092 cmd->length = cpu_to_le16(buf_size);
6093
6094 return ice_aq_send_cmd(hw, &desc, buf, buf_size, cd);
6095 }
6096
6097 /**
6098 * ice_fw_supports_lldp_fltr_ctrl - check NVM version supports lldp_fltr_ctrl
6099 * @hw: pointer to HW struct
6100 */
ice_fw_supports_lldp_fltr_ctrl(struct ice_hw * hw)6101 bool ice_fw_supports_lldp_fltr_ctrl(struct ice_hw *hw)
6102 {
6103 if (hw->mac_type != ICE_MAC_E810)
6104 return false;
6105
6106 return ice_is_fw_api_min_ver(hw, ICE_FW_API_LLDP_FLTR_MAJ,
6107 ICE_FW_API_LLDP_FLTR_MIN,
6108 ICE_FW_API_LLDP_FLTR_PATCH);
6109 }
6110
6111 /**
6112 * ice_lldp_fltr_add_remove - add or remove a LLDP Rx switch filter
6113 * @hw: pointer to HW struct
6114 * @vsi_num: absolute HW index for VSI
6115 * @add: boolean for if adding or removing a filter
6116 */
6117 int
ice_lldp_fltr_add_remove(struct ice_hw * hw,u16 vsi_num,bool add)6118 ice_lldp_fltr_add_remove(struct ice_hw *hw, u16 vsi_num, bool add)
6119 {
6120 struct ice_aqc_lldp_filter_ctrl *cmd;
6121 struct ice_aq_desc desc;
6122
6123 cmd = &desc.params.lldp_filter_ctrl;
6124
6125 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_lldp_filter_ctrl);
6126
6127 if (add)
6128 cmd->cmd_flags = ICE_AQC_LLDP_FILTER_ACTION_ADD;
6129 else
6130 cmd->cmd_flags = ICE_AQC_LLDP_FILTER_ACTION_DELETE;
6131
6132 cmd->vsi_num = cpu_to_le16(vsi_num);
6133
6134 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL);
6135 }
6136
6137 /**
6138 * ice_lldp_execute_pending_mib - execute LLDP pending MIB request
6139 * @hw: pointer to HW struct
6140 */
ice_lldp_execute_pending_mib(struct ice_hw * hw)6141 int ice_lldp_execute_pending_mib(struct ice_hw *hw)
6142 {
6143 struct ice_aq_desc desc;
6144
6145 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_lldp_execute_pending_mib);
6146
6147 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL);
6148 }
6149
6150 /**
6151 * ice_fw_supports_report_dflt_cfg
6152 * @hw: pointer to the hardware structure
6153 *
6154 * Checks if the firmware supports report default configuration
6155 */
ice_fw_supports_report_dflt_cfg(struct ice_hw * hw)6156 bool ice_fw_supports_report_dflt_cfg(struct ice_hw *hw)
6157 {
6158 return ice_is_fw_api_min_ver(hw, ICE_FW_API_REPORT_DFLT_CFG_MAJ,
6159 ICE_FW_API_REPORT_DFLT_CFG_MIN,
6160 ICE_FW_API_REPORT_DFLT_CFG_PATCH);
6161 }
6162
6163 /* each of the indexes into the following array match the speed of a return
6164 * value from the list of AQ returned speeds like the range:
6165 * ICE_AQ_LINK_SPEED_10MB .. ICE_AQ_LINK_SPEED_100GB excluding
6166 * ICE_AQ_LINK_SPEED_UNKNOWN which is BIT(15) and maps to BIT(14) in this
6167 * array. The array is defined as 15 elements long because the link_speed
6168 * returned by the firmware is a 16 bit * value, but is indexed
6169 * by [fls(speed) - 1]
6170 */
6171 static const u32 ice_aq_to_link_speed[] = {
6172 SPEED_10, /* BIT(0) */
6173 SPEED_100,
6174 SPEED_1000,
6175 SPEED_2500,
6176 SPEED_5000,
6177 SPEED_10000,
6178 SPEED_20000,
6179 SPEED_25000,
6180 SPEED_40000,
6181 SPEED_50000,
6182 SPEED_100000, /* BIT(10) */
6183 SPEED_200000,
6184 };
6185
6186 /**
6187 * ice_get_link_speed - get integer speed from table
6188 * @index: array index from fls(aq speed) - 1
6189 *
6190 * Returns: u32 value containing integer speed
6191 */
ice_get_link_speed(u16 index)6192 u32 ice_get_link_speed(u16 index)
6193 {
6194 if (index >= ARRAY_SIZE(ice_aq_to_link_speed))
6195 return 0;
6196
6197 return ice_aq_to_link_speed[index];
6198 }
6199