1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Marvell RVU Admin Function driver
3 *
4 * Copyright (C) 2018 Marvell.
5 *
6 */
7
8 #ifndef RVU_H
9 #define RVU_H
10
11 #include <linux/pci.h>
12 #include <net/devlink.h>
13
14 #include "rvu_struct.h"
15 #include "rvu_devlink.h"
16 #include "common.h"
17 #include "mbox.h"
18 #include "npc.h"
19 #include "rvu_reg.h"
20 #include "ptp.h"
21
22 /* PCI device IDs */
23 #define PCI_DEVID_OCTEONTX2_RVU_AF 0xA065
24 #define PCI_DEVID_OCTEONTX2_LBK 0xA061
25
26 /* Subsystem Device ID */
27 #define PCI_SUBSYS_DEVID_98XX 0xB100
28 #define PCI_SUBSYS_DEVID_96XX 0xB200
29 #define PCI_SUBSYS_DEVID_CN10K_A 0xB900
30 #define PCI_SUBSYS_DEVID_CNF10K_A 0xBA00
31 #define PCI_SUBSYS_DEVID_CNF10K_B 0xBC00
32 #define PCI_SUBSYS_DEVID_CN10K_B 0xBD00
33 #define PCI_SUBSYS_DEVID_CN20KA 0xC220
34 #define PCI_SUBSYS_DEVID_CNF20KA 0xC320
35
36 /* PCI BAR nos */
37 #define PCI_AF_REG_BAR_NUM 0
38 #define PCI_PF_REG_BAR_NUM 2
39 #define PCI_MBOX_BAR_NUM 4
40
41 #define NAME_SIZE 32
42 #define MAX_NIX_BLKS 2
43 #define MAX_CPT_BLKS 2
44
45 /* PF_FUNC */
46 #define RVU_PFVF_PF_SHIFT 10
47 #define RVU_PFVF_PF_MASK 0x3F
48 #define RVU_PFVF_FUNC_SHIFT 0
49 #define RVU_PFVF_FUNC_MASK 0x3FF
50
51 #ifdef CONFIG_DEBUG_FS
52 struct dump_ctx {
53 int lf;
54 int id;
55 bool all;
56 };
57
58 struct cpt_ctx {
59 int blkaddr;
60 struct rvu *rvu;
61 };
62
63 struct rvu_debugfs {
64 struct dentry *root;
65 struct dentry *cgx_root;
66 struct dentry *cgx;
67 struct dentry *lmac;
68 struct dentry *npa;
69 struct dentry *nix;
70 struct dentry *npc;
71 struct dentry *cpt;
72 struct dentry *mcs_root;
73 struct dentry *mcs;
74 struct dentry *mcs_rx;
75 struct dentry *mcs_tx;
76 struct dump_ctx npa_aura_ctx;
77 struct dump_ctx npa_pool_ctx;
78 struct dump_ctx nix_cq_ctx;
79 struct dump_ctx nix_rq_ctx;
80 struct dump_ctx nix_sq_ctx;
81 struct dump_ctx nix_tm_ctx;
82 struct cpt_ctx cpt_ctx[MAX_CPT_BLKS];
83 int npa_qsize_id;
84 int nix_qsize_id;
85 };
86 #endif
87
88 struct rvu_work {
89 struct work_struct work;
90 struct rvu *rvu;
91 int num_msgs;
92 int up_num_msgs;
93 };
94
95 struct rsrc_bmap {
96 unsigned long *bmap; /* Pointer to resource bitmap */
97 u16 max; /* Max resource id or count */
98 };
99
100 struct rvu_block {
101 struct rsrc_bmap lf;
102 struct admin_queue *aq; /* NIX/NPA AQ */
103 u16 *fn_map; /* LF to pcifunc mapping */
104 bool multislot;
105 bool implemented;
106 u8 addr; /* RVU_BLOCK_ADDR_E */
107 u8 type; /* RVU_BLOCK_TYPE_E */
108 u8 lfshift;
109 u64 lookup_reg;
110 u64 pf_lfcnt_reg;
111 u64 vf_lfcnt_reg;
112 u64 lfcfg_reg;
113 u64 msixcfg_reg;
114 u64 lfreset_reg;
115 unsigned char name[NAME_SIZE];
116 struct rvu *rvu;
117 u64 cpt_flt_eng_map[3];
118 u64 cpt_rcvrd_eng_map[3];
119 };
120
121 struct nix_mcast {
122 struct qmem *mce_ctx;
123 struct qmem *mcast_buf;
124 int replay_pkind;
125 struct rsrc_bmap mce_counter[2];
126 /* Counters for both ingress and egress mcast lists */
127 struct mutex mce_lock; /* Serialize MCE updates */
128 };
129
130 struct nix_mce_list {
131 struct hlist_head head;
132 int count;
133 int max;
134 };
135
136 struct nix_mcast_grp_elem {
137 struct nix_mce_list mcast_mce_list;
138 u32 mcast_grp_idx;
139 u32 pcifunc;
140 int mcam_index;
141 int mce_start_index;
142 struct list_head list;
143 u8 dir;
144 };
145
146 struct nix_mcast_grp {
147 struct list_head mcast_grp_head;
148 int count;
149 int next_grp_index;
150 struct mutex mcast_grp_lock; /* Serialize MCE updates */
151 };
152
153 /* layer metadata to uniquely identify a packet header field */
154 struct npc_layer_mdata {
155 u8 lid;
156 u8 ltype;
157 u8 hdr;
158 u8 key;
159 u8 len;
160 };
161
162 /* Structure to represent a field present in the
163 * generated key. A key field may present anywhere and can
164 * be of any size in the generated key. Once this structure
165 * is populated for fields of interest then field's presence
166 * and location (if present) can be known.
167 */
168 struct npc_key_field {
169 /* Masks where all set bits indicate position
170 * of a field in the key
171 */
172 u64 kw_mask[NPC_MAX_KWS_IN_KEY];
173 /* Number of words in the key a field spans. If a field is
174 * of 16 bytes and key offset is 4 then the field will use
175 * 4 bytes in KW0, 8 bytes in KW1 and 4 bytes in KW2 and
176 * nr_kws will be 3(KW0, KW1 and KW2).
177 */
178 int nr_kws;
179 /* used by packet header fields */
180 struct npc_layer_mdata layer_mdata;
181 };
182
183 struct npc_mcam {
184 struct rsrc_bmap counters;
185 struct mutex lock; /* MCAM entries and counters update lock */
186 unsigned long *bmap; /* bitmap, 0 => bmap_entries */
187 unsigned long *bmap_reverse; /* Reverse bitmap, bmap_entries => 0 */
188 u16 bmap_entries; /* Number of unreserved MCAM entries */
189 u16 bmap_fcnt; /* MCAM entries free count */
190 u16 *entry2pfvf_map;
191 u16 *entry2cntr_map;
192 u16 *cntr2pfvf_map;
193 u16 *cntr_refcnt;
194 u16 *entry2target_pffunc;
195 u8 keysize; /* MCAM keysize 112/224/448 bits */
196 u8 banks; /* Number of MCAM banks */
197 u8 banks_per_entry;/* Number of keywords in key */
198 u16 banksize; /* Number of MCAM entries in each bank */
199 u16 total_entries; /* Total number of MCAM entries */
200 u16 nixlf_offset; /* Offset of nixlf rsvd uncast entries */
201 u16 pf_offset; /* Offset of PF's rsvd bcast, promisc entries */
202 u16 lprio_count;
203 u16 lprio_start;
204 u16 hprio_count;
205 u16 hprio_end;
206 u16 rx_miss_act_cntr; /* Counter for RX MISS action */
207 /* fields present in the generated key */
208 struct npc_key_field tx_key_fields[NPC_KEY_FIELDS_MAX];
209 struct npc_key_field rx_key_fields[NPC_KEY_FIELDS_MAX];
210 u64 tx_features;
211 u64 rx_features;
212 struct list_head mcam_rules;
213 };
214
215 /* Structure for per RVU func info ie PF/VF */
216 struct rvu_pfvf {
217 bool npalf; /* Only one NPALF per RVU_FUNC */
218 bool nixlf; /* Only one NIXLF per RVU_FUNC */
219 u16 sso;
220 u16 ssow;
221 u16 cptlfs;
222 u16 timlfs;
223 u16 cpt1_lfs;
224 u8 cgx_lmac;
225
226 /* Block LF's MSIX vector info */
227 struct rsrc_bmap msix; /* Bitmap for MSIX vector alloc */
228 #define MSIX_BLKLF(blkaddr, lf) (((blkaddr) << 8) | ((lf) & 0xFF))
229 u16 *msix_lfmap; /* Vector to block LF mapping */
230
231 /* NPA contexts */
232 struct qmem *aura_ctx;
233 struct qmem *pool_ctx;
234 struct qmem *npa_qints_ctx;
235 unsigned long *aura_bmap;
236 unsigned long *pool_bmap;
237
238 /* NIX contexts */
239 struct qmem *rq_ctx;
240 struct qmem *sq_ctx;
241 struct qmem *cq_ctx;
242 struct qmem *rss_ctx;
243 struct qmem *cq_ints_ctx;
244 struct qmem *nix_qints_ctx;
245 unsigned long *sq_bmap;
246 unsigned long *rq_bmap;
247 unsigned long *cq_bmap;
248
249 u16 rx_chan_base;
250 u16 tx_chan_base;
251 u8 rx_chan_cnt; /* total number of RX channels */
252 u8 tx_chan_cnt; /* total number of TX channels */
253 u16 maxlen;
254 u16 minlen;
255
256 bool hw_rx_tstamp_en; /* Is rx_tstamp enabled */
257 u8 mac_addr[ETH_ALEN]; /* MAC address of this PF/VF */
258 u8 default_mac[ETH_ALEN]; /* MAC address from FWdata */
259
260 /* Broadcast/Multicast/Promisc pkt replication info */
261 u16 bcast_mce_idx;
262 u16 mcast_mce_idx;
263 u16 promisc_mce_idx;
264 struct nix_mce_list bcast_mce_list;
265 struct nix_mce_list mcast_mce_list;
266 struct nix_mce_list promisc_mce_list;
267 bool use_mce_list;
268
269 struct rvu_npc_mcam_rule *def_ucast_rule;
270
271 bool cgx_in_use; /* this PF/VF using CGX? */
272 int cgx_users; /* number of cgx users - used only by PFs */
273
274 int intf_mode;
275 u8 nix_blkaddr; /* BLKADDR_NIX0/1 assigned to this PF */
276 u8 nix_rx_intf; /* NIX0_RX/NIX1_RX interface to NPC */
277 u8 nix_tx_intf; /* NIX0_TX/NIX1_TX interface to NPC */
278 u8 lbkid; /* NIX0/1 lbk link ID */
279 u64 lmt_base_addr; /* Preseving the pcifunc's lmtst base addr*/
280 u64 lmt_map_ent_w1; /* Preseving the word1 of lmtst map table entry*/
281 unsigned long flags;
282 struct sdp_node_info *sdp_info;
283 };
284
285 enum rvu_pfvf_flags {
286 NIXLF_INITIALIZED = 0,
287 PF_SET_VF_MAC,
288 PF_SET_VF_CFG,
289 PF_SET_VF_TRUSTED,
290 };
291
292 #define RVU_CLEAR_VF_PERM ~GENMASK(PF_SET_VF_TRUSTED, PF_SET_VF_MAC)
293
294 struct nix_bp {
295 struct rsrc_bmap bpids; /* free bpids bitmap */
296 u16 cgx_bpid_cnt;
297 u16 sdp_bpid_cnt;
298 u16 free_pool_base;
299 u16 *fn_map; /* pcifunc mapping */
300 u8 *intf_map; /* interface type map */
301 u8 *ref_cnt;
302 };
303
304 struct nix_txsch {
305 struct rsrc_bmap schq;
306 u8 lvl;
307 #define NIX_TXSCHQ_FREE BIT_ULL(1)
308 #define NIX_TXSCHQ_CFG_DONE BIT_ULL(0)
309 #define TXSCH_MAP_FUNC(__pfvf_map) ((__pfvf_map) & 0xFFFF)
310 #define TXSCH_MAP_FLAGS(__pfvf_map) ((__pfvf_map) >> 16)
311 #define TXSCH_MAP(__func, __flags) (((__func) & 0xFFFF) | ((__flags) << 16))
312 #define TXSCH_SET_FLAG(__pfvf_map, flag) ((__pfvf_map) | ((flag) << 16))
313 u32 *pfvf_map;
314 };
315
316 struct nix_mark_format {
317 u8 total;
318 u8 in_use;
319 u32 *cfg;
320 };
321
322 /* smq(flush) to tl1 cir/pir info */
323 struct nix_smq_tree_ctx {
324 u16 schq;
325 u64 cir_off;
326 u64 cir_val;
327 u64 pir_off;
328 u64 pir_val;
329 };
330
331 /* smq flush context */
332 struct nix_smq_flush_ctx {
333 int smq;
334 struct nix_smq_tree_ctx smq_tree_ctx[NIX_TXSCH_LVL_CNT];
335 };
336
337 struct npc_pkind {
338 struct rsrc_bmap rsrc;
339 u32 *pfchan_map;
340 };
341
342 struct nix_flowkey {
343 #define NIX_FLOW_KEY_ALG_MAX 32
344 u32 flowkey[NIX_FLOW_KEY_ALG_MAX];
345 int in_use;
346 };
347
348 struct nix_lso {
349 u8 total;
350 u8 in_use;
351 };
352
353 struct nix_txvlan {
354 #define NIX_TX_VTAG_DEF_MAX 0x400
355 struct rsrc_bmap rsrc;
356 u16 *entry2pfvf_map;
357 struct mutex rsrc_lock; /* Serialize resource alloc/free */
358 };
359
360 struct nix_ipolicer {
361 struct rsrc_bmap band_prof;
362 u16 *pfvf_map;
363 u16 *match_id;
364 u16 *ref_count;
365 };
366
367 struct nix_hw {
368 int blkaddr;
369 struct rvu *rvu;
370 struct nix_txsch txsch[NIX_TXSCH_LVL_CNT]; /* Tx schedulers */
371 struct nix_mcast mcast;
372 struct nix_mcast_grp mcast_grp;
373 struct nix_flowkey flowkey;
374 struct nix_mark_format mark_format;
375 struct nix_lso lso;
376 struct nix_txvlan txvlan;
377 struct nix_ipolicer *ipolicer;
378 struct nix_bp bp;
379 u64 *tx_credits;
380 u8 cc_mcs_cnt;
381 };
382
383 /* RVU block's capabilities or functionality,
384 * which vary by silicon version/skew.
385 */
386 struct hw_cap {
387 /* Transmit side supported functionality */
388 u8 nix_tx_aggr_lvl; /* Tx link's traffic aggregation level */
389 u16 nix_txsch_per_cgx_lmac; /* Max Q's transmitting to CGX LMAC */
390 u16 nix_txsch_per_lbk_lmac; /* Max Q's transmitting to LBK LMAC */
391 u16 nix_txsch_per_sdp_lmac; /* Max Q's transmitting to SDP LMAC */
392 bool nix_fixed_txschq_mapping; /* Schq mapping fixed or flexible */
393 bool nix_shaping; /* Is shaping and coloring supported */
394 bool nix_shaper_toggle_wait; /* Shaping toggle needs poll/wait */
395 bool nix_tx_link_bp; /* Can link backpressure TL queues ? */
396 bool nix_rx_multicast; /* Rx packet replication support */
397 bool nix_common_dwrr_mtu; /* Common DWRR MTU for quantum config */
398 bool per_pf_mbox_regs; /* PF mbox specified in per PF registers ? */
399 bool programmable_chans; /* Channels programmable ? */
400 bool ipolicer;
401 bool nix_multiple_dwrr_mtu; /* Multiple DWRR_MTU to choose from */
402 bool npc_hash_extract; /* Hash extract enabled ? */
403 bool npc_exact_match_enabled; /* Exact match supported ? */
404 bool cpt_rxc; /* Is CPT-RXC supported */
405 };
406
407 struct rvu_hwinfo {
408 u8 total_pfs; /* MAX RVU PFs HW supports */
409 u16 total_vfs; /* Max RVU VFs HW supports */
410 u16 max_vfs_per_pf; /* Max VFs that can be attached to a PF */
411 u8 cgx;
412 u8 lmac_per_cgx;
413 u16 cgx_chan_base; /* CGX base channel number */
414 u16 lbk_chan_base; /* LBK base channel number */
415 u16 sdp_chan_base; /* SDP base channel number */
416 u16 cpt_chan_base; /* CPT base channel number */
417 u8 cgx_links;
418 u8 lbk_links;
419 u8 sdp_links;
420 u8 cpt_links; /* Number of CPT links */
421 u8 npc_kpus; /* No of parser units */
422 u8 npc_pkinds; /* No of port kinds */
423 u8 npc_intfs; /* No of interfaces */
424 u8 npc_kpu_entries; /* No of KPU entries */
425 u16 npc_counters; /* No of match stats counters */
426 u32 lbk_bufsize; /* FIFO size supported by LBK */
427 bool npc_ext_set; /* Extended register set */
428 u64 npc_stat_ena; /* Match stats enable bit */
429
430 struct hw_cap cap;
431 struct rvu_block block[BLK_COUNT]; /* Block info */
432 struct nix_hw *nix;
433 struct rvu *rvu;
434 struct npc_pkind pkind;
435 struct npc_mcam mcam;
436 struct npc_exact_table *table;
437 };
438
439 struct mbox_wq_info {
440 struct otx2_mbox mbox;
441 struct rvu_work *mbox_wrk;
442
443 struct otx2_mbox mbox_up;
444 struct rvu_work *mbox_wrk_up;
445
446 struct workqueue_struct *mbox_wq;
447 };
448
449 struct channel_fwdata {
450 struct sdp_node_info info;
451 u8 valid;
452 #define RVU_CHANL_INFO_RESERVED 379
453 u8 reserved[RVU_CHANL_INFO_RESERVED];
454 };
455
456 struct rvu_fwdata {
457 #define RVU_FWDATA_HEADER_MAGIC 0xCFDA /* Custom Firmware Data*/
458 #define RVU_FWDATA_VERSION 0x0001
459 u32 header_magic;
460 u32 version; /* version id */
461
462 /* MAC address */
463 #define PF_MACNUM_MAX 32
464 #define VF_MACNUM_MAX 256
465 u64 pf_macs[PF_MACNUM_MAX];
466 u64 vf_macs[VF_MACNUM_MAX];
467 u64 sclk;
468 u64 rclk;
469 u64 mcam_addr;
470 u64 mcam_sz;
471 u64 msixtr_base;
472 u32 ptp_ext_clk_rate;
473 u32 ptp_ext_tstamp;
474 struct channel_fwdata channel_data;
475 #define FWDATA_RESERVED_MEM 958
476 u64 reserved[FWDATA_RESERVED_MEM];
477 #define CGX_MAX 9
478 #define CGX_LMACS_MAX 4
479 #define CGX_LMACS_USX 8
480 #define FWDATA_CGX_LMAC_OFFSET 10536
481 union {
482 struct cgx_lmac_fwdata_s
483 cgx_fw_data[CGX_MAX][CGX_LMACS_MAX];
484 struct cgx_lmac_fwdata_s
485 cgx_fw_data_usx[CGX_MAX][CGX_LMACS_USX];
486 };
487 /* Do not add new fields below this line */
488 };
489
490 struct ptp;
491
492 /* KPU profile adapter structure gathering all KPU configuration data and abstracting out the
493 * source where it came from.
494 */
495 struct npc_kpu_profile_adapter {
496 const char *name;
497 u64 version;
498 const struct npc_lt_def_cfg *lt_def;
499 const struct npc_kpu_profile_action *ikpu; /* array[pkinds] */
500 const struct npc_kpu_profile *kpu; /* array[kpus] */
501 struct npc_mcam_kex *mkex;
502 struct npc_mcam_kex_hash *mkex_hash;
503 bool custom;
504 size_t pkinds;
505 size_t kpus;
506 };
507
508 #define RVU_SWITCH_LBK_CHAN 63
509
510 struct rvu_switch {
511 struct mutex switch_lock; /* Serialize flow installation */
512 u32 used_entries;
513 u16 *entry2pcifunc;
514 u16 mode;
515 u16 start_entry;
516 };
517
518 struct rvu {
519 void __iomem *afreg_base;
520 void __iomem *pfreg_base;
521 struct pci_dev *pdev;
522 struct device *dev;
523 struct rvu_hwinfo *hw;
524 struct rvu_pfvf *pf;
525 struct rvu_pfvf *hwvf;
526 struct mutex rsrc_lock; /* Serialize resource alloc/free */
527 struct mutex alias_lock; /* Serialize bar2 alias access */
528 int vfs; /* Number of VFs attached to RVU */
529 u16 vf_devid; /* VF devices id */
530 int nix_blkaddr[MAX_NIX_BLKS];
531
532 /* Mbox */
533 struct mbox_wq_info afpf_wq_info;
534 struct mbox_wq_info afvf_wq_info;
535
536 /* PF FLR */
537 struct rvu_work *flr_wrk;
538 struct workqueue_struct *flr_wq;
539 struct mutex flr_lock; /* Serialize FLRs */
540
541 /* MSI-X */
542 u16 num_vec;
543 char *irq_name;
544 bool *irq_allocated;
545 dma_addr_t msix_base_iova;
546 u64 msixtr_base_phy; /* Register reset value */
547
548 /* CGX */
549 #define PF_CGXMAP_BASE 1 /* PF 0 is reserved for RVU PF */
550 u16 cgx_mapped_vfs; /* maximum CGX mapped VFs */
551 u8 cgx_mapped_pfs;
552 u8 cgx_cnt_max; /* CGX port count max */
553 u8 *pf2cgxlmac_map; /* pf to cgx_lmac map */
554 u64 *cgxlmac2pf_map; /* bitmap of mapped pfs for
555 * every cgx lmac port
556 */
557 unsigned long pf_notify_bmap; /* Flags for PF notification */
558 void **cgx_idmap; /* cgx id to cgx data map table */
559 struct work_struct cgx_evh_work;
560 struct workqueue_struct *cgx_evh_wq;
561 spinlock_t cgx_evq_lock; /* cgx event queue lock */
562 struct list_head cgx_evq_head; /* cgx event queue head */
563 struct mutex cgx_cfg_lock; /* serialize cgx configuration */
564
565 char mkex_pfl_name[MKEX_NAME_LEN]; /* Configured MKEX profile name */
566 char kpu_pfl_name[KPU_NAME_LEN]; /* Configured KPU profile name */
567
568 /* Firmware data */
569 struct rvu_fwdata *fwdata;
570 void *kpu_fwdata;
571 size_t kpu_fwdata_sz;
572 void __iomem *kpu_prfl_addr;
573
574 /* NPC KPU data */
575 struct npc_kpu_profile_adapter kpu;
576
577 struct ptp *ptp;
578
579 int mcs_blk_cnt;
580 int cpt_pf_num;
581
582 #ifdef CONFIG_DEBUG_FS
583 struct rvu_debugfs rvu_dbg;
584 #endif
585 struct rvu_devlink *rvu_dl;
586
587 /* RVU switch implementation over NPC with DMAC rules */
588 struct rvu_switch rswitch;
589
590 struct work_struct mcs_intr_work;
591 struct workqueue_struct *mcs_intr_wq;
592 struct list_head mcs_intrq_head;
593 /* mcs interrupt queue lock */
594 spinlock_t mcs_intrq_lock;
595 /* CPT interrupt lock */
596 spinlock_t cpt_intr_lock;
597
598 struct mutex mbox_lock; /* Serialize mbox up and down msgs */
599 };
600
rvu_write64(struct rvu * rvu,u64 block,u64 offset,u64 val)601 static inline void rvu_write64(struct rvu *rvu, u64 block, u64 offset, u64 val)
602 {
603 writeq(val, rvu->afreg_base + ((block << 28) | offset));
604 }
605
rvu_read64(struct rvu * rvu,u64 block,u64 offset)606 static inline u64 rvu_read64(struct rvu *rvu, u64 block, u64 offset)
607 {
608 return readq(rvu->afreg_base + ((block << 28) | offset));
609 }
610
rvupf_write64(struct rvu * rvu,u64 offset,u64 val)611 static inline void rvupf_write64(struct rvu *rvu, u64 offset, u64 val)
612 {
613 writeq(val, rvu->pfreg_base + offset);
614 }
615
rvupf_read64(struct rvu * rvu,u64 offset)616 static inline u64 rvupf_read64(struct rvu *rvu, u64 offset)
617 {
618 return readq(rvu->pfreg_base + offset);
619 }
620
rvu_bar2_sel_write64(struct rvu * rvu,u64 block,u64 offset,u64 val)621 static inline void rvu_bar2_sel_write64(struct rvu *rvu, u64 block, u64 offset, u64 val)
622 {
623 /* HW requires read back of RVU_AF_BAR2_SEL register to make sure completion of
624 * write operation.
625 */
626 rvu_write64(rvu, block, offset, val);
627 rvu_read64(rvu, block, offset);
628 /* Barrier to ensure read completes before accessing LF registers */
629 mb();
630 }
631
632 /* Silicon revisions */
is_rvu_pre_96xx_C0(struct rvu * rvu)633 static inline bool is_rvu_pre_96xx_C0(struct rvu *rvu)
634 {
635 struct pci_dev *pdev = rvu->pdev;
636 /* 96XX A0/B0, 95XX A0/A1/B0 chips */
637 return ((pdev->revision == 0x00) || (pdev->revision == 0x01) ||
638 (pdev->revision == 0x10) || (pdev->revision == 0x11) ||
639 (pdev->revision == 0x14));
640 }
641
is_rvu_96xx_A0(struct rvu * rvu)642 static inline bool is_rvu_96xx_A0(struct rvu *rvu)
643 {
644 struct pci_dev *pdev = rvu->pdev;
645
646 return (pdev->revision == 0x00);
647 }
648
is_rvu_96xx_B0(struct rvu * rvu)649 static inline bool is_rvu_96xx_B0(struct rvu *rvu)
650 {
651 struct pci_dev *pdev = rvu->pdev;
652
653 return (pdev->revision == 0x00) || (pdev->revision == 0x01);
654 }
655
is_rvu_95xx_A0(struct rvu * rvu)656 static inline bool is_rvu_95xx_A0(struct rvu *rvu)
657 {
658 struct pci_dev *pdev = rvu->pdev;
659
660 return (pdev->revision == 0x10) || (pdev->revision == 0x11);
661 }
662
663 /* REVID for PCIe devices.
664 * Bits 0..1: minor pass, bit 3..2: major pass
665 * bits 7..4: midr id
666 */
667 #define PCI_REVISION_ID_96XX 0x00
668 #define PCI_REVISION_ID_95XX 0x10
669 #define PCI_REVISION_ID_95XXN 0x20
670 #define PCI_REVISION_ID_98XX 0x30
671 #define PCI_REVISION_ID_95XXMM 0x40
672 #define PCI_REVISION_ID_95XXO 0xE0
673
is_rvu_otx2(struct rvu * rvu)674 static inline bool is_rvu_otx2(struct rvu *rvu)
675 {
676 struct pci_dev *pdev = rvu->pdev;
677
678 u8 midr = pdev->revision & 0xF0;
679
680 return (midr == PCI_REVISION_ID_96XX || midr == PCI_REVISION_ID_95XX ||
681 midr == PCI_REVISION_ID_95XXN || midr == PCI_REVISION_ID_98XX ||
682 midr == PCI_REVISION_ID_95XXMM || midr == PCI_REVISION_ID_95XXO);
683 }
684
is_cnf10ka_a0(struct rvu * rvu)685 static inline bool is_cnf10ka_a0(struct rvu *rvu)
686 {
687 struct pci_dev *pdev = rvu->pdev;
688
689 if (pdev->subsystem_device == PCI_SUBSYS_DEVID_CNF10K_A &&
690 (pdev->revision & 0x0F) == 0x0)
691 return true;
692 return false;
693 }
694
is_cn10ka_a0(struct rvu * rvu)695 static inline bool is_cn10ka_a0(struct rvu *rvu)
696 {
697 struct pci_dev *pdev = rvu->pdev;
698
699 if (pdev->subsystem_device == PCI_SUBSYS_DEVID_CN10K_A &&
700 (pdev->revision & 0x0F) == 0x0)
701 return true;
702 return false;
703 }
704
is_cn10ka_a1(struct rvu * rvu)705 static inline bool is_cn10ka_a1(struct rvu *rvu)
706 {
707 struct pci_dev *pdev = rvu->pdev;
708
709 if (pdev->subsystem_device == PCI_SUBSYS_DEVID_CN10K_A &&
710 (pdev->revision & 0x0F) == 0x1)
711 return true;
712 return false;
713 }
714
is_cn10kb(struct rvu * rvu)715 static inline bool is_cn10kb(struct rvu *rvu)
716 {
717 struct pci_dev *pdev = rvu->pdev;
718
719 if (pdev->subsystem_device == PCI_SUBSYS_DEVID_CN10K_B)
720 return true;
721 return false;
722 }
723
is_rvu_npc_hash_extract_en(struct rvu * rvu)724 static inline bool is_rvu_npc_hash_extract_en(struct rvu *rvu)
725 {
726 u64 npc_const3;
727
728 npc_const3 = rvu_read64(rvu, BLKADDR_NPC, NPC_AF_CONST3);
729 if (!(npc_const3 & BIT_ULL(62)))
730 return false;
731
732 return true;
733 }
734
rvu_nix_chan_cgx(struct rvu * rvu,u8 cgxid,u8 lmacid,u8 chan)735 static inline u16 rvu_nix_chan_cgx(struct rvu *rvu, u8 cgxid,
736 u8 lmacid, u8 chan)
737 {
738 u64 nix_const = rvu_read64(rvu, BLKADDR_NIX0, NIX_AF_CONST);
739 u16 cgx_chans = nix_const & 0xFFULL;
740 struct rvu_hwinfo *hw = rvu->hw;
741
742 if (!hw->cap.programmable_chans)
743 return NIX_CHAN_CGX_LMAC_CHX(cgxid, lmacid, chan);
744
745 return rvu->hw->cgx_chan_base +
746 (cgxid * hw->lmac_per_cgx + lmacid) * cgx_chans + chan;
747 }
748
rvu_nix_chan_lbk(struct rvu * rvu,u8 lbkid,u8 chan)749 static inline u16 rvu_nix_chan_lbk(struct rvu *rvu, u8 lbkid,
750 u8 chan)
751 {
752 u64 nix_const = rvu_read64(rvu, BLKADDR_NIX0, NIX_AF_CONST);
753 u16 lbk_chans = (nix_const >> 16) & 0xFFULL;
754 struct rvu_hwinfo *hw = rvu->hw;
755
756 if (!hw->cap.programmable_chans)
757 return NIX_CHAN_LBK_CHX(lbkid, chan);
758
759 return rvu->hw->lbk_chan_base + lbkid * lbk_chans + chan;
760 }
761
rvu_nix_chan_sdp(struct rvu * rvu,u8 chan)762 static inline u16 rvu_nix_chan_sdp(struct rvu *rvu, u8 chan)
763 {
764 struct rvu_hwinfo *hw = rvu->hw;
765
766 if (!hw->cap.programmable_chans)
767 return NIX_CHAN_SDP_CHX(chan);
768
769 return hw->sdp_chan_base + chan;
770 }
771
rvu_nix_chan_cpt(struct rvu * rvu,u8 chan)772 static inline u16 rvu_nix_chan_cpt(struct rvu *rvu, u8 chan)
773 {
774 return rvu->hw->cpt_chan_base + chan;
775 }
776
is_rvu_supports_nix1(struct rvu * rvu)777 static inline bool is_rvu_supports_nix1(struct rvu *rvu)
778 {
779 struct pci_dev *pdev = rvu->pdev;
780
781 if (pdev->subsystem_device == PCI_SUBSYS_DEVID_98XX)
782 return true;
783
784 return false;
785 }
786
787 /* Function Prototypes
788 * RVU
789 */
790 #define RVU_LBK_VF_DEVID 0xA0F8
is_lbk_vf(struct rvu * rvu,u16 pcifunc)791 static inline bool is_lbk_vf(struct rvu *rvu, u16 pcifunc)
792 {
793 return (!(pcifunc & ~RVU_PFVF_FUNC_MASK) &&
794 (rvu->vf_devid == RVU_LBK_VF_DEVID));
795 }
796
is_vf(u16 pcifunc)797 static inline bool is_vf(u16 pcifunc)
798 {
799 return !!(pcifunc & RVU_PFVF_FUNC_MASK);
800 }
801
802 /* check if PF_FUNC is AF */
is_pffunc_af(u16 pcifunc)803 static inline bool is_pffunc_af(u16 pcifunc)
804 {
805 return !pcifunc;
806 }
807
is_rvu_fwdata_valid(struct rvu * rvu)808 static inline bool is_rvu_fwdata_valid(struct rvu *rvu)
809 {
810 return (rvu->fwdata->header_magic == RVU_FWDATA_HEADER_MAGIC) &&
811 (rvu->fwdata->version == RVU_FWDATA_VERSION);
812 }
813
814 int rvu_alloc_bitmap(struct rsrc_bmap *rsrc);
815 void rvu_free_bitmap(struct rsrc_bmap *rsrc);
816 int rvu_alloc_rsrc(struct rsrc_bmap *rsrc);
817 void rvu_free_rsrc(struct rsrc_bmap *rsrc, int id);
818 bool is_rsrc_free(struct rsrc_bmap *rsrc, int id);
819 int rvu_rsrc_free_count(struct rsrc_bmap *rsrc);
820 int rvu_alloc_rsrc_contig(struct rsrc_bmap *rsrc, int nrsrc);
821 void rvu_free_rsrc_contig(struct rsrc_bmap *rsrc, int nrsrc, int start);
822 bool rvu_rsrc_check_contig(struct rsrc_bmap *rsrc, int nrsrc);
823 u16 rvu_get_rsrc_mapcount(struct rvu_pfvf *pfvf, int blkaddr);
824 int rvu_get_pf(u16 pcifunc);
825 struct rvu_pfvf *rvu_get_pfvf(struct rvu *rvu, int pcifunc);
826 void rvu_get_pf_numvfs(struct rvu *rvu, int pf, int *numvfs, int *hwvf);
827 bool is_block_implemented(struct rvu_hwinfo *hw, int blkaddr);
828 bool is_pffunc_map_valid(struct rvu *rvu, u16 pcifunc, int blktype);
829 int rvu_get_lf(struct rvu *rvu, struct rvu_block *block, u16 pcifunc, u16 slot);
830 int rvu_lf_reset(struct rvu *rvu, struct rvu_block *block, int lf);
831 int rvu_get_blkaddr(struct rvu *rvu, int blktype, u16 pcifunc);
832 int rvu_poll_reg(struct rvu *rvu, u64 block, u64 offset, u64 mask, bool zero);
833 int rvu_get_num_lbk_chans(void);
834 int rvu_ndc_sync(struct rvu *rvu, int lfblkid, int lfidx, u64 lfoffset);
835 int rvu_get_blkaddr_from_slot(struct rvu *rvu, int blktype, u16 pcifunc,
836 u16 global_slot, u16 *slot_in_block);
837
838 /* RVU HW reg validation */
839 enum regmap_block {
840 TXSCHQ_HWREGMAP = 0,
841 MAX_HWREGMAP,
842 };
843
844 bool rvu_check_valid_reg(int regmap, int regblk, u64 reg);
845
846 /* NPA/NIX AQ APIs */
847 int rvu_aq_alloc(struct rvu *rvu, struct admin_queue **ad_queue,
848 int qsize, int inst_size, int res_size);
849 void rvu_aq_free(struct rvu *rvu, struct admin_queue *aq);
850
851 /* SDP APIs */
852 int rvu_sdp_init(struct rvu *rvu);
853 bool is_sdp_pfvf(u16 pcifunc);
854 bool is_sdp_pf(u16 pcifunc);
855 bool is_sdp_vf(struct rvu *rvu, u16 pcifunc);
856
857 /* CGX APIs */
is_pf_cgxmapped(struct rvu * rvu,u8 pf)858 static inline bool is_pf_cgxmapped(struct rvu *rvu, u8 pf)
859 {
860 return (pf >= PF_CGXMAP_BASE && pf <= rvu->cgx_mapped_pfs) &&
861 !is_sdp_pf(pf << RVU_PFVF_PF_SHIFT);
862 }
863
rvu_get_cgx_lmac_id(u8 map,u8 * cgx_id,u8 * lmac_id)864 static inline void rvu_get_cgx_lmac_id(u8 map, u8 *cgx_id, u8 *lmac_id)
865 {
866 *cgx_id = (map >> 4) & 0xF;
867 *lmac_id = (map & 0xF);
868 }
869
is_cgx_vf(struct rvu * rvu,u16 pcifunc)870 static inline bool is_cgx_vf(struct rvu *rvu, u16 pcifunc)
871 {
872 return ((pcifunc & RVU_PFVF_FUNC_MASK) &&
873 is_pf_cgxmapped(rvu, rvu_get_pf(pcifunc)));
874 }
875
876 #define M(_name, _id, fn_name, req, rsp) \
877 int rvu_mbox_handler_ ## fn_name(struct rvu *, struct req *, struct rsp *);
878 MBOX_MESSAGES
879 #undef M
880
881 int rvu_cgx_init(struct rvu *rvu);
882 int rvu_cgx_exit(struct rvu *rvu);
883 void *rvu_cgx_pdata(u8 cgx_id, struct rvu *rvu);
884 int rvu_cgx_config_rxtx(struct rvu *rvu, u16 pcifunc, bool start);
885 void rvu_cgx_enadis_rx_bp(struct rvu *rvu, int pf, bool enable);
886 int rvu_cgx_start_stop_io(struct rvu *rvu, u16 pcifunc, bool start);
887 int rvu_cgx_nix_cuml_stats(struct rvu *rvu, void *cgxd, int lmac_id, int index,
888 int rxtxflag, u64 *stat);
889 void rvu_cgx_disable_dmac_entries(struct rvu *rvu, u16 pcifunc);
890
891 /* NPA APIs */
892 int rvu_npa_init(struct rvu *rvu);
893 void rvu_npa_freemem(struct rvu *rvu);
894 void rvu_npa_lf_teardown(struct rvu *rvu, u16 pcifunc, int npalf);
895 int rvu_npa_aq_enq_inst(struct rvu *rvu, struct npa_aq_enq_req *req,
896 struct npa_aq_enq_rsp *rsp);
897
898 /* NIX APIs */
899 bool is_nixlf_attached(struct rvu *rvu, u16 pcifunc);
900 int rvu_nix_init(struct rvu *rvu);
901 int rvu_nix_reserve_mark_format(struct rvu *rvu, struct nix_hw *nix_hw,
902 int blkaddr, u32 cfg);
903 void rvu_nix_freemem(struct rvu *rvu);
904 int rvu_get_nixlf_count(struct rvu *rvu);
905 void rvu_nix_lf_teardown(struct rvu *rvu, u16 pcifunc, int blkaddr, int npalf);
906 int nix_get_nixlf(struct rvu *rvu, u16 pcifunc, int *nixlf, int *nix_blkaddr);
907 int nix_update_mce_list(struct rvu *rvu, u16 pcifunc,
908 struct nix_mce_list *mce_list,
909 int mce_idx, int mcam_index, bool add);
910 void nix_get_mce_list(struct rvu *rvu, u16 pcifunc, int type,
911 struct nix_mce_list **mce_list, int *mce_idx);
912 struct nix_hw *get_nix_hw(struct rvu_hwinfo *hw, int blkaddr);
913 int rvu_get_next_nix_blkaddr(struct rvu *rvu, int blkaddr);
914 void rvu_nix_reset_mac(struct rvu_pfvf *pfvf, int pcifunc);
915 int nix_get_struct_ptrs(struct rvu *rvu, u16 pcifunc,
916 struct nix_hw **nix_hw, int *blkaddr);
917 int rvu_nix_setup_ratelimit_aggr(struct rvu *rvu, u16 pcifunc,
918 u16 rq_idx, u16 match_id);
919 int nix_aq_context_read(struct rvu *rvu, struct nix_hw *nix_hw,
920 struct nix_cn10k_aq_enq_req *aq_req,
921 struct nix_cn10k_aq_enq_rsp *aq_rsp,
922 u16 pcifunc, u8 ctype, u32 qidx);
923 int rvu_get_nix_blkaddr(struct rvu *rvu, u16 pcifunc);
924 int nix_get_dwrr_mtu_reg(struct rvu_hwinfo *hw, int smq_link_type);
925 u32 convert_dwrr_mtu_to_bytes(u8 dwrr_mtu);
926 u32 convert_bytes_to_dwrr_mtu(u32 bytes);
927 void rvu_nix_tx_tl2_cfg(struct rvu *rvu, int blkaddr, u16 pcifunc,
928 struct nix_txsch *txsch, bool enable);
929 void rvu_nix_mcast_flr_free_entries(struct rvu *rvu, u16 pcifunc);
930 int rvu_nix_mcast_get_mce_index(struct rvu *rvu, u16 pcifunc,
931 u32 mcast_grp_idx);
932 int rvu_nix_mcast_update_mcam_entry(struct rvu *rvu, u16 pcifunc,
933 u32 mcast_grp_idx, u16 mcam_index);
934 void rvu_nix_flr_free_bpids(struct rvu *rvu, u16 pcifunc);
935
936 /* NPC APIs */
937 void rvu_npc_freemem(struct rvu *rvu);
938 int rvu_npc_get_pkind(struct rvu *rvu, u16 pf);
939 void rvu_npc_set_pkind(struct rvu *rvu, int pkind, struct rvu_pfvf *pfvf);
940 int npc_config_ts_kpuaction(struct rvu *rvu, int pf, u16 pcifunc, bool en);
941 void rvu_npc_install_ucast_entry(struct rvu *rvu, u16 pcifunc,
942 int nixlf, u64 chan, u8 *mac_addr);
943 void rvu_npc_install_promisc_entry(struct rvu *rvu, u16 pcifunc,
944 int nixlf, u64 chan, u8 chan_cnt);
945 void rvu_npc_enable_promisc_entry(struct rvu *rvu, u16 pcifunc, int nixlf,
946 bool enable);
947 void rvu_npc_install_bcast_match_entry(struct rvu *rvu, u16 pcifunc,
948 int nixlf, u64 chan);
949 void rvu_npc_enable_bcast_entry(struct rvu *rvu, u16 pcifunc, int nixlf,
950 bool enable);
951 void rvu_npc_install_allmulti_entry(struct rvu *rvu, u16 pcifunc, int nixlf,
952 u64 chan);
953 void rvu_npc_enable_allmulti_entry(struct rvu *rvu, u16 pcifunc, int nixlf,
954 bool enable);
955
956 void npc_enadis_default_mce_entry(struct rvu *rvu, u16 pcifunc,
957 int nixlf, int type, bool enable);
958 void rvu_npc_disable_mcam_entries(struct rvu *rvu, u16 pcifunc, int nixlf);
959 bool rvu_npc_enable_mcam_by_entry_index(struct rvu *rvu, int entry, int intf, bool enable);
960 void rvu_npc_free_mcam_entries(struct rvu *rvu, u16 pcifunc, int nixlf);
961 void rvu_npc_disable_default_entries(struct rvu *rvu, u16 pcifunc, int nixlf);
962 void rvu_npc_enable_default_entries(struct rvu *rvu, u16 pcifunc, int nixlf);
963 void rvu_npc_update_flowkey_alg_idx(struct rvu *rvu, u16 pcifunc, int nixlf,
964 int group, int alg_idx, int mcam_index);
965
966 void rvu_npc_get_mcam_entry_alloc_info(struct rvu *rvu, u16 pcifunc,
967 int blkaddr, int *alloc_cnt,
968 int *enable_cnt);
969 void rvu_npc_get_mcam_counter_alloc_info(struct rvu *rvu, u16 pcifunc,
970 int blkaddr, int *alloc_cnt,
971 int *enable_cnt);
972 bool is_npc_intf_tx(u8 intf);
973 bool is_npc_intf_rx(u8 intf);
974 bool is_npc_interface_valid(struct rvu *rvu, u8 intf);
975 int rvu_npc_get_tx_nibble_cfg(struct rvu *rvu, u64 nibble_ena);
976 int npc_flow_steering_init(struct rvu *rvu, int blkaddr);
977 const char *npc_get_field_name(u8 hdr);
978 int npc_get_bank(struct npc_mcam *mcam, int index);
979 void npc_mcam_enable_flows(struct rvu *rvu, u16 target);
980 void npc_mcam_disable_flows(struct rvu *rvu, u16 target);
981 void npc_enable_mcam_entry(struct rvu *rvu, struct npc_mcam *mcam,
982 int blkaddr, int index, bool enable);
983 u64 npc_get_mcam_action(struct rvu *rvu, struct npc_mcam *mcam,
984 int blkaddr, int index);
985 void npc_set_mcam_action(struct rvu *rvu, struct npc_mcam *mcam,
986 int blkaddr, int index, u64 cfg);
987 void npc_read_mcam_entry(struct rvu *rvu, struct npc_mcam *mcam,
988 int blkaddr, u16 src, struct mcam_entry *entry,
989 u8 *intf, u8 *ena);
990 bool is_cgx_config_permitted(struct rvu *rvu, u16 pcifunc);
991 bool is_mac_feature_supported(struct rvu *rvu, int pf, int feature);
992 u32 rvu_cgx_get_fifolen(struct rvu *rvu);
993 void *rvu_first_cgx_pdata(struct rvu *rvu);
994 int cgxlmac_to_pf(struct rvu *rvu, int cgx_id, int lmac_id);
995 int rvu_cgx_config_tx(void *cgxd, int lmac_id, bool enable);
996 int rvu_cgx_tx_enable(struct rvu *rvu, u16 pcifunc, bool enable);
997 int rvu_cgx_prio_flow_ctrl_cfg(struct rvu *rvu, u16 pcifunc, u8 tx_pause, u8 rx_pause,
998 u16 pfc_en);
999 int rvu_cgx_cfg_pause_frm(struct rvu *rvu, u16 pcifunc, u8 tx_pause, u8 rx_pause);
1000 void rvu_mac_reset(struct rvu *rvu, u16 pcifunc);
1001 u32 rvu_cgx_get_lmac_fifolen(struct rvu *rvu, int cgx, int lmac);
1002 void cgx_start_linkup(struct rvu *rvu);
1003 int npc_get_nixlf_mcam_index(struct npc_mcam *mcam, u16 pcifunc, int nixlf,
1004 int type);
1005 bool is_mcam_entry_enabled(struct rvu *rvu, struct npc_mcam *mcam, int blkaddr,
1006 int index);
1007 int rvu_npc_init(struct rvu *rvu);
1008 int npc_install_mcam_drop_rule(struct rvu *rvu, int mcam_idx, u16 *counter_idx,
1009 u64 chan_val, u64 chan_mask, u64 exact_val, u64 exact_mask,
1010 u64 bcast_mcast_val, u64 bcast_mcast_mask);
1011 void npc_mcam_rsrcs_reserve(struct rvu *rvu, int blkaddr, int entry_idx);
1012 bool npc_is_feature_supported(struct rvu *rvu, u64 features, u8 intf);
1013 int npc_mcam_rsrcs_init(struct rvu *rvu, int blkaddr);
1014 void npc_mcam_rsrcs_deinit(struct rvu *rvu);
1015
1016 /* CPT APIs */
1017 int rvu_cpt_register_interrupts(struct rvu *rvu);
1018 void rvu_cpt_unregister_interrupts(struct rvu *rvu);
1019 int rvu_cpt_lf_teardown(struct rvu *rvu, u16 pcifunc, int blkaddr, int lf,
1020 int slot);
1021 int rvu_cpt_ctx_flush(struct rvu *rvu, u16 pcifunc);
1022 int rvu_cpt_init(struct rvu *rvu);
1023
1024 #define NDC_AF_BANK_MASK GENMASK_ULL(7, 0)
1025 #define NDC_AF_BANK_LINE_MASK GENMASK_ULL(31, 16)
1026
1027 /* CN10K RVU */
1028 int rvu_set_channels_base(struct rvu *rvu);
1029 void rvu_program_channels(struct rvu *rvu);
1030
1031 /* CN10K NIX */
1032 void rvu_nix_block_cn10k_init(struct rvu *rvu, struct nix_hw *nix_hw);
1033
1034 /* CN10K RVU - LMT*/
1035 void rvu_reset_lmt_map_tbl(struct rvu *rvu, u16 pcifunc);
1036 void rvu_apr_block_cn10k_init(struct rvu *rvu);
1037
1038 #ifdef CONFIG_DEBUG_FS
1039 void rvu_dbg_init(struct rvu *rvu);
1040 void rvu_dbg_exit(struct rvu *rvu);
1041 #else
rvu_dbg_init(struct rvu * rvu)1042 static inline void rvu_dbg_init(struct rvu *rvu) {}
rvu_dbg_exit(struct rvu * rvu)1043 static inline void rvu_dbg_exit(struct rvu *rvu) {}
1044 #endif
1045
1046 int rvu_ndc_fix_locked_cacheline(struct rvu *rvu, int blkaddr);
1047
1048 /* RVU Switch */
1049 void rvu_switch_enable(struct rvu *rvu);
1050 void rvu_switch_disable(struct rvu *rvu);
1051 void rvu_switch_update_rules(struct rvu *rvu, u16 pcifunc);
1052
1053 int rvu_npc_set_parse_mode(struct rvu *rvu, u16 pcifunc, u64 mode, u8 dir,
1054 u64 pkind, u8 var_len_off, u8 var_len_off_mask,
1055 u8 shift_dir);
1056 int rvu_get_hwvf(struct rvu *rvu, int pcifunc);
1057
1058 /* CN10K MCS */
1059 int rvu_mcs_init(struct rvu *rvu);
1060 int rvu_mcs_flr_handler(struct rvu *rvu, u16 pcifunc);
1061 void rvu_mcs_ptp_cfg(struct rvu *rvu, u8 rpm_id, u8 lmac_id, bool ena);
1062 void rvu_mcs_exit(struct rvu *rvu);
1063
1064 #endif /* RVU_H */
1065