1 /*
2 * Copyright (c) 2018, Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33 #include <linux/bpf_trace.h>
34 #include <net/xdp_sock_drv.h>
35 #include "en/xdp.h"
36 #include "en/params.h"
37 #include <linux/bitfield.h>
38 #include <net/page_pool/helpers.h>
39
mlx5e_xdp_max_mtu(struct mlx5e_params * params,struct mlx5e_xsk_param * xsk)40 int mlx5e_xdp_max_mtu(struct mlx5e_params *params, struct mlx5e_xsk_param *xsk)
41 {
42 int hr = mlx5e_get_linear_rq_headroom(params, xsk);
43
44 /* Let S := SKB_DATA_ALIGN(sizeof(struct skb_shared_info)).
45 * The condition checked in mlx5e_rx_is_linear_skb is:
46 * SKB_DATA_ALIGN(sw_mtu + hard_mtu + hr) + S <= PAGE_SIZE (1)
47 * (Note that hw_mtu == sw_mtu + hard_mtu.)
48 * What is returned from this function is:
49 * max_mtu = PAGE_SIZE - S - hr - hard_mtu (2)
50 * After assigning sw_mtu := max_mtu, the left side of (1) turns to
51 * SKB_DATA_ALIGN(PAGE_SIZE - S) + S, which is equal to PAGE_SIZE,
52 * because both PAGE_SIZE and S are already aligned. Any number greater
53 * than max_mtu would make the left side of (1) greater than PAGE_SIZE,
54 * so max_mtu is the maximum MTU allowed.
55 */
56
57 return MLX5E_HW2SW_MTU(params, SKB_MAX_HEAD(hr));
58 }
59
60 static inline bool
mlx5e_xmit_xdp_buff(struct mlx5e_xdpsq * sq,struct mlx5e_rq * rq,struct xdp_buff * xdp)61 mlx5e_xmit_xdp_buff(struct mlx5e_xdpsq *sq, struct mlx5e_rq *rq,
62 struct xdp_buff *xdp)
63 {
64 struct page *page = virt_to_page(xdp->data);
65 struct mlx5e_xmit_data_frags xdptxdf = {};
66 struct mlx5e_xmit_data *xdptxd;
67 struct xdp_frame *xdpf;
68 dma_addr_t dma_addr;
69 int i;
70
71 xdpf = xdp_convert_buff_to_frame(xdp);
72 if (unlikely(!xdpf))
73 return false;
74
75 xdptxd = &xdptxdf.xd;
76 xdptxd->data = xdpf->data;
77 xdptxd->len = xdpf->len;
78 xdptxd->has_frags = xdp_frame_has_frags(xdpf);
79
80 if (xdp->rxq->mem.type == MEM_TYPE_XSK_BUFF_POOL) {
81 /* The xdp_buff was in the UMEM and was copied into a newly
82 * allocated page. The UMEM page was returned via the ZCA, and
83 * this new page has to be mapped at this point and has to be
84 * unmapped and returned via xdp_return_frame on completion.
85 */
86
87 /* Prevent double recycling of the UMEM page. Even in case this
88 * function returns false, the xdp_buff shouldn't be recycled,
89 * as it was already done in xdp_convert_zc_to_xdp_frame.
90 */
91 __set_bit(MLX5E_RQ_FLAG_XDP_XMIT, rq->flags); /* non-atomic */
92
93 if (unlikely(xdptxd->has_frags))
94 return false;
95
96 dma_addr = dma_map_single(sq->pdev, xdptxd->data, xdptxd->len,
97 DMA_TO_DEVICE);
98 if (dma_mapping_error(sq->pdev, dma_addr)) {
99 xdp_return_frame(xdpf);
100 return false;
101 }
102
103 xdptxd->dma_addr = dma_addr;
104
105 if (unlikely(!INDIRECT_CALL_2(sq->xmit_xdp_frame, mlx5e_xmit_xdp_frame_mpwqe,
106 mlx5e_xmit_xdp_frame, sq, xdptxd, 0, NULL)))
107 return false;
108
109 /* xmit_mode == MLX5E_XDP_XMIT_MODE_FRAME */
110 mlx5e_xdpi_fifo_push(&sq->db.xdpi_fifo,
111 (union mlx5e_xdp_info) { .mode = MLX5E_XDP_XMIT_MODE_FRAME });
112 mlx5e_xdpi_fifo_push(&sq->db.xdpi_fifo,
113 (union mlx5e_xdp_info) { .frame.xdpf = xdpf });
114 mlx5e_xdpi_fifo_push(&sq->db.xdpi_fifo,
115 (union mlx5e_xdp_info) { .frame.dma_addr = dma_addr });
116 return true;
117 }
118
119 /* Driver assumes that xdp_convert_buff_to_frame returns an xdp_frame
120 * that points to the same memory region as the original xdp_buff. It
121 * allows to map the memory only once and to use the DMA_BIDIRECTIONAL
122 * mode.
123 */
124
125 dma_addr = page_pool_get_dma_addr(page) + (xdpf->data - (void *)xdpf);
126 dma_sync_single_for_device(sq->pdev, dma_addr, xdptxd->len, DMA_BIDIRECTIONAL);
127
128 if (xdptxd->has_frags) {
129 xdptxdf.sinfo = xdp_get_shared_info_from_frame(xdpf);
130 xdptxdf.dma_arr = NULL;
131
132 for (i = 0; i < xdptxdf.sinfo->nr_frags; i++) {
133 skb_frag_t *frag = &xdptxdf.sinfo->frags[i];
134 dma_addr_t addr;
135 u32 len;
136
137 addr = page_pool_get_dma_addr(skb_frag_page(frag)) +
138 skb_frag_off(frag);
139 len = skb_frag_size(frag);
140 dma_sync_single_for_device(sq->pdev, addr, len,
141 DMA_BIDIRECTIONAL);
142 }
143 }
144
145 xdptxd->dma_addr = dma_addr;
146
147 if (unlikely(!INDIRECT_CALL_2(sq->xmit_xdp_frame, mlx5e_xmit_xdp_frame_mpwqe,
148 mlx5e_xmit_xdp_frame, sq, xdptxd, 0, NULL)))
149 return false;
150
151 /* xmit_mode == MLX5E_XDP_XMIT_MODE_PAGE */
152 mlx5e_xdpi_fifo_push(&sq->db.xdpi_fifo,
153 (union mlx5e_xdp_info) { .mode = MLX5E_XDP_XMIT_MODE_PAGE });
154
155 if (xdptxd->has_frags) {
156 mlx5e_xdpi_fifo_push(&sq->db.xdpi_fifo,
157 (union mlx5e_xdp_info)
158 { .page.num = 1 + xdptxdf.sinfo->nr_frags });
159 mlx5e_xdpi_fifo_push(&sq->db.xdpi_fifo,
160 (union mlx5e_xdp_info) { .page.page = page });
161 for (i = 0; i < xdptxdf.sinfo->nr_frags; i++) {
162 skb_frag_t *frag = &xdptxdf.sinfo->frags[i];
163
164 mlx5e_xdpi_fifo_push(&sq->db.xdpi_fifo,
165 (union mlx5e_xdp_info)
166 { .page.page = skb_frag_page(frag) });
167 }
168 } else {
169 mlx5e_xdpi_fifo_push(&sq->db.xdpi_fifo,
170 (union mlx5e_xdp_info) { .page.num = 1 });
171 mlx5e_xdpi_fifo_push(&sq->db.xdpi_fifo,
172 (union mlx5e_xdp_info) { .page.page = page });
173 }
174
175 return true;
176 }
177
mlx5e_xdp_rx_timestamp(const struct xdp_md * ctx,u64 * timestamp)178 static int mlx5e_xdp_rx_timestamp(const struct xdp_md *ctx, u64 *timestamp)
179 {
180 const struct mlx5e_xdp_buff *_ctx = (void *)ctx;
181
182 if (unlikely(!mlx5e_rx_hw_stamp(_ctx->rq->tstamp)))
183 return -ENODATA;
184
185 *timestamp = mlx5e_cqe_ts_to_ns(_ctx->rq->ptp_cyc2time,
186 _ctx->rq->clock, get_cqe_ts(_ctx->cqe));
187 return 0;
188 }
189
190 /* Mapping HW RSS Type bits CQE_RSS_HTYPE_IP + CQE_RSS_HTYPE_L4 into 4-bits*/
191 #define RSS_TYPE_MAX_TABLE 16 /* 4-bits max 16 entries */
192 #define RSS_L4 GENMASK(1, 0)
193 #define RSS_L3 GENMASK(3, 2) /* Same as CQE_RSS_HTYPE_IP */
194
195 /* Valid combinations of CQE_RSS_HTYPE_IP + CQE_RSS_HTYPE_L4 sorted numerical */
196 enum mlx5_rss_hash_type {
197 RSS_TYPE_NO_HASH = (FIELD_PREP_CONST(RSS_L3, CQE_RSS_IP_NONE) |
198 FIELD_PREP_CONST(RSS_L4, CQE_RSS_L4_NONE)),
199 RSS_TYPE_L3_IPV4 = (FIELD_PREP_CONST(RSS_L3, CQE_RSS_IPV4) |
200 FIELD_PREP_CONST(RSS_L4, CQE_RSS_L4_NONE)),
201 RSS_TYPE_L4_IPV4_TCP = (FIELD_PREP_CONST(RSS_L3, CQE_RSS_IPV4) |
202 FIELD_PREP_CONST(RSS_L4, CQE_RSS_L4_TCP)),
203 RSS_TYPE_L4_IPV4_UDP = (FIELD_PREP_CONST(RSS_L3, CQE_RSS_IPV4) |
204 FIELD_PREP_CONST(RSS_L4, CQE_RSS_L4_UDP)),
205 RSS_TYPE_L4_IPV4_IPSEC = (FIELD_PREP_CONST(RSS_L3, CQE_RSS_IPV4) |
206 FIELD_PREP_CONST(RSS_L4, CQE_RSS_L4_IPSEC)),
207 RSS_TYPE_L3_IPV6 = (FIELD_PREP_CONST(RSS_L3, CQE_RSS_IPV6) |
208 FIELD_PREP_CONST(RSS_L4, CQE_RSS_L4_NONE)),
209 RSS_TYPE_L4_IPV6_TCP = (FIELD_PREP_CONST(RSS_L3, CQE_RSS_IPV6) |
210 FIELD_PREP_CONST(RSS_L4, CQE_RSS_L4_TCP)),
211 RSS_TYPE_L4_IPV6_UDP = (FIELD_PREP_CONST(RSS_L3, CQE_RSS_IPV6) |
212 FIELD_PREP_CONST(RSS_L4, CQE_RSS_L4_UDP)),
213 RSS_TYPE_L4_IPV6_IPSEC = (FIELD_PREP_CONST(RSS_L3, CQE_RSS_IPV6) |
214 FIELD_PREP_CONST(RSS_L4, CQE_RSS_L4_IPSEC)),
215 };
216
217 /* Invalid combinations will simply return zero, allows no boundary checks */
218 static const enum xdp_rss_hash_type mlx5_xdp_rss_type[RSS_TYPE_MAX_TABLE] = {
219 [RSS_TYPE_NO_HASH] = XDP_RSS_TYPE_NONE,
220 [1] = XDP_RSS_TYPE_NONE, /* Implicit zero */
221 [2] = XDP_RSS_TYPE_NONE, /* Implicit zero */
222 [3] = XDP_RSS_TYPE_NONE, /* Implicit zero */
223 [RSS_TYPE_L3_IPV4] = XDP_RSS_TYPE_L3_IPV4,
224 [RSS_TYPE_L4_IPV4_TCP] = XDP_RSS_TYPE_L4_IPV4_TCP,
225 [RSS_TYPE_L4_IPV4_UDP] = XDP_RSS_TYPE_L4_IPV4_UDP,
226 [RSS_TYPE_L4_IPV4_IPSEC] = XDP_RSS_TYPE_L4_IPV4_IPSEC,
227 [RSS_TYPE_L3_IPV6] = XDP_RSS_TYPE_L3_IPV6,
228 [RSS_TYPE_L4_IPV6_TCP] = XDP_RSS_TYPE_L4_IPV6_TCP,
229 [RSS_TYPE_L4_IPV6_UDP] = XDP_RSS_TYPE_L4_IPV6_UDP,
230 [RSS_TYPE_L4_IPV6_IPSEC] = XDP_RSS_TYPE_L4_IPV6_IPSEC,
231 [12] = XDP_RSS_TYPE_NONE, /* Implicit zero */
232 [13] = XDP_RSS_TYPE_NONE, /* Implicit zero */
233 [14] = XDP_RSS_TYPE_NONE, /* Implicit zero */
234 [15] = XDP_RSS_TYPE_NONE, /* Implicit zero */
235 };
236
mlx5e_xdp_rx_hash(const struct xdp_md * ctx,u32 * hash,enum xdp_rss_hash_type * rss_type)237 static int mlx5e_xdp_rx_hash(const struct xdp_md *ctx, u32 *hash,
238 enum xdp_rss_hash_type *rss_type)
239 {
240 const struct mlx5e_xdp_buff *_ctx = (void *)ctx;
241 const struct mlx5_cqe64 *cqe = _ctx->cqe;
242 u32 hash_type, l4_type, ip_type, lookup;
243
244 if (unlikely(!(_ctx->xdp.rxq->dev->features & NETIF_F_RXHASH)))
245 return -ENODATA;
246
247 *hash = be32_to_cpu(cqe->rss_hash_result);
248
249 hash_type = cqe->rss_hash_type;
250 BUILD_BUG_ON(CQE_RSS_HTYPE_IP != RSS_L3); /* same mask */
251 ip_type = hash_type & CQE_RSS_HTYPE_IP;
252 l4_type = FIELD_GET(CQE_RSS_HTYPE_L4, hash_type);
253 lookup = ip_type | l4_type;
254 *rss_type = mlx5_xdp_rss_type[lookup];
255
256 return 0;
257 }
258
mlx5e_xdp_rx_vlan_tag(const struct xdp_md * ctx,__be16 * vlan_proto,u16 * vlan_tci)259 static int mlx5e_xdp_rx_vlan_tag(const struct xdp_md *ctx, __be16 *vlan_proto,
260 u16 *vlan_tci)
261 {
262 const struct mlx5e_xdp_buff *_ctx = (void *)ctx;
263 const struct mlx5_cqe64 *cqe = _ctx->cqe;
264
265 if (!cqe_has_vlan(cqe))
266 return -ENODATA;
267
268 *vlan_proto = htons(ETH_P_8021Q);
269 *vlan_tci = be16_to_cpu(cqe->vlan_info);
270 return 0;
271 }
272
273 const struct xdp_metadata_ops mlx5e_xdp_metadata_ops = {
274 .xmo_rx_timestamp = mlx5e_xdp_rx_timestamp,
275 .xmo_rx_hash = mlx5e_xdp_rx_hash,
276 .xmo_rx_vlan_tag = mlx5e_xdp_rx_vlan_tag,
277 };
278
279 struct mlx5e_xsk_tx_complete {
280 struct mlx5_cqe64 *cqe;
281 struct mlx5e_cq *cq;
282 };
283
mlx5e_xsk_fill_timestamp(void * _priv)284 static u64 mlx5e_xsk_fill_timestamp(void *_priv)
285 {
286 struct mlx5e_xsk_tx_complete *priv = _priv;
287 u64 ts;
288
289 ts = get_cqe_ts(priv->cqe);
290
291 if (mlx5_is_real_time_rq(priv->cq->mdev) || mlx5_is_real_time_sq(priv->cq->mdev))
292 return mlx5_real_time_cyc2time(&priv->cq->mdev->clock, ts);
293
294 return mlx5_timecounter_cyc2time(&priv->cq->mdev->clock, ts);
295 }
296
mlx5e_xsk_request_checksum(u16 csum_start,u16 csum_offset,void * priv)297 static void mlx5e_xsk_request_checksum(u16 csum_start, u16 csum_offset, void *priv)
298 {
299 struct mlx5_wqe_eth_seg *eseg = priv;
300
301 /* HW/FW is doing parsing, so offsets are largely ignored. */
302 eseg->cs_flags |= MLX5_ETH_WQE_L3_CSUM | MLX5_ETH_WQE_L4_CSUM;
303 }
304
305 const struct xsk_tx_metadata_ops mlx5e_xsk_tx_metadata_ops = {
306 .tmo_fill_timestamp = mlx5e_xsk_fill_timestamp,
307 .tmo_request_checksum = mlx5e_xsk_request_checksum,
308 };
309
310 /* returns true if packet was consumed by xdp */
mlx5e_xdp_handle(struct mlx5e_rq * rq,struct bpf_prog * prog,struct mlx5e_xdp_buff * mxbuf)311 bool mlx5e_xdp_handle(struct mlx5e_rq *rq,
312 struct bpf_prog *prog, struct mlx5e_xdp_buff *mxbuf)
313 {
314 struct xdp_buff *xdp = &mxbuf->xdp;
315 u32 act;
316 int err;
317
318 act = bpf_prog_run_xdp(prog, xdp);
319 switch (act) {
320 case XDP_PASS:
321 return false;
322 case XDP_TX:
323 if (unlikely(!mlx5e_xmit_xdp_buff(rq->xdpsq, rq, xdp)))
324 goto xdp_abort;
325 __set_bit(MLX5E_RQ_FLAG_XDP_XMIT, rq->flags); /* non-atomic */
326 return true;
327 case XDP_REDIRECT:
328 /* When XDP enabled then page-refcnt==1 here */
329 err = xdp_do_redirect(rq->netdev, xdp, prog);
330 if (unlikely(err))
331 goto xdp_abort;
332 __set_bit(MLX5E_RQ_FLAG_XDP_XMIT, rq->flags);
333 __set_bit(MLX5E_RQ_FLAG_XDP_REDIRECT, rq->flags);
334 rq->stats->xdp_redirect++;
335 return true;
336 default:
337 bpf_warn_invalid_xdp_action(rq->netdev, prog, act);
338 fallthrough;
339 case XDP_ABORTED:
340 xdp_abort:
341 trace_xdp_exception(rq->netdev, prog, act);
342 fallthrough;
343 case XDP_DROP:
344 rq->stats->xdp_drop++;
345 return true;
346 }
347 }
348
mlx5e_xdpsq_get_next_pi(struct mlx5e_xdpsq * sq,u16 size)349 static u16 mlx5e_xdpsq_get_next_pi(struct mlx5e_xdpsq *sq, u16 size)
350 {
351 struct mlx5_wq_cyc *wq = &sq->wq;
352 u16 pi, contig_wqebbs;
353
354 pi = mlx5_wq_cyc_ctr2ix(wq, sq->pc);
355 contig_wqebbs = mlx5_wq_cyc_get_contig_wqebbs(wq, pi);
356 if (unlikely(contig_wqebbs < size)) {
357 struct mlx5e_xdp_wqe_info *wi, *edge_wi;
358
359 wi = &sq->db.wqe_info[pi];
360 edge_wi = wi + contig_wqebbs;
361
362 /* Fill SQ frag edge with NOPs to avoid WQE wrapping two pages. */
363 for (; wi < edge_wi; wi++) {
364 *wi = (struct mlx5e_xdp_wqe_info) {
365 .num_wqebbs = 1,
366 .num_pkts = 0,
367 };
368 mlx5e_post_nop(wq, sq->sqn, &sq->pc);
369 }
370 sq->stats->nops += contig_wqebbs;
371
372 pi = mlx5_wq_cyc_ctr2ix(wq, sq->pc);
373 }
374
375 return pi;
376 }
377
mlx5e_xdp_mpwqe_session_start(struct mlx5e_xdpsq * sq)378 static void mlx5e_xdp_mpwqe_session_start(struct mlx5e_xdpsq *sq)
379 {
380 struct mlx5e_tx_mpwqe *session = &sq->mpwqe;
381 struct mlx5e_xdpsq_stats *stats = sq->stats;
382 struct mlx5e_tx_wqe *wqe;
383 u16 pi;
384
385 pi = mlx5e_xdpsq_get_next_pi(sq, sq->max_sq_mpw_wqebbs);
386 wqe = MLX5E_TX_FETCH_WQE(sq, pi);
387 net_prefetchw(wqe->data);
388
389 *session = (struct mlx5e_tx_mpwqe) {
390 .wqe = wqe,
391 .bytes_count = 0,
392 .ds_count = MLX5E_TX_WQE_EMPTY_DS_COUNT,
393 .pkt_count = 0,
394 .inline_on = mlx5e_xdp_get_inline_state(sq, session->inline_on),
395 };
396
397 stats->mpwqe++;
398 }
399
mlx5e_xdp_mpwqe_complete(struct mlx5e_xdpsq * sq)400 void mlx5e_xdp_mpwqe_complete(struct mlx5e_xdpsq *sq)
401 {
402 struct mlx5_wq_cyc *wq = &sq->wq;
403 struct mlx5e_tx_mpwqe *session = &sq->mpwqe;
404 struct mlx5_wqe_ctrl_seg *cseg = &session->wqe->ctrl;
405 u16 ds_count = session->ds_count;
406 u16 pi = mlx5_wq_cyc_ctr2ix(wq, sq->pc);
407 struct mlx5e_xdp_wqe_info *wi = &sq->db.wqe_info[pi];
408
409 cseg->opmod_idx_opcode =
410 cpu_to_be32((sq->pc << 8) | MLX5_OPCODE_ENHANCED_MPSW);
411 cseg->qpn_ds = cpu_to_be32((sq->sqn << 8) | ds_count);
412
413 wi->num_wqebbs = DIV_ROUND_UP(ds_count, MLX5_SEND_WQEBB_NUM_DS);
414 wi->num_pkts = session->pkt_count;
415
416 sq->pc += wi->num_wqebbs;
417
418 sq->doorbell_cseg = cseg;
419
420 session->wqe = NULL; /* Close session */
421 }
422
423 enum {
424 MLX5E_XDP_CHECK_OK = 1,
425 MLX5E_XDP_CHECK_START_MPWQE = 2,
426 };
427
mlx5e_xmit_xdp_frame_check_mpwqe(struct mlx5e_xdpsq * sq)428 INDIRECT_CALLABLE_SCOPE int mlx5e_xmit_xdp_frame_check_mpwqe(struct mlx5e_xdpsq *sq)
429 {
430 if (unlikely(!sq->mpwqe.wqe)) {
431 if (unlikely(!mlx5e_wqc_has_room_for(&sq->wq, sq->cc, sq->pc,
432 sq->stop_room))) {
433 /* SQ is full, ring doorbell */
434 mlx5e_xmit_xdp_doorbell(sq);
435 sq->stats->full++;
436 return -EBUSY;
437 }
438
439 return MLX5E_XDP_CHECK_START_MPWQE;
440 }
441
442 return MLX5E_XDP_CHECK_OK;
443 }
444
445 INDIRECT_CALLABLE_SCOPE bool
446 mlx5e_xmit_xdp_frame(struct mlx5e_xdpsq *sq, struct mlx5e_xmit_data *xdptxd,
447 int check_result, struct xsk_tx_metadata *meta);
448
449 INDIRECT_CALLABLE_SCOPE bool
mlx5e_xmit_xdp_frame_mpwqe(struct mlx5e_xdpsq * sq,struct mlx5e_xmit_data * xdptxd,int check_result,struct xsk_tx_metadata * meta)450 mlx5e_xmit_xdp_frame_mpwqe(struct mlx5e_xdpsq *sq, struct mlx5e_xmit_data *xdptxd,
451 int check_result, struct xsk_tx_metadata *meta)
452 {
453 struct mlx5e_tx_mpwqe *session = &sq->mpwqe;
454 struct mlx5e_xdpsq_stats *stats = sq->stats;
455 struct mlx5e_xmit_data *p = xdptxd;
456 struct mlx5e_xmit_data tmp;
457
458 if (xdptxd->has_frags) {
459 struct mlx5e_xmit_data_frags *xdptxdf =
460 container_of(xdptxd, struct mlx5e_xmit_data_frags, xd);
461
462 if (!!xdptxd->len + xdptxdf->sinfo->nr_frags > 1) {
463 /* MPWQE is enabled, but a multi-buffer packet is queued for
464 * transmission. MPWQE can't send fragmented packets, so close
465 * the current session and fall back to a regular WQE.
466 */
467 if (unlikely(sq->mpwqe.wqe))
468 mlx5e_xdp_mpwqe_complete(sq);
469 return mlx5e_xmit_xdp_frame(sq, xdptxd, 0, meta);
470 }
471 if (!xdptxd->len) {
472 skb_frag_t *frag = &xdptxdf->sinfo->frags[0];
473
474 tmp.data = skb_frag_address(frag);
475 tmp.len = skb_frag_size(frag);
476 tmp.dma_addr = xdptxdf->dma_arr ? xdptxdf->dma_arr[0] :
477 page_pool_get_dma_addr(skb_frag_page(frag)) +
478 skb_frag_off(frag);
479 p = &tmp;
480 }
481 }
482
483 if (unlikely(p->len > sq->hw_mtu)) {
484 stats->err++;
485 return false;
486 }
487
488 if (!check_result)
489 check_result = mlx5e_xmit_xdp_frame_check_mpwqe(sq);
490 if (unlikely(check_result < 0))
491 return false;
492
493 if (check_result == MLX5E_XDP_CHECK_START_MPWQE) {
494 /* Start the session when nothing can fail, so it's guaranteed
495 * that if there is an active session, it has at least one dseg,
496 * and it's safe to complete it at any time.
497 */
498 mlx5e_xdp_mpwqe_session_start(sq);
499 xsk_tx_metadata_request(meta, &mlx5e_xsk_tx_metadata_ops, &session->wqe->eth);
500 }
501
502 mlx5e_xdp_mpwqe_add_dseg(sq, p, stats);
503
504 if (unlikely(mlx5e_xdp_mpwqe_is_full(session, sq->max_sq_mpw_wqebbs)))
505 mlx5e_xdp_mpwqe_complete(sq);
506
507 stats->xmit++;
508 return true;
509 }
510
mlx5e_xmit_xdp_frame_check_stop_room(struct mlx5e_xdpsq * sq,int stop_room)511 static int mlx5e_xmit_xdp_frame_check_stop_room(struct mlx5e_xdpsq *sq, int stop_room)
512 {
513 if (unlikely(!mlx5e_wqc_has_room_for(&sq->wq, sq->cc, sq->pc, stop_room))) {
514 /* SQ is full, ring doorbell */
515 mlx5e_xmit_xdp_doorbell(sq);
516 sq->stats->full++;
517 return -EBUSY;
518 }
519
520 return MLX5E_XDP_CHECK_OK;
521 }
522
mlx5e_xmit_xdp_frame_check(struct mlx5e_xdpsq * sq)523 INDIRECT_CALLABLE_SCOPE int mlx5e_xmit_xdp_frame_check(struct mlx5e_xdpsq *sq)
524 {
525 return mlx5e_xmit_xdp_frame_check_stop_room(sq, 1);
526 }
527
528 INDIRECT_CALLABLE_SCOPE bool
mlx5e_xmit_xdp_frame(struct mlx5e_xdpsq * sq,struct mlx5e_xmit_data * xdptxd,int check_result,struct xsk_tx_metadata * meta)529 mlx5e_xmit_xdp_frame(struct mlx5e_xdpsq *sq, struct mlx5e_xmit_data *xdptxd,
530 int check_result, struct xsk_tx_metadata *meta)
531 {
532 struct mlx5e_xmit_data_frags *xdptxdf =
533 container_of(xdptxd, struct mlx5e_xmit_data_frags, xd);
534 struct mlx5_wq_cyc *wq = &sq->wq;
535 struct mlx5_wqe_ctrl_seg *cseg;
536 struct mlx5_wqe_data_seg *dseg;
537 struct mlx5_wqe_eth_seg *eseg;
538 struct mlx5e_tx_wqe *wqe;
539
540 dma_addr_t dma_addr = xdptxd->dma_addr;
541 u32 dma_len = xdptxd->len;
542 u16 ds_cnt, inline_hdr_sz;
543 unsigned int frags_size;
544 u8 num_wqebbs = 1;
545 int num_frags = 0;
546 bool inline_ok;
547 bool linear;
548 u16 pi;
549 int i;
550
551 struct mlx5e_xdpsq_stats *stats = sq->stats;
552
553 inline_ok = sq->min_inline_mode == MLX5_INLINE_MODE_NONE ||
554 dma_len >= MLX5E_XDP_MIN_INLINE;
555 frags_size = xdptxd->has_frags ? xdptxdf->sinfo->xdp_frags_size : 0;
556
557 if (unlikely(!inline_ok || sq->hw_mtu < dma_len + frags_size)) {
558 stats->err++;
559 return false;
560 }
561
562 inline_hdr_sz = 0;
563 if (sq->min_inline_mode != MLX5_INLINE_MODE_NONE)
564 inline_hdr_sz = MLX5E_XDP_MIN_INLINE;
565
566 linear = !!(dma_len - inline_hdr_sz);
567 ds_cnt = MLX5E_TX_WQE_EMPTY_DS_COUNT + linear + !!inline_hdr_sz;
568
569 /* check_result must be 0 if xdptxd->has_frags is true. */
570 if (!check_result) {
571 int stop_room = 1;
572
573 if (xdptxd->has_frags) {
574 ds_cnt += xdptxdf->sinfo->nr_frags;
575 num_frags = xdptxdf->sinfo->nr_frags;
576 num_wqebbs = DIV_ROUND_UP(ds_cnt, MLX5_SEND_WQEBB_NUM_DS);
577 /* Assuming MLX5_CAP_GEN(mdev, max_wqe_sz_sq) is big
578 * enough to hold all fragments.
579 */
580 stop_room = MLX5E_STOP_ROOM(num_wqebbs);
581 }
582
583 check_result = mlx5e_xmit_xdp_frame_check_stop_room(sq, stop_room);
584 }
585 if (unlikely(check_result < 0))
586 return false;
587
588 pi = mlx5e_xdpsq_get_next_pi(sq, num_wqebbs);
589 wqe = mlx5_wq_cyc_get_wqe(wq, pi);
590 net_prefetchw(wqe);
591
592 cseg = &wqe->ctrl;
593 eseg = &wqe->eth;
594 dseg = wqe->data;
595
596 /* copy the inline part if required */
597 if (inline_hdr_sz) {
598 memcpy(eseg->inline_hdr.start, xdptxd->data, sizeof(eseg->inline_hdr.start));
599 memcpy(dseg, xdptxd->data + sizeof(eseg->inline_hdr.start),
600 inline_hdr_sz - sizeof(eseg->inline_hdr.start));
601 dma_len -= inline_hdr_sz;
602 dma_addr += inline_hdr_sz;
603 dseg++;
604 }
605
606 /* write the dma part */
607 if (linear) {
608 dseg->addr = cpu_to_be64(dma_addr);
609 dseg->byte_count = cpu_to_be32(dma_len);
610 dseg->lkey = sq->mkey_be;
611 dseg++;
612 }
613
614 cseg->opmod_idx_opcode = cpu_to_be32((sq->pc << 8) | MLX5_OPCODE_SEND);
615
616 memset(&cseg->trailer, 0, sizeof(cseg->trailer));
617 memset(eseg, 0, sizeof(*eseg) - sizeof(eseg->trailer));
618
619 eseg->inline_hdr.sz = cpu_to_be16(inline_hdr_sz);
620
621 for (i = 0; i < num_frags; i++) {
622 skb_frag_t *frag = &xdptxdf->sinfo->frags[i];
623 dma_addr_t addr;
624
625 addr = xdptxdf->dma_arr ? xdptxdf->dma_arr[i] :
626 page_pool_get_dma_addr(skb_frag_page(frag)) +
627 skb_frag_off(frag);
628
629 dseg->addr = cpu_to_be64(addr);
630 dseg->byte_count = cpu_to_be32(skb_frag_size(frag));
631 dseg->lkey = sq->mkey_be;
632 dseg++;
633 }
634
635 cseg->qpn_ds = cpu_to_be32((sq->sqn << 8) | ds_cnt);
636
637 sq->db.wqe_info[pi] = (struct mlx5e_xdp_wqe_info) {
638 .num_wqebbs = num_wqebbs,
639 .num_pkts = 1,
640 };
641
642 sq->pc += num_wqebbs;
643
644 xsk_tx_metadata_request(meta, &mlx5e_xsk_tx_metadata_ops, eseg);
645
646 sq->doorbell_cseg = cseg;
647
648 stats->xmit++;
649 return true;
650 }
651
mlx5e_free_xdpsq_desc(struct mlx5e_xdpsq * sq,struct mlx5e_xdp_wqe_info * wi,u32 * xsk_frames,struct xdp_frame_bulk * bq,struct mlx5e_cq * cq,struct mlx5_cqe64 * cqe)652 static void mlx5e_free_xdpsq_desc(struct mlx5e_xdpsq *sq,
653 struct mlx5e_xdp_wqe_info *wi,
654 u32 *xsk_frames,
655 struct xdp_frame_bulk *bq,
656 struct mlx5e_cq *cq,
657 struct mlx5_cqe64 *cqe)
658 {
659 struct mlx5e_xdp_info_fifo *xdpi_fifo = &sq->db.xdpi_fifo;
660 u16 i;
661
662 for (i = 0; i < wi->num_pkts; i++) {
663 union mlx5e_xdp_info xdpi = mlx5e_xdpi_fifo_pop(xdpi_fifo);
664
665 switch (xdpi.mode) {
666 case MLX5E_XDP_XMIT_MODE_FRAME: {
667 /* XDP_TX from the XSK RQ and XDP_REDIRECT */
668 struct xdp_frame *xdpf;
669 dma_addr_t dma_addr;
670
671 xdpi = mlx5e_xdpi_fifo_pop(xdpi_fifo);
672 xdpf = xdpi.frame.xdpf;
673 xdpi = mlx5e_xdpi_fifo_pop(xdpi_fifo);
674 dma_addr = xdpi.frame.dma_addr;
675
676 dma_unmap_single(sq->pdev, dma_addr,
677 xdpf->len, DMA_TO_DEVICE);
678 if (xdp_frame_has_frags(xdpf)) {
679 struct skb_shared_info *sinfo;
680 int j;
681
682 sinfo = xdp_get_shared_info_from_frame(xdpf);
683 for (j = 0; j < sinfo->nr_frags; j++) {
684 skb_frag_t *frag = &sinfo->frags[j];
685
686 xdpi = mlx5e_xdpi_fifo_pop(xdpi_fifo);
687 dma_addr = xdpi.frame.dma_addr;
688
689 dma_unmap_single(sq->pdev, dma_addr,
690 skb_frag_size(frag), DMA_TO_DEVICE);
691 }
692 }
693 xdp_return_frame_bulk(xdpf, bq);
694 break;
695 }
696 case MLX5E_XDP_XMIT_MODE_PAGE: {
697 /* XDP_TX from the regular RQ */
698 u8 num, n = 0;
699
700 xdpi = mlx5e_xdpi_fifo_pop(xdpi_fifo);
701 num = xdpi.page.num;
702
703 do {
704 struct page *page;
705
706 xdpi = mlx5e_xdpi_fifo_pop(xdpi_fifo);
707 page = xdpi.page.page;
708
709 /* No need to check page_pool_page_is_pp() as we
710 * know this is a page_pool page.
711 */
712 page_pool_recycle_direct(page->pp, page);
713 } while (++n < num);
714
715 break;
716 }
717 case MLX5E_XDP_XMIT_MODE_XSK: {
718 /* AF_XDP send */
719 struct xsk_tx_metadata_compl *compl = NULL;
720 struct mlx5e_xsk_tx_complete priv = {
721 .cqe = cqe,
722 .cq = cq,
723 };
724
725 if (xp_tx_metadata_enabled(sq->xsk_pool)) {
726 xdpi = mlx5e_xdpi_fifo_pop(xdpi_fifo);
727 compl = &xdpi.xsk_meta;
728
729 xsk_tx_metadata_complete(compl, &mlx5e_xsk_tx_metadata_ops, &priv);
730 }
731
732 (*xsk_frames)++;
733 break;
734 }
735 default:
736 WARN_ON_ONCE(true);
737 }
738 }
739 }
740
mlx5e_poll_xdpsq_cq(struct mlx5e_cq * cq)741 bool mlx5e_poll_xdpsq_cq(struct mlx5e_cq *cq)
742 {
743 struct xdp_frame_bulk bq;
744 struct mlx5e_xdpsq *sq;
745 struct mlx5_cqe64 *cqe;
746 u32 xsk_frames = 0;
747 u16 sqcc;
748 int i;
749
750 xdp_frame_bulk_init(&bq);
751
752 sq = container_of(cq, struct mlx5e_xdpsq, cq);
753
754 if (unlikely(!test_bit(MLX5E_SQ_STATE_ENABLED, &sq->state)))
755 return false;
756
757 cqe = mlx5_cqwq_get_cqe(&cq->wq);
758 if (!cqe)
759 return false;
760
761 /* sq->cc must be updated only after mlx5_cqwq_update_db_record(),
762 * otherwise a cq overrun may occur
763 */
764 sqcc = sq->cc;
765
766 i = 0;
767 do {
768 struct mlx5e_xdp_wqe_info *wi;
769 u16 wqe_counter, ci;
770 bool last_wqe;
771
772 mlx5_cqwq_pop(&cq->wq);
773
774 wqe_counter = be16_to_cpu(cqe->wqe_counter);
775
776 do {
777 last_wqe = (sqcc == wqe_counter);
778 ci = mlx5_wq_cyc_ctr2ix(&sq->wq, sqcc);
779 wi = &sq->db.wqe_info[ci];
780
781 sqcc += wi->num_wqebbs;
782
783 mlx5e_free_xdpsq_desc(sq, wi, &xsk_frames, &bq, cq, cqe);
784 } while (!last_wqe);
785
786 if (unlikely(get_cqe_opcode(cqe) != MLX5_CQE_REQ)) {
787 netdev_WARN_ONCE(sq->channel->netdev,
788 "Bad OP in XDPSQ CQE: 0x%x\n",
789 get_cqe_opcode(cqe));
790 mlx5e_dump_error_cqe(&sq->cq, sq->sqn,
791 (struct mlx5_err_cqe *)cqe);
792 mlx5_wq_cyc_wqe_dump(&sq->wq, ci, wi->num_wqebbs);
793 }
794 } while ((++i < MLX5E_TX_CQ_POLL_BUDGET) && (cqe = mlx5_cqwq_get_cqe(&cq->wq)));
795
796 xdp_flush_frame_bulk(&bq);
797
798 if (xsk_frames)
799 xsk_tx_completed(sq->xsk_pool, xsk_frames);
800
801 sq->stats->cqes += i;
802
803 mlx5_cqwq_update_db_record(&cq->wq);
804
805 /* ensure cq space is freed before enabling more cqes */
806 wmb();
807
808 sq->cc = sqcc;
809 return (i == MLX5E_TX_CQ_POLL_BUDGET);
810 }
811
mlx5e_free_xdpsq_descs(struct mlx5e_xdpsq * sq)812 void mlx5e_free_xdpsq_descs(struct mlx5e_xdpsq *sq)
813 {
814 struct xdp_frame_bulk bq;
815 u32 xsk_frames = 0;
816
817 xdp_frame_bulk_init(&bq);
818
819 rcu_read_lock(); /* need for xdp_return_frame_bulk */
820
821 while (sq->cc != sq->pc) {
822 struct mlx5e_xdp_wqe_info *wi;
823 u16 ci;
824
825 ci = mlx5_wq_cyc_ctr2ix(&sq->wq, sq->cc);
826 wi = &sq->db.wqe_info[ci];
827
828 sq->cc += wi->num_wqebbs;
829
830 mlx5e_free_xdpsq_desc(sq, wi, &xsk_frames, &bq, NULL, NULL);
831 }
832
833 xdp_flush_frame_bulk(&bq);
834 rcu_read_unlock();
835
836 if (xsk_frames)
837 xsk_tx_completed(sq->xsk_pool, xsk_frames);
838 }
839
mlx5e_xdp_xmit(struct net_device * dev,int n,struct xdp_frame ** frames,u32 flags)840 int mlx5e_xdp_xmit(struct net_device *dev, int n, struct xdp_frame **frames,
841 u32 flags)
842 {
843 struct mlx5e_priv *priv = netdev_priv(dev);
844 struct mlx5e_xdpsq *sq;
845 int nxmit = 0;
846 int sq_num;
847 int i;
848
849 /* this flag is sufficient, no need to test internal sq state */
850 if (unlikely(!mlx5e_xdp_tx_is_enabled(priv)))
851 return -ENETDOWN;
852
853 if (unlikely(flags & ~XDP_XMIT_FLAGS_MASK))
854 return -EINVAL;
855
856 sq_num = smp_processor_id();
857
858 if (unlikely(sq_num >= priv->channels.num))
859 return -ENXIO;
860
861 sq = &priv->channels.c[sq_num]->xdpsq;
862
863 for (i = 0; i < n; i++) {
864 struct mlx5e_xmit_data_frags xdptxdf = {};
865 struct xdp_frame *xdpf = frames[i];
866 dma_addr_t dma_arr[MAX_SKB_FRAGS];
867 struct mlx5e_xmit_data *xdptxd;
868 bool ret;
869
870 xdptxd = &xdptxdf.xd;
871 xdptxd->data = xdpf->data;
872 xdptxd->len = xdpf->len;
873 xdptxd->has_frags = xdp_frame_has_frags(xdpf);
874 xdptxd->dma_addr = dma_map_single(sq->pdev, xdptxd->data,
875 xdptxd->len, DMA_TO_DEVICE);
876
877 if (unlikely(dma_mapping_error(sq->pdev, xdptxd->dma_addr)))
878 break;
879
880 if (xdptxd->has_frags) {
881 int j;
882
883 xdptxdf.sinfo = xdp_get_shared_info_from_frame(xdpf);
884 xdptxdf.dma_arr = dma_arr;
885 for (j = 0; j < xdptxdf.sinfo->nr_frags; j++) {
886 skb_frag_t *frag = &xdptxdf.sinfo->frags[j];
887
888 dma_arr[j] = dma_map_single(sq->pdev, skb_frag_address(frag),
889 skb_frag_size(frag), DMA_TO_DEVICE);
890
891 if (!dma_mapping_error(sq->pdev, dma_arr[j]))
892 continue;
893 /* mapping error */
894 while (--j >= 0)
895 dma_unmap_single(sq->pdev, dma_arr[j],
896 skb_frag_size(&xdptxdf.sinfo->frags[j]),
897 DMA_TO_DEVICE);
898 goto out;
899 }
900 }
901
902 ret = INDIRECT_CALL_2(sq->xmit_xdp_frame, mlx5e_xmit_xdp_frame_mpwqe,
903 mlx5e_xmit_xdp_frame, sq, xdptxd, 0, NULL);
904 if (unlikely(!ret)) {
905 int j;
906
907 dma_unmap_single(sq->pdev, xdptxd->dma_addr,
908 xdptxd->len, DMA_TO_DEVICE);
909 if (!xdptxd->has_frags)
910 break;
911 for (j = 0; j < xdptxdf.sinfo->nr_frags; j++)
912 dma_unmap_single(sq->pdev, dma_arr[j],
913 skb_frag_size(&xdptxdf.sinfo->frags[j]),
914 DMA_TO_DEVICE);
915 break;
916 }
917
918 /* xmit_mode == MLX5E_XDP_XMIT_MODE_FRAME */
919 mlx5e_xdpi_fifo_push(&sq->db.xdpi_fifo,
920 (union mlx5e_xdp_info) { .mode = MLX5E_XDP_XMIT_MODE_FRAME });
921 mlx5e_xdpi_fifo_push(&sq->db.xdpi_fifo,
922 (union mlx5e_xdp_info) { .frame.xdpf = xdpf });
923 mlx5e_xdpi_fifo_push(&sq->db.xdpi_fifo,
924 (union mlx5e_xdp_info) { .frame.dma_addr = xdptxd->dma_addr });
925 if (xdptxd->has_frags) {
926 int j;
927
928 for (j = 0; j < xdptxdf.sinfo->nr_frags; j++)
929 mlx5e_xdpi_fifo_push(&sq->db.xdpi_fifo,
930 (union mlx5e_xdp_info)
931 { .frame.dma_addr = dma_arr[j] });
932 }
933 nxmit++;
934 }
935
936 out:
937 if (sq->mpwqe.wqe)
938 mlx5e_xdp_mpwqe_complete(sq);
939
940 if (flags & XDP_XMIT_FLUSH)
941 mlx5e_xmit_xdp_doorbell(sq);
942
943 return nxmit;
944 }
945
mlx5e_xdp_rx_poll_complete(struct mlx5e_rq * rq)946 void mlx5e_xdp_rx_poll_complete(struct mlx5e_rq *rq)
947 {
948 struct mlx5e_xdpsq *xdpsq = rq->xdpsq;
949
950 if (xdpsq->mpwqe.wqe)
951 mlx5e_xdp_mpwqe_complete(xdpsq);
952
953 mlx5e_xmit_xdp_doorbell(xdpsq);
954
955 if (test_bit(MLX5E_RQ_FLAG_XDP_REDIRECT, rq->flags)) {
956 xdp_do_flush();
957 __clear_bit(MLX5E_RQ_FLAG_XDP_REDIRECT, rq->flags);
958 }
959 }
960
mlx5e_set_xmit_fp(struct mlx5e_xdpsq * sq,bool is_mpw)961 void mlx5e_set_xmit_fp(struct mlx5e_xdpsq *sq, bool is_mpw)
962 {
963 sq->xmit_xdp_frame_check = is_mpw ?
964 mlx5e_xmit_xdp_frame_check_mpwqe : mlx5e_xmit_xdp_frame_check;
965 sq->xmit_xdp_frame = is_mpw ?
966 mlx5e_xmit_xdp_frame_mpwqe : mlx5e_xmit_xdp_frame;
967 }
968