1 /*
2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33 #include <linux/highmem.h>
34 #include <linux/module.h>
35 #include <linux/init.h>
36 #include <linux/errno.h>
37 #include <linux/pci.h>
38 #include <linux/dma-mapping.h>
39 #include <linux/slab.h>
40 #include <linux/interrupt.h>
41 #include <linux/delay.h>
42 #include <linux/mlx5/driver.h>
43 #include <linux/mlx5/cq.h>
44 #include <linux/mlx5/qp.h>
45 #include <linux/debugfs.h>
46 #include <linux/kmod.h>
47 #include <linux/mlx5/mlx5_ifc.h>
48 #include <linux/mlx5/vport.h>
49 #include <linux/version.h>
50 #include <net/devlink.h>
51 #include "mlx5_core.h"
52 #include "lib/eq.h"
53 #include "fs_core.h"
54 #include "lib/mpfs.h"
55 #include "eswitch.h"
56 #include "devlink.h"
57 #include "fw_reset.h"
58 #include "lib/mlx5.h"
59 #include "lib/tout.h"
60 #include "fpga/core.h"
61 #include "en_accel/ipsec.h"
62 #include "lib/clock.h"
63 #include "lib/vxlan.h"
64 #include "lib/geneve.h"
65 #include "lib/devcom.h"
66 #include "lib/pci_vsc.h"
67 #include "diag/fw_tracer.h"
68 #include "ecpf.h"
69 #include "lib/hv_vhca.h"
70 #include "diag/rsc_dump.h"
71 #include "sf/vhca_event.h"
72 #include "sf/dev/dev.h"
73 #include "sf/sf.h"
74 #include "mlx5_irq.h"
75 #include "hwmon.h"
76 #include "lag/lag.h"
77
78 MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>");
79 MODULE_DESCRIPTION("Mellanox 5th generation network adapters (ConnectX series) core driver");
80 MODULE_LICENSE("Dual BSD/GPL");
81
82 unsigned int mlx5_core_debug_mask;
83 module_param_named(debug_mask, mlx5_core_debug_mask, uint, 0644);
84 MODULE_PARM_DESC(debug_mask, "debug mask: 1 = dump cmd data, 2 = dump cmd exec time, 3 = both. Default=0");
85
86 static unsigned int prof_sel = MLX5_DEFAULT_PROF;
87 module_param_named(prof_sel, prof_sel, uint, 0444);
88 MODULE_PARM_DESC(prof_sel, "profile selector. Valid range 0 - 2");
89
90 static u32 sw_owner_id[4];
91 #define MAX_SW_VHCA_ID (BIT(__mlx5_bit_sz(cmd_hca_cap_2, sw_vhca_id)) - 1)
92 static DEFINE_IDA(sw_vhca_ida);
93
94 enum {
95 MLX5_ATOMIC_REQ_MODE_BE = 0x0,
96 MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS = 0x1,
97 };
98
99 #define LOG_MAX_SUPPORTED_QPS 0xff
100
101 static struct mlx5_profile profile[] = {
102 [0] = {
103 .mask = 0,
104 .num_cmd_caches = MLX5_NUM_COMMAND_CACHES,
105 },
106 [1] = {
107 .mask = MLX5_PROF_MASK_QP_SIZE,
108 .log_max_qp = 12,
109 .num_cmd_caches = MLX5_NUM_COMMAND_CACHES,
110
111 },
112 [2] = {
113 .mask = MLX5_PROF_MASK_QP_SIZE |
114 MLX5_PROF_MASK_MR_CACHE,
115 .log_max_qp = LOG_MAX_SUPPORTED_QPS,
116 .num_cmd_caches = MLX5_NUM_COMMAND_CACHES,
117 .mr_cache[0] = {
118 .size = 500,
119 .limit = 250
120 },
121 .mr_cache[1] = {
122 .size = 500,
123 .limit = 250
124 },
125 .mr_cache[2] = {
126 .size = 500,
127 .limit = 250
128 },
129 .mr_cache[3] = {
130 .size = 500,
131 .limit = 250
132 },
133 .mr_cache[4] = {
134 .size = 500,
135 .limit = 250
136 },
137 .mr_cache[5] = {
138 .size = 500,
139 .limit = 250
140 },
141 .mr_cache[6] = {
142 .size = 500,
143 .limit = 250
144 },
145 .mr_cache[7] = {
146 .size = 500,
147 .limit = 250
148 },
149 .mr_cache[8] = {
150 .size = 500,
151 .limit = 250
152 },
153 .mr_cache[9] = {
154 .size = 500,
155 .limit = 250
156 },
157 .mr_cache[10] = {
158 .size = 500,
159 .limit = 250
160 },
161 .mr_cache[11] = {
162 .size = 500,
163 .limit = 250
164 },
165 .mr_cache[12] = {
166 .size = 64,
167 .limit = 32
168 },
169 .mr_cache[13] = {
170 .size = 32,
171 .limit = 16
172 },
173 .mr_cache[14] = {
174 .size = 16,
175 .limit = 8
176 },
177 .mr_cache[15] = {
178 .size = 8,
179 .limit = 4
180 },
181 },
182 [3] = {
183 .mask = MLX5_PROF_MASK_QP_SIZE,
184 .log_max_qp = LOG_MAX_SUPPORTED_QPS,
185 .num_cmd_caches = 0,
186 },
187 };
188
wait_fw_init(struct mlx5_core_dev * dev,u32 max_wait_mili,u32 warn_time_mili,const char * init_state)189 static int wait_fw_init(struct mlx5_core_dev *dev, u32 max_wait_mili,
190 u32 warn_time_mili, const char *init_state)
191 {
192 unsigned long warn = jiffies + msecs_to_jiffies(warn_time_mili);
193 unsigned long end = jiffies + msecs_to_jiffies(max_wait_mili);
194 u32 fw_initializing;
195
196 do {
197 fw_initializing = ioread32be(&dev->iseg->initializing);
198 if (!(fw_initializing >> 31))
199 break;
200 if (time_after(jiffies, end)) {
201 mlx5_core_err(dev, "Firmware over %u MS in %s state, aborting\n",
202 max_wait_mili, init_state);
203 return -ETIMEDOUT;
204 }
205 if (test_bit(MLX5_BREAK_FW_WAIT, &dev->intf_state)) {
206 mlx5_core_warn(dev, "device is being removed, stop waiting for FW %s\n",
207 init_state);
208 return -ENODEV;
209 }
210 if (warn_time_mili && time_after(jiffies, warn)) {
211 mlx5_core_warn(dev, "Waiting for FW %s, timeout abort in %ds (0x%x)\n",
212 init_state, jiffies_to_msecs(end - warn) / 1000,
213 fw_initializing);
214 warn = jiffies + msecs_to_jiffies(warn_time_mili);
215 }
216 msleep(mlx5_tout_ms(dev, FW_PRE_INIT_WAIT));
217 } while (true);
218
219 return 0;
220 }
221
mlx5_set_driver_version(struct mlx5_core_dev * dev)222 static void mlx5_set_driver_version(struct mlx5_core_dev *dev)
223 {
224 int driver_ver_sz = MLX5_FLD_SZ_BYTES(set_driver_version_in,
225 driver_version);
226 u8 in[MLX5_ST_SZ_BYTES(set_driver_version_in)] = {};
227 char *string;
228
229 if (!MLX5_CAP_GEN(dev, driver_version))
230 return;
231
232 string = MLX5_ADDR_OF(set_driver_version_in, in, driver_version);
233
234 snprintf(string, driver_ver_sz, "Linux,%s,%u.%u.%u",
235 KBUILD_MODNAME, LINUX_VERSION_MAJOR,
236 LINUX_VERSION_PATCHLEVEL, LINUX_VERSION_SUBLEVEL);
237
238 /*Send the command*/
239 MLX5_SET(set_driver_version_in, in, opcode,
240 MLX5_CMD_OP_SET_DRIVER_VERSION);
241
242 mlx5_cmd_exec_in(dev, set_driver_version, in);
243 }
244
set_dma_caps(struct pci_dev * pdev)245 static int set_dma_caps(struct pci_dev *pdev)
246 {
247 int err;
248
249 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
250 if (err) {
251 dev_warn(&pdev->dev, "Warning: couldn't set 64-bit PCI DMA mask\n");
252 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
253 if (err) {
254 dev_err(&pdev->dev, "Can't set PCI DMA mask, aborting\n");
255 return err;
256 }
257 }
258
259 dma_set_max_seg_size(&pdev->dev, 2u * 1024 * 1024 * 1024);
260 return err;
261 }
262
mlx5_pci_enable_device(struct mlx5_core_dev * dev)263 static int mlx5_pci_enable_device(struct mlx5_core_dev *dev)
264 {
265 struct pci_dev *pdev = dev->pdev;
266 int err = 0;
267
268 mutex_lock(&dev->pci_status_mutex);
269 if (dev->pci_status == MLX5_PCI_STATUS_DISABLED) {
270 err = pci_enable_device(pdev);
271 if (!err)
272 dev->pci_status = MLX5_PCI_STATUS_ENABLED;
273 }
274 mutex_unlock(&dev->pci_status_mutex);
275
276 return err;
277 }
278
mlx5_pci_disable_device(struct mlx5_core_dev * dev)279 static void mlx5_pci_disable_device(struct mlx5_core_dev *dev)
280 {
281 struct pci_dev *pdev = dev->pdev;
282
283 mutex_lock(&dev->pci_status_mutex);
284 if (dev->pci_status == MLX5_PCI_STATUS_ENABLED) {
285 pci_disable_device(pdev);
286 dev->pci_status = MLX5_PCI_STATUS_DISABLED;
287 }
288 mutex_unlock(&dev->pci_status_mutex);
289 }
290
request_bar(struct pci_dev * pdev)291 static int request_bar(struct pci_dev *pdev)
292 {
293 int err = 0;
294
295 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
296 dev_err(&pdev->dev, "Missing registers BAR, aborting\n");
297 return -ENODEV;
298 }
299
300 err = pci_request_regions(pdev, KBUILD_MODNAME);
301 if (err)
302 dev_err(&pdev->dev, "Couldn't get PCI resources, aborting\n");
303
304 return err;
305 }
306
release_bar(struct pci_dev * pdev)307 static void release_bar(struct pci_dev *pdev)
308 {
309 pci_release_regions(pdev);
310 }
311
312 struct mlx5_reg_host_endianness {
313 u8 he;
314 u8 rsvd[15];
315 };
316
to_fw_pkey_sz(struct mlx5_core_dev * dev,u32 size)317 static u16 to_fw_pkey_sz(struct mlx5_core_dev *dev, u32 size)
318 {
319 switch (size) {
320 case 128:
321 return 0;
322 case 256:
323 return 1;
324 case 512:
325 return 2;
326 case 1024:
327 return 3;
328 case 2048:
329 return 4;
330 case 4096:
331 return 5;
332 default:
333 mlx5_core_warn(dev, "invalid pkey table size %d\n", size);
334 return 0;
335 }
336 }
337
mlx5_core_uplink_netdev_set(struct mlx5_core_dev * dev,struct net_device * netdev)338 void mlx5_core_uplink_netdev_set(struct mlx5_core_dev *dev, struct net_device *netdev)
339 {
340 mutex_lock(&dev->mlx5e_res.uplink_netdev_lock);
341 dev->mlx5e_res.uplink_netdev = netdev;
342 mlx5_blocking_notifier_call_chain(dev, MLX5_DRIVER_EVENT_UPLINK_NETDEV,
343 netdev);
344 mutex_unlock(&dev->mlx5e_res.uplink_netdev_lock);
345 }
346
mlx5_core_uplink_netdev_event_replay(struct mlx5_core_dev * dev)347 void mlx5_core_uplink_netdev_event_replay(struct mlx5_core_dev *dev)
348 {
349 mutex_lock(&dev->mlx5e_res.uplink_netdev_lock);
350 mlx5_blocking_notifier_call_chain(dev, MLX5_DRIVER_EVENT_UPLINK_NETDEV,
351 dev->mlx5e_res.uplink_netdev);
352 mutex_unlock(&dev->mlx5e_res.uplink_netdev_lock);
353 }
354 EXPORT_SYMBOL(mlx5_core_uplink_netdev_event_replay);
355
mlx5_core_mp_event_replay(struct mlx5_core_dev * dev,u32 event,void * data)356 void mlx5_core_mp_event_replay(struct mlx5_core_dev *dev, u32 event, void *data)
357 {
358 mlx5_blocking_notifier_call_chain(dev, event, data);
359 }
360 EXPORT_SYMBOL(mlx5_core_mp_event_replay);
361
mlx5_core_get_caps_mode(struct mlx5_core_dev * dev,enum mlx5_cap_type cap_type,enum mlx5_cap_mode cap_mode)362 int mlx5_core_get_caps_mode(struct mlx5_core_dev *dev, enum mlx5_cap_type cap_type,
363 enum mlx5_cap_mode cap_mode)
364 {
365 u8 in[MLX5_ST_SZ_BYTES(query_hca_cap_in)];
366 int out_sz = MLX5_ST_SZ_BYTES(query_hca_cap_out);
367 void *out, *hca_caps;
368 u16 opmod = (cap_type << 1) | (cap_mode & 0x01);
369 int err;
370
371 memset(in, 0, sizeof(in));
372 out = kzalloc(out_sz, GFP_KERNEL);
373 if (!out)
374 return -ENOMEM;
375
376 MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP);
377 MLX5_SET(query_hca_cap_in, in, op_mod, opmod);
378 err = mlx5_cmd_exec_inout(dev, query_hca_cap, in, out);
379 if (err) {
380 mlx5_core_warn(dev,
381 "QUERY_HCA_CAP : type(%x) opmode(%x) Failed(%d)\n",
382 cap_type, cap_mode, err);
383 goto query_ex;
384 }
385
386 hca_caps = MLX5_ADDR_OF(query_hca_cap_out, out, capability);
387
388 switch (cap_mode) {
389 case HCA_CAP_OPMOD_GET_MAX:
390 memcpy(dev->caps.hca[cap_type]->max, hca_caps,
391 MLX5_UN_SZ_BYTES(hca_cap_union));
392 break;
393 case HCA_CAP_OPMOD_GET_CUR:
394 memcpy(dev->caps.hca[cap_type]->cur, hca_caps,
395 MLX5_UN_SZ_BYTES(hca_cap_union));
396 break;
397 default:
398 mlx5_core_warn(dev,
399 "Tried to query dev cap type(%x) with wrong opmode(%x)\n",
400 cap_type, cap_mode);
401 err = -EINVAL;
402 break;
403 }
404 query_ex:
405 kfree(out);
406 return err;
407 }
408
mlx5_core_get_caps(struct mlx5_core_dev * dev,enum mlx5_cap_type cap_type)409 int mlx5_core_get_caps(struct mlx5_core_dev *dev, enum mlx5_cap_type cap_type)
410 {
411 int ret;
412
413 ret = mlx5_core_get_caps_mode(dev, cap_type, HCA_CAP_OPMOD_GET_CUR);
414 if (ret)
415 return ret;
416 return mlx5_core_get_caps_mode(dev, cap_type, HCA_CAP_OPMOD_GET_MAX);
417 }
418
set_caps(struct mlx5_core_dev * dev,void * in,int opmod)419 static int set_caps(struct mlx5_core_dev *dev, void *in, int opmod)
420 {
421 MLX5_SET(set_hca_cap_in, in, opcode, MLX5_CMD_OP_SET_HCA_CAP);
422 MLX5_SET(set_hca_cap_in, in, op_mod, opmod << 1);
423 return mlx5_cmd_exec_in(dev, set_hca_cap, in);
424 }
425
handle_hca_cap_atomic(struct mlx5_core_dev * dev,void * set_ctx)426 static int handle_hca_cap_atomic(struct mlx5_core_dev *dev, void *set_ctx)
427 {
428 void *set_hca_cap;
429 int req_endianness;
430 int err;
431
432 if (!MLX5_CAP_GEN(dev, atomic))
433 return 0;
434
435 err = mlx5_core_get_caps(dev, MLX5_CAP_ATOMIC);
436 if (err)
437 return err;
438
439 req_endianness =
440 MLX5_CAP_ATOMIC(dev,
441 supported_atomic_req_8B_endianness_mode_1);
442
443 if (req_endianness != MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS)
444 return 0;
445
446 set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, capability);
447
448 /* Set requestor to host endianness */
449 MLX5_SET(atomic_caps, set_hca_cap, atomic_req_8B_endianness_mode,
450 MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS);
451
452 return set_caps(dev, set_ctx, MLX5_SET_HCA_CAP_OP_MOD_ATOMIC);
453 }
454
handle_hca_cap_odp(struct mlx5_core_dev * dev,void * set_ctx)455 static int handle_hca_cap_odp(struct mlx5_core_dev *dev, void *set_ctx)
456 {
457 bool do_set = false, mem_page_fault = false;
458 void *set_hca_cap;
459 int err;
460
461 if (!IS_ENABLED(CONFIG_INFINIBAND_ON_DEMAND_PAGING) ||
462 !MLX5_CAP_GEN(dev, pg))
463 return 0;
464
465 err = mlx5_core_get_caps(dev, MLX5_CAP_ODP);
466 if (err)
467 return err;
468
469 set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, capability);
470 memcpy(set_hca_cap, dev->caps.hca[MLX5_CAP_ODP]->cur,
471 MLX5_ST_SZ_BYTES(odp_cap));
472
473 /* For best performance, enable memory scheme ODP only when
474 * it has page prefetch enabled.
475 */
476 if (MLX5_CAP_ODP_MAX(dev, mem_page_fault) &&
477 MLX5_CAP_ODP_MAX(dev, memory_page_fault_scheme_cap.page_prefetch)) {
478 mem_page_fault = true;
479 do_set = true;
480 MLX5_SET(odp_cap, set_hca_cap, mem_page_fault, mem_page_fault);
481 goto set;
482 }
483
484 #define ODP_CAP_SET_MAX(dev, field) \
485 do { \
486 u32 _res = MLX5_CAP_ODP_MAX(dev, field); \
487 if (_res) { \
488 do_set = true; \
489 MLX5_SET(odp_cap, set_hca_cap, field, _res); \
490 } \
491 } while (0)
492
493 ODP_CAP_SET_MAX(dev, transport_page_fault_scheme_cap.ud_odp_caps.srq_receive);
494 ODP_CAP_SET_MAX(dev, transport_page_fault_scheme_cap.rc_odp_caps.srq_receive);
495 ODP_CAP_SET_MAX(dev, transport_page_fault_scheme_cap.xrc_odp_caps.srq_receive);
496 ODP_CAP_SET_MAX(dev, transport_page_fault_scheme_cap.xrc_odp_caps.send);
497 ODP_CAP_SET_MAX(dev, transport_page_fault_scheme_cap.xrc_odp_caps.receive);
498 ODP_CAP_SET_MAX(dev, transport_page_fault_scheme_cap.xrc_odp_caps.write);
499 ODP_CAP_SET_MAX(dev, transport_page_fault_scheme_cap.xrc_odp_caps.read);
500 ODP_CAP_SET_MAX(dev, transport_page_fault_scheme_cap.xrc_odp_caps.atomic);
501 ODP_CAP_SET_MAX(dev, transport_page_fault_scheme_cap.dc_odp_caps.srq_receive);
502 ODP_CAP_SET_MAX(dev, transport_page_fault_scheme_cap.dc_odp_caps.send);
503 ODP_CAP_SET_MAX(dev, transport_page_fault_scheme_cap.dc_odp_caps.receive);
504 ODP_CAP_SET_MAX(dev, transport_page_fault_scheme_cap.dc_odp_caps.write);
505 ODP_CAP_SET_MAX(dev, transport_page_fault_scheme_cap.dc_odp_caps.read);
506 ODP_CAP_SET_MAX(dev, transport_page_fault_scheme_cap.dc_odp_caps.atomic);
507
508 set:
509 if (do_set)
510 err = set_caps(dev, set_ctx, MLX5_SET_HCA_CAP_OP_MOD_ODP);
511
512 mlx5_core_dbg(dev, "Using ODP %s scheme\n",
513 mem_page_fault ? "memory" : "transport");
514 return err;
515 }
516
max_uc_list_get_devlink_param(struct mlx5_core_dev * dev)517 static int max_uc_list_get_devlink_param(struct mlx5_core_dev *dev)
518 {
519 struct devlink *devlink = priv_to_devlink(dev);
520 union devlink_param_value val;
521 int err;
522
523 err = devl_param_driverinit_value_get(devlink,
524 DEVLINK_PARAM_GENERIC_ID_MAX_MACS,
525 &val);
526 if (!err)
527 return val.vu32;
528 mlx5_core_dbg(dev, "Failed to get param. err = %d\n", err);
529 return err;
530 }
531
mlx5_is_roce_on(struct mlx5_core_dev * dev)532 bool mlx5_is_roce_on(struct mlx5_core_dev *dev)
533 {
534 struct devlink *devlink = priv_to_devlink(dev);
535 union devlink_param_value val;
536 int err;
537
538 err = devl_param_driverinit_value_get(devlink,
539 DEVLINK_PARAM_GENERIC_ID_ENABLE_ROCE,
540 &val);
541
542 if (!err)
543 return val.vbool;
544
545 mlx5_core_dbg(dev, "Failed to get param. err = %d\n", err);
546 return MLX5_CAP_GEN(dev, roce);
547 }
548 EXPORT_SYMBOL(mlx5_is_roce_on);
549
handle_hca_cap_2(struct mlx5_core_dev * dev,void * set_ctx)550 static int handle_hca_cap_2(struct mlx5_core_dev *dev, void *set_ctx)
551 {
552 void *set_hca_cap;
553 int err;
554
555 if (!MLX5_CAP_GEN_MAX(dev, hca_cap_2))
556 return 0;
557
558 err = mlx5_core_get_caps(dev, MLX5_CAP_GENERAL_2);
559 if (err)
560 return err;
561
562 if (!MLX5_CAP_GEN_2_MAX(dev, sw_vhca_id_valid) ||
563 !(dev->priv.sw_vhca_id > 0))
564 return 0;
565
566 set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx,
567 capability);
568 memcpy(set_hca_cap, dev->caps.hca[MLX5_CAP_GENERAL_2]->cur,
569 MLX5_ST_SZ_BYTES(cmd_hca_cap_2));
570 MLX5_SET(cmd_hca_cap_2, set_hca_cap, sw_vhca_id_valid, 1);
571
572 return set_caps(dev, set_ctx, MLX5_CAP_GENERAL_2);
573 }
574
handle_hca_cap(struct mlx5_core_dev * dev,void * set_ctx)575 static int handle_hca_cap(struct mlx5_core_dev *dev, void *set_ctx)
576 {
577 struct mlx5_profile *prof = &dev->profile;
578 void *set_hca_cap;
579 int max_uc_list;
580 int err;
581
582 err = mlx5_core_get_caps(dev, MLX5_CAP_GENERAL);
583 if (err)
584 return err;
585
586 set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx,
587 capability);
588 memcpy(set_hca_cap, dev->caps.hca[MLX5_CAP_GENERAL]->cur,
589 MLX5_ST_SZ_BYTES(cmd_hca_cap));
590
591 mlx5_core_dbg(dev, "Current Pkey table size %d Setting new size %d\n",
592 mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(dev, pkey_table_size)),
593 128);
594 /* we limit the size of the pkey table to 128 entries for now */
595 MLX5_SET(cmd_hca_cap, set_hca_cap, pkey_table_size,
596 to_fw_pkey_sz(dev, 128));
597
598 /* Check log_max_qp from HCA caps to set in current profile */
599 if (prof->log_max_qp == LOG_MAX_SUPPORTED_QPS) {
600 prof->log_max_qp = min_t(u8, 18, MLX5_CAP_GEN_MAX(dev, log_max_qp));
601 } else if (MLX5_CAP_GEN_MAX(dev, log_max_qp) < prof->log_max_qp) {
602 mlx5_core_warn(dev, "log_max_qp value in current profile is %d, changing it to HCA capability limit (%d)\n",
603 prof->log_max_qp,
604 MLX5_CAP_GEN_MAX(dev, log_max_qp));
605 prof->log_max_qp = MLX5_CAP_GEN_MAX(dev, log_max_qp);
606 }
607 if (prof->mask & MLX5_PROF_MASK_QP_SIZE)
608 MLX5_SET(cmd_hca_cap, set_hca_cap, log_max_qp,
609 prof->log_max_qp);
610
611 /* disable cmdif checksum */
612 MLX5_SET(cmd_hca_cap, set_hca_cap, cmdif_checksum, 0);
613
614 /* Enable 4K UAR only when HCA supports it and page size is bigger
615 * than 4K.
616 */
617 if (MLX5_CAP_GEN_MAX(dev, uar_4k) && PAGE_SIZE > 4096)
618 MLX5_SET(cmd_hca_cap, set_hca_cap, uar_4k, 1);
619
620 MLX5_SET(cmd_hca_cap, set_hca_cap, log_uar_page_sz, PAGE_SHIFT - 12);
621
622 if (MLX5_CAP_GEN_MAX(dev, cache_line_128byte))
623 MLX5_SET(cmd_hca_cap,
624 set_hca_cap,
625 cache_line_128byte,
626 cache_line_size() >= 128 ? 1 : 0);
627
628 if (MLX5_CAP_GEN_MAX(dev, dct))
629 MLX5_SET(cmd_hca_cap, set_hca_cap, dct, 1);
630
631 if (MLX5_CAP_GEN_MAX(dev, pci_sync_for_fw_update_event))
632 MLX5_SET(cmd_hca_cap, set_hca_cap, pci_sync_for_fw_update_event, 1);
633 if (MLX5_CAP_GEN_MAX(dev, pci_sync_for_fw_update_with_driver_unload))
634 MLX5_SET(cmd_hca_cap, set_hca_cap,
635 pci_sync_for_fw_update_with_driver_unload, 1);
636 if (MLX5_CAP_GEN_MAX(dev, pcie_reset_using_hotreset_method))
637 MLX5_SET(cmd_hca_cap, set_hca_cap,
638 pcie_reset_using_hotreset_method, 1);
639
640 if (MLX5_CAP_GEN_MAX(dev, num_vhca_ports))
641 MLX5_SET(cmd_hca_cap,
642 set_hca_cap,
643 num_vhca_ports,
644 MLX5_CAP_GEN_MAX(dev, num_vhca_ports));
645
646 if (MLX5_CAP_GEN_MAX(dev, release_all_pages))
647 MLX5_SET(cmd_hca_cap, set_hca_cap, release_all_pages, 1);
648
649 if (MLX5_CAP_GEN_MAX(dev, mkey_by_name))
650 MLX5_SET(cmd_hca_cap, set_hca_cap, mkey_by_name, 1);
651
652 mlx5_vhca_state_cap_handle(dev, set_hca_cap);
653
654 if (MLX5_CAP_GEN_MAX(dev, num_total_dynamic_vf_msix))
655 MLX5_SET(cmd_hca_cap, set_hca_cap, num_total_dynamic_vf_msix,
656 MLX5_CAP_GEN_MAX(dev, num_total_dynamic_vf_msix));
657
658 if (MLX5_CAP_GEN(dev, roce_rw_supported) && MLX5_CAP_GEN_MAX(dev, roce))
659 MLX5_SET(cmd_hca_cap, set_hca_cap, roce,
660 mlx5_is_roce_on(dev));
661
662 max_uc_list = max_uc_list_get_devlink_param(dev);
663 if (max_uc_list > 0)
664 MLX5_SET(cmd_hca_cap, set_hca_cap, log_max_current_uc_list,
665 ilog2(max_uc_list));
666
667 return set_caps(dev, set_ctx, MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE);
668 }
669
670 /* Cached MLX5_CAP_GEN(dev, roce) can be out of sync this early in the
671 * boot process.
672 * In case RoCE cap is writable in FW and user/devlink requested to change the
673 * cap, we are yet to query the final state of the above cap.
674 * Hence, the need for this function.
675 *
676 * Returns
677 * True:
678 * 1) RoCE cap is read only in FW and already disabled
679 * OR:
680 * 2) RoCE cap is writable in FW and user/devlink requested it off.
681 *
682 * In any other case, return False.
683 */
is_roce_fw_disabled(struct mlx5_core_dev * dev)684 static bool is_roce_fw_disabled(struct mlx5_core_dev *dev)
685 {
686 return (MLX5_CAP_GEN(dev, roce_rw_supported) && !mlx5_is_roce_on(dev)) ||
687 (!MLX5_CAP_GEN(dev, roce_rw_supported) && !MLX5_CAP_GEN(dev, roce));
688 }
689
handle_hca_cap_roce(struct mlx5_core_dev * dev,void * set_ctx)690 static int handle_hca_cap_roce(struct mlx5_core_dev *dev, void *set_ctx)
691 {
692 void *set_hca_cap;
693 int err;
694
695 if (is_roce_fw_disabled(dev))
696 return 0;
697
698 err = mlx5_core_get_caps(dev, MLX5_CAP_ROCE);
699 if (err)
700 return err;
701
702 if (MLX5_CAP_ROCE(dev, sw_r_roce_src_udp_port) ||
703 !MLX5_CAP_ROCE_MAX(dev, sw_r_roce_src_udp_port))
704 return 0;
705
706 set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, capability);
707 memcpy(set_hca_cap, dev->caps.hca[MLX5_CAP_ROCE]->cur,
708 MLX5_ST_SZ_BYTES(roce_cap));
709 MLX5_SET(roce_cap, set_hca_cap, sw_r_roce_src_udp_port, 1);
710
711 if (MLX5_CAP_ROCE_MAX(dev, qp_ooo_transmit_default))
712 MLX5_SET(roce_cap, set_hca_cap, qp_ooo_transmit_default, 1);
713
714 err = set_caps(dev, set_ctx, MLX5_SET_HCA_CAP_OP_MOD_ROCE);
715 return err;
716 }
717
handle_hca_cap_port_selection(struct mlx5_core_dev * dev,void * set_ctx)718 static int handle_hca_cap_port_selection(struct mlx5_core_dev *dev,
719 void *set_ctx)
720 {
721 void *set_hca_cap;
722 int err;
723
724 if (!MLX5_CAP_GEN(dev, port_selection_cap))
725 return 0;
726
727 err = mlx5_core_get_caps(dev, MLX5_CAP_PORT_SELECTION);
728 if (err)
729 return err;
730
731 if (MLX5_CAP_PORT_SELECTION(dev, port_select_flow_table_bypass) ||
732 !MLX5_CAP_PORT_SELECTION_MAX(dev, port_select_flow_table_bypass))
733 return 0;
734
735 set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, capability);
736 memcpy(set_hca_cap, dev->caps.hca[MLX5_CAP_PORT_SELECTION]->cur,
737 MLX5_ST_SZ_BYTES(port_selection_cap));
738 MLX5_SET(port_selection_cap, set_hca_cap, port_select_flow_table_bypass, 1);
739
740 err = set_caps(dev, set_ctx, MLX5_SET_HCA_CAP_OP_MOD_PORT_SELECTION);
741
742 return err;
743 }
744
set_hca_cap(struct mlx5_core_dev * dev)745 static int set_hca_cap(struct mlx5_core_dev *dev)
746 {
747 int set_sz = MLX5_ST_SZ_BYTES(set_hca_cap_in);
748 void *set_ctx;
749 int err;
750
751 set_ctx = kzalloc(set_sz, GFP_KERNEL);
752 if (!set_ctx)
753 return -ENOMEM;
754
755 err = handle_hca_cap(dev, set_ctx);
756 if (err) {
757 mlx5_core_err(dev, "handle_hca_cap failed\n");
758 goto out;
759 }
760
761 memset(set_ctx, 0, set_sz);
762 err = handle_hca_cap_atomic(dev, set_ctx);
763 if (err) {
764 mlx5_core_err(dev, "handle_hca_cap_atomic failed\n");
765 goto out;
766 }
767
768 memset(set_ctx, 0, set_sz);
769 err = handle_hca_cap_odp(dev, set_ctx);
770 if (err) {
771 mlx5_core_err(dev, "handle_hca_cap_odp failed\n");
772 goto out;
773 }
774
775 memset(set_ctx, 0, set_sz);
776 err = handle_hca_cap_roce(dev, set_ctx);
777 if (err) {
778 mlx5_core_err(dev, "handle_hca_cap_roce failed\n");
779 goto out;
780 }
781
782 memset(set_ctx, 0, set_sz);
783 err = handle_hca_cap_2(dev, set_ctx);
784 if (err) {
785 mlx5_core_err(dev, "handle_hca_cap_2 failed\n");
786 goto out;
787 }
788
789 memset(set_ctx, 0, set_sz);
790 err = handle_hca_cap_port_selection(dev, set_ctx);
791 if (err) {
792 mlx5_core_err(dev, "handle_hca_cap_port_selection failed\n");
793 goto out;
794 }
795
796 out:
797 kfree(set_ctx);
798 return err;
799 }
800
set_hca_ctrl(struct mlx5_core_dev * dev)801 static int set_hca_ctrl(struct mlx5_core_dev *dev)
802 {
803 struct mlx5_reg_host_endianness he_in;
804 struct mlx5_reg_host_endianness he_out;
805 int err;
806
807 if (!mlx5_core_is_pf(dev))
808 return 0;
809
810 memset(&he_in, 0, sizeof(he_in));
811 he_in.he = MLX5_SET_HOST_ENDIANNESS;
812 err = mlx5_core_access_reg(dev, &he_in, sizeof(he_in),
813 &he_out, sizeof(he_out),
814 MLX5_REG_HOST_ENDIANNESS, 0, 1);
815 return err;
816 }
817
mlx5_core_set_hca_defaults(struct mlx5_core_dev * dev)818 static int mlx5_core_set_hca_defaults(struct mlx5_core_dev *dev)
819 {
820 int ret = 0;
821
822 /* Disable local_lb by default */
823 if (MLX5_CAP_GEN(dev, port_type) == MLX5_CAP_PORT_TYPE_ETH)
824 ret = mlx5_nic_vport_update_local_lb(dev, false);
825
826 return ret;
827 }
828
mlx5_core_enable_hca(struct mlx5_core_dev * dev,u16 func_id)829 int mlx5_core_enable_hca(struct mlx5_core_dev *dev, u16 func_id)
830 {
831 u32 in[MLX5_ST_SZ_DW(enable_hca_in)] = {};
832
833 MLX5_SET(enable_hca_in, in, opcode, MLX5_CMD_OP_ENABLE_HCA);
834 MLX5_SET(enable_hca_in, in, function_id, func_id);
835 MLX5_SET(enable_hca_in, in, embedded_cpu_function,
836 dev->caps.embedded_cpu);
837 return mlx5_cmd_exec_in(dev, enable_hca, in);
838 }
839
mlx5_core_disable_hca(struct mlx5_core_dev * dev,u16 func_id)840 int mlx5_core_disable_hca(struct mlx5_core_dev *dev, u16 func_id)
841 {
842 u32 in[MLX5_ST_SZ_DW(disable_hca_in)] = {};
843
844 MLX5_SET(disable_hca_in, in, opcode, MLX5_CMD_OP_DISABLE_HCA);
845 MLX5_SET(disable_hca_in, in, function_id, func_id);
846 MLX5_SET(enable_hca_in, in, embedded_cpu_function,
847 dev->caps.embedded_cpu);
848 return mlx5_cmd_exec_in(dev, disable_hca, in);
849 }
850
mlx5_core_set_issi(struct mlx5_core_dev * dev)851 static int mlx5_core_set_issi(struct mlx5_core_dev *dev)
852 {
853 u32 query_out[MLX5_ST_SZ_DW(query_issi_out)] = {};
854 u32 query_in[MLX5_ST_SZ_DW(query_issi_in)] = {};
855 u32 sup_issi;
856 int err;
857
858 MLX5_SET(query_issi_in, query_in, opcode, MLX5_CMD_OP_QUERY_ISSI);
859 err = mlx5_cmd_exec_inout(dev, query_issi, query_in, query_out);
860 if (err) {
861 u32 syndrome = MLX5_GET(query_issi_out, query_out, syndrome);
862 u8 status = MLX5_GET(query_issi_out, query_out, status);
863
864 if (!status || syndrome == MLX5_DRIVER_SYND) {
865 mlx5_core_err(dev, "Failed to query ISSI err(%d) status(%d) synd(%d)\n",
866 err, status, syndrome);
867 return err;
868 }
869
870 mlx5_core_warn(dev, "Query ISSI is not supported by FW, ISSI is 0\n");
871 dev->issi = 0;
872 return 0;
873 }
874
875 sup_issi = MLX5_GET(query_issi_out, query_out, supported_issi_dw0);
876
877 if (sup_issi & (1 << 1)) {
878 u32 set_in[MLX5_ST_SZ_DW(set_issi_in)] = {};
879
880 MLX5_SET(set_issi_in, set_in, opcode, MLX5_CMD_OP_SET_ISSI);
881 MLX5_SET(set_issi_in, set_in, current_issi, 1);
882 err = mlx5_cmd_exec_in(dev, set_issi, set_in);
883 if (err) {
884 mlx5_core_err(dev, "Failed to set ISSI to 1 err(%d)\n",
885 err);
886 return err;
887 }
888
889 dev->issi = 1;
890
891 return 0;
892 } else if (sup_issi & (1 << 0) || !sup_issi) {
893 return 0;
894 }
895
896 return -EOPNOTSUPP;
897 }
898
mlx5_pci_init(struct mlx5_core_dev * dev,struct pci_dev * pdev,const struct pci_device_id * id)899 static int mlx5_pci_init(struct mlx5_core_dev *dev, struct pci_dev *pdev,
900 const struct pci_device_id *id)
901 {
902 int err = 0;
903
904 mutex_init(&dev->pci_status_mutex);
905 pci_set_drvdata(dev->pdev, dev);
906
907 dev->bar_addr = pci_resource_start(pdev, 0);
908
909 err = mlx5_pci_enable_device(dev);
910 if (err) {
911 mlx5_core_err(dev, "Cannot enable PCI device, aborting\n");
912 return err;
913 }
914
915 err = request_bar(pdev);
916 if (err) {
917 mlx5_core_err(dev, "error requesting BARs, aborting\n");
918 goto err_disable;
919 }
920
921 pci_set_master(pdev);
922
923 err = set_dma_caps(pdev);
924 if (err) {
925 mlx5_core_err(dev, "Failed setting DMA capabilities mask, aborting\n");
926 goto err_clr_master;
927 }
928
929 if (pci_enable_atomic_ops_to_root(pdev, PCI_EXP_DEVCAP2_ATOMIC_COMP32) &&
930 pci_enable_atomic_ops_to_root(pdev, PCI_EXP_DEVCAP2_ATOMIC_COMP64) &&
931 pci_enable_atomic_ops_to_root(pdev, PCI_EXP_DEVCAP2_ATOMIC_COMP128))
932 mlx5_core_dbg(dev, "Enabling pci atomics failed\n");
933
934 dev->iseg_base = dev->bar_addr;
935 dev->iseg = ioremap(dev->iseg_base, sizeof(*dev->iseg));
936 if (!dev->iseg) {
937 err = -ENOMEM;
938 mlx5_core_err(dev, "Failed mapping initialization segment, aborting\n");
939 goto err_clr_master;
940 }
941
942 mlx5_pci_vsc_init(dev);
943
944 err = pci_enable_ptm(pdev, NULL);
945 if (err)
946 mlx5_core_info(dev, "PTM is not supported by PCIe\n");
947
948 return 0;
949
950 err_clr_master:
951 release_bar(dev->pdev);
952 err_disable:
953 mlx5_pci_disable_device(dev);
954 return err;
955 }
956
mlx5_pci_close(struct mlx5_core_dev * dev)957 static void mlx5_pci_close(struct mlx5_core_dev *dev)
958 {
959 /* health work might still be active, and it needs pci bar in
960 * order to know the NIC state. Therefore, drain the health WQ
961 * before removing the pci bars
962 */
963 mlx5_drain_health_wq(dev);
964 pci_disable_ptm(dev->pdev);
965 iounmap(dev->iseg);
966 release_bar(dev->pdev);
967 mlx5_pci_disable_device(dev);
968 }
969
mlx5_register_hca_devcom_comp(struct mlx5_core_dev * dev)970 static void mlx5_register_hca_devcom_comp(struct mlx5_core_dev *dev)
971 {
972 /* This component is use to sync adding core_dev to lag_dev and to sync
973 * changes of mlx5_adev_devices between LAG layer and other layers.
974 */
975 if (!mlx5_lag_is_supported(dev))
976 return;
977
978 dev->priv.hca_devcom_comp =
979 mlx5_devcom_register_component(dev->priv.devc, MLX5_DEVCOM_HCA_PORTS,
980 mlx5_query_nic_system_image_guid(dev),
981 NULL, dev);
982 if (IS_ERR(dev->priv.hca_devcom_comp))
983 mlx5_core_err(dev, "Failed to register devcom HCA component\n");
984 }
985
mlx5_unregister_hca_devcom_comp(struct mlx5_core_dev * dev)986 static void mlx5_unregister_hca_devcom_comp(struct mlx5_core_dev *dev)
987 {
988 mlx5_devcom_unregister_component(dev->priv.hca_devcom_comp);
989 }
990
mlx5_init_once(struct mlx5_core_dev * dev)991 static int mlx5_init_once(struct mlx5_core_dev *dev)
992 {
993 int err;
994
995 dev->priv.devc = mlx5_devcom_register_device(dev);
996 if (IS_ERR(dev->priv.devc))
997 mlx5_core_warn(dev, "failed to register devcom device %ld\n",
998 PTR_ERR(dev->priv.devc));
999 mlx5_register_hca_devcom_comp(dev);
1000
1001 err = mlx5_query_board_id(dev);
1002 if (err) {
1003 mlx5_core_err(dev, "query board id failed\n");
1004 goto err_devcom;
1005 }
1006
1007 err = mlx5_irq_table_init(dev);
1008 if (err) {
1009 mlx5_core_err(dev, "failed to initialize irq table\n");
1010 goto err_devcom;
1011 }
1012
1013 err = mlx5_eq_table_init(dev);
1014 if (err) {
1015 mlx5_core_err(dev, "failed to initialize eq\n");
1016 goto err_irq_cleanup;
1017 }
1018
1019 err = mlx5_events_init(dev);
1020 if (err) {
1021 mlx5_core_err(dev, "failed to initialize events\n");
1022 goto err_eq_cleanup;
1023 }
1024
1025 err = mlx5_fw_reset_init(dev);
1026 if (err) {
1027 mlx5_core_err(dev, "failed to initialize fw reset events\n");
1028 goto err_events_cleanup;
1029 }
1030
1031 mlx5_cq_debugfs_init(dev);
1032
1033 mlx5_init_reserved_gids(dev);
1034
1035 mlx5_init_clock(dev);
1036
1037 dev->vxlan = mlx5_vxlan_create(dev);
1038 dev->geneve = mlx5_geneve_create(dev);
1039
1040 err = mlx5_init_rl_table(dev);
1041 if (err) {
1042 mlx5_core_err(dev, "Failed to init rate limiting\n");
1043 goto err_tables_cleanup;
1044 }
1045
1046 err = mlx5_mpfs_init(dev);
1047 if (err) {
1048 mlx5_core_err(dev, "Failed to init l2 table %d\n", err);
1049 goto err_rl_cleanup;
1050 }
1051
1052 err = mlx5_sriov_init(dev);
1053 if (err) {
1054 mlx5_core_err(dev, "Failed to init sriov %d\n", err);
1055 goto err_mpfs_cleanup;
1056 }
1057
1058 err = mlx5_eswitch_init(dev);
1059 if (err) {
1060 mlx5_core_err(dev, "Failed to init eswitch %d\n", err);
1061 goto err_sriov_cleanup;
1062 }
1063
1064 err = mlx5_fpga_init(dev);
1065 if (err) {
1066 mlx5_core_err(dev, "Failed to init fpga device %d\n", err);
1067 goto err_eswitch_cleanup;
1068 }
1069
1070 err = mlx5_vhca_event_init(dev);
1071 if (err) {
1072 mlx5_core_err(dev, "Failed to init vhca event notifier %d\n", err);
1073 goto err_fpga_cleanup;
1074 }
1075
1076 err = mlx5_sf_hw_table_init(dev);
1077 if (err) {
1078 mlx5_core_err(dev, "Failed to init SF HW table %d\n", err);
1079 goto err_sf_hw_table_cleanup;
1080 }
1081
1082 err = mlx5_sf_table_init(dev);
1083 if (err) {
1084 mlx5_core_err(dev, "Failed to init SF table %d\n", err);
1085 goto err_sf_table_cleanup;
1086 }
1087
1088 err = mlx5_fs_core_alloc(dev);
1089 if (err) {
1090 mlx5_core_err(dev, "Failed to alloc flow steering\n");
1091 goto err_fs;
1092 }
1093
1094 dev->dm = mlx5_dm_create(dev);
1095 dev->tracer = mlx5_fw_tracer_create(dev);
1096 dev->hv_vhca = mlx5_hv_vhca_create(dev);
1097 dev->rsc_dump = mlx5_rsc_dump_create(dev);
1098
1099 return 0;
1100
1101 err_fs:
1102 mlx5_sf_table_cleanup(dev);
1103 err_sf_table_cleanup:
1104 mlx5_sf_hw_table_cleanup(dev);
1105 err_sf_hw_table_cleanup:
1106 mlx5_vhca_event_cleanup(dev);
1107 err_fpga_cleanup:
1108 mlx5_fpga_cleanup(dev);
1109 err_eswitch_cleanup:
1110 mlx5_eswitch_cleanup(dev->priv.eswitch);
1111 err_sriov_cleanup:
1112 mlx5_sriov_cleanup(dev);
1113 err_mpfs_cleanup:
1114 mlx5_mpfs_cleanup(dev);
1115 err_rl_cleanup:
1116 mlx5_cleanup_rl_table(dev);
1117 err_tables_cleanup:
1118 mlx5_geneve_destroy(dev->geneve);
1119 mlx5_vxlan_destroy(dev->vxlan);
1120 mlx5_cleanup_clock(dev);
1121 mlx5_cleanup_reserved_gids(dev);
1122 mlx5_cq_debugfs_cleanup(dev);
1123 mlx5_fw_reset_cleanup(dev);
1124 err_events_cleanup:
1125 mlx5_events_cleanup(dev);
1126 err_eq_cleanup:
1127 mlx5_eq_table_cleanup(dev);
1128 err_irq_cleanup:
1129 mlx5_irq_table_cleanup(dev);
1130 err_devcom:
1131 mlx5_unregister_hca_devcom_comp(dev);
1132 mlx5_devcom_unregister_device(dev->priv.devc);
1133
1134 return err;
1135 }
1136
mlx5_cleanup_once(struct mlx5_core_dev * dev)1137 static void mlx5_cleanup_once(struct mlx5_core_dev *dev)
1138 {
1139 mlx5_rsc_dump_destroy(dev);
1140 mlx5_hv_vhca_destroy(dev->hv_vhca);
1141 mlx5_fw_tracer_destroy(dev->tracer);
1142 mlx5_dm_cleanup(dev);
1143 mlx5_fs_core_free(dev);
1144 mlx5_sf_table_cleanup(dev);
1145 mlx5_sf_hw_table_cleanup(dev);
1146 mlx5_vhca_event_cleanup(dev);
1147 mlx5_fpga_cleanup(dev);
1148 mlx5_eswitch_cleanup(dev->priv.eswitch);
1149 mlx5_sriov_cleanup(dev);
1150 mlx5_mpfs_cleanup(dev);
1151 mlx5_cleanup_rl_table(dev);
1152 mlx5_geneve_destroy(dev->geneve);
1153 mlx5_vxlan_destroy(dev->vxlan);
1154 mlx5_cleanup_clock(dev);
1155 mlx5_cleanup_reserved_gids(dev);
1156 mlx5_cq_debugfs_cleanup(dev);
1157 mlx5_fw_reset_cleanup(dev);
1158 mlx5_events_cleanup(dev);
1159 mlx5_eq_table_cleanup(dev);
1160 mlx5_irq_table_cleanup(dev);
1161 mlx5_unregister_hca_devcom_comp(dev);
1162 mlx5_devcom_unregister_device(dev->priv.devc);
1163 }
1164
mlx5_function_enable(struct mlx5_core_dev * dev,bool boot,u64 timeout)1165 static int mlx5_function_enable(struct mlx5_core_dev *dev, bool boot, u64 timeout)
1166 {
1167 int err;
1168
1169 mlx5_core_info(dev, "firmware version: %d.%d.%d\n", fw_rev_maj(dev),
1170 fw_rev_min(dev), fw_rev_sub(dev));
1171
1172 /* Only PFs hold the relevant PCIe information for this query */
1173 if (mlx5_core_is_pf(dev))
1174 pcie_print_link_status(dev->pdev);
1175
1176 /* wait for firmware to accept initialization segments configurations
1177 */
1178 err = wait_fw_init(dev, timeout,
1179 mlx5_tout_ms(dev, FW_PRE_INIT_WARN_MESSAGE_INTERVAL),
1180 "pre-initializing");
1181 if (err)
1182 return err;
1183
1184 err = mlx5_cmd_enable(dev);
1185 if (err) {
1186 mlx5_core_err(dev, "Failed initializing command interface, aborting\n");
1187 return err;
1188 }
1189
1190 mlx5_tout_query_iseg(dev);
1191
1192 err = wait_fw_init(dev, mlx5_tout_ms(dev, FW_INIT), 0, "initializing");
1193 if (err)
1194 goto err_cmd_cleanup;
1195
1196 dev->caps.embedded_cpu = mlx5_read_embedded_cpu(dev);
1197 mlx5_cmd_set_state(dev, MLX5_CMDIF_STATE_UP);
1198
1199 mlx5_start_health_poll(dev);
1200
1201 err = mlx5_core_enable_hca(dev, 0);
1202 if (err) {
1203 mlx5_core_err(dev, "enable hca failed\n");
1204 goto stop_health_poll;
1205 }
1206
1207 err = mlx5_core_set_issi(dev);
1208 if (err) {
1209 mlx5_core_err(dev, "failed to set issi\n");
1210 goto err_disable_hca;
1211 }
1212
1213 err = mlx5_satisfy_startup_pages(dev, 1);
1214 if (err) {
1215 mlx5_core_err(dev, "failed to allocate boot pages\n");
1216 goto err_disable_hca;
1217 }
1218
1219 err = mlx5_tout_query_dtor(dev);
1220 if (err) {
1221 mlx5_core_err(dev, "failed to read dtor\n");
1222 goto reclaim_boot_pages;
1223 }
1224
1225 return 0;
1226
1227 reclaim_boot_pages:
1228 mlx5_reclaim_startup_pages(dev);
1229 err_disable_hca:
1230 mlx5_core_disable_hca(dev, 0);
1231 stop_health_poll:
1232 mlx5_stop_health_poll(dev, boot);
1233 err_cmd_cleanup:
1234 mlx5_cmd_set_state(dev, MLX5_CMDIF_STATE_DOWN);
1235 mlx5_cmd_disable(dev);
1236
1237 return err;
1238 }
1239
mlx5_function_disable(struct mlx5_core_dev * dev,bool boot)1240 static void mlx5_function_disable(struct mlx5_core_dev *dev, bool boot)
1241 {
1242 mlx5_reclaim_startup_pages(dev);
1243 mlx5_core_disable_hca(dev, 0);
1244 mlx5_stop_health_poll(dev, boot);
1245 mlx5_cmd_set_state(dev, MLX5_CMDIF_STATE_DOWN);
1246 mlx5_cmd_disable(dev);
1247 }
1248
mlx5_function_open(struct mlx5_core_dev * dev)1249 static int mlx5_function_open(struct mlx5_core_dev *dev)
1250 {
1251 int err;
1252
1253 err = set_hca_ctrl(dev);
1254 if (err) {
1255 mlx5_core_err(dev, "set_hca_ctrl failed\n");
1256 return err;
1257 }
1258
1259 err = set_hca_cap(dev);
1260 if (err) {
1261 mlx5_core_err(dev, "set_hca_cap failed\n");
1262 return err;
1263 }
1264
1265 err = mlx5_satisfy_startup_pages(dev, 0);
1266 if (err) {
1267 mlx5_core_err(dev, "failed to allocate init pages\n");
1268 return err;
1269 }
1270
1271 err = mlx5_cmd_init_hca(dev, sw_owner_id);
1272 if (err) {
1273 mlx5_core_err(dev, "init hca failed\n");
1274 return err;
1275 }
1276
1277 mlx5_set_driver_version(dev);
1278
1279 err = mlx5_query_hca_caps(dev);
1280 if (err) {
1281 mlx5_core_err(dev, "query hca failed\n");
1282 return err;
1283 }
1284 mlx5_start_health_fw_log_up(dev);
1285 return 0;
1286 }
1287
mlx5_function_close(struct mlx5_core_dev * dev)1288 static int mlx5_function_close(struct mlx5_core_dev *dev)
1289 {
1290 int err;
1291
1292 err = mlx5_cmd_teardown_hca(dev);
1293 if (err) {
1294 mlx5_core_err(dev, "tear_down_hca failed, skip cleanup\n");
1295 return err;
1296 }
1297
1298 return 0;
1299 }
1300
mlx5_function_setup(struct mlx5_core_dev * dev,bool boot,u64 timeout)1301 static int mlx5_function_setup(struct mlx5_core_dev *dev, bool boot, u64 timeout)
1302 {
1303 int err;
1304
1305 err = mlx5_function_enable(dev, boot, timeout);
1306 if (err)
1307 return err;
1308
1309 err = mlx5_function_open(dev);
1310 if (err)
1311 mlx5_function_disable(dev, boot);
1312 return err;
1313 }
1314
mlx5_function_teardown(struct mlx5_core_dev * dev,bool boot)1315 static int mlx5_function_teardown(struct mlx5_core_dev *dev, bool boot)
1316 {
1317 int err = mlx5_function_close(dev);
1318
1319 if (!err)
1320 mlx5_function_disable(dev, boot);
1321 else
1322 mlx5_stop_health_poll(dev, boot);
1323
1324 return err;
1325 }
1326
mlx5_load(struct mlx5_core_dev * dev)1327 static int mlx5_load(struct mlx5_core_dev *dev)
1328 {
1329 int err;
1330
1331 dev->priv.uar = mlx5_get_uars_page(dev);
1332 if (IS_ERR(dev->priv.uar)) {
1333 mlx5_core_err(dev, "Failed allocating uar, aborting\n");
1334 err = PTR_ERR(dev->priv.uar);
1335 return err;
1336 }
1337
1338 mlx5_events_start(dev);
1339 mlx5_pagealloc_start(dev);
1340
1341 err = mlx5_irq_table_create(dev);
1342 if (err) {
1343 mlx5_core_err(dev, "Failed to alloc IRQs\n");
1344 goto err_irq_table;
1345 }
1346
1347 err = mlx5_eq_table_create(dev);
1348 if (err) {
1349 mlx5_core_err(dev, "Failed to create EQs\n");
1350 goto err_eq_table;
1351 }
1352
1353 err = mlx5_fw_tracer_init(dev->tracer);
1354 if (err) {
1355 mlx5_core_err(dev, "Failed to init FW tracer %d\n", err);
1356 mlx5_fw_tracer_destroy(dev->tracer);
1357 dev->tracer = NULL;
1358 }
1359
1360 mlx5_fw_reset_events_start(dev);
1361 mlx5_hv_vhca_init(dev->hv_vhca);
1362
1363 err = mlx5_rsc_dump_init(dev);
1364 if (err) {
1365 mlx5_core_err(dev, "Failed to init Resource dump %d\n", err);
1366 mlx5_rsc_dump_destroy(dev);
1367 dev->rsc_dump = NULL;
1368 }
1369
1370 err = mlx5_fpga_device_start(dev);
1371 if (err) {
1372 mlx5_core_err(dev, "fpga device start failed %d\n", err);
1373 goto err_fpga_start;
1374 }
1375
1376 err = mlx5_fs_core_init(dev);
1377 if (err) {
1378 mlx5_core_err(dev, "Failed to init flow steering\n");
1379 goto err_fs;
1380 }
1381
1382 err = mlx5_core_set_hca_defaults(dev);
1383 if (err) {
1384 mlx5_core_err(dev, "Failed to set hca defaults\n");
1385 goto err_set_hca;
1386 }
1387
1388 mlx5_vhca_event_start(dev);
1389
1390 err = mlx5_sf_hw_table_create(dev);
1391 if (err) {
1392 mlx5_core_err(dev, "sf table create failed %d\n", err);
1393 goto err_vhca;
1394 }
1395
1396 err = mlx5_ec_init(dev);
1397 if (err) {
1398 mlx5_core_err(dev, "Failed to init embedded CPU\n");
1399 goto err_ec;
1400 }
1401
1402 mlx5_lag_add_mdev(dev);
1403 err = mlx5_sriov_attach(dev);
1404 if (err) {
1405 mlx5_core_err(dev, "sriov init failed %d\n", err);
1406 goto err_sriov;
1407 }
1408
1409 mlx5_sf_dev_table_create(dev);
1410
1411 err = mlx5_devlink_traps_register(priv_to_devlink(dev));
1412 if (err)
1413 goto err_traps_reg;
1414
1415 return 0;
1416
1417 err_traps_reg:
1418 mlx5_sf_dev_table_destroy(dev);
1419 mlx5_sriov_detach(dev);
1420 err_sriov:
1421 mlx5_lag_remove_mdev(dev);
1422 mlx5_ec_cleanup(dev);
1423 err_ec:
1424 mlx5_sf_hw_table_destroy(dev);
1425 err_vhca:
1426 mlx5_vhca_event_stop(dev);
1427 err_set_hca:
1428 mlx5_fs_core_cleanup(dev);
1429 err_fs:
1430 mlx5_fpga_device_stop(dev);
1431 err_fpga_start:
1432 mlx5_rsc_dump_cleanup(dev);
1433 mlx5_hv_vhca_cleanup(dev->hv_vhca);
1434 mlx5_fw_reset_events_stop(dev);
1435 mlx5_fw_tracer_cleanup(dev->tracer);
1436 mlx5_eq_table_destroy(dev);
1437 err_eq_table:
1438 mlx5_irq_table_destroy(dev);
1439 err_irq_table:
1440 mlx5_pagealloc_stop(dev);
1441 mlx5_events_stop(dev);
1442 mlx5_put_uars_page(dev, dev->priv.uar);
1443 return err;
1444 }
1445
mlx5_unload(struct mlx5_core_dev * dev)1446 static void mlx5_unload(struct mlx5_core_dev *dev)
1447 {
1448 mlx5_eswitch_disable(dev->priv.eswitch);
1449 mlx5_devlink_traps_unregister(priv_to_devlink(dev));
1450 mlx5_sf_dev_table_destroy(dev);
1451 mlx5_sriov_detach(dev);
1452 mlx5_lag_remove_mdev(dev);
1453 mlx5_ec_cleanup(dev);
1454 mlx5_sf_hw_table_destroy(dev);
1455 mlx5_vhca_event_stop(dev);
1456 mlx5_fs_core_cleanup(dev);
1457 mlx5_fpga_device_stop(dev);
1458 mlx5_rsc_dump_cleanup(dev);
1459 mlx5_hv_vhca_cleanup(dev->hv_vhca);
1460 mlx5_fw_reset_events_stop(dev);
1461 mlx5_fw_tracer_cleanup(dev->tracer);
1462 mlx5_eq_table_destroy(dev);
1463 mlx5_irq_table_destroy(dev);
1464 mlx5_pagealloc_stop(dev);
1465 mlx5_events_stop(dev);
1466 mlx5_put_uars_page(dev, dev->priv.uar);
1467 }
1468
mlx5_init_one_devl_locked(struct mlx5_core_dev * dev)1469 int mlx5_init_one_devl_locked(struct mlx5_core_dev *dev)
1470 {
1471 bool light_probe = mlx5_dev_is_lightweight(dev);
1472 int err = 0;
1473
1474 mutex_lock(&dev->intf_state_mutex);
1475 dev->state = MLX5_DEVICE_STATE_UP;
1476
1477 err = mlx5_function_setup(dev, true, mlx5_tout_ms(dev, FW_PRE_INIT_TIMEOUT));
1478 if (err)
1479 goto err_function;
1480
1481 err = mlx5_init_once(dev);
1482 if (err) {
1483 mlx5_core_err(dev, "sw objs init failed\n");
1484 goto function_teardown;
1485 }
1486
1487 /* In case of light_probe, mlx5_devlink is already registered.
1488 * Hence, don't register devlink again.
1489 */
1490 if (!light_probe) {
1491 err = mlx5_devlink_params_register(priv_to_devlink(dev));
1492 if (err)
1493 goto err_devlink_params_reg;
1494 }
1495
1496 err = mlx5_load(dev);
1497 if (err)
1498 goto err_load;
1499
1500 set_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state);
1501
1502 err = mlx5_register_device(dev);
1503 if (err)
1504 goto err_register;
1505
1506 err = mlx5_crdump_enable(dev);
1507 if (err)
1508 mlx5_core_err(dev, "mlx5_crdump_enable failed with error code %d\n", err);
1509
1510 err = mlx5_hwmon_dev_register(dev);
1511 if (err)
1512 mlx5_core_err(dev, "mlx5_hwmon_dev_register failed with error code %d\n", err);
1513
1514 mutex_unlock(&dev->intf_state_mutex);
1515 return 0;
1516
1517 err_register:
1518 clear_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state);
1519 mlx5_unload(dev);
1520 err_load:
1521 if (!light_probe)
1522 mlx5_devlink_params_unregister(priv_to_devlink(dev));
1523 err_devlink_params_reg:
1524 mlx5_cleanup_once(dev);
1525 function_teardown:
1526 mlx5_function_teardown(dev, true);
1527 err_function:
1528 dev->state = MLX5_DEVICE_STATE_INTERNAL_ERROR;
1529 mutex_unlock(&dev->intf_state_mutex);
1530 return err;
1531 }
1532
mlx5_init_one(struct mlx5_core_dev * dev)1533 int mlx5_init_one(struct mlx5_core_dev *dev)
1534 {
1535 struct devlink *devlink = priv_to_devlink(dev);
1536 int err;
1537
1538 devl_lock(devlink);
1539 devl_register(devlink);
1540 err = mlx5_init_one_devl_locked(dev);
1541 if (err)
1542 devl_unregister(devlink);
1543 devl_unlock(devlink);
1544 return err;
1545 }
1546
mlx5_uninit_one(struct mlx5_core_dev * dev)1547 void mlx5_uninit_one(struct mlx5_core_dev *dev)
1548 {
1549 struct devlink *devlink = priv_to_devlink(dev);
1550
1551 devl_lock(devlink);
1552 mutex_lock(&dev->intf_state_mutex);
1553
1554 mlx5_hwmon_dev_unregister(dev);
1555 mlx5_crdump_disable(dev);
1556 mlx5_unregister_device(dev);
1557
1558 if (!test_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state)) {
1559 mlx5_core_warn(dev, "%s: interface is down, NOP\n",
1560 __func__);
1561 mlx5_devlink_params_unregister(priv_to_devlink(dev));
1562 mlx5_cleanup_once(dev);
1563 goto out;
1564 }
1565
1566 clear_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state);
1567 mlx5_unload(dev);
1568 mlx5_devlink_params_unregister(priv_to_devlink(dev));
1569 mlx5_cleanup_once(dev);
1570 mlx5_function_teardown(dev, true);
1571 out:
1572 mutex_unlock(&dev->intf_state_mutex);
1573 devl_unregister(devlink);
1574 devl_unlock(devlink);
1575 }
1576
mlx5_load_one_devl_locked(struct mlx5_core_dev * dev,bool recovery)1577 int mlx5_load_one_devl_locked(struct mlx5_core_dev *dev, bool recovery)
1578 {
1579 int err = 0;
1580 u64 timeout;
1581
1582 devl_assert_locked(priv_to_devlink(dev));
1583 mutex_lock(&dev->intf_state_mutex);
1584 if (test_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state)) {
1585 mlx5_core_warn(dev, "interface is up, NOP\n");
1586 goto out;
1587 }
1588 /* remove any previous indication of internal error */
1589 dev->state = MLX5_DEVICE_STATE_UP;
1590
1591 if (recovery)
1592 timeout = mlx5_tout_ms(dev, FW_PRE_INIT_ON_RECOVERY_TIMEOUT);
1593 else
1594 timeout = mlx5_tout_ms(dev, FW_PRE_INIT_TIMEOUT);
1595 err = mlx5_function_setup(dev, false, timeout);
1596 if (err)
1597 goto err_function;
1598
1599 err = mlx5_load(dev);
1600 if (err)
1601 goto err_load;
1602
1603 set_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state);
1604
1605 err = mlx5_attach_device(dev);
1606 if (err)
1607 goto err_attach;
1608
1609 mutex_unlock(&dev->intf_state_mutex);
1610 return 0;
1611
1612 err_attach:
1613 clear_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state);
1614 mlx5_unload(dev);
1615 err_load:
1616 mlx5_function_teardown(dev, false);
1617 err_function:
1618 dev->state = MLX5_DEVICE_STATE_INTERNAL_ERROR;
1619 out:
1620 mutex_unlock(&dev->intf_state_mutex);
1621 return err;
1622 }
1623
mlx5_load_one(struct mlx5_core_dev * dev,bool recovery)1624 int mlx5_load_one(struct mlx5_core_dev *dev, bool recovery)
1625 {
1626 struct devlink *devlink = priv_to_devlink(dev);
1627 int ret;
1628
1629 devl_lock(devlink);
1630 ret = mlx5_load_one_devl_locked(dev, recovery);
1631 devl_unlock(devlink);
1632 return ret;
1633 }
1634
mlx5_unload_one_devl_locked(struct mlx5_core_dev * dev,bool suspend)1635 void mlx5_unload_one_devl_locked(struct mlx5_core_dev *dev, bool suspend)
1636 {
1637 devl_assert_locked(priv_to_devlink(dev));
1638 mutex_lock(&dev->intf_state_mutex);
1639
1640 mlx5_detach_device(dev, suspend);
1641
1642 if (!test_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state)) {
1643 mlx5_core_warn(dev, "%s: interface is down, NOP\n",
1644 __func__);
1645 goto out;
1646 }
1647
1648 clear_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state);
1649 mlx5_unload(dev);
1650 mlx5_function_teardown(dev, false);
1651 out:
1652 mutex_unlock(&dev->intf_state_mutex);
1653 }
1654
mlx5_unload_one(struct mlx5_core_dev * dev,bool suspend)1655 void mlx5_unload_one(struct mlx5_core_dev *dev, bool suspend)
1656 {
1657 struct devlink *devlink = priv_to_devlink(dev);
1658
1659 devl_lock(devlink);
1660 mlx5_unload_one_devl_locked(dev, suspend);
1661 devl_unlock(devlink);
1662 }
1663
1664 /* In case of light probe, we don't need a full query of hca_caps, but only the bellow caps.
1665 * A full query of hca_caps will be done when the device will reload.
1666 */
mlx5_query_hca_caps_light(struct mlx5_core_dev * dev)1667 static int mlx5_query_hca_caps_light(struct mlx5_core_dev *dev)
1668 {
1669 int err;
1670
1671 err = mlx5_core_get_caps(dev, MLX5_CAP_GENERAL);
1672 if (err)
1673 return err;
1674
1675 if (MLX5_CAP_GEN(dev, eth_net_offloads)) {
1676 err = mlx5_core_get_caps_mode(dev, MLX5_CAP_ETHERNET_OFFLOADS,
1677 HCA_CAP_OPMOD_GET_CUR);
1678 if (err)
1679 return err;
1680 }
1681
1682 if (MLX5_CAP_GEN(dev, nic_flow_table) ||
1683 MLX5_CAP_GEN(dev, ipoib_enhanced_offloads)) {
1684 err = mlx5_core_get_caps_mode(dev, MLX5_CAP_FLOW_TABLE,
1685 HCA_CAP_OPMOD_GET_CUR);
1686 if (err)
1687 return err;
1688 }
1689
1690 if (MLX5_CAP_GEN_64(dev, general_obj_types) &
1691 MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_NET_Q) {
1692 err = mlx5_core_get_caps_mode(dev, MLX5_CAP_VDPA_EMULATION,
1693 HCA_CAP_OPMOD_GET_CUR);
1694 if (err)
1695 return err;
1696 }
1697
1698 return 0;
1699 }
1700
mlx5_init_one_light(struct mlx5_core_dev * dev)1701 int mlx5_init_one_light(struct mlx5_core_dev *dev)
1702 {
1703 struct devlink *devlink = priv_to_devlink(dev);
1704 int err;
1705
1706 devl_lock(devlink);
1707 devl_register(devlink);
1708 dev->state = MLX5_DEVICE_STATE_UP;
1709 err = mlx5_function_enable(dev, true, mlx5_tout_ms(dev, FW_PRE_INIT_TIMEOUT));
1710 if (err) {
1711 mlx5_core_warn(dev, "mlx5_function_enable err=%d\n", err);
1712 goto out;
1713 }
1714
1715 err = mlx5_query_hca_caps_light(dev);
1716 if (err) {
1717 mlx5_core_warn(dev, "mlx5_query_hca_caps_light err=%d\n", err);
1718 goto query_hca_caps_err;
1719 }
1720
1721 err = mlx5_devlink_params_register(priv_to_devlink(dev));
1722 if (err) {
1723 mlx5_core_warn(dev, "mlx5_devlink_param_reg err = %d\n", err);
1724 goto query_hca_caps_err;
1725 }
1726
1727 devl_unlock(devlink);
1728 return 0;
1729
1730 query_hca_caps_err:
1731 mlx5_function_disable(dev, true);
1732 out:
1733 dev->state = MLX5_DEVICE_STATE_INTERNAL_ERROR;
1734 devl_unregister(devlink);
1735 devl_unlock(devlink);
1736 return err;
1737 }
1738
mlx5_uninit_one_light(struct mlx5_core_dev * dev)1739 void mlx5_uninit_one_light(struct mlx5_core_dev *dev)
1740 {
1741 struct devlink *devlink = priv_to_devlink(dev);
1742
1743 devl_lock(devlink);
1744 mlx5_devlink_params_unregister(priv_to_devlink(dev));
1745 devl_unregister(devlink);
1746 devl_unlock(devlink);
1747 if (dev->state != MLX5_DEVICE_STATE_UP)
1748 return;
1749 mlx5_function_disable(dev, true);
1750 }
1751
1752 /* xxx_light() function are used in order to configure the device without full
1753 * init (light init). e.g.: There isn't a point in reload a device to light state.
1754 * Hence, mlx5_load_one_light() isn't needed.
1755 */
1756
mlx5_unload_one_light(struct mlx5_core_dev * dev)1757 void mlx5_unload_one_light(struct mlx5_core_dev *dev)
1758 {
1759 if (dev->state != MLX5_DEVICE_STATE_UP)
1760 return;
1761 mlx5_function_disable(dev, false);
1762 dev->state = MLX5_DEVICE_STATE_INTERNAL_ERROR;
1763 }
1764
1765 static const int types[] = {
1766 MLX5_CAP_GENERAL,
1767 MLX5_CAP_GENERAL_2,
1768 MLX5_CAP_ETHERNET_OFFLOADS,
1769 MLX5_CAP_IPOIB_ENHANCED_OFFLOADS,
1770 MLX5_CAP_ODP,
1771 MLX5_CAP_ATOMIC,
1772 MLX5_CAP_ROCE,
1773 MLX5_CAP_IPOIB_OFFLOADS,
1774 MLX5_CAP_FLOW_TABLE,
1775 MLX5_CAP_ESWITCH_FLOW_TABLE,
1776 MLX5_CAP_ESWITCH,
1777 MLX5_CAP_QOS,
1778 MLX5_CAP_DEBUG,
1779 MLX5_CAP_DEV_MEM,
1780 MLX5_CAP_DEV_EVENT,
1781 MLX5_CAP_TLS,
1782 MLX5_CAP_VDPA_EMULATION,
1783 MLX5_CAP_IPSEC,
1784 MLX5_CAP_PORT_SELECTION,
1785 MLX5_CAP_MACSEC,
1786 MLX5_CAP_ADV_VIRTUALIZATION,
1787 MLX5_CAP_CRYPTO,
1788 };
1789
mlx5_hca_caps_free(struct mlx5_core_dev * dev)1790 static void mlx5_hca_caps_free(struct mlx5_core_dev *dev)
1791 {
1792 int type;
1793 int i;
1794
1795 for (i = 0; i < ARRAY_SIZE(types); i++) {
1796 type = types[i];
1797 kfree(dev->caps.hca[type]);
1798 }
1799 }
1800
mlx5_hca_caps_alloc(struct mlx5_core_dev * dev)1801 static int mlx5_hca_caps_alloc(struct mlx5_core_dev *dev)
1802 {
1803 struct mlx5_hca_cap *cap;
1804 int type;
1805 int i;
1806
1807 for (i = 0; i < ARRAY_SIZE(types); i++) {
1808 cap = kzalloc(sizeof(*cap), GFP_KERNEL);
1809 if (!cap)
1810 goto err;
1811 type = types[i];
1812 dev->caps.hca[type] = cap;
1813 }
1814
1815 return 0;
1816
1817 err:
1818 mlx5_hca_caps_free(dev);
1819 return -ENOMEM;
1820 }
1821
vhca_id_show(struct seq_file * file,void * priv)1822 static int vhca_id_show(struct seq_file *file, void *priv)
1823 {
1824 struct mlx5_core_dev *dev = file->private;
1825
1826 seq_printf(file, "0x%x\n", MLX5_CAP_GEN(dev, vhca_id));
1827 return 0;
1828 }
1829
1830 DEFINE_SHOW_ATTRIBUTE(vhca_id);
1831
mlx5_mdev_init(struct mlx5_core_dev * dev,int profile_idx)1832 int mlx5_mdev_init(struct mlx5_core_dev *dev, int profile_idx)
1833 {
1834 struct mlx5_priv *priv = &dev->priv;
1835 int err;
1836
1837 memcpy(&dev->profile, &profile[profile_idx], sizeof(dev->profile));
1838 lockdep_register_key(&dev->lock_key);
1839 mutex_init(&dev->intf_state_mutex);
1840 lockdep_set_class(&dev->intf_state_mutex, &dev->lock_key);
1841 mutex_init(&dev->mlx5e_res.uplink_netdev_lock);
1842 mutex_init(&dev->wc_state_lock);
1843
1844 mutex_init(&priv->bfregs.reg_head.lock);
1845 mutex_init(&priv->bfregs.wc_head.lock);
1846 INIT_LIST_HEAD(&priv->bfregs.reg_head.list);
1847 INIT_LIST_HEAD(&priv->bfregs.wc_head.list);
1848
1849 mutex_init(&priv->alloc_mutex);
1850 mutex_init(&priv->pgdir_mutex);
1851 INIT_LIST_HEAD(&priv->pgdir_list);
1852
1853 priv->numa_node = dev_to_node(mlx5_core_dma_dev(dev));
1854 priv->dbg.dbg_root = debugfs_create_dir(dev_name(dev->device),
1855 mlx5_debugfs_root);
1856 debugfs_create_file("vhca_id", 0400, priv->dbg.dbg_root, dev, &vhca_id_fops);
1857 INIT_LIST_HEAD(&priv->traps);
1858
1859 err = mlx5_cmd_init(dev);
1860 if (err) {
1861 mlx5_core_err(dev, "Failed initializing cmdif SW structs, aborting\n");
1862 goto err_cmd_init;
1863 }
1864
1865 err = mlx5_tout_init(dev);
1866 if (err) {
1867 mlx5_core_err(dev, "Failed initializing timeouts, aborting\n");
1868 goto err_timeout_init;
1869 }
1870
1871 err = mlx5_health_init(dev);
1872 if (err)
1873 goto err_health_init;
1874
1875 err = mlx5_pagealloc_init(dev);
1876 if (err)
1877 goto err_pagealloc_init;
1878
1879 err = mlx5_adev_init(dev);
1880 if (err)
1881 goto err_adev_init;
1882
1883 err = mlx5_hca_caps_alloc(dev);
1884 if (err)
1885 goto err_hca_caps;
1886
1887 /* The conjunction of sw_vhca_id with sw_owner_id will be a global
1888 * unique id per function which uses mlx5_core.
1889 * Those values are supplied to FW as part of the init HCA command to
1890 * be used by both driver and FW when it's applicable.
1891 */
1892 dev->priv.sw_vhca_id = ida_alloc_range(&sw_vhca_ida, 1,
1893 MAX_SW_VHCA_ID,
1894 GFP_KERNEL);
1895 if (dev->priv.sw_vhca_id < 0)
1896 mlx5_core_err(dev, "failed to allocate sw_vhca_id, err=%d\n",
1897 dev->priv.sw_vhca_id);
1898
1899 return 0;
1900
1901 err_hca_caps:
1902 mlx5_adev_cleanup(dev);
1903 err_adev_init:
1904 mlx5_pagealloc_cleanup(dev);
1905 err_pagealloc_init:
1906 mlx5_health_cleanup(dev);
1907 err_health_init:
1908 mlx5_tout_cleanup(dev);
1909 err_timeout_init:
1910 mlx5_cmd_cleanup(dev);
1911 err_cmd_init:
1912 debugfs_remove(dev->priv.dbg.dbg_root);
1913 mutex_destroy(&priv->pgdir_mutex);
1914 mutex_destroy(&priv->alloc_mutex);
1915 mutex_destroy(&priv->bfregs.wc_head.lock);
1916 mutex_destroy(&priv->bfregs.reg_head.lock);
1917 mutex_destroy(&dev->intf_state_mutex);
1918 lockdep_unregister_key(&dev->lock_key);
1919 return err;
1920 }
1921
mlx5_mdev_uninit(struct mlx5_core_dev * dev)1922 void mlx5_mdev_uninit(struct mlx5_core_dev *dev)
1923 {
1924 struct mlx5_priv *priv = &dev->priv;
1925
1926 if (priv->sw_vhca_id > 0)
1927 ida_free(&sw_vhca_ida, dev->priv.sw_vhca_id);
1928
1929 mlx5_hca_caps_free(dev);
1930 mlx5_adev_cleanup(dev);
1931 mlx5_pagealloc_cleanup(dev);
1932 mlx5_health_cleanup(dev);
1933 mlx5_tout_cleanup(dev);
1934 mlx5_cmd_cleanup(dev);
1935 debugfs_remove_recursive(dev->priv.dbg.dbg_root);
1936 mutex_destroy(&priv->pgdir_mutex);
1937 mutex_destroy(&priv->alloc_mutex);
1938 mutex_destroy(&priv->bfregs.wc_head.lock);
1939 mutex_destroy(&priv->bfregs.reg_head.lock);
1940 mutex_destroy(&dev->wc_state_lock);
1941 mutex_destroy(&dev->mlx5e_res.uplink_netdev_lock);
1942 mutex_destroy(&dev->intf_state_mutex);
1943 lockdep_unregister_key(&dev->lock_key);
1944 }
1945
probe_one(struct pci_dev * pdev,const struct pci_device_id * id)1946 static int probe_one(struct pci_dev *pdev, const struct pci_device_id *id)
1947 {
1948 struct mlx5_core_dev *dev;
1949 struct devlink *devlink;
1950 int err;
1951
1952 devlink = mlx5_devlink_alloc(&pdev->dev);
1953 if (!devlink) {
1954 dev_err(&pdev->dev, "devlink alloc failed\n");
1955 return -ENOMEM;
1956 }
1957
1958 dev = devlink_priv(devlink);
1959 dev->device = &pdev->dev;
1960 dev->pdev = pdev;
1961
1962 dev->coredev_type = id->driver_data & MLX5_PCI_DEV_IS_VF ?
1963 MLX5_COREDEV_VF : MLX5_COREDEV_PF;
1964
1965 dev->priv.adev_idx = mlx5_adev_idx_alloc();
1966 if (dev->priv.adev_idx < 0) {
1967 err = dev->priv.adev_idx;
1968 goto adev_init_err;
1969 }
1970
1971 err = mlx5_mdev_init(dev, prof_sel);
1972 if (err)
1973 goto mdev_init_err;
1974
1975 err = mlx5_pci_init(dev, pdev, id);
1976 if (err) {
1977 mlx5_core_err(dev, "mlx5_pci_init failed with error code %d\n",
1978 err);
1979 goto pci_init_err;
1980 }
1981
1982 err = mlx5_init_one(dev);
1983 if (err) {
1984 mlx5_core_err(dev, "mlx5_init_one failed with error code %d\n",
1985 err);
1986 goto err_init_one;
1987 }
1988
1989 pci_save_state(pdev);
1990 return 0;
1991
1992 err_init_one:
1993 mlx5_pci_close(dev);
1994 pci_init_err:
1995 mlx5_mdev_uninit(dev);
1996 mdev_init_err:
1997 mlx5_adev_idx_free(dev->priv.adev_idx);
1998 adev_init_err:
1999 mlx5_devlink_free(devlink);
2000
2001 return err;
2002 }
2003
remove_one(struct pci_dev * pdev)2004 static void remove_one(struct pci_dev *pdev)
2005 {
2006 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
2007 struct devlink *devlink = priv_to_devlink(dev);
2008
2009 set_bit(MLX5_BREAK_FW_WAIT, &dev->intf_state);
2010 mlx5_drain_fw_reset(dev);
2011 mlx5_drain_health_wq(dev);
2012 mlx5_sriov_disable(pdev, false);
2013 mlx5_uninit_one(dev);
2014 mlx5_pci_close(dev);
2015 mlx5_mdev_uninit(dev);
2016 mlx5_adev_idx_free(dev->priv.adev_idx);
2017 mlx5_devlink_free(devlink);
2018 }
2019
2020 #define mlx5_pci_trace(dev, fmt, ...) ({ \
2021 struct mlx5_core_dev *__dev = (dev); \
2022 mlx5_core_info(__dev, "%s Device state = %d health sensors: %d pci_status: %d. " fmt, \
2023 __func__, __dev->state, mlx5_health_check_fatal_sensors(__dev), \
2024 __dev->pci_status, ##__VA_ARGS__); \
2025 })
2026
result2str(enum pci_ers_result result)2027 static const char *result2str(enum pci_ers_result result)
2028 {
2029 return result == PCI_ERS_RESULT_NEED_RESET ? "need reset" :
2030 result == PCI_ERS_RESULT_DISCONNECT ? "disconnect" :
2031 result == PCI_ERS_RESULT_RECOVERED ? "recovered" :
2032 "unknown";
2033 }
2034
mlx5_pci_err_detected(struct pci_dev * pdev,pci_channel_state_t state)2035 static pci_ers_result_t mlx5_pci_err_detected(struct pci_dev *pdev,
2036 pci_channel_state_t state)
2037 {
2038 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
2039 enum pci_ers_result res;
2040
2041 mlx5_pci_trace(dev, "Enter, pci channel state = %d\n", state);
2042
2043 mlx5_enter_error_state(dev, false);
2044 mlx5_error_sw_reset(dev);
2045 mlx5_unload_one(dev, false);
2046 mlx5_drain_health_wq(dev);
2047 mlx5_pci_disable_device(dev);
2048
2049 res = state == pci_channel_io_perm_failure ?
2050 PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_NEED_RESET;
2051
2052 mlx5_core_info(dev, "%s Device state = %d pci_status: %d. Exit, result = %d, %s\n",
2053 __func__, dev->state, dev->pci_status, res, result2str(res));
2054 return res;
2055 }
2056
2057 /* wait for the device to show vital signs by waiting
2058 * for the health counter to start counting.
2059 */
wait_vital(struct pci_dev * pdev)2060 static int wait_vital(struct pci_dev *pdev)
2061 {
2062 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
2063 struct mlx5_core_health *health = &dev->priv.health;
2064 const int niter = 100;
2065 u32 last_count = 0;
2066 u32 count;
2067 int i;
2068
2069 for (i = 0; i < niter; i++) {
2070 count = ioread32be(health->health_counter);
2071 if (count && count != 0xffffffff) {
2072 if (last_count && last_count != count) {
2073 mlx5_core_info(dev,
2074 "wait vital counter value 0x%x after %d iterations\n",
2075 count, i);
2076 return 0;
2077 }
2078 last_count = count;
2079 }
2080 msleep(50);
2081 }
2082
2083 return -ETIMEDOUT;
2084 }
2085
mlx5_pci_slot_reset(struct pci_dev * pdev)2086 static pci_ers_result_t mlx5_pci_slot_reset(struct pci_dev *pdev)
2087 {
2088 enum pci_ers_result res = PCI_ERS_RESULT_DISCONNECT;
2089 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
2090 int err;
2091
2092 mlx5_core_info(dev, "%s Device state = %d pci_status: %d. Enter\n",
2093 __func__, dev->state, dev->pci_status);
2094
2095 err = mlx5_pci_enable_device(dev);
2096 if (err) {
2097 mlx5_core_err(dev, "%s: mlx5_pci_enable_device failed with error code: %d\n",
2098 __func__, err);
2099 goto out;
2100 }
2101
2102 pci_set_master(pdev);
2103 pci_restore_state(pdev);
2104 pci_save_state(pdev);
2105
2106 err = wait_vital(pdev);
2107 if (err) {
2108 mlx5_core_err(dev, "%s: wait vital failed with error code: %d\n",
2109 __func__, err);
2110 goto out;
2111 }
2112
2113 res = PCI_ERS_RESULT_RECOVERED;
2114 out:
2115 mlx5_core_info(dev, "%s Device state = %d pci_status: %d. Exit, err = %d, result = %d, %s\n",
2116 __func__, dev->state, dev->pci_status, err, res, result2str(res));
2117 return res;
2118 }
2119
mlx5_pci_resume(struct pci_dev * pdev)2120 static void mlx5_pci_resume(struct pci_dev *pdev)
2121 {
2122 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
2123 int err;
2124
2125 mlx5_pci_trace(dev, "Enter, loading driver..\n");
2126
2127 err = mlx5_load_one(dev, false);
2128
2129 if (!err)
2130 devlink_health_reporter_state_update(dev->priv.health.fw_fatal_reporter,
2131 DEVLINK_HEALTH_REPORTER_STATE_HEALTHY);
2132
2133 mlx5_pci_trace(dev, "Done, err = %d, device %s\n", err,
2134 !err ? "recovered" : "Failed");
2135 }
2136
2137 static const struct pci_error_handlers mlx5_err_handler = {
2138 .error_detected = mlx5_pci_err_detected,
2139 .slot_reset = mlx5_pci_slot_reset,
2140 .resume = mlx5_pci_resume
2141 };
2142
mlx5_try_fast_unload(struct mlx5_core_dev * dev)2143 static int mlx5_try_fast_unload(struct mlx5_core_dev *dev)
2144 {
2145 bool fast_teardown = false, force_teardown = false;
2146 int ret = 1;
2147
2148 fast_teardown = MLX5_CAP_GEN(dev, fast_teardown);
2149 force_teardown = MLX5_CAP_GEN(dev, force_teardown);
2150
2151 mlx5_core_dbg(dev, "force teardown firmware support=%d\n", force_teardown);
2152 mlx5_core_dbg(dev, "fast teardown firmware support=%d\n", fast_teardown);
2153
2154 if (!fast_teardown && !force_teardown)
2155 return -EOPNOTSUPP;
2156
2157 if (dev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) {
2158 mlx5_core_dbg(dev, "Device in internal error state, giving up\n");
2159 return -EAGAIN;
2160 }
2161
2162 /* Panic tear down fw command will stop the PCI bus communication
2163 * with the HCA, so the health poll is no longer needed.
2164 */
2165 mlx5_stop_health_poll(dev, false);
2166
2167 ret = mlx5_cmd_fast_teardown_hca(dev);
2168 if (!ret)
2169 goto succeed;
2170
2171 ret = mlx5_cmd_force_teardown_hca(dev);
2172 if (!ret)
2173 goto succeed;
2174
2175 mlx5_core_dbg(dev, "Firmware couldn't do fast unload error: %d\n", ret);
2176 mlx5_start_health_poll(dev);
2177 return ret;
2178
2179 succeed:
2180 mlx5_enter_error_state(dev, true);
2181
2182 /* Some platforms requiring freeing the IRQ's in the shutdown
2183 * flow. If they aren't freed they can't be allocated after
2184 * kexec. There is no need to cleanup the mlx5_core software
2185 * contexts.
2186 */
2187 mlx5_core_eq_free_irqs(dev);
2188
2189 return 0;
2190 }
2191
shutdown(struct pci_dev * pdev)2192 static void shutdown(struct pci_dev *pdev)
2193 {
2194 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
2195 int err;
2196
2197 mlx5_core_info(dev, "Shutdown was called\n");
2198 set_bit(MLX5_BREAK_FW_WAIT, &dev->intf_state);
2199 mlx5_drain_health_wq(dev);
2200 err = mlx5_try_fast_unload(dev);
2201 if (err)
2202 mlx5_unload_one(dev, false);
2203 mlx5_pci_disable_device(dev);
2204 }
2205
mlx5_suspend(struct pci_dev * pdev,pm_message_t state)2206 static int mlx5_suspend(struct pci_dev *pdev, pm_message_t state)
2207 {
2208 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
2209
2210 mlx5_unload_one(dev, true);
2211
2212 return 0;
2213 }
2214
mlx5_resume(struct pci_dev * pdev)2215 static int mlx5_resume(struct pci_dev *pdev)
2216 {
2217 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
2218
2219 return mlx5_load_one(dev, false);
2220 }
2221
2222 static const struct pci_device_id mlx5_core_pci_table[] = {
2223 { PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_CONNECTIB) },
2224 { PCI_VDEVICE(MELLANOX, 0x1012), MLX5_PCI_DEV_IS_VF}, /* Connect-IB VF */
2225 { PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_CONNECTX4) },
2226 { PCI_VDEVICE(MELLANOX, 0x1014), MLX5_PCI_DEV_IS_VF}, /* ConnectX-4 VF */
2227 { PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_CONNECTX4_LX) },
2228 { PCI_VDEVICE(MELLANOX, 0x1016), MLX5_PCI_DEV_IS_VF}, /* ConnectX-4LX VF */
2229 { PCI_VDEVICE(MELLANOX, 0x1017) }, /* ConnectX-5, PCIe 3.0 */
2230 { PCI_VDEVICE(MELLANOX, 0x1018), MLX5_PCI_DEV_IS_VF}, /* ConnectX-5 VF */
2231 { PCI_VDEVICE(MELLANOX, 0x1019) }, /* ConnectX-5 Ex */
2232 { PCI_VDEVICE(MELLANOX, 0x101a), MLX5_PCI_DEV_IS_VF}, /* ConnectX-5 Ex VF */
2233 { PCI_VDEVICE(MELLANOX, 0x101b) }, /* ConnectX-6 */
2234 { PCI_VDEVICE(MELLANOX, 0x101c), MLX5_PCI_DEV_IS_VF}, /* ConnectX-6 VF */
2235 { PCI_VDEVICE(MELLANOX, 0x101d) }, /* ConnectX-6 Dx */
2236 { PCI_VDEVICE(MELLANOX, 0x101e), MLX5_PCI_DEV_IS_VF}, /* ConnectX Family mlx5Gen Virtual Function */
2237 { PCI_VDEVICE(MELLANOX, 0x101f) }, /* ConnectX-6 LX */
2238 { PCI_VDEVICE(MELLANOX, 0x1021) }, /* ConnectX-7 */
2239 { PCI_VDEVICE(MELLANOX, 0x1023) }, /* ConnectX-8 */
2240 { PCI_VDEVICE(MELLANOX, 0x1025) }, /* ConnectX-9 */
2241 { PCI_VDEVICE(MELLANOX, 0x1027) }, /* ConnectX-10 */
2242 { PCI_VDEVICE(MELLANOX, 0xa2d2) }, /* BlueField integrated ConnectX-5 network controller */
2243 { PCI_VDEVICE(MELLANOX, 0xa2d3), MLX5_PCI_DEV_IS_VF}, /* BlueField integrated ConnectX-5 network controller VF */
2244 { PCI_VDEVICE(MELLANOX, 0xa2d6) }, /* BlueField-2 integrated ConnectX-6 Dx network controller */
2245 { PCI_VDEVICE(MELLANOX, 0xa2dc) }, /* BlueField-3 integrated ConnectX-7 network controller */
2246 { PCI_VDEVICE(MELLANOX, 0xa2df) }, /* BlueField-4 integrated ConnectX-8 network controller */
2247 { 0, }
2248 };
2249
2250 MODULE_DEVICE_TABLE(pci, mlx5_core_pci_table);
2251
mlx5_disable_device(struct mlx5_core_dev * dev)2252 void mlx5_disable_device(struct mlx5_core_dev *dev)
2253 {
2254 mlx5_error_sw_reset(dev);
2255 mlx5_unload_one_devl_locked(dev, false);
2256 }
2257
mlx5_recover_device(struct mlx5_core_dev * dev)2258 int mlx5_recover_device(struct mlx5_core_dev *dev)
2259 {
2260 if (!mlx5_core_is_sf(dev)) {
2261 mlx5_pci_disable_device(dev);
2262 if (mlx5_pci_slot_reset(dev->pdev) != PCI_ERS_RESULT_RECOVERED)
2263 return -EIO;
2264 }
2265
2266 return mlx5_load_one_devl_locked(dev, true);
2267 }
2268
2269 static struct pci_driver mlx5_core_driver = {
2270 .name = KBUILD_MODNAME,
2271 .id_table = mlx5_core_pci_table,
2272 .probe = probe_one,
2273 .remove = remove_one,
2274 .suspend = mlx5_suspend,
2275 .resume = mlx5_resume,
2276 .shutdown = shutdown,
2277 .err_handler = &mlx5_err_handler,
2278 .sriov_configure = mlx5_core_sriov_configure,
2279 .sriov_get_vf_total_msix = mlx5_sriov_get_vf_total_msix,
2280 .sriov_set_msix_vec_count = mlx5_core_sriov_set_msix_vec_count,
2281 };
2282
2283 /**
2284 * mlx5_vf_get_core_dev - Get the mlx5 core device from a given VF PCI device if
2285 * mlx5_core is its driver.
2286 * @pdev: The associated PCI device.
2287 *
2288 * Upon return the interface state lock stay held to let caller uses it safely.
2289 * Caller must ensure to use the returned mlx5 device for a narrow window
2290 * and put it back with mlx5_vf_put_core_dev() immediately once usage was over.
2291 *
2292 * Return: Pointer to the associated mlx5_core_dev or NULL.
2293 */
mlx5_vf_get_core_dev(struct pci_dev * pdev)2294 struct mlx5_core_dev *mlx5_vf_get_core_dev(struct pci_dev *pdev)
2295 {
2296 struct mlx5_core_dev *mdev;
2297
2298 mdev = pci_iov_get_pf_drvdata(pdev, &mlx5_core_driver);
2299 if (IS_ERR(mdev))
2300 return NULL;
2301
2302 mutex_lock(&mdev->intf_state_mutex);
2303 if (!test_bit(MLX5_INTERFACE_STATE_UP, &mdev->intf_state)) {
2304 mutex_unlock(&mdev->intf_state_mutex);
2305 return NULL;
2306 }
2307
2308 return mdev;
2309 }
2310 EXPORT_SYMBOL(mlx5_vf_get_core_dev);
2311
2312 /**
2313 * mlx5_vf_put_core_dev - Put the mlx5 core device back.
2314 * @mdev: The mlx5 core device.
2315 *
2316 * Upon return the interface state lock is unlocked and caller should not
2317 * access the mdev any more.
2318 */
mlx5_vf_put_core_dev(struct mlx5_core_dev * mdev)2319 void mlx5_vf_put_core_dev(struct mlx5_core_dev *mdev)
2320 {
2321 mutex_unlock(&mdev->intf_state_mutex);
2322 }
2323 EXPORT_SYMBOL(mlx5_vf_put_core_dev);
2324
mlx5_core_verify_params(void)2325 static void mlx5_core_verify_params(void)
2326 {
2327 if (prof_sel >= ARRAY_SIZE(profile)) {
2328 pr_warn("mlx5_core: WARNING: Invalid module parameter prof_sel %d, valid range 0-%zu, changing back to default(%d)\n",
2329 prof_sel,
2330 ARRAY_SIZE(profile) - 1,
2331 MLX5_DEFAULT_PROF);
2332 prof_sel = MLX5_DEFAULT_PROF;
2333 }
2334 }
2335
mlx5_init(void)2336 static int __init mlx5_init(void)
2337 {
2338 int err;
2339
2340 WARN_ONCE(strcmp(MLX5_ADEV_NAME, KBUILD_MODNAME),
2341 "mlx5_core name not in sync with kernel module name");
2342
2343 get_random_bytes(&sw_owner_id, sizeof(sw_owner_id));
2344
2345 mlx5_core_verify_params();
2346 mlx5_register_debugfs();
2347
2348 err = mlx5e_init();
2349 if (err)
2350 goto err_debug;
2351
2352 err = mlx5_sf_driver_register();
2353 if (err)
2354 goto err_sf;
2355
2356 err = pci_register_driver(&mlx5_core_driver);
2357 if (err)
2358 goto err_pci;
2359
2360 return 0;
2361
2362 err_pci:
2363 mlx5_sf_driver_unregister();
2364 err_sf:
2365 mlx5e_cleanup();
2366 err_debug:
2367 mlx5_unregister_debugfs();
2368 return err;
2369 }
2370
mlx5_cleanup(void)2371 static void __exit mlx5_cleanup(void)
2372 {
2373 pci_unregister_driver(&mlx5_core_driver);
2374 mlx5_sf_driver_unregister();
2375 mlx5e_cleanup();
2376 mlx5_unregister_debugfs();
2377 }
2378
2379 module_init(mlx5_init);
2380 module_exit(mlx5_cleanup);
2381