1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /**
3 * DOC: dwmac-rk.c - Rockchip RK3288 DWMAC specific glue layer
4 *
5 * Copyright (C) 2014 Chen-Zhi (Roger Chen)
6 *
7 * Chen-Zhi (Roger Chen) <roger.chen@rock-chips.com>
8 */
9
10 #include <linux/stmmac.h>
11 #include <linux/bitops.h>
12 #include <linux/clk.h>
13 #include <linux/phy.h>
14 #include <linux/of_net.h>
15 #include <linux/module.h>
16 #include <linux/of.h>
17 #include <linux/platform_device.h>
18 #include <linux/regulator/consumer.h>
19 #include <linux/delay.h>
20 #include <linux/mfd/syscon.h>
21 #include <linux/regmap.h>
22 #include <linux/pm_runtime.h>
23
24 #include "stmmac_platform.h"
25
26 struct rk_priv_data;
27 struct rk_gmac_ops {
28 void (*set_to_rgmii)(struct rk_priv_data *bsp_priv,
29 int tx_delay, int rx_delay);
30 void (*set_to_rmii)(struct rk_priv_data *bsp_priv);
31 void (*set_rgmii_speed)(struct rk_priv_data *bsp_priv, int speed);
32 void (*set_rmii_speed)(struct rk_priv_data *bsp_priv, int speed);
33 void (*set_clock_selection)(struct rk_priv_data *bsp_priv, bool input,
34 bool enable);
35 void (*integrated_phy_powerup)(struct rk_priv_data *bsp_priv);
36 bool php_grf_required;
37 bool regs_valid;
38 u32 regs[];
39 };
40
41 static const char * const rk_clocks[] = {
42 "aclk_mac", "pclk_mac", "mac_clk_tx", "clk_mac_speed",
43 };
44
45 static const char * const rk_rmii_clocks[] = {
46 "mac_clk_rx", "clk_mac_ref", "clk_mac_refout",
47 };
48
49 enum rk_clocks_index {
50 RK_ACLK_MAC = 0,
51 RK_PCLK_MAC,
52 RK_MAC_CLK_TX,
53 RK_CLK_MAC_SPEED,
54 RK_MAC_CLK_RX,
55 RK_CLK_MAC_REF,
56 RK_CLK_MAC_REFOUT,
57 };
58
59 struct rk_priv_data {
60 struct platform_device *pdev;
61 phy_interface_t phy_iface;
62 int id;
63 struct regulator *regulator;
64 bool suspended;
65 const struct rk_gmac_ops *ops;
66
67 bool clk_enabled;
68 bool clock_input;
69 bool integrated_phy;
70
71 struct clk_bulk_data *clks;
72 int num_clks;
73 struct clk *clk_mac;
74 struct clk *clk_phy;
75
76 struct reset_control *phy_reset;
77
78 int tx_delay;
79 int rx_delay;
80
81 struct regmap *grf;
82 struct regmap *php_grf;
83 };
84
85 #define HIWORD_UPDATE(val, mask, shift) \
86 ((val) << (shift) | (mask) << ((shift) + 16))
87
88 #define GRF_BIT(nr) (BIT(nr) | BIT(nr+16))
89 #define GRF_CLR_BIT(nr) (BIT(nr+16))
90
91 #define DELAY_ENABLE(soc, tx, rx) \
92 (((tx) ? soc##_GMAC_TXCLK_DLY_ENABLE : soc##_GMAC_TXCLK_DLY_DISABLE) | \
93 ((rx) ? soc##_GMAC_RXCLK_DLY_ENABLE : soc##_GMAC_RXCLK_DLY_DISABLE))
94
95 #define PX30_GRF_GMAC_CON1 0x0904
96
97 /* PX30_GRF_GMAC_CON1 */
98 #define PX30_GMAC_PHY_INTF_SEL_RMII (GRF_CLR_BIT(4) | GRF_CLR_BIT(5) | \
99 GRF_BIT(6))
100 #define PX30_GMAC_SPEED_10M GRF_CLR_BIT(2)
101 #define PX30_GMAC_SPEED_100M GRF_BIT(2)
102
px30_set_to_rmii(struct rk_priv_data * bsp_priv)103 static void px30_set_to_rmii(struct rk_priv_data *bsp_priv)
104 {
105 struct device *dev = &bsp_priv->pdev->dev;
106
107 if (IS_ERR(bsp_priv->grf)) {
108 dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
109 return;
110 }
111
112 regmap_write(bsp_priv->grf, PX30_GRF_GMAC_CON1,
113 PX30_GMAC_PHY_INTF_SEL_RMII);
114 }
115
px30_set_rmii_speed(struct rk_priv_data * bsp_priv,int speed)116 static void px30_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed)
117 {
118 struct clk *clk_mac_speed = bsp_priv->clks[RK_CLK_MAC_SPEED].clk;
119 struct device *dev = &bsp_priv->pdev->dev;
120 int ret;
121
122 if (!clk_mac_speed) {
123 dev_err(dev, "%s: Missing clk_mac_speed clock\n", __func__);
124 return;
125 }
126
127 if (speed == 10) {
128 regmap_write(bsp_priv->grf, PX30_GRF_GMAC_CON1,
129 PX30_GMAC_SPEED_10M);
130
131 ret = clk_set_rate(clk_mac_speed, 2500000);
132 if (ret)
133 dev_err(dev, "%s: set clk_mac_speed rate 2500000 failed: %d\n",
134 __func__, ret);
135 } else if (speed == 100) {
136 regmap_write(bsp_priv->grf, PX30_GRF_GMAC_CON1,
137 PX30_GMAC_SPEED_100M);
138
139 ret = clk_set_rate(clk_mac_speed, 25000000);
140 if (ret)
141 dev_err(dev, "%s: set clk_mac_speed rate 25000000 failed: %d\n",
142 __func__, ret);
143
144 } else {
145 dev_err(dev, "unknown speed value for RMII! speed=%d", speed);
146 }
147 }
148
149 static const struct rk_gmac_ops px30_ops = {
150 .set_to_rmii = px30_set_to_rmii,
151 .set_rmii_speed = px30_set_rmii_speed,
152 };
153
154 #define RK3128_GRF_MAC_CON0 0x0168
155 #define RK3128_GRF_MAC_CON1 0x016c
156
157 /* RK3128_GRF_MAC_CON0 */
158 #define RK3128_GMAC_TXCLK_DLY_ENABLE GRF_BIT(14)
159 #define RK3128_GMAC_TXCLK_DLY_DISABLE GRF_CLR_BIT(14)
160 #define RK3128_GMAC_RXCLK_DLY_ENABLE GRF_BIT(15)
161 #define RK3128_GMAC_RXCLK_DLY_DISABLE GRF_CLR_BIT(15)
162 #define RK3128_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 7)
163 #define RK3128_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 0)
164
165 /* RK3128_GRF_MAC_CON1 */
166 #define RK3128_GMAC_PHY_INTF_SEL_RGMII \
167 (GRF_BIT(6) | GRF_CLR_BIT(7) | GRF_CLR_BIT(8))
168 #define RK3128_GMAC_PHY_INTF_SEL_RMII \
169 (GRF_CLR_BIT(6) | GRF_CLR_BIT(7) | GRF_BIT(8))
170 #define RK3128_GMAC_FLOW_CTRL GRF_BIT(9)
171 #define RK3128_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(9)
172 #define RK3128_GMAC_SPEED_10M GRF_CLR_BIT(10)
173 #define RK3128_GMAC_SPEED_100M GRF_BIT(10)
174 #define RK3128_GMAC_RMII_CLK_25M GRF_BIT(11)
175 #define RK3128_GMAC_RMII_CLK_2_5M GRF_CLR_BIT(11)
176 #define RK3128_GMAC_CLK_125M (GRF_CLR_BIT(12) | GRF_CLR_BIT(13))
177 #define RK3128_GMAC_CLK_25M (GRF_BIT(12) | GRF_BIT(13))
178 #define RK3128_GMAC_CLK_2_5M (GRF_CLR_BIT(12) | GRF_BIT(13))
179 #define RK3128_GMAC_RMII_MODE GRF_BIT(14)
180 #define RK3128_GMAC_RMII_MODE_CLR GRF_CLR_BIT(14)
181
rk3128_set_to_rgmii(struct rk_priv_data * bsp_priv,int tx_delay,int rx_delay)182 static void rk3128_set_to_rgmii(struct rk_priv_data *bsp_priv,
183 int tx_delay, int rx_delay)
184 {
185 struct device *dev = &bsp_priv->pdev->dev;
186
187 if (IS_ERR(bsp_priv->grf)) {
188 dev_err(dev, "Missing rockchip,grf property\n");
189 return;
190 }
191
192 regmap_write(bsp_priv->grf, RK3128_GRF_MAC_CON1,
193 RK3128_GMAC_PHY_INTF_SEL_RGMII |
194 RK3128_GMAC_RMII_MODE_CLR);
195 regmap_write(bsp_priv->grf, RK3128_GRF_MAC_CON0,
196 DELAY_ENABLE(RK3128, tx_delay, rx_delay) |
197 RK3128_GMAC_CLK_RX_DL_CFG(rx_delay) |
198 RK3128_GMAC_CLK_TX_DL_CFG(tx_delay));
199 }
200
rk3128_set_to_rmii(struct rk_priv_data * bsp_priv)201 static void rk3128_set_to_rmii(struct rk_priv_data *bsp_priv)
202 {
203 struct device *dev = &bsp_priv->pdev->dev;
204
205 if (IS_ERR(bsp_priv->grf)) {
206 dev_err(dev, "Missing rockchip,grf property\n");
207 return;
208 }
209
210 regmap_write(bsp_priv->grf, RK3128_GRF_MAC_CON1,
211 RK3128_GMAC_PHY_INTF_SEL_RMII | RK3128_GMAC_RMII_MODE);
212 }
213
rk3128_set_rgmii_speed(struct rk_priv_data * bsp_priv,int speed)214 static void rk3128_set_rgmii_speed(struct rk_priv_data *bsp_priv, int speed)
215 {
216 struct device *dev = &bsp_priv->pdev->dev;
217
218 if (IS_ERR(bsp_priv->grf)) {
219 dev_err(dev, "Missing rockchip,grf property\n");
220 return;
221 }
222
223 if (speed == 10)
224 regmap_write(bsp_priv->grf, RK3128_GRF_MAC_CON1,
225 RK3128_GMAC_CLK_2_5M);
226 else if (speed == 100)
227 regmap_write(bsp_priv->grf, RK3128_GRF_MAC_CON1,
228 RK3128_GMAC_CLK_25M);
229 else if (speed == 1000)
230 regmap_write(bsp_priv->grf, RK3128_GRF_MAC_CON1,
231 RK3128_GMAC_CLK_125M);
232 else
233 dev_err(dev, "unknown speed value for RGMII! speed=%d", speed);
234 }
235
rk3128_set_rmii_speed(struct rk_priv_data * bsp_priv,int speed)236 static void rk3128_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed)
237 {
238 struct device *dev = &bsp_priv->pdev->dev;
239
240 if (IS_ERR(bsp_priv->grf)) {
241 dev_err(dev, "Missing rockchip,grf property\n");
242 return;
243 }
244
245 if (speed == 10) {
246 regmap_write(bsp_priv->grf, RK3128_GRF_MAC_CON1,
247 RK3128_GMAC_RMII_CLK_2_5M |
248 RK3128_GMAC_SPEED_10M);
249 } else if (speed == 100) {
250 regmap_write(bsp_priv->grf, RK3128_GRF_MAC_CON1,
251 RK3128_GMAC_RMII_CLK_25M |
252 RK3128_GMAC_SPEED_100M);
253 } else {
254 dev_err(dev, "unknown speed value for RMII! speed=%d", speed);
255 }
256 }
257
258 static const struct rk_gmac_ops rk3128_ops = {
259 .set_to_rgmii = rk3128_set_to_rgmii,
260 .set_to_rmii = rk3128_set_to_rmii,
261 .set_rgmii_speed = rk3128_set_rgmii_speed,
262 .set_rmii_speed = rk3128_set_rmii_speed,
263 };
264
265 #define RK3228_GRF_MAC_CON0 0x0900
266 #define RK3228_GRF_MAC_CON1 0x0904
267
268 #define RK3228_GRF_CON_MUX 0x50
269
270 /* RK3228_GRF_MAC_CON0 */
271 #define RK3228_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 7)
272 #define RK3228_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 0)
273
274 /* RK3228_GRF_MAC_CON1 */
275 #define RK3228_GMAC_PHY_INTF_SEL_RGMII \
276 (GRF_BIT(4) | GRF_CLR_BIT(5) | GRF_CLR_BIT(6))
277 #define RK3228_GMAC_PHY_INTF_SEL_RMII \
278 (GRF_CLR_BIT(4) | GRF_CLR_BIT(5) | GRF_BIT(6))
279 #define RK3228_GMAC_FLOW_CTRL GRF_BIT(3)
280 #define RK3228_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(3)
281 #define RK3228_GMAC_SPEED_10M GRF_CLR_BIT(2)
282 #define RK3228_GMAC_SPEED_100M GRF_BIT(2)
283 #define RK3228_GMAC_RMII_CLK_25M GRF_BIT(7)
284 #define RK3228_GMAC_RMII_CLK_2_5M GRF_CLR_BIT(7)
285 #define RK3228_GMAC_CLK_125M (GRF_CLR_BIT(8) | GRF_CLR_BIT(9))
286 #define RK3228_GMAC_CLK_25M (GRF_BIT(8) | GRF_BIT(9))
287 #define RK3228_GMAC_CLK_2_5M (GRF_CLR_BIT(8) | GRF_BIT(9))
288 #define RK3228_GMAC_RMII_MODE GRF_BIT(10)
289 #define RK3228_GMAC_RMII_MODE_CLR GRF_CLR_BIT(10)
290 #define RK3228_GMAC_TXCLK_DLY_ENABLE GRF_BIT(0)
291 #define RK3228_GMAC_TXCLK_DLY_DISABLE GRF_CLR_BIT(0)
292 #define RK3228_GMAC_RXCLK_DLY_ENABLE GRF_BIT(1)
293 #define RK3228_GMAC_RXCLK_DLY_DISABLE GRF_CLR_BIT(1)
294
295 /* RK3228_GRF_COM_MUX */
296 #define RK3228_GRF_CON_MUX_GMAC_INTEGRATED_PHY GRF_BIT(15)
297
rk3228_set_to_rgmii(struct rk_priv_data * bsp_priv,int tx_delay,int rx_delay)298 static void rk3228_set_to_rgmii(struct rk_priv_data *bsp_priv,
299 int tx_delay, int rx_delay)
300 {
301 struct device *dev = &bsp_priv->pdev->dev;
302
303 if (IS_ERR(bsp_priv->grf)) {
304 dev_err(dev, "Missing rockchip,grf property\n");
305 return;
306 }
307
308 regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON1,
309 RK3228_GMAC_PHY_INTF_SEL_RGMII |
310 RK3228_GMAC_RMII_MODE_CLR |
311 DELAY_ENABLE(RK3228, tx_delay, rx_delay));
312
313 regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON0,
314 RK3228_GMAC_CLK_RX_DL_CFG(rx_delay) |
315 RK3228_GMAC_CLK_TX_DL_CFG(tx_delay));
316 }
317
rk3228_set_to_rmii(struct rk_priv_data * bsp_priv)318 static void rk3228_set_to_rmii(struct rk_priv_data *bsp_priv)
319 {
320 struct device *dev = &bsp_priv->pdev->dev;
321
322 if (IS_ERR(bsp_priv->grf)) {
323 dev_err(dev, "Missing rockchip,grf property\n");
324 return;
325 }
326
327 regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON1,
328 RK3228_GMAC_PHY_INTF_SEL_RMII |
329 RK3228_GMAC_RMII_MODE);
330
331 /* set MAC to RMII mode */
332 regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON1, GRF_BIT(11));
333 }
334
rk3228_set_rgmii_speed(struct rk_priv_data * bsp_priv,int speed)335 static void rk3228_set_rgmii_speed(struct rk_priv_data *bsp_priv, int speed)
336 {
337 struct device *dev = &bsp_priv->pdev->dev;
338
339 if (IS_ERR(bsp_priv->grf)) {
340 dev_err(dev, "Missing rockchip,grf property\n");
341 return;
342 }
343
344 if (speed == 10)
345 regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON1,
346 RK3228_GMAC_CLK_2_5M);
347 else if (speed == 100)
348 regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON1,
349 RK3228_GMAC_CLK_25M);
350 else if (speed == 1000)
351 regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON1,
352 RK3228_GMAC_CLK_125M);
353 else
354 dev_err(dev, "unknown speed value for RGMII! speed=%d", speed);
355 }
356
rk3228_set_rmii_speed(struct rk_priv_data * bsp_priv,int speed)357 static void rk3228_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed)
358 {
359 struct device *dev = &bsp_priv->pdev->dev;
360
361 if (IS_ERR(bsp_priv->grf)) {
362 dev_err(dev, "Missing rockchip,grf property\n");
363 return;
364 }
365
366 if (speed == 10)
367 regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON1,
368 RK3228_GMAC_RMII_CLK_2_5M |
369 RK3228_GMAC_SPEED_10M);
370 else if (speed == 100)
371 regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON1,
372 RK3228_GMAC_RMII_CLK_25M |
373 RK3228_GMAC_SPEED_100M);
374 else
375 dev_err(dev, "unknown speed value for RMII! speed=%d", speed);
376 }
377
rk3228_integrated_phy_powerup(struct rk_priv_data * priv)378 static void rk3228_integrated_phy_powerup(struct rk_priv_data *priv)
379 {
380 regmap_write(priv->grf, RK3228_GRF_CON_MUX,
381 RK3228_GRF_CON_MUX_GMAC_INTEGRATED_PHY);
382 }
383
384 static const struct rk_gmac_ops rk3228_ops = {
385 .set_to_rgmii = rk3228_set_to_rgmii,
386 .set_to_rmii = rk3228_set_to_rmii,
387 .set_rgmii_speed = rk3228_set_rgmii_speed,
388 .set_rmii_speed = rk3228_set_rmii_speed,
389 .integrated_phy_powerup = rk3228_integrated_phy_powerup,
390 };
391
392 #define RK3288_GRF_SOC_CON1 0x0248
393 #define RK3288_GRF_SOC_CON3 0x0250
394
395 /*RK3288_GRF_SOC_CON1*/
396 #define RK3288_GMAC_PHY_INTF_SEL_RGMII (GRF_BIT(6) | GRF_CLR_BIT(7) | \
397 GRF_CLR_BIT(8))
398 #define RK3288_GMAC_PHY_INTF_SEL_RMII (GRF_CLR_BIT(6) | GRF_CLR_BIT(7) | \
399 GRF_BIT(8))
400 #define RK3288_GMAC_FLOW_CTRL GRF_BIT(9)
401 #define RK3288_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(9)
402 #define RK3288_GMAC_SPEED_10M GRF_CLR_BIT(10)
403 #define RK3288_GMAC_SPEED_100M GRF_BIT(10)
404 #define RK3288_GMAC_RMII_CLK_25M GRF_BIT(11)
405 #define RK3288_GMAC_RMII_CLK_2_5M GRF_CLR_BIT(11)
406 #define RK3288_GMAC_CLK_125M (GRF_CLR_BIT(12) | GRF_CLR_BIT(13))
407 #define RK3288_GMAC_CLK_25M (GRF_BIT(12) | GRF_BIT(13))
408 #define RK3288_GMAC_CLK_2_5M (GRF_CLR_BIT(12) | GRF_BIT(13))
409 #define RK3288_GMAC_RMII_MODE GRF_BIT(14)
410 #define RK3288_GMAC_RMII_MODE_CLR GRF_CLR_BIT(14)
411
412 /*RK3288_GRF_SOC_CON3*/
413 #define RK3288_GMAC_TXCLK_DLY_ENABLE GRF_BIT(14)
414 #define RK3288_GMAC_TXCLK_DLY_DISABLE GRF_CLR_BIT(14)
415 #define RK3288_GMAC_RXCLK_DLY_ENABLE GRF_BIT(15)
416 #define RK3288_GMAC_RXCLK_DLY_DISABLE GRF_CLR_BIT(15)
417 #define RK3288_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 7)
418 #define RK3288_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 0)
419
rk3288_set_to_rgmii(struct rk_priv_data * bsp_priv,int tx_delay,int rx_delay)420 static void rk3288_set_to_rgmii(struct rk_priv_data *bsp_priv,
421 int tx_delay, int rx_delay)
422 {
423 struct device *dev = &bsp_priv->pdev->dev;
424
425 if (IS_ERR(bsp_priv->grf)) {
426 dev_err(dev, "Missing rockchip,grf property\n");
427 return;
428 }
429
430 regmap_write(bsp_priv->grf, RK3288_GRF_SOC_CON1,
431 RK3288_GMAC_PHY_INTF_SEL_RGMII |
432 RK3288_GMAC_RMII_MODE_CLR);
433 regmap_write(bsp_priv->grf, RK3288_GRF_SOC_CON3,
434 DELAY_ENABLE(RK3288, tx_delay, rx_delay) |
435 RK3288_GMAC_CLK_RX_DL_CFG(rx_delay) |
436 RK3288_GMAC_CLK_TX_DL_CFG(tx_delay));
437 }
438
rk3288_set_to_rmii(struct rk_priv_data * bsp_priv)439 static void rk3288_set_to_rmii(struct rk_priv_data *bsp_priv)
440 {
441 struct device *dev = &bsp_priv->pdev->dev;
442
443 if (IS_ERR(bsp_priv->grf)) {
444 dev_err(dev, "Missing rockchip,grf property\n");
445 return;
446 }
447
448 regmap_write(bsp_priv->grf, RK3288_GRF_SOC_CON1,
449 RK3288_GMAC_PHY_INTF_SEL_RMII | RK3288_GMAC_RMII_MODE);
450 }
451
rk3288_set_rgmii_speed(struct rk_priv_data * bsp_priv,int speed)452 static void rk3288_set_rgmii_speed(struct rk_priv_data *bsp_priv, int speed)
453 {
454 struct device *dev = &bsp_priv->pdev->dev;
455
456 if (IS_ERR(bsp_priv->grf)) {
457 dev_err(dev, "Missing rockchip,grf property\n");
458 return;
459 }
460
461 if (speed == 10)
462 regmap_write(bsp_priv->grf, RK3288_GRF_SOC_CON1,
463 RK3288_GMAC_CLK_2_5M);
464 else if (speed == 100)
465 regmap_write(bsp_priv->grf, RK3288_GRF_SOC_CON1,
466 RK3288_GMAC_CLK_25M);
467 else if (speed == 1000)
468 regmap_write(bsp_priv->grf, RK3288_GRF_SOC_CON1,
469 RK3288_GMAC_CLK_125M);
470 else
471 dev_err(dev, "unknown speed value for RGMII! speed=%d", speed);
472 }
473
rk3288_set_rmii_speed(struct rk_priv_data * bsp_priv,int speed)474 static void rk3288_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed)
475 {
476 struct device *dev = &bsp_priv->pdev->dev;
477
478 if (IS_ERR(bsp_priv->grf)) {
479 dev_err(dev, "Missing rockchip,grf property\n");
480 return;
481 }
482
483 if (speed == 10) {
484 regmap_write(bsp_priv->grf, RK3288_GRF_SOC_CON1,
485 RK3288_GMAC_RMII_CLK_2_5M |
486 RK3288_GMAC_SPEED_10M);
487 } else if (speed == 100) {
488 regmap_write(bsp_priv->grf, RK3288_GRF_SOC_CON1,
489 RK3288_GMAC_RMII_CLK_25M |
490 RK3288_GMAC_SPEED_100M);
491 } else {
492 dev_err(dev, "unknown speed value for RMII! speed=%d", speed);
493 }
494 }
495
496 static const struct rk_gmac_ops rk3288_ops = {
497 .set_to_rgmii = rk3288_set_to_rgmii,
498 .set_to_rmii = rk3288_set_to_rmii,
499 .set_rgmii_speed = rk3288_set_rgmii_speed,
500 .set_rmii_speed = rk3288_set_rmii_speed,
501 };
502
503 #define RK3308_GRF_MAC_CON0 0x04a0
504
505 /* RK3308_GRF_MAC_CON0 */
506 #define RK3308_GMAC_PHY_INTF_SEL_RMII (GRF_CLR_BIT(2) | GRF_CLR_BIT(3) | \
507 GRF_BIT(4))
508 #define RK3308_GMAC_FLOW_CTRL GRF_BIT(3)
509 #define RK3308_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(3)
510 #define RK3308_GMAC_SPEED_10M GRF_CLR_BIT(0)
511 #define RK3308_GMAC_SPEED_100M GRF_BIT(0)
512
rk3308_set_to_rmii(struct rk_priv_data * bsp_priv)513 static void rk3308_set_to_rmii(struct rk_priv_data *bsp_priv)
514 {
515 struct device *dev = &bsp_priv->pdev->dev;
516
517 if (IS_ERR(bsp_priv->grf)) {
518 dev_err(dev, "Missing rockchip,grf property\n");
519 return;
520 }
521
522 regmap_write(bsp_priv->grf, RK3308_GRF_MAC_CON0,
523 RK3308_GMAC_PHY_INTF_SEL_RMII);
524 }
525
rk3308_set_rmii_speed(struct rk_priv_data * bsp_priv,int speed)526 static void rk3308_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed)
527 {
528 struct device *dev = &bsp_priv->pdev->dev;
529
530 if (IS_ERR(bsp_priv->grf)) {
531 dev_err(dev, "Missing rockchip,grf property\n");
532 return;
533 }
534
535 if (speed == 10) {
536 regmap_write(bsp_priv->grf, RK3308_GRF_MAC_CON0,
537 RK3308_GMAC_SPEED_10M);
538 } else if (speed == 100) {
539 regmap_write(bsp_priv->grf, RK3308_GRF_MAC_CON0,
540 RK3308_GMAC_SPEED_100M);
541 } else {
542 dev_err(dev, "unknown speed value for RMII! speed=%d", speed);
543 }
544 }
545
546 static const struct rk_gmac_ops rk3308_ops = {
547 .set_to_rmii = rk3308_set_to_rmii,
548 .set_rmii_speed = rk3308_set_rmii_speed,
549 };
550
551 #define RK3328_GRF_MAC_CON0 0x0900
552 #define RK3328_GRF_MAC_CON1 0x0904
553 #define RK3328_GRF_MAC_CON2 0x0908
554 #define RK3328_GRF_MACPHY_CON1 0xb04
555
556 /* RK3328_GRF_MAC_CON0 */
557 #define RK3328_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 7)
558 #define RK3328_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 0)
559
560 /* RK3328_GRF_MAC_CON1 */
561 #define RK3328_GMAC_PHY_INTF_SEL_RGMII \
562 (GRF_BIT(4) | GRF_CLR_BIT(5) | GRF_CLR_BIT(6))
563 #define RK3328_GMAC_PHY_INTF_SEL_RMII \
564 (GRF_CLR_BIT(4) | GRF_CLR_BIT(5) | GRF_BIT(6))
565 #define RK3328_GMAC_FLOW_CTRL GRF_BIT(3)
566 #define RK3328_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(3)
567 #define RK3328_GMAC_SPEED_10M GRF_CLR_BIT(2)
568 #define RK3328_GMAC_SPEED_100M GRF_BIT(2)
569 #define RK3328_GMAC_RMII_CLK_25M GRF_BIT(7)
570 #define RK3328_GMAC_RMII_CLK_2_5M GRF_CLR_BIT(7)
571 #define RK3328_GMAC_CLK_125M (GRF_CLR_BIT(11) | GRF_CLR_BIT(12))
572 #define RK3328_GMAC_CLK_25M (GRF_BIT(11) | GRF_BIT(12))
573 #define RK3328_GMAC_CLK_2_5M (GRF_CLR_BIT(11) | GRF_BIT(12))
574 #define RK3328_GMAC_RMII_MODE GRF_BIT(9)
575 #define RK3328_GMAC_RMII_MODE_CLR GRF_CLR_BIT(9)
576 #define RK3328_GMAC_TXCLK_DLY_ENABLE GRF_BIT(0)
577 #define RK3328_GMAC_TXCLK_DLY_DISABLE GRF_CLR_BIT(0)
578 #define RK3328_GMAC_RXCLK_DLY_ENABLE GRF_BIT(1)
579 #define RK3328_GMAC_RXCLK_DLY_DISABLE GRF_CLR_BIT(0)
580
581 /* RK3328_GRF_MACPHY_CON1 */
582 #define RK3328_MACPHY_RMII_MODE GRF_BIT(9)
583
rk3328_set_to_rgmii(struct rk_priv_data * bsp_priv,int tx_delay,int rx_delay)584 static void rk3328_set_to_rgmii(struct rk_priv_data *bsp_priv,
585 int tx_delay, int rx_delay)
586 {
587 struct device *dev = &bsp_priv->pdev->dev;
588
589 if (IS_ERR(bsp_priv->grf)) {
590 dev_err(dev, "Missing rockchip,grf property\n");
591 return;
592 }
593
594 regmap_write(bsp_priv->grf, RK3328_GRF_MAC_CON1,
595 RK3328_GMAC_PHY_INTF_SEL_RGMII |
596 RK3328_GMAC_RMII_MODE_CLR |
597 RK3328_GMAC_RXCLK_DLY_ENABLE |
598 RK3328_GMAC_TXCLK_DLY_ENABLE);
599
600 regmap_write(bsp_priv->grf, RK3328_GRF_MAC_CON0,
601 RK3328_GMAC_CLK_RX_DL_CFG(rx_delay) |
602 RK3328_GMAC_CLK_TX_DL_CFG(tx_delay));
603 }
604
rk3328_set_to_rmii(struct rk_priv_data * bsp_priv)605 static void rk3328_set_to_rmii(struct rk_priv_data *bsp_priv)
606 {
607 struct device *dev = &bsp_priv->pdev->dev;
608 unsigned int reg;
609
610 if (IS_ERR(bsp_priv->grf)) {
611 dev_err(dev, "Missing rockchip,grf property\n");
612 return;
613 }
614
615 reg = bsp_priv->integrated_phy ? RK3328_GRF_MAC_CON2 :
616 RK3328_GRF_MAC_CON1;
617
618 regmap_write(bsp_priv->grf, reg,
619 RK3328_GMAC_PHY_INTF_SEL_RMII |
620 RK3328_GMAC_RMII_MODE);
621 }
622
rk3328_set_rgmii_speed(struct rk_priv_data * bsp_priv,int speed)623 static void rk3328_set_rgmii_speed(struct rk_priv_data *bsp_priv, int speed)
624 {
625 struct device *dev = &bsp_priv->pdev->dev;
626
627 if (IS_ERR(bsp_priv->grf)) {
628 dev_err(dev, "Missing rockchip,grf property\n");
629 return;
630 }
631
632 if (speed == 10)
633 regmap_write(bsp_priv->grf, RK3328_GRF_MAC_CON1,
634 RK3328_GMAC_CLK_2_5M);
635 else if (speed == 100)
636 regmap_write(bsp_priv->grf, RK3328_GRF_MAC_CON1,
637 RK3328_GMAC_CLK_25M);
638 else if (speed == 1000)
639 regmap_write(bsp_priv->grf, RK3328_GRF_MAC_CON1,
640 RK3328_GMAC_CLK_125M);
641 else
642 dev_err(dev, "unknown speed value for RGMII! speed=%d", speed);
643 }
644
rk3328_set_rmii_speed(struct rk_priv_data * bsp_priv,int speed)645 static void rk3328_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed)
646 {
647 struct device *dev = &bsp_priv->pdev->dev;
648 unsigned int reg;
649
650 if (IS_ERR(bsp_priv->grf)) {
651 dev_err(dev, "Missing rockchip,grf property\n");
652 return;
653 }
654
655 reg = bsp_priv->integrated_phy ? RK3328_GRF_MAC_CON2 :
656 RK3328_GRF_MAC_CON1;
657
658 if (speed == 10)
659 regmap_write(bsp_priv->grf, reg,
660 RK3328_GMAC_RMII_CLK_2_5M |
661 RK3328_GMAC_SPEED_10M);
662 else if (speed == 100)
663 regmap_write(bsp_priv->grf, reg,
664 RK3328_GMAC_RMII_CLK_25M |
665 RK3328_GMAC_SPEED_100M);
666 else
667 dev_err(dev, "unknown speed value for RMII! speed=%d", speed);
668 }
669
rk3328_integrated_phy_powerup(struct rk_priv_data * priv)670 static void rk3328_integrated_phy_powerup(struct rk_priv_data *priv)
671 {
672 regmap_write(priv->grf, RK3328_GRF_MACPHY_CON1,
673 RK3328_MACPHY_RMII_MODE);
674 }
675
676 static const struct rk_gmac_ops rk3328_ops = {
677 .set_to_rgmii = rk3328_set_to_rgmii,
678 .set_to_rmii = rk3328_set_to_rmii,
679 .set_rgmii_speed = rk3328_set_rgmii_speed,
680 .set_rmii_speed = rk3328_set_rmii_speed,
681 .integrated_phy_powerup = rk3328_integrated_phy_powerup,
682 };
683
684 #define RK3366_GRF_SOC_CON6 0x0418
685 #define RK3366_GRF_SOC_CON7 0x041c
686
687 /* RK3366_GRF_SOC_CON6 */
688 #define RK3366_GMAC_PHY_INTF_SEL_RGMII (GRF_BIT(9) | GRF_CLR_BIT(10) | \
689 GRF_CLR_BIT(11))
690 #define RK3366_GMAC_PHY_INTF_SEL_RMII (GRF_CLR_BIT(9) | GRF_CLR_BIT(10) | \
691 GRF_BIT(11))
692 #define RK3366_GMAC_FLOW_CTRL GRF_BIT(8)
693 #define RK3366_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(8)
694 #define RK3366_GMAC_SPEED_10M GRF_CLR_BIT(7)
695 #define RK3366_GMAC_SPEED_100M GRF_BIT(7)
696 #define RK3366_GMAC_RMII_CLK_25M GRF_BIT(3)
697 #define RK3366_GMAC_RMII_CLK_2_5M GRF_CLR_BIT(3)
698 #define RK3366_GMAC_CLK_125M (GRF_CLR_BIT(4) | GRF_CLR_BIT(5))
699 #define RK3366_GMAC_CLK_25M (GRF_BIT(4) | GRF_BIT(5))
700 #define RK3366_GMAC_CLK_2_5M (GRF_CLR_BIT(4) | GRF_BIT(5))
701 #define RK3366_GMAC_RMII_MODE GRF_BIT(6)
702 #define RK3366_GMAC_RMII_MODE_CLR GRF_CLR_BIT(6)
703
704 /* RK3366_GRF_SOC_CON7 */
705 #define RK3366_GMAC_TXCLK_DLY_ENABLE GRF_BIT(7)
706 #define RK3366_GMAC_TXCLK_DLY_DISABLE GRF_CLR_BIT(7)
707 #define RK3366_GMAC_RXCLK_DLY_ENABLE GRF_BIT(15)
708 #define RK3366_GMAC_RXCLK_DLY_DISABLE GRF_CLR_BIT(15)
709 #define RK3366_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 8)
710 #define RK3366_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 0)
711
rk3366_set_to_rgmii(struct rk_priv_data * bsp_priv,int tx_delay,int rx_delay)712 static void rk3366_set_to_rgmii(struct rk_priv_data *bsp_priv,
713 int tx_delay, int rx_delay)
714 {
715 struct device *dev = &bsp_priv->pdev->dev;
716
717 if (IS_ERR(bsp_priv->grf)) {
718 dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
719 return;
720 }
721
722 regmap_write(bsp_priv->grf, RK3366_GRF_SOC_CON6,
723 RK3366_GMAC_PHY_INTF_SEL_RGMII |
724 RK3366_GMAC_RMII_MODE_CLR);
725 regmap_write(bsp_priv->grf, RK3366_GRF_SOC_CON7,
726 DELAY_ENABLE(RK3366, tx_delay, rx_delay) |
727 RK3366_GMAC_CLK_RX_DL_CFG(rx_delay) |
728 RK3366_GMAC_CLK_TX_DL_CFG(tx_delay));
729 }
730
rk3366_set_to_rmii(struct rk_priv_data * bsp_priv)731 static void rk3366_set_to_rmii(struct rk_priv_data *bsp_priv)
732 {
733 struct device *dev = &bsp_priv->pdev->dev;
734
735 if (IS_ERR(bsp_priv->grf)) {
736 dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
737 return;
738 }
739
740 regmap_write(bsp_priv->grf, RK3366_GRF_SOC_CON6,
741 RK3366_GMAC_PHY_INTF_SEL_RMII | RK3366_GMAC_RMII_MODE);
742 }
743
rk3366_set_rgmii_speed(struct rk_priv_data * bsp_priv,int speed)744 static void rk3366_set_rgmii_speed(struct rk_priv_data *bsp_priv, int speed)
745 {
746 struct device *dev = &bsp_priv->pdev->dev;
747
748 if (IS_ERR(bsp_priv->grf)) {
749 dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
750 return;
751 }
752
753 if (speed == 10)
754 regmap_write(bsp_priv->grf, RK3366_GRF_SOC_CON6,
755 RK3366_GMAC_CLK_2_5M);
756 else if (speed == 100)
757 regmap_write(bsp_priv->grf, RK3366_GRF_SOC_CON6,
758 RK3366_GMAC_CLK_25M);
759 else if (speed == 1000)
760 regmap_write(bsp_priv->grf, RK3366_GRF_SOC_CON6,
761 RK3366_GMAC_CLK_125M);
762 else
763 dev_err(dev, "unknown speed value for RGMII! speed=%d", speed);
764 }
765
rk3366_set_rmii_speed(struct rk_priv_data * bsp_priv,int speed)766 static void rk3366_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed)
767 {
768 struct device *dev = &bsp_priv->pdev->dev;
769
770 if (IS_ERR(bsp_priv->grf)) {
771 dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
772 return;
773 }
774
775 if (speed == 10) {
776 regmap_write(bsp_priv->grf, RK3366_GRF_SOC_CON6,
777 RK3366_GMAC_RMII_CLK_2_5M |
778 RK3366_GMAC_SPEED_10M);
779 } else if (speed == 100) {
780 regmap_write(bsp_priv->grf, RK3366_GRF_SOC_CON6,
781 RK3366_GMAC_RMII_CLK_25M |
782 RK3366_GMAC_SPEED_100M);
783 } else {
784 dev_err(dev, "unknown speed value for RMII! speed=%d", speed);
785 }
786 }
787
788 static const struct rk_gmac_ops rk3366_ops = {
789 .set_to_rgmii = rk3366_set_to_rgmii,
790 .set_to_rmii = rk3366_set_to_rmii,
791 .set_rgmii_speed = rk3366_set_rgmii_speed,
792 .set_rmii_speed = rk3366_set_rmii_speed,
793 };
794
795 #define RK3368_GRF_SOC_CON15 0x043c
796 #define RK3368_GRF_SOC_CON16 0x0440
797
798 /* RK3368_GRF_SOC_CON15 */
799 #define RK3368_GMAC_PHY_INTF_SEL_RGMII (GRF_BIT(9) | GRF_CLR_BIT(10) | \
800 GRF_CLR_BIT(11))
801 #define RK3368_GMAC_PHY_INTF_SEL_RMII (GRF_CLR_BIT(9) | GRF_CLR_BIT(10) | \
802 GRF_BIT(11))
803 #define RK3368_GMAC_FLOW_CTRL GRF_BIT(8)
804 #define RK3368_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(8)
805 #define RK3368_GMAC_SPEED_10M GRF_CLR_BIT(7)
806 #define RK3368_GMAC_SPEED_100M GRF_BIT(7)
807 #define RK3368_GMAC_RMII_CLK_25M GRF_BIT(3)
808 #define RK3368_GMAC_RMII_CLK_2_5M GRF_CLR_BIT(3)
809 #define RK3368_GMAC_CLK_125M (GRF_CLR_BIT(4) | GRF_CLR_BIT(5))
810 #define RK3368_GMAC_CLK_25M (GRF_BIT(4) | GRF_BIT(5))
811 #define RK3368_GMAC_CLK_2_5M (GRF_CLR_BIT(4) | GRF_BIT(5))
812 #define RK3368_GMAC_RMII_MODE GRF_BIT(6)
813 #define RK3368_GMAC_RMII_MODE_CLR GRF_CLR_BIT(6)
814
815 /* RK3368_GRF_SOC_CON16 */
816 #define RK3368_GMAC_TXCLK_DLY_ENABLE GRF_BIT(7)
817 #define RK3368_GMAC_TXCLK_DLY_DISABLE GRF_CLR_BIT(7)
818 #define RK3368_GMAC_RXCLK_DLY_ENABLE GRF_BIT(15)
819 #define RK3368_GMAC_RXCLK_DLY_DISABLE GRF_CLR_BIT(15)
820 #define RK3368_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 8)
821 #define RK3368_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 0)
822
rk3368_set_to_rgmii(struct rk_priv_data * bsp_priv,int tx_delay,int rx_delay)823 static void rk3368_set_to_rgmii(struct rk_priv_data *bsp_priv,
824 int tx_delay, int rx_delay)
825 {
826 struct device *dev = &bsp_priv->pdev->dev;
827
828 if (IS_ERR(bsp_priv->grf)) {
829 dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
830 return;
831 }
832
833 regmap_write(bsp_priv->grf, RK3368_GRF_SOC_CON15,
834 RK3368_GMAC_PHY_INTF_SEL_RGMII |
835 RK3368_GMAC_RMII_MODE_CLR);
836 regmap_write(bsp_priv->grf, RK3368_GRF_SOC_CON16,
837 DELAY_ENABLE(RK3368, tx_delay, rx_delay) |
838 RK3368_GMAC_CLK_RX_DL_CFG(rx_delay) |
839 RK3368_GMAC_CLK_TX_DL_CFG(tx_delay));
840 }
841
rk3368_set_to_rmii(struct rk_priv_data * bsp_priv)842 static void rk3368_set_to_rmii(struct rk_priv_data *bsp_priv)
843 {
844 struct device *dev = &bsp_priv->pdev->dev;
845
846 if (IS_ERR(bsp_priv->grf)) {
847 dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
848 return;
849 }
850
851 regmap_write(bsp_priv->grf, RK3368_GRF_SOC_CON15,
852 RK3368_GMAC_PHY_INTF_SEL_RMII | RK3368_GMAC_RMII_MODE);
853 }
854
rk3368_set_rgmii_speed(struct rk_priv_data * bsp_priv,int speed)855 static void rk3368_set_rgmii_speed(struct rk_priv_data *bsp_priv, int speed)
856 {
857 struct device *dev = &bsp_priv->pdev->dev;
858
859 if (IS_ERR(bsp_priv->grf)) {
860 dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
861 return;
862 }
863
864 if (speed == 10)
865 regmap_write(bsp_priv->grf, RK3368_GRF_SOC_CON15,
866 RK3368_GMAC_CLK_2_5M);
867 else if (speed == 100)
868 regmap_write(bsp_priv->grf, RK3368_GRF_SOC_CON15,
869 RK3368_GMAC_CLK_25M);
870 else if (speed == 1000)
871 regmap_write(bsp_priv->grf, RK3368_GRF_SOC_CON15,
872 RK3368_GMAC_CLK_125M);
873 else
874 dev_err(dev, "unknown speed value for RGMII! speed=%d", speed);
875 }
876
rk3368_set_rmii_speed(struct rk_priv_data * bsp_priv,int speed)877 static void rk3368_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed)
878 {
879 struct device *dev = &bsp_priv->pdev->dev;
880
881 if (IS_ERR(bsp_priv->grf)) {
882 dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
883 return;
884 }
885
886 if (speed == 10) {
887 regmap_write(bsp_priv->grf, RK3368_GRF_SOC_CON15,
888 RK3368_GMAC_RMII_CLK_2_5M |
889 RK3368_GMAC_SPEED_10M);
890 } else if (speed == 100) {
891 regmap_write(bsp_priv->grf, RK3368_GRF_SOC_CON15,
892 RK3368_GMAC_RMII_CLK_25M |
893 RK3368_GMAC_SPEED_100M);
894 } else {
895 dev_err(dev, "unknown speed value for RMII! speed=%d", speed);
896 }
897 }
898
899 static const struct rk_gmac_ops rk3368_ops = {
900 .set_to_rgmii = rk3368_set_to_rgmii,
901 .set_to_rmii = rk3368_set_to_rmii,
902 .set_rgmii_speed = rk3368_set_rgmii_speed,
903 .set_rmii_speed = rk3368_set_rmii_speed,
904 };
905
906 #define RK3399_GRF_SOC_CON5 0xc214
907 #define RK3399_GRF_SOC_CON6 0xc218
908
909 /* RK3399_GRF_SOC_CON5 */
910 #define RK3399_GMAC_PHY_INTF_SEL_RGMII (GRF_BIT(9) | GRF_CLR_BIT(10) | \
911 GRF_CLR_BIT(11))
912 #define RK3399_GMAC_PHY_INTF_SEL_RMII (GRF_CLR_BIT(9) | GRF_CLR_BIT(10) | \
913 GRF_BIT(11))
914 #define RK3399_GMAC_FLOW_CTRL GRF_BIT(8)
915 #define RK3399_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(8)
916 #define RK3399_GMAC_SPEED_10M GRF_CLR_BIT(7)
917 #define RK3399_GMAC_SPEED_100M GRF_BIT(7)
918 #define RK3399_GMAC_RMII_CLK_25M GRF_BIT(3)
919 #define RK3399_GMAC_RMII_CLK_2_5M GRF_CLR_BIT(3)
920 #define RK3399_GMAC_CLK_125M (GRF_CLR_BIT(4) | GRF_CLR_BIT(5))
921 #define RK3399_GMAC_CLK_25M (GRF_BIT(4) | GRF_BIT(5))
922 #define RK3399_GMAC_CLK_2_5M (GRF_CLR_BIT(4) | GRF_BIT(5))
923 #define RK3399_GMAC_RMII_MODE GRF_BIT(6)
924 #define RK3399_GMAC_RMII_MODE_CLR GRF_CLR_BIT(6)
925
926 /* RK3399_GRF_SOC_CON6 */
927 #define RK3399_GMAC_TXCLK_DLY_ENABLE GRF_BIT(7)
928 #define RK3399_GMAC_TXCLK_DLY_DISABLE GRF_CLR_BIT(7)
929 #define RK3399_GMAC_RXCLK_DLY_ENABLE GRF_BIT(15)
930 #define RK3399_GMAC_RXCLK_DLY_DISABLE GRF_CLR_BIT(15)
931 #define RK3399_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 8)
932 #define RK3399_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 0)
933
rk3399_set_to_rgmii(struct rk_priv_data * bsp_priv,int tx_delay,int rx_delay)934 static void rk3399_set_to_rgmii(struct rk_priv_data *bsp_priv,
935 int tx_delay, int rx_delay)
936 {
937 struct device *dev = &bsp_priv->pdev->dev;
938
939 if (IS_ERR(bsp_priv->grf)) {
940 dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
941 return;
942 }
943
944 regmap_write(bsp_priv->grf, RK3399_GRF_SOC_CON5,
945 RK3399_GMAC_PHY_INTF_SEL_RGMII |
946 RK3399_GMAC_RMII_MODE_CLR);
947 regmap_write(bsp_priv->grf, RK3399_GRF_SOC_CON6,
948 DELAY_ENABLE(RK3399, tx_delay, rx_delay) |
949 RK3399_GMAC_CLK_RX_DL_CFG(rx_delay) |
950 RK3399_GMAC_CLK_TX_DL_CFG(tx_delay));
951 }
952
rk3399_set_to_rmii(struct rk_priv_data * bsp_priv)953 static void rk3399_set_to_rmii(struct rk_priv_data *bsp_priv)
954 {
955 struct device *dev = &bsp_priv->pdev->dev;
956
957 if (IS_ERR(bsp_priv->grf)) {
958 dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
959 return;
960 }
961
962 regmap_write(bsp_priv->grf, RK3399_GRF_SOC_CON5,
963 RK3399_GMAC_PHY_INTF_SEL_RMII | RK3399_GMAC_RMII_MODE);
964 }
965
rk3399_set_rgmii_speed(struct rk_priv_data * bsp_priv,int speed)966 static void rk3399_set_rgmii_speed(struct rk_priv_data *bsp_priv, int speed)
967 {
968 struct device *dev = &bsp_priv->pdev->dev;
969
970 if (IS_ERR(bsp_priv->grf)) {
971 dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
972 return;
973 }
974
975 if (speed == 10)
976 regmap_write(bsp_priv->grf, RK3399_GRF_SOC_CON5,
977 RK3399_GMAC_CLK_2_5M);
978 else if (speed == 100)
979 regmap_write(bsp_priv->grf, RK3399_GRF_SOC_CON5,
980 RK3399_GMAC_CLK_25M);
981 else if (speed == 1000)
982 regmap_write(bsp_priv->grf, RK3399_GRF_SOC_CON5,
983 RK3399_GMAC_CLK_125M);
984 else
985 dev_err(dev, "unknown speed value for RGMII! speed=%d", speed);
986 }
987
rk3399_set_rmii_speed(struct rk_priv_data * bsp_priv,int speed)988 static void rk3399_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed)
989 {
990 struct device *dev = &bsp_priv->pdev->dev;
991
992 if (IS_ERR(bsp_priv->grf)) {
993 dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
994 return;
995 }
996
997 if (speed == 10) {
998 regmap_write(bsp_priv->grf, RK3399_GRF_SOC_CON5,
999 RK3399_GMAC_RMII_CLK_2_5M |
1000 RK3399_GMAC_SPEED_10M);
1001 } else if (speed == 100) {
1002 regmap_write(bsp_priv->grf, RK3399_GRF_SOC_CON5,
1003 RK3399_GMAC_RMII_CLK_25M |
1004 RK3399_GMAC_SPEED_100M);
1005 } else {
1006 dev_err(dev, "unknown speed value for RMII! speed=%d", speed);
1007 }
1008 }
1009
1010 static const struct rk_gmac_ops rk3399_ops = {
1011 .set_to_rgmii = rk3399_set_to_rgmii,
1012 .set_to_rmii = rk3399_set_to_rmii,
1013 .set_rgmii_speed = rk3399_set_rgmii_speed,
1014 .set_rmii_speed = rk3399_set_rmii_speed,
1015 };
1016
1017 #define RK3568_GRF_GMAC0_CON0 0x0380
1018 #define RK3568_GRF_GMAC0_CON1 0x0384
1019 #define RK3568_GRF_GMAC1_CON0 0x0388
1020 #define RK3568_GRF_GMAC1_CON1 0x038c
1021
1022 /* RK3568_GRF_GMAC0_CON1 && RK3568_GRF_GMAC1_CON1 */
1023 #define RK3568_GMAC_PHY_INTF_SEL_RGMII \
1024 (GRF_BIT(4) | GRF_CLR_BIT(5) | GRF_CLR_BIT(6))
1025 #define RK3568_GMAC_PHY_INTF_SEL_RMII \
1026 (GRF_CLR_BIT(4) | GRF_CLR_BIT(5) | GRF_BIT(6))
1027 #define RK3568_GMAC_FLOW_CTRL GRF_BIT(3)
1028 #define RK3568_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(3)
1029 #define RK3568_GMAC_RXCLK_DLY_ENABLE GRF_BIT(1)
1030 #define RK3568_GMAC_RXCLK_DLY_DISABLE GRF_CLR_BIT(1)
1031 #define RK3568_GMAC_TXCLK_DLY_ENABLE GRF_BIT(0)
1032 #define RK3568_GMAC_TXCLK_DLY_DISABLE GRF_CLR_BIT(0)
1033
1034 /* RK3568_GRF_GMAC0_CON0 && RK3568_GRF_GMAC1_CON0 */
1035 #define RK3568_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 8)
1036 #define RK3568_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 0)
1037
rk3568_set_to_rgmii(struct rk_priv_data * bsp_priv,int tx_delay,int rx_delay)1038 static void rk3568_set_to_rgmii(struct rk_priv_data *bsp_priv,
1039 int tx_delay, int rx_delay)
1040 {
1041 struct device *dev = &bsp_priv->pdev->dev;
1042 u32 con0, con1;
1043
1044 if (IS_ERR(bsp_priv->grf)) {
1045 dev_err(dev, "Missing rockchip,grf property\n");
1046 return;
1047 }
1048
1049 con0 = (bsp_priv->id == 1) ? RK3568_GRF_GMAC1_CON0 :
1050 RK3568_GRF_GMAC0_CON0;
1051 con1 = (bsp_priv->id == 1) ? RK3568_GRF_GMAC1_CON1 :
1052 RK3568_GRF_GMAC0_CON1;
1053
1054 regmap_write(bsp_priv->grf, con0,
1055 RK3568_GMAC_CLK_RX_DL_CFG(rx_delay) |
1056 RK3568_GMAC_CLK_TX_DL_CFG(tx_delay));
1057
1058 regmap_write(bsp_priv->grf, con1,
1059 RK3568_GMAC_PHY_INTF_SEL_RGMII |
1060 RK3568_GMAC_RXCLK_DLY_ENABLE |
1061 RK3568_GMAC_TXCLK_DLY_ENABLE);
1062 }
1063
rk3568_set_to_rmii(struct rk_priv_data * bsp_priv)1064 static void rk3568_set_to_rmii(struct rk_priv_data *bsp_priv)
1065 {
1066 struct device *dev = &bsp_priv->pdev->dev;
1067 u32 con1;
1068
1069 if (IS_ERR(bsp_priv->grf)) {
1070 dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
1071 return;
1072 }
1073
1074 con1 = (bsp_priv->id == 1) ? RK3568_GRF_GMAC1_CON1 :
1075 RK3568_GRF_GMAC0_CON1;
1076 regmap_write(bsp_priv->grf, con1, RK3568_GMAC_PHY_INTF_SEL_RMII);
1077 }
1078
rk3568_set_gmac_speed(struct rk_priv_data * bsp_priv,int speed)1079 static void rk3568_set_gmac_speed(struct rk_priv_data *bsp_priv, int speed)
1080 {
1081 struct clk *clk_mac_speed = bsp_priv->clks[RK_CLK_MAC_SPEED].clk;
1082 struct device *dev = &bsp_priv->pdev->dev;
1083 unsigned long rate;
1084 int ret;
1085
1086 switch (speed) {
1087 case 10:
1088 rate = 2500000;
1089 break;
1090 case 100:
1091 rate = 25000000;
1092 break;
1093 case 1000:
1094 rate = 125000000;
1095 break;
1096 default:
1097 dev_err(dev, "unknown speed value for GMAC speed=%d", speed);
1098 return;
1099 }
1100
1101 ret = clk_set_rate(clk_mac_speed, rate);
1102 if (ret)
1103 dev_err(dev, "%s: set clk_mac_speed rate %ld failed %d\n",
1104 __func__, rate, ret);
1105 }
1106
1107 static const struct rk_gmac_ops rk3568_ops = {
1108 .set_to_rgmii = rk3568_set_to_rgmii,
1109 .set_to_rmii = rk3568_set_to_rmii,
1110 .set_rgmii_speed = rk3568_set_gmac_speed,
1111 .set_rmii_speed = rk3568_set_gmac_speed,
1112 .regs_valid = true,
1113 .regs = {
1114 0xfe2a0000, /* gmac0 */
1115 0xfe010000, /* gmac1 */
1116 0x0, /* sentinel */
1117 },
1118 };
1119
1120 /* VCCIO0_1_3_IOC */
1121 #define RK3576_VCCIO0_1_3_IOC_CON2 0X6408
1122 #define RK3576_VCCIO0_1_3_IOC_CON3 0X640c
1123 #define RK3576_VCCIO0_1_3_IOC_CON4 0X6410
1124 #define RK3576_VCCIO0_1_3_IOC_CON5 0X6414
1125
1126 #define RK3576_GMAC_RXCLK_DLY_ENABLE GRF_BIT(15)
1127 #define RK3576_GMAC_RXCLK_DLY_DISABLE GRF_CLR_BIT(15)
1128 #define RK3576_GMAC_TXCLK_DLY_ENABLE GRF_BIT(7)
1129 #define RK3576_GMAC_TXCLK_DLY_DISABLE GRF_CLR_BIT(7)
1130
1131 #define RK3576_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 8)
1132 #define RK3576_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 0)
1133
1134 /* SDGMAC_GRF */
1135 #define RK3576_GRF_GMAC_CON0 0X0020
1136 #define RK3576_GRF_GMAC_CON1 0X0024
1137
1138 #define RK3576_GMAC_RMII_MODE GRF_BIT(3)
1139 #define RK3576_GMAC_RGMII_MODE GRF_CLR_BIT(3)
1140
1141 #define RK3576_GMAC_CLK_SELECT_IO GRF_BIT(7)
1142 #define RK3576_GMAC_CLK_SELECT_CRU GRF_CLR_BIT(7)
1143
1144 #define RK3576_GMAC_CLK_RMII_DIV2 GRF_BIT(5)
1145 #define RK3576_GMAC_CLK_RMII_DIV20 GRF_CLR_BIT(5)
1146
1147 #define RK3576_GMAC_CLK_RGMII_DIV1 \
1148 (GRF_CLR_BIT(6) | GRF_CLR_BIT(5))
1149 #define RK3576_GMAC_CLK_RGMII_DIV5 \
1150 (GRF_BIT(6) | GRF_BIT(5))
1151 #define RK3576_GMAC_CLK_RGMII_DIV50 \
1152 (GRF_BIT(6) | GRF_CLR_BIT(5))
1153
1154 #define RK3576_GMAC_CLK_RMII_GATE GRF_BIT(4)
1155 #define RK3576_GMAC_CLK_RMII_NOGATE GRF_CLR_BIT(4)
1156
rk3576_set_to_rgmii(struct rk_priv_data * bsp_priv,int tx_delay,int rx_delay)1157 static void rk3576_set_to_rgmii(struct rk_priv_data *bsp_priv,
1158 int tx_delay, int rx_delay)
1159 {
1160 struct device *dev = &bsp_priv->pdev->dev;
1161 unsigned int offset_con;
1162
1163 if (IS_ERR(bsp_priv->grf) || IS_ERR(bsp_priv->php_grf)) {
1164 dev_err(dev, "Missing rockchip,grf or rockchip,php-grf property\n");
1165 return;
1166 }
1167
1168 offset_con = bsp_priv->id == 1 ? RK3576_GRF_GMAC_CON1 :
1169 RK3576_GRF_GMAC_CON0;
1170
1171 regmap_write(bsp_priv->grf, offset_con, RK3576_GMAC_RGMII_MODE);
1172
1173 offset_con = bsp_priv->id == 1 ? RK3576_VCCIO0_1_3_IOC_CON4 :
1174 RK3576_VCCIO0_1_3_IOC_CON2;
1175
1176 /* m0 && m1 delay enabled */
1177 regmap_write(bsp_priv->php_grf, offset_con,
1178 DELAY_ENABLE(RK3576, tx_delay, rx_delay));
1179 regmap_write(bsp_priv->php_grf, offset_con + 0x4,
1180 DELAY_ENABLE(RK3576, tx_delay, rx_delay));
1181
1182 /* m0 && m1 delay value */
1183 regmap_write(bsp_priv->php_grf, offset_con,
1184 RK3576_GMAC_CLK_TX_DL_CFG(tx_delay) |
1185 RK3576_GMAC_CLK_RX_DL_CFG(rx_delay));
1186 regmap_write(bsp_priv->php_grf, offset_con + 0x4,
1187 RK3576_GMAC_CLK_TX_DL_CFG(tx_delay) |
1188 RK3576_GMAC_CLK_RX_DL_CFG(rx_delay));
1189 }
1190
rk3576_set_to_rmii(struct rk_priv_data * bsp_priv)1191 static void rk3576_set_to_rmii(struct rk_priv_data *bsp_priv)
1192 {
1193 struct device *dev = &bsp_priv->pdev->dev;
1194 unsigned int offset_con;
1195
1196 if (IS_ERR(bsp_priv->grf)) {
1197 dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
1198 return;
1199 }
1200
1201 offset_con = bsp_priv->id == 1 ? RK3576_GRF_GMAC_CON1 :
1202 RK3576_GRF_GMAC_CON0;
1203
1204 regmap_write(bsp_priv->grf, offset_con, RK3576_GMAC_RMII_MODE);
1205 }
1206
rk3576_set_gmac_speed(struct rk_priv_data * bsp_priv,int speed)1207 static void rk3576_set_gmac_speed(struct rk_priv_data *bsp_priv, int speed)
1208 {
1209 struct device *dev = &bsp_priv->pdev->dev;
1210 unsigned int val = 0, offset_con;
1211
1212 switch (speed) {
1213 case 10:
1214 if (bsp_priv->phy_iface == PHY_INTERFACE_MODE_RMII)
1215 val = RK3576_GMAC_CLK_RMII_DIV20;
1216 else
1217 val = RK3576_GMAC_CLK_RGMII_DIV50;
1218 break;
1219 case 100:
1220 if (bsp_priv->phy_iface == PHY_INTERFACE_MODE_RMII)
1221 val = RK3576_GMAC_CLK_RMII_DIV2;
1222 else
1223 val = RK3576_GMAC_CLK_RGMII_DIV5;
1224 break;
1225 case 1000:
1226 if (bsp_priv->phy_iface != PHY_INTERFACE_MODE_RMII)
1227 val = RK3576_GMAC_CLK_RGMII_DIV1;
1228 else
1229 goto err;
1230 break;
1231 default:
1232 goto err;
1233 }
1234
1235 offset_con = bsp_priv->id == 1 ? RK3576_GRF_GMAC_CON1 :
1236 RK3576_GRF_GMAC_CON0;
1237
1238 regmap_write(bsp_priv->grf, offset_con, val);
1239
1240 return;
1241 err:
1242 dev_err(dev, "unknown speed value for GMAC speed=%d", speed);
1243 }
1244
rk3576_set_clock_selection(struct rk_priv_data * bsp_priv,bool input,bool enable)1245 static void rk3576_set_clock_selection(struct rk_priv_data *bsp_priv, bool input,
1246 bool enable)
1247 {
1248 unsigned int val = input ? RK3576_GMAC_CLK_SELECT_IO :
1249 RK3576_GMAC_CLK_SELECT_CRU;
1250 unsigned int offset_con;
1251
1252 val |= enable ? RK3576_GMAC_CLK_RMII_NOGATE :
1253 RK3576_GMAC_CLK_RMII_GATE;
1254
1255 offset_con = bsp_priv->id == 1 ? RK3576_GRF_GMAC_CON1 :
1256 RK3576_GRF_GMAC_CON0;
1257
1258 regmap_write(bsp_priv->grf, offset_con, val);
1259 }
1260
1261 static const struct rk_gmac_ops rk3576_ops = {
1262 .set_to_rgmii = rk3576_set_to_rgmii,
1263 .set_to_rmii = rk3576_set_to_rmii,
1264 .set_rgmii_speed = rk3576_set_gmac_speed,
1265 .set_rmii_speed = rk3576_set_gmac_speed,
1266 .set_clock_selection = rk3576_set_clock_selection,
1267 .php_grf_required = true,
1268 .regs_valid = true,
1269 .regs = {
1270 0x2a220000, /* gmac0 */
1271 0x2a230000, /* gmac1 */
1272 0x0, /* sentinel */
1273 },
1274 };
1275
1276 /* sys_grf */
1277 #define RK3588_GRF_GMAC_CON7 0X031c
1278 #define RK3588_GRF_GMAC_CON8 0X0320
1279 #define RK3588_GRF_GMAC_CON9 0X0324
1280
1281 #define RK3588_GMAC_RXCLK_DLY_ENABLE(id) GRF_BIT(2 * (id) + 3)
1282 #define RK3588_GMAC_RXCLK_DLY_DISABLE(id) GRF_CLR_BIT(2 * (id) + 3)
1283 #define RK3588_GMAC_TXCLK_DLY_ENABLE(id) GRF_BIT(2 * (id) + 2)
1284 #define RK3588_GMAC_TXCLK_DLY_DISABLE(id) GRF_CLR_BIT(2 * (id) + 2)
1285
1286 #define RK3588_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0xFF, 8)
1287 #define RK3588_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0xFF, 0)
1288
1289 /* php_grf */
1290 #define RK3588_GRF_GMAC_CON0 0X0008
1291 #define RK3588_GRF_CLK_CON1 0X0070
1292
1293 #define RK3588_GMAC_PHY_INTF_SEL_RGMII(id) \
1294 (GRF_BIT(3 + (id) * 6) | GRF_CLR_BIT(4 + (id) * 6) | GRF_CLR_BIT(5 + (id) * 6))
1295 #define RK3588_GMAC_PHY_INTF_SEL_RMII(id) \
1296 (GRF_CLR_BIT(3 + (id) * 6) | GRF_CLR_BIT(4 + (id) * 6) | GRF_BIT(5 + (id) * 6))
1297
1298 #define RK3588_GMAC_CLK_RMII_MODE(id) GRF_BIT(5 * (id))
1299 #define RK3588_GMAC_CLK_RGMII_MODE(id) GRF_CLR_BIT(5 * (id))
1300
1301 #define RK3588_GMAC_CLK_SELECT_CRU(id) GRF_BIT(5 * (id) + 4)
1302 #define RK3588_GMAC_CLK_SELECT_IO(id) GRF_CLR_BIT(5 * (id) + 4)
1303
1304 #define RK3588_GMA_CLK_RMII_DIV2(id) GRF_BIT(5 * (id) + 2)
1305 #define RK3588_GMA_CLK_RMII_DIV20(id) GRF_CLR_BIT(5 * (id) + 2)
1306
1307 #define RK3588_GMAC_CLK_RGMII_DIV1(id) \
1308 (GRF_CLR_BIT(5 * (id) + 2) | GRF_CLR_BIT(5 * (id) + 3))
1309 #define RK3588_GMAC_CLK_RGMII_DIV5(id) \
1310 (GRF_BIT(5 * (id) + 2) | GRF_BIT(5 * (id) + 3))
1311 #define RK3588_GMAC_CLK_RGMII_DIV50(id) \
1312 (GRF_CLR_BIT(5 * (id) + 2) | GRF_BIT(5 * (id) + 3))
1313
1314 #define RK3588_GMAC_CLK_RMII_GATE(id) GRF_BIT(5 * (id) + 1)
1315 #define RK3588_GMAC_CLK_RMII_NOGATE(id) GRF_CLR_BIT(5 * (id) + 1)
1316
rk3588_set_to_rgmii(struct rk_priv_data * bsp_priv,int tx_delay,int rx_delay)1317 static void rk3588_set_to_rgmii(struct rk_priv_data *bsp_priv,
1318 int tx_delay, int rx_delay)
1319 {
1320 struct device *dev = &bsp_priv->pdev->dev;
1321 u32 offset_con, id = bsp_priv->id;
1322
1323 if (IS_ERR(bsp_priv->grf) || IS_ERR(bsp_priv->php_grf)) {
1324 dev_err(dev, "Missing rockchip,grf or rockchip,php_grf property\n");
1325 return;
1326 }
1327
1328 offset_con = bsp_priv->id == 1 ? RK3588_GRF_GMAC_CON9 :
1329 RK3588_GRF_GMAC_CON8;
1330
1331 regmap_write(bsp_priv->php_grf, RK3588_GRF_GMAC_CON0,
1332 RK3588_GMAC_PHY_INTF_SEL_RGMII(id));
1333
1334 regmap_write(bsp_priv->php_grf, RK3588_GRF_CLK_CON1,
1335 RK3588_GMAC_CLK_RGMII_MODE(id));
1336
1337 regmap_write(bsp_priv->grf, RK3588_GRF_GMAC_CON7,
1338 RK3588_GMAC_RXCLK_DLY_ENABLE(id) |
1339 RK3588_GMAC_TXCLK_DLY_ENABLE(id));
1340
1341 regmap_write(bsp_priv->grf, offset_con,
1342 RK3588_GMAC_CLK_RX_DL_CFG(rx_delay) |
1343 RK3588_GMAC_CLK_TX_DL_CFG(tx_delay));
1344 }
1345
rk3588_set_to_rmii(struct rk_priv_data * bsp_priv)1346 static void rk3588_set_to_rmii(struct rk_priv_data *bsp_priv)
1347 {
1348 struct device *dev = &bsp_priv->pdev->dev;
1349
1350 if (IS_ERR(bsp_priv->php_grf)) {
1351 dev_err(dev, "%s: Missing rockchip,php_grf property\n", __func__);
1352 return;
1353 }
1354
1355 regmap_write(bsp_priv->php_grf, RK3588_GRF_GMAC_CON0,
1356 RK3588_GMAC_PHY_INTF_SEL_RMII(bsp_priv->id));
1357
1358 regmap_write(bsp_priv->php_grf, RK3588_GRF_CLK_CON1,
1359 RK3588_GMAC_CLK_RMII_MODE(bsp_priv->id));
1360 }
1361
rk3588_set_gmac_speed(struct rk_priv_data * bsp_priv,int speed)1362 static void rk3588_set_gmac_speed(struct rk_priv_data *bsp_priv, int speed)
1363 {
1364 struct device *dev = &bsp_priv->pdev->dev;
1365 unsigned int val = 0, id = bsp_priv->id;
1366
1367 switch (speed) {
1368 case 10:
1369 if (bsp_priv->phy_iface == PHY_INTERFACE_MODE_RMII)
1370 val = RK3588_GMA_CLK_RMII_DIV20(id);
1371 else
1372 val = RK3588_GMAC_CLK_RGMII_DIV50(id);
1373 break;
1374 case 100:
1375 if (bsp_priv->phy_iface == PHY_INTERFACE_MODE_RMII)
1376 val = RK3588_GMA_CLK_RMII_DIV2(id);
1377 else
1378 val = RK3588_GMAC_CLK_RGMII_DIV5(id);
1379 break;
1380 case 1000:
1381 if (bsp_priv->phy_iface != PHY_INTERFACE_MODE_RMII)
1382 val = RK3588_GMAC_CLK_RGMII_DIV1(id);
1383 else
1384 goto err;
1385 break;
1386 default:
1387 goto err;
1388 }
1389
1390 regmap_write(bsp_priv->php_grf, RK3588_GRF_CLK_CON1, val);
1391
1392 return;
1393 err:
1394 dev_err(dev, "unknown speed value for GMAC speed=%d", speed);
1395 }
1396
rk3588_set_clock_selection(struct rk_priv_data * bsp_priv,bool input,bool enable)1397 static void rk3588_set_clock_selection(struct rk_priv_data *bsp_priv, bool input,
1398 bool enable)
1399 {
1400 unsigned int val = input ? RK3588_GMAC_CLK_SELECT_IO(bsp_priv->id) :
1401 RK3588_GMAC_CLK_SELECT_CRU(bsp_priv->id);
1402
1403 val |= enable ? RK3588_GMAC_CLK_RMII_NOGATE(bsp_priv->id) :
1404 RK3588_GMAC_CLK_RMII_GATE(bsp_priv->id);
1405
1406 regmap_write(bsp_priv->php_grf, RK3588_GRF_CLK_CON1, val);
1407 }
1408
1409 static const struct rk_gmac_ops rk3588_ops = {
1410 .set_to_rgmii = rk3588_set_to_rgmii,
1411 .set_to_rmii = rk3588_set_to_rmii,
1412 .set_rgmii_speed = rk3588_set_gmac_speed,
1413 .set_rmii_speed = rk3588_set_gmac_speed,
1414 .set_clock_selection = rk3588_set_clock_selection,
1415 .php_grf_required = true,
1416 .regs_valid = true,
1417 .regs = {
1418 0xfe1b0000, /* gmac0 */
1419 0xfe1c0000, /* gmac1 */
1420 0x0, /* sentinel */
1421 },
1422 };
1423
1424 #define RV1108_GRF_GMAC_CON0 0X0900
1425
1426 /* RV1108_GRF_GMAC_CON0 */
1427 #define RV1108_GMAC_PHY_INTF_SEL_RMII (GRF_CLR_BIT(4) | GRF_CLR_BIT(5) | \
1428 GRF_BIT(6))
1429 #define RV1108_GMAC_FLOW_CTRL GRF_BIT(3)
1430 #define RV1108_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(3)
1431 #define RV1108_GMAC_SPEED_10M GRF_CLR_BIT(2)
1432 #define RV1108_GMAC_SPEED_100M GRF_BIT(2)
1433 #define RV1108_GMAC_RMII_CLK_25M GRF_BIT(7)
1434 #define RV1108_GMAC_RMII_CLK_2_5M GRF_CLR_BIT(7)
1435
rv1108_set_to_rmii(struct rk_priv_data * bsp_priv)1436 static void rv1108_set_to_rmii(struct rk_priv_data *bsp_priv)
1437 {
1438 struct device *dev = &bsp_priv->pdev->dev;
1439
1440 if (IS_ERR(bsp_priv->grf)) {
1441 dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
1442 return;
1443 }
1444
1445 regmap_write(bsp_priv->grf, RV1108_GRF_GMAC_CON0,
1446 RV1108_GMAC_PHY_INTF_SEL_RMII);
1447 }
1448
rv1108_set_rmii_speed(struct rk_priv_data * bsp_priv,int speed)1449 static void rv1108_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed)
1450 {
1451 struct device *dev = &bsp_priv->pdev->dev;
1452
1453 if (IS_ERR(bsp_priv->grf)) {
1454 dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
1455 return;
1456 }
1457
1458 if (speed == 10) {
1459 regmap_write(bsp_priv->grf, RV1108_GRF_GMAC_CON0,
1460 RV1108_GMAC_RMII_CLK_2_5M |
1461 RV1108_GMAC_SPEED_10M);
1462 } else if (speed == 100) {
1463 regmap_write(bsp_priv->grf, RV1108_GRF_GMAC_CON0,
1464 RV1108_GMAC_RMII_CLK_25M |
1465 RV1108_GMAC_SPEED_100M);
1466 } else {
1467 dev_err(dev, "unknown speed value for RMII! speed=%d", speed);
1468 }
1469 }
1470
1471 static const struct rk_gmac_ops rv1108_ops = {
1472 .set_to_rmii = rv1108_set_to_rmii,
1473 .set_rmii_speed = rv1108_set_rmii_speed,
1474 };
1475
1476 #define RV1126_GRF_GMAC_CON0 0X0070
1477 #define RV1126_GRF_GMAC_CON1 0X0074
1478 #define RV1126_GRF_GMAC_CON2 0X0078
1479
1480 /* RV1126_GRF_GMAC_CON0 */
1481 #define RV1126_GMAC_PHY_INTF_SEL_RGMII \
1482 (GRF_BIT(4) | GRF_CLR_BIT(5) | GRF_CLR_BIT(6))
1483 #define RV1126_GMAC_PHY_INTF_SEL_RMII \
1484 (GRF_CLR_BIT(4) | GRF_CLR_BIT(5) | GRF_BIT(6))
1485 #define RV1126_GMAC_FLOW_CTRL GRF_BIT(7)
1486 #define RV1126_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(7)
1487 #define RV1126_GMAC_M0_RXCLK_DLY_ENABLE GRF_BIT(1)
1488 #define RV1126_GMAC_M0_RXCLK_DLY_DISABLE GRF_CLR_BIT(1)
1489 #define RV1126_GMAC_M0_TXCLK_DLY_ENABLE GRF_BIT(0)
1490 #define RV1126_GMAC_M0_TXCLK_DLY_DISABLE GRF_CLR_BIT(0)
1491 #define RV1126_GMAC_M1_RXCLK_DLY_ENABLE GRF_BIT(3)
1492 #define RV1126_GMAC_M1_RXCLK_DLY_DISABLE GRF_CLR_BIT(3)
1493 #define RV1126_GMAC_M1_TXCLK_DLY_ENABLE GRF_BIT(2)
1494 #define RV1126_GMAC_M1_TXCLK_DLY_DISABLE GRF_CLR_BIT(2)
1495
1496 /* RV1126_GRF_GMAC_CON1 */
1497 #define RV1126_GMAC_M0_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 8)
1498 #define RV1126_GMAC_M0_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 0)
1499 /* RV1126_GRF_GMAC_CON2 */
1500 #define RV1126_GMAC_M1_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 8)
1501 #define RV1126_GMAC_M1_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 0)
1502
rv1126_set_to_rgmii(struct rk_priv_data * bsp_priv,int tx_delay,int rx_delay)1503 static void rv1126_set_to_rgmii(struct rk_priv_data *bsp_priv,
1504 int tx_delay, int rx_delay)
1505 {
1506 struct device *dev = &bsp_priv->pdev->dev;
1507
1508 if (IS_ERR(bsp_priv->grf)) {
1509 dev_err(dev, "Missing rockchip,grf property\n");
1510 return;
1511 }
1512
1513 regmap_write(bsp_priv->grf, RV1126_GRF_GMAC_CON0,
1514 RV1126_GMAC_PHY_INTF_SEL_RGMII |
1515 RV1126_GMAC_M0_RXCLK_DLY_ENABLE |
1516 RV1126_GMAC_M0_TXCLK_DLY_ENABLE |
1517 RV1126_GMAC_M1_RXCLK_DLY_ENABLE |
1518 RV1126_GMAC_M1_TXCLK_DLY_ENABLE);
1519
1520 regmap_write(bsp_priv->grf, RV1126_GRF_GMAC_CON1,
1521 RV1126_GMAC_M0_CLK_RX_DL_CFG(rx_delay) |
1522 RV1126_GMAC_M0_CLK_TX_DL_CFG(tx_delay));
1523
1524 regmap_write(bsp_priv->grf, RV1126_GRF_GMAC_CON2,
1525 RV1126_GMAC_M1_CLK_RX_DL_CFG(rx_delay) |
1526 RV1126_GMAC_M1_CLK_TX_DL_CFG(tx_delay));
1527 }
1528
rv1126_set_to_rmii(struct rk_priv_data * bsp_priv)1529 static void rv1126_set_to_rmii(struct rk_priv_data *bsp_priv)
1530 {
1531 struct device *dev = &bsp_priv->pdev->dev;
1532
1533 if (IS_ERR(bsp_priv->grf)) {
1534 dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
1535 return;
1536 }
1537
1538 regmap_write(bsp_priv->grf, RV1126_GRF_GMAC_CON0,
1539 RV1126_GMAC_PHY_INTF_SEL_RMII);
1540 }
1541
rv1126_set_rgmii_speed(struct rk_priv_data * bsp_priv,int speed)1542 static void rv1126_set_rgmii_speed(struct rk_priv_data *bsp_priv, int speed)
1543 {
1544 struct clk *clk_mac_speed = bsp_priv->clks[RK_CLK_MAC_SPEED].clk;
1545 struct device *dev = &bsp_priv->pdev->dev;
1546 unsigned long rate;
1547 int ret;
1548
1549 switch (speed) {
1550 case 10:
1551 rate = 2500000;
1552 break;
1553 case 100:
1554 rate = 25000000;
1555 break;
1556 case 1000:
1557 rate = 125000000;
1558 break;
1559 default:
1560 dev_err(dev, "unknown speed value for RGMII speed=%d", speed);
1561 return;
1562 }
1563
1564 ret = clk_set_rate(clk_mac_speed, rate);
1565 if (ret)
1566 dev_err(dev, "%s: set clk_mac_speed rate %ld failed %d\n",
1567 __func__, rate, ret);
1568 }
1569
rv1126_set_rmii_speed(struct rk_priv_data * bsp_priv,int speed)1570 static void rv1126_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed)
1571 {
1572 struct clk *clk_mac_speed = bsp_priv->clks[RK_CLK_MAC_SPEED].clk;
1573 struct device *dev = &bsp_priv->pdev->dev;
1574 unsigned long rate;
1575 int ret;
1576
1577 switch (speed) {
1578 case 10:
1579 rate = 2500000;
1580 break;
1581 case 100:
1582 rate = 25000000;
1583 break;
1584 default:
1585 dev_err(dev, "unknown speed value for RGMII speed=%d", speed);
1586 return;
1587 }
1588
1589 ret = clk_set_rate(clk_mac_speed, rate);
1590 if (ret)
1591 dev_err(dev, "%s: set clk_mac_speed rate %ld failed %d\n",
1592 __func__, rate, ret);
1593 }
1594
1595 static const struct rk_gmac_ops rv1126_ops = {
1596 .set_to_rgmii = rv1126_set_to_rgmii,
1597 .set_to_rmii = rv1126_set_to_rmii,
1598 .set_rgmii_speed = rv1126_set_rgmii_speed,
1599 .set_rmii_speed = rv1126_set_rmii_speed,
1600 };
1601
1602 #define RK_GRF_MACPHY_CON0 0xb00
1603 #define RK_GRF_MACPHY_CON1 0xb04
1604 #define RK_GRF_MACPHY_CON2 0xb08
1605 #define RK_GRF_MACPHY_CON3 0xb0c
1606
1607 #define RK_MACPHY_ENABLE GRF_BIT(0)
1608 #define RK_MACPHY_DISABLE GRF_CLR_BIT(0)
1609 #define RK_MACPHY_CFG_CLK_50M GRF_BIT(14)
1610 #define RK_GMAC2PHY_RMII_MODE (GRF_BIT(6) | GRF_CLR_BIT(7))
1611 #define RK_GRF_CON2_MACPHY_ID HIWORD_UPDATE(0x1234, 0xffff, 0)
1612 #define RK_GRF_CON3_MACPHY_ID HIWORD_UPDATE(0x35, 0x3f, 0)
1613
rk_gmac_integrated_phy_powerup(struct rk_priv_data * priv)1614 static void rk_gmac_integrated_phy_powerup(struct rk_priv_data *priv)
1615 {
1616 if (priv->ops->integrated_phy_powerup)
1617 priv->ops->integrated_phy_powerup(priv);
1618
1619 regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_MACPHY_CFG_CLK_50M);
1620 regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_GMAC2PHY_RMII_MODE);
1621
1622 regmap_write(priv->grf, RK_GRF_MACPHY_CON2, RK_GRF_CON2_MACPHY_ID);
1623 regmap_write(priv->grf, RK_GRF_MACPHY_CON3, RK_GRF_CON3_MACPHY_ID);
1624
1625 if (priv->phy_reset) {
1626 /* PHY needs to be disabled before trying to reset it */
1627 regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_MACPHY_DISABLE);
1628 if (priv->phy_reset)
1629 reset_control_assert(priv->phy_reset);
1630 usleep_range(10, 20);
1631 if (priv->phy_reset)
1632 reset_control_deassert(priv->phy_reset);
1633 usleep_range(10, 20);
1634 regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_MACPHY_ENABLE);
1635 msleep(30);
1636 }
1637 }
1638
rk_gmac_integrated_phy_powerdown(struct rk_priv_data * priv)1639 static void rk_gmac_integrated_phy_powerdown(struct rk_priv_data *priv)
1640 {
1641 regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_MACPHY_DISABLE);
1642 if (priv->phy_reset)
1643 reset_control_assert(priv->phy_reset);
1644 }
1645
rk_gmac_clk_init(struct plat_stmmacenet_data * plat)1646 static int rk_gmac_clk_init(struct plat_stmmacenet_data *plat)
1647 {
1648 struct rk_priv_data *bsp_priv = plat->bsp_priv;
1649 struct device *dev = &bsp_priv->pdev->dev;
1650 int phy_iface = bsp_priv->phy_iface;
1651 int i, j, ret;
1652
1653 bsp_priv->clk_enabled = false;
1654
1655 bsp_priv->num_clks = ARRAY_SIZE(rk_clocks);
1656 if (phy_iface == PHY_INTERFACE_MODE_RMII)
1657 bsp_priv->num_clks += ARRAY_SIZE(rk_rmii_clocks);
1658
1659 bsp_priv->clks = devm_kcalloc(dev, bsp_priv->num_clks,
1660 sizeof(*bsp_priv->clks), GFP_KERNEL);
1661 if (!bsp_priv->clks)
1662 return -ENOMEM;
1663
1664 for (i = 0; i < ARRAY_SIZE(rk_clocks); i++)
1665 bsp_priv->clks[i].id = rk_clocks[i];
1666
1667 if (phy_iface == PHY_INTERFACE_MODE_RMII) {
1668 for (j = 0; j < ARRAY_SIZE(rk_rmii_clocks); j++)
1669 bsp_priv->clks[i++].id = rk_rmii_clocks[j];
1670 }
1671
1672 ret = devm_clk_bulk_get_optional(dev, bsp_priv->num_clks,
1673 bsp_priv->clks);
1674 if (ret)
1675 return dev_err_probe(dev, ret, "Failed to get clocks\n");
1676
1677 /* "stmmaceth" will be enabled by the core */
1678 bsp_priv->clk_mac = devm_clk_get(dev, "stmmaceth");
1679 ret = PTR_ERR_OR_ZERO(bsp_priv->clk_mac);
1680 if (ret)
1681 return dev_err_probe(dev, ret, "Cannot get stmmaceth clock\n");
1682
1683 if (bsp_priv->clock_input) {
1684 dev_info(dev, "clock input from PHY\n");
1685 } else if (phy_iface == PHY_INTERFACE_MODE_RMII) {
1686 clk_set_rate(bsp_priv->clk_mac, 50000000);
1687 }
1688
1689 if (plat->phy_node && bsp_priv->integrated_phy) {
1690 bsp_priv->clk_phy = of_clk_get(plat->phy_node, 0);
1691 ret = PTR_ERR_OR_ZERO(bsp_priv->clk_phy);
1692 if (ret)
1693 return dev_err_probe(dev, ret, "Cannot get PHY clock\n");
1694 clk_set_rate(bsp_priv->clk_phy, 50000000);
1695 }
1696
1697 return 0;
1698 }
1699
gmac_clk_enable(struct rk_priv_data * bsp_priv,bool enable)1700 static int gmac_clk_enable(struct rk_priv_data *bsp_priv, bool enable)
1701 {
1702 int ret;
1703
1704 if (enable) {
1705 if (!bsp_priv->clk_enabled) {
1706 ret = clk_bulk_prepare_enable(bsp_priv->num_clks,
1707 bsp_priv->clks);
1708 if (ret)
1709 return ret;
1710
1711 ret = clk_prepare_enable(bsp_priv->clk_phy);
1712 if (ret)
1713 return ret;
1714
1715 if (bsp_priv->ops && bsp_priv->ops->set_clock_selection)
1716 bsp_priv->ops->set_clock_selection(bsp_priv,
1717 bsp_priv->clock_input, true);
1718
1719 mdelay(5);
1720 bsp_priv->clk_enabled = true;
1721 }
1722 } else {
1723 if (bsp_priv->clk_enabled) {
1724 clk_bulk_disable_unprepare(bsp_priv->num_clks,
1725 bsp_priv->clks);
1726 clk_disable_unprepare(bsp_priv->clk_phy);
1727
1728 if (bsp_priv->ops && bsp_priv->ops->set_clock_selection)
1729 bsp_priv->ops->set_clock_selection(bsp_priv,
1730 bsp_priv->clock_input, false);
1731
1732 bsp_priv->clk_enabled = false;
1733 }
1734 }
1735
1736 return 0;
1737 }
1738
phy_power_on(struct rk_priv_data * bsp_priv,bool enable)1739 static int phy_power_on(struct rk_priv_data *bsp_priv, bool enable)
1740 {
1741 struct regulator *ldo = bsp_priv->regulator;
1742 int ret;
1743 struct device *dev = &bsp_priv->pdev->dev;
1744
1745 if (enable) {
1746 ret = regulator_enable(ldo);
1747 if (ret)
1748 dev_err(dev, "fail to enable phy-supply\n");
1749 } else {
1750 ret = regulator_disable(ldo);
1751 if (ret)
1752 dev_err(dev, "fail to disable phy-supply\n");
1753 }
1754
1755 return 0;
1756 }
1757
rk_gmac_setup(struct platform_device * pdev,struct plat_stmmacenet_data * plat,const struct rk_gmac_ops * ops)1758 static struct rk_priv_data *rk_gmac_setup(struct platform_device *pdev,
1759 struct plat_stmmacenet_data *plat,
1760 const struct rk_gmac_ops *ops)
1761 {
1762 struct rk_priv_data *bsp_priv;
1763 struct device *dev = &pdev->dev;
1764 struct resource *res;
1765 int ret;
1766 const char *strings = NULL;
1767 int value;
1768
1769 bsp_priv = devm_kzalloc(dev, sizeof(*bsp_priv), GFP_KERNEL);
1770 if (!bsp_priv)
1771 return ERR_PTR(-ENOMEM);
1772
1773 of_get_phy_mode(dev->of_node, &bsp_priv->phy_iface);
1774 bsp_priv->ops = ops;
1775
1776 /* Some SoCs have multiple MAC controllers, which need
1777 * to be distinguished.
1778 */
1779 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1780 if (res && ops->regs_valid) {
1781 int i = 0;
1782
1783 while (ops->regs[i]) {
1784 if (ops->regs[i] == res->start) {
1785 bsp_priv->id = i;
1786 break;
1787 }
1788 i++;
1789 }
1790 }
1791
1792 bsp_priv->regulator = devm_regulator_get(dev, "phy");
1793 if (IS_ERR(bsp_priv->regulator)) {
1794 ret = PTR_ERR(bsp_priv->regulator);
1795 dev_err_probe(dev, ret, "failed to get phy regulator\n");
1796 return ERR_PTR(ret);
1797 }
1798
1799 ret = of_property_read_string(dev->of_node, "clock_in_out", &strings);
1800 if (ret) {
1801 dev_err(dev, "Can not read property: clock_in_out.\n");
1802 bsp_priv->clock_input = true;
1803 } else {
1804 dev_info(dev, "clock input or output? (%s).\n",
1805 strings);
1806 if (!strcmp(strings, "input"))
1807 bsp_priv->clock_input = true;
1808 else
1809 bsp_priv->clock_input = false;
1810 }
1811
1812 ret = of_property_read_u32(dev->of_node, "tx_delay", &value);
1813 if (ret) {
1814 bsp_priv->tx_delay = 0x30;
1815 dev_err(dev, "Can not read property: tx_delay.");
1816 dev_err(dev, "set tx_delay to 0x%x\n",
1817 bsp_priv->tx_delay);
1818 } else {
1819 dev_info(dev, "TX delay(0x%x).\n", value);
1820 bsp_priv->tx_delay = value;
1821 }
1822
1823 ret = of_property_read_u32(dev->of_node, "rx_delay", &value);
1824 if (ret) {
1825 bsp_priv->rx_delay = 0x10;
1826 dev_err(dev, "Can not read property: rx_delay.");
1827 dev_err(dev, "set rx_delay to 0x%x\n",
1828 bsp_priv->rx_delay);
1829 } else {
1830 dev_info(dev, "RX delay(0x%x).\n", value);
1831 bsp_priv->rx_delay = value;
1832 }
1833
1834 bsp_priv->grf = syscon_regmap_lookup_by_phandle(dev->of_node,
1835 "rockchip,grf");
1836 if (IS_ERR(bsp_priv->grf)) {
1837 dev_err_probe(dev, PTR_ERR(bsp_priv->grf),
1838 "failed to lookup rockchip,grf\n");
1839 return ERR_CAST(bsp_priv->grf);
1840 }
1841
1842 if (ops->php_grf_required) {
1843 bsp_priv->php_grf =
1844 syscon_regmap_lookup_by_phandle(dev->of_node,
1845 "rockchip,php-grf");
1846 if (IS_ERR(bsp_priv->php_grf)) {
1847 dev_err_probe(dev, PTR_ERR(bsp_priv->php_grf),
1848 "failed to lookup rockchip,php-grf\n");
1849 return ERR_CAST(bsp_priv->php_grf);
1850 }
1851 }
1852
1853 if (plat->phy_node) {
1854 bsp_priv->integrated_phy = of_property_read_bool(plat->phy_node,
1855 "phy-is-integrated");
1856 if (bsp_priv->integrated_phy) {
1857 bsp_priv->phy_reset = of_reset_control_get(plat->phy_node, NULL);
1858 if (IS_ERR(bsp_priv->phy_reset)) {
1859 dev_err(&pdev->dev, "No PHY reset control found.\n");
1860 bsp_priv->phy_reset = NULL;
1861 }
1862 }
1863 }
1864 dev_info(dev, "integrated PHY? (%s).\n",
1865 bsp_priv->integrated_phy ? "yes" : "no");
1866
1867 bsp_priv->pdev = pdev;
1868
1869 return bsp_priv;
1870 }
1871
rk_gmac_check_ops(struct rk_priv_data * bsp_priv)1872 static int rk_gmac_check_ops(struct rk_priv_data *bsp_priv)
1873 {
1874 switch (bsp_priv->phy_iface) {
1875 case PHY_INTERFACE_MODE_RGMII:
1876 case PHY_INTERFACE_MODE_RGMII_ID:
1877 case PHY_INTERFACE_MODE_RGMII_RXID:
1878 case PHY_INTERFACE_MODE_RGMII_TXID:
1879 if (!bsp_priv->ops->set_to_rgmii)
1880 return -EINVAL;
1881 break;
1882 case PHY_INTERFACE_MODE_RMII:
1883 if (!bsp_priv->ops->set_to_rmii)
1884 return -EINVAL;
1885 break;
1886 default:
1887 dev_err(&bsp_priv->pdev->dev,
1888 "unsupported interface %d", bsp_priv->phy_iface);
1889 }
1890 return 0;
1891 }
1892
rk_gmac_powerup(struct rk_priv_data * bsp_priv)1893 static int rk_gmac_powerup(struct rk_priv_data *bsp_priv)
1894 {
1895 int ret;
1896 struct device *dev = &bsp_priv->pdev->dev;
1897
1898 ret = rk_gmac_check_ops(bsp_priv);
1899 if (ret)
1900 return ret;
1901
1902 ret = gmac_clk_enable(bsp_priv, true);
1903 if (ret)
1904 return ret;
1905
1906 /*rmii or rgmii*/
1907 switch (bsp_priv->phy_iface) {
1908 case PHY_INTERFACE_MODE_RGMII:
1909 dev_info(dev, "init for RGMII\n");
1910 bsp_priv->ops->set_to_rgmii(bsp_priv, bsp_priv->tx_delay,
1911 bsp_priv->rx_delay);
1912 break;
1913 case PHY_INTERFACE_MODE_RGMII_ID:
1914 dev_info(dev, "init for RGMII_ID\n");
1915 bsp_priv->ops->set_to_rgmii(bsp_priv, 0, 0);
1916 break;
1917 case PHY_INTERFACE_MODE_RGMII_RXID:
1918 dev_info(dev, "init for RGMII_RXID\n");
1919 bsp_priv->ops->set_to_rgmii(bsp_priv, bsp_priv->tx_delay, 0);
1920 break;
1921 case PHY_INTERFACE_MODE_RGMII_TXID:
1922 dev_info(dev, "init for RGMII_TXID\n");
1923 bsp_priv->ops->set_to_rgmii(bsp_priv, 0, bsp_priv->rx_delay);
1924 break;
1925 case PHY_INTERFACE_MODE_RMII:
1926 dev_info(dev, "init for RMII\n");
1927 bsp_priv->ops->set_to_rmii(bsp_priv);
1928 break;
1929 default:
1930 dev_err(dev, "NO interface defined!\n");
1931 }
1932
1933 ret = phy_power_on(bsp_priv, true);
1934 if (ret) {
1935 gmac_clk_enable(bsp_priv, false);
1936 return ret;
1937 }
1938
1939 pm_runtime_get_sync(dev);
1940
1941 if (bsp_priv->integrated_phy)
1942 rk_gmac_integrated_phy_powerup(bsp_priv);
1943
1944 return 0;
1945 }
1946
rk_gmac_powerdown(struct rk_priv_data * gmac)1947 static void rk_gmac_powerdown(struct rk_priv_data *gmac)
1948 {
1949 if (gmac->integrated_phy)
1950 rk_gmac_integrated_phy_powerdown(gmac);
1951
1952 pm_runtime_put_sync(&gmac->pdev->dev);
1953
1954 phy_power_on(gmac, false);
1955 gmac_clk_enable(gmac, false);
1956 }
1957
rk_fix_speed(void * priv,unsigned int speed,unsigned int mode)1958 static void rk_fix_speed(void *priv, unsigned int speed, unsigned int mode)
1959 {
1960 struct rk_priv_data *bsp_priv = priv;
1961 struct device *dev = &bsp_priv->pdev->dev;
1962
1963 switch (bsp_priv->phy_iface) {
1964 case PHY_INTERFACE_MODE_RGMII:
1965 case PHY_INTERFACE_MODE_RGMII_ID:
1966 case PHY_INTERFACE_MODE_RGMII_RXID:
1967 case PHY_INTERFACE_MODE_RGMII_TXID:
1968 if (bsp_priv->ops->set_rgmii_speed)
1969 bsp_priv->ops->set_rgmii_speed(bsp_priv, speed);
1970 break;
1971 case PHY_INTERFACE_MODE_RMII:
1972 if (bsp_priv->ops->set_rmii_speed)
1973 bsp_priv->ops->set_rmii_speed(bsp_priv, speed);
1974 break;
1975 default:
1976 dev_err(dev, "unsupported interface %d", bsp_priv->phy_iface);
1977 }
1978 }
1979
rk_gmac_probe(struct platform_device * pdev)1980 static int rk_gmac_probe(struct platform_device *pdev)
1981 {
1982 struct plat_stmmacenet_data *plat_dat;
1983 struct stmmac_resources stmmac_res;
1984 const struct rk_gmac_ops *data;
1985 int ret;
1986
1987 data = of_device_get_match_data(&pdev->dev);
1988 if (!data) {
1989 dev_err(&pdev->dev, "no of match data provided\n");
1990 return -EINVAL;
1991 }
1992
1993 ret = stmmac_get_platform_resources(pdev, &stmmac_res);
1994 if (ret)
1995 return ret;
1996
1997 plat_dat = devm_stmmac_probe_config_dt(pdev, stmmac_res.mac);
1998 if (IS_ERR(plat_dat))
1999 return PTR_ERR(plat_dat);
2000
2001 /* If the stmmac is not already selected as gmac4,
2002 * then make sure we fallback to gmac.
2003 */
2004 if (!plat_dat->has_gmac4)
2005 plat_dat->has_gmac = true;
2006 plat_dat->fix_mac_speed = rk_fix_speed;
2007
2008 plat_dat->bsp_priv = rk_gmac_setup(pdev, plat_dat, data);
2009 if (IS_ERR(plat_dat->bsp_priv))
2010 return PTR_ERR(plat_dat->bsp_priv);
2011
2012 ret = rk_gmac_clk_init(plat_dat);
2013 if (ret)
2014 return ret;
2015
2016 ret = rk_gmac_powerup(plat_dat->bsp_priv);
2017 if (ret)
2018 return ret;
2019
2020 ret = stmmac_dvr_probe(&pdev->dev, plat_dat, &stmmac_res);
2021 if (ret)
2022 goto err_gmac_powerdown;
2023
2024 return 0;
2025
2026 err_gmac_powerdown:
2027 rk_gmac_powerdown(plat_dat->bsp_priv);
2028
2029 return ret;
2030 }
2031
rk_gmac_remove(struct platform_device * pdev)2032 static void rk_gmac_remove(struct platform_device *pdev)
2033 {
2034 struct rk_priv_data *bsp_priv = get_stmmac_bsp_priv(&pdev->dev);
2035
2036 stmmac_dvr_remove(&pdev->dev);
2037
2038 rk_gmac_powerdown(bsp_priv);
2039 }
2040
2041 #ifdef CONFIG_PM_SLEEP
rk_gmac_suspend(struct device * dev)2042 static int rk_gmac_suspend(struct device *dev)
2043 {
2044 struct rk_priv_data *bsp_priv = get_stmmac_bsp_priv(dev);
2045 int ret = stmmac_suspend(dev);
2046
2047 /* Keep the PHY up if we use Wake-on-Lan. */
2048 if (!device_may_wakeup(dev)) {
2049 rk_gmac_powerdown(bsp_priv);
2050 bsp_priv->suspended = true;
2051 }
2052
2053 return ret;
2054 }
2055
rk_gmac_resume(struct device * dev)2056 static int rk_gmac_resume(struct device *dev)
2057 {
2058 struct rk_priv_data *bsp_priv = get_stmmac_bsp_priv(dev);
2059
2060 /* The PHY was up for Wake-on-Lan. */
2061 if (bsp_priv->suspended) {
2062 rk_gmac_powerup(bsp_priv);
2063 bsp_priv->suspended = false;
2064 }
2065
2066 return stmmac_resume(dev);
2067 }
2068 #endif /* CONFIG_PM_SLEEP */
2069
2070 static SIMPLE_DEV_PM_OPS(rk_gmac_pm_ops, rk_gmac_suspend, rk_gmac_resume);
2071
2072 static const struct of_device_id rk_gmac_dwmac_match[] = {
2073 { .compatible = "rockchip,px30-gmac", .data = &px30_ops },
2074 { .compatible = "rockchip,rk3128-gmac", .data = &rk3128_ops },
2075 { .compatible = "rockchip,rk3228-gmac", .data = &rk3228_ops },
2076 { .compatible = "rockchip,rk3288-gmac", .data = &rk3288_ops },
2077 { .compatible = "rockchip,rk3308-gmac", .data = &rk3308_ops },
2078 { .compatible = "rockchip,rk3328-gmac", .data = &rk3328_ops },
2079 { .compatible = "rockchip,rk3366-gmac", .data = &rk3366_ops },
2080 { .compatible = "rockchip,rk3368-gmac", .data = &rk3368_ops },
2081 { .compatible = "rockchip,rk3399-gmac", .data = &rk3399_ops },
2082 { .compatible = "rockchip,rk3568-gmac", .data = &rk3568_ops },
2083 { .compatible = "rockchip,rk3576-gmac", .data = &rk3576_ops },
2084 { .compatible = "rockchip,rk3588-gmac", .data = &rk3588_ops },
2085 { .compatible = "rockchip,rv1108-gmac", .data = &rv1108_ops },
2086 { .compatible = "rockchip,rv1126-gmac", .data = &rv1126_ops },
2087 { }
2088 };
2089 MODULE_DEVICE_TABLE(of, rk_gmac_dwmac_match);
2090
2091 static struct platform_driver rk_gmac_dwmac_driver = {
2092 .probe = rk_gmac_probe,
2093 .remove_new = rk_gmac_remove,
2094 .driver = {
2095 .name = "rk_gmac-dwmac",
2096 .pm = &rk_gmac_pm_ops,
2097 .of_match_table = rk_gmac_dwmac_match,
2098 },
2099 };
2100 module_platform_driver(rk_gmac_dwmac_driver);
2101
2102 MODULE_AUTHOR("Chen-Zhi (Roger Chen) <roger.chen@rock-chips.com>");
2103 MODULE_DESCRIPTION("Rockchip RK3288 DWMAC specific glue layer");
2104 MODULE_LICENSE("GPL");
2105