1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Marvell 88Q2XXX automotive 100BASE-T1/1000BASE-T1 PHY driver
4 *
5 * Derived from Marvell Q222x API
6 *
7 * Copyright (C) 2024 Liebherr-Electronics and Drives GmbH
8 */
9 #include <linux/ethtool_netlink.h>
10 #include <linux/marvell_phy.h>
11 #include <linux/phy.h>
12 #include <linux/hwmon.h>
13
14 #define PHY_ID_88Q2220_REVB0 (MARVELL_PHY_ID_88Q2220 | 0x1)
15 #define PHY_ID_88Q2220_REVB1 (MARVELL_PHY_ID_88Q2220 | 0x2)
16 #define PHY_ID_88Q2220_REVB2 (MARVELL_PHY_ID_88Q2220 | 0x3)
17
18 #define MDIO_MMD_AN_MV_STAT 32769
19 #define MDIO_MMD_AN_MV_STAT_ANEG 0x0100
20 #define MDIO_MMD_AN_MV_STAT_LOCAL_RX 0x1000
21 #define MDIO_MMD_AN_MV_STAT_REMOTE_RX 0x2000
22 #define MDIO_MMD_AN_MV_STAT_LOCAL_MASTER 0x4000
23 #define MDIO_MMD_AN_MV_STAT_MS_CONF_FAULT 0x8000
24
25 #define MDIO_MMD_AN_MV_STAT2 32794
26 #define MDIO_MMD_AN_MV_STAT2_AN_RESOLVED 0x0800
27 #define MDIO_MMD_AN_MV_STAT2_100BT1 0x2000
28 #define MDIO_MMD_AN_MV_STAT2_1000BT1 0x4000
29
30 #define MDIO_MMD_PCS_MV_INT_EN 32784
31 #define MDIO_MMD_PCS_MV_INT_EN_LINK_UP 0x0040
32 #define MDIO_MMD_PCS_MV_INT_EN_LINK_DOWN 0x0080
33 #define MDIO_MMD_PCS_MV_INT_EN_100BT1 0x1000
34
35 #define MDIO_MMD_PCS_MV_GPIO_INT_STAT 32785
36 #define MDIO_MMD_PCS_MV_GPIO_INT_STAT_LINK_UP 0x0040
37 #define MDIO_MMD_PCS_MV_GPIO_INT_STAT_LINK_DOWN 0x0080
38 #define MDIO_MMD_PCS_MV_GPIO_INT_STAT_100BT1_GEN 0x1000
39
40 #define MDIO_MMD_PCS_MV_GPIO_INT_CTRL 32787
41 #define MDIO_MMD_PCS_MV_GPIO_INT_CTRL_TRI_DIS 0x0800
42
43 #define MDIO_MMD_PCS_MV_TEMP_SENSOR1 32833
44 #define MDIO_MMD_PCS_MV_TEMP_SENSOR1_RAW_INT 0x0001
45 #define MDIO_MMD_PCS_MV_TEMP_SENSOR1_INT 0x0040
46 #define MDIO_MMD_PCS_MV_TEMP_SENSOR1_INT_EN 0x0080
47
48 #define MDIO_MMD_PCS_MV_TEMP_SENSOR2 32834
49 #define MDIO_MMD_PCS_MV_TEMP_SENSOR2_DIS_MASK 0xc000
50
51 #define MDIO_MMD_PCS_MV_TEMP_SENSOR3 32835
52 #define MDIO_MMD_PCS_MV_TEMP_SENSOR3_INT_THRESH_MASK 0xff00
53 #define MDIO_MMD_PCS_MV_TEMP_SENSOR3_MASK 0x00ff
54
55 #define MDIO_MMD_PCS_MV_100BT1_STAT1 33032
56 #define MDIO_MMD_PCS_MV_100BT1_STAT1_IDLE_ERROR 0x00ff
57 #define MDIO_MMD_PCS_MV_100BT1_STAT1_JABBER 0x0100
58 #define MDIO_MMD_PCS_MV_100BT1_STAT1_LINK 0x0200
59 #define MDIO_MMD_PCS_MV_100BT1_STAT1_LOCAL_RX 0x1000
60 #define MDIO_MMD_PCS_MV_100BT1_STAT1_REMOTE_RX 0x2000
61 #define MDIO_MMD_PCS_MV_100BT1_STAT1_LOCAL_MASTER 0x4000
62
63 #define MDIO_MMD_PCS_MV_100BT1_STAT2 33033
64 #define MDIO_MMD_PCS_MV_100BT1_STAT2_JABBER 0x0001
65 #define MDIO_MMD_PCS_MV_100BT1_STAT2_POL 0x0002
66 #define MDIO_MMD_PCS_MV_100BT1_STAT2_LINK 0x0004
67 #define MDIO_MMD_PCS_MV_100BT1_STAT2_ANGE 0x0008
68
69 #define MDIO_MMD_PCS_MV_100BT1_INT_EN 33042
70 #define MDIO_MMD_PCS_MV_100BT1_INT_EN_LINKEVENT 0x0400
71
72 #define MDIO_MMD_PCS_MV_COPPER_INT_STAT 33043
73 #define MDIO_MMD_PCS_MV_COPPER_INT_STAT_LINKEVENT 0x0400
74
75 #define MDIO_MMD_PCS_MV_RX_STAT 33328
76
77 #define MDIO_MMD_PCS_MV_TDR_RESET 65226
78 #define MDIO_MMD_PCS_MV_TDR_RESET_TDR_RST 0x1000
79
80 #define MDIO_MMD_PCS_MV_TDR_OFF_SHORT_CABLE 65241
81
82 #define MDIO_MMD_PCS_MV_TDR_OFF_LONG_CABLE 65242
83
84 #define MDIO_MMD_PCS_MV_TDR_STATUS 65245
85 #define MDIO_MMD_PCS_MV_TDR_STATUS_MASK 0x0003
86 #define MDIO_MMD_PCS_MV_TDR_STATUS_OFF 0x0001
87 #define MDIO_MMD_PCS_MV_TDR_STATUS_ON 0x0002
88 #define MDIO_MMD_PCS_MV_TDR_STATUS_DIST_MASK 0xff00
89 #define MDIO_MMD_PCS_MV_TDR_STATUS_VCT_STAT_MASK 0x00f0
90 #define MDIO_MMD_PCS_MV_TDR_STATUS_VCT_STAT_SHORT 0x0030
91 #define MDIO_MMD_PCS_MV_TDR_STATUS_VCT_STAT_OPEN 0x00e0
92 #define MDIO_MMD_PCS_MV_TDR_STATUS_VCT_STAT_OK 0x0070
93 #define MDIO_MMD_PCS_MV_TDR_STATUS_VCT_STAT_IN_PROGR 0x0080
94 #define MDIO_MMD_PCS_MV_TDR_STATUS_VCT_STAT_NOISE 0x0050
95
96 #define MDIO_MMD_PCS_MV_TDR_OFF_CUTOFF 65246
97
98 struct mv88q2xxx_priv {
99 bool enable_temp;
100 };
101
102 struct mmd_val {
103 int devad;
104 u32 regnum;
105 u16 val;
106 };
107
108 static const struct mmd_val mv88q222x_revb0_init_seq0[] = {
109 { MDIO_MMD_PCS, 0x8033, 0x6801 },
110 { MDIO_MMD_AN, MDIO_AN_T1_CTRL, 0x0 },
111 { MDIO_MMD_PMAPMD, MDIO_CTRL1,
112 MDIO_CTRL1_LPOWER | MDIO_PMA_CTRL1_SPEED1000 },
113 { MDIO_MMD_PCS, 0xfe1b, 0x48 },
114 { MDIO_MMD_PCS, 0xffe4, 0x6b6 },
115 { MDIO_MMD_PMAPMD, MDIO_CTRL1, 0x0 },
116 { MDIO_MMD_PCS, MDIO_CTRL1, 0x0 },
117 };
118
119 static const struct mmd_val mv88q222x_revb0_init_seq1[] = {
120 { MDIO_MMD_PCS, 0xfe79, 0x0 },
121 { MDIO_MMD_PCS, 0xfe07, 0x125a },
122 { MDIO_MMD_PCS, 0xfe09, 0x1288 },
123 { MDIO_MMD_PCS, 0xfe08, 0x2588 },
124 { MDIO_MMD_PCS, 0xfe11, 0x1105 },
125 { MDIO_MMD_PCS, 0xfe72, 0x042c },
126 { MDIO_MMD_PCS, 0xfbba, 0xcb2 },
127 { MDIO_MMD_PCS, 0xfbbb, 0xc4a },
128 { MDIO_MMD_AN, 0x8032, 0x2020 },
129 { MDIO_MMD_AN, 0x8031, 0xa28 },
130 { MDIO_MMD_AN, 0x8031, 0xc28 },
131 { MDIO_MMD_PCS, 0xffdb, 0xfc10 },
132 { MDIO_MMD_PCS, 0xfe1b, 0x58 },
133 { MDIO_MMD_PCS, 0xfe79, 0x4 },
134 { MDIO_MMD_PCS, 0xfe5f, 0xe8 },
135 { MDIO_MMD_PCS, 0xfe05, 0x755c },
136 };
137
138 static const struct mmd_val mv88q222x_revb1_init_seq0[] = {
139 { MDIO_MMD_PCS, 0xffe4, 0x0007 },
140 { MDIO_MMD_AN, MDIO_AN_T1_CTRL, 0x0 },
141 { MDIO_MMD_PCS, 0xffe3, 0x7000 },
142 { MDIO_MMD_PMAPMD, MDIO_CTRL1, 0x0840 },
143 };
144
145 static const struct mmd_val mv88q222x_revb2_init_seq0[] = {
146 { MDIO_MMD_PCS, 0xffe4, 0x0007 },
147 { MDIO_MMD_AN, MDIO_AN_T1_CTRL, 0x0 },
148 { MDIO_MMD_PMAPMD, MDIO_CTRL1, 0x0840 },
149 };
150
151 static const struct mmd_val mv88q222x_revb1_revb2_init_seq1[] = {
152 { MDIO_MMD_PCS, 0xfe07, 0x125a },
153 { MDIO_MMD_PCS, 0xfe09, 0x1288 },
154 { MDIO_MMD_PCS, 0xfe08, 0x2588 },
155 { MDIO_MMD_PCS, 0xfe72, 0x042c },
156 { MDIO_MMD_PCS, 0xffe4, 0x0071 },
157 { MDIO_MMD_PCS, 0xffe4, 0x0001 },
158 { MDIO_MMD_PCS, 0xfe1b, 0x0048 },
159 { MDIO_MMD_PMAPMD, 0x0000, 0x0000 },
160 { MDIO_MMD_PCS, 0x0000, 0x0000 },
161 { MDIO_MMD_PCS, 0xffdb, 0xfc10 },
162 { MDIO_MMD_PCS, 0xfe1b, 0x58 },
163 { MDIO_MMD_PCS, 0xfcad, 0x030c },
164 { MDIO_MMD_PCS, 0x8032, 0x6001 },
165 { MDIO_MMD_PCS, 0xfdff, 0x05a5 },
166 { MDIO_MMD_PCS, 0xfdec, 0xdbaf },
167 { MDIO_MMD_PCS, 0xfcab, 0x1054 },
168 { MDIO_MMD_PCS, 0xfcac, 0x1483 },
169 { MDIO_MMD_PCS, 0x8033, 0xc801 },
170 { MDIO_MMD_AN, 0x8032, 0x2020 },
171 { MDIO_MMD_AN, 0x8031, 0xa28 },
172 { MDIO_MMD_AN, 0x8031, 0xc28 },
173 { MDIO_MMD_PCS, 0xfbba, 0x0cb2 },
174 { MDIO_MMD_PCS, 0xfbbb, 0x0c4a },
175 { MDIO_MMD_PCS, 0xfe5f, 0xe8 },
176 { MDIO_MMD_PCS, 0xfe05, 0x755c },
177 { MDIO_MMD_PCS, 0xfa20, 0x002a },
178 { MDIO_MMD_PCS, 0xfe11, 0x1105 },
179 };
180
mv88q2xxx_soft_reset(struct phy_device * phydev)181 static int mv88q2xxx_soft_reset(struct phy_device *phydev)
182 {
183 int ret;
184 int val;
185
186 ret = phy_write_mmd(phydev, MDIO_MMD_PCS,
187 MDIO_PCS_1000BT1_CTRL, MDIO_PCS_1000BT1_CTRL_RESET);
188 if (ret < 0)
189 return ret;
190
191 return phy_read_mmd_poll_timeout(phydev, MDIO_MMD_PCS,
192 MDIO_PCS_1000BT1_CTRL, val,
193 !(val & MDIO_PCS_1000BT1_CTRL_RESET),
194 50000, 600000, true);
195 }
196
mv88q2xxx_read_link_gbit(struct phy_device * phydev)197 static int mv88q2xxx_read_link_gbit(struct phy_device *phydev)
198 {
199 int ret;
200 bool link = false;
201
202 /* Read vendor specific Auto-Negotiation status register to get local
203 * and remote receiver status according to software initialization
204 * guide. However, when not in polling mode the local and remote
205 * receiver status are not evaluated due to the Marvell 88Q2xxx APIs.
206 */
207 ret = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_MMD_AN_MV_STAT);
208 if (ret < 0) {
209 return ret;
210 } else if (((ret & MDIO_MMD_AN_MV_STAT_LOCAL_RX) &&
211 (ret & MDIO_MMD_AN_MV_STAT_REMOTE_RX)) ||
212 !phy_polling_mode(phydev)) {
213 /* The link state is latched low so that momentary link
214 * drops can be detected. Do not double-read the status
215 * in polling mode to detect such short link drops except
216 * the link was already down.
217 */
218 if (!phy_polling_mode(phydev) || !phydev->link) {
219 ret = phy_read_mmd(phydev, MDIO_MMD_PCS,
220 MDIO_PCS_1000BT1_STAT);
221 if (ret < 0)
222 return ret;
223 else if (ret & MDIO_PCS_1000BT1_STAT_LINK)
224 link = true;
225 }
226
227 if (!link) {
228 ret = phy_read_mmd(phydev, MDIO_MMD_PCS,
229 MDIO_PCS_1000BT1_STAT);
230 if (ret < 0)
231 return ret;
232 else if (ret & MDIO_PCS_1000BT1_STAT_LINK)
233 link = true;
234 }
235 }
236
237 phydev->link = link;
238
239 return 0;
240 }
241
mv88q2xxx_read_link_100m(struct phy_device * phydev)242 static int mv88q2xxx_read_link_100m(struct phy_device *phydev)
243 {
244 int ret;
245
246 /* The link state is latched low so that momentary link
247 * drops can be detected. Do not double-read the status
248 * in polling mode to detect such short link drops except
249 * the link was already down. In case we are not polling,
250 * we always read the realtime status.
251 */
252 if (!phy_polling_mode(phydev)) {
253 phydev->link = false;
254 ret = phy_read_mmd(phydev, MDIO_MMD_PCS,
255 MDIO_MMD_PCS_MV_100BT1_STAT2);
256 if (ret < 0)
257 return ret;
258
259 if (ret & MDIO_MMD_PCS_MV_100BT1_STAT2_LINK)
260 phydev->link = true;
261
262 return 0;
263 } else if (!phydev->link) {
264 ret = phy_read_mmd(phydev, MDIO_MMD_PCS,
265 MDIO_MMD_PCS_MV_100BT1_STAT1);
266 if (ret < 0)
267 return ret;
268 else if (ret & MDIO_MMD_PCS_MV_100BT1_STAT1_LINK)
269 goto out;
270 }
271
272 ret = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_MMD_PCS_MV_100BT1_STAT1);
273 if (ret < 0)
274 return ret;
275
276 out:
277 /* Check if we have link and if the remote and local receiver are ok */
278 if ((ret & MDIO_MMD_PCS_MV_100BT1_STAT1_LINK) &&
279 (ret & MDIO_MMD_PCS_MV_100BT1_STAT1_LOCAL_RX) &&
280 (ret & MDIO_MMD_PCS_MV_100BT1_STAT1_REMOTE_RX))
281 phydev->link = true;
282 else
283 phydev->link = false;
284
285 return 0;
286 }
287
mv88q2xxx_read_link(struct phy_device * phydev)288 static int mv88q2xxx_read_link(struct phy_device *phydev)
289 {
290 /* The 88Q2XXX PHYs do not have the PMA/PMD status register available,
291 * therefore we need to read the link status from the vendor specific
292 * registers depending on the speed.
293 */
294
295 if (phydev->speed == SPEED_1000)
296 return mv88q2xxx_read_link_gbit(phydev);
297 else if (phydev->speed == SPEED_100)
298 return mv88q2xxx_read_link_100m(phydev);
299
300 phydev->link = false;
301 return 0;
302 }
303
mv88q2xxx_read_master_slave_state(struct phy_device * phydev)304 static int mv88q2xxx_read_master_slave_state(struct phy_device *phydev)
305 {
306 int ret;
307
308 phydev->master_slave_state = MASTER_SLAVE_STATE_UNKNOWN;
309 ret = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_MMD_AN_MV_STAT);
310 if (ret < 0)
311 return ret;
312
313 if (ret & MDIO_MMD_AN_MV_STAT_LOCAL_MASTER)
314 phydev->master_slave_state = MASTER_SLAVE_STATE_MASTER;
315 else
316 phydev->master_slave_state = MASTER_SLAVE_STATE_SLAVE;
317
318 return 0;
319 }
320
mv88q2xxx_read_aneg_speed(struct phy_device * phydev)321 static int mv88q2xxx_read_aneg_speed(struct phy_device *phydev)
322 {
323 int ret;
324
325 phydev->speed = SPEED_UNKNOWN;
326 ret = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_MMD_AN_MV_STAT2);
327 if (ret < 0)
328 return ret;
329
330 if (!(ret & MDIO_MMD_AN_MV_STAT2_AN_RESOLVED))
331 return 0;
332
333 if (ret & MDIO_MMD_AN_MV_STAT2_100BT1)
334 phydev->speed = SPEED_100;
335 else if (ret & MDIO_MMD_AN_MV_STAT2_1000BT1)
336 phydev->speed = SPEED_1000;
337
338 return 0;
339 }
340
mv88q2xxx_read_status(struct phy_device * phydev)341 static int mv88q2xxx_read_status(struct phy_device *phydev)
342 {
343 int ret;
344
345 if (phydev->autoneg == AUTONEG_ENABLE) {
346 /* We have to get the negotiated speed first, otherwise we are
347 * not able to read the link.
348 */
349 ret = mv88q2xxx_read_aneg_speed(phydev);
350 if (ret < 0)
351 return ret;
352
353 ret = mv88q2xxx_read_link(phydev);
354 if (ret < 0)
355 return ret;
356
357 ret = genphy_c45_read_lpa(phydev);
358 if (ret < 0)
359 return ret;
360
361 ret = genphy_c45_baset1_read_status(phydev);
362 if (ret < 0)
363 return ret;
364
365 ret = mv88q2xxx_read_master_slave_state(phydev);
366 if (ret < 0)
367 return ret;
368
369 phy_resolve_aneg_linkmode(phydev);
370
371 return 0;
372 }
373
374 ret = mv88q2xxx_read_link(phydev);
375 if (ret < 0)
376 return ret;
377
378 return genphy_c45_read_pma(phydev);
379 }
380
mv88q2xxx_get_features(struct phy_device * phydev)381 static int mv88q2xxx_get_features(struct phy_device *phydev)
382 {
383 int ret;
384
385 ret = genphy_c45_pma_read_abilities(phydev);
386 if (ret)
387 return ret;
388
389 /* We need to read the baset1 extended abilities manually because the
390 * PHY does not signalize it has the extended abilities register
391 * available.
392 */
393 ret = genphy_c45_pma_baset1_read_abilities(phydev);
394 if (ret)
395 return ret;
396
397 /* The PHY signalizes it supports autonegotiation. Unfortunately, so
398 * far it was not possible to get a link even when following the init
399 * sequence provided by Marvell. Disable it for now until a proper
400 * workaround is found or a new PHY revision is released.
401 */
402 if (phydev->drv->phy_id == MARVELL_PHY_ID_88Q2110)
403 linkmode_clear_bit(ETHTOOL_LINK_MODE_Autoneg_BIT,
404 phydev->supported);
405
406 return 0;
407 }
408
mv88q2xxx_config_aneg(struct phy_device * phydev)409 static int mv88q2xxx_config_aneg(struct phy_device *phydev)
410 {
411 int ret;
412
413 ret = genphy_c45_config_aneg(phydev);
414 if (ret)
415 return ret;
416
417 return phydev->drv->soft_reset(phydev);
418 }
419
mv88q2xxx_config_init(struct phy_device * phydev)420 static int mv88q2xxx_config_init(struct phy_device *phydev)
421 {
422 /* The 88Q2XXX PHYs do have the extended ability register available, but
423 * register MDIO_PMA_EXTABLE where they should signalize it does not
424 * work according to specification. Therefore, we force it here.
425 */
426 phydev->pma_extable = MDIO_PMA_EXTABLE_BT1;
427
428 /* Configure interrupt with default settings, output is driven low for
429 * active interrupt and high for inactive.
430 */
431 if (phy_interrupt_is_valid(phydev))
432 return phy_set_bits_mmd(phydev, MDIO_MMD_PCS,
433 MDIO_MMD_PCS_MV_GPIO_INT_CTRL,
434 MDIO_MMD_PCS_MV_GPIO_INT_CTRL_TRI_DIS);
435
436 return 0;
437 }
438
mv88q2xxx_get_sqi(struct phy_device * phydev)439 static int mv88q2xxx_get_sqi(struct phy_device *phydev)
440 {
441 int ret;
442
443 if (phydev->speed == SPEED_100) {
444 /* Read the SQI from the vendor specific receiver status
445 * register
446 */
447 ret = phy_read_mmd(phydev, MDIO_MMD_PCS,
448 MDIO_MMD_PCS_MV_RX_STAT);
449 if (ret < 0)
450 return ret;
451
452 ret = ret >> 12;
453 } else {
454 /* Read from vendor specific registers, they are not documented
455 * but can be found in the Software Initialization Guide. Only
456 * revisions >= A0 are supported.
457 */
458 ret = phy_modify_mmd(phydev, MDIO_MMD_PCS, 0xfc5d, 0xff, 0xac);
459 if (ret < 0)
460 return ret;
461
462 ret = phy_read_mmd(phydev, MDIO_MMD_PCS, 0xfc88);
463 if (ret < 0)
464 return ret;
465 }
466
467 return ret & 0x0f;
468 }
469
mv88q2xxx_get_sqi_max(struct phy_device * phydev)470 static int mv88q2xxx_get_sqi_max(struct phy_device *phydev)
471 {
472 return 15;
473 }
474
mv88q2xxx_config_intr(struct phy_device * phydev)475 static int mv88q2xxx_config_intr(struct phy_device *phydev)
476 {
477 int ret;
478
479 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
480 /* Enable interrupts for 1000BASE-T1 link up and down events
481 * and enable general interrupts for 100BASE-T1.
482 */
483 ret = phy_write_mmd(phydev, MDIO_MMD_PCS,
484 MDIO_MMD_PCS_MV_INT_EN,
485 MDIO_MMD_PCS_MV_INT_EN_LINK_UP |
486 MDIO_MMD_PCS_MV_INT_EN_LINK_DOWN |
487 MDIO_MMD_PCS_MV_INT_EN_100BT1);
488 if (ret < 0)
489 return ret;
490
491 /* Enable interrupts for 100BASE-T1 link events */
492 return phy_write_mmd(phydev, MDIO_MMD_PCS,
493 MDIO_MMD_PCS_MV_100BT1_INT_EN,
494 MDIO_MMD_PCS_MV_100BT1_INT_EN_LINKEVENT);
495 } else {
496 ret = phy_write_mmd(phydev, MDIO_MMD_PCS,
497 MDIO_MMD_PCS_MV_INT_EN, 0);
498 if (ret < 0)
499 return ret;
500
501 return phy_write_mmd(phydev, MDIO_MMD_PCS,
502 MDIO_MMD_PCS_MV_100BT1_INT_EN, 0);
503 }
504 }
505
mv88q2xxx_handle_interrupt(struct phy_device * phydev)506 static irqreturn_t mv88q2xxx_handle_interrupt(struct phy_device *phydev)
507 {
508 bool trigger_machine = false;
509 int irq;
510
511 /* Before we can acknowledge the 100BT1 general interrupt, that is in
512 * the 1000BT1 interrupt status register, we have to acknowledge any
513 * interrupts that are related to it. Therefore we read first the 100BT1
514 * interrupt status register, followed by reading the 1000BT1 interrupt
515 * status register.
516 */
517
518 irq = phy_read_mmd(phydev, MDIO_MMD_PCS,
519 MDIO_MMD_PCS_MV_COPPER_INT_STAT);
520 if (irq < 0) {
521 phy_error(phydev);
522 return IRQ_NONE;
523 }
524
525 /* Check link status for 100BT1 */
526 if (irq & MDIO_MMD_PCS_MV_COPPER_INT_STAT_LINKEVENT)
527 trigger_machine = true;
528
529 irq = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_MMD_PCS_MV_GPIO_INT_STAT);
530 if (irq < 0) {
531 phy_error(phydev);
532 return IRQ_NONE;
533 }
534
535 /* Check link status for 1000BT1 */
536 if ((irq & MDIO_MMD_PCS_MV_GPIO_INT_STAT_LINK_UP) ||
537 (irq & MDIO_MMD_PCS_MV_GPIO_INT_STAT_LINK_DOWN))
538 trigger_machine = true;
539
540 if (!trigger_machine)
541 return IRQ_NONE;
542
543 phy_trigger_machine(phydev);
544
545 return IRQ_HANDLED;
546 }
547
mv88q2xxx_suspend(struct phy_device * phydev)548 static int mv88q2xxx_suspend(struct phy_device *phydev)
549 {
550 int ret;
551
552 /* Disable PHY interrupts */
553 if (phy_interrupt_is_valid(phydev)) {
554 phydev->interrupts = PHY_INTERRUPT_DISABLED;
555 ret = mv88q2xxx_config_intr(phydev);
556 if (ret)
557 return ret;
558 }
559
560 return phy_set_bits_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_CTRL1,
561 MDIO_CTRL1_LPOWER);
562 }
563
mv88q2xxx_resume(struct phy_device * phydev)564 static int mv88q2xxx_resume(struct phy_device *phydev)
565 {
566 int ret;
567
568 /* Enable PHY interrupts */
569 if (phy_interrupt_is_valid(phydev)) {
570 phydev->interrupts = PHY_INTERRUPT_ENABLED;
571 ret = mv88q2xxx_config_intr(phydev);
572 if (ret)
573 return ret;
574 }
575
576 return phy_clear_bits_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_CTRL1,
577 MDIO_CTRL1_LPOWER);
578 }
579
580 #if IS_ENABLED(CONFIG_HWMON)
581 static const struct hwmon_channel_info * const mv88q2xxx_hwmon_info[] = {
582 HWMON_CHANNEL_INFO(temp, HWMON_T_INPUT | HWMON_T_MAX | HWMON_T_ALARM),
583 NULL
584 };
585
mv88q2xxx_hwmon_is_visible(const void * data,enum hwmon_sensor_types type,u32 attr,int channel)586 static umode_t mv88q2xxx_hwmon_is_visible(const void *data,
587 enum hwmon_sensor_types type,
588 u32 attr, int channel)
589 {
590 switch (attr) {
591 case hwmon_temp_input:
592 return 0444;
593 case hwmon_temp_max:
594 return 0644;
595 case hwmon_temp_alarm:
596 return 0444;
597 default:
598 return 0;
599 }
600 }
601
mv88q2xxx_hwmon_read(struct device * dev,enum hwmon_sensor_types type,u32 attr,int channel,long * val)602 static int mv88q2xxx_hwmon_read(struct device *dev,
603 enum hwmon_sensor_types type,
604 u32 attr, int channel, long *val)
605 {
606 struct phy_device *phydev = dev_get_drvdata(dev);
607 int ret;
608
609 switch (attr) {
610 case hwmon_temp_input:
611 ret = phy_read_mmd(phydev, MDIO_MMD_PCS,
612 MDIO_MMD_PCS_MV_TEMP_SENSOR3);
613 if (ret < 0)
614 return ret;
615
616 ret = FIELD_GET(MDIO_MMD_PCS_MV_TEMP_SENSOR3_MASK, ret);
617 *val = (ret - 75) * 1000;
618 return 0;
619 case hwmon_temp_max:
620 ret = phy_read_mmd(phydev, MDIO_MMD_PCS,
621 MDIO_MMD_PCS_MV_TEMP_SENSOR3);
622 if (ret < 0)
623 return ret;
624
625 ret = FIELD_GET(MDIO_MMD_PCS_MV_TEMP_SENSOR3_INT_THRESH_MASK,
626 ret);
627 *val = (ret - 75) * 1000;
628 return 0;
629 case hwmon_temp_alarm:
630 ret = phy_read_mmd(phydev, MDIO_MMD_PCS,
631 MDIO_MMD_PCS_MV_TEMP_SENSOR1);
632 if (ret < 0)
633 return ret;
634
635 *val = !!(ret & MDIO_MMD_PCS_MV_TEMP_SENSOR1_RAW_INT);
636 return 0;
637 default:
638 return -EOPNOTSUPP;
639 }
640 }
641
mv88q2xxx_hwmon_write(struct device * dev,enum hwmon_sensor_types type,u32 attr,int channel,long val)642 static int mv88q2xxx_hwmon_write(struct device *dev,
643 enum hwmon_sensor_types type, u32 attr,
644 int channel, long val)
645 {
646 struct phy_device *phydev = dev_get_drvdata(dev);
647
648 switch (attr) {
649 case hwmon_temp_max:
650 clamp_val(val, -75000, 180000);
651 val = (val / 1000) + 75;
652 val = FIELD_PREP(MDIO_MMD_PCS_MV_TEMP_SENSOR3_INT_THRESH_MASK,
653 val);
654 return phy_modify_mmd(phydev, MDIO_MMD_PCS,
655 MDIO_MMD_PCS_MV_TEMP_SENSOR3,
656 MDIO_MMD_PCS_MV_TEMP_SENSOR3_INT_THRESH_MASK,
657 val);
658 default:
659 return -EOPNOTSUPP;
660 }
661 }
662
663 static const struct hwmon_ops mv88q2xxx_hwmon_hwmon_ops = {
664 .is_visible = mv88q2xxx_hwmon_is_visible,
665 .read = mv88q2xxx_hwmon_read,
666 .write = mv88q2xxx_hwmon_write,
667 };
668
669 static const struct hwmon_chip_info mv88q2xxx_hwmon_chip_info = {
670 .ops = &mv88q2xxx_hwmon_hwmon_ops,
671 .info = mv88q2xxx_hwmon_info,
672 };
673
mv88q2xxx_hwmon_probe(struct phy_device * phydev)674 static int mv88q2xxx_hwmon_probe(struct phy_device *phydev)
675 {
676 struct mv88q2xxx_priv *priv = phydev->priv;
677 struct device *dev = &phydev->mdio.dev;
678 struct device *hwmon;
679 char *hwmon_name;
680
681 priv->enable_temp = true;
682 hwmon_name = devm_hwmon_sanitize_name(dev, dev_name(dev));
683 if (IS_ERR(hwmon_name))
684 return PTR_ERR(hwmon_name);
685
686 hwmon = devm_hwmon_device_register_with_info(dev,
687 hwmon_name,
688 phydev,
689 &mv88q2xxx_hwmon_chip_info,
690 NULL);
691
692 return PTR_ERR_OR_ZERO(hwmon);
693 }
694
695 #else
mv88q2xxx_hwmon_probe(struct phy_device * phydev)696 static int mv88q2xxx_hwmon_probe(struct phy_device *phydev)
697 {
698 return 0;
699 }
700 #endif
701
mv88q2xxx_probe(struct phy_device * phydev)702 static int mv88q2xxx_probe(struct phy_device *phydev)
703 {
704 struct mv88q2xxx_priv *priv;
705
706 priv = devm_kzalloc(&phydev->mdio.dev, sizeof(*priv), GFP_KERNEL);
707 if (!priv)
708 return -ENOMEM;
709
710 phydev->priv = priv;
711
712 return mv88q2xxx_hwmon_probe(phydev);
713 }
714
mv88q222x_soft_reset(struct phy_device * phydev)715 static int mv88q222x_soft_reset(struct phy_device *phydev)
716 {
717 int ret;
718
719 /* Enable RESET of DCL */
720 if (phydev->autoneg == AUTONEG_ENABLE || phydev->speed == SPEED_1000) {
721 ret = phy_write_mmd(phydev, MDIO_MMD_PCS, 0xfe1b, 0x48);
722 if (ret < 0)
723 return ret;
724 }
725
726 ret = phy_write_mmd(phydev, MDIO_MMD_PCS, MDIO_PCS_1000BT1_CTRL,
727 MDIO_PCS_1000BT1_CTRL_RESET);
728 if (ret < 0)
729 return ret;
730
731 ret = phy_write_mmd(phydev, MDIO_MMD_PCS, 0xffe4, 0xc);
732 if (ret < 0)
733 return ret;
734
735 /* Disable RESET of DCL */
736 if (phydev->autoneg == AUTONEG_ENABLE || phydev->speed == SPEED_1000)
737 return phy_write_mmd(phydev, MDIO_MMD_PCS, 0xfe1b, 0x58);
738
739 return 0;
740 }
741
mv88q222x_write_mmd_vals(struct phy_device * phydev,const struct mmd_val * vals,size_t len)742 static int mv88q222x_write_mmd_vals(struct phy_device *phydev,
743 const struct mmd_val *vals, size_t len)
744 {
745 int ret;
746
747 for (; len; vals++, len--) {
748 ret = phy_write_mmd(phydev, vals->devad, vals->regnum,
749 vals->val);
750 if (ret < 0)
751 return ret;
752 }
753
754 return 0;
755 }
756
mv88q222x_revb0_config_init(struct phy_device * phydev)757 static int mv88q222x_revb0_config_init(struct phy_device *phydev)
758 {
759 int ret;
760
761 ret = mv88q222x_write_mmd_vals(phydev, mv88q222x_revb0_init_seq0,
762 ARRAY_SIZE(mv88q222x_revb0_init_seq0));
763 if (ret < 0)
764 return ret;
765
766 usleep_range(5000, 10000);
767
768 ret = mv88q222x_write_mmd_vals(phydev, mv88q222x_revb0_init_seq1,
769 ARRAY_SIZE(mv88q222x_revb0_init_seq1));
770 if (ret < 0)
771 return ret;
772
773 return mv88q2xxx_config_init(phydev);
774 }
775
mv88q222x_revb1_revb2_config_init(struct phy_device * phydev)776 static int mv88q222x_revb1_revb2_config_init(struct phy_device *phydev)
777 {
778 bool is_rev_b1 = phydev->c45_ids.device_ids[MDIO_MMD_PMAPMD] == PHY_ID_88Q2220_REVB1;
779 int ret;
780
781 if (is_rev_b1)
782 ret = mv88q222x_write_mmd_vals(phydev, mv88q222x_revb1_init_seq0,
783 ARRAY_SIZE(mv88q222x_revb1_init_seq0));
784 else
785 ret = mv88q222x_write_mmd_vals(phydev, mv88q222x_revb2_init_seq0,
786 ARRAY_SIZE(mv88q222x_revb2_init_seq0));
787 if (ret < 0)
788 return ret;
789
790 usleep_range(3000, 5000);
791
792 ret = mv88q222x_write_mmd_vals(phydev, mv88q222x_revb1_revb2_init_seq1,
793 ARRAY_SIZE(mv88q222x_revb1_revb2_init_seq1));
794 if (ret < 0)
795 return ret;
796
797 return mv88q2xxx_config_init(phydev);
798 }
799
mv88q222x_config_init(struct phy_device * phydev)800 static int mv88q222x_config_init(struct phy_device *phydev)
801 {
802 struct mv88q2xxx_priv *priv = phydev->priv;
803 int ret;
804
805 /* Enable temperature sense */
806 if (priv->enable_temp) {
807 ret = phy_modify_mmd(phydev, MDIO_MMD_PCS,
808 MDIO_MMD_PCS_MV_TEMP_SENSOR2,
809 MDIO_MMD_PCS_MV_TEMP_SENSOR2_DIS_MASK, 0);
810 if (ret < 0)
811 return ret;
812 }
813
814 if (phydev->c45_ids.device_ids[MDIO_MMD_PMAPMD] == PHY_ID_88Q2220_REVB0)
815 return mv88q222x_revb0_config_init(phydev);
816 else
817 return mv88q222x_revb1_revb2_config_init(phydev);
818 }
819
mv88q222x_cable_test_start(struct phy_device * phydev)820 static int mv88q222x_cable_test_start(struct phy_device *phydev)
821 {
822 int ret;
823
824 ret = phy_write_mmd(phydev, MDIO_MMD_PCS,
825 MDIO_MMD_PCS_MV_TDR_OFF_CUTOFF, 0x0058);
826 if (ret < 0)
827 return ret;
828
829 ret = phy_write_mmd(phydev, MDIO_MMD_PCS,
830 MDIO_MMD_PCS_MV_TDR_OFF_LONG_CABLE, 0x00eb);
831 if (ret < 0)
832 return ret;
833
834 ret = phy_write_mmd(phydev, MDIO_MMD_PCS,
835 MDIO_MMD_PCS_MV_TDR_OFF_SHORT_CABLE, 0x010e);
836 if (ret < 0)
837 return ret;
838
839 ret = phy_write_mmd(phydev, MDIO_MMD_PCS, MDIO_MMD_PCS_MV_TDR_RESET,
840 0x0d90);
841 if (ret < 0)
842 return ret;
843
844 ret = phy_write_mmd(phydev, MDIO_MMD_PCS, MDIO_MMD_PCS_MV_TDR_STATUS,
845 MDIO_MMD_PCS_MV_TDR_STATUS_ON);
846 if (ret < 0)
847 return ret;
848
849 /* According to the Marvell API the test is finished within 500 ms */
850 msleep(500);
851
852 return 0;
853 }
854
mv88q222x_cable_test_get_status(struct phy_device * phydev,bool * finished)855 static int mv88q222x_cable_test_get_status(struct phy_device *phydev,
856 bool *finished)
857 {
858 int ret, status;
859 u32 dist;
860
861 status = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_MMD_PCS_MV_TDR_STATUS);
862 if (status < 0)
863 return status;
864
865 ret = phy_write_mmd(phydev, MDIO_MMD_PCS, MDIO_MMD_PCS_MV_TDR_RESET,
866 MDIO_MMD_PCS_MV_TDR_RESET_TDR_RST | 0xd90);
867 if (ret < 0)
868 return ret;
869
870 /* Test could not be finished */
871 if (FIELD_GET(MDIO_MMD_PCS_MV_TDR_STATUS_MASK, status) !=
872 MDIO_MMD_PCS_MV_TDR_STATUS_OFF)
873 return -ETIMEDOUT;
874
875 *finished = true;
876 /* Fault length reported in meters, convert to centimeters */
877 dist = FIELD_GET(MDIO_MMD_PCS_MV_TDR_STATUS_DIST_MASK, status) * 100;
878 switch (status & MDIO_MMD_PCS_MV_TDR_STATUS_VCT_STAT_MASK) {
879 case MDIO_MMD_PCS_MV_TDR_STATUS_VCT_STAT_OPEN:
880 ethnl_cable_test_result(phydev, ETHTOOL_A_CABLE_PAIR_A,
881 ETHTOOL_A_CABLE_RESULT_CODE_OPEN);
882 ethnl_cable_test_fault_length(phydev, ETHTOOL_A_CABLE_PAIR_A,
883 dist);
884 break;
885 case MDIO_MMD_PCS_MV_TDR_STATUS_VCT_STAT_SHORT:
886 ethnl_cable_test_result(phydev, ETHTOOL_A_CABLE_PAIR_A,
887 ETHTOOL_A_CABLE_RESULT_CODE_SAME_SHORT);
888 ethnl_cable_test_fault_length(phydev, ETHTOOL_A_CABLE_PAIR_A,
889 dist);
890 break;
891 case MDIO_MMD_PCS_MV_TDR_STATUS_VCT_STAT_OK:
892 ethnl_cable_test_result(phydev, ETHTOOL_A_CABLE_PAIR_A,
893 ETHTOOL_A_CABLE_RESULT_CODE_OK);
894 break;
895 default:
896 ethnl_cable_test_result(phydev, ETHTOOL_A_CABLE_PAIR_A,
897 ETHTOOL_A_CABLE_RESULT_CODE_UNSPEC);
898 }
899
900 return 0;
901 }
902
903 static struct phy_driver mv88q2xxx_driver[] = {
904 {
905 .phy_id = MARVELL_PHY_ID_88Q2110,
906 .phy_id_mask = MARVELL_PHY_ID_MASK,
907 .name = "mv88q2110",
908 .get_features = mv88q2xxx_get_features,
909 .config_aneg = mv88q2xxx_config_aneg,
910 .config_init = mv88q2xxx_config_init,
911 .read_status = mv88q2xxx_read_status,
912 .soft_reset = mv88q2xxx_soft_reset,
913 .set_loopback = genphy_c45_loopback,
914 .get_sqi = mv88q2xxx_get_sqi,
915 .get_sqi_max = mv88q2xxx_get_sqi_max,
916 },
917 {
918 .phy_id = MARVELL_PHY_ID_88Q2220,
919 .phy_id_mask = MARVELL_PHY_ID_MASK,
920 .name = "mv88q2220",
921 .flags = PHY_POLL_CABLE_TEST,
922 .probe = mv88q2xxx_probe,
923 .get_features = mv88q2xxx_get_features,
924 .config_aneg = mv88q2xxx_config_aneg,
925 .aneg_done = genphy_c45_aneg_done,
926 .config_init = mv88q222x_config_init,
927 .read_status = mv88q2xxx_read_status,
928 .soft_reset = mv88q222x_soft_reset,
929 .config_intr = mv88q2xxx_config_intr,
930 .handle_interrupt = mv88q2xxx_handle_interrupt,
931 .set_loopback = genphy_c45_loopback,
932 .cable_test_start = mv88q222x_cable_test_start,
933 .cable_test_get_status = mv88q222x_cable_test_get_status,
934 .get_sqi = mv88q2xxx_get_sqi,
935 .get_sqi_max = mv88q2xxx_get_sqi_max,
936 .suspend = mv88q2xxx_suspend,
937 .resume = mv88q2xxx_resume,
938 },
939 };
940
941 module_phy_driver(mv88q2xxx_driver);
942
943 static struct mdio_device_id __maybe_unused mv88q2xxx_tbl[] = {
944 { MARVELL_PHY_ID_88Q2110, MARVELL_PHY_ID_MASK },
945 { MARVELL_PHY_ID_88Q2220, MARVELL_PHY_ID_MASK },
946 { /*sentinel*/ }
947 };
948 MODULE_DEVICE_TABLE(mdio, mv88q2xxx_tbl);
949
950 MODULE_DESCRIPTION("Marvell 88Q2XXX 100/1000BASE-T1 Automotive Ethernet PHY driver");
951 MODULE_LICENSE("GPL");
952