1 // SPDX-License-Identifier: BSD-3-Clause-Clear
2 /*
3 * Copyright (c) 2018-2019 The Linux Foundation. All rights reserved.
4 * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved.
5 */
6
7 #include "dp_rx.h"
8 #include "debug.h"
9 #include "hif.h"
10
11 const struct ce_attr ath11k_host_ce_config_ipq8074[] = {
12 /* CE0: host->target HTC control and raw streams */
13 {
14 .flags = CE_ATTR_FLAGS,
15 .src_nentries = 16,
16 .src_sz_max = 2048,
17 .dest_nentries = 0,
18 .send_cb = ath11k_htc_tx_completion_handler,
19 },
20
21 /* CE1: target->host HTT + HTC control */
22 {
23 .flags = CE_ATTR_FLAGS,
24 .src_nentries = 0,
25 .src_sz_max = 2048,
26 .dest_nentries = 512,
27 .recv_cb = ath11k_htc_rx_completion_handler,
28 },
29
30 /* CE2: target->host WMI */
31 {
32 .flags = CE_ATTR_FLAGS,
33 .src_nentries = 0,
34 .src_sz_max = 2048,
35 .dest_nentries = 512,
36 .recv_cb = ath11k_htc_rx_completion_handler,
37 },
38
39 /* CE3: host->target WMI (mac0) */
40 {
41 .flags = CE_ATTR_FLAGS,
42 .src_nentries = 32,
43 .src_sz_max = 2048,
44 .dest_nentries = 0,
45 .send_cb = ath11k_htc_tx_completion_handler,
46 },
47
48 /* CE4: host->target HTT */
49 {
50 .flags = CE_ATTR_FLAGS | CE_ATTR_DIS_INTR,
51 .src_nentries = 2048,
52 .src_sz_max = 256,
53 .dest_nentries = 0,
54 },
55
56 /* CE5: target->host pktlog */
57 {
58 .flags = CE_ATTR_FLAGS,
59 .src_nentries = 0,
60 .src_sz_max = 2048,
61 .dest_nentries = 512,
62 .recv_cb = ath11k_dp_htt_htc_t2h_msg_handler,
63 },
64
65 /* CE6: target autonomous hif_memcpy */
66 {
67 .flags = CE_ATTR_FLAGS | CE_ATTR_DIS_INTR,
68 .src_nentries = 0,
69 .src_sz_max = 0,
70 .dest_nentries = 0,
71 },
72
73 /* CE7: host->target WMI (mac1) */
74 {
75 .flags = CE_ATTR_FLAGS,
76 .src_nentries = 32,
77 .src_sz_max = 2048,
78 .dest_nentries = 0,
79 .send_cb = ath11k_htc_tx_completion_handler,
80 },
81
82 /* CE8: target autonomous hif_memcpy */
83 {
84 .flags = CE_ATTR_FLAGS | CE_ATTR_DIS_INTR,
85 .src_nentries = 0,
86 .src_sz_max = 0,
87 .dest_nentries = 0,
88 },
89
90 /* CE9: host->target WMI (mac2) */
91 {
92 .flags = CE_ATTR_FLAGS,
93 .src_nentries = 32,
94 .src_sz_max = 2048,
95 .dest_nentries = 0,
96 .send_cb = ath11k_htc_tx_completion_handler,
97 },
98
99 /* CE10: target->host HTT */
100 {
101 .flags = CE_ATTR_FLAGS,
102 .src_nentries = 0,
103 .src_sz_max = 2048,
104 .dest_nentries = 512,
105 .recv_cb = ath11k_htc_rx_completion_handler,
106 },
107
108 /* CE11: Not used */
109 {
110 .flags = CE_ATTR_FLAGS,
111 .src_nentries = 0,
112 .src_sz_max = 0,
113 .dest_nentries = 0,
114 },
115 };
116
117 const struct ce_attr ath11k_host_ce_config_qca6390[] = {
118 /* CE0: host->target HTC control and raw streams */
119 {
120 .flags = CE_ATTR_FLAGS,
121 .src_nentries = 16,
122 .src_sz_max = 2048,
123 .dest_nentries = 0,
124 },
125
126 /* CE1: target->host HTT + HTC control */
127 {
128 .flags = CE_ATTR_FLAGS,
129 .src_nentries = 0,
130 .src_sz_max = 2048,
131 .dest_nentries = 512,
132 .recv_cb = ath11k_htc_rx_completion_handler,
133 },
134
135 /* CE2: target->host WMI */
136 {
137 .flags = CE_ATTR_FLAGS,
138 .src_nentries = 0,
139 .src_sz_max = 2048,
140 .dest_nentries = 512,
141 .recv_cb = ath11k_htc_rx_completion_handler,
142 },
143
144 /* CE3: host->target WMI (mac0) */
145 {
146 .flags = CE_ATTR_FLAGS,
147 .src_nentries = 32,
148 .src_sz_max = 2048,
149 .dest_nentries = 0,
150 .send_cb = ath11k_htc_tx_completion_handler,
151 },
152
153 /* CE4: host->target HTT */
154 {
155 .flags = CE_ATTR_FLAGS | CE_ATTR_DIS_INTR,
156 .src_nentries = 2048,
157 .src_sz_max = 256,
158 .dest_nentries = 0,
159 },
160
161 /* CE5: target->host pktlog */
162 {
163 .flags = CE_ATTR_FLAGS,
164 .src_nentries = 0,
165 .src_sz_max = 2048,
166 .dest_nentries = 512,
167 .recv_cb = ath11k_dp_htt_htc_t2h_msg_handler,
168 },
169
170 /* CE6: target autonomous hif_memcpy */
171 {
172 .flags = CE_ATTR_FLAGS | CE_ATTR_DIS_INTR,
173 .src_nentries = 0,
174 .src_sz_max = 0,
175 .dest_nentries = 0,
176 },
177
178 /* CE7: host->target WMI (mac1) */
179 {
180 .flags = CE_ATTR_FLAGS,
181 .src_nentries = 32,
182 .src_sz_max = 2048,
183 .dest_nentries = 0,
184 .send_cb = ath11k_htc_tx_completion_handler,
185 },
186
187 /* CE8: target autonomous hif_memcpy */
188 {
189 .flags = CE_ATTR_FLAGS,
190 .src_nentries = 0,
191 .src_sz_max = 0,
192 .dest_nentries = 0,
193 },
194
195 };
196
197 const struct ce_attr ath11k_host_ce_config_qcn9074[] = {
198 /* CE0: host->target HTC control and raw streams */
199 {
200 .flags = CE_ATTR_FLAGS,
201 .src_nentries = 16,
202 .src_sz_max = 2048,
203 .dest_nentries = 0,
204 },
205
206 /* CE1: target->host HTT + HTC control */
207 {
208 .flags = CE_ATTR_FLAGS,
209 .src_nentries = 0,
210 .src_sz_max = 2048,
211 .dest_nentries = 512,
212 .recv_cb = ath11k_htc_rx_completion_handler,
213 },
214
215 /* CE2: target->host WMI */
216 {
217 .flags = CE_ATTR_FLAGS,
218 .src_nentries = 0,
219 .src_sz_max = 2048,
220 .dest_nentries = 32,
221 .recv_cb = ath11k_htc_rx_completion_handler,
222 },
223
224 /* CE3: host->target WMI (mac0) */
225 {
226 .flags = CE_ATTR_FLAGS,
227 .src_nentries = 32,
228 .src_sz_max = 2048,
229 .dest_nentries = 0,
230 .send_cb = ath11k_htc_tx_completion_handler,
231 },
232
233 /* CE4: host->target HTT */
234 {
235 .flags = CE_ATTR_FLAGS | CE_ATTR_DIS_INTR,
236 .src_nentries = 2048,
237 .src_sz_max = 256,
238 .dest_nentries = 0,
239 },
240
241 /* CE5: target->host pktlog */
242 {
243 .flags = CE_ATTR_FLAGS,
244 .src_nentries = 0,
245 .src_sz_max = 2048,
246 .dest_nentries = 512,
247 .recv_cb = ath11k_dp_htt_htc_t2h_msg_handler,
248 },
249 };
250
ath11k_ce_need_shadow_fix(int ce_id)251 static bool ath11k_ce_need_shadow_fix(int ce_id)
252 {
253 /* only ce4 needs shadow workaround */
254 if (ce_id == 4)
255 return true;
256 return false;
257 }
258
ath11k_ce_stop_shadow_timers(struct ath11k_base * ab)259 void ath11k_ce_stop_shadow_timers(struct ath11k_base *ab)
260 {
261 int i;
262
263 if (!ab->hw_params.supports_shadow_regs)
264 return;
265
266 for (i = 0; i < ab->hw_params.ce_count; i++)
267 if (ath11k_ce_need_shadow_fix(i))
268 ath11k_dp_shadow_stop_timer(ab, &ab->ce.hp_timer[i]);
269 }
270
ath11k_ce_rx_buf_enqueue_pipe(struct ath11k_ce_pipe * pipe,struct sk_buff * skb,dma_addr_t paddr)271 static int ath11k_ce_rx_buf_enqueue_pipe(struct ath11k_ce_pipe *pipe,
272 struct sk_buff *skb, dma_addr_t paddr)
273 {
274 struct ath11k_base *ab = pipe->ab;
275 struct ath11k_ce_ring *ring = pipe->dest_ring;
276 struct hal_srng *srng;
277 unsigned int write_index;
278 unsigned int nentries_mask = ring->nentries_mask;
279 u32 *desc;
280 int ret;
281
282 lockdep_assert_held(&ab->ce.ce_lock);
283
284 write_index = ring->write_index;
285
286 srng = &ab->hal.srng_list[ring->hal_ring_id];
287
288 spin_lock_bh(&srng->lock);
289
290 ath11k_hal_srng_access_begin(ab, srng);
291
292 if (unlikely(ath11k_hal_srng_src_num_free(ab, srng, false) < 1)) {
293 ret = -ENOSPC;
294 goto exit;
295 }
296
297 desc = ath11k_hal_srng_src_get_next_entry(ab, srng);
298 if (!desc) {
299 ret = -ENOSPC;
300 goto exit;
301 }
302
303 ath11k_hal_ce_dst_set_desc(desc, paddr);
304
305 ring->skb[write_index] = skb;
306 write_index = CE_RING_IDX_INCR(nentries_mask, write_index);
307 ring->write_index = write_index;
308
309 pipe->rx_buf_needed--;
310
311 ret = 0;
312 exit:
313 ath11k_hal_srng_access_end(ab, srng);
314
315 spin_unlock_bh(&srng->lock);
316
317 return ret;
318 }
319
ath11k_ce_rx_post_pipe(struct ath11k_ce_pipe * pipe)320 static int ath11k_ce_rx_post_pipe(struct ath11k_ce_pipe *pipe)
321 {
322 struct ath11k_base *ab = pipe->ab;
323 struct sk_buff *skb;
324 dma_addr_t paddr;
325 int ret = 0;
326
327 if (!(pipe->dest_ring || pipe->status_ring))
328 return 0;
329
330 spin_lock_bh(&ab->ce.ce_lock);
331 while (pipe->rx_buf_needed) {
332 skb = dev_alloc_skb(pipe->buf_sz);
333 if (!skb) {
334 ret = -ENOMEM;
335 goto exit;
336 }
337
338 WARN_ON_ONCE(!IS_ALIGNED((unsigned long)skb->data, 4));
339
340 paddr = dma_map_single(ab->dev, skb->data,
341 skb->len + skb_tailroom(skb),
342 DMA_FROM_DEVICE);
343 if (unlikely(dma_mapping_error(ab->dev, paddr))) {
344 ath11k_warn(ab, "failed to dma map ce rx buf\n");
345 dev_kfree_skb_any(skb);
346 ret = -EIO;
347 goto exit;
348 }
349
350 ATH11K_SKB_RXCB(skb)->paddr = paddr;
351
352 ret = ath11k_ce_rx_buf_enqueue_pipe(pipe, skb, paddr);
353
354 if (ret) {
355 ath11k_warn(ab, "failed to enqueue rx buf: %d\n", ret);
356 dma_unmap_single(ab->dev, paddr,
357 skb->len + skb_tailroom(skb),
358 DMA_FROM_DEVICE);
359 dev_kfree_skb_any(skb);
360 goto exit;
361 }
362 }
363
364 exit:
365 spin_unlock_bh(&ab->ce.ce_lock);
366 return ret;
367 }
368
ath11k_ce_completed_recv_next(struct ath11k_ce_pipe * pipe,struct sk_buff ** skb,int * nbytes)369 static int ath11k_ce_completed_recv_next(struct ath11k_ce_pipe *pipe,
370 struct sk_buff **skb, int *nbytes)
371 {
372 struct ath11k_base *ab = pipe->ab;
373 struct hal_srng *srng;
374 unsigned int sw_index;
375 unsigned int nentries_mask;
376 u32 *desc;
377 int ret = 0;
378
379 spin_lock_bh(&ab->ce.ce_lock);
380
381 sw_index = pipe->dest_ring->sw_index;
382 nentries_mask = pipe->dest_ring->nentries_mask;
383
384 srng = &ab->hal.srng_list[pipe->status_ring->hal_ring_id];
385
386 spin_lock_bh(&srng->lock);
387
388 ath11k_hal_srng_access_begin(ab, srng);
389
390 desc = ath11k_hal_srng_dst_get_next_entry(ab, srng);
391 if (!desc) {
392 ret = -EIO;
393 goto err;
394 }
395
396 *nbytes = ath11k_hal_ce_dst_status_get_length(desc);
397
398 *skb = pipe->dest_ring->skb[sw_index];
399 pipe->dest_ring->skb[sw_index] = NULL;
400
401 sw_index = CE_RING_IDX_INCR(nentries_mask, sw_index);
402 pipe->dest_ring->sw_index = sw_index;
403
404 pipe->rx_buf_needed++;
405 err:
406 ath11k_hal_srng_access_end(ab, srng);
407
408 spin_unlock_bh(&srng->lock);
409
410 spin_unlock_bh(&ab->ce.ce_lock);
411
412 return ret;
413 }
414
ath11k_ce_recv_process_cb(struct ath11k_ce_pipe * pipe)415 static void ath11k_ce_recv_process_cb(struct ath11k_ce_pipe *pipe)
416 {
417 struct ath11k_base *ab = pipe->ab;
418 struct sk_buff *skb;
419 struct sk_buff_head list;
420 unsigned int nbytes, max_nbytes;
421 int ret;
422
423 __skb_queue_head_init(&list);
424 while (ath11k_ce_completed_recv_next(pipe, &skb, &nbytes) == 0) {
425 max_nbytes = skb->len + skb_tailroom(skb);
426 dma_unmap_single(ab->dev, ATH11K_SKB_RXCB(skb)->paddr,
427 max_nbytes, DMA_FROM_DEVICE);
428
429 if (unlikely(max_nbytes < nbytes || nbytes == 0)) {
430 ath11k_warn(ab, "unexpected rx length (nbytes %d, max %d)",
431 nbytes, max_nbytes);
432 dev_kfree_skb_any(skb);
433 continue;
434 }
435
436 skb_put(skb, nbytes);
437 __skb_queue_tail(&list, skb);
438 }
439
440 while ((skb = __skb_dequeue(&list))) {
441 ath11k_dbg(ab, ATH11K_DBG_CE, "rx ce pipe %d len %d\n",
442 pipe->pipe_num, skb->len);
443 pipe->recv_cb(ab, skb);
444 }
445
446 ret = ath11k_ce_rx_post_pipe(pipe);
447 if (ret && ret != -ENOSPC) {
448 ath11k_warn(ab, "failed to post rx buf to pipe: %d err: %d\n",
449 pipe->pipe_num, ret);
450 mod_timer(&ab->rx_replenish_retry,
451 jiffies + ATH11K_CE_RX_POST_RETRY_JIFFIES);
452 }
453 }
454
ath11k_ce_completed_send_next(struct ath11k_ce_pipe * pipe)455 static struct sk_buff *ath11k_ce_completed_send_next(struct ath11k_ce_pipe *pipe)
456 {
457 struct ath11k_base *ab = pipe->ab;
458 struct hal_srng *srng;
459 unsigned int sw_index;
460 unsigned int nentries_mask;
461 struct sk_buff *skb;
462 u32 *desc;
463
464 spin_lock_bh(&ab->ce.ce_lock);
465
466 sw_index = pipe->src_ring->sw_index;
467 nentries_mask = pipe->src_ring->nentries_mask;
468
469 srng = &ab->hal.srng_list[pipe->src_ring->hal_ring_id];
470
471 spin_lock_bh(&srng->lock);
472
473 ath11k_hal_srng_access_begin(ab, srng);
474
475 desc = ath11k_hal_srng_src_reap_next(ab, srng);
476 if (!desc) {
477 skb = ERR_PTR(-EIO);
478 goto err_unlock;
479 }
480
481 skb = pipe->src_ring->skb[sw_index];
482
483 pipe->src_ring->skb[sw_index] = NULL;
484
485 sw_index = CE_RING_IDX_INCR(nentries_mask, sw_index);
486 pipe->src_ring->sw_index = sw_index;
487
488 err_unlock:
489 spin_unlock_bh(&srng->lock);
490
491 spin_unlock_bh(&ab->ce.ce_lock);
492
493 return skb;
494 }
495
ath11k_ce_tx_process_cb(struct ath11k_ce_pipe * pipe)496 static void ath11k_ce_tx_process_cb(struct ath11k_ce_pipe *pipe)
497 {
498 struct ath11k_base *ab = pipe->ab;
499 struct sk_buff *skb;
500 struct sk_buff_head list;
501
502 __skb_queue_head_init(&list);
503 while (!IS_ERR(skb = ath11k_ce_completed_send_next(pipe))) {
504 if (!skb)
505 continue;
506
507 dma_unmap_single(ab->dev, ATH11K_SKB_CB(skb)->paddr, skb->len,
508 DMA_TO_DEVICE);
509
510 if ((!pipe->send_cb) || ab->hw_params.credit_flow) {
511 dev_kfree_skb_any(skb);
512 continue;
513 }
514
515 __skb_queue_tail(&list, skb);
516 }
517
518 while ((skb = __skb_dequeue(&list))) {
519 ath11k_dbg(ab, ATH11K_DBG_CE, "tx ce pipe %d len %d\n",
520 pipe->pipe_num, skb->len);
521 pipe->send_cb(ab, skb);
522 }
523 }
524
ath11k_ce_srng_msi_ring_params_setup(struct ath11k_base * ab,u32 ce_id,struct hal_srng_params * ring_params)525 static void ath11k_ce_srng_msi_ring_params_setup(struct ath11k_base *ab, u32 ce_id,
526 struct hal_srng_params *ring_params)
527 {
528 u32 msi_data_start;
529 u32 msi_data_count, msi_data_idx;
530 u32 msi_irq_start;
531 u32 addr_lo;
532 u32 addr_hi;
533 int ret;
534
535 ret = ath11k_get_user_msi_vector(ab, "CE",
536 &msi_data_count, &msi_data_start,
537 &msi_irq_start);
538
539 if (ret)
540 return;
541
542 ath11k_get_msi_address(ab, &addr_lo, &addr_hi);
543 ath11k_get_ce_msi_idx(ab, ce_id, &msi_data_idx);
544
545 ring_params->msi_addr = addr_lo;
546 ring_params->msi_addr |= (dma_addr_t)(((uint64_t)addr_hi) << 32);
547 ring_params->msi_data = (msi_data_idx % msi_data_count) + msi_data_start;
548 ring_params->flags |= HAL_SRNG_FLAGS_MSI_INTR;
549 }
550
ath11k_ce_init_ring(struct ath11k_base * ab,struct ath11k_ce_ring * ce_ring,int ce_id,enum hal_ring_type type)551 static int ath11k_ce_init_ring(struct ath11k_base *ab,
552 struct ath11k_ce_ring *ce_ring,
553 int ce_id, enum hal_ring_type type)
554 {
555 struct hal_srng_params params = { 0 };
556 int ret;
557
558 params.ring_base_paddr = ce_ring->base_addr_ce_space;
559 params.ring_base_vaddr = ce_ring->base_addr_owner_space;
560 params.num_entries = ce_ring->nentries;
561
562 if (!(CE_ATTR_DIS_INTR & ab->hw_params.host_ce_config[ce_id].flags))
563 ath11k_ce_srng_msi_ring_params_setup(ab, ce_id, ¶ms);
564
565 switch (type) {
566 case HAL_CE_SRC:
567 if (!(CE_ATTR_DIS_INTR & ab->hw_params.host_ce_config[ce_id].flags))
568 params.intr_batch_cntr_thres_entries = 1;
569 break;
570 case HAL_CE_DST:
571 params.max_buffer_len = ab->hw_params.host_ce_config[ce_id].src_sz_max;
572 if (!(ab->hw_params.host_ce_config[ce_id].flags & CE_ATTR_DIS_INTR)) {
573 params.intr_timer_thres_us = 1024;
574 params.flags |= HAL_SRNG_FLAGS_LOW_THRESH_INTR_EN;
575 params.low_threshold = ce_ring->nentries - 3;
576 }
577 break;
578 case HAL_CE_DST_STATUS:
579 if (!(ab->hw_params.host_ce_config[ce_id].flags & CE_ATTR_DIS_INTR)) {
580 params.intr_batch_cntr_thres_entries = 1;
581 params.intr_timer_thres_us = 0x1000;
582 }
583 break;
584 default:
585 ath11k_warn(ab, "Invalid CE ring type %d\n", type);
586 return -EINVAL;
587 }
588
589 /* TODO: Init other params needed by HAL to init the ring */
590
591 ret = ath11k_hal_srng_setup(ab, type, ce_id, 0, ¶ms);
592 if (ret < 0) {
593 ath11k_warn(ab, "failed to setup srng: %d ring_id %d\n",
594 ret, ce_id);
595 return ret;
596 }
597
598 ce_ring->hal_ring_id = ret;
599
600 if (ab->hw_params.supports_shadow_regs &&
601 ath11k_ce_need_shadow_fix(ce_id))
602 ath11k_dp_shadow_init_timer(ab, &ab->ce.hp_timer[ce_id],
603 ATH11K_SHADOW_CTRL_TIMER_INTERVAL,
604 ce_ring->hal_ring_id);
605
606 return 0;
607 }
608
609 static struct ath11k_ce_ring *
ath11k_ce_alloc_ring(struct ath11k_base * ab,int nentries,int desc_sz)610 ath11k_ce_alloc_ring(struct ath11k_base *ab, int nentries, int desc_sz)
611 {
612 struct ath11k_ce_ring *ce_ring;
613 dma_addr_t base_addr;
614
615 ce_ring = kzalloc(struct_size(ce_ring, skb, nentries), GFP_KERNEL);
616 if (ce_ring == NULL)
617 return ERR_PTR(-ENOMEM);
618
619 ce_ring->nentries = nentries;
620 ce_ring->nentries_mask = nentries - 1;
621
622 /* Legacy platforms that do not support cache
623 * coherent DMA are unsupported
624 */
625 ce_ring->base_addr_owner_space_unaligned =
626 dma_alloc_coherent(ab->dev,
627 nentries * desc_sz + CE_DESC_RING_ALIGN,
628 &base_addr, GFP_KERNEL);
629 if (!ce_ring->base_addr_owner_space_unaligned) {
630 kfree(ce_ring);
631 return ERR_PTR(-ENOMEM);
632 }
633
634 ce_ring->base_addr_ce_space_unaligned = base_addr;
635
636 ce_ring->base_addr_owner_space = PTR_ALIGN(
637 ce_ring->base_addr_owner_space_unaligned,
638 CE_DESC_RING_ALIGN);
639 ce_ring->base_addr_ce_space = ALIGN(
640 ce_ring->base_addr_ce_space_unaligned,
641 CE_DESC_RING_ALIGN);
642
643 return ce_ring;
644 }
645
ath11k_ce_alloc_pipe(struct ath11k_base * ab,int ce_id)646 static int ath11k_ce_alloc_pipe(struct ath11k_base *ab, int ce_id)
647 {
648 struct ath11k_ce_pipe *pipe = &ab->ce.ce_pipe[ce_id];
649 const struct ce_attr *attr = &ab->hw_params.host_ce_config[ce_id];
650 struct ath11k_ce_ring *ring;
651 int nentries;
652 int desc_sz;
653
654 pipe->attr_flags = attr->flags;
655
656 if (attr->src_nentries) {
657 pipe->send_cb = attr->send_cb;
658 nentries = roundup_pow_of_two(attr->src_nentries);
659 desc_sz = ath11k_hal_ce_get_desc_size(HAL_CE_DESC_SRC);
660 ring = ath11k_ce_alloc_ring(ab, nentries, desc_sz);
661 if (IS_ERR(ring))
662 return PTR_ERR(ring);
663 pipe->src_ring = ring;
664 }
665
666 if (attr->dest_nentries) {
667 pipe->recv_cb = attr->recv_cb;
668 nentries = roundup_pow_of_two(attr->dest_nentries);
669 desc_sz = ath11k_hal_ce_get_desc_size(HAL_CE_DESC_DST);
670 ring = ath11k_ce_alloc_ring(ab, nentries, desc_sz);
671 if (IS_ERR(ring))
672 return PTR_ERR(ring);
673 pipe->dest_ring = ring;
674
675 desc_sz = ath11k_hal_ce_get_desc_size(HAL_CE_DESC_DST_STATUS);
676 ring = ath11k_ce_alloc_ring(ab, nentries, desc_sz);
677 if (IS_ERR(ring))
678 return PTR_ERR(ring);
679 pipe->status_ring = ring;
680 }
681
682 return 0;
683 }
684
ath11k_ce_per_engine_service(struct ath11k_base * ab,u16 ce_id)685 void ath11k_ce_per_engine_service(struct ath11k_base *ab, u16 ce_id)
686 {
687 struct ath11k_ce_pipe *pipe = &ab->ce.ce_pipe[ce_id];
688 const struct ce_attr *attr = &ab->hw_params.host_ce_config[ce_id];
689
690 if (attr->src_nentries)
691 ath11k_ce_tx_process_cb(pipe);
692
693 if (pipe->recv_cb)
694 ath11k_ce_recv_process_cb(pipe);
695 }
696
ath11k_ce_poll_send_completed(struct ath11k_base * ab,u8 pipe_id)697 void ath11k_ce_poll_send_completed(struct ath11k_base *ab, u8 pipe_id)
698 {
699 struct ath11k_ce_pipe *pipe = &ab->ce.ce_pipe[pipe_id];
700 const struct ce_attr *attr = &ab->hw_params.host_ce_config[pipe_id];
701
702 if ((pipe->attr_flags & CE_ATTR_DIS_INTR) && attr->src_nentries)
703 ath11k_ce_tx_process_cb(pipe);
704 }
705 EXPORT_SYMBOL(ath11k_ce_per_engine_service);
706
ath11k_ce_send(struct ath11k_base * ab,struct sk_buff * skb,u8 pipe_id,u16 transfer_id)707 int ath11k_ce_send(struct ath11k_base *ab, struct sk_buff *skb, u8 pipe_id,
708 u16 transfer_id)
709 {
710 struct ath11k_ce_pipe *pipe = &ab->ce.ce_pipe[pipe_id];
711 struct hal_srng *srng;
712 u32 *desc;
713 unsigned int write_index, sw_index;
714 unsigned int nentries_mask;
715 int ret = 0;
716 u8 byte_swap_data = 0;
717 int num_used;
718
719 /* Check if some entries could be regained by handling tx completion if
720 * the CE has interrupts disabled and the used entries is more than the
721 * defined usage threshold.
722 */
723 if (pipe->attr_flags & CE_ATTR_DIS_INTR) {
724 spin_lock_bh(&ab->ce.ce_lock);
725 write_index = pipe->src_ring->write_index;
726
727 sw_index = pipe->src_ring->sw_index;
728
729 if (write_index >= sw_index)
730 num_used = write_index - sw_index;
731 else
732 num_used = pipe->src_ring->nentries - sw_index +
733 write_index;
734
735 spin_unlock_bh(&ab->ce.ce_lock);
736
737 if (num_used > ATH11K_CE_USAGE_THRESHOLD)
738 ath11k_ce_poll_send_completed(ab, pipe->pipe_num);
739 }
740
741 if (test_bit(ATH11K_FLAG_CRASH_FLUSH, &ab->dev_flags))
742 return -ESHUTDOWN;
743
744 spin_lock_bh(&ab->ce.ce_lock);
745
746 write_index = pipe->src_ring->write_index;
747 nentries_mask = pipe->src_ring->nentries_mask;
748
749 srng = &ab->hal.srng_list[pipe->src_ring->hal_ring_id];
750
751 spin_lock_bh(&srng->lock);
752
753 ath11k_hal_srng_access_begin(ab, srng);
754
755 if (unlikely(ath11k_hal_srng_src_num_free(ab, srng, false) < 1)) {
756 ath11k_hal_srng_access_end(ab, srng);
757 ret = -ENOBUFS;
758 goto err_unlock;
759 }
760
761 desc = ath11k_hal_srng_src_get_next_reaped(ab, srng);
762 if (!desc) {
763 ath11k_hal_srng_access_end(ab, srng);
764 ret = -ENOBUFS;
765 goto err_unlock;
766 }
767
768 if (pipe->attr_flags & CE_ATTR_BYTE_SWAP_DATA)
769 byte_swap_data = 1;
770
771 ath11k_hal_ce_src_set_desc(desc, ATH11K_SKB_CB(skb)->paddr,
772 skb->len, transfer_id, byte_swap_data);
773
774 pipe->src_ring->skb[write_index] = skb;
775 pipe->src_ring->write_index = CE_RING_IDX_INCR(nentries_mask,
776 write_index);
777
778 ath11k_hal_srng_access_end(ab, srng);
779
780 if (ath11k_ce_need_shadow_fix(pipe_id))
781 ath11k_dp_shadow_start_timer(ab, srng, &ab->ce.hp_timer[pipe_id]);
782
783 spin_unlock_bh(&srng->lock);
784
785 spin_unlock_bh(&ab->ce.ce_lock);
786
787 return 0;
788
789 err_unlock:
790 spin_unlock_bh(&srng->lock);
791
792 spin_unlock_bh(&ab->ce.ce_lock);
793
794 return ret;
795 }
796
ath11k_ce_rx_pipe_cleanup(struct ath11k_ce_pipe * pipe)797 static void ath11k_ce_rx_pipe_cleanup(struct ath11k_ce_pipe *pipe)
798 {
799 struct ath11k_base *ab = pipe->ab;
800 struct ath11k_ce_ring *ring = pipe->dest_ring;
801 struct sk_buff *skb;
802 int i;
803
804 if (!(ring && pipe->buf_sz))
805 return;
806
807 for (i = 0; i < ring->nentries; i++) {
808 skb = ring->skb[i];
809 if (!skb)
810 continue;
811
812 ring->skb[i] = NULL;
813 dma_unmap_single(ab->dev, ATH11K_SKB_RXCB(skb)->paddr,
814 skb->len + skb_tailroom(skb), DMA_FROM_DEVICE);
815 dev_kfree_skb_any(skb);
816 }
817 }
818
ath11k_ce_shadow_config(struct ath11k_base * ab)819 static void ath11k_ce_shadow_config(struct ath11k_base *ab)
820 {
821 int i;
822
823 for (i = 0; i < ab->hw_params.ce_count; i++) {
824 if (ab->hw_params.host_ce_config[i].src_nentries)
825 ath11k_hal_srng_update_shadow_config(ab,
826 HAL_CE_SRC, i);
827
828 if (ab->hw_params.host_ce_config[i].dest_nentries) {
829 ath11k_hal_srng_update_shadow_config(ab,
830 HAL_CE_DST, i);
831
832 ath11k_hal_srng_update_shadow_config(ab,
833 HAL_CE_DST_STATUS, i);
834 }
835 }
836 }
837
ath11k_ce_get_shadow_config(struct ath11k_base * ab,u32 ** shadow_cfg,u32 * shadow_cfg_len)838 void ath11k_ce_get_shadow_config(struct ath11k_base *ab,
839 u32 **shadow_cfg, u32 *shadow_cfg_len)
840 {
841 if (!ab->hw_params.supports_shadow_regs)
842 return;
843
844 ath11k_hal_srng_get_shadow_config(ab, shadow_cfg, shadow_cfg_len);
845
846 /* shadow is already configured */
847 if (*shadow_cfg_len)
848 return;
849
850 /* shadow isn't configured yet, configure now.
851 * non-CE srngs are configured firstly, then
852 * all CE srngs.
853 */
854 ath11k_hal_srng_shadow_config(ab);
855 ath11k_ce_shadow_config(ab);
856
857 /* get the shadow configuration */
858 ath11k_hal_srng_get_shadow_config(ab, shadow_cfg, shadow_cfg_len);
859 }
860 EXPORT_SYMBOL(ath11k_ce_get_shadow_config);
861
ath11k_ce_cleanup_pipes(struct ath11k_base * ab)862 void ath11k_ce_cleanup_pipes(struct ath11k_base *ab)
863 {
864 struct ath11k_ce_pipe *pipe;
865 int pipe_num;
866
867 ath11k_ce_stop_shadow_timers(ab);
868
869 for (pipe_num = 0; pipe_num < ab->hw_params.ce_count; pipe_num++) {
870 pipe = &ab->ce.ce_pipe[pipe_num];
871 ath11k_ce_rx_pipe_cleanup(pipe);
872
873 /* Cleanup any src CE's which have interrupts disabled */
874 ath11k_ce_poll_send_completed(ab, pipe_num);
875
876 /* NOTE: Should we also clean up tx buffer in all pipes? */
877 }
878 }
879 EXPORT_SYMBOL(ath11k_ce_cleanup_pipes);
880
ath11k_ce_rx_post_buf(struct ath11k_base * ab)881 void ath11k_ce_rx_post_buf(struct ath11k_base *ab)
882 {
883 struct ath11k_ce_pipe *pipe;
884 int i;
885 int ret;
886
887 for (i = 0; i < ab->hw_params.ce_count; i++) {
888 pipe = &ab->ce.ce_pipe[i];
889 ret = ath11k_ce_rx_post_pipe(pipe);
890 if (ret) {
891 if (ret == -ENOSPC)
892 continue;
893
894 ath11k_warn(ab, "failed to post rx buf to pipe: %d err: %d\n",
895 i, ret);
896 mod_timer(&ab->rx_replenish_retry,
897 jiffies + ATH11K_CE_RX_POST_RETRY_JIFFIES);
898
899 return;
900 }
901 }
902 }
903 EXPORT_SYMBOL(ath11k_ce_rx_post_buf);
904
ath11k_ce_rx_replenish_retry(struct timer_list * t)905 void ath11k_ce_rx_replenish_retry(struct timer_list *t)
906 {
907 struct ath11k_base *ab = from_timer(ab, t, rx_replenish_retry);
908
909 ath11k_ce_rx_post_buf(ab);
910 }
911
ath11k_ce_init_pipes(struct ath11k_base * ab)912 int ath11k_ce_init_pipes(struct ath11k_base *ab)
913 {
914 struct ath11k_ce_pipe *pipe;
915 int i;
916 int ret;
917
918 for (i = 0; i < ab->hw_params.ce_count; i++) {
919 pipe = &ab->ce.ce_pipe[i];
920
921 if (pipe->src_ring) {
922 ret = ath11k_ce_init_ring(ab, pipe->src_ring, i,
923 HAL_CE_SRC);
924 if (ret) {
925 ath11k_warn(ab, "failed to init src ring: %d\n",
926 ret);
927 /* Should we clear any partial init */
928 return ret;
929 }
930
931 pipe->src_ring->write_index = 0;
932 pipe->src_ring->sw_index = 0;
933 }
934
935 if (pipe->dest_ring) {
936 ret = ath11k_ce_init_ring(ab, pipe->dest_ring, i,
937 HAL_CE_DST);
938 if (ret) {
939 ath11k_warn(ab, "failed to init dest ring: %d\n",
940 ret);
941 /* Should we clear any partial init */
942 return ret;
943 }
944
945 pipe->rx_buf_needed = pipe->dest_ring->nentries ?
946 pipe->dest_ring->nentries - 2 : 0;
947
948 pipe->dest_ring->write_index = 0;
949 pipe->dest_ring->sw_index = 0;
950 }
951
952 if (pipe->status_ring) {
953 ret = ath11k_ce_init_ring(ab, pipe->status_ring, i,
954 HAL_CE_DST_STATUS);
955 if (ret) {
956 ath11k_warn(ab, "failed to init dest status ing: %d\n",
957 ret);
958 /* Should we clear any partial init */
959 return ret;
960 }
961
962 pipe->status_ring->write_index = 0;
963 pipe->status_ring->sw_index = 0;
964 }
965 }
966
967 return 0;
968 }
969
ath11k_ce_free_pipes(struct ath11k_base * ab)970 void ath11k_ce_free_pipes(struct ath11k_base *ab)
971 {
972 struct ath11k_ce_pipe *pipe;
973 struct ath11k_ce_ring *ce_ring;
974 int desc_sz;
975 int i;
976
977 for (i = 0; i < ab->hw_params.ce_count; i++) {
978 pipe = &ab->ce.ce_pipe[i];
979
980 if (ath11k_ce_need_shadow_fix(i))
981 ath11k_dp_shadow_stop_timer(ab, &ab->ce.hp_timer[i]);
982
983 if (pipe->src_ring) {
984 desc_sz = ath11k_hal_ce_get_desc_size(HAL_CE_DESC_SRC);
985 ce_ring = pipe->src_ring;
986 dma_free_coherent(ab->dev,
987 pipe->src_ring->nentries * desc_sz +
988 CE_DESC_RING_ALIGN,
989 ce_ring->base_addr_owner_space_unaligned,
990 ce_ring->base_addr_ce_space_unaligned);
991 kfree(pipe->src_ring);
992 pipe->src_ring = NULL;
993 }
994
995 if (pipe->dest_ring) {
996 desc_sz = ath11k_hal_ce_get_desc_size(HAL_CE_DESC_DST);
997 ce_ring = pipe->dest_ring;
998 dma_free_coherent(ab->dev,
999 pipe->dest_ring->nentries * desc_sz +
1000 CE_DESC_RING_ALIGN,
1001 ce_ring->base_addr_owner_space_unaligned,
1002 ce_ring->base_addr_ce_space_unaligned);
1003 kfree(pipe->dest_ring);
1004 pipe->dest_ring = NULL;
1005 }
1006
1007 if (pipe->status_ring) {
1008 desc_sz =
1009 ath11k_hal_ce_get_desc_size(HAL_CE_DESC_DST_STATUS);
1010 ce_ring = pipe->status_ring;
1011 dma_free_coherent(ab->dev,
1012 pipe->status_ring->nentries * desc_sz +
1013 CE_DESC_RING_ALIGN,
1014 ce_ring->base_addr_owner_space_unaligned,
1015 ce_ring->base_addr_ce_space_unaligned);
1016 kfree(pipe->status_ring);
1017 pipe->status_ring = NULL;
1018 }
1019 }
1020 }
1021 EXPORT_SYMBOL(ath11k_ce_free_pipes);
1022
ath11k_ce_alloc_pipes(struct ath11k_base * ab)1023 int ath11k_ce_alloc_pipes(struct ath11k_base *ab)
1024 {
1025 struct ath11k_ce_pipe *pipe;
1026 int i;
1027 int ret;
1028 const struct ce_attr *attr;
1029
1030 spin_lock_init(&ab->ce.ce_lock);
1031
1032 for (i = 0; i < ab->hw_params.ce_count; i++) {
1033 attr = &ab->hw_params.host_ce_config[i];
1034 pipe = &ab->ce.ce_pipe[i];
1035 pipe->pipe_num = i;
1036 pipe->ab = ab;
1037 pipe->buf_sz = attr->src_sz_max;
1038
1039 ret = ath11k_ce_alloc_pipe(ab, i);
1040 if (ret) {
1041 /* Free any partial successful allocation */
1042 ath11k_ce_free_pipes(ab);
1043 return ret;
1044 }
1045 }
1046
1047 return 0;
1048 }
1049 EXPORT_SYMBOL(ath11k_ce_alloc_pipes);
1050
1051 /* For Big Endian Host, Copy Engine byte_swap is enabled
1052 * When Copy Engine does byte_swap, need to byte swap again for the
1053 * Host to get/put buffer content in the correct byte order
1054 */
ath11k_ce_byte_swap(void * mem,u32 len)1055 void ath11k_ce_byte_swap(void *mem, u32 len)
1056 {
1057 int i;
1058
1059 if (IS_ENABLED(CONFIG_CPU_BIG_ENDIAN)) {
1060 if (!mem)
1061 return;
1062
1063 for (i = 0; i < (len / 4); i++) {
1064 *(u32 *)mem = swab32(*(u32 *)mem);
1065 mem += 4;
1066 }
1067 }
1068 }
1069
ath11k_ce_get_attr_flags(struct ath11k_base * ab,int ce_id)1070 int ath11k_ce_get_attr_flags(struct ath11k_base *ab, int ce_id)
1071 {
1072 if (ce_id >= ab->hw_params.ce_count)
1073 return -EINVAL;
1074
1075 return ab->hw_params.host_ce_config[ce_id].flags;
1076 }
1077 EXPORT_SYMBOL(ath11k_ce_get_attr_flags);
1078