1 // SPDX-License-Identifier: BSD-3-Clause-Clear
2 /*
3 * Copyright (c) 2018-2019 The Linux Foundation. All rights reserved.
4 * Copyright (c) 2021-2025 Qualcomm Innovation Center, Inc. All rights reserved.
5 */
6
7 #include <linux/module.h>
8 #include <linux/slab.h>
9 #include <linux/remoteproc.h>
10 #include <linux/firmware.h>
11 #include <linux/of.h>
12
13 #include "core.h"
14 #include "dp_tx.h"
15 #include "dp_rx.h"
16 #include "debug.h"
17 #include "hif.h"
18 #include "wow.h"
19 #include "fw.h"
20
21 unsigned int ath11k_debug_mask;
22 EXPORT_SYMBOL(ath11k_debug_mask);
23 module_param_named(debug_mask, ath11k_debug_mask, uint, 0644);
24 MODULE_PARM_DESC(debug_mask, "Debugging mask");
25
26 static unsigned int ath11k_crypto_mode;
27 module_param_named(crypto_mode, ath11k_crypto_mode, uint, 0644);
28 MODULE_PARM_DESC(crypto_mode, "crypto mode: 0-hardware, 1-software");
29
30 /* frame mode values are mapped as per enum ath11k_hw_txrx_mode */
31 unsigned int ath11k_frame_mode = ATH11K_HW_TXRX_NATIVE_WIFI;
32 module_param_named(frame_mode, ath11k_frame_mode, uint, 0644);
33 MODULE_PARM_DESC(frame_mode,
34 "Datapath frame mode (0: raw, 1: native wifi (default), 2: ethernet)");
35
36 bool ath11k_ftm_mode;
37 module_param_named(ftm_mode, ath11k_ftm_mode, bool, 0444);
38 MODULE_PARM_DESC(ftm_mode, "Boots up in factory test mode");
39
40 static const struct ath11k_hw_params ath11k_hw_params[] = {
41 {
42 .hw_rev = ATH11K_HW_IPQ8074,
43 .name = "ipq8074 hw2.0",
44 .fw = {
45 .dir = "IPQ8074/hw2.0",
46 .board_size = 256 * 1024,
47 .cal_offset = 128 * 1024,
48 },
49 .max_radios = 3,
50 .bdf_addr = 0x4B0C0000,
51 .hw_ops = &ipq8074_ops,
52 .ring_mask = &ath11k_hw_ring_mask_ipq8074,
53 .internal_sleep_clock = false,
54 .regs = &ipq8074_regs,
55 .qmi_service_ins_id = ATH11K_QMI_WLFW_SERVICE_INS_ID_V01_IPQ8074,
56 .host_ce_config = ath11k_host_ce_config_ipq8074,
57 .ce_count = 12,
58 .target_ce_config = ath11k_target_ce_config_wlan_ipq8074,
59 .target_ce_count = 11,
60 .svc_to_ce_map = ath11k_target_service_to_ce_map_wlan_ipq8074,
61 .svc_to_ce_map_len = 21,
62 .ce_ie_addr = &ath11k_ce_ie_addr_ipq8074,
63 .single_pdev_only = false,
64 .rxdma1_enable = true,
65 .num_rxdma_per_pdev = 1,
66 .rx_mac_buf_ring = false,
67 .vdev_start_delay = false,
68 .htt_peer_map_v2 = true,
69
70 .spectral = {
71 .fft_sz = 2,
72 /* HW bug, expected BIN size is 2 bytes but HW report as 4 bytes.
73 * so added pad size as 2 bytes to compensate the BIN size
74 */
75 .fft_pad_sz = 2,
76 .summary_pad_sz = 0,
77 .fft_hdr_len = 16,
78 .max_fft_bins = 512,
79 .fragment_160mhz = true,
80 },
81
82 .interface_modes = BIT(NL80211_IFTYPE_STATION) |
83 BIT(NL80211_IFTYPE_AP) |
84 BIT(NL80211_IFTYPE_MESH_POINT),
85 .supports_monitor = true,
86 .full_monitor_mode = false,
87 .supports_shadow_regs = false,
88 .idle_ps = false,
89 .supports_sta_ps = false,
90 .coldboot_cal_mm = true,
91 .coldboot_cal_ftm = true,
92 .cbcal_restart_fw = true,
93 .fw_mem_mode = 0,
94 .num_vdevs = 16 + 1,
95 .num_peers = 512,
96 .supports_suspend = false,
97 .hal_desc_sz = sizeof(struct hal_rx_desc_ipq8074),
98 .supports_regdb = false,
99 .fix_l1ss = true,
100 .credit_flow = false,
101 .max_tx_ring = DP_TCL_NUM_RING_MAX,
102 .hal_params = &ath11k_hw_hal_params_ipq8074,
103 .supports_dynamic_smps_6ghz = false,
104 .alloc_cacheable_memory = true,
105 .supports_rssi_stats = false,
106 .fw_wmi_diag_event = false,
107 .current_cc_support = false,
108 .dbr_debug_support = true,
109 .global_reset = false,
110 .bios_sar_capa = NULL,
111 .m3_fw_support = false,
112 .fixed_bdf_addr = true,
113 .fixed_mem_region = true,
114 .static_window_map = false,
115 .hybrid_bus_type = false,
116 .fixed_fw_mem = false,
117 .support_off_channel_tx = false,
118 .supports_multi_bssid = false,
119
120 .sram_dump = {},
121
122 .tcl_ring_retry = true,
123 .tx_ring_size = DP_TCL_DATA_RING_SIZE,
124 .smp2p_wow_exit = false,
125 .support_dual_stations = false,
126 },
127 {
128 .hw_rev = ATH11K_HW_IPQ6018_HW10,
129 .name = "ipq6018 hw1.0",
130 .fw = {
131 .dir = "IPQ6018/hw1.0",
132 .board_size = 256 * 1024,
133 .cal_offset = 128 * 1024,
134 },
135 .max_radios = 2,
136 .bdf_addr = 0x4ABC0000,
137 .hw_ops = &ipq6018_ops,
138 .ring_mask = &ath11k_hw_ring_mask_ipq8074,
139 .internal_sleep_clock = false,
140 .regs = &ipq8074_regs,
141 .qmi_service_ins_id = ATH11K_QMI_WLFW_SERVICE_INS_ID_V01_IPQ8074,
142 .host_ce_config = ath11k_host_ce_config_ipq8074,
143 .ce_count = 12,
144 .target_ce_config = ath11k_target_ce_config_wlan_ipq8074,
145 .target_ce_count = 11,
146 .svc_to_ce_map = ath11k_target_service_to_ce_map_wlan_ipq6018,
147 .svc_to_ce_map_len = 19,
148 .ce_ie_addr = &ath11k_ce_ie_addr_ipq8074,
149 .single_pdev_only = false,
150 .rxdma1_enable = true,
151 .num_rxdma_per_pdev = 1,
152 .rx_mac_buf_ring = false,
153 .vdev_start_delay = false,
154 .htt_peer_map_v2 = true,
155
156 .spectral = {
157 .fft_sz = 4,
158 .fft_pad_sz = 0,
159 .summary_pad_sz = 0,
160 .fft_hdr_len = 16,
161 .max_fft_bins = 512,
162 .fragment_160mhz = true,
163 },
164
165 .interface_modes = BIT(NL80211_IFTYPE_STATION) |
166 BIT(NL80211_IFTYPE_AP) |
167 BIT(NL80211_IFTYPE_MESH_POINT),
168 .supports_monitor = true,
169 .full_monitor_mode = false,
170 .supports_shadow_regs = false,
171 .idle_ps = false,
172 .supports_sta_ps = false,
173 .coldboot_cal_mm = true,
174 .coldboot_cal_ftm = true,
175 .cbcal_restart_fw = true,
176 .fw_mem_mode = 0,
177 .num_vdevs = 16 + 1,
178 .num_peers = 512,
179 .supports_suspend = false,
180 .hal_desc_sz = sizeof(struct hal_rx_desc_ipq8074),
181 .supports_regdb = false,
182 .fix_l1ss = true,
183 .credit_flow = false,
184 .max_tx_ring = DP_TCL_NUM_RING_MAX,
185 .hal_params = &ath11k_hw_hal_params_ipq8074,
186 .supports_dynamic_smps_6ghz = false,
187 .alloc_cacheable_memory = true,
188 .supports_rssi_stats = false,
189 .fw_wmi_diag_event = false,
190 .current_cc_support = false,
191 .dbr_debug_support = true,
192 .global_reset = false,
193 .bios_sar_capa = NULL,
194 .m3_fw_support = false,
195 .fixed_bdf_addr = true,
196 .fixed_mem_region = true,
197 .static_window_map = false,
198 .hybrid_bus_type = false,
199 .fixed_fw_mem = false,
200 .support_off_channel_tx = false,
201 .supports_multi_bssid = false,
202
203 .sram_dump = {},
204
205 .tcl_ring_retry = true,
206 .tx_ring_size = DP_TCL_DATA_RING_SIZE,
207 .smp2p_wow_exit = false,
208 .support_fw_mac_sequence = false,
209 .support_dual_stations = false,
210 },
211 {
212 .name = "qca6390 hw2.0",
213 .hw_rev = ATH11K_HW_QCA6390_HW20,
214 .fw = {
215 .dir = "QCA6390/hw2.0",
216 .board_size = 256 * 1024,
217 .cal_offset = 128 * 1024,
218 },
219 .max_radios = 3,
220 .bdf_addr = 0x4B0C0000,
221 .hw_ops = &qca6390_ops,
222 .ring_mask = &ath11k_hw_ring_mask_qca6390,
223 .internal_sleep_clock = true,
224 .regs = &qca6390_regs,
225 .qmi_service_ins_id = ATH11K_QMI_WLFW_SERVICE_INS_ID_V01_QCA6390,
226 .host_ce_config = ath11k_host_ce_config_qca6390,
227 .ce_count = 9,
228 .target_ce_config = ath11k_target_ce_config_wlan_qca6390,
229 .target_ce_count = 9,
230 .svc_to_ce_map = ath11k_target_service_to_ce_map_wlan_qca6390,
231 .svc_to_ce_map_len = 14,
232 .ce_ie_addr = &ath11k_ce_ie_addr_ipq8074,
233 .single_pdev_only = true,
234 .rxdma1_enable = false,
235 .num_rxdma_per_pdev = 2,
236 .rx_mac_buf_ring = true,
237 .vdev_start_delay = true,
238 .htt_peer_map_v2 = false,
239
240 .spectral = {
241 .fft_sz = 0,
242 .fft_pad_sz = 0,
243 .summary_pad_sz = 0,
244 .fft_hdr_len = 0,
245 .max_fft_bins = 0,
246 .fragment_160mhz = false,
247 },
248
249 .interface_modes = BIT(NL80211_IFTYPE_STATION) |
250 BIT(NL80211_IFTYPE_AP) |
251 BIT(NL80211_IFTYPE_P2P_DEVICE) |
252 BIT(NL80211_IFTYPE_P2P_CLIENT) |
253 BIT(NL80211_IFTYPE_P2P_GO),
254 .supports_monitor = false,
255 .full_monitor_mode = false,
256 .supports_shadow_regs = true,
257 .idle_ps = true,
258 .supports_sta_ps = true,
259 .coldboot_cal_mm = false,
260 .coldboot_cal_ftm = false,
261 .cbcal_restart_fw = false,
262 .fw_mem_mode = 0,
263 .num_vdevs = 2 + 1,
264 .num_peers = 512,
265 .supports_suspend = true,
266 .hal_desc_sz = sizeof(struct hal_rx_desc_ipq8074),
267 .supports_regdb = false,
268 .fix_l1ss = true,
269 .credit_flow = true,
270 .max_tx_ring = DP_TCL_NUM_RING_MAX_QCA6390,
271 .hal_params = &ath11k_hw_hal_params_qca6390,
272 .supports_dynamic_smps_6ghz = false,
273 .alloc_cacheable_memory = false,
274 .supports_rssi_stats = true,
275 .fw_wmi_diag_event = true,
276 .current_cc_support = true,
277 .dbr_debug_support = false,
278 .global_reset = true,
279 .bios_sar_capa = NULL,
280 .m3_fw_support = true,
281 .fixed_bdf_addr = false,
282 .fixed_mem_region = false,
283 .static_window_map = false,
284 .hybrid_bus_type = false,
285 .fixed_fw_mem = false,
286 .support_off_channel_tx = true,
287 .supports_multi_bssid = true,
288
289 .sram_dump = {
290 .start = 0x01400000,
291 .end = 0x0171ffff,
292 },
293
294 .tcl_ring_retry = true,
295 .tx_ring_size = DP_TCL_DATA_RING_SIZE,
296 .smp2p_wow_exit = false,
297 .support_fw_mac_sequence = true,
298 .support_dual_stations = true,
299 },
300 {
301 .name = "qcn9074 hw1.0",
302 .hw_rev = ATH11K_HW_QCN9074_HW10,
303 .fw = {
304 .dir = "QCN9074/hw1.0",
305 .board_size = 256 * 1024,
306 .cal_offset = 128 * 1024,
307 },
308 .max_radios = 1,
309 .single_pdev_only = false,
310 .qmi_service_ins_id = ATH11K_QMI_WLFW_SERVICE_INS_ID_V01_QCN9074,
311 .hw_ops = &qcn9074_ops,
312 .ring_mask = &ath11k_hw_ring_mask_qcn9074,
313 .internal_sleep_clock = false,
314 .regs = &qcn9074_regs,
315 .host_ce_config = ath11k_host_ce_config_qcn9074,
316 .ce_count = 6,
317 .target_ce_config = ath11k_target_ce_config_wlan_qcn9074,
318 .target_ce_count = 9,
319 .svc_to_ce_map = ath11k_target_service_to_ce_map_wlan_qcn9074,
320 .svc_to_ce_map_len = 18,
321 .ce_ie_addr = &ath11k_ce_ie_addr_ipq8074,
322 .rxdma1_enable = true,
323 .num_rxdma_per_pdev = 1,
324 .rx_mac_buf_ring = false,
325 .vdev_start_delay = false,
326 .htt_peer_map_v2 = true,
327
328 .spectral = {
329 .fft_sz = 2,
330 .fft_pad_sz = 0,
331 .summary_pad_sz = 16,
332 .fft_hdr_len = 24,
333 .max_fft_bins = 1024,
334 .fragment_160mhz = false,
335 },
336
337 .interface_modes = BIT(NL80211_IFTYPE_STATION) |
338 BIT(NL80211_IFTYPE_AP) |
339 BIT(NL80211_IFTYPE_MESH_POINT),
340 .supports_monitor = true,
341 .full_monitor_mode = true,
342 .supports_shadow_regs = false,
343 .idle_ps = false,
344 .supports_sta_ps = false,
345 .coldboot_cal_mm = false,
346 .coldboot_cal_ftm = true,
347 .cbcal_restart_fw = true,
348 .fw_mem_mode = 2,
349 .num_vdevs = 8,
350 .num_peers = 128,
351 .supports_suspend = false,
352 .hal_desc_sz = sizeof(struct hal_rx_desc_qcn9074),
353 .supports_regdb = false,
354 .fix_l1ss = true,
355 .credit_flow = false,
356 .max_tx_ring = DP_TCL_NUM_RING_MAX,
357 .hal_params = &ath11k_hw_hal_params_ipq8074,
358 .supports_dynamic_smps_6ghz = true,
359 .alloc_cacheable_memory = true,
360 .supports_rssi_stats = false,
361 .fw_wmi_diag_event = false,
362 .current_cc_support = false,
363 .dbr_debug_support = true,
364 .global_reset = false,
365 .bios_sar_capa = NULL,
366 .m3_fw_support = true,
367 .fixed_bdf_addr = false,
368 .fixed_mem_region = false,
369 .static_window_map = true,
370 .hybrid_bus_type = false,
371 .fixed_fw_mem = false,
372 .support_off_channel_tx = false,
373 .supports_multi_bssid = false,
374
375 .sram_dump = {},
376
377 .tcl_ring_retry = true,
378 .tx_ring_size = DP_TCL_DATA_RING_SIZE,
379 .smp2p_wow_exit = false,
380 .support_fw_mac_sequence = false,
381 .support_dual_stations = false,
382 },
383 {
384 .name = "wcn6855 hw2.0",
385 .hw_rev = ATH11K_HW_WCN6855_HW20,
386 .fw = {
387 .dir = "WCN6855/hw2.0",
388 .board_size = 256 * 1024,
389 .cal_offset = 128 * 1024,
390 },
391 .max_radios = 3,
392 .bdf_addr = 0x4B0C0000,
393 .hw_ops = &wcn6855_ops,
394 .ring_mask = &ath11k_hw_ring_mask_qca6390,
395 .internal_sleep_clock = true,
396 .regs = &wcn6855_regs,
397 .qmi_service_ins_id = ATH11K_QMI_WLFW_SERVICE_INS_ID_V01_QCA6390,
398 .host_ce_config = ath11k_host_ce_config_qca6390,
399 .ce_count = 9,
400 .target_ce_config = ath11k_target_ce_config_wlan_qca6390,
401 .target_ce_count = 9,
402 .svc_to_ce_map = ath11k_target_service_to_ce_map_wlan_qca6390,
403 .svc_to_ce_map_len = 14,
404 .ce_ie_addr = &ath11k_ce_ie_addr_ipq8074,
405 .single_pdev_only = true,
406 .rxdma1_enable = false,
407 .num_rxdma_per_pdev = 2,
408 .rx_mac_buf_ring = true,
409 .vdev_start_delay = true,
410 .htt_peer_map_v2 = false,
411
412 .spectral = {
413 .fft_sz = 0,
414 .fft_pad_sz = 0,
415 .summary_pad_sz = 0,
416 .fft_hdr_len = 0,
417 .max_fft_bins = 0,
418 .fragment_160mhz = false,
419 },
420
421 .interface_modes = BIT(NL80211_IFTYPE_STATION) |
422 BIT(NL80211_IFTYPE_AP) |
423 BIT(NL80211_IFTYPE_P2P_DEVICE) |
424 BIT(NL80211_IFTYPE_P2P_CLIENT) |
425 BIT(NL80211_IFTYPE_P2P_GO),
426 .supports_monitor = false,
427 .full_monitor_mode = false,
428 .supports_shadow_regs = true,
429 .idle_ps = true,
430 .supports_sta_ps = true,
431 .coldboot_cal_mm = false,
432 .coldboot_cal_ftm = false,
433 .cbcal_restart_fw = false,
434 .fw_mem_mode = 0,
435 .num_vdevs = 2 + 1,
436 .num_peers = 512,
437 .supports_suspend = true,
438 .hal_desc_sz = sizeof(struct hal_rx_desc_wcn6855),
439 .supports_regdb = true,
440 .fix_l1ss = false,
441 .credit_flow = true,
442 .max_tx_ring = DP_TCL_NUM_RING_MAX_QCA6390,
443 .hal_params = &ath11k_hw_hal_params_qca6390,
444 .supports_dynamic_smps_6ghz = false,
445 .alloc_cacheable_memory = false,
446 .supports_rssi_stats = true,
447 .fw_wmi_diag_event = true,
448 .current_cc_support = true,
449 .dbr_debug_support = false,
450 .global_reset = true,
451 .bios_sar_capa = &ath11k_hw_sar_capa_wcn6855,
452 .m3_fw_support = true,
453 .fixed_bdf_addr = false,
454 .fixed_mem_region = false,
455 .static_window_map = false,
456 .hybrid_bus_type = false,
457 .fixed_fw_mem = false,
458 .support_off_channel_tx = true,
459 .supports_multi_bssid = true,
460
461 .sram_dump = {
462 .start = 0x01400000,
463 .end = 0x0177ffff,
464 },
465
466 .tcl_ring_retry = true,
467 .tx_ring_size = DP_TCL_DATA_RING_SIZE,
468 .smp2p_wow_exit = false,
469 .support_fw_mac_sequence = true,
470 .support_dual_stations = true,
471 },
472 {
473 .name = "wcn6855 hw2.1",
474 .hw_rev = ATH11K_HW_WCN6855_HW21,
475 .fw = {
476 .dir = "WCN6855/hw2.1",
477 .board_size = 256 * 1024,
478 .cal_offset = 128 * 1024,
479 },
480 .max_radios = 3,
481 .bdf_addr = 0x4B0C0000,
482 .hw_ops = &wcn6855_ops,
483 .ring_mask = &ath11k_hw_ring_mask_qca6390,
484 .internal_sleep_clock = true,
485 .regs = &wcn6855_regs,
486 .qmi_service_ins_id = ATH11K_QMI_WLFW_SERVICE_INS_ID_V01_QCA6390,
487 .host_ce_config = ath11k_host_ce_config_qca6390,
488 .ce_count = 9,
489 .target_ce_config = ath11k_target_ce_config_wlan_qca6390,
490 .target_ce_count = 9,
491 .svc_to_ce_map = ath11k_target_service_to_ce_map_wlan_qca6390,
492 .svc_to_ce_map_len = 14,
493 .single_pdev_only = true,
494 .rxdma1_enable = false,
495 .num_rxdma_per_pdev = 2,
496 .rx_mac_buf_ring = true,
497 .vdev_start_delay = true,
498 .htt_peer_map_v2 = false,
499
500 .spectral = {
501 .fft_sz = 0,
502 .fft_pad_sz = 0,
503 .summary_pad_sz = 0,
504 .fft_hdr_len = 0,
505 .max_fft_bins = 0,
506 .fragment_160mhz = false,
507 },
508
509 .interface_modes = BIT(NL80211_IFTYPE_STATION) |
510 BIT(NL80211_IFTYPE_AP) |
511 BIT(NL80211_IFTYPE_P2P_DEVICE) |
512 BIT(NL80211_IFTYPE_P2P_CLIENT) |
513 BIT(NL80211_IFTYPE_P2P_GO),
514 .supports_monitor = false,
515 .supports_shadow_regs = true,
516 .idle_ps = true,
517 .supports_sta_ps = true,
518 .coldboot_cal_mm = false,
519 .coldboot_cal_ftm = false,
520 .cbcal_restart_fw = false,
521 .fw_mem_mode = 0,
522 .num_vdevs = 2 + 1,
523 .num_peers = 512,
524 .supports_suspend = true,
525 .hal_desc_sz = sizeof(struct hal_rx_desc_wcn6855),
526 .supports_regdb = true,
527 .fix_l1ss = false,
528 .credit_flow = true,
529 .max_tx_ring = DP_TCL_NUM_RING_MAX_QCA6390,
530 .hal_params = &ath11k_hw_hal_params_qca6390,
531 .supports_dynamic_smps_6ghz = false,
532 .alloc_cacheable_memory = false,
533 .supports_rssi_stats = true,
534 .fw_wmi_diag_event = true,
535 .current_cc_support = true,
536 .dbr_debug_support = false,
537 .global_reset = true,
538 .bios_sar_capa = &ath11k_hw_sar_capa_wcn6855,
539 .m3_fw_support = true,
540 .fixed_bdf_addr = false,
541 .fixed_mem_region = false,
542 .static_window_map = false,
543 .hybrid_bus_type = false,
544 .fixed_fw_mem = false,
545 .support_off_channel_tx = true,
546 .supports_multi_bssid = true,
547
548 .sram_dump = {
549 .start = 0x01400000,
550 .end = 0x0177ffff,
551 },
552
553 .tcl_ring_retry = true,
554 .tx_ring_size = DP_TCL_DATA_RING_SIZE,
555 .smp2p_wow_exit = false,
556 .support_fw_mac_sequence = true,
557 .support_dual_stations = true,
558 },
559 {
560 .name = "wcn6750 hw1.0",
561 .hw_rev = ATH11K_HW_WCN6750_HW10,
562 .fw = {
563 .dir = "WCN6750/hw1.0",
564 .board_size = 256 * 1024,
565 .cal_offset = 128 * 1024,
566 },
567 .max_radios = 1,
568 .bdf_addr = 0x4B0C0000,
569 .hw_ops = &wcn6750_ops,
570 .ring_mask = &ath11k_hw_ring_mask_wcn6750,
571 .internal_sleep_clock = false,
572 .regs = &wcn6750_regs,
573 .qmi_service_ins_id = ATH11K_QMI_WLFW_SERVICE_INS_ID_V01_WCN6750,
574 .host_ce_config = ath11k_host_ce_config_qca6390,
575 .ce_count = 9,
576 .target_ce_config = ath11k_target_ce_config_wlan_qca6390,
577 .target_ce_count = 9,
578 .svc_to_ce_map = ath11k_target_service_to_ce_map_wlan_qca6390,
579 .svc_to_ce_map_len = 14,
580 .ce_ie_addr = &ath11k_ce_ie_addr_ipq8074,
581 .single_pdev_only = true,
582 .rxdma1_enable = false,
583 .num_rxdma_per_pdev = 1,
584 .rx_mac_buf_ring = true,
585 .vdev_start_delay = true,
586 .htt_peer_map_v2 = false,
587
588 .spectral = {
589 .fft_sz = 0,
590 .fft_pad_sz = 0,
591 .summary_pad_sz = 0,
592 .fft_hdr_len = 0,
593 .max_fft_bins = 0,
594 .fragment_160mhz = false,
595 },
596
597 .interface_modes = BIT(NL80211_IFTYPE_STATION) |
598 BIT(NL80211_IFTYPE_AP),
599 .supports_monitor = false,
600 .supports_shadow_regs = true,
601 .idle_ps = true,
602 .supports_sta_ps = true,
603 .coldboot_cal_mm = true,
604 .coldboot_cal_ftm = true,
605 .cbcal_restart_fw = false,
606 .fw_mem_mode = 0,
607 .num_vdevs = 3,
608 .num_peers = 512,
609 .supports_suspend = false,
610 .hal_desc_sz = sizeof(struct hal_rx_desc_qcn9074),
611 .supports_regdb = true,
612 .fix_l1ss = false,
613 .credit_flow = true,
614 .max_tx_ring = DP_TCL_NUM_RING_MAX,
615 .hal_params = &ath11k_hw_hal_params_wcn6750,
616 .supports_dynamic_smps_6ghz = false,
617 .alloc_cacheable_memory = false,
618 .supports_rssi_stats = true,
619 .fw_wmi_diag_event = false,
620 .current_cc_support = true,
621 .dbr_debug_support = false,
622 .global_reset = false,
623 .bios_sar_capa = &ath11k_hw_sar_capa_wcn6855,
624 .m3_fw_support = false,
625 .fixed_bdf_addr = false,
626 .fixed_mem_region = false,
627 .static_window_map = true,
628 .hybrid_bus_type = true,
629 .fixed_fw_mem = true,
630 .support_off_channel_tx = true,
631 .supports_multi_bssid = true,
632
633 .sram_dump = {},
634
635 .tcl_ring_retry = false,
636 .tx_ring_size = DP_TCL_DATA_RING_SIZE_WCN6750,
637 .smp2p_wow_exit = true,
638 .support_fw_mac_sequence = true,
639 .support_dual_stations = false,
640 },
641 {
642 .hw_rev = ATH11K_HW_IPQ5018_HW10,
643 .name = "ipq5018 hw1.0",
644 .fw = {
645 .dir = "IPQ5018/hw1.0",
646 .board_size = 256 * 1024,
647 .cal_offset = 128 * 1024,
648 },
649 .max_radios = MAX_RADIOS_5018,
650 .bdf_addr = 0x4BA00000,
651 /* hal_desc_sz and hw ops are similar to qcn9074 */
652 .hal_desc_sz = sizeof(struct hal_rx_desc_qcn9074),
653 .qmi_service_ins_id = ATH11K_QMI_WLFW_SERVICE_INS_ID_V01_IPQ8074,
654 .ring_mask = &ath11k_hw_ring_mask_ipq8074,
655 .credit_flow = false,
656 .max_tx_ring = 1,
657 .spectral = {
658 .fft_sz = 2,
659 .fft_pad_sz = 0,
660 .summary_pad_sz = 16,
661 .fft_hdr_len = 24,
662 .max_fft_bins = 1024,
663 },
664 .internal_sleep_clock = false,
665 .regs = &ipq5018_regs,
666 .hw_ops = &ipq5018_ops,
667 .host_ce_config = ath11k_host_ce_config_qcn9074,
668 .ce_count = CE_CNT_5018,
669 .target_ce_config = ath11k_target_ce_config_wlan_ipq5018,
670 .target_ce_count = TARGET_CE_CNT_5018,
671 .svc_to_ce_map = ath11k_target_service_to_ce_map_wlan_ipq5018,
672 .svc_to_ce_map_len = SVC_CE_MAP_LEN_5018,
673 .ce_ie_addr = &ath11k_ce_ie_addr_ipq5018,
674 .ce_remap = &ath11k_ce_remap_ipq5018,
675 .rxdma1_enable = true,
676 .num_rxdma_per_pdev = RXDMA_PER_PDEV_5018,
677 .rx_mac_buf_ring = false,
678 .vdev_start_delay = false,
679 .htt_peer_map_v2 = true,
680 .interface_modes = BIT(NL80211_IFTYPE_STATION) |
681 BIT(NL80211_IFTYPE_AP) |
682 BIT(NL80211_IFTYPE_MESH_POINT),
683 .supports_monitor = false,
684 .supports_sta_ps = false,
685 .supports_shadow_regs = false,
686 .fw_mem_mode = 0,
687 .num_vdevs = 16 + 1,
688 .num_peers = 512,
689 .supports_regdb = false,
690 .idle_ps = false,
691 .supports_suspend = false,
692 .hal_params = &ath11k_hw_hal_params_ipq8074,
693 .single_pdev_only = false,
694 .coldboot_cal_mm = true,
695 .coldboot_cal_ftm = true,
696 .cbcal_restart_fw = true,
697 .fix_l1ss = true,
698 .supports_dynamic_smps_6ghz = false,
699 .alloc_cacheable_memory = true,
700 .supports_rssi_stats = false,
701 .fw_wmi_diag_event = false,
702 .current_cc_support = false,
703 .dbr_debug_support = true,
704 .global_reset = false,
705 .bios_sar_capa = NULL,
706 .m3_fw_support = false,
707 .fixed_bdf_addr = true,
708 .fixed_mem_region = true,
709 .static_window_map = false,
710 .hybrid_bus_type = false,
711 .fixed_fw_mem = false,
712 .support_off_channel_tx = false,
713 .supports_multi_bssid = false,
714
715 .sram_dump = {},
716
717 .tcl_ring_retry = true,
718 .tx_ring_size = DP_TCL_DATA_RING_SIZE,
719 .smp2p_wow_exit = false,
720 .support_fw_mac_sequence = false,
721 .support_dual_stations = false,
722 },
723 {
724 .name = "qca2066 hw2.1",
725 .hw_rev = ATH11K_HW_QCA2066_HW21,
726 .fw = {
727 .dir = "QCA2066/hw2.1",
728 .board_size = 256 * 1024,
729 .cal_offset = 128 * 1024,
730 },
731 .max_radios = 3,
732 .bdf_addr = 0x4B0C0000,
733 .hw_ops = &wcn6855_ops,
734 .ring_mask = &ath11k_hw_ring_mask_qca6390,
735 .internal_sleep_clock = true,
736 .regs = &wcn6855_regs,
737 .qmi_service_ins_id = ATH11K_QMI_WLFW_SERVICE_INS_ID_V01_QCA6390,
738 .host_ce_config = ath11k_host_ce_config_qca6390,
739 .ce_count = 9,
740 .target_ce_config = ath11k_target_ce_config_wlan_qca6390,
741 .target_ce_count = 9,
742 .svc_to_ce_map = ath11k_target_service_to_ce_map_wlan_qca6390,
743 .svc_to_ce_map_len = 14,
744 .ce_ie_addr = &ath11k_ce_ie_addr_ipq8074,
745 .single_pdev_only = true,
746 .rxdma1_enable = false,
747 .num_rxdma_per_pdev = 2,
748 .rx_mac_buf_ring = true,
749 .vdev_start_delay = true,
750 .htt_peer_map_v2 = false,
751
752 .spectral = {
753 .fft_sz = 0,
754 .fft_pad_sz = 0,
755 .summary_pad_sz = 0,
756 .fft_hdr_len = 0,
757 .max_fft_bins = 0,
758 .fragment_160mhz = false,
759 },
760
761 .interface_modes = BIT(NL80211_IFTYPE_STATION) |
762 BIT(NL80211_IFTYPE_AP) |
763 BIT(NL80211_IFTYPE_P2P_DEVICE) |
764 BIT(NL80211_IFTYPE_P2P_CLIENT) |
765 BIT(NL80211_IFTYPE_P2P_GO),
766 .supports_monitor = false,
767 .full_monitor_mode = false,
768 .supports_shadow_regs = true,
769 .idle_ps = true,
770 .supports_sta_ps = true,
771 .coldboot_cal_mm = false,
772 .coldboot_cal_ftm = false,
773 .cbcal_restart_fw = false,
774 .fw_mem_mode = 0,
775 .num_vdevs = 2 + 1,
776 .num_peers = 512,
777 .supports_suspend = true,
778 .hal_desc_sz = sizeof(struct hal_rx_desc_wcn6855),
779 .supports_regdb = true,
780 .fix_l1ss = false,
781 .credit_flow = true,
782 .max_tx_ring = DP_TCL_NUM_RING_MAX_QCA6390,
783 .hal_params = &ath11k_hw_hal_params_qca6390,
784 .supports_dynamic_smps_6ghz = false,
785 .alloc_cacheable_memory = false,
786 .supports_rssi_stats = true,
787 .fw_wmi_diag_event = true,
788 .current_cc_support = true,
789 .dbr_debug_support = false,
790 .global_reset = true,
791 .bios_sar_capa = &ath11k_hw_sar_capa_wcn6855,
792 .m3_fw_support = true,
793 .fixed_bdf_addr = false,
794 .fixed_mem_region = false,
795 .static_window_map = false,
796 .hybrid_bus_type = false,
797 .fixed_fw_mem = false,
798 .support_off_channel_tx = true,
799 .supports_multi_bssid = true,
800
801 .sram_dump = {
802 .start = 0x01400000,
803 .end = 0x0177ffff,
804 },
805
806 .tcl_ring_retry = true,
807 .tx_ring_size = DP_TCL_DATA_RING_SIZE,
808 .smp2p_wow_exit = false,
809 .support_fw_mac_sequence = true,
810 .support_dual_stations = true,
811 },
812 };
813
814 static const struct dmi_system_id ath11k_pm_quirk_table[] = {
815 {
816 .driver_data = (void *)ATH11K_PM_WOW,
817 .matches = {
818 DMI_MATCH(DMI_BOARD_VENDOR, "LENOVO"),
819 DMI_MATCH(DMI_PRODUCT_NAME, "21J4"),
820 },
821 },
822 {
823 .driver_data = (void *)ATH11K_PM_WOW,
824 .matches = {
825 DMI_MATCH(DMI_BOARD_VENDOR, "LENOVO"),
826 DMI_MATCH(DMI_PRODUCT_NAME, "21K4"),
827 },
828 },
829 {
830 .driver_data = (void *)ATH11K_PM_WOW,
831 .matches = {
832 DMI_MATCH(DMI_BOARD_VENDOR, "LENOVO"),
833 DMI_MATCH(DMI_PRODUCT_NAME, "21K6"),
834 },
835 },
836 {
837 .driver_data = (void *)ATH11K_PM_WOW,
838 .matches = {
839 DMI_MATCH(DMI_BOARD_VENDOR, "LENOVO"),
840 DMI_MATCH(DMI_PRODUCT_NAME, "21K8"),
841 },
842 },
843 {
844 .driver_data = (void *)ATH11K_PM_WOW,
845 .matches = {
846 DMI_MATCH(DMI_BOARD_VENDOR, "LENOVO"),
847 DMI_MATCH(DMI_PRODUCT_NAME, "21KA"),
848 },
849 },
850 {
851 .driver_data = (void *)ATH11K_PM_WOW,
852 .matches = {
853 DMI_MATCH(DMI_BOARD_VENDOR, "LENOVO"),
854 DMI_MATCH(DMI_PRODUCT_NAME, "21F9"),
855 },
856 },
857 {}
858 };
859
ath11k_core_get_single_pdev(struct ath11k_base * ab)860 static inline struct ath11k_pdev *ath11k_core_get_single_pdev(struct ath11k_base *ab)
861 {
862 WARN_ON(!ab->hw_params.single_pdev_only);
863
864 return &ab->pdevs[0];
865 }
866
ath11k_fw_stats_pdevs_free(struct list_head * head)867 void ath11k_fw_stats_pdevs_free(struct list_head *head)
868 {
869 struct ath11k_fw_stats_pdev *i, *tmp;
870
871 list_for_each_entry_safe(i, tmp, head, list) {
872 list_del(&i->list);
873 kfree(i);
874 }
875 }
876
ath11k_fw_stats_vdevs_free(struct list_head * head)877 void ath11k_fw_stats_vdevs_free(struct list_head *head)
878 {
879 struct ath11k_fw_stats_vdev *i, *tmp;
880
881 list_for_each_entry_safe(i, tmp, head, list) {
882 list_del(&i->list);
883 kfree(i);
884 }
885 }
886
ath11k_fw_stats_bcn_free(struct list_head * head)887 void ath11k_fw_stats_bcn_free(struct list_head *head)
888 {
889 struct ath11k_fw_stats_bcn *i, *tmp;
890
891 list_for_each_entry_safe(i, tmp, head, list) {
892 list_del(&i->list);
893 kfree(i);
894 }
895 }
896
ath11k_fw_stats_init(struct ath11k * ar)897 void ath11k_fw_stats_init(struct ath11k *ar)
898 {
899 INIT_LIST_HEAD(&ar->fw_stats.pdevs);
900 INIT_LIST_HEAD(&ar->fw_stats.vdevs);
901 INIT_LIST_HEAD(&ar->fw_stats.bcn);
902
903 init_completion(&ar->fw_stats_complete);
904 init_completion(&ar->fw_stats_done);
905 }
906
ath11k_fw_stats_free(struct ath11k_fw_stats * stats)907 void ath11k_fw_stats_free(struct ath11k_fw_stats *stats)
908 {
909 ath11k_fw_stats_pdevs_free(&stats->pdevs);
910 ath11k_fw_stats_vdevs_free(&stats->vdevs);
911 ath11k_fw_stats_bcn_free(&stats->bcn);
912 }
913
ath11k_core_coldboot_cal_support(struct ath11k_base * ab)914 bool ath11k_core_coldboot_cal_support(struct ath11k_base *ab)
915 {
916 if (!ath11k_cold_boot_cal)
917 return false;
918
919 if (ath11k_ftm_mode)
920 return ab->hw_params.coldboot_cal_ftm;
921
922 else
923 return ab->hw_params.coldboot_cal_mm;
924 }
925
ath11k_core_suspend(struct ath11k_base * ab)926 int ath11k_core_suspend(struct ath11k_base *ab)
927 {
928 int ret;
929 struct ath11k_pdev *pdev;
930 struct ath11k *ar;
931
932 if (!ab->hw_params.supports_suspend)
933 return -EOPNOTSUPP;
934
935 /* so far single_pdev_only chips have supports_suspend as true
936 * and only the first pdev is valid.
937 */
938 pdev = ath11k_core_get_single_pdev(ab);
939 ar = pdev->ar;
940 if (!ar || ar->state != ATH11K_STATE_OFF)
941 return 0;
942
943 ret = ath11k_dp_rx_pktlog_stop(ab, true);
944 if (ret) {
945 ath11k_warn(ab, "failed to stop dp rx (and timer) pktlog during suspend: %d\n",
946 ret);
947 return ret;
948 }
949
950 ret = ath11k_mac_wait_tx_complete(ar);
951 if (ret) {
952 ath11k_warn(ab, "failed to wait tx complete: %d\n", ret);
953 return ret;
954 }
955
956 ret = ath11k_wow_enable(ab);
957 if (ret) {
958 ath11k_warn(ab, "failed to enable wow during suspend: %d\n", ret);
959 return ret;
960 }
961
962 ret = ath11k_dp_rx_pktlog_stop(ab, false);
963 if (ret) {
964 ath11k_warn(ab, "failed to stop dp rx pktlog during suspend: %d\n",
965 ret);
966 return ret;
967 }
968
969 ath11k_ce_stop_shadow_timers(ab);
970 ath11k_dp_stop_shadow_timers(ab);
971
972 ath11k_hif_irq_disable(ab);
973 ath11k_hif_ce_irq_disable(ab);
974
975 ret = ath11k_hif_suspend(ab);
976 if (ret) {
977 ath11k_warn(ab, "failed to suspend hif: %d\n", ret);
978 return ret;
979 }
980
981 return 0;
982 }
983 EXPORT_SYMBOL(ath11k_core_suspend);
984
ath11k_core_resume(struct ath11k_base * ab)985 int ath11k_core_resume(struct ath11k_base *ab)
986 {
987 int ret;
988 struct ath11k_pdev *pdev;
989 struct ath11k *ar;
990
991 if (!ab->hw_params.supports_suspend)
992 return -EOPNOTSUPP;
993
994 /* so far signle_pdev_only chips have supports_suspend as true
995 * and only the first pdev is valid.
996 */
997 pdev = ath11k_core_get_single_pdev(ab);
998 ar = pdev->ar;
999 if (!ar || ar->state != ATH11K_STATE_OFF)
1000 return 0;
1001
1002 ret = ath11k_hif_resume(ab);
1003 if (ret) {
1004 ath11k_warn(ab, "failed to resume hif during resume: %d\n", ret);
1005 return ret;
1006 }
1007
1008 ath11k_hif_ce_irq_enable(ab);
1009 ath11k_hif_irq_enable(ab);
1010
1011 ret = ath11k_dp_rx_pktlog_start(ab);
1012 if (ret) {
1013 ath11k_warn(ab, "failed to start rx pktlog during resume: %d\n",
1014 ret);
1015 return ret;
1016 }
1017
1018 ret = ath11k_wow_wakeup(ab);
1019 if (ret) {
1020 ath11k_warn(ab, "failed to wakeup wow during resume: %d\n", ret);
1021 return ret;
1022 }
1023
1024 return 0;
1025 }
1026 EXPORT_SYMBOL(ath11k_core_resume);
1027
ath11k_core_check_cc_code_bdfext(const struct dmi_header * hdr,void * data)1028 static void ath11k_core_check_cc_code_bdfext(const struct dmi_header *hdr, void *data)
1029 {
1030 struct ath11k_base *ab = data;
1031 const char *magic = ATH11K_SMBIOS_BDF_EXT_MAGIC;
1032 struct ath11k_smbios_bdf *smbios = (struct ath11k_smbios_bdf *)hdr;
1033 ssize_t copied;
1034 size_t len;
1035 int i;
1036
1037 if (ab->qmi.target.bdf_ext[0] != '\0')
1038 return;
1039
1040 if (hdr->type != ATH11K_SMBIOS_BDF_EXT_TYPE)
1041 return;
1042
1043 if (hdr->length != ATH11K_SMBIOS_BDF_EXT_LENGTH) {
1044 ath11k_dbg(ab, ATH11K_DBG_BOOT,
1045 "wrong smbios bdf ext type length (%d).\n",
1046 hdr->length);
1047 return;
1048 }
1049
1050 spin_lock_bh(&ab->base_lock);
1051
1052 switch (smbios->country_code_flag) {
1053 case ATH11K_SMBIOS_CC_ISO:
1054 ab->new_alpha2[0] = (smbios->cc_code >> 8) & 0xff;
1055 ab->new_alpha2[1] = smbios->cc_code & 0xff;
1056 ath11k_dbg(ab, ATH11K_DBG_BOOT, "smbios cc_code %c%c\n",
1057 ab->new_alpha2[0], ab->new_alpha2[1]);
1058 break;
1059 case ATH11K_SMBIOS_CC_WW:
1060 ab->new_alpha2[0] = '0';
1061 ab->new_alpha2[1] = '0';
1062 ath11k_dbg(ab, ATH11K_DBG_BOOT, "smbios worldwide regdomain\n");
1063 break;
1064 default:
1065 ath11k_dbg(ab, ATH11K_DBG_BOOT, "ignore smbios country code setting %d\n",
1066 smbios->country_code_flag);
1067 break;
1068 }
1069
1070 spin_unlock_bh(&ab->base_lock);
1071
1072 if (!smbios->bdf_enabled) {
1073 ath11k_dbg(ab, ATH11K_DBG_BOOT, "bdf variant name not found.\n");
1074 return;
1075 }
1076
1077 /* Only one string exists (per spec) */
1078 if (memcmp(smbios->bdf_ext, magic, strlen(magic)) != 0) {
1079 ath11k_dbg(ab, ATH11K_DBG_BOOT,
1080 "bdf variant magic does not match.\n");
1081 return;
1082 }
1083
1084 len = min_t(size_t,
1085 strlen(smbios->bdf_ext), sizeof(ab->qmi.target.bdf_ext));
1086 for (i = 0; i < len; i++) {
1087 if (!isascii(smbios->bdf_ext[i]) || !isprint(smbios->bdf_ext[i])) {
1088 ath11k_dbg(ab, ATH11K_DBG_BOOT,
1089 "bdf variant name contains non ascii chars.\n");
1090 return;
1091 }
1092 }
1093
1094 /* Copy extension name without magic prefix */
1095 copied = strscpy(ab->qmi.target.bdf_ext, smbios->bdf_ext + strlen(magic),
1096 sizeof(ab->qmi.target.bdf_ext));
1097 if (copied < 0) {
1098 ath11k_dbg(ab, ATH11K_DBG_BOOT,
1099 "bdf variant string is longer than the buffer can accommodate\n");
1100 return;
1101 }
1102
1103 ath11k_dbg(ab, ATH11K_DBG_BOOT,
1104 "found and validated bdf variant smbios_type 0x%x bdf %s\n",
1105 ATH11K_SMBIOS_BDF_EXT_TYPE, ab->qmi.target.bdf_ext);
1106 }
1107
ath11k_core_check_smbios(struct ath11k_base * ab)1108 int ath11k_core_check_smbios(struct ath11k_base *ab)
1109 {
1110 ab->qmi.target.bdf_ext[0] = '\0';
1111 dmi_walk(ath11k_core_check_cc_code_bdfext, ab);
1112
1113 if (ab->qmi.target.bdf_ext[0] == '\0')
1114 return -ENODATA;
1115
1116 return 0;
1117 }
1118
ath11k_core_check_dt(struct ath11k_base * ab)1119 int ath11k_core_check_dt(struct ath11k_base *ab)
1120 {
1121 size_t max_len = sizeof(ab->qmi.target.bdf_ext);
1122 const char *variant = NULL;
1123 struct device_node *node;
1124
1125 node = ab->dev->of_node;
1126 if (!node)
1127 return -ENOENT;
1128
1129 of_property_read_string(node, "qcom,ath11k-calibration-variant",
1130 &variant);
1131 if (!variant)
1132 return -ENODATA;
1133
1134 if (strscpy(ab->qmi.target.bdf_ext, variant, max_len) < 0)
1135 ath11k_dbg(ab, ATH11K_DBG_BOOT,
1136 "bdf variant string is longer than the buffer can accommodate (variant: %s)\n",
1137 variant);
1138
1139 return 0;
1140 }
1141
1142 enum ath11k_bdf_name_type {
1143 ATH11K_BDF_NAME_FULL,
1144 ATH11K_BDF_NAME_BUS_NAME,
1145 ATH11K_BDF_NAME_CHIP_ID,
1146 };
1147
__ath11k_core_create_board_name(struct ath11k_base * ab,char * name,size_t name_len,bool with_variant,enum ath11k_bdf_name_type name_type)1148 static int __ath11k_core_create_board_name(struct ath11k_base *ab, char *name,
1149 size_t name_len, bool with_variant,
1150 enum ath11k_bdf_name_type name_type)
1151 {
1152 /* strlen(',variant=') + strlen(ab->qmi.target.bdf_ext) */
1153 char variant[9 + ATH11K_QMI_BDF_EXT_STR_LENGTH] = { 0 };
1154
1155 if (with_variant && ab->qmi.target.bdf_ext[0] != '\0')
1156 scnprintf(variant, sizeof(variant), ",variant=%s",
1157 ab->qmi.target.bdf_ext);
1158
1159 switch (ab->id.bdf_search) {
1160 case ATH11K_BDF_SEARCH_BUS_AND_BOARD:
1161 switch (name_type) {
1162 case ATH11K_BDF_NAME_FULL:
1163 scnprintf(name, name_len,
1164 "bus=%s,vendor=%04x,device=%04x,subsystem-vendor=%04x,subsystem-device=%04x,qmi-chip-id=%d,qmi-board-id=%d%s",
1165 ath11k_bus_str(ab->hif.bus),
1166 ab->id.vendor, ab->id.device,
1167 ab->id.subsystem_vendor,
1168 ab->id.subsystem_device,
1169 ab->qmi.target.chip_id,
1170 ab->qmi.target.board_id,
1171 variant);
1172 break;
1173 case ATH11K_BDF_NAME_BUS_NAME:
1174 scnprintf(name, name_len,
1175 "bus=%s",
1176 ath11k_bus_str(ab->hif.bus));
1177 break;
1178 case ATH11K_BDF_NAME_CHIP_ID:
1179 scnprintf(name, name_len,
1180 "bus=%s,qmi-chip-id=%d",
1181 ath11k_bus_str(ab->hif.bus),
1182 ab->qmi.target.chip_id);
1183 break;
1184 }
1185 break;
1186 default:
1187 scnprintf(name, name_len,
1188 "bus=%s,qmi-chip-id=%d,qmi-board-id=%d%s",
1189 ath11k_bus_str(ab->hif.bus),
1190 ab->qmi.target.chip_id,
1191 ab->qmi.target.board_id, variant);
1192 break;
1193 }
1194
1195 ath11k_dbg(ab, ATH11K_DBG_BOOT, "using board name '%s'\n", name);
1196
1197 return 0;
1198 }
1199
ath11k_core_create_board_name(struct ath11k_base * ab,char * name,size_t name_len)1200 static int ath11k_core_create_board_name(struct ath11k_base *ab, char *name,
1201 size_t name_len)
1202 {
1203 return __ath11k_core_create_board_name(ab, name, name_len, true,
1204 ATH11K_BDF_NAME_FULL);
1205 }
1206
ath11k_core_create_fallback_board_name(struct ath11k_base * ab,char * name,size_t name_len)1207 static int ath11k_core_create_fallback_board_name(struct ath11k_base *ab, char *name,
1208 size_t name_len)
1209 {
1210 return __ath11k_core_create_board_name(ab, name, name_len, false,
1211 ATH11K_BDF_NAME_FULL);
1212 }
1213
ath11k_core_create_bus_type_board_name(struct ath11k_base * ab,char * name,size_t name_len)1214 static int ath11k_core_create_bus_type_board_name(struct ath11k_base *ab, char *name,
1215 size_t name_len)
1216 {
1217 return __ath11k_core_create_board_name(ab, name, name_len, false,
1218 ATH11K_BDF_NAME_BUS_NAME);
1219 }
1220
ath11k_core_create_chip_id_board_name(struct ath11k_base * ab,char * name,size_t name_len)1221 static int ath11k_core_create_chip_id_board_name(struct ath11k_base *ab, char *name,
1222 size_t name_len)
1223 {
1224 return __ath11k_core_create_board_name(ab, name, name_len, false,
1225 ATH11K_BDF_NAME_CHIP_ID);
1226 }
1227
ath11k_core_firmware_request(struct ath11k_base * ab,const char * file)1228 const struct firmware *ath11k_core_firmware_request(struct ath11k_base *ab,
1229 const char *file)
1230 {
1231 const struct firmware *fw;
1232 char path[100];
1233 int ret;
1234
1235 if (file == NULL)
1236 return ERR_PTR(-ENOENT);
1237
1238 ath11k_core_create_firmware_path(ab, file, path, sizeof(path));
1239
1240 ret = firmware_request_nowarn(&fw, path, ab->dev);
1241 if (ret)
1242 return ERR_PTR(ret);
1243
1244 ath11k_dbg(ab, ATH11K_DBG_BOOT, "firmware request %s size %zu\n",
1245 path, fw->size);
1246
1247 return fw;
1248 }
1249
ath11k_core_free_bdf(struct ath11k_base * ab,struct ath11k_board_data * bd)1250 void ath11k_core_free_bdf(struct ath11k_base *ab, struct ath11k_board_data *bd)
1251 {
1252 if (!IS_ERR(bd->fw))
1253 release_firmware(bd->fw);
1254
1255 memset(bd, 0, sizeof(*bd));
1256 }
1257
ath11k_core_parse_bd_ie_board(struct ath11k_base * ab,struct ath11k_board_data * bd,const void * buf,size_t buf_len,const char * boardname,int ie_id,int name_id,int data_id)1258 static int ath11k_core_parse_bd_ie_board(struct ath11k_base *ab,
1259 struct ath11k_board_data *bd,
1260 const void *buf, size_t buf_len,
1261 const char *boardname,
1262 int ie_id,
1263 int name_id,
1264 int data_id)
1265 {
1266 const struct ath11k_fw_ie *hdr;
1267 bool name_match_found;
1268 int ret, board_ie_id;
1269 size_t board_ie_len;
1270 const void *board_ie_data;
1271
1272 name_match_found = false;
1273
1274 /* go through ATH11K_BD_IE_BOARD_/ATH11K_BD_IE_REGDB_ elements */
1275 while (buf_len > sizeof(struct ath11k_fw_ie)) {
1276 hdr = buf;
1277 board_ie_id = le32_to_cpu(hdr->id);
1278 board_ie_len = le32_to_cpu(hdr->len);
1279 board_ie_data = hdr->data;
1280
1281 buf_len -= sizeof(*hdr);
1282 buf += sizeof(*hdr);
1283
1284 if (buf_len < ALIGN(board_ie_len, 4)) {
1285 ath11k_err(ab, "invalid %s length: %zu < %zu\n",
1286 ath11k_bd_ie_type_str(ie_id),
1287 buf_len, ALIGN(board_ie_len, 4));
1288 ret = -EINVAL;
1289 goto out;
1290 }
1291
1292 if (board_ie_id == name_id) {
1293 ath11k_dbg_dump(ab, ATH11K_DBG_BOOT, "board name", "",
1294 board_ie_data, board_ie_len);
1295
1296 if (board_ie_len != strlen(boardname))
1297 goto next;
1298
1299 ret = memcmp(board_ie_data, boardname, strlen(boardname));
1300 if (ret)
1301 goto next;
1302
1303 name_match_found = true;
1304 ath11k_dbg(ab, ATH11K_DBG_BOOT,
1305 "found match %s for name '%s'",
1306 ath11k_bd_ie_type_str(ie_id),
1307 boardname);
1308 } else if (board_ie_id == data_id) {
1309 if (!name_match_found)
1310 /* no match found */
1311 goto next;
1312
1313 ath11k_dbg(ab, ATH11K_DBG_BOOT,
1314 "found %s for '%s'",
1315 ath11k_bd_ie_type_str(ie_id),
1316 boardname);
1317
1318 bd->data = board_ie_data;
1319 bd->len = board_ie_len;
1320
1321 ret = 0;
1322 goto out;
1323 } else {
1324 ath11k_warn(ab, "unknown %s id found: %d\n",
1325 ath11k_bd_ie_type_str(ie_id),
1326 board_ie_id);
1327 }
1328 next:
1329 /* jump over the padding */
1330 board_ie_len = ALIGN(board_ie_len, 4);
1331
1332 buf_len -= board_ie_len;
1333 buf += board_ie_len;
1334 }
1335
1336 /* no match found */
1337 ret = -ENOENT;
1338
1339 out:
1340 return ret;
1341 }
1342
ath11k_core_fetch_board_data_api_n(struct ath11k_base * ab,struct ath11k_board_data * bd,const char * boardname,int ie_id_match,int name_id,int data_id)1343 static int ath11k_core_fetch_board_data_api_n(struct ath11k_base *ab,
1344 struct ath11k_board_data *bd,
1345 const char *boardname,
1346 int ie_id_match,
1347 int name_id,
1348 int data_id)
1349 {
1350 size_t len, magic_len;
1351 const u8 *data;
1352 char *filename, filepath[100];
1353 size_t ie_len;
1354 struct ath11k_fw_ie *hdr;
1355 int ret, ie_id;
1356
1357 filename = ATH11K_BOARD_API2_FILE;
1358
1359 if (!bd->fw)
1360 bd->fw = ath11k_core_firmware_request(ab, filename);
1361
1362 if (IS_ERR(bd->fw))
1363 return PTR_ERR(bd->fw);
1364
1365 data = bd->fw->data;
1366 len = bd->fw->size;
1367
1368 ath11k_core_create_firmware_path(ab, filename,
1369 filepath, sizeof(filepath));
1370
1371 /* magic has extra null byte padded */
1372 magic_len = strlen(ATH11K_BOARD_MAGIC) + 1;
1373 if (len < magic_len) {
1374 ath11k_err(ab, "failed to find magic value in %s, file too short: %zu\n",
1375 filepath, len);
1376 ret = -EINVAL;
1377 goto err;
1378 }
1379
1380 if (memcmp(data, ATH11K_BOARD_MAGIC, magic_len)) {
1381 ath11k_err(ab, "found invalid board magic\n");
1382 ret = -EINVAL;
1383 goto err;
1384 }
1385
1386 /* magic is padded to 4 bytes */
1387 magic_len = ALIGN(magic_len, 4);
1388 if (len < magic_len) {
1389 ath11k_err(ab, "failed: %s too small to contain board data, len: %zu\n",
1390 filepath, len);
1391 ret = -EINVAL;
1392 goto err;
1393 }
1394
1395 data += magic_len;
1396 len -= magic_len;
1397
1398 while (len > sizeof(struct ath11k_fw_ie)) {
1399 hdr = (struct ath11k_fw_ie *)data;
1400 ie_id = le32_to_cpu(hdr->id);
1401 ie_len = le32_to_cpu(hdr->len);
1402
1403 len -= sizeof(*hdr);
1404 data = hdr->data;
1405
1406 if (len < ALIGN(ie_len, 4)) {
1407 ath11k_err(ab, "invalid length for board ie_id %d ie_len %zu len %zu\n",
1408 ie_id, ie_len, len);
1409 ret = -EINVAL;
1410 goto err;
1411 }
1412
1413 if (ie_id == ie_id_match) {
1414 ret = ath11k_core_parse_bd_ie_board(ab, bd, data,
1415 ie_len,
1416 boardname,
1417 ie_id_match,
1418 name_id,
1419 data_id);
1420 if (ret == -ENOENT)
1421 /* no match found, continue */
1422 goto next;
1423 else if (ret)
1424 /* there was an error, bail out */
1425 goto err;
1426 /* either found or error, so stop searching */
1427 goto out;
1428 }
1429 next:
1430 /* jump over the padding */
1431 ie_len = ALIGN(ie_len, 4);
1432
1433 len -= ie_len;
1434 data += ie_len;
1435 }
1436
1437 out:
1438 if (!bd->data || !bd->len) {
1439 ath11k_dbg(ab, ATH11K_DBG_BOOT,
1440 "failed to fetch %s for %s from %s\n",
1441 ath11k_bd_ie_type_str(ie_id_match),
1442 boardname, filepath);
1443 ret = -ENODATA;
1444 goto err;
1445 }
1446
1447 return 0;
1448
1449 err:
1450 ath11k_core_free_bdf(ab, bd);
1451 return ret;
1452 }
1453
ath11k_core_fetch_board_data_api_1(struct ath11k_base * ab,struct ath11k_board_data * bd,const char * name)1454 int ath11k_core_fetch_board_data_api_1(struct ath11k_base *ab,
1455 struct ath11k_board_data *bd,
1456 const char *name)
1457 {
1458 bd->fw = ath11k_core_firmware_request(ab, name);
1459
1460 if (IS_ERR(bd->fw))
1461 return PTR_ERR(bd->fw);
1462
1463 bd->data = bd->fw->data;
1464 bd->len = bd->fw->size;
1465
1466 return 0;
1467 }
1468
1469 #define BOARD_NAME_SIZE 200
ath11k_core_fetch_bdf(struct ath11k_base * ab,struct ath11k_board_data * bd)1470 int ath11k_core_fetch_bdf(struct ath11k_base *ab, struct ath11k_board_data *bd)
1471 {
1472 char *boardname = NULL, *fallback_boardname = NULL, *chip_id_boardname = NULL;
1473 char *filename, filepath[100];
1474 int bd_api;
1475 int ret = 0;
1476
1477 filename = ATH11K_BOARD_API2_FILE;
1478 boardname = kzalloc(BOARD_NAME_SIZE, GFP_KERNEL);
1479 if (!boardname) {
1480 ret = -ENOMEM;
1481 goto exit;
1482 }
1483
1484 ret = ath11k_core_create_board_name(ab, boardname, BOARD_NAME_SIZE);
1485 if (ret) {
1486 ath11k_err(ab, "failed to create board name: %d", ret);
1487 goto exit;
1488 }
1489
1490 bd_api = 2;
1491 ret = ath11k_core_fetch_board_data_api_n(ab, bd, boardname,
1492 ATH11K_BD_IE_BOARD,
1493 ATH11K_BD_IE_BOARD_NAME,
1494 ATH11K_BD_IE_BOARD_DATA);
1495 if (!ret)
1496 goto exit;
1497
1498 fallback_boardname = kzalloc(BOARD_NAME_SIZE, GFP_KERNEL);
1499 if (!fallback_boardname) {
1500 ret = -ENOMEM;
1501 goto exit;
1502 }
1503
1504 ret = ath11k_core_create_fallback_board_name(ab, fallback_boardname,
1505 BOARD_NAME_SIZE);
1506 if (ret) {
1507 ath11k_err(ab, "failed to create fallback board name: %d", ret);
1508 goto exit;
1509 }
1510
1511 ret = ath11k_core_fetch_board_data_api_n(ab, bd, fallback_boardname,
1512 ATH11K_BD_IE_BOARD,
1513 ATH11K_BD_IE_BOARD_NAME,
1514 ATH11K_BD_IE_BOARD_DATA);
1515 if (!ret)
1516 goto exit;
1517
1518 chip_id_boardname = kzalloc(BOARD_NAME_SIZE, GFP_KERNEL);
1519 if (!chip_id_boardname) {
1520 ret = -ENOMEM;
1521 goto exit;
1522 }
1523
1524 ret = ath11k_core_create_chip_id_board_name(ab, chip_id_boardname,
1525 BOARD_NAME_SIZE);
1526 if (ret) {
1527 ath11k_err(ab, "failed to create chip id board name: %d", ret);
1528 goto exit;
1529 }
1530
1531 ret = ath11k_core_fetch_board_data_api_n(ab, bd, chip_id_boardname,
1532 ATH11K_BD_IE_BOARD,
1533 ATH11K_BD_IE_BOARD_NAME,
1534 ATH11K_BD_IE_BOARD_DATA);
1535
1536 if (!ret)
1537 goto exit;
1538
1539 bd_api = 1;
1540 ret = ath11k_core_fetch_board_data_api_1(ab, bd, ATH11K_DEFAULT_BOARD_FILE);
1541 if (ret) {
1542 ath11k_core_create_firmware_path(ab, filename,
1543 filepath, sizeof(filepath));
1544 ath11k_err(ab, "failed to fetch board data for %s from %s\n",
1545 boardname, filepath);
1546 if (memcmp(boardname, fallback_boardname, strlen(boardname)))
1547 ath11k_err(ab, "failed to fetch board data for %s from %s\n",
1548 fallback_boardname, filepath);
1549
1550 ath11k_err(ab, "failed to fetch board data for %s from %s\n",
1551 chip_id_boardname, filepath);
1552
1553 ath11k_err(ab, "failed to fetch board.bin from %s\n",
1554 ab->hw_params.fw.dir);
1555 }
1556
1557 exit:
1558 kfree(boardname);
1559 kfree(fallback_boardname);
1560 kfree(chip_id_boardname);
1561
1562 if (!ret)
1563 ath11k_dbg(ab, ATH11K_DBG_BOOT, "using board api %d\n", bd_api);
1564
1565 return ret;
1566 }
1567
ath11k_core_fetch_regdb(struct ath11k_base * ab,struct ath11k_board_data * bd)1568 int ath11k_core_fetch_regdb(struct ath11k_base *ab, struct ath11k_board_data *bd)
1569 {
1570 char boardname[BOARD_NAME_SIZE], default_boardname[BOARD_NAME_SIZE];
1571 int ret;
1572
1573 ret = ath11k_core_create_board_name(ab, boardname, BOARD_NAME_SIZE);
1574 if (ret) {
1575 ath11k_dbg(ab, ATH11K_DBG_BOOT,
1576 "failed to create board name for regdb: %d", ret);
1577 goto exit;
1578 }
1579
1580 ret = ath11k_core_fetch_board_data_api_n(ab, bd, boardname,
1581 ATH11K_BD_IE_REGDB,
1582 ATH11K_BD_IE_REGDB_NAME,
1583 ATH11K_BD_IE_REGDB_DATA);
1584 if (!ret)
1585 goto exit;
1586
1587 ret = ath11k_core_create_bus_type_board_name(ab, default_boardname,
1588 BOARD_NAME_SIZE);
1589 if (ret) {
1590 ath11k_dbg(ab, ATH11K_DBG_BOOT,
1591 "failed to create default board name for regdb: %d", ret);
1592 goto exit;
1593 }
1594
1595 ret = ath11k_core_fetch_board_data_api_n(ab, bd, default_boardname,
1596 ATH11K_BD_IE_REGDB,
1597 ATH11K_BD_IE_REGDB_NAME,
1598 ATH11K_BD_IE_REGDB_DATA);
1599 if (!ret)
1600 goto exit;
1601
1602 ret = ath11k_core_fetch_board_data_api_1(ab, bd, ATH11K_REGDB_FILE_NAME);
1603 if (ret)
1604 ath11k_dbg(ab, ATH11K_DBG_BOOT, "failed to fetch %s from %s\n",
1605 ATH11K_REGDB_FILE_NAME, ab->hw_params.fw.dir);
1606
1607 exit:
1608 if (!ret)
1609 ath11k_dbg(ab, ATH11K_DBG_BOOT, "fetched regdb\n");
1610
1611 return ret;
1612 }
1613
ath11k_core_stop(struct ath11k_base * ab)1614 static void ath11k_core_stop(struct ath11k_base *ab)
1615 {
1616 if (!test_bit(ATH11K_FLAG_CRASH_FLUSH, &ab->dev_flags))
1617 ath11k_qmi_firmware_stop(ab);
1618
1619 ath11k_hif_stop(ab);
1620 ath11k_wmi_detach(ab);
1621 ath11k_dp_pdev_reo_cleanup(ab);
1622
1623 /* De-Init of components as needed */
1624 }
1625
ath11k_core_soc_create(struct ath11k_base * ab)1626 static int ath11k_core_soc_create(struct ath11k_base *ab)
1627 {
1628 int ret;
1629
1630 if (ath11k_ftm_mode) {
1631 ab->fw_mode = ATH11K_FIRMWARE_MODE_FTM;
1632 ath11k_info(ab, "Booting in factory test mode\n");
1633 }
1634
1635 ret = ath11k_qmi_init_service(ab);
1636 if (ret) {
1637 ath11k_err(ab, "failed to initialize qmi :%d\n", ret);
1638 return ret;
1639 }
1640
1641 ret = ath11k_debugfs_soc_create(ab);
1642 if (ret) {
1643 ath11k_err(ab, "failed to create ath11k debugfs\n");
1644 goto err_qmi_deinit;
1645 }
1646
1647 ret = ath11k_hif_power_up(ab);
1648 if (ret) {
1649 ath11k_err(ab, "failed to power up :%d\n", ret);
1650 goto err_debugfs_reg;
1651 }
1652
1653 return 0;
1654
1655 err_debugfs_reg:
1656 ath11k_debugfs_soc_destroy(ab);
1657 err_qmi_deinit:
1658 ath11k_qmi_deinit_service(ab);
1659 return ret;
1660 }
1661
ath11k_core_soc_destroy(struct ath11k_base * ab)1662 static void ath11k_core_soc_destroy(struct ath11k_base *ab)
1663 {
1664 ath11k_debugfs_soc_destroy(ab);
1665 ath11k_dp_free(ab);
1666 ath11k_reg_free(ab);
1667 ath11k_qmi_deinit_service(ab);
1668 }
1669
ath11k_core_pdev_create(struct ath11k_base * ab)1670 static int ath11k_core_pdev_create(struct ath11k_base *ab)
1671 {
1672 int ret;
1673
1674 ret = ath11k_debugfs_pdev_create(ab);
1675 if (ret) {
1676 ath11k_err(ab, "failed to create core pdev debugfs: %d\n", ret);
1677 return ret;
1678 }
1679
1680 ret = ath11k_dp_pdev_alloc(ab);
1681 if (ret) {
1682 ath11k_err(ab, "failed to attach DP pdev: %d\n", ret);
1683 goto err_pdev_debug;
1684 }
1685
1686 ret = ath11k_mac_register(ab);
1687 if (ret) {
1688 ath11k_err(ab, "failed register the radio with mac80211: %d\n", ret);
1689 goto err_dp_pdev_free;
1690 }
1691
1692 ret = ath11k_thermal_register(ab);
1693 if (ret) {
1694 ath11k_err(ab, "could not register thermal device: %d\n",
1695 ret);
1696 goto err_mac_unregister;
1697 }
1698
1699 ret = ath11k_spectral_init(ab);
1700 if (ret) {
1701 ath11k_err(ab, "failed to init spectral %d\n", ret);
1702 goto err_thermal_unregister;
1703 }
1704
1705 return 0;
1706
1707 err_thermal_unregister:
1708 ath11k_thermal_unregister(ab);
1709 err_mac_unregister:
1710 ath11k_mac_unregister(ab);
1711 err_dp_pdev_free:
1712 ath11k_dp_pdev_free(ab);
1713 err_pdev_debug:
1714 ath11k_debugfs_pdev_destroy(ab);
1715
1716 return ret;
1717 }
1718
ath11k_core_pdev_destroy(struct ath11k_base * ab)1719 static void ath11k_core_pdev_destroy(struct ath11k_base *ab)
1720 {
1721 ath11k_spectral_deinit(ab);
1722 ath11k_thermal_unregister(ab);
1723 ath11k_mac_unregister(ab);
1724 ath11k_hif_irq_disable(ab);
1725 ath11k_dp_pdev_free(ab);
1726 ath11k_debugfs_pdev_destroy(ab);
1727 }
1728
ath11k_core_start(struct ath11k_base * ab)1729 static int ath11k_core_start(struct ath11k_base *ab)
1730 {
1731 int ret;
1732
1733 ret = ath11k_wmi_attach(ab);
1734 if (ret) {
1735 ath11k_err(ab, "failed to attach wmi: %d\n", ret);
1736 return ret;
1737 }
1738
1739 ret = ath11k_htc_init(ab);
1740 if (ret) {
1741 ath11k_err(ab, "failed to init htc: %d\n", ret);
1742 goto err_wmi_detach;
1743 }
1744
1745 ret = ath11k_hif_start(ab);
1746 if (ret) {
1747 ath11k_err(ab, "failed to start HIF: %d\n", ret);
1748 goto err_wmi_detach;
1749 }
1750
1751 ret = ath11k_htc_wait_target(&ab->htc);
1752 if (ret) {
1753 ath11k_err(ab, "failed to connect to HTC: %d\n", ret);
1754 goto err_hif_stop;
1755 }
1756
1757 ret = ath11k_dp_htt_connect(&ab->dp);
1758 if (ret) {
1759 ath11k_err(ab, "failed to connect to HTT: %d\n", ret);
1760 goto err_hif_stop;
1761 }
1762
1763 ret = ath11k_wmi_connect(ab);
1764 if (ret) {
1765 ath11k_err(ab, "failed to connect wmi: %d\n", ret);
1766 goto err_hif_stop;
1767 }
1768
1769 ret = ath11k_htc_start(&ab->htc);
1770 if (ret) {
1771 ath11k_err(ab, "failed to start HTC: %d\n", ret);
1772 goto err_hif_stop;
1773 }
1774
1775 ret = ath11k_wmi_wait_for_service_ready(ab);
1776 if (ret) {
1777 ath11k_err(ab, "failed to receive wmi service ready event: %d\n",
1778 ret);
1779 goto err_hif_stop;
1780 }
1781
1782 ret = ath11k_mac_allocate(ab);
1783 if (ret) {
1784 ath11k_err(ab, "failed to create new hw device with mac80211 :%d\n",
1785 ret);
1786 goto err_hif_stop;
1787 }
1788
1789 ath11k_dp_pdev_pre_alloc(ab);
1790
1791 ret = ath11k_dp_pdev_reo_setup(ab);
1792 if (ret) {
1793 ath11k_err(ab, "failed to initialize reo destination rings: %d\n", ret);
1794 goto err_mac_destroy;
1795 }
1796
1797 ret = ath11k_wmi_cmd_init(ab);
1798 if (ret) {
1799 ath11k_err(ab, "failed to send wmi init cmd: %d\n", ret);
1800 goto err_reo_cleanup;
1801 }
1802
1803 ret = ath11k_wmi_wait_for_unified_ready(ab);
1804 if (ret) {
1805 ath11k_err(ab, "failed to receive wmi unified ready event: %d\n",
1806 ret);
1807 goto err_reo_cleanup;
1808 }
1809
1810 /* put hardware to DBS mode */
1811 if (ab->hw_params.single_pdev_only && ab->hw_params.num_rxdma_per_pdev > 1) {
1812 ret = ath11k_wmi_set_hw_mode(ab, WMI_HOST_HW_MODE_DBS);
1813 if (ret) {
1814 ath11k_err(ab, "failed to send dbs mode: %d\n", ret);
1815 goto err_hif_stop;
1816 }
1817 }
1818
1819 ret = ath11k_dp_tx_htt_h2t_ver_req_msg(ab);
1820 if (ret) {
1821 ath11k_err(ab, "failed to send htt version request message: %d\n",
1822 ret);
1823 goto err_reo_cleanup;
1824 }
1825
1826 return 0;
1827
1828 err_reo_cleanup:
1829 ath11k_dp_pdev_reo_cleanup(ab);
1830 err_mac_destroy:
1831 ath11k_mac_destroy(ab);
1832 err_hif_stop:
1833 ath11k_hif_stop(ab);
1834 err_wmi_detach:
1835 ath11k_wmi_detach(ab);
1836
1837 return ret;
1838 }
1839
ath11k_core_start_firmware(struct ath11k_base * ab,enum ath11k_firmware_mode mode)1840 static int ath11k_core_start_firmware(struct ath11k_base *ab,
1841 enum ath11k_firmware_mode mode)
1842 {
1843 int ret;
1844
1845 ath11k_ce_get_shadow_config(ab, &ab->qmi.ce_cfg.shadow_reg_v2,
1846 &ab->qmi.ce_cfg.shadow_reg_v2_len);
1847
1848 ret = ath11k_qmi_firmware_start(ab, mode);
1849 if (ret) {
1850 ath11k_err(ab, "failed to send firmware start: %d\n", ret);
1851 return ret;
1852 }
1853
1854 return ret;
1855 }
1856
ath11k_core_qmi_firmware_ready(struct ath11k_base * ab)1857 int ath11k_core_qmi_firmware_ready(struct ath11k_base *ab)
1858 {
1859 int ret;
1860
1861 switch (ath11k_crypto_mode) {
1862 case ATH11K_CRYPT_MODE_SW:
1863 set_bit(ATH11K_FLAG_HW_CRYPTO_DISABLED, &ab->dev_flags);
1864 set_bit(ATH11K_FLAG_RAW_MODE, &ab->dev_flags);
1865 break;
1866 case ATH11K_CRYPT_MODE_HW:
1867 clear_bit(ATH11K_FLAG_HW_CRYPTO_DISABLED, &ab->dev_flags);
1868 clear_bit(ATH11K_FLAG_RAW_MODE, &ab->dev_flags);
1869 break;
1870 default:
1871 ath11k_info(ab, "invalid crypto_mode: %d\n", ath11k_crypto_mode);
1872 return -EINVAL;
1873 }
1874
1875 ret = ath11k_core_start_firmware(ab, ab->fw_mode);
1876 if (ret) {
1877 ath11k_err(ab, "failed to start firmware: %d\n", ret);
1878 return ret;
1879 }
1880
1881 ret = ath11k_ce_init_pipes(ab);
1882 if (ret) {
1883 ath11k_err(ab, "failed to initialize CE: %d\n", ret);
1884 goto err_firmware_stop;
1885 }
1886
1887 ret = ath11k_dp_alloc(ab);
1888 if (ret) {
1889 ath11k_err(ab, "failed to init DP: %d\n", ret);
1890 goto err_firmware_stop;
1891 }
1892
1893 if (ath11k_frame_mode == ATH11K_HW_TXRX_RAW)
1894 set_bit(ATH11K_FLAG_RAW_MODE, &ab->dev_flags);
1895
1896 mutex_lock(&ab->core_lock);
1897 ret = ath11k_core_start(ab);
1898 if (ret) {
1899 ath11k_err(ab, "failed to start core: %d\n", ret);
1900 goto err_dp_free;
1901 }
1902
1903 ret = ath11k_core_pdev_create(ab);
1904 if (ret) {
1905 ath11k_err(ab, "failed to create pdev core: %d\n", ret);
1906 goto err_core_stop;
1907 }
1908 ath11k_hif_irq_enable(ab);
1909 mutex_unlock(&ab->core_lock);
1910
1911 return 0;
1912
1913 err_core_stop:
1914 ath11k_core_stop(ab);
1915 ath11k_mac_destroy(ab);
1916 err_dp_free:
1917 ath11k_dp_free(ab);
1918 mutex_unlock(&ab->core_lock);
1919 err_firmware_stop:
1920 ath11k_qmi_firmware_stop(ab);
1921
1922 return ret;
1923 }
1924
ath11k_core_reconfigure_on_crash(struct ath11k_base * ab)1925 static int ath11k_core_reconfigure_on_crash(struct ath11k_base *ab)
1926 {
1927 int ret;
1928
1929 mutex_lock(&ab->core_lock);
1930 ath11k_thermal_unregister(ab);
1931 ath11k_dp_pdev_free(ab);
1932 ath11k_spectral_deinit(ab);
1933 ath11k_ce_cleanup_pipes(ab);
1934 ath11k_wmi_detach(ab);
1935 ath11k_dp_pdev_reo_cleanup(ab);
1936 mutex_unlock(&ab->core_lock);
1937
1938 ath11k_dp_free(ab);
1939 ath11k_hal_srng_deinit(ab);
1940
1941 ab->free_vdev_map = (1LL << (ab->num_radios * TARGET_NUM_VDEVS(ab))) - 1;
1942
1943 ret = ath11k_hal_srng_init(ab);
1944 if (ret)
1945 return ret;
1946
1947 clear_bit(ATH11K_FLAG_CRASH_FLUSH, &ab->dev_flags);
1948
1949 ret = ath11k_core_qmi_firmware_ready(ab);
1950 if (ret)
1951 goto err_hal_srng_deinit;
1952
1953 clear_bit(ATH11K_FLAG_RECOVERY, &ab->dev_flags);
1954
1955 return 0;
1956
1957 err_hal_srng_deinit:
1958 ath11k_hal_srng_deinit(ab);
1959 return ret;
1960 }
1961
ath11k_core_halt(struct ath11k * ar)1962 void ath11k_core_halt(struct ath11k *ar)
1963 {
1964 struct ath11k_base *ab = ar->ab;
1965 struct list_head *pos, *n;
1966
1967 lockdep_assert_held(&ar->conf_mutex);
1968
1969 ar->num_created_vdevs = 0;
1970 ar->allocated_vdev_map = 0;
1971
1972 ath11k_mac_scan_finish(ar);
1973 ath11k_mac_peer_cleanup_all(ar);
1974 cancel_delayed_work_sync(&ar->scan.timeout);
1975 cancel_work_sync(&ar->channel_update_work);
1976 cancel_work_sync(&ar->regd_update_work);
1977 cancel_work_sync(&ab->update_11d_work);
1978
1979 rcu_assign_pointer(ab->pdevs_active[ar->pdev_idx], NULL);
1980 synchronize_rcu();
1981
1982 spin_lock_bh(&ar->data_lock);
1983 list_for_each_safe(pos, n, &ar->arvifs)
1984 list_del_init(pos);
1985 spin_unlock_bh(&ar->data_lock);
1986
1987 idr_init(&ar->txmgmt_idr);
1988 }
1989
ath11k_update_11d(struct work_struct * work)1990 static void ath11k_update_11d(struct work_struct *work)
1991 {
1992 struct ath11k_base *ab = container_of(work, struct ath11k_base, update_11d_work);
1993 struct ath11k *ar;
1994 struct ath11k_pdev *pdev;
1995 int ret, i;
1996
1997 for (i = 0; i < ab->num_radios; i++) {
1998 pdev = &ab->pdevs[i];
1999 ar = pdev->ar;
2000
2001 spin_lock_bh(&ab->base_lock);
2002 memcpy(&ar->alpha2, &ab->new_alpha2, 2);
2003 spin_unlock_bh(&ab->base_lock);
2004
2005 ath11k_dbg(ab, ATH11K_DBG_WMI, "update 11d new cc %c%c for pdev %d\n",
2006 ar->alpha2[0], ar->alpha2[1], i);
2007
2008 ret = ath11k_reg_set_cc(ar);
2009 if (ret)
2010 ath11k_warn(ar->ab,
2011 "pdev id %d failed set current country code: %d\n",
2012 i, ret);
2013 }
2014 }
2015
ath11k_core_pre_reconfigure_recovery(struct ath11k_base * ab)2016 void ath11k_core_pre_reconfigure_recovery(struct ath11k_base *ab)
2017 {
2018 struct ath11k *ar;
2019 struct ath11k_pdev *pdev;
2020 int i;
2021
2022 spin_lock_bh(&ab->base_lock);
2023 ab->stats.fw_crash_counter++;
2024 spin_unlock_bh(&ab->base_lock);
2025
2026 for (i = 0; i < ab->num_radios; i++) {
2027 pdev = &ab->pdevs[i];
2028 ar = pdev->ar;
2029 if (!ar || ar->state == ATH11K_STATE_OFF ||
2030 ar->state == ATH11K_STATE_FTM)
2031 continue;
2032
2033 ieee80211_stop_queues(ar->hw);
2034 ath11k_mac_drain_tx(ar);
2035 ar->state_11d = ATH11K_11D_IDLE;
2036 complete(&ar->completed_11d_scan);
2037 complete(&ar->scan.started);
2038 complete_all(&ar->scan.completed);
2039 complete(&ar->scan.on_channel);
2040 complete(&ar->peer_assoc_done);
2041 complete(&ar->peer_delete_done);
2042 complete(&ar->install_key_done);
2043 complete(&ar->vdev_setup_done);
2044 complete(&ar->vdev_delete_done);
2045 complete(&ar->bss_survey_done);
2046 complete(&ar->thermal.wmi_sync);
2047
2048 wake_up(&ar->dp.tx_empty_waitq);
2049 idr_for_each(&ar->txmgmt_idr,
2050 ath11k_mac_tx_mgmt_pending_free, ar);
2051 idr_destroy(&ar->txmgmt_idr);
2052 wake_up(&ar->txmgmt_empty_waitq);
2053
2054 ar->monitor_vdev_id = -1;
2055 clear_bit(ATH11K_FLAG_MONITOR_STARTED, &ar->monitor_flags);
2056 clear_bit(ATH11K_FLAG_MONITOR_VDEV_CREATED, &ar->monitor_flags);
2057 }
2058
2059 wake_up(&ab->wmi_ab.tx_credits_wq);
2060 wake_up(&ab->peer_mapping_wq);
2061
2062 reinit_completion(&ab->driver_recovery);
2063 }
2064
ath11k_core_post_reconfigure_recovery(struct ath11k_base * ab)2065 static void ath11k_core_post_reconfigure_recovery(struct ath11k_base *ab)
2066 {
2067 struct ath11k *ar;
2068 struct ath11k_pdev *pdev;
2069 int i;
2070
2071 for (i = 0; i < ab->num_radios; i++) {
2072 pdev = &ab->pdevs[i];
2073 ar = pdev->ar;
2074 if (!ar || ar->state == ATH11K_STATE_OFF)
2075 continue;
2076
2077 mutex_lock(&ar->conf_mutex);
2078
2079 switch (ar->state) {
2080 case ATH11K_STATE_ON:
2081 ar->state = ATH11K_STATE_RESTARTING;
2082 ath11k_core_halt(ar);
2083 ieee80211_restart_hw(ar->hw);
2084 break;
2085 case ATH11K_STATE_OFF:
2086 ath11k_warn(ab,
2087 "cannot restart radio %d that hasn't been started\n",
2088 i);
2089 break;
2090 case ATH11K_STATE_RESTARTING:
2091 break;
2092 case ATH11K_STATE_RESTARTED:
2093 ar->state = ATH11K_STATE_WEDGED;
2094 fallthrough;
2095 case ATH11K_STATE_WEDGED:
2096 ath11k_warn(ab,
2097 "device is wedged, will not restart radio %d\n", i);
2098 break;
2099 case ATH11K_STATE_FTM:
2100 ath11k_dbg(ab, ATH11K_DBG_TESTMODE,
2101 "fw mode reset done radio %d\n", i);
2102 break;
2103 }
2104
2105 mutex_unlock(&ar->conf_mutex);
2106 }
2107 complete(&ab->driver_recovery);
2108 }
2109
ath11k_core_restart(struct work_struct * work)2110 static void ath11k_core_restart(struct work_struct *work)
2111 {
2112 struct ath11k_base *ab = container_of(work, struct ath11k_base, restart_work);
2113 int ret;
2114
2115 ret = ath11k_core_reconfigure_on_crash(ab);
2116 if (ret) {
2117 ath11k_err(ab, "failed to reconfigure driver on crash recovery\n");
2118 return;
2119 }
2120
2121 if (ab->is_reset)
2122 complete_all(&ab->reconfigure_complete);
2123
2124 if (!ab->is_reset)
2125 ath11k_core_post_reconfigure_recovery(ab);
2126 }
2127
ath11k_core_reset(struct work_struct * work)2128 static void ath11k_core_reset(struct work_struct *work)
2129 {
2130 struct ath11k_base *ab = container_of(work, struct ath11k_base, reset_work);
2131 int reset_count, fail_cont_count;
2132 long time_left;
2133
2134 if (!(test_bit(ATH11K_FLAG_REGISTERED, &ab->dev_flags))) {
2135 ath11k_warn(ab, "ignore reset dev flags 0x%lx\n", ab->dev_flags);
2136 return;
2137 }
2138
2139 /* Sometimes the recovery will fail and then the next all recovery fail,
2140 * this is to avoid infinite recovery since it can not recovery success.
2141 */
2142 fail_cont_count = atomic_read(&ab->fail_cont_count);
2143
2144 if (fail_cont_count >= ATH11K_RESET_MAX_FAIL_COUNT_FINAL)
2145 return;
2146
2147 if (fail_cont_count >= ATH11K_RESET_MAX_FAIL_COUNT_FIRST &&
2148 time_before(jiffies, ab->reset_fail_timeout))
2149 return;
2150
2151 reset_count = atomic_inc_return(&ab->reset_count);
2152
2153 if (reset_count > 1) {
2154 /* Sometimes it happened another reset worker before the previous one
2155 * completed, then the second reset worker will destroy the previous one,
2156 * thus below is to avoid that.
2157 */
2158 ath11k_warn(ab, "already resetting count %d\n", reset_count);
2159
2160 reinit_completion(&ab->reset_complete);
2161 time_left = wait_for_completion_timeout(&ab->reset_complete,
2162 ATH11K_RESET_TIMEOUT_HZ);
2163
2164 if (time_left) {
2165 ath11k_dbg(ab, ATH11K_DBG_BOOT, "to skip reset\n");
2166 atomic_dec(&ab->reset_count);
2167 return;
2168 }
2169
2170 ab->reset_fail_timeout = jiffies + ATH11K_RESET_FAIL_TIMEOUT_HZ;
2171 /* Record the continuous recovery fail count when recovery failed*/
2172 atomic_inc(&ab->fail_cont_count);
2173 }
2174
2175 ath11k_dbg(ab, ATH11K_DBG_BOOT, "reset starting\n");
2176
2177 ab->is_reset = true;
2178 atomic_set(&ab->recovery_count, 0);
2179 reinit_completion(&ab->recovery_start);
2180 atomic_set(&ab->recovery_start_count, 0);
2181
2182 ath11k_core_pre_reconfigure_recovery(ab);
2183
2184 reinit_completion(&ab->reconfigure_complete);
2185 ath11k_core_post_reconfigure_recovery(ab);
2186
2187 ath11k_dbg(ab, ATH11K_DBG_BOOT, "waiting recovery start...\n");
2188
2189 time_left = wait_for_completion_timeout(&ab->recovery_start,
2190 ATH11K_RECOVER_START_TIMEOUT_HZ);
2191
2192 ath11k_hif_irq_disable(ab);
2193 ath11k_hif_ce_irq_disable(ab);
2194
2195 ath11k_hif_power_down(ab);
2196 ath11k_hif_power_up(ab);
2197
2198 ath11k_dbg(ab, ATH11K_DBG_BOOT, "reset started\n");
2199 }
2200
ath11k_init_hw_params(struct ath11k_base * ab)2201 static int ath11k_init_hw_params(struct ath11k_base *ab)
2202 {
2203 const struct ath11k_hw_params *hw_params = NULL;
2204 int i;
2205
2206 for (i = 0; i < ARRAY_SIZE(ath11k_hw_params); i++) {
2207 hw_params = &ath11k_hw_params[i];
2208
2209 if (hw_params->hw_rev == ab->hw_rev)
2210 break;
2211 }
2212
2213 if (i == ARRAY_SIZE(ath11k_hw_params)) {
2214 ath11k_err(ab, "Unsupported hardware version: 0x%x\n", ab->hw_rev);
2215 return -EINVAL;
2216 }
2217
2218 ab->hw_params = *hw_params;
2219
2220 ath11k_info(ab, "%s\n", ab->hw_params.name);
2221
2222 return 0;
2223 }
2224
ath11k_core_pre_init(struct ath11k_base * ab)2225 int ath11k_core_pre_init(struct ath11k_base *ab)
2226 {
2227 int ret;
2228
2229 ret = ath11k_init_hw_params(ab);
2230 if (ret) {
2231 ath11k_err(ab, "failed to get hw params: %d\n", ret);
2232 return ret;
2233 }
2234
2235 ret = ath11k_fw_pre_init(ab);
2236 if (ret) {
2237 ath11k_err(ab, "failed to pre init firmware: %d", ret);
2238 return ret;
2239 }
2240
2241 return 0;
2242 }
2243 EXPORT_SYMBOL(ath11k_core_pre_init);
2244
ath11k_core_init(struct ath11k_base * ab)2245 int ath11k_core_init(struct ath11k_base *ab)
2246 {
2247 const struct dmi_system_id *dmi_id;
2248 int ret;
2249
2250 dmi_id = dmi_first_match(ath11k_pm_quirk_table);
2251 if (dmi_id)
2252 ab->pm_policy = (kernel_ulong_t)dmi_id->driver_data;
2253 else
2254 ab->pm_policy = ATH11K_PM_DEFAULT;
2255
2256 ath11k_dbg(ab, ATH11K_DBG_BOOT, "pm policy %u\n", ab->pm_policy);
2257
2258 ret = ath11k_core_soc_create(ab);
2259 if (ret) {
2260 ath11k_err(ab, "failed to create soc core: %d\n", ret);
2261 return ret;
2262 }
2263
2264 return 0;
2265 }
2266 EXPORT_SYMBOL(ath11k_core_init);
2267
ath11k_core_deinit(struct ath11k_base * ab)2268 void ath11k_core_deinit(struct ath11k_base *ab)
2269 {
2270 mutex_lock(&ab->core_lock);
2271
2272 ath11k_core_pdev_destroy(ab);
2273 ath11k_core_stop(ab);
2274
2275 mutex_unlock(&ab->core_lock);
2276
2277 ath11k_hif_power_down(ab);
2278 ath11k_mac_destroy(ab);
2279 ath11k_core_soc_destroy(ab);
2280 }
2281 EXPORT_SYMBOL(ath11k_core_deinit);
2282
ath11k_core_free(struct ath11k_base * ab)2283 void ath11k_core_free(struct ath11k_base *ab)
2284 {
2285 destroy_workqueue(ab->workqueue_aux);
2286 destroy_workqueue(ab->workqueue);
2287
2288 kfree(ab);
2289 }
2290 EXPORT_SYMBOL(ath11k_core_free);
2291
ath11k_core_alloc(struct device * dev,size_t priv_size,enum ath11k_bus bus)2292 struct ath11k_base *ath11k_core_alloc(struct device *dev, size_t priv_size,
2293 enum ath11k_bus bus)
2294 {
2295 struct ath11k_base *ab;
2296
2297 ab = kzalloc(sizeof(*ab) + priv_size, GFP_KERNEL);
2298 if (!ab)
2299 return NULL;
2300
2301 init_completion(&ab->driver_recovery);
2302
2303 ab->workqueue = create_singlethread_workqueue("ath11k_wq");
2304 if (!ab->workqueue)
2305 goto err_sc_free;
2306
2307 ab->workqueue_aux = create_singlethread_workqueue("ath11k_aux_wq");
2308 if (!ab->workqueue_aux)
2309 goto err_free_wq;
2310
2311 mutex_init(&ab->core_lock);
2312 mutex_init(&ab->tbl_mtx_lock);
2313 spin_lock_init(&ab->base_lock);
2314 mutex_init(&ab->vdev_id_11d_lock);
2315 init_completion(&ab->reset_complete);
2316 init_completion(&ab->reconfigure_complete);
2317 init_completion(&ab->recovery_start);
2318
2319 INIT_LIST_HEAD(&ab->peers);
2320 init_waitqueue_head(&ab->peer_mapping_wq);
2321 init_waitqueue_head(&ab->wmi_ab.tx_credits_wq);
2322 init_waitqueue_head(&ab->qmi.cold_boot_waitq);
2323 INIT_WORK(&ab->restart_work, ath11k_core_restart);
2324 INIT_WORK(&ab->update_11d_work, ath11k_update_11d);
2325 INIT_WORK(&ab->reset_work, ath11k_core_reset);
2326 timer_setup(&ab->rx_replenish_retry, ath11k_ce_rx_replenish_retry, 0);
2327 init_completion(&ab->htc_suspend);
2328 init_completion(&ab->wow.wakeup_completed);
2329
2330 ab->dev = dev;
2331 ab->hif.bus = bus;
2332
2333 return ab;
2334
2335 err_free_wq:
2336 destroy_workqueue(ab->workqueue);
2337 err_sc_free:
2338 kfree(ab);
2339 return NULL;
2340 }
2341 EXPORT_SYMBOL(ath11k_core_alloc);
2342
2343 MODULE_DESCRIPTION("Core module for Qualcomm Atheros 802.11ax wireless LAN cards.");
2344 MODULE_LICENSE("Dual BSD/GPL");
2345