1 /* SPDX-License-Identifier: BSD-3-Clause-Clear */
2 /*
3 * Copyright (c) 2018-2019 The Linux Foundation. All rights reserved.
4 * Copyright (c) 2021-2023, 2025 Qualcomm Innovation Center, Inc. All rights reserved.
5 */
6
7 #ifndef ATH11K_DP_H
8 #define ATH11K_DP_H
9
10 #include "hal_rx.h"
11
12 #define MAX_RXDMA_PER_PDEV 2
13
14 struct ath11k_base;
15 struct ath11k_peer;
16 struct ath11k_dp;
17 struct ath11k_vif;
18 struct hal_tcl_status_ring;
19 struct ath11k_ext_irq_grp;
20
21 struct dp_rx_tid {
22 u8 tid;
23 dma_addr_t paddr;
24 u32 size;
25 u32 ba_win_sz;
26 bool active;
27
28 /* Info related to rx fragments */
29 u32 cur_sn;
30 u16 last_frag_no;
31 u16 rx_frag_bitmap;
32
33 struct sk_buff_head rx_frags;
34 struct hal_reo_dest_ring *dst_ring_desc;
35
36 /* Timer info related to fragments */
37 struct timer_list frag_timer;
38 struct ath11k_base *ab;
39 u32 *vaddr_unaligned;
40 dma_addr_t paddr_unaligned;
41 u32 unaligned_size;
42 };
43
44 #define DP_REO_DESC_FREE_THRESHOLD 64
45 #define DP_REO_DESC_FREE_TIMEOUT_MS 1000
46 #define DP_MON_PURGE_TIMEOUT_MS 100
47 #define DP_MON_SERVICE_BUDGET 128
48
49 struct dp_reo_cache_flush_elem {
50 struct list_head list;
51 struct dp_rx_tid data;
52 unsigned long ts;
53 };
54
55 struct dp_reo_cmd {
56 struct list_head list;
57 struct dp_rx_tid data;
58 int cmd_num;
59 void (*handler)(struct ath11k_dp *, void *,
60 enum hal_reo_cmd_status status);
61 };
62
63 struct dp_srng {
64 u32 *vaddr_unaligned;
65 u32 *vaddr;
66 dma_addr_t paddr_unaligned;
67 dma_addr_t paddr;
68 int size;
69 u32 ring_id;
70 u8 cached;
71 };
72
73 struct dp_rxdma_ring {
74 struct dp_srng refill_buf_ring;
75 struct idr bufs_idr;
76 /* Protects bufs_idr */
77 spinlock_t idr_lock;
78 int bufs_max;
79 };
80
81 #define ATH11K_TX_COMPL_NEXT(x) (((x) + 1) % DP_TX_COMP_RING_SIZE)
82
83 struct dp_tx_ring {
84 u8 tcl_data_ring_id;
85 struct dp_srng tcl_data_ring;
86 struct dp_srng tcl_comp_ring;
87 struct idr txbuf_idr;
88 /* Protects txbuf_idr and num_pending */
89 spinlock_t tx_idr_lock;
90 struct hal_wbm_release_ring *tx_status;
91 int tx_status_head;
92 int tx_status_tail;
93 };
94
95 enum dp_mon_status_buf_state {
96 /* PPDU id matches in dst ring and status ring */
97 DP_MON_STATUS_MATCH,
98 /* status ring dma is not done */
99 DP_MON_STATUS_NO_DMA,
100 /* status ring is lagging, reap status ring */
101 DP_MON_STATUS_LAG,
102 /* status ring is leading, reap dst ring and drop */
103 DP_MON_STATUS_LEAD,
104 /* replinish monitor status ring */
105 DP_MON_STATUS_REPLINISH,
106 };
107
108 struct ath11k_pdev_mon_stats {
109 u32 status_ppdu_state;
110 u32 status_ppdu_start;
111 u32 status_ppdu_end;
112 u32 status_ppdu_compl;
113 u32 status_ppdu_start_mis;
114 u32 status_ppdu_end_mis;
115 u32 status_ppdu_done;
116 u32 dest_ppdu_done;
117 u32 dest_mpdu_done;
118 u32 dest_mpdu_drop;
119 u32 dup_mon_linkdesc_cnt;
120 u32 dup_mon_buf_cnt;
121 u32 dest_mon_stuck;
122 u32 dest_mon_not_reaped;
123 };
124
125 struct dp_full_mon_mpdu {
126 struct list_head list;
127 struct sk_buff *head;
128 struct sk_buff *tail;
129 };
130
131 struct dp_link_desc_bank {
132 void *vaddr_unaligned;
133 void *vaddr;
134 dma_addr_t paddr_unaligned;
135 dma_addr_t paddr;
136 u32 size;
137 };
138
139 /* Size to enforce scatter idle list mode */
140 #define DP_LINK_DESC_ALLOC_SIZE_THRESH 0x200000
141 #define DP_LINK_DESC_BANKS_MAX 8
142
143 #define DP_RX_DESC_COOKIE_INDEX_MAX 0x3ffff
144 #define DP_RX_DESC_COOKIE_POOL_ID_MAX 0x1c0000
145 #define DP_RX_DESC_COOKIE_MAX \
146 (DP_RX_DESC_COOKIE_INDEX_MAX | DP_RX_DESC_COOKIE_POOL_ID_MAX)
147 #define DP_NOT_PPDU_ID_WRAP_AROUND 20000
148
149 enum ath11k_dp_ppdu_state {
150 DP_PPDU_STATUS_START,
151 DP_PPDU_STATUS_DONE,
152 };
153
154 struct ath11k_mon_data {
155 struct dp_link_desc_bank link_desc_banks[DP_LINK_DESC_BANKS_MAX];
156 struct hal_rx_mon_ppdu_info mon_ppdu_info;
157
158 u32 mon_ppdu_status;
159 u32 mon_last_buf_cookie;
160 u64 mon_last_linkdesc_paddr;
161 u16 chan_noise_floor;
162 bool hold_mon_dst_ring;
163 enum dp_mon_status_buf_state buf_state;
164 dma_addr_t mon_status_paddr;
165 struct dp_full_mon_mpdu *mon_mpdu;
166 struct hal_sw_mon_ring_entries sw_mon_entries;
167 struct ath11k_pdev_mon_stats rx_mon_stats;
168 /* lock for monitor data */
169 spinlock_t mon_lock;
170 struct sk_buff_head rx_status_q;
171 };
172
173 struct ath11k_pdev_dp {
174 u32 mac_id;
175 u32 mon_dest_ring_stuck_cnt;
176 atomic_t num_tx_pending;
177 wait_queue_head_t tx_empty_waitq;
178 struct dp_rxdma_ring rx_refill_buf_ring;
179 struct dp_srng rx_mac_buf_ring[MAX_RXDMA_PER_PDEV];
180 struct dp_srng rxdma_err_dst_ring[MAX_RXDMA_PER_PDEV];
181 struct dp_srng rxdma_mon_dst_ring;
182 struct dp_srng rxdma_mon_desc_ring;
183
184 struct dp_rxdma_ring rxdma_mon_buf_ring;
185 struct dp_rxdma_ring rx_mon_status_refill_ring[MAX_RXDMA_PER_PDEV];
186 struct ieee80211_rx_status rx_status;
187 struct ath11k_mon_data mon_data;
188 };
189
190 #define DP_NUM_CLIENTS_MAX 64
191 #define DP_AVG_TIDS_PER_CLIENT 2
192 #define DP_NUM_TIDS_MAX (DP_NUM_CLIENTS_MAX * DP_AVG_TIDS_PER_CLIENT)
193 #define DP_AVG_MSDUS_PER_FLOW 128
194 #define DP_AVG_FLOWS_PER_TID 2
195 #define DP_AVG_MPDUS_PER_TID_MAX 128
196 #define DP_AVG_MSDUS_PER_MPDU 4
197
198 #define DP_RX_HASH_ENABLE 1 /* Enable hash based Rx steering */
199
200 #define DP_BA_WIN_SZ_MAX 256
201
202 #define DP_TCL_NUM_RING_MAX 3
203 #define DP_TCL_NUM_RING_MAX_QCA6390 1
204
205 #define DP_IDLE_SCATTER_BUFS_MAX 16
206
207 #define DP_WBM_RELEASE_RING_SIZE 64
208 #define DP_TCL_DATA_RING_SIZE 512
209 #define DP_TCL_DATA_RING_SIZE_WCN6750 2048
210 #define DP_TX_COMP_RING_SIZE 32768
211 #define DP_TX_IDR_SIZE DP_TX_COMP_RING_SIZE
212 #define DP_TCL_CMD_RING_SIZE 32
213 #define DP_TCL_STATUS_RING_SIZE 32
214 #define DP_REO_DST_RING_MAX 4
215 #define DP_REO_DST_RING_SIZE 2048
216 #define DP_REO_REINJECT_RING_SIZE 32
217 #define DP_RX_RELEASE_RING_SIZE 1024
218 #define DP_REO_EXCEPTION_RING_SIZE 128
219 #define DP_REO_CMD_RING_SIZE 256
220 #define DP_REO_STATUS_RING_SIZE 2048
221 #define DP_RXDMA_BUF_RING_SIZE 4096
222 #define DP_RXDMA_REFILL_RING_SIZE 2048
223 #define DP_RXDMA_ERR_DST_RING_SIZE 1024
224 #define DP_RXDMA_MON_STATUS_RING_SIZE 1024
225 #define DP_RXDMA_MONITOR_BUF_RING_SIZE 4096
226 #define DP_RXDMA_MONITOR_DST_RING_SIZE 2048
227 #define DP_RXDMA_MONITOR_DESC_RING_SIZE 4096
228
229 #define DP_RX_RELEASE_RING_NUM 3
230
231 #define DP_RX_BUFFER_SIZE 2048
232 #define DP_RX_BUFFER_SIZE_LITE 1024
233 #define DP_RX_BUFFER_ALIGN_SIZE 128
234
235 #define DP_RXDMA_BUF_COOKIE_BUF_ID GENMASK(17, 0)
236 #define DP_RXDMA_BUF_COOKIE_PDEV_ID GENMASK(20, 18)
237
238 #define DP_HW2SW_MACID(mac_id) ((mac_id) ? ((mac_id) - 1) : 0)
239 #define DP_SW2HW_MACID(mac_id) ((mac_id) + 1)
240
241 #define DP_TX_DESC_ID_MAC_ID GENMASK(1, 0)
242 #define DP_TX_DESC_ID_MSDU_ID GENMASK(18, 2)
243 #define DP_TX_DESC_ID_POOL_ID GENMASK(20, 19)
244
245 #define ATH11K_SHADOW_DP_TIMER_INTERVAL 20
246 #define ATH11K_SHADOW_CTRL_TIMER_INTERVAL 10
247
248 struct ath11k_hp_update_timer {
249 struct timer_list timer;
250 bool started;
251 bool init;
252 u32 tx_num;
253 u32 timer_tx_num;
254 u32 ring_id;
255 u32 interval;
256 struct ath11k_base *ab;
257 };
258
259 struct ath11k_dp {
260 struct ath11k_base *ab;
261 enum ath11k_htc_ep_id eid;
262 struct completion htt_tgt_version_received;
263 u8 htt_tgt_ver_major;
264 u8 htt_tgt_ver_minor;
265 struct dp_link_desc_bank link_desc_banks[DP_LINK_DESC_BANKS_MAX];
266 struct dp_srng wbm_idle_ring;
267 struct dp_srng wbm_desc_rel_ring;
268 struct dp_srng tcl_cmd_ring;
269 struct dp_srng tcl_status_ring;
270 struct dp_srng reo_reinject_ring;
271 struct dp_srng rx_rel_ring;
272 struct dp_srng reo_except_ring;
273 struct dp_srng reo_cmd_ring;
274 struct dp_srng reo_status_ring;
275 struct dp_srng reo_dst_ring[DP_REO_DST_RING_MAX];
276 struct dp_tx_ring tx_ring[DP_TCL_NUM_RING_MAX];
277 struct hal_wbm_idle_scatter_list scatter_list[DP_IDLE_SCATTER_BUFS_MAX];
278 struct list_head reo_cmd_list;
279 struct list_head reo_cmd_cache_flush_list;
280 struct list_head dp_full_mon_mpdu_list;
281 u32 reo_cmd_cache_flush_count;
282 /**
283 * protects access to below fields,
284 * - reo_cmd_list
285 * - reo_cmd_cache_flush_list
286 * - reo_cmd_cache_flush_count
287 */
288 spinlock_t reo_cmd_lock;
289 struct ath11k_hp_update_timer reo_cmd_timer;
290 struct ath11k_hp_update_timer tx_ring_timer[DP_TCL_NUM_RING_MAX];
291 };
292
293 /* HTT definitions */
294
295 #define HTT_TCL_META_DATA_TYPE BIT(0)
296 #define HTT_TCL_META_DATA_VALID_HTT BIT(1)
297
298 /* vdev meta data */
299 #define HTT_TCL_META_DATA_VDEV_ID GENMASK(9, 2)
300 #define HTT_TCL_META_DATA_PDEV_ID GENMASK(11, 10)
301 #define HTT_TCL_META_DATA_HOST_INSPECTED BIT(12)
302
303 /* peer meta data */
304 #define HTT_TCL_META_DATA_PEER_ID GENMASK(15, 2)
305
306 #define HTT_TX_WBM_COMP_STATUS_OFFSET 8
307
308 #define HTT_INVALID_PEER_ID 0xffff
309
310 /* HTT tx completion is overlaid in wbm_release_ring */
311 #define HTT_TX_WBM_COMP_INFO0_STATUS GENMASK(12, 9)
312 #define HTT_TX_WBM_COMP_INFO0_REINJECT_REASON GENMASK(16, 13)
313 #define HTT_TX_WBM_COMP_INFO0_REINJECT_REASON GENMASK(16, 13)
314
315 #define HTT_TX_WBM_COMP_INFO1_ACK_RSSI GENMASK(31, 24)
316 #define HTT_TX_WBM_COMP_INFO2_SW_PEER_ID GENMASK(15, 0)
317 #define HTT_TX_WBM_COMP_INFO2_VALID BIT(21)
318
319 struct htt_tx_wbm_completion {
320 u32 info0;
321 u32 info1;
322 u32 info2;
323 u32 info3;
324 } __packed;
325
326 enum htt_h2t_msg_type {
327 HTT_H2T_MSG_TYPE_VERSION_REQ = 0,
328 HTT_H2T_MSG_TYPE_SRING_SETUP = 0xb,
329 HTT_H2T_MSG_TYPE_RX_RING_SELECTION_CFG = 0xc,
330 HTT_H2T_MSG_TYPE_EXT_STATS_CFG = 0x10,
331 HTT_H2T_MSG_TYPE_PPDU_STATS_CFG = 0x11,
332 HTT_H2T_MSG_TYPE_RX_FULL_MONITOR_MODE = 0x17,
333 };
334
335 #define HTT_VER_REQ_INFO_MSG_ID GENMASK(7, 0)
336
337 struct htt_ver_req_cmd {
338 u32 ver_reg_info;
339 } __packed;
340
341 enum htt_srng_ring_type {
342 HTT_HW_TO_SW_RING,
343 HTT_SW_TO_HW_RING,
344 HTT_SW_TO_SW_RING,
345 };
346
347 enum htt_srng_ring_id {
348 HTT_RXDMA_HOST_BUF_RING,
349 HTT_RXDMA_MONITOR_STATUS_RING,
350 HTT_RXDMA_MONITOR_BUF_RING,
351 HTT_RXDMA_MONITOR_DESC_RING,
352 HTT_RXDMA_MONITOR_DEST_RING,
353 HTT_HOST1_TO_FW_RXBUF_RING,
354 HTT_HOST2_TO_FW_RXBUF_RING,
355 HTT_RXDMA_NON_MONITOR_DEST_RING,
356 };
357
358 /* host -> target HTT_SRING_SETUP message
359 *
360 * After target is booted up, Host can send SRING setup message for
361 * each host facing LMAC SRING. Target setups up HW registers based
362 * on setup message and confirms back to Host if response_required is set.
363 * Host should wait for confirmation message before sending new SRING
364 * setup message
365 *
366 * The message would appear as follows:
367 *
368 * |31 24|23 20|19|18 16|15|14 8|7 0|
369 * |--------------- +-----------------+----------------+------------------|
370 * | ring_type | ring_id | pdev_id | msg_type |
371 * |----------------------------------------------------------------------|
372 * | ring_base_addr_lo |
373 * |----------------------------------------------------------------------|
374 * | ring_base_addr_hi |
375 * |----------------------------------------------------------------------|
376 * |ring_misc_cfg_flag|ring_entry_size| ring_size |
377 * |----------------------------------------------------------------------|
378 * | ring_head_offset32_remote_addr_lo |
379 * |----------------------------------------------------------------------|
380 * | ring_head_offset32_remote_addr_hi |
381 * |----------------------------------------------------------------------|
382 * | ring_tail_offset32_remote_addr_lo |
383 * |----------------------------------------------------------------------|
384 * | ring_tail_offset32_remote_addr_hi |
385 * |----------------------------------------------------------------------|
386 * | ring_msi_addr_lo |
387 * |----------------------------------------------------------------------|
388 * | ring_msi_addr_hi |
389 * |----------------------------------------------------------------------|
390 * | ring_msi_data |
391 * |----------------------------------------------------------------------|
392 * | intr_timer_th |IM| intr_batch_counter_th |
393 * |----------------------------------------------------------------------|
394 * | reserved |RR|PTCF| intr_low_threshold |
395 * |----------------------------------------------------------------------|
396 * Where
397 * IM = sw_intr_mode
398 * RR = response_required
399 * PTCF = prefetch_timer_cfg
400 *
401 * The message is interpreted as follows:
402 * dword0 - b'0:7 - msg_type: This will be set to
403 * HTT_H2T_MSG_TYPE_SRING_SETUP
404 * b'8:15 - pdev_id:
405 * 0 (for rings at SOC/UMAC level),
406 * 1/2/3 mac id (for rings at LMAC level)
407 * b'16:23 - ring_id: identify which ring is to setup,
408 * more details can be got from enum htt_srng_ring_id
409 * b'24:31 - ring_type: identify type of host rings,
410 * more details can be got from enum htt_srng_ring_type
411 * dword1 - b'0:31 - ring_base_addr_lo: Lower 32bits of ring base address
412 * dword2 - b'0:31 - ring_base_addr_hi: Upper 32bits of ring base address
413 * dword3 - b'0:15 - ring_size: size of the ring in unit of 4-bytes words
414 * b'16:23 - ring_entry_size: Size of each entry in 4-byte word units
415 * b'24:31 - ring_misc_cfg_flag: Valid only for HW_TO_SW_RING and
416 * SW_TO_HW_RING.
417 * Refer to HTT_SRING_SETUP_RING_MISC_CFG_RING defs.
418 * dword4 - b'0:31 - ring_head_off32_remote_addr_lo:
419 * Lower 32 bits of memory address of the remote variable
420 * storing the 4-byte word offset that identifies the head
421 * element within the ring.
422 * (The head offset variable has type u32.)
423 * Valid for HW_TO_SW and SW_TO_SW rings.
424 * dword5 - b'0:31 - ring_head_off32_remote_addr_hi:
425 * Upper 32 bits of memory address of the remote variable
426 * storing the 4-byte word offset that identifies the head
427 * element within the ring.
428 * (The head offset variable has type u32.)
429 * Valid for HW_TO_SW and SW_TO_SW rings.
430 * dword6 - b'0:31 - ring_tail_off32_remote_addr_lo:
431 * Lower 32 bits of memory address of the remote variable
432 * storing the 4-byte word offset that identifies the tail
433 * element within the ring.
434 * (The tail offset variable has type u32.)
435 * Valid for HW_TO_SW and SW_TO_SW rings.
436 * dword7 - b'0:31 - ring_tail_off32_remote_addr_hi:
437 * Upper 32 bits of memory address of the remote variable
438 * storing the 4-byte word offset that identifies the tail
439 * element within the ring.
440 * (The tail offset variable has type u32.)
441 * Valid for HW_TO_SW and SW_TO_SW rings.
442 * dword8 - b'0:31 - ring_msi_addr_lo: Lower 32bits of MSI cfg address
443 * valid only for HW_TO_SW_RING and SW_TO_HW_RING
444 * dword9 - b'0:31 - ring_msi_addr_hi: Upper 32bits of MSI cfg address
445 * valid only for HW_TO_SW_RING and SW_TO_HW_RING
446 * dword10 - b'0:31 - ring_msi_data: MSI data
447 * Refer to HTT_SRING_SETUP_RING_MSC_CFG_xxx defs
448 * valid only for HW_TO_SW_RING and SW_TO_HW_RING
449 * dword11 - b'0:14 - intr_batch_counter_th:
450 * batch counter threshold is in units of 4-byte words.
451 * HW internally maintains and increments batch count.
452 * (see SRING spec for detail description).
453 * When batch count reaches threshold value, an interrupt
454 * is generated by HW.
455 * b'15 - sw_intr_mode:
456 * This configuration shall be static.
457 * Only programmed at power up.
458 * 0: generate pulse style sw interrupts
459 * 1: generate level style sw interrupts
460 * b'16:31 - intr_timer_th:
461 * The timer init value when timer is idle or is
462 * initialized to start downcounting.
463 * In 8us units (to cover a range of 0 to 524 ms)
464 * dword12 - b'0:15 - intr_low_threshold:
465 * Used only by Consumer ring to generate ring_sw_int_p.
466 * Ring entries low threshold water mark, that is used
467 * in combination with the interrupt timer as well as
468 * the clearing of the level interrupt.
469 * b'16:18 - prefetch_timer_cfg:
470 * Used only by Consumer ring to set timer mode to
471 * support Application prefetch handling.
472 * The external tail offset/pointer will be updated
473 * at following intervals:
474 * 3'b000: (Prefetch feature disabled; used only for debug)
475 * 3'b001: 1 usec
476 * 3'b010: 4 usec
477 * 3'b011: 8 usec (default)
478 * 3'b100: 16 usec
479 * Others: Reserved
480 * b'19 - response_required:
481 * Host needs HTT_T2H_MSG_TYPE_SRING_SETUP_DONE as response
482 * b'20:31 - reserved: reserved for future use
483 */
484
485 #define HTT_SRNG_SETUP_CMD_INFO0_MSG_TYPE GENMASK(7, 0)
486 #define HTT_SRNG_SETUP_CMD_INFO0_PDEV_ID GENMASK(15, 8)
487 #define HTT_SRNG_SETUP_CMD_INFO0_RING_ID GENMASK(23, 16)
488 #define HTT_SRNG_SETUP_CMD_INFO0_RING_TYPE GENMASK(31, 24)
489
490 #define HTT_SRNG_SETUP_CMD_INFO1_RING_SIZE GENMASK(15, 0)
491 #define HTT_SRNG_SETUP_CMD_INFO1_RING_ENTRY_SIZE GENMASK(23, 16)
492 #define HTT_SRNG_SETUP_CMD_INFO1_RING_LOOP_CNT_DIS BIT(25)
493 #define HTT_SRNG_SETUP_CMD_INFO1_RING_FLAGS_MSI_SWAP BIT(27)
494 #define HTT_SRNG_SETUP_CMD_INFO1_RING_FLAGS_HOST_FW_SWAP BIT(28)
495 #define HTT_SRNG_SETUP_CMD_INFO1_RING_FLAGS_TLV_SWAP BIT(29)
496
497 #define HTT_SRNG_SETUP_CMD_INTR_INFO_BATCH_COUNTER_THRESH GENMASK(14, 0)
498 #define HTT_SRNG_SETUP_CMD_INTR_INFO_SW_INTR_MODE BIT(15)
499 #define HTT_SRNG_SETUP_CMD_INTR_INFO_INTR_TIMER_THRESH GENMASK(31, 16)
500
501 #define HTT_SRNG_SETUP_CMD_INFO2_INTR_LOW_THRESH GENMASK(15, 0)
502 #define HTT_SRNG_SETUP_CMD_INFO2_PRE_FETCH_TIMER_CFG BIT(16)
503 #define HTT_SRNG_SETUP_CMD_INFO2_RESPONSE_REQUIRED BIT(19)
504
505 struct htt_srng_setup_cmd {
506 u32 info0;
507 u32 ring_base_addr_lo;
508 u32 ring_base_addr_hi;
509 u32 info1;
510 u32 ring_head_off32_remote_addr_lo;
511 u32 ring_head_off32_remote_addr_hi;
512 u32 ring_tail_off32_remote_addr_lo;
513 u32 ring_tail_off32_remote_addr_hi;
514 u32 ring_msi_addr_lo;
515 u32 ring_msi_addr_hi;
516 u32 msi_data;
517 u32 intr_info;
518 u32 info2;
519 } __packed;
520
521 /* host -> target FW PPDU_STATS config message
522 *
523 * @details
524 * The following field definitions describe the format of the HTT host
525 * to target FW for PPDU_STATS_CFG msg.
526 * The message allows the host to configure the PPDU_STATS_IND messages
527 * produced by the target.
528 *
529 * |31 24|23 16|15 8|7 0|
530 * |-----------------------------------------------------------|
531 * | REQ bit mask | pdev_mask | msg type |
532 * |-----------------------------------------------------------|
533 * Header fields:
534 * - MSG_TYPE
535 * Bits 7:0
536 * Purpose: identifies this is a req to configure ppdu_stats_ind from target
537 * Value: 0x11
538 * - PDEV_MASK
539 * Bits 8:15
540 * Purpose: identifies which pdevs this PPDU stats configuration applies to
541 * Value: This is a overloaded field, refer to usage and interpretation of
542 * PDEV in interface document.
543 * Bit 8 : Reserved for SOC stats
544 * Bit 9 - 15 : Indicates PDEV_MASK in DBDC
545 * Indicates MACID_MASK in DBS
546 * - REQ_TLV_BIT_MASK
547 * Bits 16:31
548 * Purpose: each set bit indicates the corresponding PPDU stats TLV type
549 * needs to be included in the target's PPDU_STATS_IND messages.
550 * Value: refer htt_ppdu_stats_tlv_tag_t <<<???
551 *
552 */
553
554 struct htt_ppdu_stats_cfg_cmd {
555 u32 msg;
556 } __packed;
557
558 #define HTT_PPDU_STATS_CFG_MSG_TYPE GENMASK(7, 0)
559 #define HTT_PPDU_STATS_CFG_SOC_STATS BIT(8)
560 #define HTT_PPDU_STATS_CFG_PDEV_ID GENMASK(15, 9)
561 #define HTT_PPDU_STATS_CFG_TLV_TYPE_BITMASK GENMASK(31, 16)
562
563 enum htt_ppdu_stats_tag_type {
564 HTT_PPDU_STATS_TAG_COMMON,
565 HTT_PPDU_STATS_TAG_USR_COMMON,
566 HTT_PPDU_STATS_TAG_USR_RATE,
567 HTT_PPDU_STATS_TAG_USR_MPDU_ENQ_BITMAP_64,
568 HTT_PPDU_STATS_TAG_USR_MPDU_ENQ_BITMAP_256,
569 HTT_PPDU_STATS_TAG_SCH_CMD_STATUS,
570 HTT_PPDU_STATS_TAG_USR_COMPLTN_COMMON,
571 HTT_PPDU_STATS_TAG_USR_COMPLTN_BA_BITMAP_64,
572 HTT_PPDU_STATS_TAG_USR_COMPLTN_BA_BITMAP_256,
573 HTT_PPDU_STATS_TAG_USR_COMPLTN_ACK_BA_STATUS,
574 HTT_PPDU_STATS_TAG_USR_COMPLTN_FLUSH,
575 HTT_PPDU_STATS_TAG_USR_COMMON_ARRAY,
576 HTT_PPDU_STATS_TAG_INFO,
577 HTT_PPDU_STATS_TAG_TX_MGMTCTRL_PAYLOAD,
578
579 /* New TLV's are added above to this line */
580 HTT_PPDU_STATS_TAG_MAX,
581 };
582
583 #define HTT_PPDU_STATS_TAG_DEFAULT (BIT(HTT_PPDU_STATS_TAG_COMMON) \
584 | BIT(HTT_PPDU_STATS_TAG_USR_COMMON) \
585 | BIT(HTT_PPDU_STATS_TAG_USR_RATE) \
586 | BIT(HTT_PPDU_STATS_TAG_SCH_CMD_STATUS) \
587 | BIT(HTT_PPDU_STATS_TAG_USR_COMPLTN_COMMON) \
588 | BIT(HTT_PPDU_STATS_TAG_USR_COMPLTN_ACK_BA_STATUS) \
589 | BIT(HTT_PPDU_STATS_TAG_USR_COMPLTN_FLUSH) \
590 | BIT(HTT_PPDU_STATS_TAG_USR_COMMON_ARRAY))
591
592 #define HTT_PPDU_STATS_TAG_PKTLOG (BIT(HTT_PPDU_STATS_TAG_USR_MPDU_ENQ_BITMAP_64) | \
593 BIT(HTT_PPDU_STATS_TAG_USR_MPDU_ENQ_BITMAP_256) | \
594 BIT(HTT_PPDU_STATS_TAG_USR_COMPLTN_BA_BITMAP_64) | \
595 BIT(HTT_PPDU_STATS_TAG_USR_COMPLTN_BA_BITMAP_256) | \
596 BIT(HTT_PPDU_STATS_TAG_INFO) | \
597 BIT(HTT_PPDU_STATS_TAG_TX_MGMTCTRL_PAYLOAD) | \
598 HTT_PPDU_STATS_TAG_DEFAULT)
599
600 /* HTT_H2T_MSG_TYPE_RX_RING_SELECTION_CFG Message
601 *
602 * details:
603 * HTT_H2T_MSG_TYPE_RX_RING_SELECTION_CFG message is sent by host to
604 * configure RXDMA rings.
605 * The configuration is per ring based and includes both packet subtypes
606 * and PPDU/MPDU TLVs.
607 *
608 * The message would appear as follows:
609 *
610 * |31 26|25|24|23 16|15 8|7 0|
611 * |-----------------+----------------+----------------+---------------|
612 * | rsvd1 |PS|SS| ring_id | pdev_id | msg_type |
613 * |-------------------------------------------------------------------|
614 * | rsvd2 | ring_buffer_size |
615 * |-------------------------------------------------------------------|
616 * | packet_type_enable_flags_0 |
617 * |-------------------------------------------------------------------|
618 * | packet_type_enable_flags_1 |
619 * |-------------------------------------------------------------------|
620 * | packet_type_enable_flags_2 |
621 * |-------------------------------------------------------------------|
622 * | packet_type_enable_flags_3 |
623 * |-------------------------------------------------------------------|
624 * | tlv_filter_in_flags |
625 * |-------------------------------------------------------------------|
626 * Where:
627 * PS = pkt_swap
628 * SS = status_swap
629 * The message is interpreted as follows:
630 * dword0 - b'0:7 - msg_type: This will be set to
631 * HTT_H2T_MSG_TYPE_RX_RING_SELECTION_CFG
632 * b'8:15 - pdev_id:
633 * 0 (for rings at SOC/UMAC level),
634 * 1/2/3 mac id (for rings at LMAC level)
635 * b'16:23 - ring_id : Identify the ring to configure.
636 * More details can be got from enum htt_srng_ring_id
637 * b'24 - status_swap: 1 is to swap status TLV
638 * b'25 - pkt_swap: 1 is to swap packet TLV
639 * b'26:31 - rsvd1: reserved for future use
640 * dword1 - b'0:16 - ring_buffer_size: size of buffers referenced by rx ring,
641 * in byte units.
642 * Valid only for HW_TO_SW_RING and SW_TO_HW_RING
643 * - b'16:31 - rsvd2: Reserved for future use
644 * dword2 - b'0:31 - packet_type_enable_flags_0:
645 * Enable MGMT packet from 0b0000 to 0b1001
646 * bits from low to high: FP, MD, MO - 3 bits
647 * FP: Filter_Pass
648 * MD: Monitor_Direct
649 * MO: Monitor_Other
650 * 10 mgmt subtypes * 3 bits -> 30 bits
651 * Refer to PKT_TYPE_ENABLE_FLAG0_xxx_MGMT_xxx defs
652 * dword3 - b'0:31 - packet_type_enable_flags_1:
653 * Enable MGMT packet from 0b1010 to 0b1111
654 * bits from low to high: FP, MD, MO - 3 bits
655 * Refer to PKT_TYPE_ENABLE_FLAG1_xxx_MGMT_xxx defs
656 * dword4 - b'0:31 - packet_type_enable_flags_2:
657 * Enable CTRL packet from 0b0000 to 0b1001
658 * bits from low to high: FP, MD, MO - 3 bits
659 * Refer to PKT_TYPE_ENABLE_FLAG2_xxx_CTRL_xxx defs
660 * dword5 - b'0:31 - packet_type_enable_flags_3:
661 * Enable CTRL packet from 0b1010 to 0b1111,
662 * MCAST_DATA, UCAST_DATA, NULL_DATA
663 * bits from low to high: FP, MD, MO - 3 bits
664 * Refer to PKT_TYPE_ENABLE_FLAG3_xxx_CTRL_xxx defs
665 * dword6 - b'0:31 - tlv_filter_in_flags:
666 * Filter in Attention/MPDU/PPDU/Header/User tlvs
667 * Refer to CFG_TLV_FILTER_IN_FLAG defs
668 */
669
670 #define HTT_RX_RING_SELECTION_CFG_CMD_INFO0_MSG_TYPE GENMASK(7, 0)
671 #define HTT_RX_RING_SELECTION_CFG_CMD_INFO0_PDEV_ID GENMASK(15, 8)
672 #define HTT_RX_RING_SELECTION_CFG_CMD_INFO0_RING_ID GENMASK(23, 16)
673 #define HTT_RX_RING_SELECTION_CFG_CMD_INFO0_SS BIT(24)
674 #define HTT_RX_RING_SELECTION_CFG_CMD_INFO0_PS BIT(25)
675
676 #define HTT_RX_RING_SELECTION_CFG_CMD_INFO1_BUF_SIZE GENMASK(15, 0)
677
678 enum htt_rx_filter_tlv_flags {
679 HTT_RX_FILTER_TLV_FLAGS_MPDU_START = BIT(0),
680 HTT_RX_FILTER_TLV_FLAGS_MSDU_START = BIT(1),
681 HTT_RX_FILTER_TLV_FLAGS_RX_PACKET = BIT(2),
682 HTT_RX_FILTER_TLV_FLAGS_MSDU_END = BIT(3),
683 HTT_RX_FILTER_TLV_FLAGS_MPDU_END = BIT(4),
684 HTT_RX_FILTER_TLV_FLAGS_PACKET_HEADER = BIT(5),
685 HTT_RX_FILTER_TLV_FLAGS_PER_MSDU_HEADER = BIT(6),
686 HTT_RX_FILTER_TLV_FLAGS_ATTENTION = BIT(7),
687 HTT_RX_FILTER_TLV_FLAGS_PPDU_START = BIT(8),
688 HTT_RX_FILTER_TLV_FLAGS_PPDU_END = BIT(9),
689 HTT_RX_FILTER_TLV_FLAGS_PPDU_END_USER_STATS = BIT(10),
690 HTT_RX_FILTER_TLV_FLAGS_PPDU_END_USER_STATS_EXT = BIT(11),
691 HTT_RX_FILTER_TLV_FLAGS_PPDU_END_STATUS_DONE = BIT(12),
692 };
693
694 enum htt_rx_mgmt_pkt_filter_tlv_flags0 {
695 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_REQ = BIT(0),
696 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_REQ = BIT(1),
697 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_REQ = BIT(2),
698 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_RESP = BIT(3),
699 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_RESP = BIT(4),
700 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_RESP = BIT(5),
701 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_REQ = BIT(6),
702 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_REQ = BIT(7),
703 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_REQ = BIT(8),
704 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_RESP = BIT(9),
705 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_RESP = BIT(10),
706 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_RESP = BIT(11),
707 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_REQ = BIT(12),
708 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_REQ = BIT(13),
709 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_REQ = BIT(14),
710 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_RESP = BIT(15),
711 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_RESP = BIT(16),
712 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_RESP = BIT(17),
713 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_TIMING_ADV = BIT(18),
714 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_TIMING_ADV = BIT(19),
715 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_TIMING_ADV = BIT(20),
716 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_RESERVED_7 = BIT(21),
717 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_RESERVED_7 = BIT(22),
718 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_RESERVED_7 = BIT(23),
719 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_BEACON = BIT(24),
720 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_BEACON = BIT(25),
721 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_BEACON = BIT(26),
722 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_ATIM = BIT(27),
723 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_ATIM = BIT(28),
724 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_ATIM = BIT(29),
725 };
726
727 enum htt_rx_mgmt_pkt_filter_tlv_flags1 {
728 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_DISASSOC = BIT(0),
729 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_DISASSOC = BIT(1),
730 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_DISASSOC = BIT(2),
731 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_AUTH = BIT(3),
732 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_AUTH = BIT(4),
733 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_AUTH = BIT(5),
734 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_DEAUTH = BIT(6),
735 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_DEAUTH = BIT(7),
736 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_DEAUTH = BIT(8),
737 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION = BIT(9),
738 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION = BIT(10),
739 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION = BIT(11),
740 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION_NOACK = BIT(12),
741 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION_NOACK = BIT(13),
742 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION_NOACK = BIT(14),
743 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_RESERVED_15 = BIT(15),
744 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_RESERVED_15 = BIT(16),
745 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_RESERVED_15 = BIT(17),
746 };
747
748 enum htt_rx_ctrl_pkt_filter_tlv_flags2 {
749 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_1 = BIT(0),
750 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_1 = BIT(1),
751 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_1 = BIT(2),
752 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_2 = BIT(3),
753 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_2 = BIT(4),
754 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_2 = BIT(5),
755 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_TRIGGER = BIT(6),
756 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_TRIGGER = BIT(7),
757 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_TRIGGER = BIT(8),
758 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_4 = BIT(9),
759 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_4 = BIT(10),
760 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_4 = BIT(11),
761 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_BF_REP_POLL = BIT(12),
762 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_BF_REP_POLL = BIT(13),
763 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_BF_REP_POLL = BIT(14),
764 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_VHT_NDP = BIT(15),
765 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_VHT_NDP = BIT(16),
766 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_VHT_NDP = BIT(17),
767 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_FRAME_EXT = BIT(18),
768 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_FRAME_EXT = BIT(19),
769 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_FRAME_EXT = BIT(20),
770 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_WRAPPER = BIT(21),
771 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_WRAPPER = BIT(22),
772 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_WRAPPER = BIT(23),
773 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_BAR = BIT(24),
774 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_BAR = BIT(25),
775 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_BAR = BIT(26),
776 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_BA = BIT(27),
777 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_BA = BIT(28),
778 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_BA = BIT(29),
779 };
780
781 enum htt_rx_ctrl_pkt_filter_tlv_flags3 {
782 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_PSPOLL = BIT(0),
783 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_PSPOLL = BIT(1),
784 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_PSPOLL = BIT(2),
785 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_RTS = BIT(3),
786 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_RTS = BIT(4),
787 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_RTS = BIT(5),
788 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_CTS = BIT(6),
789 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_CTS = BIT(7),
790 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_CTS = BIT(8),
791 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_ACK = BIT(9),
792 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_ACK = BIT(10),
793 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_ACK = BIT(11),
794 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND = BIT(12),
795 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND = BIT(13),
796 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND = BIT(14),
797 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND_ACK = BIT(15),
798 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND_ACK = BIT(16),
799 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND_ACK = BIT(17),
800 };
801
802 enum htt_rx_data_pkt_filter_tlv_flasg3 {
803 HTT_RX_FP_DATA_PKT_FILTER_TLV_FLASG3_MCAST = BIT(18),
804 HTT_RX_MD_DATA_PKT_FILTER_TLV_FLASG3_MCAST = BIT(19),
805 HTT_RX_MO_DATA_PKT_FILTER_TLV_FLASG3_MCAST = BIT(20),
806 HTT_RX_FP_DATA_PKT_FILTER_TLV_FLASG3_UCAST = BIT(21),
807 HTT_RX_MD_DATA_PKT_FILTER_TLV_FLASG3_UCAST = BIT(22),
808 HTT_RX_MO_DATA_PKT_FILTER_TLV_FLASG3_UCAST = BIT(23),
809 HTT_RX_FP_DATA_PKT_FILTER_TLV_FLASG3_NULL_DATA = BIT(24),
810 HTT_RX_MD_DATA_PKT_FILTER_TLV_FLASG3_NULL_DATA = BIT(25),
811 HTT_RX_MO_DATA_PKT_FILTER_TLV_FLASG3_NULL_DATA = BIT(26),
812 };
813
814 #define HTT_RX_FP_MGMT_FILTER_FLAGS0 \
815 (HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_REQ \
816 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_RESP \
817 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_REQ \
818 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_RESP \
819 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_REQ \
820 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_RESP \
821 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_TIMING_ADV \
822 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_BEACON \
823 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_ATIM)
824
825 #define HTT_RX_MD_MGMT_FILTER_FLAGS0 \
826 (HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_REQ \
827 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_RESP \
828 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_REQ \
829 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_RESP \
830 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_REQ \
831 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_RESP \
832 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_TIMING_ADV \
833 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_BEACON \
834 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_ATIM)
835
836 #define HTT_RX_MO_MGMT_FILTER_FLAGS0 \
837 (HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_REQ \
838 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_RESP \
839 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_REQ \
840 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_RESP \
841 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_REQ \
842 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_RESP \
843 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_TIMING_ADV \
844 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_BEACON \
845 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_ATIM)
846
847 #define HTT_RX_FP_MGMT_FILTER_FLAGS1 (HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_DISASSOC \
848 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_AUTH \
849 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_DEAUTH \
850 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION \
851 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION_NOACK)
852
853 #define HTT_RX_MD_MGMT_FILTER_FLAGS1 (HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_DISASSOC \
854 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_AUTH \
855 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_DEAUTH \
856 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION \
857 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION_NOACK)
858
859 #define HTT_RX_MO_MGMT_FILTER_FLAGS1 (HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_DISASSOC \
860 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_AUTH \
861 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_DEAUTH \
862 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION \
863 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION_NOACK)
864
865 #define HTT_RX_FP_CTRL_FILTER_FLASG2 (HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_WRAPPER \
866 | HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_BAR \
867 | HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_BA)
868
869 #define HTT_RX_MD_CTRL_FILTER_FLASG2 (HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_WRAPPER \
870 | HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_BAR \
871 | HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_BA)
872
873 #define HTT_RX_MO_CTRL_FILTER_FLASG2 (HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_WRAPPER \
874 | HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_BAR \
875 | HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_BA)
876
877 #define HTT_RX_FP_CTRL_FILTER_FLASG3 (HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_PSPOLL \
878 | HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_RTS \
879 | HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_CTS \
880 | HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_ACK \
881 | HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND \
882 | HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND_ACK)
883
884 #define HTT_RX_MD_CTRL_FILTER_FLASG3 (HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_PSPOLL \
885 | HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_RTS \
886 | HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_CTS \
887 | HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_ACK \
888 | HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND \
889 | HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND_ACK)
890
891 #define HTT_RX_MO_CTRL_FILTER_FLASG3 (HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_PSPOLL \
892 | HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_RTS \
893 | HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_CTS \
894 | HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_ACK \
895 | HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND \
896 | HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND_ACK)
897
898 #define HTT_RX_FP_DATA_FILTER_FLASG3 (HTT_RX_FP_DATA_PKT_FILTER_TLV_FLASG3_MCAST \
899 | HTT_RX_FP_DATA_PKT_FILTER_TLV_FLASG3_UCAST \
900 | HTT_RX_FP_DATA_PKT_FILTER_TLV_FLASG3_NULL_DATA)
901
902 #define HTT_RX_MD_DATA_FILTER_FLASG3 (HTT_RX_MD_DATA_PKT_FILTER_TLV_FLASG3_MCAST \
903 | HTT_RX_MD_DATA_PKT_FILTER_TLV_FLASG3_UCAST \
904 | HTT_RX_MD_DATA_PKT_FILTER_TLV_FLASG3_NULL_DATA)
905
906 #define HTT_RX_MO_DATA_FILTER_FLASG3 (HTT_RX_MO_DATA_PKT_FILTER_TLV_FLASG3_MCAST \
907 | HTT_RX_MO_DATA_PKT_FILTER_TLV_FLASG3_UCAST \
908 | HTT_RX_MO_DATA_PKT_FILTER_TLV_FLASG3_NULL_DATA)
909
910 #define HTT_RX_MON_FP_MGMT_FILTER_FLAGS0 \
911 (HTT_RX_FP_MGMT_FILTER_FLAGS0 | \
912 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_RESERVED_7)
913
914 #define HTT_RX_MON_MO_MGMT_FILTER_FLAGS0 \
915 (HTT_RX_MO_MGMT_FILTER_FLAGS0 | \
916 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_RESERVED_7)
917
918 #define HTT_RX_MON_FP_MGMT_FILTER_FLAGS1 \
919 (HTT_RX_FP_MGMT_FILTER_FLAGS1 | \
920 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_RESERVED_15)
921
922 #define HTT_RX_MON_MO_MGMT_FILTER_FLAGS1 \
923 (HTT_RX_MO_MGMT_FILTER_FLAGS1 | \
924 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_RESERVED_15)
925
926 #define HTT_RX_MON_FP_CTRL_FILTER_FLASG2 \
927 (HTT_RX_FP_CTRL_FILTER_FLASG2 | \
928 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_1 | \
929 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_2 | \
930 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_TRIGGER | \
931 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_4 | \
932 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_BF_REP_POLL | \
933 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_VHT_NDP | \
934 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_FRAME_EXT)
935
936 #define HTT_RX_MON_MO_CTRL_FILTER_FLASG2 \
937 (HTT_RX_MO_CTRL_FILTER_FLASG2 | \
938 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_1 | \
939 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_2 | \
940 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_TRIGGER | \
941 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_4 | \
942 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_BF_REP_POLL | \
943 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_VHT_NDP | \
944 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_FRAME_EXT)
945
946 #define HTT_RX_MON_FP_CTRL_FILTER_FLASG3 HTT_RX_FP_CTRL_FILTER_FLASG3
947
948 #define HTT_RX_MON_MO_CTRL_FILTER_FLASG3 HTT_RX_MO_CTRL_FILTER_FLASG3
949
950 #define HTT_RX_MON_FP_DATA_FILTER_FLASG3 HTT_RX_FP_DATA_FILTER_FLASG3
951
952 #define HTT_RX_MON_MO_DATA_FILTER_FLASG3 HTT_RX_MO_DATA_FILTER_FLASG3
953
954 #define HTT_RX_MON_FILTER_TLV_FLAGS \
955 (HTT_RX_FILTER_TLV_FLAGS_MPDU_START | \
956 HTT_RX_FILTER_TLV_FLAGS_PPDU_START | \
957 HTT_RX_FILTER_TLV_FLAGS_PPDU_END | \
958 HTT_RX_FILTER_TLV_FLAGS_PPDU_END_USER_STATS | \
959 HTT_RX_FILTER_TLV_FLAGS_PPDU_END_USER_STATS_EXT | \
960 HTT_RX_FILTER_TLV_FLAGS_PPDU_END_STATUS_DONE)
961
962 #define HTT_RX_MON_FILTER_TLV_FLAGS_MON_STATUS_RING \
963 (HTT_RX_FILTER_TLV_FLAGS_MPDU_START | \
964 HTT_RX_FILTER_TLV_FLAGS_PPDU_START | \
965 HTT_RX_FILTER_TLV_FLAGS_PPDU_END | \
966 HTT_RX_FILTER_TLV_FLAGS_PPDU_END_USER_STATS | \
967 HTT_RX_FILTER_TLV_FLAGS_PPDU_END_USER_STATS_EXT | \
968 HTT_RX_FILTER_TLV_FLAGS_PPDU_END_STATUS_DONE)
969
970 #define HTT_RX_MON_FILTER_TLV_FLAGS_MON_BUF_RING \
971 (HTT_RX_FILTER_TLV_FLAGS_MPDU_START | \
972 HTT_RX_FILTER_TLV_FLAGS_MSDU_START | \
973 HTT_RX_FILTER_TLV_FLAGS_RX_PACKET | \
974 HTT_RX_FILTER_TLV_FLAGS_MSDU_END | \
975 HTT_RX_FILTER_TLV_FLAGS_MPDU_END | \
976 HTT_RX_FILTER_TLV_FLAGS_PACKET_HEADER | \
977 HTT_RX_FILTER_TLV_FLAGS_PER_MSDU_HEADER | \
978 HTT_RX_FILTER_TLV_FLAGS_ATTENTION)
979
980 struct htt_rx_ring_selection_cfg_cmd {
981 u32 info0;
982 u32 info1;
983 u32 pkt_type_en_flags0;
984 u32 pkt_type_en_flags1;
985 u32 pkt_type_en_flags2;
986 u32 pkt_type_en_flags3;
987 u32 rx_filter_tlv;
988 } __packed;
989
990 struct htt_rx_ring_tlv_filter {
991 u32 rx_filter; /* see htt_rx_filter_tlv_flags */
992 u32 pkt_filter_flags0; /* MGMT */
993 u32 pkt_filter_flags1; /* MGMT */
994 u32 pkt_filter_flags2; /* CTRL */
995 u32 pkt_filter_flags3; /* DATA */
996 };
997
998 #define HTT_RX_FULL_MON_MODE_CFG_CMD_INFO0_MSG_TYPE GENMASK(7, 0)
999 #define HTT_RX_FULL_MON_MODE_CFG_CMD_INFO0_PDEV_ID GENMASK(15, 8)
1000
1001 #define HTT_RX_FULL_MON_MODE_CFG_CMD_CFG_ENABLE BIT(0)
1002 #define HTT_RX_FULL_MON_MODE_CFG_CMD_CFG_ZERO_MPDUS_END BIT(1)
1003 #define HTT_RX_FULL_MON_MODE_CFG_CMD_CFG_NON_ZERO_MPDUS_END BIT(2)
1004 #define HTT_RX_FULL_MON_MODE_CFG_CMD_CFG_RELEASE_RING GENMASK(10, 3)
1005
1006 /* Enumeration for full monitor mode destination ring select
1007 * 0 - REO destination ring select
1008 * 1 - FW destination ring select
1009 * 2 - SW destination ring select
1010 * 3 - Release destination ring select
1011 */
1012 enum htt_rx_full_mon_release_ring {
1013 HTT_RX_MON_RING_REO,
1014 HTT_RX_MON_RING_FW,
1015 HTT_RX_MON_RING_SW,
1016 HTT_RX_MON_RING_RELEASE,
1017 };
1018
1019 struct htt_rx_full_monitor_mode_cfg_cmd {
1020 u32 info0;
1021 u32 cfg;
1022 } __packed;
1023
1024 /* HTT message target->host */
1025
1026 enum htt_t2h_msg_type {
1027 HTT_T2H_MSG_TYPE_VERSION_CONF,
1028 HTT_T2H_MSG_TYPE_PEER_MAP = 0x3,
1029 HTT_T2H_MSG_TYPE_PEER_UNMAP = 0x4,
1030 HTT_T2H_MSG_TYPE_RX_ADDBA = 0x5,
1031 HTT_T2H_MSG_TYPE_PKTLOG = 0x8,
1032 HTT_T2H_MSG_TYPE_SEC_IND = 0xb,
1033 HTT_T2H_MSG_TYPE_PEER_MAP2 = 0x1e,
1034 HTT_T2H_MSG_TYPE_PEER_UNMAP2 = 0x1f,
1035 HTT_T2H_MSG_TYPE_PPDU_STATS_IND = 0x1d,
1036 HTT_T2H_MSG_TYPE_EXT_STATS_CONF = 0x1c,
1037 HTT_T2H_MSG_TYPE_BKPRESSURE_EVENT_IND = 0x24,
1038 };
1039
1040 #define HTT_TARGET_VERSION_MAJOR 3
1041
1042 #define HTT_T2H_MSG_TYPE GENMASK(7, 0)
1043 #define HTT_T2H_VERSION_CONF_MINOR GENMASK(15, 8)
1044 #define HTT_T2H_VERSION_CONF_MAJOR GENMASK(23, 16)
1045
1046 struct htt_t2h_version_conf_msg {
1047 u32 version;
1048 } __packed;
1049
1050 #define HTT_T2H_PEER_MAP_INFO_VDEV_ID GENMASK(15, 8)
1051 #define HTT_T2H_PEER_MAP_INFO_PEER_ID GENMASK(31, 16)
1052 #define HTT_T2H_PEER_MAP_INFO1_MAC_ADDR_H16 GENMASK(15, 0)
1053 #define HTT_T2H_PEER_MAP_INFO1_HW_PEER_ID GENMASK(31, 16)
1054 #define HTT_T2H_PEER_MAP_INFO2_AST_HASH_VAL GENMASK(15, 0)
1055 #define HTT_T2H_PEER_MAP_INFO2_NEXT_HOP_M BIT(16)
1056 #define HTT_T2H_PEER_MAP_INFO2_NEXT_HOP_S 16
1057
1058 struct htt_t2h_peer_map_event {
1059 u32 info;
1060 u32 mac_addr_l32;
1061 u32 info1;
1062 u32 info2;
1063 } __packed;
1064
1065 #define HTT_T2H_PEER_UNMAP_INFO_VDEV_ID HTT_T2H_PEER_MAP_INFO_VDEV_ID
1066 #define HTT_T2H_PEER_UNMAP_INFO_PEER_ID HTT_T2H_PEER_MAP_INFO_PEER_ID
1067 #define HTT_T2H_PEER_UNMAP_INFO1_MAC_ADDR_H16 \
1068 HTT_T2H_PEER_MAP_INFO1_MAC_ADDR_H16
1069 #define HTT_T2H_PEER_MAP_INFO1_NEXT_HOP_M HTT_T2H_PEER_MAP_INFO2_NEXT_HOP_M
1070 #define HTT_T2H_PEER_MAP_INFO1_NEXT_HOP_S HTT_T2H_PEER_MAP_INFO2_NEXT_HOP_S
1071
1072 struct htt_t2h_peer_unmap_event {
1073 u32 info;
1074 u32 mac_addr_l32;
1075 u32 info1;
1076 } __packed;
1077
1078 struct htt_resp_msg {
1079 union {
1080 struct htt_t2h_version_conf_msg version_msg;
1081 struct htt_t2h_peer_map_event peer_map_ev;
1082 struct htt_t2h_peer_unmap_event peer_unmap_ev;
1083 };
1084 } __packed;
1085
1086 #define HTT_BACKPRESSURE_EVENT_PDEV_ID_M GENMASK(15, 8)
1087 #define HTT_BACKPRESSURE_EVENT_RING_TYPE_M GENMASK(23, 16)
1088 #define HTT_BACKPRESSURE_EVENT_RING_ID_M GENMASK(31, 24)
1089
1090 #define HTT_BACKPRESSURE_EVENT_HP_M GENMASK(15, 0)
1091 #define HTT_BACKPRESSURE_EVENT_TP_M GENMASK(31, 16)
1092
1093 #define HTT_BACKPRESSURE_UMAC_RING_TYPE 0
1094 #define HTT_BACKPRESSURE_LMAC_RING_TYPE 1
1095
1096 enum htt_backpressure_umac_ringid {
1097 HTT_SW_RING_IDX_REO_REO2SW1_RING,
1098 HTT_SW_RING_IDX_REO_REO2SW2_RING,
1099 HTT_SW_RING_IDX_REO_REO2SW3_RING,
1100 HTT_SW_RING_IDX_REO_REO2SW4_RING,
1101 HTT_SW_RING_IDX_REO_WBM2REO_LINK_RING,
1102 HTT_SW_RING_IDX_REO_REO2TCL_RING,
1103 HTT_SW_RING_IDX_REO_REO2FW_RING,
1104 HTT_SW_RING_IDX_REO_REO_RELEASE_RING,
1105 HTT_SW_RING_IDX_WBM_PPE_RELEASE_RING,
1106 HTT_SW_RING_IDX_TCL_TCL2TQM_RING,
1107 HTT_SW_RING_IDX_WBM_TQM_RELEASE_RING,
1108 HTT_SW_RING_IDX_WBM_REO_RELEASE_RING,
1109 HTT_SW_RING_IDX_WBM_WBM2SW0_RELEASE_RING,
1110 HTT_SW_RING_IDX_WBM_WBM2SW1_RELEASE_RING,
1111 HTT_SW_RING_IDX_WBM_WBM2SW2_RELEASE_RING,
1112 HTT_SW_RING_IDX_WBM_WBM2SW3_RELEASE_RING,
1113 HTT_SW_RING_IDX_REO_REO_CMD_RING,
1114 HTT_SW_RING_IDX_REO_REO_STATUS_RING,
1115 HTT_SW_UMAC_RING_IDX_MAX,
1116 };
1117
1118 enum htt_backpressure_lmac_ringid {
1119 HTT_SW_RING_IDX_FW2RXDMA_BUF_RING,
1120 HTT_SW_RING_IDX_FW2RXDMA_STATUS_RING,
1121 HTT_SW_RING_IDX_FW2RXDMA_LINK_RING,
1122 HTT_SW_RING_IDX_SW2RXDMA_BUF_RING,
1123 HTT_SW_RING_IDX_WBM2RXDMA_LINK_RING,
1124 HTT_SW_RING_IDX_RXDMA2FW_RING,
1125 HTT_SW_RING_IDX_RXDMA2SW_RING,
1126 HTT_SW_RING_IDX_RXDMA2RELEASE_RING,
1127 HTT_SW_RING_IDX_RXDMA2REO_RING,
1128 HTT_SW_RING_IDX_MONITOR_STATUS_RING,
1129 HTT_SW_RING_IDX_MONITOR_BUF_RING,
1130 HTT_SW_RING_IDX_MONITOR_DESC_RING,
1131 HTT_SW_RING_IDX_MONITOR_DEST_RING,
1132 HTT_SW_LMAC_RING_IDX_MAX,
1133 };
1134
1135 /* ppdu stats
1136 *
1137 * @details
1138 * The following field definitions describe the format of the HTT target
1139 * to host ppdu stats indication message.
1140 *
1141 *
1142 * |31 16|15 12|11 10|9 8|7 0 |
1143 * |----------------------------------------------------------------------|
1144 * | payload_size | rsvd |pdev_id|mac_id | msg type |
1145 * |----------------------------------------------------------------------|
1146 * | ppdu_id |
1147 * |----------------------------------------------------------------------|
1148 * | Timestamp in us |
1149 * |----------------------------------------------------------------------|
1150 * | reserved |
1151 * |----------------------------------------------------------------------|
1152 * | type-specific stats info |
1153 * | (see htt_ppdu_stats.h) |
1154 * |----------------------------------------------------------------------|
1155 * Header fields:
1156 * - MSG_TYPE
1157 * Bits 7:0
1158 * Purpose: Identifies this is a PPDU STATS indication
1159 * message.
1160 * Value: 0x1d
1161 * - mac_id
1162 * Bits 9:8
1163 * Purpose: mac_id of this ppdu_id
1164 * Value: 0-3
1165 * - pdev_id
1166 * Bits 11:10
1167 * Purpose: pdev_id of this ppdu_id
1168 * Value: 0-3
1169 * 0 (for rings at SOC level),
1170 * 1/2/3 PDEV -> 0/1/2
1171 * - payload_size
1172 * Bits 31:16
1173 * Purpose: total tlv size
1174 * Value: payload_size in bytes
1175 */
1176
1177 #define HTT_T2H_PPDU_STATS_INFO_PDEV_ID GENMASK(11, 10)
1178 #define HTT_T2H_PPDU_STATS_INFO_PAYLOAD_SIZE GENMASK(31, 16)
1179
1180 struct ath11k_htt_ppdu_stats_msg {
1181 u32 info;
1182 u32 ppdu_id;
1183 u32 timestamp;
1184 u32 rsvd;
1185 u8 data[];
1186 } __packed;
1187
1188 struct htt_tlv {
1189 u32 header;
1190 u8 value[];
1191 } __packed;
1192
1193 #define HTT_TLV_TAG GENMASK(11, 0)
1194 #define HTT_TLV_LEN GENMASK(23, 12)
1195
1196 enum HTT_PPDU_STATS_BW {
1197 HTT_PPDU_STATS_BANDWIDTH_5MHZ = 0,
1198 HTT_PPDU_STATS_BANDWIDTH_10MHZ = 1,
1199 HTT_PPDU_STATS_BANDWIDTH_20MHZ = 2,
1200 HTT_PPDU_STATS_BANDWIDTH_40MHZ = 3,
1201 HTT_PPDU_STATS_BANDWIDTH_80MHZ = 4,
1202 HTT_PPDU_STATS_BANDWIDTH_160MHZ = 5, /* includes 80+80 */
1203 HTT_PPDU_STATS_BANDWIDTH_DYN = 6,
1204 };
1205
1206 #define HTT_PPDU_STATS_CMN_FLAGS_FRAME_TYPE_M GENMASK(7, 0)
1207 #define HTT_PPDU_STATS_CMN_FLAGS_QUEUE_TYPE_M GENMASK(15, 8)
1208 /* bw - HTT_PPDU_STATS_BW */
1209 #define HTT_PPDU_STATS_CMN_FLAGS_BW_M GENMASK(19, 16)
1210
1211 struct htt_ppdu_stats_common {
1212 u32 ppdu_id;
1213 u16 sched_cmdid;
1214 u8 ring_id;
1215 u8 num_users;
1216 u32 flags; /* %HTT_PPDU_STATS_COMMON_FLAGS_*/
1217 u32 chain_mask;
1218 u32 fes_duration_us; /* frame exchange sequence */
1219 u32 ppdu_sch_eval_start_tstmp_us;
1220 u32 ppdu_sch_end_tstmp_us;
1221 u32 ppdu_start_tstmp_us;
1222 /* BIT [15 : 0] - phy mode (WLAN_PHY_MODE) with which ppdu was transmitted
1223 * BIT [31 : 16] - bandwidth (in MHz) with which ppdu was transmitted
1224 */
1225 u16 phy_mode;
1226 u16 bw_mhz;
1227 } __packed;
1228
1229 enum htt_ppdu_stats_gi {
1230 HTT_PPDU_STATS_SGI_0_8_US,
1231 HTT_PPDU_STATS_SGI_0_4_US,
1232 HTT_PPDU_STATS_SGI_1_6_US,
1233 HTT_PPDU_STATS_SGI_3_2_US,
1234 };
1235
1236 #define HTT_PPDU_STATS_USER_RATE_INFO0_USER_POS_M GENMASK(3, 0)
1237 #define HTT_PPDU_STATS_USER_RATE_INFO0_MU_GROUP_ID_M GENMASK(11, 4)
1238
1239 #define HTT_PPDU_STATS_USER_RATE_INFO1_RESP_TYPE_VALD_M BIT(0)
1240 #define HTT_PPDU_STATS_USER_RATE_INFO1_PPDU_TYPE_M GENMASK(5, 1)
1241
1242 #define HTT_PPDU_STATS_USER_RATE_FLAGS_LTF_SIZE_M GENMASK(1, 0)
1243 #define HTT_PPDU_STATS_USER_RATE_FLAGS_STBC_M BIT(2)
1244 #define HTT_PPDU_STATS_USER_RATE_FLAGS_HE_RE_M BIT(3)
1245 #define HTT_PPDU_STATS_USER_RATE_FLAGS_TXBF_M GENMASK(7, 4)
1246 #define HTT_PPDU_STATS_USER_RATE_FLAGS_BW_M GENMASK(11, 8)
1247 #define HTT_PPDU_STATS_USER_RATE_FLAGS_NSS_M GENMASK(15, 12)
1248 #define HTT_PPDU_STATS_USER_RATE_FLAGS_MCS_M GENMASK(19, 16)
1249 #define HTT_PPDU_STATS_USER_RATE_FLAGS_PREAMBLE_M GENMASK(23, 20)
1250 #define HTT_PPDU_STATS_USER_RATE_FLAGS_GI_M GENMASK(27, 24)
1251 #define HTT_PPDU_STATS_USER_RATE_FLAGS_DCM_M BIT(28)
1252 #define HTT_PPDU_STATS_USER_RATE_FLAGS_LDPC_M BIT(29)
1253
1254 #define HTT_USR_RATE_PREAMBLE(_val) \
1255 FIELD_GET(HTT_PPDU_STATS_USER_RATE_FLAGS_PREAMBLE_M, _val)
1256 #define HTT_USR_RATE_BW(_val) \
1257 FIELD_GET(HTT_PPDU_STATS_USER_RATE_FLAGS_BW_M, _val)
1258 #define HTT_USR_RATE_NSS(_val) \
1259 FIELD_GET(HTT_PPDU_STATS_USER_RATE_FLAGS_NSS_M, _val)
1260 #define HTT_USR_RATE_MCS(_val) \
1261 FIELD_GET(HTT_PPDU_STATS_USER_RATE_FLAGS_MCS_M, _val)
1262 #define HTT_USR_RATE_GI(_val) \
1263 FIELD_GET(HTT_PPDU_STATS_USER_RATE_FLAGS_GI_M, _val)
1264 #define HTT_USR_RATE_DCM(_val) \
1265 FIELD_GET(HTT_PPDU_STATS_USER_RATE_FLAGS_DCM_M, _val)
1266
1267 #define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_LTF_SIZE_M GENMASK(1, 0)
1268 #define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_STBC_M BIT(2)
1269 #define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_HE_RE_M BIT(3)
1270 #define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_TXBF_M GENMASK(7, 4)
1271 #define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_BW_M GENMASK(11, 8)
1272 #define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_NSS_M GENMASK(15, 12)
1273 #define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_MCS_M GENMASK(19, 16)
1274 #define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_PREAMBLE_M GENMASK(23, 20)
1275 #define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_GI_M GENMASK(27, 24)
1276 #define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_DCM_M BIT(28)
1277 #define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_LDPC_M BIT(29)
1278
1279 struct htt_ppdu_stats_user_rate {
1280 u8 tid_num;
1281 u8 reserved0;
1282 u16 sw_peer_id;
1283 u32 info0; /* %HTT_PPDU_STATS_USER_RATE_INFO0_*/
1284 u16 ru_end;
1285 u16 ru_start;
1286 u16 resp_ru_end;
1287 u16 resp_ru_start;
1288 u32 info1; /* %HTT_PPDU_STATS_USER_RATE_INFO1_ */
1289 u32 rate_flags; /* %HTT_PPDU_STATS_USER_RATE_FLAGS_ */
1290 /* Note: resp_rate_info is only valid for if resp_type is UL */
1291 u32 resp_rate_flags; /* %HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_ */
1292 } __packed;
1293
1294 #define HTT_PPDU_STATS_TX_INFO_FLAGS_RATECODE_M GENMASK(7, 0)
1295 #define HTT_PPDU_STATS_TX_INFO_FLAGS_IS_AMPDU_M BIT(8)
1296 #define HTT_PPDU_STATS_TX_INFO_FLAGS_BA_ACK_FAILED_M GENMASK(10, 9)
1297 #define HTT_PPDU_STATS_TX_INFO_FLAGS_BW_M GENMASK(13, 11)
1298 #define HTT_PPDU_STATS_TX_INFO_FLAGS_SGI_M BIT(14)
1299 #define HTT_PPDU_STATS_TX_INFO_FLAGS_PEERID_M GENMASK(31, 16)
1300
1301 #define HTT_TX_INFO_IS_AMSDU(_flags) \
1302 FIELD_GET(HTT_PPDU_STATS_TX_INFO_FLAGS_IS_AMPDU_M, _flags)
1303 #define HTT_TX_INFO_BA_ACK_FAILED(_flags) \
1304 FIELD_GET(HTT_PPDU_STATS_TX_INFO_FLAGS_BA_ACK_FAILED_M, _flags)
1305 #define HTT_TX_INFO_RATECODE(_flags) \
1306 FIELD_GET(HTT_PPDU_STATS_TX_INFO_FLAGS_RATECODE_M, _flags)
1307 #define HTT_TX_INFO_PEERID(_flags) \
1308 FIELD_GET(HTT_PPDU_STATS_TX_INFO_FLAGS_PEERID_M, _flags)
1309
1310 enum htt_ppdu_stats_usr_compln_status {
1311 HTT_PPDU_STATS_USER_STATUS_OK,
1312 HTT_PPDU_STATS_USER_STATUS_FILTERED,
1313 HTT_PPDU_STATS_USER_STATUS_RESP_TIMEOUT,
1314 HTT_PPDU_STATS_USER_STATUS_RESP_MISMATCH,
1315 HTT_PPDU_STATS_USER_STATUS_ABORT,
1316 };
1317
1318 #define HTT_PPDU_STATS_USR_CMPLTN_CMN_FLAGS_LONG_RETRY_M GENMASK(3, 0)
1319 #define HTT_PPDU_STATS_USR_CMPLTN_CMN_FLAGS_SHORT_RETRY_M GENMASK(7, 4)
1320 #define HTT_PPDU_STATS_USR_CMPLTN_CMN_FLAGS_IS_AMPDU_M BIT(8)
1321 #define HTT_PPDU_STATS_USR_CMPLTN_CMN_FLAGS_RESP_TYPE_M GENMASK(12, 9)
1322
1323 #define HTT_USR_CMPLTN_IS_AMPDU(_val) \
1324 FIELD_GET(HTT_PPDU_STATS_USR_CMPLTN_CMN_FLAGS_IS_AMPDU_M, _val)
1325 #define HTT_USR_CMPLTN_LONG_RETRY(_val) \
1326 FIELD_GET(HTT_PPDU_STATS_USR_CMPLTN_CMN_FLAGS_LONG_RETRY_M, _val)
1327 #define HTT_USR_CMPLTN_SHORT_RETRY(_val) \
1328 FIELD_GET(HTT_PPDU_STATS_USR_CMPLTN_CMN_FLAGS_SHORT_RETRY_M, _val)
1329
1330 struct htt_ppdu_stats_usr_cmpltn_cmn {
1331 u8 status;
1332 u8 tid_num;
1333 u16 sw_peer_id;
1334 /* RSSI value of last ack packet (units = dB above noise floor) */
1335 u32 ack_rssi;
1336 u16 mpdu_tried;
1337 u16 mpdu_success;
1338 u32 flags; /* %HTT_PPDU_STATS_USR_CMPLTN_CMN_FLAGS_LONG_RETRIES*/
1339 } __packed;
1340
1341 #define HTT_PPDU_STATS_ACK_BA_INFO_NUM_MPDU_M GENMASK(8, 0)
1342 #define HTT_PPDU_STATS_ACK_BA_INFO_NUM_MSDU_M GENMASK(24, 9)
1343 #define HTT_PPDU_STATS_ACK_BA_INFO_TID_NUM GENMASK(31, 25)
1344
1345 #define HTT_PPDU_STATS_NON_QOS_TID 16
1346
1347 struct htt_ppdu_stats_usr_cmpltn_ack_ba_status {
1348 u32 ppdu_id;
1349 u16 sw_peer_id;
1350 u16 reserved0;
1351 u32 info; /* %HTT_PPDU_STATS_USR_CMPLTN_CMN_INFO_ */
1352 u16 current_seq;
1353 u16 start_seq;
1354 u32 success_bytes;
1355 } __packed;
1356
1357 struct htt_ppdu_user_stats {
1358 u16 peer_id;
1359 u32 tlv_flags;
1360 bool is_valid_peer_id;
1361 struct htt_ppdu_stats_user_rate rate;
1362 struct htt_ppdu_stats_usr_cmpltn_cmn cmpltn_cmn;
1363 struct htt_ppdu_stats_usr_cmpltn_ack_ba_status ack_ba;
1364 };
1365
1366 #define HTT_PPDU_STATS_MAX_USERS 8
1367 #define HTT_PPDU_DESC_MAX_DEPTH 16
1368
1369 struct htt_ppdu_stats {
1370 struct htt_ppdu_stats_common common;
1371 struct htt_ppdu_user_stats user_stats[HTT_PPDU_STATS_MAX_USERS];
1372 };
1373
1374 struct htt_ppdu_stats_info {
1375 u32 ppdu_id;
1376 struct htt_ppdu_stats ppdu_stats;
1377 struct list_head list;
1378 };
1379
1380 /* @brief target -> host packet log message
1381 *
1382 * @details
1383 * The following field definitions describe the format of the packet log
1384 * message sent from the target to the host.
1385 * The message consists of a 4-octet header,followed by a variable number
1386 * of 32-bit character values.
1387 *
1388 * |31 16|15 12|11 10|9 8|7 0|
1389 * |------------------------------------------------------------------|
1390 * | payload_size | rsvd |pdev_id|mac_id| msg type |
1391 * |------------------------------------------------------------------|
1392 * | payload |
1393 * |------------------------------------------------------------------|
1394 * - MSG_TYPE
1395 * Bits 7:0
1396 * Purpose: identifies this as a pktlog message
1397 * Value: HTT_T2H_MSG_TYPE_PKTLOG
1398 * - mac_id
1399 * Bits 9:8
1400 * Purpose: identifies which MAC/PHY instance generated this pktlog info
1401 * Value: 0-3
1402 * - pdev_id
1403 * Bits 11:10
1404 * Purpose: pdev_id
1405 * Value: 0-3
1406 * 0 (for rings at SOC level),
1407 * 1/2/3 PDEV -> 0/1/2
1408 * - payload_size
1409 * Bits 31:16
1410 * Purpose: explicitly specify the payload size
1411 * Value: payload size in bytes (payload size is a multiple of 4 bytes)
1412 */
1413 struct htt_pktlog_msg {
1414 u32 hdr;
1415 u8 payload[];
1416 };
1417
1418 /* @brief host -> target FW extended statistics retrieve
1419 *
1420 * @details
1421 * The following field definitions describe the format of the HTT host
1422 * to target FW extended stats retrieve message.
1423 * The message specifies the type of stats the host wants to retrieve.
1424 *
1425 * |31 24|23 16|15 8|7 0|
1426 * |-----------------------------------------------------------|
1427 * | reserved | stats type | pdev_mask | msg type |
1428 * |-----------------------------------------------------------|
1429 * | config param [0] |
1430 * |-----------------------------------------------------------|
1431 * | config param [1] |
1432 * |-----------------------------------------------------------|
1433 * | config param [2] |
1434 * |-----------------------------------------------------------|
1435 * | config param [3] |
1436 * |-----------------------------------------------------------|
1437 * | reserved |
1438 * |-----------------------------------------------------------|
1439 * | cookie LSBs |
1440 * |-----------------------------------------------------------|
1441 * | cookie MSBs |
1442 * |-----------------------------------------------------------|
1443 * Header fields:
1444 * - MSG_TYPE
1445 * Bits 7:0
1446 * Purpose: identifies this is a extended stats upload request message
1447 * Value: 0x10
1448 * - PDEV_MASK
1449 * Bits 8:15
1450 * Purpose: identifies the mask of PDEVs to retrieve stats from
1451 * Value: This is a overloaded field, refer to usage and interpretation of
1452 * PDEV in interface document.
1453 * Bit 8 : Reserved for SOC stats
1454 * Bit 9 - 15 : Indicates PDEV_MASK in DBDC
1455 * Indicates MACID_MASK in DBS
1456 * - STATS_TYPE
1457 * Bits 23:16
1458 * Purpose: identifies which FW statistics to upload
1459 * Value: Defined by htt_dbg_ext_stats_type (see htt_stats.h)
1460 * - Reserved
1461 * Bits 31:24
1462 * - CONFIG_PARAM [0]
1463 * Bits 31:0
1464 * Purpose: give an opaque configuration value to the specified stats type
1465 * Value: stats-type specific configuration value
1466 * Refer to htt_stats.h for interpretation for each stats sub_type
1467 * - CONFIG_PARAM [1]
1468 * Bits 31:0
1469 * Purpose: give an opaque configuration value to the specified stats type
1470 * Value: stats-type specific configuration value
1471 * Refer to htt_stats.h for interpretation for each stats sub_type
1472 * - CONFIG_PARAM [2]
1473 * Bits 31:0
1474 * Purpose: give an opaque configuration value to the specified stats type
1475 * Value: stats-type specific configuration value
1476 * Refer to htt_stats.h for interpretation for each stats sub_type
1477 * - CONFIG_PARAM [3]
1478 * Bits 31:0
1479 * Purpose: give an opaque configuration value to the specified stats type
1480 * Value: stats-type specific configuration value
1481 * Refer to htt_stats.h for interpretation for each stats sub_type
1482 * - Reserved [31:0] for future use.
1483 * - COOKIE_LSBS
1484 * Bits 31:0
1485 * Purpose: Provide a mechanism to match a target->host stats confirmation
1486 * message with its preceding host->target stats request message.
1487 * Value: LSBs of the opaque cookie specified by the host-side requestor
1488 * - COOKIE_MSBS
1489 * Bits 31:0
1490 * Purpose: Provide a mechanism to match a target->host stats confirmation
1491 * message with its preceding host->target stats request message.
1492 * Value: MSBs of the opaque cookie specified by the host-side requestor
1493 */
1494
1495 struct htt_ext_stats_cfg_hdr {
1496 u8 msg_type;
1497 u8 pdev_mask;
1498 u8 stats_type;
1499 u8 reserved;
1500 } __packed;
1501
1502 struct htt_ext_stats_cfg_cmd {
1503 struct htt_ext_stats_cfg_hdr hdr;
1504 u32 cfg_param0;
1505 u32 cfg_param1;
1506 u32 cfg_param2;
1507 u32 cfg_param3;
1508 u32 reserved;
1509 u32 cookie_lsb;
1510 u32 cookie_msb;
1511 } __packed;
1512
1513 /* htt stats config default params */
1514 #define HTT_STAT_DEFAULT_RESET_START_OFFSET 0
1515 #define HTT_STAT_DEFAULT_CFG0_ALL_HWQS 0xffffffff
1516 #define HTT_STAT_DEFAULT_CFG0_ALL_TXQS 0xffffffff
1517 #define HTT_STAT_DEFAULT_CFG0_ALL_CMDQS 0xffff
1518 #define HTT_STAT_DEFAULT_CFG0_ALL_RINGS 0xffff
1519 #define HTT_STAT_DEFAULT_CFG0_ACTIVE_PEERS 0xff
1520 #define HTT_STAT_DEFAULT_CFG0_CCA_CUMULATIVE 0x00
1521 #define HTT_STAT_DEFAULT_CFG0_ACTIVE_VDEVS 0x00
1522
1523 /* HTT_DBG_EXT_STATS_PEER_INFO
1524 * PARAMS:
1525 * @config_param0:
1526 * [Bit0] - [0] for sw_peer_id, [1] for mac_addr based request
1527 * [Bit15 : Bit 1] htt_peer_stats_req_mode_t
1528 * [Bit31 : Bit16] sw_peer_id
1529 * @config_param1:
1530 * peer_stats_req_type_mask:32 (enum htt_peer_stats_tlv_enum)
1531 * 0 bit htt_peer_stats_cmn_tlv
1532 * 1 bit htt_peer_details_tlv
1533 * 2 bit htt_tx_peer_rate_stats_tlv
1534 * 3 bit htt_rx_peer_rate_stats_tlv
1535 * 4 bit htt_tx_tid_stats_tlv/htt_tx_tid_stats_v1_tlv
1536 * 5 bit htt_rx_tid_stats_tlv
1537 * 6 bit htt_msdu_flow_stats_tlv
1538 * @config_param2: [Bit31 : Bit0] mac_addr31to0
1539 * @config_param3: [Bit15 : Bit0] mac_addr47to32
1540 * [Bit31 : Bit16] reserved
1541 */
1542 #define HTT_STAT_PEER_INFO_MAC_ADDR BIT(0)
1543 #define HTT_STAT_DEFAULT_PEER_REQ_TYPE 0x7f
1544
1545 /* Used to set different configs to the specified stats type.*/
1546 struct htt_ext_stats_cfg_params {
1547 u32 cfg0;
1548 u32 cfg1;
1549 u32 cfg2;
1550 u32 cfg3;
1551 };
1552
1553 /* @brief target -> host extended statistics upload
1554 *
1555 * @details
1556 * The following field definitions describe the format of the HTT target
1557 * to host stats upload confirmation message.
1558 * The message contains a cookie echoed from the HTT host->target stats
1559 * upload request, which identifies which request the confirmation is
1560 * for, and a single stats can span over multiple HTT stats indication
1561 * due to the HTT message size limitation so every HTT ext stats indication
1562 * will have tag-length-value stats information elements.
1563 * The tag-length header for each HTT stats IND message also includes a
1564 * status field, to indicate whether the request for the stat type in
1565 * question was fully met, partially met, unable to be met, or invalid
1566 * (if the stat type in question is disabled in the target).
1567 * A Done bit 1's indicate the end of the of stats info elements.
1568 *
1569 *
1570 * |31 16|15 12|11|10 8|7 5|4 0|
1571 * |--------------------------------------------------------------|
1572 * | reserved | msg type |
1573 * |--------------------------------------------------------------|
1574 * | cookie LSBs |
1575 * |--------------------------------------------------------------|
1576 * | cookie MSBs |
1577 * |--------------------------------------------------------------|
1578 * | stats entry length | rsvd | D| S | stat type |
1579 * |--------------------------------------------------------------|
1580 * | type-specific stats info |
1581 * | (see htt_stats.h) |
1582 * |--------------------------------------------------------------|
1583 * Header fields:
1584 * - MSG_TYPE
1585 * Bits 7:0
1586 * Purpose: Identifies this is a extended statistics upload confirmation
1587 * message.
1588 * Value: 0x1c
1589 * - COOKIE_LSBS
1590 * Bits 31:0
1591 * Purpose: Provide a mechanism to match a target->host stats confirmation
1592 * message with its preceding host->target stats request message.
1593 * Value: LSBs of the opaque cookie specified by the host-side requestor
1594 * - COOKIE_MSBS
1595 * Bits 31:0
1596 * Purpose: Provide a mechanism to match a target->host stats confirmation
1597 * message with its preceding host->target stats request message.
1598 * Value: MSBs of the opaque cookie specified by the host-side requestor
1599 *
1600 * Stats Information Element tag-length header fields:
1601 * - STAT_TYPE
1602 * Bits 7:0
1603 * Purpose: identifies the type of statistics info held in the
1604 * following information element
1605 * Value: htt_dbg_ext_stats_type
1606 * - STATUS
1607 * Bits 10:8
1608 * Purpose: indicate whether the requested stats are present
1609 * Value: htt_dbg_ext_stats_status
1610 * - DONE
1611 * Bits 11
1612 * Purpose:
1613 * Indicates the completion of the stats entry, this will be the last
1614 * stats conf HTT segment for the requested stats type.
1615 * Value:
1616 * 0 -> the stats retrieval is ongoing
1617 * 1 -> the stats retrieval is complete
1618 * - LENGTH
1619 * Bits 31:16
1620 * Purpose: indicate the stats information size
1621 * Value: This field specifies the number of bytes of stats information
1622 * that follows the element tag-length header.
1623 * It is expected but not required that this length is a multiple of
1624 * 4 bytes.
1625 */
1626
1627 #define HTT_T2H_EXT_STATS_INFO1_DONE BIT(11)
1628 #define HTT_T2H_EXT_STATS_INFO1_LENGTH GENMASK(31, 16)
1629
1630 struct ath11k_htt_extd_stats_msg {
1631 u32 info0;
1632 u64 cookie;
1633 u32 info1;
1634 u8 data[];
1635 } __packed;
1636
1637 #define HTT_MAC_ADDR_L32_0 GENMASK(7, 0)
1638 #define HTT_MAC_ADDR_L32_1 GENMASK(15, 8)
1639 #define HTT_MAC_ADDR_L32_2 GENMASK(23, 16)
1640 #define HTT_MAC_ADDR_L32_3 GENMASK(31, 24)
1641 #define HTT_MAC_ADDR_H16_0 GENMASK(7, 0)
1642 #define HTT_MAC_ADDR_H16_1 GENMASK(15, 8)
1643
1644 struct htt_mac_addr {
1645 u32 mac_addr_l32;
1646 u32 mac_addr_h16;
1647 };
1648
ath11k_dp_get_mac_addr(u32 addr_l32,u16 addr_h16,u8 * addr)1649 static inline void ath11k_dp_get_mac_addr(u32 addr_l32, u16 addr_h16, u8 *addr)
1650 {
1651 if (IS_ENABLED(CONFIG_CPU_BIG_ENDIAN)) {
1652 addr_l32 = swab32(addr_l32);
1653 addr_h16 = swab16(addr_h16);
1654 }
1655
1656 memcpy(addr, &addr_l32, 4);
1657 memcpy(addr + 4, &addr_h16, ETH_ALEN - 4);
1658 }
1659
1660 int ath11k_dp_service_srng(struct ath11k_base *ab,
1661 struct ath11k_ext_irq_grp *irq_grp,
1662 int budget);
1663 int ath11k_dp_htt_connect(struct ath11k_dp *dp);
1664 void ath11k_dp_vdev_tx_attach(struct ath11k *ar, struct ath11k_vif *arvif);
1665 void ath11k_dp_free(struct ath11k_base *ab);
1666 int ath11k_dp_alloc(struct ath11k_base *ab);
1667 int ath11k_dp_pdev_alloc(struct ath11k_base *ab);
1668 void ath11k_dp_pdev_pre_alloc(struct ath11k_base *ab);
1669 void ath11k_dp_pdev_free(struct ath11k_base *ab);
1670 int ath11k_dp_tx_htt_srng_setup(struct ath11k_base *ab, u32 ring_id,
1671 int mac_id, enum hal_ring_type ring_type);
1672 int ath11k_dp_peer_setup(struct ath11k *ar, int vdev_id, const u8 *addr);
1673 void ath11k_dp_peer_cleanup(struct ath11k *ar, int vdev_id, const u8 *addr);
1674 void ath11k_dp_srng_cleanup(struct ath11k_base *ab, struct dp_srng *ring);
1675 int ath11k_dp_srng_setup(struct ath11k_base *ab, struct dp_srng *ring,
1676 enum hal_ring_type type, int ring_num,
1677 int mac_id, int num_entries);
1678 void ath11k_dp_link_desc_cleanup(struct ath11k_base *ab,
1679 struct dp_link_desc_bank *desc_bank,
1680 u32 ring_type, struct dp_srng *ring);
1681 int ath11k_dp_link_desc_setup(struct ath11k_base *ab,
1682 struct dp_link_desc_bank *link_desc_banks,
1683 u32 ring_type, struct hal_srng *srng,
1684 u32 n_link_desc);
1685 void ath11k_dp_shadow_start_timer(struct ath11k_base *ab,
1686 struct hal_srng *srng,
1687 struct ath11k_hp_update_timer *update_timer);
1688 void ath11k_dp_shadow_stop_timer(struct ath11k_base *ab,
1689 struct ath11k_hp_update_timer *update_timer);
1690 void ath11k_dp_shadow_init_timer(struct ath11k_base *ab,
1691 struct ath11k_hp_update_timer *update_timer,
1692 u32 interval, u32 ring_id);
1693 void ath11k_dp_stop_shadow_timers(struct ath11k_base *ab);
1694
1695 #endif
1696